3633 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3634 emit_int8(0x38);
3635 emit_operand(dst, src);
3636 // 0x01 - insert into upper 128 bits
3637 emit_int8(0x01);
3638 }
3639
3640 void Assembler::vextracti128h(Address dst, XMMRegister src) {
3641 assert(VM_Version::supports_avx2(), "");
3642 InstructionMark im(this);
3643 bool vector256 = true;
3644 assert(src != xnoreg, "sanity");
3645 int src_enc = src->encoding();
3646 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3647 emit_int8(0x39);
3648 emit_operand(src, dst);
3649 // 0x01 - extract from upper 128 bits
3650 emit_int8(0x01);
3651 }
3652
3653 void Assembler::vzeroupper() {
3654 assert(VM_Version::supports_avx(), "");
3655 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
3656 emit_int8(0x77);
3657 }
3658
3659
3660 #ifndef _LP64
3661 // 32bit only pieces of the assembler
3662
3663 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3664 // NO PREFIX AS NEVER 64BIT
3665 InstructionMark im(this);
3666 emit_int8((unsigned char)0x81);
3667 emit_int8((unsigned char)(0xF8 | src1->encoding()));
3668 emit_data(imm32, rspec, 0);
3669 }
3670
3671 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3672 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
|
3633 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3634 emit_int8(0x38);
3635 emit_operand(dst, src);
3636 // 0x01 - insert into upper 128 bits
3637 emit_int8(0x01);
3638 }
3639
3640 void Assembler::vextracti128h(Address dst, XMMRegister src) {
3641 assert(VM_Version::supports_avx2(), "");
3642 InstructionMark im(this);
3643 bool vector256 = true;
3644 assert(src != xnoreg, "sanity");
3645 int src_enc = src->encoding();
3646 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3647 emit_int8(0x39);
3648 emit_operand(src, dst);
3649 // 0x01 - extract from upper 128 bits
3650 emit_int8(0x01);
3651 }
3652
3653 // duplicate 4-bytes integer data from src into 8 locations in dest
3654 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
3655 assert(VM_Version::supports_avx2(), "");
3656 bool vector256 = true;
3657 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3658 emit_int8(0x58);
3659 emit_int8((unsigned char)(0xC0 | encode));
3660 }
3661
3662 void Assembler::vzeroupper() {
3663 assert(VM_Version::supports_avx(), "");
3664 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
3665 emit_int8(0x77);
3666 }
3667
3668
3669 #ifndef _LP64
3670 // 32bit only pieces of the assembler
3671
3672 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3673 // NO PREFIX AS NEVER 64BIT
3674 InstructionMark im(this);
3675 emit_int8((unsigned char)0x81);
3676 emit_int8((unsigned char)(0xF8 | src1->encoding()));
3677 emit_data(imm32, rspec, 0);
3678 }
3679
3680 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3681 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
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