src/cpu/x86/vm/assembler_x86.cpp
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src/cpu/x86/vm/assembler_x86.cpp

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rev 5968 : 8031320: Use Intel RTM instructions for locks
Summary: Use RTM for inflated locks and stack locks.
Reviewed-by: iveresov, twisti, roland, dcubed


2326 }
2327 
2328 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2329   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2330   emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2331 }
2332 
2333 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2334   assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
2335   emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector256);
2336 }
2337 
2338 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256) {
2339   assert(VM_Version::supports_avx2(), "");
2340   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector256);
2341   emit_int8(0x00);
2342   emit_int8(0xC0 | encode);
2343   emit_int8(imm8);
2344 }
2345 





2346 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2347   assert(VM_Version::supports_sse4_2(), "");
2348   InstructionMark im(this);
2349   simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2350   emit_int8(0x61);
2351   emit_operand(dst, src);
2352   emit_int8(imm8);
2353 }
2354 
2355 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2356   assert(VM_Version::supports_sse4_2(), "");
2357   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2358   emit_int8(0x61);
2359   emit_int8((unsigned char)(0xC0 | encode));
2360   emit_int8(imm8);
2361 }
2362 
2363 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
2364   assert(VM_Version::supports_sse4_1(), "");
2365   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, false);


2650   InstructionMark im(this);
2651   prefix(src);
2652   emit_int8((unsigned char)0xFF);
2653   emit_operand(rsi, src);
2654 }
2655 #endif
2656 
2657 void Assembler::rcll(Register dst, int imm8) {
2658   assert(isShiftCount(imm8), "illegal shift count");
2659   int encode = prefix_and_encode(dst->encoding());
2660   if (imm8 == 1) {
2661     emit_int8((unsigned char)0xD1);
2662     emit_int8((unsigned char)(0xD0 | encode));
2663   } else {
2664     emit_int8((unsigned char)0xC1);
2665     emit_int8((unsigned char)0xD0 | encode);
2666     emit_int8(imm8);
2667   }
2668 }
2669 





2670 // copies data from [esi] to [edi] using rcx pointer sized words
2671 // generic
2672 void Assembler::rep_mov() {
2673   emit_int8((unsigned char)0xF3);
2674   // MOVSQ
2675   LP64_ONLY(prefix(REX_W));
2676   emit_int8((unsigned char)0xA5);
2677 }
2678 
2679 // sets rcx bytes with rax, value at [edi]
2680 void Assembler::rep_stosb() {
2681   emit_int8((unsigned char)0xF3); // REP
2682   LP64_ONLY(prefix(REX_W));
2683   emit_int8((unsigned char)0xAA); // STOSB
2684 }
2685 
2686 // sets rcx pointer sized words with rax, value at [edi]
2687 // generic
2688 void Assembler::rep_stos() {
2689   emit_int8((unsigned char)0xF3); // REP


2959 void Assembler::ucomisd(XMMRegister dst, Address src) {
2960   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2961   emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2962 }
2963 
2964 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2965   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2966   emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2967 }
2968 
2969 void Assembler::ucomiss(XMMRegister dst, Address src) {
2970   NOT_LP64(assert(VM_Version::supports_sse(), ""));
2971   emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2972 }
2973 
2974 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2975   NOT_LP64(assert(VM_Version::supports_sse(), ""));
2976   emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2977 }
2978 





2979 
2980 void Assembler::xaddl(Address dst, Register src) {
2981   InstructionMark im(this);
2982   prefix(dst, src);
2983   emit_int8(0x0F);
2984   emit_int8((unsigned char)0xC1);
2985   emit_operand(src, dst);
2986 }
2987 


















2988 void Assembler::xchgl(Register dst, Address src) { // xchg
2989   InstructionMark im(this);
2990   prefix(src, dst);
2991   emit_int8((unsigned char)0x87);
2992   emit_operand(dst, src);
2993 }
2994 
2995 void Assembler::xchgl(Register dst, Register src) {
2996   int encode = prefix_and_encode(dst->encoding(), src->encoding());
2997   emit_int8((unsigned char)0x87);
2998   emit_int8((unsigned char)(0xC0 | encode));
2999 }
3000 






3001 void Assembler::xgetbv() {
3002   emit_int8(0x0F);
3003   emit_int8(0x01);
3004   emit_int8((unsigned char)0xD0);
3005 }
3006 
3007 void Assembler::xorl(Register dst, int32_t imm32) {
3008   prefix(dst);
3009   emit_arith(0x81, 0xF0, dst, imm32);
3010 }
3011 
3012 void Assembler::xorl(Register dst, Address src) {
3013   InstructionMark im(this);
3014   prefix(src, dst);
3015   emit_int8(0x33);
3016   emit_operand(dst, src);
3017 }
3018 
3019 void Assembler::xorl(Register dst, Register src) {
3020   (void) prefix_and_encode(dst->encoding(), src->encoding());




2326 }
2327 
2328 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2329   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2330   emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2331 }
2332 
2333 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2334   assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
2335   emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector256);
2336 }
2337 
2338 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256) {
2339   assert(VM_Version::supports_avx2(), "");
2340   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector256);
2341   emit_int8(0x00);
2342   emit_int8(0xC0 | encode);
2343   emit_int8(imm8);
2344 }
2345 
2346 void Assembler::pause() {
2347   emit_int8((unsigned char)0xF3);
2348   emit_int8((unsigned char)0x90);
2349 }
2350 
2351 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2352   assert(VM_Version::supports_sse4_2(), "");
2353   InstructionMark im(this);
2354   simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2355   emit_int8(0x61);
2356   emit_operand(dst, src);
2357   emit_int8(imm8);
2358 }
2359 
2360 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2361   assert(VM_Version::supports_sse4_2(), "");
2362   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2363   emit_int8(0x61);
2364   emit_int8((unsigned char)(0xC0 | encode));
2365   emit_int8(imm8);
2366 }
2367 
2368 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
2369   assert(VM_Version::supports_sse4_1(), "");
2370   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, false);


2655   InstructionMark im(this);
2656   prefix(src);
2657   emit_int8((unsigned char)0xFF);
2658   emit_operand(rsi, src);
2659 }
2660 #endif
2661 
2662 void Assembler::rcll(Register dst, int imm8) {
2663   assert(isShiftCount(imm8), "illegal shift count");
2664   int encode = prefix_and_encode(dst->encoding());
2665   if (imm8 == 1) {
2666     emit_int8((unsigned char)0xD1);
2667     emit_int8((unsigned char)(0xD0 | encode));
2668   } else {
2669     emit_int8((unsigned char)0xC1);
2670     emit_int8((unsigned char)0xD0 | encode);
2671     emit_int8(imm8);
2672   }
2673 }
2674 
2675 void Assembler::rdtsc() {
2676   emit_int8((unsigned char)0x0F);
2677   emit_int8((unsigned char)0x31);
2678 }
2679 
2680 // copies data from [esi] to [edi] using rcx pointer sized words
2681 // generic
2682 void Assembler::rep_mov() {
2683   emit_int8((unsigned char)0xF3);
2684   // MOVSQ
2685   LP64_ONLY(prefix(REX_W));
2686   emit_int8((unsigned char)0xA5);
2687 }
2688 
2689 // sets rcx bytes with rax, value at [edi]
2690 void Assembler::rep_stosb() {
2691   emit_int8((unsigned char)0xF3); // REP
2692   LP64_ONLY(prefix(REX_W));
2693   emit_int8((unsigned char)0xAA); // STOSB
2694 }
2695 
2696 // sets rcx pointer sized words with rax, value at [edi]
2697 // generic
2698 void Assembler::rep_stos() {
2699   emit_int8((unsigned char)0xF3); // REP


2969 void Assembler::ucomisd(XMMRegister dst, Address src) {
2970   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2971   emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2972 }
2973 
2974 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2975   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2976   emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2977 }
2978 
2979 void Assembler::ucomiss(XMMRegister dst, Address src) {
2980   NOT_LP64(assert(VM_Version::supports_sse(), ""));
2981   emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2982 }
2983 
2984 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2985   NOT_LP64(assert(VM_Version::supports_sse(), ""));
2986   emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2987 }
2988 
2989 void Assembler::xabort(int8_t imm8) {
2990   emit_int8((unsigned char)0xC6);
2991   emit_int8((unsigned char)0xF8);
2992   emit_int8((unsigned char)(imm8 & 0xFF));
2993 }
2994 
2995 void Assembler::xaddl(Address dst, Register src) {
2996   InstructionMark im(this);
2997   prefix(dst, src);
2998   emit_int8(0x0F);
2999   emit_int8((unsigned char)0xC1);
3000   emit_operand(src, dst);
3001 }
3002 
3003 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
3004   InstructionMark im(this);
3005   relocate(rtype);
3006   if (abort.is_bound()) {
3007     address entry = target(abort);
3008     assert(entry != NULL, "abort entry NULL");
3009     intptr_t offset = entry - pc();
3010     emit_int8((unsigned char)0xC7);
3011     emit_int8((unsigned char)0xF8);
3012     emit_int32(offset - 6); // 2 opcode + 4 address
3013   } else {
3014     abort.add_patch_at(code(), locator());
3015     emit_int8((unsigned char)0xC7);
3016     emit_int8((unsigned char)0xF8);
3017     emit_int32(0);
3018   }
3019 }
3020 
3021 void Assembler::xchgl(Register dst, Address src) { // xchg
3022   InstructionMark im(this);
3023   prefix(src, dst);
3024   emit_int8((unsigned char)0x87);
3025   emit_operand(dst, src);
3026 }
3027 
3028 void Assembler::xchgl(Register dst, Register src) {
3029   int encode = prefix_and_encode(dst->encoding(), src->encoding());
3030   emit_int8((unsigned char)0x87);
3031   emit_int8((unsigned char)(0xC0 | encode));
3032 }
3033 
3034 void Assembler::xend() {
3035   emit_int8((unsigned char)0x0F);
3036   emit_int8((unsigned char)0x01);
3037   emit_int8((unsigned char)0xD5);
3038 }
3039 
3040 void Assembler::xgetbv() {
3041   emit_int8(0x0F);
3042   emit_int8(0x01);
3043   emit_int8((unsigned char)0xD0);
3044 }
3045 
3046 void Assembler::xorl(Register dst, int32_t imm32) {
3047   prefix(dst);
3048   emit_arith(0x81, 0xF0, dst, imm32);
3049 }
3050 
3051 void Assembler::xorl(Register dst, Address src) {
3052   InstructionMark im(this);
3053   prefix(src, dst);
3054   emit_int8(0x33);
3055   emit_operand(dst, src);
3056 }
3057 
3058 void Assembler::xorl(Register dst, Register src) {
3059   (void) prefix_and_encode(dst->encoding(), src->encoding());


src/cpu/x86/vm/assembler_x86.cpp
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