1 /*
   2  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/assembler.hpp"
  27 #include "asm/assembler.inline.hpp"
  28 #include "compiler/disassembler.hpp"
  29 #include "gc_interface/collectedHeap.inline.hpp"
  30 #include "interpreter/interpreter.hpp"
  31 #include "memory/cardTableModRefBS.hpp"
  32 #include "memory/resourceArea.hpp"
  33 #include "memory/universe.hpp"
  34 #include "prims/methodHandles.hpp"
  35 #include "runtime/biasedLocking.hpp"
  36 #include "runtime/interfaceSupport.hpp"
  37 #include "runtime/objectMonitor.hpp"
  38 #include "runtime/os.hpp"
  39 #include "runtime/sharedRuntime.hpp"
  40 #include "runtime/stubRoutines.hpp"
  41 #include "utilities/macros.hpp"
  42 #if INCLUDE_ALL_GCS
  43 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
  44 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
  45 #include "gc_implementation/g1/heapRegion.hpp"
  46 #endif // INCLUDE_ALL_GCS
  47 
  48 #ifdef PRODUCT
  49 #define BLOCK_COMMENT(str) /* nothing */
  50 #define STOP(error) stop(error)
  51 #else
  52 #define BLOCK_COMMENT(str) block_comment(str)
  53 #define STOP(error) block_comment(error); stop(error)
  54 #endif
  55 
  56 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  57 
  58 
  59 #ifdef ASSERT
  60 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
  61 #endif
  62 
  63 static Assembler::Condition reverse[] = {
  64     Assembler::noOverflow     /* overflow      = 0x0 */ ,
  65     Assembler::overflow       /* noOverflow    = 0x1 */ ,
  66     Assembler::aboveEqual     /* carrySet      = 0x2, below         = 0x2 */ ,
  67     Assembler::below          /* aboveEqual    = 0x3, carryClear    = 0x3 */ ,
  68     Assembler::notZero        /* zero          = 0x4, equal         = 0x4 */ ,
  69     Assembler::zero           /* notZero       = 0x5, notEqual      = 0x5 */ ,
  70     Assembler::above          /* belowEqual    = 0x6 */ ,
  71     Assembler::belowEqual     /* above         = 0x7 */ ,
  72     Assembler::positive       /* negative      = 0x8 */ ,
  73     Assembler::negative       /* positive      = 0x9 */ ,
  74     Assembler::noParity       /* parity        = 0xa */ ,
  75     Assembler::parity         /* noParity      = 0xb */ ,
  76     Assembler::greaterEqual   /* less          = 0xc */ ,
  77     Assembler::less           /* greaterEqual  = 0xd */ ,
  78     Assembler::greater        /* lessEqual     = 0xe */ ,
  79     Assembler::lessEqual      /* greater       = 0xf, */
  80 
  81 };
  82 
  83 
  84 // Implementation of MacroAssembler
  85 
  86 // First all the versions that have distinct versions depending on 32/64 bit
  87 // Unless the difference is trivial (1 line or so).
  88 
  89 #ifndef _LP64
  90 
  91 // 32bit versions
  92 
  93 Address MacroAssembler::as_Address(AddressLiteral adr) {
  94   return Address(adr.target(), adr.rspec());
  95 }
  96 
  97 Address MacroAssembler::as_Address(ArrayAddress adr) {
  98   return Address::make_array(adr);
  99 }
 100 
 101 void MacroAssembler::call_VM_leaf_base(address entry_point,
 102                                        int number_of_arguments) {
 103   call(RuntimeAddress(entry_point));
 104   increment(rsp, number_of_arguments * wordSize);
 105 }
 106 
 107 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
 108   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 109 }
 110 
 111 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
 112   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 113 }
 114 
 115 void MacroAssembler::cmpoop(Address src1, jobject obj) {
 116   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 117 }
 118 
 119 void MacroAssembler::cmpoop(Register src1, jobject obj) {
 120   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 121 }
 122 
 123 void MacroAssembler::extend_sign(Register hi, Register lo) {
 124   // According to Intel Doc. AP-526, "Integer Divide", p.18.
 125   if (VM_Version::is_P6() && hi == rdx && lo == rax) {
 126     cdql();
 127   } else {
 128     movl(hi, lo);
 129     sarl(hi, 31);
 130   }
 131 }
 132 
 133 void MacroAssembler::jC2(Register tmp, Label& L) {
 134   // set parity bit if FPU flag C2 is set (via rax)
 135   save_rax(tmp);
 136   fwait(); fnstsw_ax();
 137   sahf();
 138   restore_rax(tmp);
 139   // branch
 140   jcc(Assembler::parity, L);
 141 }
 142 
 143 void MacroAssembler::jnC2(Register tmp, Label& L) {
 144   // set parity bit if FPU flag C2 is set (via rax)
 145   save_rax(tmp);
 146   fwait(); fnstsw_ax();
 147   sahf();
 148   restore_rax(tmp);
 149   // branch
 150   jcc(Assembler::noParity, L);
 151 }
 152 
 153 // 32bit can do a case table jump in one instruction but we no longer allow the base
 154 // to be installed in the Address class
 155 void MacroAssembler::jump(ArrayAddress entry) {
 156   jmp(as_Address(entry));
 157 }
 158 
 159 // Note: y_lo will be destroyed
 160 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 161   // Long compare for Java (semantics as described in JVM spec.)
 162   Label high, low, done;
 163 
 164   cmpl(x_hi, y_hi);
 165   jcc(Assembler::less, low);
 166   jcc(Assembler::greater, high);
 167   // x_hi is the return register
 168   xorl(x_hi, x_hi);
 169   cmpl(x_lo, y_lo);
 170   jcc(Assembler::below, low);
 171   jcc(Assembler::equal, done);
 172 
 173   bind(high);
 174   xorl(x_hi, x_hi);
 175   increment(x_hi);
 176   jmp(done);
 177 
 178   bind(low);
 179   xorl(x_hi, x_hi);
 180   decrementl(x_hi);
 181 
 182   bind(done);
 183 }
 184 
 185 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 186     mov_literal32(dst, (int32_t)src.target(), src.rspec());
 187 }
 188 
 189 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 190   // leal(dst, as_Address(adr));
 191   // see note in movl as to why we must use a move
 192   mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
 193 }
 194 
 195 void MacroAssembler::leave() {
 196   mov(rsp, rbp);
 197   pop(rbp);
 198 }
 199 
 200 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
 201   // Multiplication of two Java long values stored on the stack
 202   // as illustrated below. Result is in rdx:rax.
 203   //
 204   // rsp ---> [  ??  ] \               \
 205   //            ....    | y_rsp_offset  |
 206   //          [ y_lo ] /  (in bytes)    | x_rsp_offset
 207   //          [ y_hi ]                  | (in bytes)
 208   //            ....                    |
 209   //          [ x_lo ]                 /
 210   //          [ x_hi ]
 211   //            ....
 212   //
 213   // Basic idea: lo(result) = lo(x_lo * y_lo)
 214   //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
 215   Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
 216   Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
 217   Label quick;
 218   // load x_hi, y_hi and check if quick
 219   // multiplication is possible
 220   movl(rbx, x_hi);
 221   movl(rcx, y_hi);
 222   movl(rax, rbx);
 223   orl(rbx, rcx);                                 // rbx, = 0 <=> x_hi = 0 and y_hi = 0
 224   jcc(Assembler::zero, quick);                   // if rbx, = 0 do quick multiply
 225   // do full multiplication
 226   // 1st step
 227   mull(y_lo);                                    // x_hi * y_lo
 228   movl(rbx, rax);                                // save lo(x_hi * y_lo) in rbx,
 229   // 2nd step
 230   movl(rax, x_lo);
 231   mull(rcx);                                     // x_lo * y_hi
 232   addl(rbx, rax);                                // add lo(x_lo * y_hi) to rbx,
 233   // 3rd step
 234   bind(quick);                                   // note: rbx, = 0 if quick multiply!
 235   movl(rax, x_lo);
 236   mull(y_lo);                                    // x_lo * y_lo
 237   addl(rdx, rbx);                                // correct hi(x_lo * y_lo)
 238 }
 239 
 240 void MacroAssembler::lneg(Register hi, Register lo) {
 241   negl(lo);
 242   adcl(hi, 0);
 243   negl(hi);
 244 }
 245 
 246 void MacroAssembler::lshl(Register hi, Register lo) {
 247   // Java shift left long support (semantics as described in JVM spec., p.305)
 248   // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
 249   // shift value is in rcx !
 250   assert(hi != rcx, "must not use rcx");
 251   assert(lo != rcx, "must not use rcx");
 252   const Register s = rcx;                        // shift count
 253   const int      n = BitsPerWord;
 254   Label L;
 255   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 256   cmpl(s, n);                                    // if (s < n)
 257   jcc(Assembler::less, L);                       // else (s >= n)
 258   movl(hi, lo);                                  // x := x << n
 259   xorl(lo, lo);
 260   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 261   bind(L);                                       // s (mod n) < n
 262   shldl(hi, lo);                                 // x := x << s
 263   shll(lo);
 264 }
 265 
 266 
 267 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
 268   // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
 269   // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
 270   assert(hi != rcx, "must not use rcx");
 271   assert(lo != rcx, "must not use rcx");
 272   const Register s = rcx;                        // shift count
 273   const int      n = BitsPerWord;
 274   Label L;
 275   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 276   cmpl(s, n);                                    // if (s < n)
 277   jcc(Assembler::less, L);                       // else (s >= n)
 278   movl(lo, hi);                                  // x := x >> n
 279   if (sign_extension) sarl(hi, 31);
 280   else                xorl(hi, hi);
 281   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 282   bind(L);                                       // s (mod n) < n
 283   shrdl(lo, hi);                                 // x := x >> s
 284   if (sign_extension) sarl(hi);
 285   else                shrl(hi);
 286 }
 287 
 288 void MacroAssembler::movoop(Register dst, jobject obj) {
 289   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 290 }
 291 
 292 void MacroAssembler::movoop(Address dst, jobject obj) {
 293   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 294 }
 295 
 296 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 297   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 298 }
 299 
 300 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 301   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 302 }
 303 
 304 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 305   // scratch register is not used,
 306   // it is defined to match parameters of 64-bit version of this method.
 307   if (src.is_lval()) {
 308     mov_literal32(dst, (intptr_t)src.target(), src.rspec());
 309   } else {
 310     movl(dst, as_Address(src));
 311   }
 312 }
 313 
 314 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 315   movl(as_Address(dst), src);
 316 }
 317 
 318 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 319   movl(dst, as_Address(src));
 320 }
 321 
 322 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 323 void MacroAssembler::movptr(Address dst, intptr_t src) {
 324   movl(dst, src);
 325 }
 326 
 327 
 328 void MacroAssembler::pop_callee_saved_registers() {
 329   pop(rcx);
 330   pop(rdx);
 331   pop(rdi);
 332   pop(rsi);
 333 }
 334 
 335 void MacroAssembler::pop_fTOS() {
 336   fld_d(Address(rsp, 0));
 337   addl(rsp, 2 * wordSize);
 338 }
 339 
 340 void MacroAssembler::push_callee_saved_registers() {
 341   push(rsi);
 342   push(rdi);
 343   push(rdx);
 344   push(rcx);
 345 }
 346 
 347 void MacroAssembler::push_fTOS() {
 348   subl(rsp, 2 * wordSize);
 349   fstp_d(Address(rsp, 0));
 350 }
 351 
 352 
 353 void MacroAssembler::pushoop(jobject obj) {
 354   push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
 355 }
 356 
 357 void MacroAssembler::pushklass(Metadata* obj) {
 358   push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
 359 }
 360 
 361 void MacroAssembler::pushptr(AddressLiteral src) {
 362   if (src.is_lval()) {
 363     push_literal32((int32_t)src.target(), src.rspec());
 364   } else {
 365     pushl(as_Address(src));
 366   }
 367 }
 368 
 369 void MacroAssembler::set_word_if_not_zero(Register dst) {
 370   xorl(dst, dst);
 371   set_byte_if_not_zero(dst);
 372 }
 373 
 374 static void pass_arg0(MacroAssembler* masm, Register arg) {
 375   masm->push(arg);
 376 }
 377 
 378 static void pass_arg1(MacroAssembler* masm, Register arg) {
 379   masm->push(arg);
 380 }
 381 
 382 static void pass_arg2(MacroAssembler* masm, Register arg) {
 383   masm->push(arg);
 384 }
 385 
 386 static void pass_arg3(MacroAssembler* masm, Register arg) {
 387   masm->push(arg);
 388 }
 389 
 390 #ifndef PRODUCT
 391 extern "C" void findpc(intptr_t x);
 392 #endif
 393 
 394 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
 395   // In order to get locks to work, we need to fake a in_VM state
 396   JavaThread* thread = JavaThread::current();
 397   JavaThreadState saved_state = thread->thread_state();
 398   thread->set_thread_state(_thread_in_vm);
 399   if (ShowMessageBoxOnError) {
 400     JavaThread* thread = JavaThread::current();
 401     JavaThreadState saved_state = thread->thread_state();
 402     thread->set_thread_state(_thread_in_vm);
 403     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 404       ttyLocker ttyl;
 405       BytecodeCounter::print();
 406     }
 407     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 408     // This is the value of eip which points to where verify_oop will return.
 409     if (os::message_box(msg, "Execution stopped, print registers?")) {
 410       print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
 411       BREAKPOINT;
 412     }
 413   } else {
 414     ttyLocker ttyl;
 415     ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
 416   }
 417   // Don't assert holding the ttyLock
 418     assert(false, err_msg("DEBUG MESSAGE: %s", msg));
 419   ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
 420 }
 421 
 422 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
 423   ttyLocker ttyl;
 424   FlagSetting fs(Debugging, true);
 425   tty->print_cr("eip = 0x%08x", eip);
 426 #ifndef PRODUCT
 427   if ((WizardMode || Verbose) && PrintMiscellaneous) {
 428     tty->cr();
 429     findpc(eip);
 430     tty->cr();
 431   }
 432 #endif
 433 #define PRINT_REG(rax) \
 434   { tty->print("%s = ", #rax); os::print_location(tty, rax); }
 435   PRINT_REG(rax);
 436   PRINT_REG(rbx);
 437   PRINT_REG(rcx);
 438   PRINT_REG(rdx);
 439   PRINT_REG(rdi);
 440   PRINT_REG(rsi);
 441   PRINT_REG(rbp);
 442   PRINT_REG(rsp);
 443 #undef PRINT_REG
 444   // Print some words near top of staack.
 445   int* dump_sp = (int*) rsp;
 446   for (int col1 = 0; col1 < 8; col1++) {
 447     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 448     os::print_location(tty, *dump_sp++);
 449   }
 450   for (int row = 0; row < 16; row++) {
 451     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 452     for (int col = 0; col < 8; col++) {
 453       tty->print(" 0x%08x", *dump_sp++);
 454     }
 455     tty->cr();
 456   }
 457   // Print some instructions around pc:
 458   Disassembler::decode((address)eip-64, (address)eip);
 459   tty->print_cr("--------");
 460   Disassembler::decode((address)eip, (address)eip+32);
 461 }
 462 
 463 void MacroAssembler::stop(const char* msg) {
 464   ExternalAddress message((address)msg);
 465   // push address of message
 466   pushptr(message.addr());
 467   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 468   pusha();                                            // push registers
 469   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
 470   hlt();
 471 }
 472 
 473 void MacroAssembler::warn(const char* msg) {
 474   push_CPU_state();
 475 
 476   ExternalAddress message((address) msg);
 477   // push address of message
 478   pushptr(message.addr());
 479 
 480   call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
 481   addl(rsp, wordSize);       // discard argument
 482   pop_CPU_state();
 483 }
 484 
 485 void MacroAssembler::print_state() {
 486   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 487   pusha();                                            // push registers
 488 
 489   push_CPU_state();
 490   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
 491   pop_CPU_state();
 492 
 493   popa();
 494   addl(rsp, wordSize);
 495 }
 496 
 497 #else // _LP64
 498 
 499 // 64 bit versions
 500 
 501 Address MacroAssembler::as_Address(AddressLiteral adr) {
 502   // amd64 always does this as a pc-rel
 503   // we can be absolute or disp based on the instruction type
 504   // jmp/call are displacements others are absolute
 505   assert(!adr.is_lval(), "must be rval");
 506   assert(reachable(adr), "must be");
 507   return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
 508 
 509 }
 510 
 511 Address MacroAssembler::as_Address(ArrayAddress adr) {
 512   AddressLiteral base = adr.base();
 513   lea(rscratch1, base);
 514   Address index = adr.index();
 515   assert(index._disp == 0, "must not have disp"); // maybe it can?
 516   Address array(rscratch1, index._index, index._scale, index._disp);
 517   return array;
 518 }
 519 
 520 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
 521   Label L, E;
 522 
 523 #ifdef _WIN64
 524   // Windows always allocates space for it's register args
 525   assert(num_args <= 4, "only register arguments supported");
 526   subq(rsp,  frame::arg_reg_save_area_bytes);
 527 #endif
 528 
 529   // Align stack if necessary
 530   testl(rsp, 15);
 531   jcc(Assembler::zero, L);
 532 
 533   subq(rsp, 8);
 534   {
 535     call(RuntimeAddress(entry_point));
 536   }
 537   addq(rsp, 8);
 538   jmp(E);
 539 
 540   bind(L);
 541   {
 542     call(RuntimeAddress(entry_point));
 543   }
 544 
 545   bind(E);
 546 
 547 #ifdef _WIN64
 548   // restore stack pointer
 549   addq(rsp, frame::arg_reg_save_area_bytes);
 550 #endif
 551 
 552 }
 553 
 554 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
 555   assert(!src2.is_lval(), "should use cmpptr");
 556 
 557   if (reachable(src2)) {
 558     cmpq(src1, as_Address(src2));
 559   } else {
 560     lea(rscratch1, src2);
 561     Assembler::cmpq(src1, Address(rscratch1, 0));
 562   }
 563 }
 564 
 565 int MacroAssembler::corrected_idivq(Register reg) {
 566   // Full implementation of Java ldiv and lrem; checks for special
 567   // case as described in JVM spec., p.243 & p.271.  The function
 568   // returns the (pc) offset of the idivl instruction - may be needed
 569   // for implicit exceptions.
 570   //
 571   //         normal case                           special case
 572   //
 573   // input : rax: dividend                         min_long
 574   //         reg: divisor   (may not be eax/edx)   -1
 575   //
 576   // output: rax: quotient  (= rax idiv reg)       min_long
 577   //         rdx: remainder (= rax irem reg)       0
 578   assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
 579   static const int64_t min_long = 0x8000000000000000;
 580   Label normal_case, special_case;
 581 
 582   // check for special case
 583   cmp64(rax, ExternalAddress((address) &min_long));
 584   jcc(Assembler::notEqual, normal_case);
 585   xorl(rdx, rdx); // prepare rdx for possible special case (where
 586                   // remainder = 0)
 587   cmpq(reg, -1);
 588   jcc(Assembler::equal, special_case);
 589 
 590   // handle normal case
 591   bind(normal_case);
 592   cdqq();
 593   int idivq_offset = offset();
 594   idivq(reg);
 595 
 596   // normal and special case exit
 597   bind(special_case);
 598 
 599   return idivq_offset;
 600 }
 601 
 602 void MacroAssembler::decrementq(Register reg, int value) {
 603   if (value == min_jint) { subq(reg, value); return; }
 604   if (value <  0) { incrementq(reg, -value); return; }
 605   if (value == 0) {                        ; return; }
 606   if (value == 1 && UseIncDec) { decq(reg) ; return; }
 607   /* else */      { subq(reg, value)       ; return; }
 608 }
 609 
 610 void MacroAssembler::decrementq(Address dst, int value) {
 611   if (value == min_jint) { subq(dst, value); return; }
 612   if (value <  0) { incrementq(dst, -value); return; }
 613   if (value == 0) {                        ; return; }
 614   if (value == 1 && UseIncDec) { decq(dst) ; return; }
 615   /* else */      { subq(dst, value)       ; return; }
 616 }
 617 
 618 void MacroAssembler::incrementq(AddressLiteral dst) {
 619   if (reachable(dst)) {
 620     incrementq(as_Address(dst));
 621   } else {
 622     lea(rscratch1, dst);
 623     incrementq(Address(rscratch1, 0));
 624   }
 625 }
 626 
 627 void MacroAssembler::incrementq(Register reg, int value) {
 628   if (value == min_jint) { addq(reg, value); return; }
 629   if (value <  0) { decrementq(reg, -value); return; }
 630   if (value == 0) {                        ; return; }
 631   if (value == 1 && UseIncDec) { incq(reg) ; return; }
 632   /* else */      { addq(reg, value)       ; return; }
 633 }
 634 
 635 void MacroAssembler::incrementq(Address dst, int value) {
 636   if (value == min_jint) { addq(dst, value); return; }
 637   if (value <  0) { decrementq(dst, -value); return; }
 638   if (value == 0) {                        ; return; }
 639   if (value == 1 && UseIncDec) { incq(dst) ; return; }
 640   /* else */      { addq(dst, value)       ; return; }
 641 }
 642 
 643 // 32bit can do a case table jump in one instruction but we no longer allow the base
 644 // to be installed in the Address class
 645 void MacroAssembler::jump(ArrayAddress entry) {
 646   lea(rscratch1, entry.base());
 647   Address dispatch = entry.index();
 648   assert(dispatch._base == noreg, "must be");
 649   dispatch._base = rscratch1;
 650   jmp(dispatch);
 651 }
 652 
 653 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 654   ShouldNotReachHere(); // 64bit doesn't use two regs
 655   cmpq(x_lo, y_lo);
 656 }
 657 
 658 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 659     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 660 }
 661 
 662 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 663   mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
 664   movptr(dst, rscratch1);
 665 }
 666 
 667 void MacroAssembler::leave() {
 668   // %%% is this really better? Why not on 32bit too?
 669   emit_int8((unsigned char)0xC9); // LEAVE
 670 }
 671 
 672 void MacroAssembler::lneg(Register hi, Register lo) {
 673   ShouldNotReachHere(); // 64bit doesn't use two regs
 674   negq(lo);
 675 }
 676 
 677 void MacroAssembler::movoop(Register dst, jobject obj) {
 678   mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 679 }
 680 
 681 void MacroAssembler::movoop(Address dst, jobject obj) {
 682   mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 683   movq(dst, rscratch1);
 684 }
 685 
 686 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 687   mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 688 }
 689 
 690 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 691   mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 692   movq(dst, rscratch1);
 693 }
 694 
 695 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 696   if (src.is_lval()) {
 697     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 698   } else {
 699     if (reachable(src)) {
 700       movq(dst, as_Address(src));
 701     } else {
 702       lea(scratch, src);
 703       movq(dst, Address(scratch, 0));
 704     }
 705   }
 706 }
 707 
 708 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 709   movq(as_Address(dst), src);
 710 }
 711 
 712 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 713   movq(dst, as_Address(src));
 714 }
 715 
 716 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 717 void MacroAssembler::movptr(Address dst, intptr_t src) {
 718   mov64(rscratch1, src);
 719   movq(dst, rscratch1);
 720 }
 721 
 722 // These are mostly for initializing NULL
 723 void MacroAssembler::movptr(Address dst, int32_t src) {
 724   movslq(dst, src);
 725 }
 726 
 727 void MacroAssembler::movptr(Register dst, int32_t src) {
 728   mov64(dst, (intptr_t)src);
 729 }
 730 
 731 void MacroAssembler::pushoop(jobject obj) {
 732   movoop(rscratch1, obj);
 733   push(rscratch1);
 734 }
 735 
 736 void MacroAssembler::pushklass(Metadata* obj) {
 737   mov_metadata(rscratch1, obj);
 738   push(rscratch1);
 739 }
 740 
 741 void MacroAssembler::pushptr(AddressLiteral src) {
 742   lea(rscratch1, src);
 743   if (src.is_lval()) {
 744     push(rscratch1);
 745   } else {
 746     pushq(Address(rscratch1, 0));
 747   }
 748 }
 749 
 750 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
 751                                            bool clear_pc) {
 752   // we must set sp to zero to clear frame
 753   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
 754   // must clear fp, so that compiled frames are not confused; it is
 755   // possible that we need it only for debugging
 756   if (clear_fp) {
 757     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
 758   }
 759 
 760   if (clear_pc) {
 761     movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
 762   }
 763 }
 764 
 765 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
 766                                          Register last_java_fp,
 767                                          address  last_java_pc) {
 768   // determine last_java_sp register
 769   if (!last_java_sp->is_valid()) {
 770     last_java_sp = rsp;
 771   }
 772 
 773   // last_java_fp is optional
 774   if (last_java_fp->is_valid()) {
 775     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
 776            last_java_fp);
 777   }
 778 
 779   // last_java_pc is optional
 780   if (last_java_pc != NULL) {
 781     Address java_pc(r15_thread,
 782                     JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
 783     lea(rscratch1, InternalAddress(last_java_pc));
 784     movptr(java_pc, rscratch1);
 785   }
 786 
 787   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
 788 }
 789 
 790 static void pass_arg0(MacroAssembler* masm, Register arg) {
 791   if (c_rarg0 != arg ) {
 792     masm->mov(c_rarg0, arg);
 793   }
 794 }
 795 
 796 static void pass_arg1(MacroAssembler* masm, Register arg) {
 797   if (c_rarg1 != arg ) {
 798     masm->mov(c_rarg1, arg);
 799   }
 800 }
 801 
 802 static void pass_arg2(MacroAssembler* masm, Register arg) {
 803   if (c_rarg2 != arg ) {
 804     masm->mov(c_rarg2, arg);
 805   }
 806 }
 807 
 808 static void pass_arg3(MacroAssembler* masm, Register arg) {
 809   if (c_rarg3 != arg ) {
 810     masm->mov(c_rarg3, arg);
 811   }
 812 }
 813 
 814 void MacroAssembler::stop(const char* msg) {
 815   address rip = pc();
 816   pusha(); // get regs on stack
 817   lea(c_rarg0, ExternalAddress((address) msg));
 818   lea(c_rarg1, InternalAddress(rip));
 819   movq(c_rarg2, rsp); // pass pointer to regs array
 820   andq(rsp, -16); // align stack as required by ABI
 821   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
 822   hlt();
 823 }
 824 
 825 void MacroAssembler::warn(const char* msg) {
 826   push(rbp);
 827   movq(rbp, rsp);
 828   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 829   push_CPU_state();   // keeps alignment at 16 bytes
 830   lea(c_rarg0, ExternalAddress((address) msg));
 831   call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
 832   pop_CPU_state();
 833   mov(rsp, rbp);
 834   pop(rbp);
 835 }
 836 
 837 void MacroAssembler::print_state() {
 838   address rip = pc();
 839   pusha();            // get regs on stack
 840   push(rbp);
 841   movq(rbp, rsp);
 842   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 843   push_CPU_state();   // keeps alignment at 16 bytes
 844 
 845   lea(c_rarg0, InternalAddress(rip));
 846   lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
 847   call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
 848 
 849   pop_CPU_state();
 850   mov(rsp, rbp);
 851   pop(rbp);
 852   popa();
 853 }
 854 
 855 #ifndef PRODUCT
 856 extern "C" void findpc(intptr_t x);
 857 #endif
 858 
 859 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
 860   // In order to get locks to work, we need to fake a in_VM state
 861   if (ShowMessageBoxOnError) {
 862     JavaThread* thread = JavaThread::current();
 863     JavaThreadState saved_state = thread->thread_state();
 864     thread->set_thread_state(_thread_in_vm);
 865 #ifndef PRODUCT
 866     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 867       ttyLocker ttyl;
 868       BytecodeCounter::print();
 869     }
 870 #endif
 871     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 872     // XXX correct this offset for amd64
 873     // This is the value of eip which points to where verify_oop will return.
 874     if (os::message_box(msg, "Execution stopped, print registers?")) {
 875       print_state64(pc, regs);
 876       BREAKPOINT;
 877       assert(false, "start up GDB");
 878     }
 879     ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
 880   } else {
 881     ttyLocker ttyl;
 882     ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
 883                     msg);
 884     assert(false, err_msg("DEBUG MESSAGE: %s", msg));
 885   }
 886 }
 887 
 888 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
 889   ttyLocker ttyl;
 890   FlagSetting fs(Debugging, true);
 891   tty->print_cr("rip = 0x%016lx", pc);
 892 #ifndef PRODUCT
 893   tty->cr();
 894   findpc(pc);
 895   tty->cr();
 896 #endif
 897 #define PRINT_REG(rax, value) \
 898   { tty->print("%s = ", #rax); os::print_location(tty, value); }
 899   PRINT_REG(rax, regs[15]);
 900   PRINT_REG(rbx, regs[12]);
 901   PRINT_REG(rcx, regs[14]);
 902   PRINT_REG(rdx, regs[13]);
 903   PRINT_REG(rdi, regs[8]);
 904   PRINT_REG(rsi, regs[9]);
 905   PRINT_REG(rbp, regs[10]);
 906   PRINT_REG(rsp, regs[11]);
 907   PRINT_REG(r8 , regs[7]);
 908   PRINT_REG(r9 , regs[6]);
 909   PRINT_REG(r10, regs[5]);
 910   PRINT_REG(r11, regs[4]);
 911   PRINT_REG(r12, regs[3]);
 912   PRINT_REG(r13, regs[2]);
 913   PRINT_REG(r14, regs[1]);
 914   PRINT_REG(r15, regs[0]);
 915 #undef PRINT_REG
 916   // Print some words near top of staack.
 917   int64_t* rsp = (int64_t*) regs[11];
 918   int64_t* dump_sp = rsp;
 919   for (int col1 = 0; col1 < 8; col1++) {
 920     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
 921     os::print_location(tty, *dump_sp++);
 922   }
 923   for (int row = 0; row < 25; row++) {
 924     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
 925     for (int col = 0; col < 4; col++) {
 926       tty->print(" 0x%016lx", *dump_sp++);
 927     }
 928     tty->cr();
 929   }
 930   // Print some instructions around pc:
 931   Disassembler::decode((address)pc-64, (address)pc);
 932   tty->print_cr("--------");
 933   Disassembler::decode((address)pc, (address)pc+32);
 934 }
 935 
 936 #endif // _LP64
 937 
 938 // Now versions that are common to 32/64 bit
 939 
 940 void MacroAssembler::addptr(Register dst, int32_t imm32) {
 941   LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
 942 }
 943 
 944 void MacroAssembler::addptr(Register dst, Register src) {
 945   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
 946 }
 947 
 948 void MacroAssembler::addptr(Address dst, Register src) {
 949   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
 950 }
 951 
 952 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
 953   if (reachable(src)) {
 954     Assembler::addsd(dst, as_Address(src));
 955   } else {
 956     lea(rscratch1, src);
 957     Assembler::addsd(dst, Address(rscratch1, 0));
 958   }
 959 }
 960 
 961 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
 962   if (reachable(src)) {
 963     addss(dst, as_Address(src));
 964   } else {
 965     lea(rscratch1, src);
 966     addss(dst, Address(rscratch1, 0));
 967   }
 968 }
 969 
 970 void MacroAssembler::align(int modulus) {
 971   if (offset() % modulus != 0) {
 972     nop(modulus - (offset() % modulus));
 973   }
 974 }
 975 
 976 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
 977   // Used in sign-masking with aligned address.
 978   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
 979   if (reachable(src)) {
 980     Assembler::andpd(dst, as_Address(src));
 981   } else {
 982     lea(rscratch1, src);
 983     Assembler::andpd(dst, Address(rscratch1, 0));
 984   }
 985 }
 986 
 987 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
 988   // Used in sign-masking with aligned address.
 989   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
 990   if (reachable(src)) {
 991     Assembler::andps(dst, as_Address(src));
 992   } else {
 993     lea(rscratch1, src);
 994     Assembler::andps(dst, Address(rscratch1, 0));
 995   }
 996 }
 997 
 998 void MacroAssembler::andptr(Register dst, int32_t imm32) {
 999   LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1000 }
1001 
1002 void MacroAssembler::atomic_incl(Address counter_addr) {
1003   if (os::is_MP())
1004     lock();
1005   incrementl(counter_addr);
1006 }
1007 
1008 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1009   if (reachable(counter_addr)) {
1010     atomic_incl(as_Address(counter_addr));
1011   } else {
1012     lea(scr, counter_addr);
1013     atomic_incl(Address(scr, 0));
1014   }
1015 }
1016 
1017 #ifdef _LP64
1018 void MacroAssembler::atomic_incq(Address counter_addr) {
1019   if (os::is_MP())
1020     lock();
1021   incrementq(counter_addr);
1022 }
1023 
1024 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1025   if (reachable(counter_addr)) {
1026     atomic_incq(as_Address(counter_addr));
1027   } else {
1028     lea(scr, counter_addr);
1029     atomic_incq(Address(scr, 0));
1030   }
1031 }
1032 #endif
1033 
1034 // Writes to stack successive pages until offset reached to check for
1035 // stack overflow + shadow pages.  This clobbers tmp.
1036 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1037   movptr(tmp, rsp);
1038   // Bang stack for total size given plus shadow page size.
1039   // Bang one page at a time because large size can bang beyond yellow and
1040   // red zones.
1041   Label loop;
1042   bind(loop);
1043   movl(Address(tmp, (-os::vm_page_size())), size );
1044   subptr(tmp, os::vm_page_size());
1045   subl(size, os::vm_page_size());
1046   jcc(Assembler::greater, loop);
1047 
1048   // Bang down shadow pages too.
1049   // At this point, (tmp-0) is the last address touched, so don't
1050   // touch it again.  (It was touched as (tmp-pagesize) but then tmp
1051   // was post-decremented.)  Skip this address by starting at i=1, and
1052   // touch a few more pages below.  N.B.  It is important to touch all
1053   // the way down to and including i=StackShadowPages.
1054   for (int i = 1; i <= StackShadowPages; i++) {
1055     // this could be any sized move but this is can be a debugging crumb
1056     // so the bigger the better.
1057     movptr(Address(tmp, (-i*os::vm_page_size())), size );
1058   }
1059 }
1060 
1061 int MacroAssembler::biased_locking_enter(Register lock_reg,
1062                                          Register obj_reg,
1063                                          Register swap_reg,
1064                                          Register tmp_reg,
1065                                          bool swap_reg_contains_mark,
1066                                          Label& done,
1067                                          Label* slow_case,
1068                                          BiasedLockingCounters* counters) {
1069   assert(UseBiasedLocking, "why call this otherwise?");
1070   assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1071   LP64_ONLY( assert(tmp_reg != noreg, "tmp_reg must be supplied"); )
1072   bool need_tmp_reg = false;
1073   if (tmp_reg == noreg) {
1074     need_tmp_reg = true;
1075     tmp_reg = lock_reg;
1076     assert_different_registers(lock_reg, obj_reg, swap_reg);
1077   } else {
1078     assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1079   }
1080   assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1081   Address mark_addr      (obj_reg, oopDesc::mark_offset_in_bytes());
1082   Address saved_mark_addr(lock_reg, 0);
1083 
1084   if (PrintBiasedLockingStatistics && counters == NULL) {
1085     counters = BiasedLocking::counters();
1086   }
1087   // Biased locking
1088   // See whether the lock is currently biased toward our thread and
1089   // whether the epoch is still valid
1090   // Note that the runtime guarantees sufficient alignment of JavaThread
1091   // pointers to allow age to be placed into low bits
1092   // First check to see whether biasing is even enabled for this object
1093   Label cas_label;
1094   int null_check_offset = -1;
1095   if (!swap_reg_contains_mark) {
1096     null_check_offset = offset();
1097     movptr(swap_reg, mark_addr);
1098   }
1099   if (need_tmp_reg) {
1100     push(tmp_reg);
1101   }
1102   movptr(tmp_reg, swap_reg);
1103   andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1104   cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1105   if (need_tmp_reg) {
1106     pop(tmp_reg);
1107   }
1108   jcc(Assembler::notEqual, cas_label);
1109   // The bias pattern is present in the object's header. Need to check
1110   // whether the bias owner and the epoch are both still current.
1111 #ifndef _LP64
1112   // Note that because there is no current thread register on x86_32 we
1113   // need to store off the mark word we read out of the object to
1114   // avoid reloading it and needing to recheck invariants below. This
1115   // store is unfortunate but it makes the overall code shorter and
1116   // simpler.
1117   movptr(saved_mark_addr, swap_reg);
1118 #endif
1119   if (need_tmp_reg) {
1120     push(tmp_reg);
1121   }
1122   if (swap_reg_contains_mark) {
1123     null_check_offset = offset();
1124   }
1125   load_prototype_header(tmp_reg, obj_reg);
1126 #ifdef _LP64
1127   orptr(tmp_reg, r15_thread);
1128   xorptr(tmp_reg, swap_reg);
1129   Register header_reg = tmp_reg;
1130 #else
1131   xorptr(tmp_reg, swap_reg);
1132   get_thread(swap_reg);
1133   xorptr(swap_reg, tmp_reg);
1134   Register header_reg = swap_reg;
1135 #endif
1136   andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1137   if (need_tmp_reg) {
1138     pop(tmp_reg);
1139   }
1140   if (counters != NULL) {
1141     cond_inc32(Assembler::zero,
1142                ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1143   }
1144   jcc(Assembler::equal, done);
1145 
1146   Label try_revoke_bias;
1147   Label try_rebias;
1148 
1149   // At this point we know that the header has the bias pattern and
1150   // that we are not the bias owner in the current epoch. We need to
1151   // figure out more details about the state of the header in order to
1152   // know what operations can be legally performed on the object's
1153   // header.
1154 
1155   // If the low three bits in the xor result aren't clear, that means
1156   // the prototype header is no longer biased and we have to revoke
1157   // the bias on this object.
1158   testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1159   jccb(Assembler::notZero, try_revoke_bias);
1160 
1161   // Biasing is still enabled for this data type. See whether the
1162   // epoch of the current bias is still valid, meaning that the epoch
1163   // bits of the mark word are equal to the epoch bits of the
1164   // prototype header. (Note that the prototype header's epoch bits
1165   // only change at a safepoint.) If not, attempt to rebias the object
1166   // toward the current thread. Note that we must be absolutely sure
1167   // that the current epoch is invalid in order to do this because
1168   // otherwise the manipulations it performs on the mark word are
1169   // illegal.
1170   testptr(header_reg, markOopDesc::epoch_mask_in_place);
1171   jccb(Assembler::notZero, try_rebias);
1172 
1173   // The epoch of the current bias is still valid but we know nothing
1174   // about the owner; it might be set or it might be clear. Try to
1175   // acquire the bias of the object using an atomic operation. If this
1176   // fails we will go in to the runtime to revoke the object's bias.
1177   // Note that we first construct the presumed unbiased header so we
1178   // don't accidentally blow away another thread's valid bias.
1179   NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1180   andptr(swap_reg,
1181          markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1182   if (need_tmp_reg) {
1183     push(tmp_reg);
1184   }
1185 #ifdef _LP64
1186   movptr(tmp_reg, swap_reg);
1187   orptr(tmp_reg, r15_thread);
1188 #else
1189   get_thread(tmp_reg);
1190   orptr(tmp_reg, swap_reg);
1191 #endif
1192   if (os::is_MP()) {
1193     lock();
1194   }
1195   cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1196   if (need_tmp_reg) {
1197     pop(tmp_reg);
1198   }
1199   // If the biasing toward our thread failed, this means that
1200   // another thread succeeded in biasing it toward itself and we
1201   // need to revoke that bias. The revocation will occur in the
1202   // interpreter runtime in the slow case.
1203   if (counters != NULL) {
1204     cond_inc32(Assembler::zero,
1205                ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1206   }
1207   if (slow_case != NULL) {
1208     jcc(Assembler::notZero, *slow_case);
1209   }
1210   jmp(done);
1211 
1212   bind(try_rebias);
1213   // At this point we know the epoch has expired, meaning that the
1214   // current "bias owner", if any, is actually invalid. Under these
1215   // circumstances _only_, we are allowed to use the current header's
1216   // value as the comparison value when doing the cas to acquire the
1217   // bias in the current epoch. In other words, we allow transfer of
1218   // the bias from one thread to another directly in this situation.
1219   //
1220   // FIXME: due to a lack of registers we currently blow away the age
1221   // bits in this situation. Should attempt to preserve them.
1222   if (need_tmp_reg) {
1223     push(tmp_reg);
1224   }
1225   load_prototype_header(tmp_reg, obj_reg);
1226 #ifdef _LP64
1227   orptr(tmp_reg, r15_thread);
1228 #else
1229   get_thread(swap_reg);
1230   orptr(tmp_reg, swap_reg);
1231   movptr(swap_reg, saved_mark_addr);
1232 #endif
1233   if (os::is_MP()) {
1234     lock();
1235   }
1236   cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1237   if (need_tmp_reg) {
1238     pop(tmp_reg);
1239   }
1240   // If the biasing toward our thread failed, then another thread
1241   // succeeded in biasing it toward itself and we need to revoke that
1242   // bias. The revocation will occur in the runtime in the slow case.
1243   if (counters != NULL) {
1244     cond_inc32(Assembler::zero,
1245                ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1246   }
1247   if (slow_case != NULL) {
1248     jcc(Assembler::notZero, *slow_case);
1249   }
1250   jmp(done);
1251 
1252   bind(try_revoke_bias);
1253   // The prototype mark in the klass doesn't have the bias bit set any
1254   // more, indicating that objects of this data type are not supposed
1255   // to be biased any more. We are going to try to reset the mark of
1256   // this object to the prototype value and fall through to the
1257   // CAS-based locking scheme. Note that if our CAS fails, it means
1258   // that another thread raced us for the privilege of revoking the
1259   // bias of this particular object, so it's okay to continue in the
1260   // normal locking code.
1261   //
1262   // FIXME: due to a lack of registers we currently blow away the age
1263   // bits in this situation. Should attempt to preserve them.
1264   NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1265   if (need_tmp_reg) {
1266     push(tmp_reg);
1267   }
1268   load_prototype_header(tmp_reg, obj_reg);
1269   if (os::is_MP()) {
1270     lock();
1271   }
1272   cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1273   if (need_tmp_reg) {
1274     pop(tmp_reg);
1275   }
1276   // Fall through to the normal CAS-based lock, because no matter what
1277   // the result of the above CAS, some thread must have succeeded in
1278   // removing the bias bit from the object's header.
1279   if (counters != NULL) {
1280     cond_inc32(Assembler::zero,
1281                ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1282   }
1283 
1284   bind(cas_label);
1285 
1286   return null_check_offset;
1287 }
1288 
1289 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1290   assert(UseBiasedLocking, "why call this otherwise?");
1291 
1292   // Check for biased locking unlock case, which is a no-op
1293   // Note: we do not have to check the thread ID for two reasons.
1294   // First, the interpreter checks for IllegalMonitorStateException at
1295   // a higher level. Second, if the bias was revoked while we held the
1296   // lock, the object could not be rebiased toward another thread, so
1297   // the bias bit would be clear.
1298   movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1299   andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1300   cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1301   jcc(Assembler::equal, done);
1302 }
1303 
1304 #ifdef COMPILER2
1305 
1306 #if INCLUDE_RTM_OPT
1307 
1308 // Update rtm_counters based on abort status
1309 // input: abort_status
1310 //        rtm_counters (RTMLockingCounters*)
1311 // flags are killed
1312 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1313 
1314   atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1315   if (PrintPreciseRTMLockingStatistics) {
1316     for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1317       Label check_abort;
1318       testl(abort_status, (1<<i));
1319       jccb(Assembler::equal, check_abort);
1320       atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1321       bind(check_abort);
1322     }
1323   }
1324 }
1325 
1326 // Branch if (random & (count-1) != 0), count is 2^n
1327 // tmp, scr and flags are killed
1328 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1329   assert(tmp == rax, "");
1330   assert(scr == rdx, "");
1331   rdtsc(); // modifies EDX:EAX
1332   andptr(tmp, count-1);
1333   jccb(Assembler::notZero, brLabel);
1334 }
1335 
1336 // Perform abort ratio calculation, set no_rtm bit if high ratio
1337 // input:  rtm_counters_Reg (RTMLockingCounters* address)
1338 // tmpReg, rtm_counters_Reg and flags are killed
1339 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1340                                                  Register rtm_counters_Reg,
1341                                                  RTMLockingCounters* rtm_counters,
1342                                                  Metadata* method_data) {
1343   Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1344 
1345   if (RTMLockingCalculationDelay > 0) {
1346     // Delay calculation
1347     movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1348     testptr(tmpReg, tmpReg);
1349     jccb(Assembler::equal, L_done);
1350   }
1351   // Abort ratio calculation only if abort_count > RTMAbortThreshold
1352   //   Aborted transactions = abort_count * 100
1353   //   All transactions = total_count *  RTMTotalCountIncrRate
1354   //   Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1355 
1356   movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1357   cmpptr(tmpReg, RTMAbortThreshold);
1358   jccb(Assembler::below, L_check_always_rtm2);
1359   imulptr(tmpReg, tmpReg, 100);
1360 
1361   Register scrReg = rtm_counters_Reg;
1362   movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1363   imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1364   imulptr(scrReg, scrReg, RTMAbortRatio);
1365   cmpptr(tmpReg, scrReg);
1366   jccb(Assembler::below, L_check_always_rtm1);
1367   if (method_data != NULL) {
1368     // set rtm_state to "no rtm" in MDO
1369     mov_metadata(tmpReg, method_data);
1370     if (os::is_MP()) {
1371       lock();
1372     }
1373     orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1374   }
1375   jmpb(L_done);
1376   bind(L_check_always_rtm1);
1377   // Reload RTMLockingCounters* address
1378   lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1379   bind(L_check_always_rtm2);
1380   movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1381   cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1382   jccb(Assembler::below, L_done);
1383   if (method_data != NULL) {
1384     // set rtm_state to "always rtm" in MDO
1385     mov_metadata(tmpReg, method_data);
1386     if (os::is_MP()) {
1387       lock();
1388     }
1389     orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1390   }
1391   bind(L_done);
1392 }
1393 
1394 // Update counters and perform abort ratio calculation
1395 // input:  abort_status_Reg
1396 // rtm_counters_Reg, flags are killed
1397 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1398                                    Register rtm_counters_Reg,
1399                                    RTMLockingCounters* rtm_counters,
1400                                    Metadata* method_data,
1401                                    bool profile_rtm) {
1402 
1403   assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1404   // update rtm counters based on rax value at abort
1405   // reads abort_status_Reg, updates flags
1406   lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1407   rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1408   if (profile_rtm) {
1409     // Save abort status because abort_status_Reg is used by following code.
1410     if (RTMRetryCount > 0) {
1411       push(abort_status_Reg);
1412     }
1413     assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1414     rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1415     // restore abort status
1416     if (RTMRetryCount > 0) {
1417       pop(abort_status_Reg);
1418     }
1419   }
1420 }
1421 
1422 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1423 // inputs: retry_count_Reg
1424 //       : abort_status_Reg
1425 // output: retry_count_Reg decremented by 1
1426 // flags are killed
1427 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1428   Label doneRetry;
1429   assert(abort_status_Reg == rax, "");
1430   // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1431   // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1432   // if reason is in 0x6 and retry count != 0 then retry
1433   andptr(abort_status_Reg, 0x6);
1434   jccb(Assembler::zero, doneRetry);
1435   testl(retry_count_Reg, retry_count_Reg);
1436   jccb(Assembler::zero, doneRetry);
1437   pause();
1438   decrementl(retry_count_Reg);
1439   jmp(retryLabel);
1440   bind(doneRetry);
1441 }
1442 
1443 // Spin and retry if lock is busy,
1444 // inputs: box_Reg (monitor address)
1445 //       : retry_count_Reg
1446 // output: retry_count_Reg decremented by 1
1447 //       : clear z flag if retry count exceeded
1448 // tmp_Reg, scr_Reg, flags are killed
1449 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1450                                             Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1451   Label SpinLoop, SpinExit, doneRetry;
1452   // Clean monitor_value bit to get valid pointer
1453   int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value;
1454 
1455   testl(retry_count_Reg, retry_count_Reg);
1456   jccb(Assembler::zero, doneRetry);
1457   decrementl(retry_count_Reg);
1458   movptr(scr_Reg, RTMSpinLoopCount);
1459 
1460   bind(SpinLoop);
1461   pause();
1462   decrementl(scr_Reg);
1463   jccb(Assembler::lessEqual, SpinExit);
1464   movptr(tmp_Reg, Address(box_Reg, owner_offset));
1465   testptr(tmp_Reg, tmp_Reg);
1466   jccb(Assembler::notZero, SpinLoop);
1467 
1468   bind(SpinExit);
1469   jmp(retryLabel);
1470   bind(doneRetry);
1471   incrementl(retry_count_Reg); // clear z flag
1472 }
1473 
1474 // Use RTM for normal stack locks
1475 // Input: objReg (object to lock)
1476 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1477                                        Register retry_on_abort_count_Reg,
1478                                        RTMLockingCounters* stack_rtm_counters,
1479                                        Metadata* method_data, bool profile_rtm,
1480                                        Label& DONE_LABEL, Label& IsInflated) {
1481   assert(UseRTMForStackLocks, "why call this otherwise?");
1482   assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1483   assert(tmpReg == rax, "");
1484   assert(scrReg == rdx, "");
1485   Label L_rtm_retry, L_decrement_retry, L_on_abort;
1486 
1487   if (RTMRetryCount > 0) {
1488     movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1489     bind(L_rtm_retry);
1490   }
1491   if (!UseRTMXendForLockBusy) {
1492     movptr(tmpReg, Address(objReg, 0));
1493     testptr(tmpReg, markOopDesc::monitor_value);  // inflated vs stack-locked|neutral|biased
1494     jcc(Assembler::notZero, IsInflated);
1495   }
1496   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1497     Label L_noincrement;
1498     if (RTMTotalCountIncrRate > 1) {
1499       // tmpReg, scrReg and flags are killed
1500       branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1501     }
1502     assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1503     atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1504     bind(L_noincrement);
1505   }
1506   xbegin(L_on_abort);
1507   movptr(tmpReg, Address(objReg, 0));       // fetch markword
1508   andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1509   cmpptr(tmpReg, markOopDesc::unlocked_value);            // bits = 001 unlocked
1510   jcc(Assembler::equal, DONE_LABEL);        // all done if unlocked
1511 
1512   Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1513   if (UseRTMXendForLockBusy) {
1514     xend();
1515     movptr(tmpReg, Address(objReg, 0));
1516     testptr(tmpReg, markOopDesc::monitor_value);  // inflated vs stack-locked|neutral|biased
1517     jcc(Assembler::notZero, IsInflated);
1518     movptr(abort_status_Reg, 0x1);                // Set the abort status to 1 (as xabort does)
1519     jmp(L_decrement_retry);
1520   }
1521   else {
1522     xabort(0);
1523   }
1524   bind(L_on_abort);
1525   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1526     rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1527   }
1528   bind(L_decrement_retry);
1529   if (RTMRetryCount > 0) {
1530     // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1531     rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1532   }
1533 }
1534 
1535 // Use RTM for inflating locks
1536 // inputs: objReg (object to lock)
1537 //         boxReg (on-stack box address (displaced header location) - KILLED)
1538 //         tmpReg (ObjectMonitor address + 2(monitor_value))
1539 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1540                                           Register scrReg, Register retry_on_busy_count_Reg,
1541                                           Register retry_on_abort_count_Reg,
1542                                           RTMLockingCounters* rtm_counters,
1543                                           Metadata* method_data, bool profile_rtm,
1544                                           Label& DONE_LABEL) {
1545   assert(UseRTMLocking, "why call this otherwise?");
1546   assert(tmpReg == rax, "");
1547   assert(scrReg == rdx, "");
1548   Label L_rtm_retry, L_decrement_retry, L_on_abort;
1549   // Clean monitor_value bit to get valid pointer
1550   int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value;
1551 
1552   // Without cast to int32_t a movptr will destroy r10 which is typically obj
1553   movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1554   movptr(boxReg, tmpReg); // Save ObjectMonitor address
1555 
1556   if (RTMRetryCount > 0) {
1557     movl(retry_on_busy_count_Reg, RTMRetryCount);  // Retry on lock busy
1558     movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1559     bind(L_rtm_retry);
1560   }
1561   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1562     Label L_noincrement;
1563     if (RTMTotalCountIncrRate > 1) {
1564       // tmpReg, scrReg and flags are killed
1565       branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1566     }
1567     assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1568     atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1569     bind(L_noincrement);
1570   }
1571   xbegin(L_on_abort);
1572   movptr(tmpReg, Address(objReg, 0));
1573   movptr(tmpReg, Address(tmpReg, owner_offset));
1574   testptr(tmpReg, tmpReg);
1575   jcc(Assembler::zero, DONE_LABEL);
1576   if (UseRTMXendForLockBusy) {
1577     xend();
1578     jmp(L_decrement_retry);
1579   }
1580   else {
1581     xabort(0);
1582   }
1583   bind(L_on_abort);
1584   Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1585   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1586     rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1587   }
1588   if (RTMRetryCount > 0) {
1589     // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1590     rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1591   }
1592 
1593   movptr(tmpReg, Address(boxReg, owner_offset)) ;
1594   testptr(tmpReg, tmpReg) ;
1595   jccb(Assembler::notZero, L_decrement_retry) ;
1596 
1597   // Appears unlocked - try to swing _owner from null to non-null.
1598   // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
1599 #ifdef _LP64
1600   Register threadReg = r15_thread;
1601 #else
1602   get_thread(scrReg);
1603   Register threadReg = scrReg;
1604 #endif
1605   if (os::is_MP()) {
1606     lock();
1607   }
1608   cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1609 
1610   if (RTMRetryCount > 0) {
1611     // success done else retry
1612     jccb(Assembler::equal, DONE_LABEL) ;
1613     bind(L_decrement_retry);
1614     // Spin and retry if lock is busy.
1615     rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1616   }
1617   else {
1618     bind(L_decrement_retry);
1619   }
1620 }
1621 
1622 #endif //  INCLUDE_RTM_OPT
1623 
1624 // Fast_Lock and Fast_Unlock used by C2
1625 
1626 // Because the transitions from emitted code to the runtime
1627 // monitorenter/exit helper stubs are so slow it's critical that
1628 // we inline both the stack-locking fast-path and the inflated fast path.
1629 //
1630 // See also: cmpFastLock and cmpFastUnlock.
1631 //
1632 // What follows is a specialized inline transliteration of the code
1633 // in slow_enter() and slow_exit().  If we're concerned about I$ bloat
1634 // another option would be to emit TrySlowEnter and TrySlowExit methods
1635 // at startup-time.  These methods would accept arguments as
1636 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1637 // indications in the icc.ZFlag.  Fast_Lock and Fast_Unlock would simply
1638 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1639 // In practice, however, the # of lock sites is bounded and is usually small.
1640 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1641 // if the processor uses simple bimodal branch predictors keyed by EIP
1642 // Since the helper routines would be called from multiple synchronization
1643 // sites.
1644 //
1645 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1646 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1647 // to those specialized methods.  That'd give us a mostly platform-independent
1648 // implementation that the JITs could optimize and inline at their pleasure.
1649 // Done correctly, the only time we'd need to cross to native could would be
1650 // to park() or unpark() threads.  We'd also need a few more unsafe operators
1651 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1652 // (b) explicit barriers or fence operations.
1653 //
1654 // TODO:
1655 //
1656 // *  Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1657 //    This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1658 //    Given TLAB allocation, Self is usually manifested in a register, so passing it into
1659 //    the lock operators would typically be faster than reifying Self.
1660 //
1661 // *  Ideally I'd define the primitives as:
1662 //       fast_lock   (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1663 //       fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1664 //    Unfortunately ADLC bugs prevent us from expressing the ideal form.
1665 //    Instead, we're stuck with a rather awkward and brittle register assignments below.
1666 //    Furthermore the register assignments are overconstrained, possibly resulting in
1667 //    sub-optimal code near the synchronization site.
1668 //
1669 // *  Eliminate the sp-proximity tests and just use "== Self" tests instead.
1670 //    Alternately, use a better sp-proximity test.
1671 //
1672 // *  Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1673 //    Either one is sufficient to uniquely identify a thread.
1674 //    TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1675 //
1676 // *  Intrinsify notify() and notifyAll() for the common cases where the
1677 //    object is locked by the calling thread but the waitlist is empty.
1678 //    avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1679 //
1680 // *  use jccb and jmpb instead of jcc and jmp to improve code density.
1681 //    But beware of excessive branch density on AMD Opterons.
1682 //
1683 // *  Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1684 //    or failure of the fast-path.  If the fast-path fails then we pass
1685 //    control to the slow-path, typically in C.  In Fast_Lock and
1686 //    Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1687 //    will emit a conditional branch immediately after the node.
1688 //    So we have branches to branches and lots of ICC.ZF games.
1689 //    Instead, it might be better to have C2 pass a "FailureLabel"
1690 //    into Fast_Lock and Fast_Unlock.  In the case of success, control
1691 //    will drop through the node.  ICC.ZF is undefined at exit.
1692 //    In the case of failure, the node will branch directly to the
1693 //    FailureLabel
1694 
1695 
1696 // obj: object to lock
1697 // box: on-stack box address (displaced header location) - KILLED
1698 // rax,: tmp -- KILLED
1699 // scr: tmp -- KILLED
1700 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1701                                Register scrReg, Register cx1Reg, Register cx2Reg,
1702                                BiasedLockingCounters* counters,
1703                                RTMLockingCounters* rtm_counters,
1704                                RTMLockingCounters* stack_rtm_counters,
1705                                Metadata* method_data,
1706                                bool use_rtm, bool profile_rtm) {
1707   // Ensure the register assignents are disjoint
1708   assert(tmpReg == rax, "");
1709 
1710   if (use_rtm) {
1711     assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1712   } else {
1713     assert(cx1Reg == noreg, "");
1714     assert(cx2Reg == noreg, "");
1715     assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1716   }
1717 
1718   if (counters != NULL) {
1719     atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1720   }
1721   if (EmitSync & 1) {
1722       // set box->dhw = unused_mark (3)
1723       // Force all sync thru slow-path: slow_enter() and slow_exit()
1724       movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1725       cmpptr (rsp, (int32_t)NULL_WORD);
1726   } else
1727   if (EmitSync & 2) {
1728       Label DONE_LABEL ;
1729       if (UseBiasedLocking) {
1730          // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
1731          biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1732       }
1733 
1734       movptr(tmpReg, Address(objReg, 0));           // fetch markword
1735       orptr (tmpReg, 0x1);
1736       movptr(Address(boxReg, 0), tmpReg);           // Anticipate successful CAS
1737       if (os::is_MP()) {
1738         lock();
1739       }
1740       cmpxchgptr(boxReg, Address(objReg, 0));       // Updates tmpReg
1741       jccb(Assembler::equal, DONE_LABEL);
1742       // Recursive locking
1743       subptr(tmpReg, rsp);
1744       andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1745       movptr(Address(boxReg, 0), tmpReg);
1746       bind(DONE_LABEL);
1747   } else {
1748     // Possible cases that we'll encounter in fast_lock
1749     // ------------------------------------------------
1750     // * Inflated
1751     //    -- unlocked
1752     //    -- Locked
1753     //       = by self
1754     //       = by other
1755     // * biased
1756     //    -- by Self
1757     //    -- by other
1758     // * neutral
1759     // * stack-locked
1760     //    -- by self
1761     //       = sp-proximity test hits
1762     //       = sp-proximity test generates false-negative
1763     //    -- by other
1764     //
1765 
1766     Label IsInflated, DONE_LABEL;
1767 
1768     // it's stack-locked, biased or neutral
1769     // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1770     // order to reduce the number of conditional branches in the most common cases.
1771     // Beware -- there's a subtle invariant that fetch of the markword
1772     // at [FETCH], below, will never observe a biased encoding (*101b).
1773     // If this invariant is not held we risk exclusion (safety) failure.
1774     if (UseBiasedLocking && !UseOptoBiasInlining) {
1775       biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, counters);
1776     }
1777 
1778 #if INCLUDE_RTM_OPT
1779     if (UseRTMForStackLocks && use_rtm) {
1780       rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1781                         stack_rtm_counters, method_data, profile_rtm,
1782                         DONE_LABEL, IsInflated);
1783     }
1784 #endif // INCLUDE_RTM_OPT
1785 
1786     movptr(tmpReg, Address(objReg, 0));          // [FETCH]
1787     testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1788     jccb(Assembler::notZero, IsInflated);
1789 
1790     // Attempt stack-locking ...
1791     orptr (tmpReg, markOopDesc::unlocked_value);
1792     movptr(Address(boxReg, 0), tmpReg);          // Anticipate successful CAS
1793     if (os::is_MP()) {
1794       lock();
1795     }
1796     cmpxchgptr(boxReg, Address(objReg, 0));      // Updates tmpReg
1797     if (counters != NULL) {
1798       cond_inc32(Assembler::equal,
1799                  ExternalAddress((address)counters->fast_path_entry_count_addr()));
1800     }
1801     jcc(Assembler::equal, DONE_LABEL);           // Success
1802 
1803     // Recursive locking.
1804     // The object is stack-locked: markword contains stack pointer to BasicLock.
1805     // Locked by current thread if difference with current SP is less than one page.
1806     subptr(tmpReg, rsp);
1807     // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1808     andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1809     movptr(Address(boxReg, 0), tmpReg);
1810     if (counters != NULL) {
1811       cond_inc32(Assembler::equal,
1812                  ExternalAddress((address)counters->fast_path_entry_count_addr()));
1813     }
1814     jmp(DONE_LABEL);
1815 
1816     bind(IsInflated);
1817     // The object is inflated. tmpReg contains pointer to ObjectMonitor* + 2(monitor_value)
1818 
1819 #if INCLUDE_RTM_OPT
1820     // Use the same RTM locking code in 32- and 64-bit VM.
1821     if (use_rtm) {
1822       rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1823                            rtm_counters, method_data, profile_rtm, DONE_LABEL);
1824     } else {
1825 #endif // INCLUDE_RTM_OPT
1826 
1827 #ifndef _LP64
1828     // The object is inflated.
1829     //
1830     // TODO-FIXME: eliminate the ugly use of manifest constants:
1831     //   Use markOopDesc::monitor_value instead of "2".
1832     //   use markOop::unused_mark() instead of "3".
1833     // The tmpReg value is an objectMonitor reference ORed with
1834     // markOopDesc::monitor_value (2).   We can either convert tmpReg to an
1835     // objectmonitor pointer by masking off the "2" bit or we can just
1836     // use tmpReg as an objectmonitor pointer but bias the objectmonitor
1837     // field offsets with "-2" to compensate for and annul the low-order tag bit.
1838     //
1839     // I use the latter as it avoids AGI stalls.
1840     // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
1841     // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
1842     //
1843     #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
1844 
1845     // boxReg refers to the on-stack BasicLock in the current frame.
1846     // We'd like to write:
1847     //   set box->_displaced_header = markOop::unused_mark().  Any non-0 value suffices.
1848     // This is convenient but results a ST-before-CAS penalty.  The following CAS suffers
1849     // additional latency as we have another ST in the store buffer that must drain.
1850 
1851     if (EmitSync & 8192) {
1852        movptr(Address(boxReg, 0), 3);            // results in ST-before-CAS penalty
1853        get_thread (scrReg);
1854        movptr(boxReg, tmpReg);                    // consider: LEA box, [tmp-2]
1855        movptr(tmpReg, NULL_WORD);                 // consider: xor vs mov
1856        if (os::is_MP()) {
1857          lock();
1858        }
1859        cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1860     } else
1861     if ((EmitSync & 128) == 0) {                      // avoid ST-before-CAS
1862        movptr(scrReg, boxReg);
1863        movptr(boxReg, tmpReg);                   // consider: LEA box, [tmp-2]
1864 
1865        // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1866        if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1867           // prefetchw [eax + Offset(_owner)-2]
1868           prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
1869        }
1870 
1871        if ((EmitSync & 64) == 0) {
1872          // Optimistic form: consider XORL tmpReg,tmpReg
1873          movptr(tmpReg, NULL_WORD);
1874        } else {
1875          // Can suffer RTS->RTO upgrades on shared or cold $ lines
1876          // Test-And-CAS instead of CAS
1877          movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));   // rax, = m->_owner
1878          testptr(tmpReg, tmpReg);                   // Locked ?
1879          jccb  (Assembler::notZero, DONE_LABEL);
1880        }
1881 
1882        // Appears unlocked - try to swing _owner from null to non-null.
1883        // Ideally, I'd manifest "Self" with get_thread and then attempt
1884        // to CAS the register containing Self into m->Owner.
1885        // But we don't have enough registers, so instead we can either try to CAS
1886        // rsp or the address of the box (in scr) into &m->owner.  If the CAS succeeds
1887        // we later store "Self" into m->Owner.  Transiently storing a stack address
1888        // (rsp or the address of the box) into  m->owner is harmless.
1889        // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
1890        if (os::is_MP()) {
1891          lock();
1892        }
1893        cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1894        movptr(Address(scrReg, 0), 3);          // box->_displaced_header = 3
1895        jccb  (Assembler::notZero, DONE_LABEL);
1896        get_thread (scrReg);                    // beware: clobbers ICCs
1897        movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg);
1898        xorptr(boxReg, boxReg);                 // set icc.ZFlag = 1 to indicate success
1899 
1900        // If the CAS fails we can either retry or pass control to the slow-path.
1901        // We use the latter tactic.
1902        // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1903        // If the CAS was successful ...
1904        //   Self has acquired the lock
1905        //   Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1906        // Intentional fall-through into DONE_LABEL ...
1907     } else {
1908        movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark()));  // results in ST-before-CAS penalty
1909        movptr(boxReg, tmpReg);
1910 
1911        // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1912        if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1913           // prefetchw [eax + Offset(_owner)-2]
1914           prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
1915        }
1916 
1917        if ((EmitSync & 64) == 0) {
1918          // Optimistic form
1919          xorptr  (tmpReg, tmpReg);
1920        } else {
1921          // Can suffer RTS->RTO upgrades on shared or cold $ lines
1922          movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));   // rax, = m->_owner
1923          testptr(tmpReg, tmpReg);                   // Locked ?
1924          jccb  (Assembler::notZero, DONE_LABEL);
1925        }
1926 
1927        // Appears unlocked - try to swing _owner from null to non-null.
1928        // Use either "Self" (in scr) or rsp as thread identity in _owner.
1929        // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
1930        get_thread (scrReg);
1931        if (os::is_MP()) {
1932          lock();
1933        }
1934        cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1935 
1936        // If the CAS fails we can either retry or pass control to the slow-path.
1937        // We use the latter tactic.
1938        // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1939        // If the CAS was successful ...
1940        //   Self has acquired the lock
1941        //   Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1942        // Intentional fall-through into DONE_LABEL ...
1943     }
1944 #else // _LP64
1945     // It's inflated
1946 
1947     // TODO: someday avoid the ST-before-CAS penalty by
1948     // relocating (deferring) the following ST.
1949     // We should also think about trying a CAS without having
1950     // fetched _owner.  If the CAS is successful we may
1951     // avoid an RTO->RTS upgrade on the $line.
1952 
1953     // Without cast to int32_t a movptr will destroy r10 which is typically obj
1954     movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1955 
1956     movptr (boxReg, tmpReg);
1957     movptr (tmpReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1958     testptr(tmpReg, tmpReg);
1959     jccb   (Assembler::notZero, DONE_LABEL);
1960 
1961     // It's inflated and appears unlocked
1962     if (os::is_MP()) {
1963       lock();
1964     }
1965     cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2));
1966     // Intentional fall-through into DONE_LABEL ...
1967 #endif // _LP64
1968 
1969 #if INCLUDE_RTM_OPT
1970     } // use_rtm()
1971 #endif
1972     // DONE_LABEL is a hot target - we'd really like to place it at the
1973     // start of cache line by padding with NOPs.
1974     // See the AMD and Intel software optimization manuals for the
1975     // most efficient "long" NOP encodings.
1976     // Unfortunately none of our alignment mechanisms suffice.
1977     bind(DONE_LABEL);
1978 
1979     // At DONE_LABEL the icc ZFlag is set as follows ...
1980     // Fast_Unlock uses the same protocol.
1981     // ZFlag == 1 -> Success
1982     // ZFlag == 0 -> Failure - force control through the slow-path
1983   }
1984 }
1985 
1986 // obj: object to unlock
1987 // box: box address (displaced header location), killed.  Must be EAX.
1988 // tmp: killed, cannot be obj nor box.
1989 //
1990 // Some commentary on balanced locking:
1991 //
1992 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1993 // Methods that don't have provably balanced locking are forced to run in the
1994 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1995 // The interpreter provides two properties:
1996 // I1:  At return-time the interpreter automatically and quietly unlocks any
1997 //      objects acquired the current activation (frame).  Recall that the
1998 //      interpreter maintains an on-stack list of locks currently held by
1999 //      a frame.
2000 // I2:  If a method attempts to unlock an object that is not held by the
2001 //      the frame the interpreter throws IMSX.
2002 //
2003 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
2004 // B() doesn't have provably balanced locking so it runs in the interpreter.
2005 // Control returns to A() and A() unlocks O.  By I1 and I2, above, we know that O
2006 // is still locked by A().
2007 //
2008 // The only other source of unbalanced locking would be JNI.  The "Java Native Interface:
2009 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
2010 // should not be unlocked by "normal" java-level locking and vice-versa.  The specification
2011 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
2012 
2013 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
2014   assert(boxReg == rax, "");
2015   assert_different_registers(objReg, boxReg, tmpReg);
2016 
2017   if (EmitSync & 4) {
2018     // Disable - inhibit all inlining.  Force control through the slow-path
2019     cmpptr (rsp, 0);
2020   } else
2021   if (EmitSync & 8) {
2022     Label DONE_LABEL;
2023     if (UseBiasedLocking) {
2024        biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2025     }
2026     // Classic stack-locking code ...
2027     // Check whether the displaced header is 0
2028     //(=> recursive unlock)
2029     movptr(tmpReg, Address(boxReg, 0));
2030     testptr(tmpReg, tmpReg);
2031     jccb(Assembler::zero, DONE_LABEL);
2032     // If not recursive lock, reset the header to displaced header
2033     if (os::is_MP()) {
2034       lock();
2035     }
2036     cmpxchgptr(tmpReg, Address(objReg, 0));   // Uses RAX which is box
2037     bind(DONE_LABEL);
2038   } else {
2039     Label DONE_LABEL, Stacked, CheckSucc;
2040 
2041     // Critically, the biased locking test must have precedence over
2042     // and appear before the (box->dhw == 0) recursive stack-lock test.
2043     if (UseBiasedLocking && !UseOptoBiasInlining) {
2044        biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2045     }
2046 
2047 #if INCLUDE_RTM_OPT
2048     if (UseRTMForStackLocks && use_rtm) {
2049       assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
2050       Label L_regular_unlock;
2051       movptr(tmpReg, Address(objReg, 0));           // fetch markword
2052       andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
2053       cmpptr(tmpReg, markOopDesc::unlocked_value);            // bits = 001 unlocked
2054       jccb(Assembler::notEqual, L_regular_unlock);  // if !HLE RegularLock
2055       xend();                                       // otherwise end...
2056       jmp(DONE_LABEL);                              // ... and we're done
2057       bind(L_regular_unlock);
2058     }
2059 #endif
2060 
2061     cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
2062     jcc   (Assembler::zero, DONE_LABEL);            // 0 indicates recursive stack-lock
2063     movptr(tmpReg, Address(objReg, 0));             // Examine the object's markword
2064     testptr(tmpReg, markOopDesc::monitor_value);    // Inflated?
2065     jccb  (Assembler::zero, Stacked);
2066 
2067     // It's inflated.
2068 #if INCLUDE_RTM_OPT
2069     if (use_rtm) {
2070       Label L_regular_inflated_unlock;
2071       // Clean monitor_value bit to get valid pointer
2072       int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value;
2073       movptr(boxReg, Address(tmpReg, owner_offset));
2074       testptr(boxReg, boxReg);
2075       jccb(Assembler::notZero, L_regular_inflated_unlock);
2076       xend();
2077       jmpb(DONE_LABEL);
2078       bind(L_regular_inflated_unlock);
2079     }
2080 #endif
2081 
2082     // Despite our balanced locking property we still check that m->_owner == Self
2083     // as java routines or native JNI code called by this thread might
2084     // have released the lock.
2085     // Refer to the comments in synchronizer.cpp for how we might encode extra
2086     // state in _succ so we can avoid fetching EntryList|cxq.
2087     //
2088     // I'd like to add more cases in fast_lock() and fast_unlock() --
2089     // such as recursive enter and exit -- but we have to be wary of
2090     // I$ bloat, T$ effects and BP$ effects.
2091     //
2092     // If there's no contention try a 1-0 exit.  That is, exit without
2093     // a costly MEMBAR or CAS.  See synchronizer.cpp for details on how
2094     // we detect and recover from the race that the 1-0 exit admits.
2095     //
2096     // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2097     // before it STs null into _owner, releasing the lock.  Updates
2098     // to data protected by the critical section must be visible before
2099     // we drop the lock (and thus before any other thread could acquire
2100     // the lock and observe the fields protected by the lock).
2101     // IA32's memory-model is SPO, so STs are ordered with respect to
2102     // each other and there's no need for an explicit barrier (fence).
2103     // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2104 #ifndef _LP64
2105     get_thread (boxReg);
2106     if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2107       // prefetchw [ebx + Offset(_owner)-2]
2108       prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2109     }
2110 
2111     // Note that we could employ various encoding schemes to reduce
2112     // the number of loads below (currently 4) to just 2 or 3.
2113     // Refer to the comments in synchronizer.cpp.
2114     // In practice the chain of fetches doesn't seem to impact performance, however.
2115     if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2116        // Attempt to reduce branch density - AMD's branch predictor.
2117        xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2118        orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2));
2119        orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2));
2120        orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2));
2121        jccb  (Assembler::notZero, DONE_LABEL);
2122        movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD);
2123        jmpb  (DONE_LABEL);
2124     } else {
2125        xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2126        orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2));
2127        jccb  (Assembler::notZero, DONE_LABEL);
2128        movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2));
2129        orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2));
2130        jccb  (Assembler::notZero, CheckSucc);
2131        movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD);
2132        jmpb  (DONE_LABEL);
2133     }
2134 
2135     // The Following code fragment (EmitSync & 65536) improves the performance of
2136     // contended applications and contended synchronization microbenchmarks.
2137     // Unfortunately the emission of the code - even though not executed - causes regressions
2138     // in scimark and jetstream, evidently because of $ effects.  Replacing the code
2139     // with an equal number of never-executed NOPs results in the same regression.
2140     // We leave it off by default.
2141 
2142     if ((EmitSync & 65536) != 0) {
2143        Label LSuccess, LGoSlowPath ;
2144 
2145        bind  (CheckSucc);
2146 
2147        // Optional pre-test ... it's safe to elide this
2148        if ((EmitSync & 16) == 0) {
2149           cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD);
2150           jccb  (Assembler::zero, LGoSlowPath);
2151        }
2152 
2153        // We have a classic Dekker-style idiom:
2154        //    ST m->_owner = 0 ; MEMBAR; LD m->_succ
2155        // There are a number of ways to implement the barrier:
2156        // (1) lock:andl &m->_owner, 0
2157        //     is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2158        //     LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2159        //     Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2160        // (2) If supported, an explicit MFENCE is appealing.
2161        //     In older IA32 processors MFENCE is slower than lock:add or xchg
2162        //     particularly if the write-buffer is full as might be the case if
2163        //     if stores closely precede the fence or fence-equivalent instruction.
2164        //     In more modern implementations MFENCE appears faster, however.
2165        // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2166        //     The $lines underlying the top-of-stack should be in M-state.
2167        //     The locked add instruction is serializing, of course.
2168        // (4) Use xchg, which is serializing
2169        //     mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2170        // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2171        //     The integer condition codes will tell us if succ was 0.
2172        //     Since _succ and _owner should reside in the same $line and
2173        //     we just stored into _owner, it's likely that the $line
2174        //     remains in M-state for the lock:orl.
2175        //
2176        // We currently use (3), although it's likely that switching to (2)
2177        // is correct for the future.
2178 
2179        movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD);
2180        if (os::is_MP()) {
2181           if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
2182             mfence();
2183           } else {
2184             lock (); addptr(Address(rsp, 0), 0);
2185           }
2186        }
2187        // Ratify _succ remains non-null
2188        cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0);
2189        jccb  (Assembler::notZero, LSuccess);
2190 
2191        xorptr(boxReg, boxReg);                  // box is really EAX
2192        if (os::is_MP()) { lock(); }
2193        cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2194        jccb  (Assembler::notEqual, LSuccess);
2195        // Since we're low on registers we installed rsp as a placeholding in _owner.
2196        // Now install Self over rsp.  This is safe as we're transitioning from
2197        // non-null to non=null
2198        get_thread (boxReg);
2199        movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg);
2200        // Intentional fall-through into LGoSlowPath ...
2201 
2202        bind  (LGoSlowPath);
2203        orptr(boxReg, 1);                      // set ICC.ZF=0 to indicate failure
2204        jmpb  (DONE_LABEL);
2205 
2206        bind  (LSuccess);
2207        xorptr(boxReg, boxReg);                 // set ICC.ZF=1 to indicate success
2208        jmpb  (DONE_LABEL);
2209     }
2210 
2211     bind (Stacked);
2212     // It's not inflated and it's not recursively stack-locked and it's not biased.
2213     // It must be stack-locked.
2214     // Try to reset the header to displaced header.
2215     // The "box" value on the stack is stable, so we can reload
2216     // and be assured we observe the same value as above.
2217     movptr(tmpReg, Address(boxReg, 0));
2218     if (os::is_MP()) {
2219       lock();
2220     }
2221     cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2222     // Intention fall-thru into DONE_LABEL
2223 
2224     // DONE_LABEL is a hot target - we'd really like to place it at the
2225     // start of cache line by padding with NOPs.
2226     // See the AMD and Intel software optimization manuals for the
2227     // most efficient "long" NOP encodings.
2228     // Unfortunately none of our alignment mechanisms suffice.
2229     if ((EmitSync & 65536) == 0) {
2230        bind (CheckSucc);
2231     }
2232 #else // _LP64
2233     // It's inflated
2234     movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2235     xorptr(boxReg, r15_thread);
2236     orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2));
2237     jccb  (Assembler::notZero, DONE_LABEL);
2238     movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2));
2239     orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2));
2240     jccb  (Assembler::notZero, CheckSucc);
2241     movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD);
2242     jmpb  (DONE_LABEL);
2243 
2244     if ((EmitSync & 65536) == 0) {
2245       Label LSuccess, LGoSlowPath ;
2246       bind  (CheckSucc);
2247       cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD);
2248       jccb  (Assembler::zero, LGoSlowPath);
2249 
2250       // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
2251       // the explicit ST;MEMBAR combination, but masm doesn't currently support
2252       // "ANDQ M,IMM".  Don't use MFENCE here.  lock:add to TOS, xchg, etc
2253       // are all faster when the write buffer is populated.
2254       movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD);
2255       if (os::is_MP()) {
2256          lock (); addl (Address(rsp, 0), 0);
2257       }
2258       cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD);
2259       jccb  (Assembler::notZero, LSuccess);
2260 
2261       movptr (boxReg, (int32_t)NULL_WORD);                   // box is really EAX
2262       if (os::is_MP()) { lock(); }
2263       cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
2264       jccb  (Assembler::notEqual, LSuccess);
2265       // Intentional fall-through into slow-path
2266 
2267       bind  (LGoSlowPath);
2268       orl   (boxReg, 1);                      // set ICC.ZF=0 to indicate failure
2269       jmpb  (DONE_LABEL);
2270 
2271       bind  (LSuccess);
2272       testl (boxReg, 0);                      // set ICC.ZF=1 to indicate success
2273       jmpb  (DONE_LABEL);
2274     }
2275 
2276     bind  (Stacked);
2277     movptr(tmpReg, Address (boxReg, 0));      // re-fetch
2278     if (os::is_MP()) { lock(); }
2279     cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2280 
2281     if (EmitSync & 65536) {
2282        bind (CheckSucc);
2283     }
2284 #endif
2285     bind(DONE_LABEL);
2286     // Avoid branch to branch on AMD processors
2287     if (EmitSync & 32768) {
2288        nop();
2289     }
2290   }
2291 }
2292 #endif // COMPILER2
2293 
2294 void MacroAssembler::c2bool(Register x) {
2295   // implements x == 0 ? 0 : 1
2296   // note: must only look at least-significant byte of x
2297   //       since C-style booleans are stored in one byte
2298   //       only! (was bug)
2299   andl(x, 0xFF);
2300   setb(Assembler::notZero, x);
2301 }
2302 
2303 // Wouldn't need if AddressLiteral version had new name
2304 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2305   Assembler::call(L, rtype);
2306 }
2307 
2308 void MacroAssembler::call(Register entry) {
2309   Assembler::call(entry);
2310 }
2311 
2312 void MacroAssembler::call(AddressLiteral entry) {
2313   if (reachable(entry)) {
2314     Assembler::call_literal(entry.target(), entry.rspec());
2315   } else {
2316     lea(rscratch1, entry);
2317     Assembler::call(rscratch1);
2318   }
2319 }
2320 
2321 void MacroAssembler::ic_call(address entry) {
2322   RelocationHolder rh = virtual_call_Relocation::spec(pc());
2323   movptr(rax, (intptr_t)Universe::non_oop_word());
2324   call(AddressLiteral(entry, rh));
2325 }
2326 
2327 // Implementation of call_VM versions
2328 
2329 void MacroAssembler::call_VM(Register oop_result,
2330                              address entry_point,
2331                              bool check_exceptions) {
2332   Label C, E;
2333   call(C, relocInfo::none);
2334   jmp(E);
2335 
2336   bind(C);
2337   call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2338   ret(0);
2339 
2340   bind(E);
2341 }
2342 
2343 void MacroAssembler::call_VM(Register oop_result,
2344                              address entry_point,
2345                              Register arg_1,
2346                              bool check_exceptions) {
2347   Label C, E;
2348   call(C, relocInfo::none);
2349   jmp(E);
2350 
2351   bind(C);
2352   pass_arg1(this, arg_1);
2353   call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2354   ret(0);
2355 
2356   bind(E);
2357 }
2358 
2359 void MacroAssembler::call_VM(Register oop_result,
2360                              address entry_point,
2361                              Register arg_1,
2362                              Register arg_2,
2363                              bool check_exceptions) {
2364   Label C, E;
2365   call(C, relocInfo::none);
2366   jmp(E);
2367 
2368   bind(C);
2369 
2370   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2371 
2372   pass_arg2(this, arg_2);
2373   pass_arg1(this, arg_1);
2374   call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2375   ret(0);
2376 
2377   bind(E);
2378 }
2379 
2380 void MacroAssembler::call_VM(Register oop_result,
2381                              address entry_point,
2382                              Register arg_1,
2383                              Register arg_2,
2384                              Register arg_3,
2385                              bool check_exceptions) {
2386   Label C, E;
2387   call(C, relocInfo::none);
2388   jmp(E);
2389 
2390   bind(C);
2391 
2392   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2393   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2394   pass_arg3(this, arg_3);
2395 
2396   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2397   pass_arg2(this, arg_2);
2398 
2399   pass_arg1(this, arg_1);
2400   call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2401   ret(0);
2402 
2403   bind(E);
2404 }
2405 
2406 void MacroAssembler::call_VM(Register oop_result,
2407                              Register last_java_sp,
2408                              address entry_point,
2409                              int number_of_arguments,
2410                              bool check_exceptions) {
2411   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2412   call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2413 }
2414 
2415 void MacroAssembler::call_VM(Register oop_result,
2416                              Register last_java_sp,
2417                              address entry_point,
2418                              Register arg_1,
2419                              bool check_exceptions) {
2420   pass_arg1(this, arg_1);
2421   call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2422 }
2423 
2424 void MacroAssembler::call_VM(Register oop_result,
2425                              Register last_java_sp,
2426                              address entry_point,
2427                              Register arg_1,
2428                              Register arg_2,
2429                              bool check_exceptions) {
2430 
2431   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2432   pass_arg2(this, arg_2);
2433   pass_arg1(this, arg_1);
2434   call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2435 }
2436 
2437 void MacroAssembler::call_VM(Register oop_result,
2438                              Register last_java_sp,
2439                              address entry_point,
2440                              Register arg_1,
2441                              Register arg_2,
2442                              Register arg_3,
2443                              bool check_exceptions) {
2444   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2445   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2446   pass_arg3(this, arg_3);
2447   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2448   pass_arg2(this, arg_2);
2449   pass_arg1(this, arg_1);
2450   call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2451 }
2452 
2453 void MacroAssembler::super_call_VM(Register oop_result,
2454                                    Register last_java_sp,
2455                                    address entry_point,
2456                                    int number_of_arguments,
2457                                    bool check_exceptions) {
2458   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2459   MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2460 }
2461 
2462 void MacroAssembler::super_call_VM(Register oop_result,
2463                                    Register last_java_sp,
2464                                    address entry_point,
2465                                    Register arg_1,
2466                                    bool check_exceptions) {
2467   pass_arg1(this, arg_1);
2468   super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2469 }
2470 
2471 void MacroAssembler::super_call_VM(Register oop_result,
2472                                    Register last_java_sp,
2473                                    address entry_point,
2474                                    Register arg_1,
2475                                    Register arg_2,
2476                                    bool check_exceptions) {
2477 
2478   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2479   pass_arg2(this, arg_2);
2480   pass_arg1(this, arg_1);
2481   super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2482 }
2483 
2484 void MacroAssembler::super_call_VM(Register oop_result,
2485                                    Register last_java_sp,
2486                                    address entry_point,
2487                                    Register arg_1,
2488                                    Register arg_2,
2489                                    Register arg_3,
2490                                    bool check_exceptions) {
2491   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2492   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2493   pass_arg3(this, arg_3);
2494   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2495   pass_arg2(this, arg_2);
2496   pass_arg1(this, arg_1);
2497   super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2498 }
2499 
2500 void MacroAssembler::call_VM_base(Register oop_result,
2501                                   Register java_thread,
2502                                   Register last_java_sp,
2503                                   address  entry_point,
2504                                   int      number_of_arguments,
2505                                   bool     check_exceptions) {
2506   // determine java_thread register
2507   if (!java_thread->is_valid()) {
2508 #ifdef _LP64
2509     java_thread = r15_thread;
2510 #else
2511     java_thread = rdi;
2512     get_thread(java_thread);
2513 #endif // LP64
2514   }
2515   // determine last_java_sp register
2516   if (!last_java_sp->is_valid()) {
2517     last_java_sp = rsp;
2518   }
2519   // debugging support
2520   assert(number_of_arguments >= 0   , "cannot have negative number of arguments");
2521   LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2522 #ifdef ASSERT
2523   // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2524   // r12 is the heapbase.
2525   LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2526 #endif // ASSERT
2527 
2528   assert(java_thread != oop_result  , "cannot use the same register for java_thread & oop_result");
2529   assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2530 
2531   // push java thread (becomes first argument of C function)
2532 
2533   NOT_LP64(push(java_thread); number_of_arguments++);
2534   LP64_ONLY(mov(c_rarg0, r15_thread));
2535 
2536   // set last Java frame before call
2537   assert(last_java_sp != rbp, "can't use ebp/rbp");
2538 
2539   // Only interpreter should have to set fp
2540   set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2541 
2542   // do the call, remove parameters
2543   MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2544 
2545   // restore the thread (cannot use the pushed argument since arguments
2546   // may be overwritten by C code generated by an optimizing compiler);
2547   // however can use the register value directly if it is callee saved.
2548   if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2549     // rdi & rsi (also r15) are callee saved -> nothing to do
2550 #ifdef ASSERT
2551     guarantee(java_thread != rax, "change this code");
2552     push(rax);
2553     { Label L;
2554       get_thread(rax);
2555       cmpptr(java_thread, rax);
2556       jcc(Assembler::equal, L);
2557       STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2558       bind(L);
2559     }
2560     pop(rax);
2561 #endif
2562   } else {
2563     get_thread(java_thread);
2564   }
2565   // reset last Java frame
2566   // Only interpreter should have to clear fp
2567   reset_last_Java_frame(java_thread, true, false);
2568 
2569 #ifndef CC_INTERP
2570    // C++ interp handles this in the interpreter
2571   check_and_handle_popframe(java_thread);
2572   check_and_handle_earlyret(java_thread);
2573 #endif /* CC_INTERP */
2574 
2575   if (check_exceptions) {
2576     // check for pending exceptions (java_thread is set upon return)
2577     cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2578 #ifndef _LP64
2579     jump_cc(Assembler::notEqual,
2580             RuntimeAddress(StubRoutines::forward_exception_entry()));
2581 #else
2582     // This used to conditionally jump to forward_exception however it is
2583     // possible if we relocate that the branch will not reach. So we must jump
2584     // around so we can always reach
2585 
2586     Label ok;
2587     jcc(Assembler::equal, ok);
2588     jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2589     bind(ok);
2590 #endif // LP64
2591   }
2592 
2593   // get oop result if there is one and reset the value in the thread
2594   if (oop_result->is_valid()) {
2595     get_vm_result(oop_result, java_thread);
2596   }
2597 }
2598 
2599 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2600 
2601   // Calculate the value for last_Java_sp
2602   // somewhat subtle. call_VM does an intermediate call
2603   // which places a return address on the stack just under the
2604   // stack pointer as the user finsihed with it. This allows
2605   // use to retrieve last_Java_pc from last_Java_sp[-1].
2606   // On 32bit we then have to push additional args on the stack to accomplish
2607   // the actual requested call. On 64bit call_VM only can use register args
2608   // so the only extra space is the return address that call_VM created.
2609   // This hopefully explains the calculations here.
2610 
2611 #ifdef _LP64
2612   // We've pushed one address, correct last_Java_sp
2613   lea(rax, Address(rsp, wordSize));
2614 #else
2615   lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2616 #endif // LP64
2617 
2618   call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2619 
2620 }
2621 
2622 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2623   call_VM_leaf_base(entry_point, number_of_arguments);
2624 }
2625 
2626 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2627   pass_arg0(this, arg_0);
2628   call_VM_leaf(entry_point, 1);
2629 }
2630 
2631 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2632 
2633   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2634   pass_arg1(this, arg_1);
2635   pass_arg0(this, arg_0);
2636   call_VM_leaf(entry_point, 2);
2637 }
2638 
2639 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2640   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2641   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2642   pass_arg2(this, arg_2);
2643   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2644   pass_arg1(this, arg_1);
2645   pass_arg0(this, arg_0);
2646   call_VM_leaf(entry_point, 3);
2647 }
2648 
2649 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2650   pass_arg0(this, arg_0);
2651   MacroAssembler::call_VM_leaf_base(entry_point, 1);
2652 }
2653 
2654 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2655 
2656   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2657   pass_arg1(this, arg_1);
2658   pass_arg0(this, arg_0);
2659   MacroAssembler::call_VM_leaf_base(entry_point, 2);
2660 }
2661 
2662 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2663   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2664   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2665   pass_arg2(this, arg_2);
2666   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2667   pass_arg1(this, arg_1);
2668   pass_arg0(this, arg_0);
2669   MacroAssembler::call_VM_leaf_base(entry_point, 3);
2670 }
2671 
2672 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2673   LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2674   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2675   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2676   pass_arg3(this, arg_3);
2677   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2678   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2679   pass_arg2(this, arg_2);
2680   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2681   pass_arg1(this, arg_1);
2682   pass_arg0(this, arg_0);
2683   MacroAssembler::call_VM_leaf_base(entry_point, 4);
2684 }
2685 
2686 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2687   movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2688   movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2689   verify_oop(oop_result, "broken oop in call_VM_base");
2690 }
2691 
2692 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2693   movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2694   movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2695 }
2696 
2697 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2698 }
2699 
2700 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2701 }
2702 
2703 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2704   if (reachable(src1)) {
2705     cmpl(as_Address(src1), imm);
2706   } else {
2707     lea(rscratch1, src1);
2708     cmpl(Address(rscratch1, 0), imm);
2709   }
2710 }
2711 
2712 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2713   assert(!src2.is_lval(), "use cmpptr");
2714   if (reachable(src2)) {
2715     cmpl(src1, as_Address(src2));
2716   } else {
2717     lea(rscratch1, src2);
2718     cmpl(src1, Address(rscratch1, 0));
2719   }
2720 }
2721 
2722 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2723   Assembler::cmpl(src1, imm);
2724 }
2725 
2726 void MacroAssembler::cmp32(Register src1, Address src2) {
2727   Assembler::cmpl(src1, src2);
2728 }
2729 
2730 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2731   ucomisd(opr1, opr2);
2732 
2733   Label L;
2734   if (unordered_is_less) {
2735     movl(dst, -1);
2736     jcc(Assembler::parity, L);
2737     jcc(Assembler::below , L);
2738     movl(dst, 0);
2739     jcc(Assembler::equal , L);
2740     increment(dst);
2741   } else { // unordered is greater
2742     movl(dst, 1);
2743     jcc(Assembler::parity, L);
2744     jcc(Assembler::above , L);
2745     movl(dst, 0);
2746     jcc(Assembler::equal , L);
2747     decrementl(dst);
2748   }
2749   bind(L);
2750 }
2751 
2752 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2753   ucomiss(opr1, opr2);
2754 
2755   Label L;
2756   if (unordered_is_less) {
2757     movl(dst, -1);
2758     jcc(Assembler::parity, L);
2759     jcc(Assembler::below , L);
2760     movl(dst, 0);
2761     jcc(Assembler::equal , L);
2762     increment(dst);
2763   } else { // unordered is greater
2764     movl(dst, 1);
2765     jcc(Assembler::parity, L);
2766     jcc(Assembler::above , L);
2767     movl(dst, 0);
2768     jcc(Assembler::equal , L);
2769     decrementl(dst);
2770   }
2771   bind(L);
2772 }
2773 
2774 
2775 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2776   if (reachable(src1)) {
2777     cmpb(as_Address(src1), imm);
2778   } else {
2779     lea(rscratch1, src1);
2780     cmpb(Address(rscratch1, 0), imm);
2781   }
2782 }
2783 
2784 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2785 #ifdef _LP64
2786   if (src2.is_lval()) {
2787     movptr(rscratch1, src2);
2788     Assembler::cmpq(src1, rscratch1);
2789   } else if (reachable(src2)) {
2790     cmpq(src1, as_Address(src2));
2791   } else {
2792     lea(rscratch1, src2);
2793     Assembler::cmpq(src1, Address(rscratch1, 0));
2794   }
2795 #else
2796   if (src2.is_lval()) {
2797     cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2798   } else {
2799     cmpl(src1, as_Address(src2));
2800   }
2801 #endif // _LP64
2802 }
2803 
2804 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2805   assert(src2.is_lval(), "not a mem-mem compare");
2806 #ifdef _LP64
2807   // moves src2's literal address
2808   movptr(rscratch1, src2);
2809   Assembler::cmpq(src1, rscratch1);
2810 #else
2811   cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2812 #endif // _LP64
2813 }
2814 
2815 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2816   if (reachable(adr)) {
2817     if (os::is_MP())
2818       lock();
2819     cmpxchgptr(reg, as_Address(adr));
2820   } else {
2821     lea(rscratch1, adr);
2822     if (os::is_MP())
2823       lock();
2824     cmpxchgptr(reg, Address(rscratch1, 0));
2825   }
2826 }
2827 
2828 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2829   LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2830 }
2831 
2832 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2833   if (reachable(src)) {
2834     Assembler::comisd(dst, as_Address(src));
2835   } else {
2836     lea(rscratch1, src);
2837     Assembler::comisd(dst, Address(rscratch1, 0));
2838   }
2839 }
2840 
2841 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2842   if (reachable(src)) {
2843     Assembler::comiss(dst, as_Address(src));
2844   } else {
2845     lea(rscratch1, src);
2846     Assembler::comiss(dst, Address(rscratch1, 0));
2847   }
2848 }
2849 
2850 
2851 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2852   Condition negated_cond = negate_condition(cond);
2853   Label L;
2854   jcc(negated_cond, L);
2855   pushf(); // Preserve flags
2856   atomic_incl(counter_addr);
2857   popf();
2858   bind(L);
2859 }
2860 
2861 int MacroAssembler::corrected_idivl(Register reg) {
2862   // Full implementation of Java idiv and irem; checks for
2863   // special case as described in JVM spec., p.243 & p.271.
2864   // The function returns the (pc) offset of the idivl
2865   // instruction - may be needed for implicit exceptions.
2866   //
2867   //         normal case                           special case
2868   //
2869   // input : rax,: dividend                         min_int
2870   //         reg: divisor   (may not be rax,/rdx)   -1
2871   //
2872   // output: rax,: quotient  (= rax, idiv reg)       min_int
2873   //         rdx: remainder (= rax, irem reg)       0
2874   assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2875   const int min_int = 0x80000000;
2876   Label normal_case, special_case;
2877 
2878   // check for special case
2879   cmpl(rax, min_int);
2880   jcc(Assembler::notEqual, normal_case);
2881   xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2882   cmpl(reg, -1);
2883   jcc(Assembler::equal, special_case);
2884 
2885   // handle normal case
2886   bind(normal_case);
2887   cdql();
2888   int idivl_offset = offset();
2889   idivl(reg);
2890 
2891   // normal and special case exit
2892   bind(special_case);
2893 
2894   return idivl_offset;
2895 }
2896 
2897 
2898 
2899 void MacroAssembler::decrementl(Register reg, int value) {
2900   if (value == min_jint) {subl(reg, value) ; return; }
2901   if (value <  0) { incrementl(reg, -value); return; }
2902   if (value == 0) {                        ; return; }
2903   if (value == 1 && UseIncDec) { decl(reg) ; return; }
2904   /* else */      { subl(reg, value)       ; return; }
2905 }
2906 
2907 void MacroAssembler::decrementl(Address dst, int value) {
2908   if (value == min_jint) {subl(dst, value) ; return; }
2909   if (value <  0) { incrementl(dst, -value); return; }
2910   if (value == 0) {                        ; return; }
2911   if (value == 1 && UseIncDec) { decl(dst) ; return; }
2912   /* else */      { subl(dst, value)       ; return; }
2913 }
2914 
2915 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2916   assert (shift_value > 0, "illegal shift value");
2917   Label _is_positive;
2918   testl (reg, reg);
2919   jcc (Assembler::positive, _is_positive);
2920   int offset = (1 << shift_value) - 1 ;
2921 
2922   if (offset == 1) {
2923     incrementl(reg);
2924   } else {
2925     addl(reg, offset);
2926   }
2927 
2928   bind (_is_positive);
2929   sarl(reg, shift_value);
2930 }
2931 
2932 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2933   if (reachable(src)) {
2934     Assembler::divsd(dst, as_Address(src));
2935   } else {
2936     lea(rscratch1, src);
2937     Assembler::divsd(dst, Address(rscratch1, 0));
2938   }
2939 }
2940 
2941 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2942   if (reachable(src)) {
2943     Assembler::divss(dst, as_Address(src));
2944   } else {
2945     lea(rscratch1, src);
2946     Assembler::divss(dst, Address(rscratch1, 0));
2947   }
2948 }
2949 
2950 // !defined(COMPILER2) is because of stupid core builds
2951 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
2952 void MacroAssembler::empty_FPU_stack() {
2953   if (VM_Version::supports_mmx()) {
2954     emms();
2955   } else {
2956     for (int i = 8; i-- > 0; ) ffree(i);
2957   }
2958 }
2959 #endif // !LP64 || C1 || !C2
2960 
2961 
2962 // Defines obj, preserves var_size_in_bytes
2963 void MacroAssembler::eden_allocate(Register obj,
2964                                    Register var_size_in_bytes,
2965                                    int con_size_in_bytes,
2966                                    Register t1,
2967                                    Label& slow_case) {
2968   assert(obj == rax, "obj must be in rax, for cmpxchg");
2969   assert_different_registers(obj, var_size_in_bytes, t1);
2970   if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
2971     jmp(slow_case);
2972   } else {
2973     Register end = t1;
2974     Label retry;
2975     bind(retry);
2976     ExternalAddress heap_top((address) Universe::heap()->top_addr());
2977     movptr(obj, heap_top);
2978     if (var_size_in_bytes == noreg) {
2979       lea(end, Address(obj, con_size_in_bytes));
2980     } else {
2981       lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2982     }
2983     // if end < obj then we wrapped around => object too long => slow case
2984     cmpptr(end, obj);
2985     jcc(Assembler::below, slow_case);
2986     cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2987     jcc(Assembler::above, slow_case);
2988     // Compare obj with the top addr, and if still equal, store the new top addr in
2989     // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2990     // it otherwise. Use lock prefix for atomicity on MPs.
2991     locked_cmpxchgptr(end, heap_top);
2992     jcc(Assembler::notEqual, retry);
2993   }
2994 }
2995 
2996 void MacroAssembler::enter() {
2997   push(rbp);
2998   mov(rbp, rsp);
2999 }
3000 
3001 // A 5 byte nop that is safe for patching (see patch_verified_entry)
3002 void MacroAssembler::fat_nop() {
3003   if (UseAddressNop) {
3004     addr_nop_5();
3005   } else {
3006     emit_int8(0x26); // es:
3007     emit_int8(0x2e); // cs:
3008     emit_int8(0x64); // fs:
3009     emit_int8(0x65); // gs:
3010     emit_int8((unsigned char)0x90);
3011   }
3012 }
3013 
3014 void MacroAssembler::fcmp(Register tmp) {
3015   fcmp(tmp, 1, true, true);
3016 }
3017 
3018 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
3019   assert(!pop_right || pop_left, "usage error");
3020   if (VM_Version::supports_cmov()) {
3021     assert(tmp == noreg, "unneeded temp");
3022     if (pop_left) {
3023       fucomip(index);
3024     } else {
3025       fucomi(index);
3026     }
3027     if (pop_right) {
3028       fpop();
3029     }
3030   } else {
3031     assert(tmp != noreg, "need temp");
3032     if (pop_left) {
3033       if (pop_right) {
3034         fcompp();
3035       } else {
3036         fcomp(index);
3037       }
3038     } else {
3039       fcom(index);
3040     }
3041     // convert FPU condition into eflags condition via rax,
3042     save_rax(tmp);
3043     fwait(); fnstsw_ax();
3044     sahf();
3045     restore_rax(tmp);
3046   }
3047   // condition codes set as follows:
3048   //
3049   // CF (corresponds to C0) if x < y
3050   // PF (corresponds to C2) if unordered
3051   // ZF (corresponds to C3) if x = y
3052 }
3053 
3054 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3055   fcmp2int(dst, unordered_is_less, 1, true, true);
3056 }
3057 
3058 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3059   fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3060   Label L;
3061   if (unordered_is_less) {
3062     movl(dst, -1);
3063     jcc(Assembler::parity, L);
3064     jcc(Assembler::below , L);
3065     movl(dst, 0);
3066     jcc(Assembler::equal , L);
3067     increment(dst);
3068   } else { // unordered is greater
3069     movl(dst, 1);
3070     jcc(Assembler::parity, L);
3071     jcc(Assembler::above , L);
3072     movl(dst, 0);
3073     jcc(Assembler::equal , L);
3074     decrementl(dst);
3075   }
3076   bind(L);
3077 }
3078 
3079 void MacroAssembler::fld_d(AddressLiteral src) {
3080   fld_d(as_Address(src));
3081 }
3082 
3083 void MacroAssembler::fld_s(AddressLiteral src) {
3084   fld_s(as_Address(src));
3085 }
3086 
3087 void MacroAssembler::fld_x(AddressLiteral src) {
3088   Assembler::fld_x(as_Address(src));
3089 }
3090 
3091 void MacroAssembler::fldcw(AddressLiteral src) {
3092   Assembler::fldcw(as_Address(src));
3093 }
3094 
3095 void MacroAssembler::pow_exp_core_encoding() {
3096   // kills rax, rcx, rdx
3097   subptr(rsp,sizeof(jdouble));
3098   // computes 2^X. Stack: X ...
3099   // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and
3100   // keep it on the thread's stack to compute 2^int(X) later
3101   // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1)
3102   // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X))
3103   fld_s(0);                 // Stack: X X ...
3104   frndint();                // Stack: int(X) X ...
3105   fsuba(1);                 // Stack: int(X) X-int(X) ...
3106   fistp_s(Address(rsp,0));  // move int(X) as integer to thread's stack. Stack: X-int(X) ...
3107   f2xm1();                  // Stack: 2^(X-int(X))-1 ...
3108   fld1();                   // Stack: 1 2^(X-int(X))-1 ...
3109   faddp(1);                 // Stack: 2^(X-int(X))
3110   // computes 2^(int(X)): add exponent bias (1023) to int(X), then
3111   // shift int(X)+1023 to exponent position.
3112   // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11
3113   // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent
3114   // values so detect them and set result to NaN.
3115   movl(rax,Address(rsp,0));
3116   movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding
3117   addl(rax, 1023);
3118   movl(rdx,rax);
3119   shll(rax,20);
3120   // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN.
3121   addl(rdx,1);
3122   // Check that 1 < int(X)+1023+1 < 2048
3123   // in 3 steps:
3124   // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048
3125   // 2- (int(X)+1023+1)&-2048 != 0
3126   // 3- (int(X)+1023+1)&-2048 != 1
3127   // Do 2- first because addl just updated the flags.
3128   cmov32(Assembler::equal,rax,rcx);
3129   cmpl(rdx,1);
3130   cmov32(Assembler::equal,rax,rcx);
3131   testl(rdx,rcx);
3132   cmov32(Assembler::notEqual,rax,rcx);
3133   movl(Address(rsp,4),rax);
3134   movl(Address(rsp,0),0);
3135   fmul_d(Address(rsp,0));   // Stack: 2^X ...
3136   addptr(rsp,sizeof(jdouble));
3137 }
3138 
3139 void MacroAssembler::increase_precision() {
3140   subptr(rsp, BytesPerWord);
3141   fnstcw(Address(rsp, 0));
3142   movl(rax, Address(rsp, 0));
3143   orl(rax, 0x300);
3144   push(rax);
3145   fldcw(Address(rsp, 0));
3146   pop(rax);
3147 }
3148 
3149 void MacroAssembler::restore_precision() {
3150   fldcw(Address(rsp, 0));
3151   addptr(rsp, BytesPerWord);
3152 }
3153 
3154 void MacroAssembler::fast_pow() {
3155   // computes X^Y = 2^(Y * log2(X))
3156   // if fast computation is not possible, result is NaN. Requires
3157   // fallback from user of this macro.
3158   // increase precision for intermediate steps of the computation
3159   increase_precision();
3160   fyl2x();                 // Stack: (Y*log2(X)) ...
3161   pow_exp_core_encoding(); // Stack: exp(X) ...
3162   restore_precision();
3163 }
3164 
3165 void MacroAssembler::fast_exp() {
3166   // computes exp(X) = 2^(X * log2(e))
3167   // if fast computation is not possible, result is NaN. Requires
3168   // fallback from user of this macro.
3169   // increase precision for intermediate steps of the computation
3170   increase_precision();
3171   fldl2e();                // Stack: log2(e) X ...
3172   fmulp(1);                // Stack: (X*log2(e)) ...
3173   pow_exp_core_encoding(); // Stack: exp(X) ...
3174   restore_precision();
3175 }
3176 
3177 void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) {
3178   // kills rax, rcx, rdx
3179   // pow and exp needs 2 extra registers on the fpu stack.
3180   Label slow_case, done;
3181   Register tmp = noreg;
3182   if (!VM_Version::supports_cmov()) {
3183     // fcmp needs a temporary so preserve rdx,
3184     tmp = rdx;
3185   }
3186   Register tmp2 = rax;
3187   Register tmp3 = rcx;
3188 
3189   if (is_exp) {
3190     // Stack: X
3191     fld_s(0);                   // duplicate argument for runtime call. Stack: X X
3192     fast_exp();                 // Stack: exp(X) X
3193     fcmp(tmp, 0, false, false); // Stack: exp(X) X
3194     // exp(X) not equal to itself: exp(X) is NaN go to slow case.
3195     jcc(Assembler::parity, slow_case);
3196     // get rid of duplicate argument. Stack: exp(X)
3197     if (num_fpu_regs_in_use > 0) {
3198       fxch();
3199       fpop();
3200     } else {
3201       ffree(1);
3202     }
3203     jmp(done);
3204   } else {
3205     // Stack: X Y
3206     Label x_negative, y_odd;
3207 
3208     fldz();                     // Stack: 0 X Y
3209     fcmp(tmp, 1, true, false);  // Stack: X Y
3210     jcc(Assembler::above, x_negative);
3211 
3212     // X >= 0
3213 
3214     fld_s(1);                   // duplicate arguments for runtime call. Stack: Y X Y
3215     fld_s(1);                   // Stack: X Y X Y
3216     fast_pow();                 // Stack: X^Y X Y
3217     fcmp(tmp, 0, false, false); // Stack: X^Y X Y
3218     // X^Y not equal to itself: X^Y is NaN go to slow case.
3219     jcc(Assembler::parity, slow_case);
3220     // get rid of duplicate arguments. Stack: X^Y
3221     if (num_fpu_regs_in_use > 0) {
3222       fxch(); fpop();
3223       fxch(); fpop();
3224     } else {
3225       ffree(2);
3226       ffree(1);
3227     }
3228     jmp(done);
3229 
3230     // X <= 0
3231     bind(x_negative);
3232 
3233     fld_s(1);                   // Stack: Y X Y
3234     frndint();                  // Stack: int(Y) X Y
3235     fcmp(tmp, 2, false, false); // Stack: int(Y) X Y
3236     jcc(Assembler::notEqual, slow_case);
3237 
3238     subptr(rsp, 8);
3239 
3240     // For X^Y, when X < 0, Y has to be an integer and the final
3241     // result depends on whether it's odd or even. We just checked
3242     // that int(Y) == Y.  We move int(Y) to gp registers as a 64 bit
3243     // integer to test its parity. If int(Y) is huge and doesn't fit
3244     // in the 64 bit integer range, the integer indefinite value will
3245     // end up in the gp registers. Huge numbers are all even, the
3246     // integer indefinite number is even so it's fine.
3247 
3248 #ifdef ASSERT
3249     // Let's check we don't end up with an integer indefinite number
3250     // when not expected. First test for huge numbers: check whether
3251     // int(Y)+1 == int(Y) which is true for very large numbers and
3252     // those are all even. A 64 bit integer is guaranteed to not
3253     // overflow for numbers where y+1 != y (when precision is set to
3254     // double precision).
3255     Label y_not_huge;
3256 
3257     fld1();                     // Stack: 1 int(Y) X Y
3258     fadd(1);                    // Stack: 1+int(Y) int(Y) X Y
3259 
3260 #ifdef _LP64
3261     // trip to memory to force the precision down from double extended
3262     // precision
3263     fstp_d(Address(rsp, 0));
3264     fld_d(Address(rsp, 0));
3265 #endif
3266 
3267     fcmp(tmp, 1, true, false);  // Stack: int(Y) X Y
3268 #endif
3269 
3270     // move int(Y) as 64 bit integer to thread's stack
3271     fistp_d(Address(rsp,0));    // Stack: X Y
3272 
3273 #ifdef ASSERT
3274     jcc(Assembler::notEqual, y_not_huge);
3275 
3276     // Y is huge so we know it's even. It may not fit in a 64 bit
3277     // integer and we don't want the debug code below to see the
3278     // integer indefinite value so overwrite int(Y) on the thread's
3279     // stack with 0.
3280     movl(Address(rsp, 0), 0);
3281     movl(Address(rsp, 4), 0);
3282 
3283     bind(y_not_huge);
3284 #endif
3285 
3286     fld_s(1);                   // duplicate arguments for runtime call. Stack: Y X Y
3287     fld_s(1);                   // Stack: X Y X Y
3288     fabs();                     // Stack: abs(X) Y X Y
3289     fast_pow();                 // Stack: abs(X)^Y X Y
3290     fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y
3291     // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case.
3292 
3293     pop(tmp2);
3294     NOT_LP64(pop(tmp3));
3295     jcc(Assembler::parity, slow_case);
3296 
3297 #ifdef ASSERT
3298     // Check that int(Y) is not integer indefinite value (int
3299     // overflow). Shouldn't happen because for values that would
3300     // overflow, 1+int(Y)==Y which was tested earlier.
3301 #ifndef _LP64
3302     {
3303       Label integer;
3304       testl(tmp2, tmp2);
3305       jcc(Assembler::notZero, integer);
3306       cmpl(tmp3, 0x80000000);
3307       jcc(Assembler::notZero, integer);
3308       STOP("integer indefinite value shouldn't be seen here");
3309       bind(integer);
3310     }
3311 #else
3312     {
3313       Label integer;
3314       mov(tmp3, tmp2); // preserve tmp2 for parity check below
3315       shlq(tmp3, 1);
3316       jcc(Assembler::carryClear, integer);
3317       jcc(Assembler::notZero, integer);
3318       STOP("integer indefinite value shouldn't be seen here");
3319       bind(integer);
3320     }
3321 #endif
3322 #endif
3323 
3324     // get rid of duplicate arguments. Stack: X^Y
3325     if (num_fpu_regs_in_use > 0) {
3326       fxch(); fpop();
3327       fxch(); fpop();
3328     } else {
3329       ffree(2);
3330       ffree(1);
3331     }
3332 
3333     testl(tmp2, 1);
3334     jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y
3335     // X <= 0, Y even: X^Y = -abs(X)^Y
3336 
3337     fchs();                     // Stack: -abs(X)^Y Y
3338     jmp(done);
3339   }
3340 
3341   // slow case: runtime call
3342   bind(slow_case);
3343 
3344   fpop();                       // pop incorrect result or int(Y)
3345 
3346   fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow),
3347                       is_exp ? 1 : 2, num_fpu_regs_in_use);
3348 
3349   // Come here with result in F-TOS
3350   bind(done);
3351 }
3352 
3353 void MacroAssembler::fpop() {
3354   ffree();
3355   fincstp();
3356 }
3357 
3358 void MacroAssembler::fremr(Register tmp) {
3359   save_rax(tmp);
3360   { Label L;
3361     bind(L);
3362     fprem();
3363     fwait(); fnstsw_ax();
3364 #ifdef _LP64
3365     testl(rax, 0x400);
3366     jcc(Assembler::notEqual, L);
3367 #else
3368     sahf();
3369     jcc(Assembler::parity, L);
3370 #endif // _LP64
3371   }
3372   restore_rax(tmp);
3373   // Result is in ST0.
3374   // Note: fxch & fpop to get rid of ST1
3375   // (otherwise FPU stack could overflow eventually)
3376   fxch(1);
3377   fpop();
3378 }
3379 
3380 
3381 void MacroAssembler::incrementl(AddressLiteral dst) {
3382   if (reachable(dst)) {
3383     incrementl(as_Address(dst));
3384   } else {
3385     lea(rscratch1, dst);
3386     incrementl(Address(rscratch1, 0));
3387   }
3388 }
3389 
3390 void MacroAssembler::incrementl(ArrayAddress dst) {
3391   incrementl(as_Address(dst));
3392 }
3393 
3394 void MacroAssembler::incrementl(Register reg, int value) {
3395   if (value == min_jint) {addl(reg, value) ; return; }
3396   if (value <  0) { decrementl(reg, -value); return; }
3397   if (value == 0) {                        ; return; }
3398   if (value == 1 && UseIncDec) { incl(reg) ; return; }
3399   /* else */      { addl(reg, value)       ; return; }
3400 }
3401 
3402 void MacroAssembler::incrementl(Address dst, int value) {
3403   if (value == min_jint) {addl(dst, value) ; return; }
3404   if (value <  0) { decrementl(dst, -value); return; }
3405   if (value == 0) {                        ; return; }
3406   if (value == 1 && UseIncDec) { incl(dst) ; return; }
3407   /* else */      { addl(dst, value)       ; return; }
3408 }
3409 
3410 void MacroAssembler::jump(AddressLiteral dst) {
3411   if (reachable(dst)) {
3412     jmp_literal(dst.target(), dst.rspec());
3413   } else {
3414     lea(rscratch1, dst);
3415     jmp(rscratch1);
3416   }
3417 }
3418 
3419 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3420   if (reachable(dst)) {
3421     InstructionMark im(this);
3422     relocate(dst.reloc());
3423     const int short_size = 2;
3424     const int long_size = 6;
3425     int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3426     if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3427       // 0111 tttn #8-bit disp
3428       emit_int8(0x70 | cc);
3429       emit_int8((offs - short_size) & 0xFF);
3430     } else {
3431       // 0000 1111 1000 tttn #32-bit disp
3432       emit_int8(0x0F);
3433       emit_int8((unsigned char)(0x80 | cc));
3434       emit_int32(offs - long_size);
3435     }
3436   } else {
3437 #ifdef ASSERT
3438     warning("reversing conditional branch");
3439 #endif /* ASSERT */
3440     Label skip;
3441     jccb(reverse[cc], skip);
3442     lea(rscratch1, dst);
3443     Assembler::jmp(rscratch1);
3444     bind(skip);
3445   }
3446 }
3447 
3448 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3449   if (reachable(src)) {
3450     Assembler::ldmxcsr(as_Address(src));
3451   } else {
3452     lea(rscratch1, src);
3453     Assembler::ldmxcsr(Address(rscratch1, 0));
3454   }
3455 }
3456 
3457 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3458   int off;
3459   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3460     off = offset();
3461     movsbl(dst, src); // movsxb
3462   } else {
3463     off = load_unsigned_byte(dst, src);
3464     shll(dst, 24);
3465     sarl(dst, 24);
3466   }
3467   return off;
3468 }
3469 
3470 // Note: load_signed_short used to be called load_signed_word.
3471 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3472 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3473 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3474 int MacroAssembler::load_signed_short(Register dst, Address src) {
3475   int off;
3476   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3477     // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3478     // version but this is what 64bit has always done. This seems to imply
3479     // that users are only using 32bits worth.
3480     off = offset();
3481     movswl(dst, src); // movsxw
3482   } else {
3483     off = load_unsigned_short(dst, src);
3484     shll(dst, 16);
3485     sarl(dst, 16);
3486   }
3487   return off;
3488 }
3489 
3490 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3491   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3492   // and "3.9 Partial Register Penalties", p. 22).
3493   int off;
3494   if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3495     off = offset();
3496     movzbl(dst, src); // movzxb
3497   } else {
3498     xorl(dst, dst);
3499     off = offset();
3500     movb(dst, src);
3501   }
3502   return off;
3503 }
3504 
3505 // Note: load_unsigned_short used to be called load_unsigned_word.
3506 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3507   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3508   // and "3.9 Partial Register Penalties", p. 22).
3509   int off;
3510   if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3511     off = offset();
3512     movzwl(dst, src); // movzxw
3513   } else {
3514     xorl(dst, dst);
3515     off = offset();
3516     movw(dst, src);
3517   }
3518   return off;
3519 }
3520 
3521 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3522   switch (size_in_bytes) {
3523 #ifndef _LP64
3524   case  8:
3525     assert(dst2 != noreg, "second dest register required");
3526     movl(dst,  src);
3527     movl(dst2, src.plus_disp(BytesPerInt));
3528     break;
3529 #else
3530   case  8:  movq(dst, src); break;
3531 #endif
3532   case  4:  movl(dst, src); break;
3533   case  2:  is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3534   case  1:  is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3535   default:  ShouldNotReachHere();
3536   }
3537 }
3538 
3539 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3540   switch (size_in_bytes) {
3541 #ifndef _LP64
3542   case  8:
3543     assert(src2 != noreg, "second source register required");
3544     movl(dst,                        src);
3545     movl(dst.plus_disp(BytesPerInt), src2);
3546     break;
3547 #else
3548   case  8:  movq(dst, src); break;
3549 #endif
3550   case  4:  movl(dst, src); break;
3551   case  2:  movw(dst, src); break;
3552   case  1:  movb(dst, src); break;
3553   default:  ShouldNotReachHere();
3554   }
3555 }
3556 
3557 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3558   if (reachable(dst)) {
3559     movl(as_Address(dst), src);
3560   } else {
3561     lea(rscratch1, dst);
3562     movl(Address(rscratch1, 0), src);
3563   }
3564 }
3565 
3566 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3567   if (reachable(src)) {
3568     movl(dst, as_Address(src));
3569   } else {
3570     lea(rscratch1, src);
3571     movl(dst, Address(rscratch1, 0));
3572   }
3573 }
3574 
3575 // C++ bool manipulation
3576 
3577 void MacroAssembler::movbool(Register dst, Address src) {
3578   if(sizeof(bool) == 1)
3579     movb(dst, src);
3580   else if(sizeof(bool) == 2)
3581     movw(dst, src);
3582   else if(sizeof(bool) == 4)
3583     movl(dst, src);
3584   else
3585     // unsupported
3586     ShouldNotReachHere();
3587 }
3588 
3589 void MacroAssembler::movbool(Address dst, bool boolconst) {
3590   if(sizeof(bool) == 1)
3591     movb(dst, (int) boolconst);
3592   else if(sizeof(bool) == 2)
3593     movw(dst, (int) boolconst);
3594   else if(sizeof(bool) == 4)
3595     movl(dst, (int) boolconst);
3596   else
3597     // unsupported
3598     ShouldNotReachHere();
3599 }
3600 
3601 void MacroAssembler::movbool(Address dst, Register src) {
3602   if(sizeof(bool) == 1)
3603     movb(dst, src);
3604   else if(sizeof(bool) == 2)
3605     movw(dst, src);
3606   else if(sizeof(bool) == 4)
3607     movl(dst, src);
3608   else
3609     // unsupported
3610     ShouldNotReachHere();
3611 }
3612 
3613 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3614   movb(as_Address(dst), src);
3615 }
3616 
3617 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3618   if (reachable(src)) {
3619     movdl(dst, as_Address(src));
3620   } else {
3621     lea(rscratch1, src);
3622     movdl(dst, Address(rscratch1, 0));
3623   }
3624 }
3625 
3626 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3627   if (reachable(src)) {
3628     movq(dst, as_Address(src));
3629   } else {
3630     lea(rscratch1, src);
3631     movq(dst, Address(rscratch1, 0));
3632   }
3633 }
3634 
3635 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3636   if (reachable(src)) {
3637     if (UseXmmLoadAndClearUpper) {
3638       movsd (dst, as_Address(src));
3639     } else {
3640       movlpd(dst, as_Address(src));
3641     }
3642   } else {
3643     lea(rscratch1, src);
3644     if (UseXmmLoadAndClearUpper) {
3645       movsd (dst, Address(rscratch1, 0));
3646     } else {
3647       movlpd(dst, Address(rscratch1, 0));
3648     }
3649   }
3650 }
3651 
3652 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3653   if (reachable(src)) {
3654     movss(dst, as_Address(src));
3655   } else {
3656     lea(rscratch1, src);
3657     movss(dst, Address(rscratch1, 0));
3658   }
3659 }
3660 
3661 void MacroAssembler::movptr(Register dst, Register src) {
3662   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3663 }
3664 
3665 void MacroAssembler::movptr(Register dst, Address src) {
3666   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3667 }
3668 
3669 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3670 void MacroAssembler::movptr(Register dst, intptr_t src) {
3671   LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3672 }
3673 
3674 void MacroAssembler::movptr(Address dst, Register src) {
3675   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3676 }
3677 
3678 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
3679   if (reachable(src)) {
3680     Assembler::movdqu(dst, as_Address(src));
3681   } else {
3682     lea(rscratch1, src);
3683     Assembler::movdqu(dst, Address(rscratch1, 0));
3684   }
3685 }
3686 
3687 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3688   if (reachable(src)) {
3689     Assembler::movdqa(dst, as_Address(src));
3690   } else {
3691     lea(rscratch1, src);
3692     Assembler::movdqa(dst, Address(rscratch1, 0));
3693   }
3694 }
3695 
3696 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3697   if (reachable(src)) {
3698     Assembler::movsd(dst, as_Address(src));
3699   } else {
3700     lea(rscratch1, src);
3701     Assembler::movsd(dst, Address(rscratch1, 0));
3702   }
3703 }
3704 
3705 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3706   if (reachable(src)) {
3707     Assembler::movss(dst, as_Address(src));
3708   } else {
3709     lea(rscratch1, src);
3710     Assembler::movss(dst, Address(rscratch1, 0));
3711   }
3712 }
3713 
3714 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3715   if (reachable(src)) {
3716     Assembler::mulsd(dst, as_Address(src));
3717   } else {
3718     lea(rscratch1, src);
3719     Assembler::mulsd(dst, Address(rscratch1, 0));
3720   }
3721 }
3722 
3723 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3724   if (reachable(src)) {
3725     Assembler::mulss(dst, as_Address(src));
3726   } else {
3727     lea(rscratch1, src);
3728     Assembler::mulss(dst, Address(rscratch1, 0));
3729   }
3730 }
3731 
3732 void MacroAssembler::null_check(Register reg, int offset) {
3733   if (needs_explicit_null_check(offset)) {
3734     // provoke OS NULL exception if reg = NULL by
3735     // accessing M[reg] w/o changing any (non-CC) registers
3736     // NOTE: cmpl is plenty here to provoke a segv
3737     cmpptr(rax, Address(reg, 0));
3738     // Note: should probably use testl(rax, Address(reg, 0));
3739     //       may be shorter code (however, this version of
3740     //       testl needs to be implemented first)
3741   } else {
3742     // nothing to do, (later) access of M[reg + offset]
3743     // will provoke OS NULL exception if reg = NULL
3744   }
3745 }
3746 
3747 void MacroAssembler::os_breakpoint() {
3748   // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3749   // (e.g., MSVC can't call ps() otherwise)
3750   call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3751 }
3752 
3753 void MacroAssembler::pop_CPU_state() {
3754   pop_FPU_state();
3755   pop_IU_state();
3756 }
3757 
3758 void MacroAssembler::pop_FPU_state() {
3759   NOT_LP64(frstor(Address(rsp, 0));)
3760   LP64_ONLY(fxrstor(Address(rsp, 0));)
3761   addptr(rsp, FPUStateSizeInWords * wordSize);
3762 }
3763 
3764 void MacroAssembler::pop_IU_state() {
3765   popa();
3766   LP64_ONLY(addq(rsp, 8));
3767   popf();
3768 }
3769 
3770 // Save Integer and Float state
3771 // Warning: Stack must be 16 byte aligned (64bit)
3772 void MacroAssembler::push_CPU_state() {
3773   push_IU_state();
3774   push_FPU_state();
3775 }
3776 
3777 void MacroAssembler::push_FPU_state() {
3778   subptr(rsp, FPUStateSizeInWords * wordSize);
3779 #ifndef _LP64
3780   fnsave(Address(rsp, 0));
3781   fwait();
3782 #else
3783   fxsave(Address(rsp, 0));
3784 #endif // LP64
3785 }
3786 
3787 void MacroAssembler::push_IU_state() {
3788   // Push flags first because pusha kills them
3789   pushf();
3790   // Make sure rsp stays 16-byte aligned
3791   LP64_ONLY(subq(rsp, 8));
3792   pusha();
3793 }
3794 
3795 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
3796   // determine java_thread register
3797   if (!java_thread->is_valid()) {
3798     java_thread = rdi;
3799     get_thread(java_thread);
3800   }
3801   // we must set sp to zero to clear frame
3802   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3803   if (clear_fp) {
3804     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3805   }
3806 
3807   if (clear_pc)
3808     movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3809 
3810 }
3811 
3812 void MacroAssembler::restore_rax(Register tmp) {
3813   if (tmp == noreg) pop(rax);
3814   else if (tmp != rax) mov(rax, tmp);
3815 }
3816 
3817 void MacroAssembler::round_to(Register reg, int modulus) {
3818   addptr(reg, modulus - 1);
3819   andptr(reg, -modulus);
3820 }
3821 
3822 void MacroAssembler::save_rax(Register tmp) {
3823   if (tmp == noreg) push(rax);
3824   else if (tmp != rax) mov(tmp, rax);
3825 }
3826 
3827 // Write serialization page so VM thread can do a pseudo remote membar.
3828 // We use the current thread pointer to calculate a thread specific
3829 // offset to write to within the page. This minimizes bus traffic
3830 // due to cache line collision.
3831 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3832   movl(tmp, thread);
3833   shrl(tmp, os::get_serialize_page_shift_count());
3834   andl(tmp, (os::vm_page_size() - sizeof(int)));
3835 
3836   Address index(noreg, tmp, Address::times_1);
3837   ExternalAddress page(os::get_memory_serialize_page());
3838 
3839   // Size of store must match masking code above
3840   movl(as_Address(ArrayAddress(page, index)), tmp);
3841 }
3842 
3843 // Calls to C land
3844 //
3845 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3846 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3847 // has to be reset to 0. This is required to allow proper stack traversal.
3848 void MacroAssembler::set_last_Java_frame(Register java_thread,
3849                                          Register last_java_sp,
3850                                          Register last_java_fp,
3851                                          address  last_java_pc) {
3852   // determine java_thread register
3853   if (!java_thread->is_valid()) {
3854     java_thread = rdi;
3855     get_thread(java_thread);
3856   }
3857   // determine last_java_sp register
3858   if (!last_java_sp->is_valid()) {
3859     last_java_sp = rsp;
3860   }
3861 
3862   // last_java_fp is optional
3863 
3864   if (last_java_fp->is_valid()) {
3865     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3866   }
3867 
3868   // last_java_pc is optional
3869 
3870   if (last_java_pc != NULL) {
3871     lea(Address(java_thread,
3872                  JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3873         InternalAddress(last_java_pc));
3874 
3875   }
3876   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3877 }
3878 
3879 void MacroAssembler::shlptr(Register dst, int imm8) {
3880   LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3881 }
3882 
3883 void MacroAssembler::shrptr(Register dst, int imm8) {
3884   LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3885 }
3886 
3887 void MacroAssembler::sign_extend_byte(Register reg) {
3888   if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3889     movsbl(reg, reg); // movsxb
3890   } else {
3891     shll(reg, 24);
3892     sarl(reg, 24);
3893   }
3894 }
3895 
3896 void MacroAssembler::sign_extend_short(Register reg) {
3897   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3898     movswl(reg, reg); // movsxw
3899   } else {
3900     shll(reg, 16);
3901     sarl(reg, 16);
3902   }
3903 }
3904 
3905 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3906   assert(reachable(src), "Address should be reachable");
3907   testl(dst, as_Address(src));
3908 }
3909 
3910 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3911   if (reachable(src)) {
3912     Assembler::sqrtsd(dst, as_Address(src));
3913   } else {
3914     lea(rscratch1, src);
3915     Assembler::sqrtsd(dst, Address(rscratch1, 0));
3916   }
3917 }
3918 
3919 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3920   if (reachable(src)) {
3921     Assembler::sqrtss(dst, as_Address(src));
3922   } else {
3923     lea(rscratch1, src);
3924     Assembler::sqrtss(dst, Address(rscratch1, 0));
3925   }
3926 }
3927 
3928 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3929   if (reachable(src)) {
3930     Assembler::subsd(dst, as_Address(src));
3931   } else {
3932     lea(rscratch1, src);
3933     Assembler::subsd(dst, Address(rscratch1, 0));
3934   }
3935 }
3936 
3937 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3938   if (reachable(src)) {
3939     Assembler::subss(dst, as_Address(src));
3940   } else {
3941     lea(rscratch1, src);
3942     Assembler::subss(dst, Address(rscratch1, 0));
3943   }
3944 }
3945 
3946 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3947   if (reachable(src)) {
3948     Assembler::ucomisd(dst, as_Address(src));
3949   } else {
3950     lea(rscratch1, src);
3951     Assembler::ucomisd(dst, Address(rscratch1, 0));
3952   }
3953 }
3954 
3955 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3956   if (reachable(src)) {
3957     Assembler::ucomiss(dst, as_Address(src));
3958   } else {
3959     lea(rscratch1, src);
3960     Assembler::ucomiss(dst, Address(rscratch1, 0));
3961   }
3962 }
3963 
3964 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
3965   // Used in sign-bit flipping with aligned address.
3966   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3967   if (reachable(src)) {
3968     Assembler::xorpd(dst, as_Address(src));
3969   } else {
3970     lea(rscratch1, src);
3971     Assembler::xorpd(dst, Address(rscratch1, 0));
3972   }
3973 }
3974 
3975 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
3976   // Used in sign-bit flipping with aligned address.
3977   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3978   if (reachable(src)) {
3979     Assembler::xorps(dst, as_Address(src));
3980   } else {
3981     lea(rscratch1, src);
3982     Assembler::xorps(dst, Address(rscratch1, 0));
3983   }
3984 }
3985 
3986 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3987   // Used in sign-bit flipping with aligned address.
3988   bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3989   assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3990   if (reachable(src)) {
3991     Assembler::pshufb(dst, as_Address(src));
3992   } else {
3993     lea(rscratch1, src);
3994     Assembler::pshufb(dst, Address(rscratch1, 0));
3995   }
3996 }
3997 
3998 // AVX 3-operands instructions
3999 
4000 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4001   if (reachable(src)) {
4002     vaddsd(dst, nds, as_Address(src));
4003   } else {
4004     lea(rscratch1, src);
4005     vaddsd(dst, nds, Address(rscratch1, 0));
4006   }
4007 }
4008 
4009 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4010   if (reachable(src)) {
4011     vaddss(dst, nds, as_Address(src));
4012   } else {
4013     lea(rscratch1, src);
4014     vaddss(dst, nds, Address(rscratch1, 0));
4015   }
4016 }
4017 
4018 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4019   if (reachable(src)) {
4020     vandpd(dst, nds, as_Address(src), vector256);
4021   } else {
4022     lea(rscratch1, src);
4023     vandpd(dst, nds, Address(rscratch1, 0), vector256);
4024   }
4025 }
4026 
4027 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4028   if (reachable(src)) {
4029     vandps(dst, nds, as_Address(src), vector256);
4030   } else {
4031     lea(rscratch1, src);
4032     vandps(dst, nds, Address(rscratch1, 0), vector256);
4033   }
4034 }
4035 
4036 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4037   if (reachable(src)) {
4038     vdivsd(dst, nds, as_Address(src));
4039   } else {
4040     lea(rscratch1, src);
4041     vdivsd(dst, nds, Address(rscratch1, 0));
4042   }
4043 }
4044 
4045 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4046   if (reachable(src)) {
4047     vdivss(dst, nds, as_Address(src));
4048   } else {
4049     lea(rscratch1, src);
4050     vdivss(dst, nds, Address(rscratch1, 0));
4051   }
4052 }
4053 
4054 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4055   if (reachable(src)) {
4056     vmulsd(dst, nds, as_Address(src));
4057   } else {
4058     lea(rscratch1, src);
4059     vmulsd(dst, nds, Address(rscratch1, 0));
4060   }
4061 }
4062 
4063 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4064   if (reachable(src)) {
4065     vmulss(dst, nds, as_Address(src));
4066   } else {
4067     lea(rscratch1, src);
4068     vmulss(dst, nds, Address(rscratch1, 0));
4069   }
4070 }
4071 
4072 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4073   if (reachable(src)) {
4074     vsubsd(dst, nds, as_Address(src));
4075   } else {
4076     lea(rscratch1, src);
4077     vsubsd(dst, nds, Address(rscratch1, 0));
4078   }
4079 }
4080 
4081 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4082   if (reachable(src)) {
4083     vsubss(dst, nds, as_Address(src));
4084   } else {
4085     lea(rscratch1, src);
4086     vsubss(dst, nds, Address(rscratch1, 0));
4087   }
4088 }
4089 
4090 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4091   if (reachable(src)) {
4092     vxorpd(dst, nds, as_Address(src), vector256);
4093   } else {
4094     lea(rscratch1, src);
4095     vxorpd(dst, nds, Address(rscratch1, 0), vector256);
4096   }
4097 }
4098 
4099 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4100   if (reachable(src)) {
4101     vxorps(dst, nds, as_Address(src), vector256);
4102   } else {
4103     lea(rscratch1, src);
4104     vxorps(dst, nds, Address(rscratch1, 0), vector256);
4105   }
4106 }
4107 
4108 
4109 //////////////////////////////////////////////////////////////////////////////////
4110 #if INCLUDE_ALL_GCS
4111 
4112 void MacroAssembler::g1_write_barrier_pre(Register obj,
4113                                           Register pre_val,
4114                                           Register thread,
4115                                           Register tmp,
4116                                           bool tosca_live,
4117                                           bool expand_call) {
4118 
4119   // If expand_call is true then we expand the call_VM_leaf macro
4120   // directly to skip generating the check by
4121   // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
4122 
4123 #ifdef _LP64
4124   assert(thread == r15_thread, "must be");
4125 #endif // _LP64
4126 
4127   Label done;
4128   Label runtime;
4129 
4130   assert(pre_val != noreg, "check this code");
4131 
4132   if (obj != noreg) {
4133     assert_different_registers(obj, pre_val, tmp);
4134     assert(pre_val != rax, "check this code");
4135   }
4136 
4137   Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4138                                        PtrQueue::byte_offset_of_active()));
4139   Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4140                                        PtrQueue::byte_offset_of_index()));
4141   Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4142                                        PtrQueue::byte_offset_of_buf()));
4143 
4144 
4145   // Is marking active?
4146   if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4147     cmpl(in_progress, 0);
4148   } else {
4149     assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
4150     cmpb(in_progress, 0);
4151   }
4152   jcc(Assembler::equal, done);
4153 
4154   // Do we need to load the previous value?
4155   if (obj != noreg) {
4156     load_heap_oop(pre_val, Address(obj, 0));
4157   }
4158 
4159   // Is the previous value null?
4160   cmpptr(pre_val, (int32_t) NULL_WORD);
4161   jcc(Assembler::equal, done);
4162 
4163   // Can we store original value in the thread's buffer?
4164   // Is index == 0?
4165   // (The index field is typed as size_t.)
4166 
4167   movptr(tmp, index);                   // tmp := *index_adr
4168   cmpptr(tmp, 0);                       // tmp == 0?
4169   jcc(Assembler::equal, runtime);       // If yes, goto runtime
4170 
4171   subptr(tmp, wordSize);                // tmp := tmp - wordSize
4172   movptr(index, tmp);                   // *index_adr := tmp
4173   addptr(tmp, buffer);                  // tmp := tmp + *buffer_adr
4174 
4175   // Record the previous value
4176   movptr(Address(tmp, 0), pre_val);
4177   jmp(done);
4178 
4179   bind(runtime);
4180   // save the live input values
4181   if(tosca_live) push(rax);
4182 
4183   if (obj != noreg && obj != rax)
4184     push(obj);
4185 
4186   if (pre_val != rax)
4187     push(pre_val);
4188 
4189   // Calling the runtime using the regular call_VM_leaf mechanism generates
4190   // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
4191   // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
4192   //
4193   // If we care generating the pre-barrier without a frame (e.g. in the
4194   // intrinsified Reference.get() routine) then ebp might be pointing to
4195   // the caller frame and so this check will most likely fail at runtime.
4196   //
4197   // Expanding the call directly bypasses the generation of the check.
4198   // So when we do not have have a full interpreter frame on the stack
4199   // expand_call should be passed true.
4200 
4201   NOT_LP64( push(thread); )
4202 
4203   if (expand_call) {
4204     LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
4205     pass_arg1(this, thread);
4206     pass_arg0(this, pre_val);
4207     MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
4208   } else {
4209     call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
4210   }
4211 
4212   NOT_LP64( pop(thread); )
4213 
4214   // save the live input values
4215   if (pre_val != rax)
4216     pop(pre_val);
4217 
4218   if (obj != noreg && obj != rax)
4219     pop(obj);
4220 
4221   if(tosca_live) pop(rax);
4222 
4223   bind(done);
4224 }
4225 
4226 void MacroAssembler::g1_write_barrier_post(Register store_addr,
4227                                            Register new_val,
4228                                            Register thread,
4229                                            Register tmp,
4230                                            Register tmp2) {
4231 #ifdef _LP64
4232   assert(thread == r15_thread, "must be");
4233 #endif // _LP64
4234 
4235   Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4236                                        PtrQueue::byte_offset_of_index()));
4237   Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4238                                        PtrQueue::byte_offset_of_buf()));
4239 
4240   BarrierSet* bs = Universe::heap()->barrier_set();
4241   CardTableModRefBS* ct = (CardTableModRefBS*)bs;
4242   assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4243 
4244   Label done;
4245   Label runtime;
4246 
4247   // Does store cross heap regions?
4248 
4249   movptr(tmp, store_addr);
4250   xorptr(tmp, new_val);
4251   shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
4252   jcc(Assembler::equal, done);
4253 
4254   // crosses regions, storing NULL?
4255 
4256   cmpptr(new_val, (int32_t) NULL_WORD);
4257   jcc(Assembler::equal, done);
4258 
4259   // storing region crossing non-NULL, is card already dirty?
4260 
4261   const Register card_addr = tmp;
4262   const Register cardtable = tmp2;
4263 
4264   movptr(card_addr, store_addr);
4265   shrptr(card_addr, CardTableModRefBS::card_shift);
4266   // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
4267   // a valid address and therefore is not properly handled by the relocation code.
4268   movptr(cardtable, (intptr_t)ct->byte_map_base);
4269   addptr(card_addr, cardtable);
4270 
4271   cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
4272   jcc(Assembler::equal, done);
4273 
4274   membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4275   cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4276   jcc(Assembler::equal, done);
4277 
4278 
4279   // storing a region crossing, non-NULL oop, card is clean.
4280   // dirty card and log.
4281 
4282   movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4283 
4284   cmpl(queue_index, 0);
4285   jcc(Assembler::equal, runtime);
4286   subl(queue_index, wordSize);
4287   movptr(tmp2, buffer);
4288 #ifdef _LP64
4289   movslq(rscratch1, queue_index);
4290   addq(tmp2, rscratch1);
4291   movq(Address(tmp2, 0), card_addr);
4292 #else
4293   addl(tmp2, queue_index);
4294   movl(Address(tmp2, 0), card_addr);
4295 #endif
4296   jmp(done);
4297 
4298   bind(runtime);
4299   // save the live input values
4300   push(store_addr);
4301   push(new_val);
4302 #ifdef _LP64
4303   call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
4304 #else
4305   push(thread);
4306   call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
4307   pop(thread);
4308 #endif
4309   pop(new_val);
4310   pop(store_addr);
4311 
4312   bind(done);
4313 }
4314 
4315 #endif // INCLUDE_ALL_GCS
4316 //////////////////////////////////////////////////////////////////////////////////
4317 
4318 
4319 void MacroAssembler::store_check(Register obj) {
4320   // Does a store check for the oop in register obj. The content of
4321   // register obj is destroyed afterwards.
4322   store_check_part_1(obj);
4323   store_check_part_2(obj);
4324 }
4325 
4326 void MacroAssembler::store_check(Register obj, Address dst) {
4327   store_check(obj);
4328 }
4329 
4330 
4331 // split the store check operation so that other instructions can be scheduled inbetween
4332 void MacroAssembler::store_check_part_1(Register obj) {
4333   BarrierSet* bs = Universe::heap()->barrier_set();
4334   assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4335   shrptr(obj, CardTableModRefBS::card_shift);
4336 }
4337 
4338 void MacroAssembler::store_check_part_2(Register obj) {
4339   BarrierSet* bs = Universe::heap()->barrier_set();
4340   assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4341   CardTableModRefBS* ct = (CardTableModRefBS*)bs;
4342   assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4343 
4344   // The calculation for byte_map_base is as follows:
4345   // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
4346   // So this essentially converts an address to a displacement and it will
4347   // never need to be relocated. On 64bit however the value may be too
4348   // large for a 32bit displacement.
4349   intptr_t disp = (intptr_t) ct->byte_map_base;
4350   if (is_simm32(disp)) {
4351     Address cardtable(noreg, obj, Address::times_1, disp);
4352     movb(cardtable, 0);
4353   } else {
4354     // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
4355     // displacement and done in a single instruction given favorable mapping and a
4356     // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
4357     // entry and that entry is not properly handled by the relocation code.
4358     AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
4359     Address index(noreg, obj, Address::times_1);
4360     movb(as_Address(ArrayAddress(cardtable, index)), 0);
4361   }
4362 }
4363 
4364 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4365   LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4366 }
4367 
4368 // Force generation of a 4 byte immediate value even if it fits into 8bit
4369 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4370   LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4371 }
4372 
4373 void MacroAssembler::subptr(Register dst, Register src) {
4374   LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4375 }
4376 
4377 // C++ bool manipulation
4378 void MacroAssembler::testbool(Register dst) {
4379   if(sizeof(bool) == 1)
4380     testb(dst, 0xff);
4381   else if(sizeof(bool) == 2) {
4382     // testw implementation needed for two byte bools
4383     ShouldNotReachHere();
4384   } else if(sizeof(bool) == 4)
4385     testl(dst, dst);
4386   else
4387     // unsupported
4388     ShouldNotReachHere();
4389 }
4390 
4391 void MacroAssembler::testptr(Register dst, Register src) {
4392   LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4393 }
4394 
4395 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4396 void MacroAssembler::tlab_allocate(Register obj,
4397                                    Register var_size_in_bytes,
4398                                    int con_size_in_bytes,
4399                                    Register t1,
4400                                    Register t2,
4401                                    Label& slow_case) {
4402   assert_different_registers(obj, t1, t2);
4403   assert_different_registers(obj, var_size_in_bytes, t1);
4404   Register end = t2;
4405   Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
4406 
4407   verify_tlab();
4408 
4409   NOT_LP64(get_thread(thread));
4410 
4411   movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
4412   if (var_size_in_bytes == noreg) {
4413     lea(end, Address(obj, con_size_in_bytes));
4414   } else {
4415     lea(end, Address(obj, var_size_in_bytes, Address::times_1));
4416   }
4417   cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
4418   jcc(Assembler::above, slow_case);
4419 
4420   // update the tlab top pointer
4421   movptr(Address(thread, JavaThread::tlab_top_offset()), end);
4422 
4423   // recover var_size_in_bytes if necessary
4424   if (var_size_in_bytes == end) {
4425     subptr(var_size_in_bytes, obj);
4426   }
4427   verify_tlab();
4428 }
4429 
4430 // Preserves rbx, and rdx.
4431 Register MacroAssembler::tlab_refill(Label& retry,
4432                                      Label& try_eden,
4433                                      Label& slow_case) {
4434   Register top = rax;
4435   Register t1  = rcx;
4436   Register t2  = rsi;
4437   Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
4438   assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
4439   Label do_refill, discard_tlab;
4440 
4441   if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
4442     // No allocation in the shared eden.
4443     jmp(slow_case);
4444   }
4445 
4446   NOT_LP64(get_thread(thread_reg));
4447 
4448   movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4449   movptr(t1,  Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4450 
4451   // calculate amount of free space
4452   subptr(t1, top);
4453   shrptr(t1, LogHeapWordSize);
4454 
4455   // Retain tlab and allocate object in shared space if
4456   // the amount free in the tlab is too large to discard.
4457   cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
4458   jcc(Assembler::lessEqual, discard_tlab);
4459 
4460   // Retain
4461   // %%% yuck as movptr...
4462   movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
4463   addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
4464   if (TLABStats) {
4465     // increment number of slow_allocations
4466     addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
4467   }
4468   jmp(try_eden);
4469 
4470   bind(discard_tlab);
4471   if (TLABStats) {
4472     // increment number of refills
4473     addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
4474     // accumulate wastage -- t1 is amount free in tlab
4475     addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
4476   }
4477 
4478   // if tlab is currently allocated (top or end != null) then
4479   // fill [top, end + alignment_reserve) with array object
4480   testptr(top, top);
4481   jcc(Assembler::zero, do_refill);
4482 
4483   // set up the mark word
4484   movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
4485   // set the length to the remaining space
4486   subptr(t1, typeArrayOopDesc::header_size(T_INT));
4487   addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
4488   shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
4489   movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
4490   // set klass to intArrayKlass
4491   // dubious reloc why not an oop reloc?
4492   movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
4493   // store klass last.  concurrent gcs assumes klass length is valid if
4494   // klass field is not null.
4495   store_klass(top, t1);
4496 
4497   movptr(t1, top);
4498   subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4499   incr_allocated_bytes(thread_reg, t1, 0);
4500 
4501   // refill the tlab with an eden allocation
4502   bind(do_refill);
4503   movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4504   shlptr(t1, LogHeapWordSize);
4505   // allocate new tlab, address returned in top
4506   eden_allocate(top, t1, 0, t2, slow_case);
4507 
4508   // Check that t1 was preserved in eden_allocate.
4509 #ifdef ASSERT
4510   if (UseTLAB) {
4511     Label ok;
4512     Register tsize = rsi;
4513     assert_different_registers(tsize, thread_reg, t1);
4514     push(tsize);
4515     movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4516     shlptr(tsize, LogHeapWordSize);
4517     cmpptr(t1, tsize);
4518     jcc(Assembler::equal, ok);
4519     STOP("assert(t1 != tlab size)");
4520     should_not_reach_here();
4521 
4522     bind(ok);
4523     pop(tsize);
4524   }
4525 #endif
4526   movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
4527   movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
4528   addptr(top, t1);
4529   subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
4530   movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
4531   verify_tlab();
4532   jmp(retry);
4533 
4534   return thread_reg; // for use by caller
4535 }
4536 
4537 void MacroAssembler::incr_allocated_bytes(Register thread,
4538                                           Register var_size_in_bytes,
4539                                           int con_size_in_bytes,
4540                                           Register t1) {
4541   if (!thread->is_valid()) {
4542 #ifdef _LP64
4543     thread = r15_thread;
4544 #else
4545     assert(t1->is_valid(), "need temp reg");
4546     thread = t1;
4547     get_thread(thread);
4548 #endif
4549   }
4550 
4551 #ifdef _LP64
4552   if (var_size_in_bytes->is_valid()) {
4553     addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4554   } else {
4555     addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4556   }
4557 #else
4558   if (var_size_in_bytes->is_valid()) {
4559     addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4560   } else {
4561     addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4562   }
4563   adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
4564 #endif
4565 }
4566 
4567 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
4568   pusha();
4569 
4570   // if we are coming from c1, xmm registers may be live
4571   int off = 0;
4572   if (UseSSE == 1)  {
4573     subptr(rsp, sizeof(jdouble)*8);
4574     movflt(Address(rsp,off++*sizeof(jdouble)),xmm0);
4575     movflt(Address(rsp,off++*sizeof(jdouble)),xmm1);
4576     movflt(Address(rsp,off++*sizeof(jdouble)),xmm2);
4577     movflt(Address(rsp,off++*sizeof(jdouble)),xmm3);
4578     movflt(Address(rsp,off++*sizeof(jdouble)),xmm4);
4579     movflt(Address(rsp,off++*sizeof(jdouble)),xmm5);
4580     movflt(Address(rsp,off++*sizeof(jdouble)),xmm6);
4581     movflt(Address(rsp,off++*sizeof(jdouble)),xmm7);
4582   } else if (UseSSE >= 2)  {
4583 #ifdef COMPILER2
4584     if (MaxVectorSize > 16) {
4585       assert(UseAVX > 0, "256bit vectors are supported only with AVX");
4586       // Save upper half of YMM registes
4587       subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4588       vextractf128h(Address(rsp,  0),xmm0);
4589       vextractf128h(Address(rsp, 16),xmm1);
4590       vextractf128h(Address(rsp, 32),xmm2);
4591       vextractf128h(Address(rsp, 48),xmm3);
4592       vextractf128h(Address(rsp, 64),xmm4);
4593       vextractf128h(Address(rsp, 80),xmm5);
4594       vextractf128h(Address(rsp, 96),xmm6);
4595       vextractf128h(Address(rsp,112),xmm7);
4596 #ifdef _LP64
4597       vextractf128h(Address(rsp,128),xmm8);
4598       vextractf128h(Address(rsp,144),xmm9);
4599       vextractf128h(Address(rsp,160),xmm10);
4600       vextractf128h(Address(rsp,176),xmm11);
4601       vextractf128h(Address(rsp,192),xmm12);
4602       vextractf128h(Address(rsp,208),xmm13);
4603       vextractf128h(Address(rsp,224),xmm14);
4604       vextractf128h(Address(rsp,240),xmm15);
4605 #endif
4606     }
4607 #endif
4608     // Save whole 128bit (16 bytes) XMM regiters
4609     subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4610     movdqu(Address(rsp,off++*16),xmm0);
4611     movdqu(Address(rsp,off++*16),xmm1);
4612     movdqu(Address(rsp,off++*16),xmm2);
4613     movdqu(Address(rsp,off++*16),xmm3);
4614     movdqu(Address(rsp,off++*16),xmm4);
4615     movdqu(Address(rsp,off++*16),xmm5);
4616     movdqu(Address(rsp,off++*16),xmm6);
4617     movdqu(Address(rsp,off++*16),xmm7);
4618 #ifdef _LP64
4619     movdqu(Address(rsp,off++*16),xmm8);
4620     movdqu(Address(rsp,off++*16),xmm9);
4621     movdqu(Address(rsp,off++*16),xmm10);
4622     movdqu(Address(rsp,off++*16),xmm11);
4623     movdqu(Address(rsp,off++*16),xmm12);
4624     movdqu(Address(rsp,off++*16),xmm13);
4625     movdqu(Address(rsp,off++*16),xmm14);
4626     movdqu(Address(rsp,off++*16),xmm15);
4627 #endif
4628   }
4629 
4630   // Preserve registers across runtime call
4631   int incoming_argument_and_return_value_offset = -1;
4632   if (num_fpu_regs_in_use > 1) {
4633     // Must preserve all other FPU regs (could alternatively convert
4634     // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
4635     // FPU state, but can not trust C compiler)
4636     NEEDS_CLEANUP;
4637     // NOTE that in this case we also push the incoming argument(s) to
4638     // the stack and restore it later; we also use this stack slot to
4639     // hold the return value from dsin, dcos etc.
4640     for (int i = 0; i < num_fpu_regs_in_use; i++) {
4641       subptr(rsp, sizeof(jdouble));
4642       fstp_d(Address(rsp, 0));
4643     }
4644     incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
4645     for (int i = nb_args-1; i >= 0; i--) {
4646       fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
4647     }
4648   }
4649 
4650   subptr(rsp, nb_args*sizeof(jdouble));
4651   for (int i = 0; i < nb_args; i++) {
4652     fstp_d(Address(rsp, i*sizeof(jdouble)));
4653   }
4654 
4655 #ifdef _LP64
4656   if (nb_args > 0) {
4657     movdbl(xmm0, Address(rsp, 0));
4658   }
4659   if (nb_args > 1) {
4660     movdbl(xmm1, Address(rsp, sizeof(jdouble)));
4661   }
4662   assert(nb_args <= 2, "unsupported number of args");
4663 #endif // _LP64
4664 
4665   // NOTE: we must not use call_VM_leaf here because that requires a
4666   // complete interpreter frame in debug mode -- same bug as 4387334
4667   // MacroAssembler::call_VM_leaf_base is perfectly safe and will
4668   // do proper 64bit abi
4669 
4670   NEEDS_CLEANUP;
4671   // Need to add stack banging before this runtime call if it needs to
4672   // be taken; however, there is no generic stack banging routine at
4673   // the MacroAssembler level
4674 
4675   MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
4676 
4677 #ifdef _LP64
4678   movsd(Address(rsp, 0), xmm0);
4679   fld_d(Address(rsp, 0));
4680 #endif // _LP64
4681   addptr(rsp, sizeof(jdouble) * nb_args);
4682   if (num_fpu_regs_in_use > 1) {
4683     // Must save return value to stack and then restore entire FPU
4684     // stack except incoming arguments
4685     fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
4686     for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
4687       fld_d(Address(rsp, 0));
4688       addptr(rsp, sizeof(jdouble));
4689     }
4690     fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
4691     addptr(rsp, sizeof(jdouble) * nb_args);
4692   }
4693 
4694   off = 0;
4695   if (UseSSE == 1)  {
4696     movflt(xmm0, Address(rsp,off++*sizeof(jdouble)));
4697     movflt(xmm1, Address(rsp,off++*sizeof(jdouble)));
4698     movflt(xmm2, Address(rsp,off++*sizeof(jdouble)));
4699     movflt(xmm3, Address(rsp,off++*sizeof(jdouble)));
4700     movflt(xmm4, Address(rsp,off++*sizeof(jdouble)));
4701     movflt(xmm5, Address(rsp,off++*sizeof(jdouble)));
4702     movflt(xmm6, Address(rsp,off++*sizeof(jdouble)));
4703     movflt(xmm7, Address(rsp,off++*sizeof(jdouble)));
4704     addptr(rsp, sizeof(jdouble)*8);
4705   } else if (UseSSE >= 2)  {
4706     // Restore whole 128bit (16 bytes) XMM regiters
4707     movdqu(xmm0, Address(rsp,off++*16));
4708     movdqu(xmm1, Address(rsp,off++*16));
4709     movdqu(xmm2, Address(rsp,off++*16));
4710     movdqu(xmm3, Address(rsp,off++*16));
4711     movdqu(xmm4, Address(rsp,off++*16));
4712     movdqu(xmm5, Address(rsp,off++*16));
4713     movdqu(xmm6, Address(rsp,off++*16));
4714     movdqu(xmm7, Address(rsp,off++*16));
4715 #ifdef _LP64
4716     movdqu(xmm8, Address(rsp,off++*16));
4717     movdqu(xmm9, Address(rsp,off++*16));
4718     movdqu(xmm10, Address(rsp,off++*16));
4719     movdqu(xmm11, Address(rsp,off++*16));
4720     movdqu(xmm12, Address(rsp,off++*16));
4721     movdqu(xmm13, Address(rsp,off++*16));
4722     movdqu(xmm14, Address(rsp,off++*16));
4723     movdqu(xmm15, Address(rsp,off++*16));
4724 #endif
4725     addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4726 #ifdef COMPILER2
4727     if (MaxVectorSize > 16) {
4728       // Restore upper half of YMM registes.
4729       vinsertf128h(xmm0, Address(rsp,  0));
4730       vinsertf128h(xmm1, Address(rsp, 16));
4731       vinsertf128h(xmm2, Address(rsp, 32));
4732       vinsertf128h(xmm3, Address(rsp, 48));
4733       vinsertf128h(xmm4, Address(rsp, 64));
4734       vinsertf128h(xmm5, Address(rsp, 80));
4735       vinsertf128h(xmm6, Address(rsp, 96));
4736       vinsertf128h(xmm7, Address(rsp,112));
4737 #ifdef _LP64
4738       vinsertf128h(xmm8, Address(rsp,128));
4739       vinsertf128h(xmm9, Address(rsp,144));
4740       vinsertf128h(xmm10, Address(rsp,160));
4741       vinsertf128h(xmm11, Address(rsp,176));
4742       vinsertf128h(xmm12, Address(rsp,192));
4743       vinsertf128h(xmm13, Address(rsp,208));
4744       vinsertf128h(xmm14, Address(rsp,224));
4745       vinsertf128h(xmm15, Address(rsp,240));
4746 #endif
4747       addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4748     }
4749 #endif
4750   }
4751   popa();
4752 }
4753 
4754 static const double     pi_4 =  0.7853981633974483;
4755 
4756 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
4757   // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
4758   // was attempted in this code; unfortunately it appears that the
4759   // switch to 80-bit precision and back causes this to be
4760   // unprofitable compared with simply performing a runtime call if
4761   // the argument is out of the (-pi/4, pi/4) range.
4762 
4763   Register tmp = noreg;
4764   if (!VM_Version::supports_cmov()) {
4765     // fcmp needs a temporary so preserve rbx,
4766     tmp = rbx;
4767     push(tmp);
4768   }
4769 
4770   Label slow_case, done;
4771 
4772   ExternalAddress pi4_adr = (address)&pi_4;
4773   if (reachable(pi4_adr)) {
4774     // x ?<= pi/4
4775     fld_d(pi4_adr);
4776     fld_s(1);                // Stack:  X  PI/4  X
4777     fabs();                  // Stack: |X| PI/4  X
4778     fcmp(tmp);
4779     jcc(Assembler::above, slow_case);
4780 
4781     // fastest case: -pi/4 <= x <= pi/4
4782     switch(trig) {
4783     case 's':
4784       fsin();
4785       break;
4786     case 'c':
4787       fcos();
4788       break;
4789     case 't':
4790       ftan();
4791       break;
4792     default:
4793       assert(false, "bad intrinsic");
4794       break;
4795     }
4796     jmp(done);
4797   }
4798 
4799   // slow case: runtime call
4800   bind(slow_case);
4801 
4802   switch(trig) {
4803   case 's':
4804     {
4805       fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
4806     }
4807     break;
4808   case 'c':
4809     {
4810       fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
4811     }
4812     break;
4813   case 't':
4814     {
4815       fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
4816     }
4817     break;
4818   default:
4819     assert(false, "bad intrinsic");
4820     break;
4821   }
4822 
4823   // Come here with result in F-TOS
4824   bind(done);
4825 
4826   if (tmp != noreg) {
4827     pop(tmp);
4828   }
4829 }
4830 
4831 
4832 // Look up the method for a megamorphic invokeinterface call.
4833 // The target method is determined by <intf_klass, itable_index>.
4834 // The receiver klass is in recv_klass.
4835 // On success, the result will be in method_result, and execution falls through.
4836 // On failure, execution transfers to the given label.
4837 void MacroAssembler::lookup_interface_method(Register recv_klass,
4838                                              Register intf_klass,
4839                                              RegisterOrConstant itable_index,
4840                                              Register method_result,
4841                                              Register scan_temp,
4842                                              Label& L_no_such_interface) {
4843   assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
4844   assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4845          "caller must use same register for non-constant itable index as for method");
4846 
4847   // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4848   int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
4849   int itentry_off = itableMethodEntry::method_offset_in_bytes();
4850   int scan_step   = itableOffsetEntry::size() * wordSize;
4851   int vte_size    = vtableEntry::size() * wordSize;
4852   Address::ScaleFactor times_vte_scale = Address::times_ptr;
4853   assert(vte_size == wordSize, "else adjust times_vte_scale");
4854 
4855   movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
4856 
4857   // %%% Could store the aligned, prescaled offset in the klassoop.
4858   lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4859   if (HeapWordsPerLong > 1) {
4860     // Round up to align_object_offset boundary
4861     // see code for InstanceKlass::start_of_itable!
4862     round_to(scan_temp, BytesPerLong);
4863   }
4864 
4865   // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4866   assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4867   lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4868 
4869   // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4870   //   if (scan->interface() == intf) {
4871   //     result = (klass + scan->offset() + itable_index);
4872   //   }
4873   // }
4874   Label search, found_method;
4875 
4876   for (int peel = 1; peel >= 0; peel--) {
4877     movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4878     cmpptr(intf_klass, method_result);
4879 
4880     if (peel) {
4881       jccb(Assembler::equal, found_method);
4882     } else {
4883       jccb(Assembler::notEqual, search);
4884       // (invert the test to fall through to found_method...)
4885     }
4886 
4887     if (!peel)  break;
4888 
4889     bind(search);
4890 
4891     // Check that the previous entry is non-null.  A null entry means that
4892     // the receiver class doesn't implement the interface, and wasn't the
4893     // same as when the caller was compiled.
4894     testptr(method_result, method_result);
4895     jcc(Assembler::zero, L_no_such_interface);
4896     addptr(scan_temp, scan_step);
4897   }
4898 
4899   bind(found_method);
4900 
4901   // Got a hit.
4902   movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4903   movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4904 }
4905 
4906 
4907 // virtual method calling
4908 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4909                                            RegisterOrConstant vtable_index,
4910                                            Register method_result) {
4911   const int base = InstanceKlass::vtable_start_offset() * wordSize;
4912   assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4913   Address vtable_entry_addr(recv_klass,
4914                             vtable_index, Address::times_ptr,
4915                             base + vtableEntry::method_offset_in_bytes());
4916   movptr(method_result, vtable_entry_addr);
4917 }
4918 
4919 
4920 void MacroAssembler::check_klass_subtype(Register sub_klass,
4921                            Register super_klass,
4922                            Register temp_reg,
4923                            Label& L_success) {
4924   Label L_failure;
4925   check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg,        &L_success, &L_failure, NULL);
4926   check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4927   bind(L_failure);
4928 }
4929 
4930 
4931 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4932                                                    Register super_klass,
4933                                                    Register temp_reg,
4934                                                    Label* L_success,
4935                                                    Label* L_failure,
4936                                                    Label* L_slow_path,
4937                                         RegisterOrConstant super_check_offset) {
4938   assert_different_registers(sub_klass, super_klass, temp_reg);
4939   bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4940   if (super_check_offset.is_register()) {
4941     assert_different_registers(sub_klass, super_klass,
4942                                super_check_offset.as_register());
4943   } else if (must_load_sco) {
4944     assert(temp_reg != noreg, "supply either a temp or a register offset");
4945   }
4946 
4947   Label L_fallthrough;
4948   int label_nulls = 0;
4949   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
4950   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
4951   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4952   assert(label_nulls <= 1, "at most one NULL in the batch");
4953 
4954   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4955   int sco_offset = in_bytes(Klass::super_check_offset_offset());
4956   Address super_check_offset_addr(super_klass, sco_offset);
4957 
4958   // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4959   // range of a jccb.  If this routine grows larger, reconsider at
4960   // least some of these.
4961 #define local_jcc(assembler_cond, label)                                \
4962   if (&(label) == &L_fallthrough)  jccb(assembler_cond, label);         \
4963   else                             jcc( assembler_cond, label) /*omit semi*/
4964 
4965   // Hacked jmp, which may only be used just before L_fallthrough.
4966 #define final_jmp(label)                                                \
4967   if (&(label) == &L_fallthrough) { /*do nothing*/ }                    \
4968   else                            jmp(label)                /*omit semi*/
4969 
4970   // If the pointers are equal, we are done (e.g., String[] elements).
4971   // This self-check enables sharing of secondary supertype arrays among
4972   // non-primary types such as array-of-interface.  Otherwise, each such
4973   // type would need its own customized SSA.
4974   // We move this check to the front of the fast path because many
4975   // type checks are in fact trivially successful in this manner,
4976   // so we get a nicely predicted branch right at the start of the check.
4977   cmpptr(sub_klass, super_klass);
4978   local_jcc(Assembler::equal, *L_success);
4979 
4980   // Check the supertype display:
4981   if (must_load_sco) {
4982     // Positive movl does right thing on LP64.
4983     movl(temp_reg, super_check_offset_addr);
4984     super_check_offset = RegisterOrConstant(temp_reg);
4985   }
4986   Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4987   cmpptr(super_klass, super_check_addr); // load displayed supertype
4988 
4989   // This check has worked decisively for primary supers.
4990   // Secondary supers are sought in the super_cache ('super_cache_addr').
4991   // (Secondary supers are interfaces and very deeply nested subtypes.)
4992   // This works in the same check above because of a tricky aliasing
4993   // between the super_cache and the primary super display elements.
4994   // (The 'super_check_addr' can address either, as the case requires.)
4995   // Note that the cache is updated below if it does not help us find
4996   // what we need immediately.
4997   // So if it was a primary super, we can just fail immediately.
4998   // Otherwise, it's the slow path for us (no success at this point).
4999 
5000   if (super_check_offset.is_register()) {
5001     local_jcc(Assembler::equal, *L_success);
5002     cmpl(super_check_offset.as_register(), sc_offset);
5003     if (L_failure == &L_fallthrough) {
5004       local_jcc(Assembler::equal, *L_slow_path);
5005     } else {
5006       local_jcc(Assembler::notEqual, *L_failure);
5007       final_jmp(*L_slow_path);
5008     }
5009   } else if (super_check_offset.as_constant() == sc_offset) {
5010     // Need a slow path; fast failure is impossible.
5011     if (L_slow_path == &L_fallthrough) {
5012       local_jcc(Assembler::equal, *L_success);
5013     } else {
5014       local_jcc(Assembler::notEqual, *L_slow_path);
5015       final_jmp(*L_success);
5016     }
5017   } else {
5018     // No slow path; it's a fast decision.
5019     if (L_failure == &L_fallthrough) {
5020       local_jcc(Assembler::equal, *L_success);
5021     } else {
5022       local_jcc(Assembler::notEqual, *L_failure);
5023       final_jmp(*L_success);
5024     }
5025   }
5026 
5027   bind(L_fallthrough);
5028 
5029 #undef local_jcc
5030 #undef final_jmp
5031 }
5032 
5033 
5034 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5035                                                    Register super_klass,
5036                                                    Register temp_reg,
5037                                                    Register temp2_reg,
5038                                                    Label* L_success,
5039                                                    Label* L_failure,
5040                                                    bool set_cond_codes) {
5041   assert_different_registers(sub_klass, super_klass, temp_reg);
5042   if (temp2_reg != noreg)
5043     assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5044 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5045 
5046   Label L_fallthrough;
5047   int label_nulls = 0;
5048   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
5049   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
5050   assert(label_nulls <= 1, "at most one NULL in the batch");
5051 
5052   // a couple of useful fields in sub_klass:
5053   int ss_offset = in_bytes(Klass::secondary_supers_offset());
5054   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5055   Address secondary_supers_addr(sub_klass, ss_offset);
5056   Address super_cache_addr(     sub_klass, sc_offset);
5057 
5058   // Do a linear scan of the secondary super-klass chain.
5059   // This code is rarely used, so simplicity is a virtue here.
5060   // The repne_scan instruction uses fixed registers, which we must spill.
5061   // Don't worry too much about pre-existing connections with the input regs.
5062 
5063   assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5064   assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5065 
5066   // Get super_klass value into rax (even if it was in rdi or rcx).
5067   bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5068   if (super_klass != rax || UseCompressedOops) {
5069     if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5070     mov(rax, super_klass);
5071   }
5072   if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5073   if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5074 
5075 #ifndef PRODUCT
5076   int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5077   ExternalAddress pst_counter_addr((address) pst_counter);
5078   NOT_LP64(  incrementl(pst_counter_addr) );
5079   LP64_ONLY( lea(rcx, pst_counter_addr) );
5080   LP64_ONLY( incrementl(Address(rcx, 0)) );
5081 #endif //PRODUCT
5082 
5083   // We will consult the secondary-super array.
5084   movptr(rdi, secondary_supers_addr);
5085   // Load the array length.  (Positive movl does right thing on LP64.)
5086   movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5087   // Skip to start of data.
5088   addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5089 
5090   // Scan RCX words at [RDI] for an occurrence of RAX.
5091   // Set NZ/Z based on last compare.
5092   // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5093   // not change flags (only scas instruction which is repeated sets flags).
5094   // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5095 
5096     testptr(rax,rax); // Set Z = 0
5097     repne_scan();
5098 
5099   // Unspill the temp. registers:
5100   if (pushed_rdi)  pop(rdi);
5101   if (pushed_rcx)  pop(rcx);
5102   if (pushed_rax)  pop(rax);
5103 
5104   if (set_cond_codes) {
5105     // Special hack for the AD files:  rdi is guaranteed non-zero.
5106     assert(!pushed_rdi, "rdi must be left non-NULL");
5107     // Also, the condition codes are properly set Z/NZ on succeed/failure.
5108   }
5109 
5110   if (L_failure == &L_fallthrough)
5111         jccb(Assembler::notEqual, *L_failure);
5112   else  jcc(Assembler::notEqual, *L_failure);
5113 
5114   // Success.  Cache the super we found and proceed in triumph.
5115   movptr(super_cache_addr, super_klass);
5116 
5117   if (L_success != &L_fallthrough) {
5118     jmp(*L_success);
5119   }
5120 
5121 #undef IS_A_TEMP
5122 
5123   bind(L_fallthrough);
5124 }
5125 
5126 
5127 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5128   if (VM_Version::supports_cmov()) {
5129     cmovl(cc, dst, src);
5130   } else {
5131     Label L;
5132     jccb(negate_condition(cc), L);
5133     movl(dst, src);
5134     bind(L);
5135   }
5136 }
5137 
5138 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5139   if (VM_Version::supports_cmov()) {
5140     cmovl(cc, dst, src);
5141   } else {
5142     Label L;
5143     jccb(negate_condition(cc), L);
5144     movl(dst, src);
5145     bind(L);
5146   }
5147 }
5148 
5149 void MacroAssembler::verify_oop(Register reg, const char* s) {
5150   if (!VerifyOops) return;
5151 
5152   // Pass register number to verify_oop_subroutine
5153   const char* b = NULL;
5154   {
5155     ResourceMark rm;
5156     stringStream ss;
5157     ss.print("verify_oop: %s: %s", reg->name(), s);
5158     b = code_string(ss.as_string());
5159   }
5160   BLOCK_COMMENT("verify_oop {");
5161 #ifdef _LP64
5162   push(rscratch1);                    // save r10, trashed by movptr()
5163 #endif
5164   push(rax);                          // save rax,
5165   push(reg);                          // pass register argument
5166   ExternalAddress buffer((address) b);
5167   // avoid using pushptr, as it modifies scratch registers
5168   // and our contract is not to modify anything
5169   movptr(rax, buffer.addr());
5170   push(rax);
5171   // call indirectly to solve generation ordering problem
5172   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5173   call(rax);
5174   // Caller pops the arguments (oop, message) and restores rax, r10
5175   BLOCK_COMMENT("} verify_oop");
5176 }
5177 
5178 
5179 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
5180                                                       Register tmp,
5181                                                       int offset) {
5182   intptr_t value = *delayed_value_addr;
5183   if (value != 0)
5184     return RegisterOrConstant(value + offset);
5185 
5186   // load indirectly to solve generation ordering problem
5187   movptr(tmp, ExternalAddress((address) delayed_value_addr));
5188 
5189 #ifdef ASSERT
5190   { Label L;
5191     testptr(tmp, tmp);
5192     if (WizardMode) {
5193       const char* buf = NULL;
5194       {
5195         ResourceMark rm;
5196         stringStream ss;
5197         ss.print("DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]);
5198         buf = code_string(ss.as_string());
5199       }
5200       jcc(Assembler::notZero, L);
5201       STOP(buf);
5202     } else {
5203       jccb(Assembler::notZero, L);
5204       hlt();
5205     }
5206     bind(L);
5207   }
5208 #endif
5209 
5210   if (offset != 0)
5211     addptr(tmp, offset);
5212 
5213   return RegisterOrConstant(tmp);
5214 }
5215 
5216 
5217 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5218                                          int extra_slot_offset) {
5219   // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5220   int stackElementSize = Interpreter::stackElementSize;
5221   int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5222 #ifdef ASSERT
5223   int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5224   assert(offset1 - offset == stackElementSize, "correct arithmetic");
5225 #endif
5226   Register             scale_reg    = noreg;
5227   Address::ScaleFactor scale_factor = Address::no_scale;
5228   if (arg_slot.is_constant()) {
5229     offset += arg_slot.as_constant() * stackElementSize;
5230   } else {
5231     scale_reg    = arg_slot.as_register();
5232     scale_factor = Address::times(stackElementSize);
5233   }
5234   offset += wordSize;           // return PC is on stack
5235   return Address(rsp, scale_reg, scale_factor, offset);
5236 }
5237 
5238 
5239 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
5240   if (!VerifyOops) return;
5241 
5242   // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
5243   // Pass register number to verify_oop_subroutine
5244   const char* b = NULL;
5245   {
5246     ResourceMark rm;
5247     stringStream ss;
5248     ss.print("verify_oop_addr: %s", s);
5249     b = code_string(ss.as_string());
5250   }
5251 #ifdef _LP64
5252   push(rscratch1);                    // save r10, trashed by movptr()
5253 #endif
5254   push(rax);                          // save rax,
5255   // addr may contain rsp so we will have to adjust it based on the push
5256   // we just did (and on 64 bit we do two pushes)
5257   // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5258   // stores rax into addr which is backwards of what was intended.
5259   if (addr.uses(rsp)) {
5260     lea(rax, addr);
5261     pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5262   } else {
5263     pushptr(addr);
5264   }
5265 
5266   ExternalAddress buffer((address) b);
5267   // pass msg argument
5268   // avoid using pushptr, as it modifies scratch registers
5269   // and our contract is not to modify anything
5270   movptr(rax, buffer.addr());
5271   push(rax);
5272 
5273   // call indirectly to solve generation ordering problem
5274   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5275   call(rax);
5276   // Caller pops the arguments (addr, message) and restores rax, r10.
5277 }
5278 
5279 void MacroAssembler::verify_tlab() {
5280 #ifdef ASSERT
5281   if (UseTLAB && VerifyOops) {
5282     Label next, ok;
5283     Register t1 = rsi;
5284     Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5285 
5286     push(t1);
5287     NOT_LP64(push(thread_reg));
5288     NOT_LP64(get_thread(thread_reg));
5289 
5290     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5291     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5292     jcc(Assembler::aboveEqual, next);
5293     STOP("assert(top >= start)");
5294     should_not_reach_here();
5295 
5296     bind(next);
5297     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5298     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5299     jcc(Assembler::aboveEqual, ok);
5300     STOP("assert(top <= end)");
5301     should_not_reach_here();
5302 
5303     bind(ok);
5304     NOT_LP64(pop(thread_reg));
5305     pop(t1);
5306   }
5307 #endif
5308 }
5309 
5310 class ControlWord {
5311  public:
5312   int32_t _value;
5313 
5314   int  rounding_control() const        { return  (_value >> 10) & 3      ; }
5315   int  precision_control() const       { return  (_value >>  8) & 3      ; }
5316   bool precision() const               { return ((_value >>  5) & 1) != 0; }
5317   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
5318   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
5319   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
5320   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
5321   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
5322 
5323   void print() const {
5324     // rounding control
5325     const char* rc;
5326     switch (rounding_control()) {
5327       case 0: rc = "round near"; break;
5328       case 1: rc = "round down"; break;
5329       case 2: rc = "round up  "; break;
5330       case 3: rc = "chop      "; break;
5331     };
5332     // precision control
5333     const char* pc;
5334     switch (precision_control()) {
5335       case 0: pc = "24 bits "; break;
5336       case 1: pc = "reserved"; break;
5337       case 2: pc = "53 bits "; break;
5338       case 3: pc = "64 bits "; break;
5339     };
5340     // flags
5341     char f[9];
5342     f[0] = ' ';
5343     f[1] = ' ';
5344     f[2] = (precision   ()) ? 'P' : 'p';
5345     f[3] = (underflow   ()) ? 'U' : 'u';
5346     f[4] = (overflow    ()) ? 'O' : 'o';
5347     f[5] = (zero_divide ()) ? 'Z' : 'z';
5348     f[6] = (denormalized()) ? 'D' : 'd';
5349     f[7] = (invalid     ()) ? 'I' : 'i';
5350     f[8] = '\x0';
5351     // output
5352     printf("%04x  masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5353   }
5354 
5355 };
5356 
5357 class StatusWord {
5358  public:
5359   int32_t _value;
5360 
5361   bool busy() const                    { return ((_value >> 15) & 1) != 0; }
5362   bool C3() const                      { return ((_value >> 14) & 1) != 0; }
5363   bool C2() const                      { return ((_value >> 10) & 1) != 0; }
5364   bool C1() const                      { return ((_value >>  9) & 1) != 0; }
5365   bool C0() const                      { return ((_value >>  8) & 1) != 0; }
5366   int  top() const                     { return  (_value >> 11) & 7      ; }
5367   bool error_status() const            { return ((_value >>  7) & 1) != 0; }
5368   bool stack_fault() const             { return ((_value >>  6) & 1) != 0; }
5369   bool precision() const               { return ((_value >>  5) & 1) != 0; }
5370   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
5371   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
5372   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
5373   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
5374   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
5375 
5376   void print() const {
5377     // condition codes
5378     char c[5];
5379     c[0] = (C3()) ? '3' : '-';
5380     c[1] = (C2()) ? '2' : '-';
5381     c[2] = (C1()) ? '1' : '-';
5382     c[3] = (C0()) ? '0' : '-';
5383     c[4] = '\x0';
5384     // flags
5385     char f[9];
5386     f[0] = (error_status()) ? 'E' : '-';
5387     f[1] = (stack_fault ()) ? 'S' : '-';
5388     f[2] = (precision   ()) ? 'P' : '-';
5389     f[3] = (underflow   ()) ? 'U' : '-';
5390     f[4] = (overflow    ()) ? 'O' : '-';
5391     f[5] = (zero_divide ()) ? 'Z' : '-';
5392     f[6] = (denormalized()) ? 'D' : '-';
5393     f[7] = (invalid     ()) ? 'I' : '-';
5394     f[8] = '\x0';
5395     // output
5396     printf("%04x  flags = %s, cc =  %s, top = %d", _value & 0xFFFF, f, c, top());
5397   }
5398 
5399 };
5400 
5401 class TagWord {
5402  public:
5403   int32_t _value;
5404 
5405   int tag_at(int i) const              { return (_value >> (i*2)) & 3; }
5406 
5407   void print() const {
5408     printf("%04x", _value & 0xFFFF);
5409   }
5410 
5411 };
5412 
5413 class FPU_Register {
5414  public:
5415   int32_t _m0;
5416   int32_t _m1;
5417   int16_t _ex;
5418 
5419   bool is_indefinite() const           {
5420     return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5421   }
5422 
5423   void print() const {
5424     char  sign = (_ex < 0) ? '-' : '+';
5425     const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : "   ";
5426     printf("%c%04hx.%08x%08x  %s", sign, _ex, _m1, _m0, kind);
5427   };
5428 
5429 };
5430 
5431 class FPU_State {
5432  public:
5433   enum {
5434     register_size       = 10,
5435     number_of_registers =  8,
5436     register_mask       =  7
5437   };
5438 
5439   ControlWord  _control_word;
5440   StatusWord   _status_word;
5441   TagWord      _tag_word;
5442   int32_t      _error_offset;
5443   int32_t      _error_selector;
5444   int32_t      _data_offset;
5445   int32_t      _data_selector;
5446   int8_t       _register[register_size * number_of_registers];
5447 
5448   int tag_for_st(int i) const          { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5449   FPU_Register* st(int i) const        { return (FPU_Register*)&_register[register_size * i]; }
5450 
5451   const char* tag_as_string(int tag) const {
5452     switch (tag) {
5453       case 0: return "valid";
5454       case 1: return "zero";
5455       case 2: return "special";
5456       case 3: return "empty";
5457     }
5458     ShouldNotReachHere();
5459     return NULL;
5460   }
5461 
5462   void print() const {
5463     // print computation registers
5464     { int t = _status_word.top();
5465       for (int i = 0; i < number_of_registers; i++) {
5466         int j = (i - t) & register_mask;
5467         printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5468         st(j)->print();
5469         printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5470       }
5471     }
5472     printf("\n");
5473     // print control registers
5474     printf("ctrl = "); _control_word.print(); printf("\n");
5475     printf("stat = "); _status_word .print(); printf("\n");
5476     printf("tags = "); _tag_word    .print(); printf("\n");
5477   }
5478 
5479 };
5480 
5481 class Flag_Register {
5482  public:
5483   int32_t _value;
5484 
5485   bool overflow() const                { return ((_value >> 11) & 1) != 0; }
5486   bool direction() const               { return ((_value >> 10) & 1) != 0; }
5487   bool sign() const                    { return ((_value >>  7) & 1) != 0; }
5488   bool zero() const                    { return ((_value >>  6) & 1) != 0; }
5489   bool auxiliary_carry() const         { return ((_value >>  4) & 1) != 0; }
5490   bool parity() const                  { return ((_value >>  2) & 1) != 0; }
5491   bool carry() const                   { return ((_value >>  0) & 1) != 0; }
5492 
5493   void print() const {
5494     // flags
5495     char f[8];
5496     f[0] = (overflow       ()) ? 'O' : '-';
5497     f[1] = (direction      ()) ? 'D' : '-';
5498     f[2] = (sign           ()) ? 'S' : '-';
5499     f[3] = (zero           ()) ? 'Z' : '-';
5500     f[4] = (auxiliary_carry()) ? 'A' : '-';
5501     f[5] = (parity         ()) ? 'P' : '-';
5502     f[6] = (carry          ()) ? 'C' : '-';
5503     f[7] = '\x0';
5504     // output
5505     printf("%08x  flags = %s", _value, f);
5506   }
5507 
5508 };
5509 
5510 class IU_Register {
5511  public:
5512   int32_t _value;
5513 
5514   void print() const {
5515     printf("%08x  %11d", _value, _value);
5516   }
5517 
5518 };
5519 
5520 class IU_State {
5521  public:
5522   Flag_Register _eflags;
5523   IU_Register   _rdi;
5524   IU_Register   _rsi;
5525   IU_Register   _rbp;
5526   IU_Register   _rsp;
5527   IU_Register   _rbx;
5528   IU_Register   _rdx;
5529   IU_Register   _rcx;
5530   IU_Register   _rax;
5531 
5532   void print() const {
5533     // computation registers
5534     printf("rax,  = "); _rax.print(); printf("\n");
5535     printf("rbx,  = "); _rbx.print(); printf("\n");
5536     printf("rcx  = "); _rcx.print(); printf("\n");
5537     printf("rdx  = "); _rdx.print(); printf("\n");
5538     printf("rdi  = "); _rdi.print(); printf("\n");
5539     printf("rsi  = "); _rsi.print(); printf("\n");
5540     printf("rbp,  = "); _rbp.print(); printf("\n");
5541     printf("rsp  = "); _rsp.print(); printf("\n");
5542     printf("\n");
5543     // control registers
5544     printf("flgs = "); _eflags.print(); printf("\n");
5545   }
5546 };
5547 
5548 
5549 class CPU_State {
5550  public:
5551   FPU_State _fpu_state;
5552   IU_State  _iu_state;
5553 
5554   void print() const {
5555     printf("--------------------------------------------------\n");
5556     _iu_state .print();
5557     printf("\n");
5558     _fpu_state.print();
5559     printf("--------------------------------------------------\n");
5560   }
5561 
5562 };
5563 
5564 
5565 static void _print_CPU_state(CPU_State* state) {
5566   state->print();
5567 };
5568 
5569 
5570 void MacroAssembler::print_CPU_state() {
5571   push_CPU_state();
5572   push(rsp);                // pass CPU state
5573   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5574   addptr(rsp, wordSize);       // discard argument
5575   pop_CPU_state();
5576 }
5577 
5578 
5579 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5580   static int counter = 0;
5581   FPU_State* fs = &state->_fpu_state;
5582   counter++;
5583   // For leaf calls, only verify that the top few elements remain empty.
5584   // We only need 1 empty at the top for C2 code.
5585   if( stack_depth < 0 ) {
5586     if( fs->tag_for_st(7) != 3 ) {
5587       printf("FPR7 not empty\n");
5588       state->print();
5589       assert(false, "error");
5590       return false;
5591     }
5592     return true;                // All other stack states do not matter
5593   }
5594 
5595   assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5596          "bad FPU control word");
5597 
5598   // compute stack depth
5599   int i = 0;
5600   while (i < FPU_State::number_of_registers && fs->tag_for_st(i)  < 3) i++;
5601   int d = i;
5602   while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5603   // verify findings
5604   if (i != FPU_State::number_of_registers) {
5605     // stack not contiguous
5606     printf("%s: stack not contiguous at ST%d\n", s, i);
5607     state->print();
5608     assert(false, "error");
5609     return false;
5610   }
5611   // check if computed stack depth corresponds to expected stack depth
5612   if (stack_depth < 0) {
5613     // expected stack depth is -stack_depth or less
5614     if (d > -stack_depth) {
5615       // too many elements on the stack
5616       printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5617       state->print();
5618       assert(false, "error");
5619       return false;
5620     }
5621   } else {
5622     // expected stack depth is stack_depth
5623     if (d != stack_depth) {
5624       // wrong stack depth
5625       printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5626       state->print();
5627       assert(false, "error");
5628       return false;
5629     }
5630   }
5631   // everything is cool
5632   return true;
5633 }
5634 
5635 
5636 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5637   if (!VerifyFPU) return;
5638   push_CPU_state();
5639   push(rsp);                // pass CPU state
5640   ExternalAddress msg((address) s);
5641   // pass message string s
5642   pushptr(msg.addr());
5643   push(stack_depth);        // pass stack depth
5644   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5645   addptr(rsp, 3 * wordSize);   // discard arguments
5646   // check for error
5647   { Label L;
5648     testl(rax, rax);
5649     jcc(Assembler::notZero, L);
5650     int3();                  // break if error condition
5651     bind(L);
5652   }
5653   pop_CPU_state();
5654 }
5655 
5656 void MacroAssembler::restore_cpu_control_state_after_jni() {
5657   // Either restore the MXCSR register after returning from the JNI Call
5658   // or verify that it wasn't changed (with -Xcheck:jni flag).
5659   if (VM_Version::supports_sse()) {
5660     if (RestoreMXCSROnJNICalls) {
5661       ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5662     } else if (CheckJNICalls) {
5663       call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5664     }
5665   }
5666   if (VM_Version::supports_avx()) {
5667     // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5668     vzeroupper();
5669   }
5670 
5671 #ifndef _LP64
5672   // Either restore the x87 floating pointer control word after returning
5673   // from the JNI call or verify that it wasn't changed.
5674   if (CheckJNICalls) {
5675     call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5676   }
5677 #endif // _LP64
5678 }
5679 
5680 
5681 void MacroAssembler::load_klass(Register dst, Register src) {
5682 #ifdef _LP64
5683   if (UseCompressedClassPointers) {
5684     movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5685     decode_klass_not_null(dst);
5686   } else
5687 #endif
5688     movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5689 }
5690 
5691 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5692   load_klass(dst, src);
5693   movptr(dst, Address(dst, Klass::prototype_header_offset()));
5694 }
5695 
5696 void MacroAssembler::store_klass(Register dst, Register src) {
5697 #ifdef _LP64
5698   if (UseCompressedClassPointers) {
5699     encode_klass_not_null(src);
5700     movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5701   } else
5702 #endif
5703     movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5704 }
5705 
5706 void MacroAssembler::load_heap_oop(Register dst, Address src) {
5707 #ifdef _LP64
5708   // FIXME: Must change all places where we try to load the klass.
5709   if (UseCompressedOops) {
5710     movl(dst, src);
5711     decode_heap_oop(dst);
5712   } else
5713 #endif
5714     movptr(dst, src);
5715 }
5716 
5717 // Doesn't do verfication, generates fixed size code
5718 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
5719 #ifdef _LP64
5720   if (UseCompressedOops) {
5721     movl(dst, src);
5722     decode_heap_oop_not_null(dst);
5723   } else
5724 #endif
5725     movptr(dst, src);
5726 }
5727 
5728 void MacroAssembler::store_heap_oop(Address dst, Register src) {
5729 #ifdef _LP64
5730   if (UseCompressedOops) {
5731     assert(!dst.uses(src), "not enough registers");
5732     encode_heap_oop(src);
5733     movl(dst, src);
5734   } else
5735 #endif
5736     movptr(dst, src);
5737 }
5738 
5739 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
5740   assert_different_registers(src1, tmp);
5741 #ifdef _LP64
5742   if (UseCompressedOops) {
5743     bool did_push = false;
5744     if (tmp == noreg) {
5745       tmp = rax;
5746       push(tmp);
5747       did_push = true;
5748       assert(!src2.uses(rsp), "can't push");
5749     }
5750     load_heap_oop(tmp, src2);
5751     cmpptr(src1, tmp);
5752     if (did_push)  pop(tmp);
5753   } else
5754 #endif
5755     cmpptr(src1, src2);
5756 }
5757 
5758 // Used for storing NULLs.
5759 void MacroAssembler::store_heap_oop_null(Address dst) {
5760 #ifdef _LP64
5761   if (UseCompressedOops) {
5762     movl(dst, (int32_t)NULL_WORD);
5763   } else {
5764     movslq(dst, (int32_t)NULL_WORD);
5765   }
5766 #else
5767   movl(dst, (int32_t)NULL_WORD);
5768 #endif
5769 }
5770 
5771 #ifdef _LP64
5772 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5773   if (UseCompressedClassPointers) {
5774     // Store to klass gap in destination
5775     movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5776   }
5777 }
5778 
5779 #ifdef ASSERT
5780 void MacroAssembler::verify_heapbase(const char* msg) {
5781   assert (UseCompressedOops, "should be compressed");
5782   assert (Universe::heap() != NULL, "java heap should be initialized");
5783   if (CheckCompressedOops) {
5784     Label ok;
5785     push(rscratch1); // cmpptr trashes rscratch1
5786     cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5787     jcc(Assembler::equal, ok);
5788     STOP(msg);
5789     bind(ok);
5790     pop(rscratch1);
5791   }
5792 }
5793 #endif
5794 
5795 // Algorithm must match oop.inline.hpp encode_heap_oop.
5796 void MacroAssembler::encode_heap_oop(Register r) {
5797 #ifdef ASSERT
5798   verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5799 #endif
5800   verify_oop(r, "broken oop in encode_heap_oop");
5801   if (Universe::narrow_oop_base() == NULL) {
5802     if (Universe::narrow_oop_shift() != 0) {
5803       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5804       shrq(r, LogMinObjAlignmentInBytes);
5805     }
5806     return;
5807   }
5808   testq(r, r);
5809   cmovq(Assembler::equal, r, r12_heapbase);
5810   subq(r, r12_heapbase);
5811   shrq(r, LogMinObjAlignmentInBytes);
5812 }
5813 
5814 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5815 #ifdef ASSERT
5816   verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5817   if (CheckCompressedOops) {
5818     Label ok;
5819     testq(r, r);
5820     jcc(Assembler::notEqual, ok);
5821     STOP("null oop passed to encode_heap_oop_not_null");
5822     bind(ok);
5823   }
5824 #endif
5825   verify_oop(r, "broken oop in encode_heap_oop_not_null");
5826   if (Universe::narrow_oop_base() != NULL) {
5827     subq(r, r12_heapbase);
5828   }
5829   if (Universe::narrow_oop_shift() != 0) {
5830     assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5831     shrq(r, LogMinObjAlignmentInBytes);
5832   }
5833 }
5834 
5835 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5836 #ifdef ASSERT
5837   verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5838   if (CheckCompressedOops) {
5839     Label ok;
5840     testq(src, src);
5841     jcc(Assembler::notEqual, ok);
5842     STOP("null oop passed to encode_heap_oop_not_null2");
5843     bind(ok);
5844   }
5845 #endif
5846   verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5847   if (dst != src) {
5848     movq(dst, src);
5849   }
5850   if (Universe::narrow_oop_base() != NULL) {
5851     subq(dst, r12_heapbase);
5852   }
5853   if (Universe::narrow_oop_shift() != 0) {
5854     assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5855     shrq(dst, LogMinObjAlignmentInBytes);
5856   }
5857 }
5858 
5859 void  MacroAssembler::decode_heap_oop(Register r) {
5860 #ifdef ASSERT
5861   verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5862 #endif
5863   if (Universe::narrow_oop_base() == NULL) {
5864     if (Universe::narrow_oop_shift() != 0) {
5865       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5866       shlq(r, LogMinObjAlignmentInBytes);
5867     }
5868   } else {
5869     Label done;
5870     shlq(r, LogMinObjAlignmentInBytes);
5871     jccb(Assembler::equal, done);
5872     addq(r, r12_heapbase);
5873     bind(done);
5874   }
5875   verify_oop(r, "broken oop in decode_heap_oop");
5876 }
5877 
5878 void  MacroAssembler::decode_heap_oop_not_null(Register r) {
5879   // Note: it will change flags
5880   assert (UseCompressedOops, "should only be used for compressed headers");
5881   assert (Universe::heap() != NULL, "java heap should be initialized");
5882   // Cannot assert, unverified entry point counts instructions (see .ad file)
5883   // vtableStubs also counts instructions in pd_code_size_limit.
5884   // Also do not verify_oop as this is called by verify_oop.
5885   if (Universe::narrow_oop_shift() != 0) {
5886     assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5887     shlq(r, LogMinObjAlignmentInBytes);
5888     if (Universe::narrow_oop_base() != NULL) {
5889       addq(r, r12_heapbase);
5890     }
5891   } else {
5892     assert (Universe::narrow_oop_base() == NULL, "sanity");
5893   }
5894 }
5895 
5896 void  MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5897   // Note: it will change flags
5898   assert (UseCompressedOops, "should only be used for compressed headers");
5899   assert (Universe::heap() != NULL, "java heap should be initialized");
5900   // Cannot assert, unverified entry point counts instructions (see .ad file)
5901   // vtableStubs also counts instructions in pd_code_size_limit.
5902   // Also do not verify_oop as this is called by verify_oop.
5903   if (Universe::narrow_oop_shift() != 0) {
5904     assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5905     if (LogMinObjAlignmentInBytes == Address::times_8) {
5906       leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5907     } else {
5908       if (dst != src) {
5909         movq(dst, src);
5910       }
5911       shlq(dst, LogMinObjAlignmentInBytes);
5912       if (Universe::narrow_oop_base() != NULL) {
5913         addq(dst, r12_heapbase);
5914       }
5915     }
5916   } else {
5917     assert (Universe::narrow_oop_base() == NULL, "sanity");
5918     if (dst != src) {
5919       movq(dst, src);
5920     }
5921   }
5922 }
5923 
5924 void MacroAssembler::encode_klass_not_null(Register r) {
5925   if (Universe::narrow_klass_base() != NULL) {
5926     // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5927     assert(r != r12_heapbase, "Encoding a klass in r12");
5928     mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5929     subq(r, r12_heapbase);
5930   }
5931   if (Universe::narrow_klass_shift() != 0) {
5932     assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5933     shrq(r, LogKlassAlignmentInBytes);
5934   }
5935   if (Universe::narrow_klass_base() != NULL) {
5936     reinit_heapbase();
5937   }
5938 }
5939 
5940 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5941   if (dst == src) {
5942     encode_klass_not_null(src);
5943   } else {
5944     if (Universe::narrow_klass_base() != NULL) {
5945       mov64(dst, (int64_t)Universe::narrow_klass_base());
5946       negq(dst);
5947       addq(dst, src);
5948     } else {
5949       movptr(dst, src);
5950     }
5951     if (Universe::narrow_klass_shift() != 0) {
5952       assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5953       shrq(dst, LogKlassAlignmentInBytes);
5954     }
5955   }
5956 }
5957 
5958 // Function instr_size_for_decode_klass_not_null() counts the instructions
5959 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5960 // when (Universe::heap() != NULL).  Hence, if the instructions they
5961 // generate change, then this method needs to be updated.
5962 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5963   assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5964   if (Universe::narrow_klass_base() != NULL) {
5965     // mov64 + addq + shlq? + mov64  (for reinit_heapbase()).
5966     return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
5967   } else {
5968     // longest load decode klass function, mov64, leaq
5969     return 16;
5970   }
5971 }
5972 
5973 // !!! If the instructions that get generated here change then function
5974 // instr_size_for_decode_klass_not_null() needs to get updated.
5975 void  MacroAssembler::decode_klass_not_null(Register r) {
5976   // Note: it will change flags
5977   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5978   assert(r != r12_heapbase, "Decoding a klass in r12");
5979   // Cannot assert, unverified entry point counts instructions (see .ad file)
5980   // vtableStubs also counts instructions in pd_code_size_limit.
5981   // Also do not verify_oop as this is called by verify_oop.
5982   if (Universe::narrow_klass_shift() != 0) {
5983     assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5984     shlq(r, LogKlassAlignmentInBytes);
5985   }
5986   // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5987   if (Universe::narrow_klass_base() != NULL) {
5988     mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5989     addq(r, r12_heapbase);
5990     reinit_heapbase();
5991   }
5992 }
5993 
5994 void  MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5995   // Note: it will change flags
5996   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5997   if (dst == src) {
5998     decode_klass_not_null(dst);
5999   } else {
6000     // Cannot assert, unverified entry point counts instructions (see .ad file)
6001     // vtableStubs also counts instructions in pd_code_size_limit.
6002     // Also do not verify_oop as this is called by verify_oop.
6003     mov64(dst, (int64_t)Universe::narrow_klass_base());
6004     if (Universe::narrow_klass_shift() != 0) {
6005       assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6006       assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6007       leaq(dst, Address(dst, src, Address::times_8, 0));
6008     } else {
6009       addq(dst, src);
6010     }
6011   }
6012 }
6013 
6014 void  MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6015   assert (UseCompressedOops, "should only be used for compressed headers");
6016   assert (Universe::heap() != NULL, "java heap should be initialized");
6017   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6018   int oop_index = oop_recorder()->find_index(obj);
6019   RelocationHolder rspec = oop_Relocation::spec(oop_index);
6020   mov_narrow_oop(dst, oop_index, rspec);
6021 }
6022 
6023 void  MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6024   assert (UseCompressedOops, "should only be used for compressed headers");
6025   assert (Universe::heap() != NULL, "java heap should be initialized");
6026   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6027   int oop_index = oop_recorder()->find_index(obj);
6028   RelocationHolder rspec = oop_Relocation::spec(oop_index);
6029   mov_narrow_oop(dst, oop_index, rspec);
6030 }
6031 
6032 void  MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6033   assert (UseCompressedClassPointers, "should only be used for compressed headers");
6034   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6035   int klass_index = oop_recorder()->find_index(k);
6036   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6037   mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6038 }
6039 
6040 void  MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6041   assert (UseCompressedClassPointers, "should only be used for compressed headers");
6042   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6043   int klass_index = oop_recorder()->find_index(k);
6044   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6045   mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6046 }
6047 
6048 void  MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6049   assert (UseCompressedOops, "should only be used for compressed headers");
6050   assert (Universe::heap() != NULL, "java heap should be initialized");
6051   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6052   int oop_index = oop_recorder()->find_index(obj);
6053   RelocationHolder rspec = oop_Relocation::spec(oop_index);
6054   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6055 }
6056 
6057 void  MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6058   assert (UseCompressedOops, "should only be used for compressed headers");
6059   assert (Universe::heap() != NULL, "java heap should be initialized");
6060   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6061   int oop_index = oop_recorder()->find_index(obj);
6062   RelocationHolder rspec = oop_Relocation::spec(oop_index);
6063   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6064 }
6065 
6066 void  MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6067   assert (UseCompressedClassPointers, "should only be used for compressed headers");
6068   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6069   int klass_index = oop_recorder()->find_index(k);
6070   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6071   Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6072 }
6073 
6074 void  MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6075   assert (UseCompressedClassPointers, "should only be used for compressed headers");
6076   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6077   int klass_index = oop_recorder()->find_index(k);
6078   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6079   Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6080 }
6081 
6082 void MacroAssembler::reinit_heapbase() {
6083   if (UseCompressedOops || UseCompressedClassPointers) {
6084     if (Universe::heap() != NULL) {
6085       if (Universe::narrow_oop_base() == NULL) {
6086         MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6087       } else {
6088         mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6089       }
6090     } else {
6091       movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6092     }
6093   }
6094 }
6095 
6096 #endif // _LP64
6097 
6098 
6099 // C2 compiled method's prolog code.
6100 void MacroAssembler::verified_entry(int framesize, bool stack_bang, bool fp_mode_24b) {
6101 
6102   // WARNING: Initial instruction MUST be 5 bytes or longer so that
6103   // NativeJump::patch_verified_entry will be able to patch out the entry
6104   // code safely. The push to verify stack depth is ok at 5 bytes,
6105   // the frame allocation can be either 3 or 6 bytes. So if we don't do
6106   // stack bang then we must use the 6 byte frame allocation even if
6107   // we have no frame. :-(
6108 
6109   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6110   // Remove word for return addr
6111   framesize -= wordSize;
6112 
6113   // Calls to C2R adapters often do not accept exceptional returns.
6114   // We require that their callers must bang for them.  But be careful, because
6115   // some VM calls (such as call site linkage) can use several kilobytes of
6116   // stack.  But the stack safety zone should account for that.
6117   // See bugs 4446381, 4468289, 4497237.
6118   if (stack_bang) {
6119     generate_stack_overflow_check(framesize);
6120 
6121     // We always push rbp, so that on return to interpreter rbp, will be
6122     // restored correctly and we can correct the stack.
6123     push(rbp);
6124     // Remove word for ebp
6125     framesize -= wordSize;
6126 
6127     // Create frame
6128     if (framesize) {
6129       subptr(rsp, framesize);
6130     }
6131   } else {
6132     // Create frame (force generation of a 4 byte immediate value)
6133     subptr_imm32(rsp, framesize);
6134 
6135     // Save RBP register now.
6136     framesize -= wordSize;
6137     movptr(Address(rsp, framesize), rbp);
6138   }
6139 
6140   if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6141     framesize -= wordSize;
6142     movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6143   }
6144 
6145 #ifndef _LP64
6146   // If method sets FPU control word do it now
6147   if (fp_mode_24b) {
6148     fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6149   }
6150   if (UseSSE >= 2 && VerifyFPU) {
6151     verify_FPU(0, "FPU stack must be clean on entry");
6152   }
6153 #endif
6154 
6155 #ifdef ASSERT
6156   if (VerifyStackAtCalls) {
6157     Label L;
6158     push(rax);
6159     mov(rax, rsp);
6160     andptr(rax, StackAlignmentInBytes-1);
6161     cmpptr(rax, StackAlignmentInBytes-wordSize);
6162     pop(rax);
6163     jcc(Assembler::equal, L);
6164     STOP("Stack is not properly aligned!");
6165     bind(L);
6166   }
6167 #endif
6168 
6169 }
6170 
6171 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) {
6172   // cnt - number of qwords (8-byte words).
6173   // base - start address, qword aligned.
6174   assert(base==rdi, "base register must be edi for rep stos");
6175   assert(tmp==rax,   "tmp register must be eax for rep stos");
6176   assert(cnt==rcx,   "cnt register must be ecx for rep stos");
6177 
6178   xorptr(tmp, tmp);
6179   if (UseFastStosb) {
6180     shlptr(cnt,3); // convert to number of bytes
6181     rep_stosb();
6182   } else {
6183     NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM
6184     rep_stos();
6185   }
6186 }
6187 
6188 // IndexOf for constant substrings with size >= 8 chars
6189 // which don't need to be loaded through stack.
6190 void MacroAssembler::string_indexofC8(Register str1, Register str2,
6191                                       Register cnt1, Register cnt2,
6192                                       int int_cnt2,  Register result,
6193                                       XMMRegister vec, Register tmp) {
6194   ShortBranchVerifier sbv(this);
6195   assert(UseSSE42Intrinsics, "SSE4.2 is required");
6196 
6197   // This method uses pcmpestri inxtruction with bound registers
6198   //   inputs:
6199   //     xmm - substring
6200   //     rax - substring length (elements count)
6201   //     mem - scanned string
6202   //     rdx - string length (elements count)
6203   //     0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6204   //   outputs:
6205   //     rcx - matched index in string
6206   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6207 
6208   Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
6209         RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
6210         MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
6211 
6212   // Note, inline_string_indexOf() generates checks:
6213   // if (substr.count > string.count) return -1;
6214   // if (substr.count == 0) return 0;
6215   assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars");
6216 
6217   // Load substring.
6218   movdqu(vec, Address(str2, 0));
6219   movl(cnt2, int_cnt2);
6220   movptr(result, str1); // string addr
6221 
6222   if (int_cnt2 > 8) {
6223     jmpb(SCAN_TO_SUBSTR);
6224 
6225     // Reload substr for rescan, this code
6226     // is executed only for large substrings (> 8 chars)
6227     bind(RELOAD_SUBSTR);
6228     movdqu(vec, Address(str2, 0));
6229     negptr(cnt2); // Jumped here with negative cnt2, convert to positive
6230 
6231     bind(RELOAD_STR);
6232     // We came here after the beginning of the substring was
6233     // matched but the rest of it was not so we need to search
6234     // again. Start from the next element after the previous match.
6235 
6236     // cnt2 is number of substring reminding elements and
6237     // cnt1 is number of string reminding elements when cmp failed.
6238     // Restored cnt1 = cnt1 - cnt2 + int_cnt2
6239     subl(cnt1, cnt2);
6240     addl(cnt1, int_cnt2);
6241     movl(cnt2, int_cnt2); // Now restore cnt2
6242 
6243     decrementl(cnt1);     // Shift to next element
6244     cmpl(cnt1, cnt2);
6245     jccb(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
6246 
6247     addptr(result, 2);
6248 
6249   } // (int_cnt2 > 8)
6250 
6251   // Scan string for start of substr in 16-byte vectors
6252   bind(SCAN_TO_SUBSTR);
6253   pcmpestri(vec, Address(result, 0), 0x0d);
6254   jccb(Assembler::below, FOUND_CANDIDATE);   // CF == 1
6255   subl(cnt1, 8);
6256   jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6257   cmpl(cnt1, cnt2);
6258   jccb(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
6259   addptr(result, 16);
6260   jmpb(SCAN_TO_SUBSTR);
6261 
6262   // Found a potential substr
6263   bind(FOUND_CANDIDATE);
6264   // Matched whole vector if first element matched (tmp(rcx) == 0).
6265   if (int_cnt2 == 8) {
6266     jccb(Assembler::overflow, RET_FOUND);    // OF == 1
6267   } else { // int_cnt2 > 8
6268     jccb(Assembler::overflow, FOUND_SUBSTR);
6269   }
6270   // After pcmpestri tmp(rcx) contains matched element index
6271   // Compute start addr of substr
6272   lea(result, Address(result, tmp, Address::times_2));
6273 
6274   // Make sure string is still long enough
6275   subl(cnt1, tmp);
6276   cmpl(cnt1, cnt2);
6277   if (int_cnt2 == 8) {
6278     jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6279   } else { // int_cnt2 > 8
6280     jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
6281   }
6282   // Left less then substring.
6283 
6284   bind(RET_NOT_FOUND);
6285   movl(result, -1);
6286   jmpb(EXIT);
6287 
6288   if (int_cnt2 > 8) {
6289     // This code is optimized for the case when whole substring
6290     // is matched if its head is matched.
6291     bind(MATCH_SUBSTR_HEAD);
6292     pcmpestri(vec, Address(result, 0), 0x0d);
6293     // Reload only string if does not match
6294     jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
6295 
6296     Label CONT_SCAN_SUBSTR;
6297     // Compare the rest of substring (> 8 chars).
6298     bind(FOUND_SUBSTR);
6299     // First 8 chars are already matched.
6300     negptr(cnt2);
6301     addptr(cnt2, 8);
6302 
6303     bind(SCAN_SUBSTR);
6304     subl(cnt1, 8);
6305     cmpl(cnt2, -8); // Do not read beyond substring
6306     jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
6307     // Back-up strings to avoid reading beyond substring:
6308     // cnt1 = cnt1 - cnt2 + 8
6309     addl(cnt1, cnt2); // cnt2 is negative
6310     addl(cnt1, 8);
6311     movl(cnt2, 8); negptr(cnt2);
6312     bind(CONT_SCAN_SUBSTR);
6313     if (int_cnt2 < (int)G) {
6314       movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2));
6315       pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d);
6316     } else {
6317       // calculate index in register to avoid integer overflow (int_cnt2*2)
6318       movl(tmp, int_cnt2);
6319       addptr(tmp, cnt2);
6320       movdqu(vec, Address(str2, tmp, Address::times_2, 0));
6321       pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d);
6322     }
6323     // Need to reload strings pointers if not matched whole vector
6324     jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6325     addptr(cnt2, 8);
6326     jcc(Assembler::negative, SCAN_SUBSTR);
6327     // Fall through if found full substring
6328 
6329   } // (int_cnt2 > 8)
6330 
6331   bind(RET_FOUND);
6332   // Found result if we matched full small substring.
6333   // Compute substr offset
6334   subptr(result, str1);
6335   shrl(result, 1); // index
6336   bind(EXIT);
6337 
6338 } // string_indexofC8
6339 
6340 // Small strings are loaded through stack if they cross page boundary.
6341 void MacroAssembler::string_indexof(Register str1, Register str2,
6342                                     Register cnt1, Register cnt2,
6343                                     int int_cnt2,  Register result,
6344                                     XMMRegister vec, Register tmp) {
6345   ShortBranchVerifier sbv(this);
6346   assert(UseSSE42Intrinsics, "SSE4.2 is required");
6347   //
6348   // int_cnt2 is length of small (< 8 chars) constant substring
6349   // or (-1) for non constant substring in which case its length
6350   // is in cnt2 register.
6351   //
6352   // Note, inline_string_indexOf() generates checks:
6353   // if (substr.count > string.count) return -1;
6354   // if (substr.count == 0) return 0;
6355   //
6356   assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0");
6357 
6358   // This method uses pcmpestri inxtruction with bound registers
6359   //   inputs:
6360   //     xmm - substring
6361   //     rax - substring length (elements count)
6362   //     mem - scanned string
6363   //     rdx - string length (elements count)
6364   //     0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6365   //   outputs:
6366   //     rcx - matched index in string
6367   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6368 
6369   Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6370         RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6371         FOUND_CANDIDATE;
6372 
6373   { //========================================================
6374     // We don't know where these strings are located
6375     // and we can't read beyond them. Load them through stack.
6376     Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6377 
6378     movptr(tmp, rsp); // save old SP
6379 
6380     if (int_cnt2 > 0) {     // small (< 8 chars) constant substring
6381       if (int_cnt2 == 1) {  // One char
6382         load_unsigned_short(result, Address(str2, 0));
6383         movdl(vec, result); // move 32 bits
6384       } else if (int_cnt2 == 2) { // Two chars
6385         movdl(vec, Address(str2, 0)); // move 32 bits
6386       } else if (int_cnt2 == 4) { // Four chars
6387         movq(vec, Address(str2, 0));  // move 64 bits
6388       } else { // cnt2 = { 3, 5, 6, 7 }
6389         // Array header size is 12 bytes in 32-bit VM
6390         // + 6 bytes for 3 chars == 18 bytes,
6391         // enough space to load vec and shift.
6392         assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6393         movdqu(vec, Address(str2, (int_cnt2*2)-16));
6394         psrldq(vec, 16-(int_cnt2*2));
6395       }
6396     } else { // not constant substring
6397       cmpl(cnt2, 8);
6398       jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6399 
6400       // We can read beyond string if srt+16 does not cross page boundary
6401       // since heaps are aligned and mapped by pages.
6402       assert(os::vm_page_size() < (int)G, "default page should be small");
6403       movl(result, str2); // We need only low 32 bits
6404       andl(result, (os::vm_page_size()-1));
6405       cmpl(result, (os::vm_page_size()-16));
6406       jccb(Assembler::belowEqual, CHECK_STR);
6407 
6408       // Move small strings to stack to allow load 16 bytes into vec.
6409       subptr(rsp, 16);
6410       int stk_offset = wordSize-2;
6411       push(cnt2);
6412 
6413       bind(COPY_SUBSTR);
6414       load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2));
6415       movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6416       decrement(cnt2);
6417       jccb(Assembler::notZero, COPY_SUBSTR);
6418 
6419       pop(cnt2);
6420       movptr(str2, rsp);  // New substring address
6421     } // non constant
6422 
6423     bind(CHECK_STR);
6424     cmpl(cnt1, 8);
6425     jccb(Assembler::aboveEqual, BIG_STRINGS);
6426 
6427     // Check cross page boundary.
6428     movl(result, str1); // We need only low 32 bits
6429     andl(result, (os::vm_page_size()-1));
6430     cmpl(result, (os::vm_page_size()-16));
6431     jccb(Assembler::belowEqual, BIG_STRINGS);
6432 
6433     subptr(rsp, 16);
6434     int stk_offset = -2;
6435     if (int_cnt2 < 0) { // not constant
6436       push(cnt2);
6437       stk_offset += wordSize;
6438     }
6439     movl(cnt2, cnt1);
6440 
6441     bind(COPY_STR);
6442     load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2));
6443     movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6444     decrement(cnt2);
6445     jccb(Assembler::notZero, COPY_STR);
6446 
6447     if (int_cnt2 < 0) { // not constant
6448       pop(cnt2);
6449     }
6450     movptr(str1, rsp);  // New string address
6451 
6452     bind(BIG_STRINGS);
6453     // Load substring.
6454     if (int_cnt2 < 0) { // -1
6455       movdqu(vec, Address(str2, 0));
6456       push(cnt2);       // substr count
6457       push(str2);       // substr addr
6458       push(str1);       // string addr
6459     } else {
6460       // Small (< 8 chars) constant substrings are loaded already.
6461       movl(cnt2, int_cnt2);
6462     }
6463     push(tmp);  // original SP
6464 
6465   } // Finished loading
6466 
6467   //========================================================
6468   // Start search
6469   //
6470 
6471   movptr(result, str1); // string addr
6472 
6473   if (int_cnt2  < 0) {  // Only for non constant substring
6474     jmpb(SCAN_TO_SUBSTR);
6475 
6476     // SP saved at sp+0
6477     // String saved at sp+1*wordSize
6478     // Substr saved at sp+2*wordSize
6479     // Substr count saved at sp+3*wordSize
6480 
6481     // Reload substr for rescan, this code
6482     // is executed only for large substrings (> 8 chars)
6483     bind(RELOAD_SUBSTR);
6484     movptr(str2, Address(rsp, 2*wordSize));
6485     movl(cnt2, Address(rsp, 3*wordSize));
6486     movdqu(vec, Address(str2, 0));
6487     // We came here after the beginning of the substring was
6488     // matched but the rest of it was not so we need to search
6489     // again. Start from the next element after the previous match.
6490     subptr(str1, result); // Restore counter
6491     shrl(str1, 1);
6492     addl(cnt1, str1);
6493     decrementl(cnt1);   // Shift to next element
6494     cmpl(cnt1, cnt2);
6495     jccb(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
6496 
6497     addptr(result, 2);
6498   } // non constant
6499 
6500   // Scan string for start of substr in 16-byte vectors
6501   bind(SCAN_TO_SUBSTR);
6502   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6503   pcmpestri(vec, Address(result, 0), 0x0d);
6504   jccb(Assembler::below, FOUND_CANDIDATE);   // CF == 1
6505   subl(cnt1, 8);
6506   jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6507   cmpl(cnt1, cnt2);
6508   jccb(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
6509   addptr(result, 16);
6510 
6511   bind(ADJUST_STR);
6512   cmpl(cnt1, 8); // Do not read beyond string
6513   jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6514   // Back-up string to avoid reading beyond string.
6515   lea(result, Address(result, cnt1, Address::times_2, -16));
6516   movl(cnt1, 8);
6517   jmpb(SCAN_TO_SUBSTR);
6518 
6519   // Found a potential substr
6520   bind(FOUND_CANDIDATE);
6521   // After pcmpestri tmp(rcx) contains matched element index
6522 
6523   // Make sure string is still long enough
6524   subl(cnt1, tmp);
6525   cmpl(cnt1, cnt2);
6526   jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6527   // Left less then substring.
6528 
6529   bind(RET_NOT_FOUND);
6530   movl(result, -1);
6531   jmpb(CLEANUP);
6532 
6533   bind(FOUND_SUBSTR);
6534   // Compute start addr of substr
6535   lea(result, Address(result, tmp, Address::times_2));
6536 
6537   if (int_cnt2 > 0) { // Constant substring
6538     // Repeat search for small substring (< 8 chars)
6539     // from new point without reloading substring.
6540     // Have to check that we don't read beyond string.
6541     cmpl(tmp, 8-int_cnt2);
6542     jccb(Assembler::greater, ADJUST_STR);
6543     // Fall through if matched whole substring.
6544   } else { // non constant
6545     assert(int_cnt2 == -1, "should be != 0");
6546 
6547     addl(tmp, cnt2);
6548     // Found result if we matched whole substring.
6549     cmpl(tmp, 8);
6550     jccb(Assembler::lessEqual, RET_FOUND);
6551 
6552     // Repeat search for small substring (<= 8 chars)
6553     // from new point 'str1' without reloading substring.
6554     cmpl(cnt2, 8);
6555     // Have to check that we don't read beyond string.
6556     jccb(Assembler::lessEqual, ADJUST_STR);
6557 
6558     Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6559     // Compare the rest of substring (> 8 chars).
6560     movptr(str1, result);
6561 
6562     cmpl(tmp, cnt2);
6563     // First 8 chars are already matched.
6564     jccb(Assembler::equal, CHECK_NEXT);
6565 
6566     bind(SCAN_SUBSTR);
6567     pcmpestri(vec, Address(str1, 0), 0x0d);
6568     // Need to reload strings pointers if not matched whole vector
6569     jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6570 
6571     bind(CHECK_NEXT);
6572     subl(cnt2, 8);
6573     jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6574     addptr(str1, 16);
6575     addptr(str2, 16);
6576     subl(cnt1, 8);
6577     cmpl(cnt2, 8); // Do not read beyond substring
6578     jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6579     // Back-up strings to avoid reading beyond substring.
6580     lea(str2, Address(str2, cnt2, Address::times_2, -16));
6581     lea(str1, Address(str1, cnt2, Address::times_2, -16));
6582     subl(cnt1, cnt2);
6583     movl(cnt2, 8);
6584     addl(cnt1, 8);
6585     bind(CONT_SCAN_SUBSTR);
6586     movdqu(vec, Address(str2, 0));
6587     jmpb(SCAN_SUBSTR);
6588 
6589     bind(RET_FOUND_LONG);
6590     movptr(str1, Address(rsp, wordSize));
6591   } // non constant
6592 
6593   bind(RET_FOUND);
6594   // Compute substr offset
6595   subptr(result, str1);
6596   shrl(result, 1); // index
6597 
6598   bind(CLEANUP);
6599   pop(rsp); // restore SP
6600 
6601 } // string_indexof
6602 
6603 // Compare strings.
6604 void MacroAssembler::string_compare(Register str1, Register str2,
6605                                     Register cnt1, Register cnt2, Register result,
6606                                     XMMRegister vec1) {
6607   ShortBranchVerifier sbv(this);
6608   Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6609 
6610   // Compute the minimum of the string lengths and the
6611   // difference of the string lengths (stack).
6612   // Do the conditional move stuff
6613   movl(result, cnt1);
6614   subl(cnt1, cnt2);
6615   push(cnt1);
6616   cmov32(Assembler::lessEqual, cnt2, result);
6617 
6618   // Is the minimum length zero?
6619   testl(cnt2, cnt2);
6620   jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6621 
6622   // Compare first characters
6623   load_unsigned_short(result, Address(str1, 0));
6624   load_unsigned_short(cnt1, Address(str2, 0));
6625   subl(result, cnt1);
6626   jcc(Assembler::notZero,  POP_LABEL);
6627   cmpl(cnt2, 1);
6628   jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6629 
6630   // Check if the strings start at the same location.
6631   cmpptr(str1, str2);
6632   jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6633 
6634   Address::ScaleFactor scale = Address::times_2;
6635   int stride = 8;
6636 
6637   if (UseAVX >= 2 && UseSSE42Intrinsics) {
6638     Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6639     Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6640     Label COMPARE_TAIL_LONG;
6641     int pcmpmask = 0x19;
6642 
6643     // Setup to compare 16-chars (32-bytes) vectors,
6644     // start from first character again because it has aligned address.
6645     int stride2 = 16;
6646     int adr_stride  = stride  << scale;
6647     int adr_stride2 = stride2 << scale;
6648 
6649     assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6650     // rax and rdx are used by pcmpestri as elements counters
6651     movl(result, cnt2);
6652     andl(cnt2, ~(stride2-1));   // cnt2 holds the vector count
6653     jcc(Assembler::zero, COMPARE_TAIL_LONG);
6654 
6655     // fast path : compare first 2 8-char vectors.
6656     bind(COMPARE_16_CHARS);
6657     movdqu(vec1, Address(str1, 0));
6658     pcmpestri(vec1, Address(str2, 0), pcmpmask);
6659     jccb(Assembler::below, COMPARE_INDEX_CHAR);
6660 
6661     movdqu(vec1, Address(str1, adr_stride));
6662     pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6663     jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6664     addl(cnt1, stride);
6665 
6666     // Compare the characters at index in cnt1
6667     bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character
6668     load_unsigned_short(result, Address(str1, cnt1, scale));
6669     load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6670     subl(result, cnt2);
6671     jmp(POP_LABEL);
6672 
6673     // Setup the registers to start vector comparison loop
6674     bind(COMPARE_WIDE_VECTORS);
6675     lea(str1, Address(str1, result, scale));
6676     lea(str2, Address(str2, result, scale));
6677     subl(result, stride2);
6678     subl(cnt2, stride2);
6679     jccb(Assembler::zero, COMPARE_WIDE_TAIL);
6680     negptr(result);
6681 
6682     //  In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6683     bind(COMPARE_WIDE_VECTORS_LOOP);
6684     vmovdqu(vec1, Address(str1, result, scale));
6685     vpxor(vec1, Address(str2, result, scale));
6686     vptest(vec1, vec1);
6687     jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
6688     addptr(result, stride2);
6689     subl(cnt2, stride2);
6690     jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6691     // clean upper bits of YMM registers
6692     vzeroupper();
6693 
6694     // compare wide vectors tail
6695     bind(COMPARE_WIDE_TAIL);
6696     testptr(result, result);
6697     jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6698 
6699     movl(result, stride2);
6700     movl(cnt2, result);
6701     negptr(result);
6702     jmpb(COMPARE_WIDE_VECTORS_LOOP);
6703 
6704     // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6705     bind(VECTOR_NOT_EQUAL);
6706     // clean upper bits of YMM registers
6707     vzeroupper();
6708     lea(str1, Address(str1, result, scale));
6709     lea(str2, Address(str2, result, scale));
6710     jmp(COMPARE_16_CHARS);
6711 
6712     // Compare tail chars, length between 1 to 15 chars
6713     bind(COMPARE_TAIL_LONG);
6714     movl(cnt2, result);
6715     cmpl(cnt2, stride);
6716     jccb(Assembler::less, COMPARE_SMALL_STR);
6717 
6718     movdqu(vec1, Address(str1, 0));
6719     pcmpestri(vec1, Address(str2, 0), pcmpmask);
6720     jcc(Assembler::below, COMPARE_INDEX_CHAR);
6721     subptr(cnt2, stride);
6722     jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6723     lea(str1, Address(str1, result, scale));
6724     lea(str2, Address(str2, result, scale));
6725     negptr(cnt2);
6726     jmpb(WHILE_HEAD_LABEL);
6727 
6728     bind(COMPARE_SMALL_STR);
6729   } else if (UseSSE42Intrinsics) {
6730     Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6731     int pcmpmask = 0x19;
6732     // Setup to compare 8-char (16-byte) vectors,
6733     // start from first character again because it has aligned address.
6734     movl(result, cnt2);
6735     andl(cnt2, ~(stride - 1));   // cnt2 holds the vector count
6736     jccb(Assembler::zero, COMPARE_TAIL);
6737 
6738     lea(str1, Address(str1, result, scale));
6739     lea(str2, Address(str2, result, scale));
6740     negptr(result);
6741 
6742     // pcmpestri
6743     //   inputs:
6744     //     vec1- substring
6745     //     rax - negative string length (elements count)
6746     //     mem - scaned string
6747     //     rdx - string length (elements count)
6748     //     pcmpmask - cmp mode: 11000 (string compare with negated result)
6749     //               + 00 (unsigned bytes) or  + 01 (unsigned shorts)
6750     //   outputs:
6751     //     rcx - first mismatched element index
6752     assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6753 
6754     bind(COMPARE_WIDE_VECTORS);
6755     movdqu(vec1, Address(str1, result, scale));
6756     pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6757     // After pcmpestri cnt1(rcx) contains mismatched element index
6758 
6759     jccb(Assembler::below, VECTOR_NOT_EQUAL);  // CF==1
6760     addptr(result, stride);
6761     subptr(cnt2, stride);
6762     jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6763 
6764     // compare wide vectors tail
6765     testptr(result, result);
6766     jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6767 
6768     movl(cnt2, stride);
6769     movl(result, stride);
6770     negptr(result);
6771     movdqu(vec1, Address(str1, result, scale));
6772     pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6773     jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6774 
6775     // Mismatched characters in the vectors
6776     bind(VECTOR_NOT_EQUAL);
6777     addptr(cnt1, result);
6778     load_unsigned_short(result, Address(str1, cnt1, scale));
6779     load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6780     subl(result, cnt2);
6781     jmpb(POP_LABEL);
6782 
6783     bind(COMPARE_TAIL); // limit is zero
6784     movl(cnt2, result);
6785     // Fallthru to tail compare
6786   }
6787   // Shift str2 and str1 to the end of the arrays, negate min
6788   lea(str1, Address(str1, cnt2, scale));
6789   lea(str2, Address(str2, cnt2, scale));
6790   decrementl(cnt2);  // first character was compared already
6791   negptr(cnt2);
6792 
6793   // Compare the rest of the elements
6794   bind(WHILE_HEAD_LABEL);
6795   load_unsigned_short(result, Address(str1, cnt2, scale, 0));
6796   load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0));
6797   subl(result, cnt1);
6798   jccb(Assembler::notZero, POP_LABEL);
6799   increment(cnt2);
6800   jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6801 
6802   // Strings are equal up to min length.  Return the length difference.
6803   bind(LENGTH_DIFF_LABEL);
6804   pop(result);
6805   jmpb(DONE_LABEL);
6806 
6807   // Discard the stored length difference
6808   bind(POP_LABEL);
6809   pop(cnt1);
6810 
6811   // That's it
6812   bind(DONE_LABEL);
6813 }
6814 
6815 // Compare char[] arrays aligned to 4 bytes or substrings.
6816 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
6817                                         Register limit, Register result, Register chr,
6818                                         XMMRegister vec1, XMMRegister vec2) {
6819   ShortBranchVerifier sbv(this);
6820   Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
6821 
6822   int length_offset  = arrayOopDesc::length_offset_in_bytes();
6823   int base_offset    = arrayOopDesc::base_offset_in_bytes(T_CHAR);
6824 
6825   // Check the input args
6826   cmpptr(ary1, ary2);
6827   jcc(Assembler::equal, TRUE_LABEL);
6828 
6829   if (is_array_equ) {
6830     // Need additional checks for arrays_equals.
6831     testptr(ary1, ary1);
6832     jcc(Assembler::zero, FALSE_LABEL);
6833     testptr(ary2, ary2);
6834     jcc(Assembler::zero, FALSE_LABEL);
6835 
6836     // Check the lengths
6837     movl(limit, Address(ary1, length_offset));
6838     cmpl(limit, Address(ary2, length_offset));
6839     jcc(Assembler::notEqual, FALSE_LABEL);
6840   }
6841 
6842   // count == 0
6843   testl(limit, limit);
6844   jcc(Assembler::zero, TRUE_LABEL);
6845 
6846   if (is_array_equ) {
6847     // Load array address
6848     lea(ary1, Address(ary1, base_offset));
6849     lea(ary2, Address(ary2, base_offset));
6850   }
6851 
6852   shll(limit, 1);      // byte count != 0
6853   movl(result, limit); // copy
6854 
6855   if (UseAVX >= 2) {
6856     // With AVX2, use 32-byte vector compare
6857     Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6858 
6859     // Compare 32-byte vectors
6860     andl(result, 0x0000001e);  //   tail count (in bytes)
6861     andl(limit, 0xffffffe0);   // vector count (in bytes)
6862     jccb(Assembler::zero, COMPARE_TAIL);
6863 
6864     lea(ary1, Address(ary1, limit, Address::times_1));
6865     lea(ary2, Address(ary2, limit, Address::times_1));
6866     negptr(limit);
6867 
6868     bind(COMPARE_WIDE_VECTORS);
6869     vmovdqu(vec1, Address(ary1, limit, Address::times_1));
6870     vmovdqu(vec2, Address(ary2, limit, Address::times_1));
6871     vpxor(vec1, vec2);
6872 
6873     vptest(vec1, vec1);
6874     jccb(Assembler::notZero, FALSE_LABEL);
6875     addptr(limit, 32);
6876     jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6877 
6878     testl(result, result);
6879     jccb(Assembler::zero, TRUE_LABEL);
6880 
6881     vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6882     vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
6883     vpxor(vec1, vec2);
6884 
6885     vptest(vec1, vec1);
6886     jccb(Assembler::notZero, FALSE_LABEL);
6887     jmpb(TRUE_LABEL);
6888 
6889     bind(COMPARE_TAIL); // limit is zero
6890     movl(limit, result);
6891     // Fallthru to tail compare
6892   } else if (UseSSE42Intrinsics) {
6893     // With SSE4.2, use double quad vector compare
6894     Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6895 
6896     // Compare 16-byte vectors
6897     andl(result, 0x0000000e);  //   tail count (in bytes)
6898     andl(limit, 0xfffffff0);   // vector count (in bytes)
6899     jccb(Assembler::zero, COMPARE_TAIL);
6900 
6901     lea(ary1, Address(ary1, limit, Address::times_1));
6902     lea(ary2, Address(ary2, limit, Address::times_1));
6903     negptr(limit);
6904 
6905     bind(COMPARE_WIDE_VECTORS);
6906     movdqu(vec1, Address(ary1, limit, Address::times_1));
6907     movdqu(vec2, Address(ary2, limit, Address::times_1));
6908     pxor(vec1, vec2);
6909 
6910     ptest(vec1, vec1);
6911     jccb(Assembler::notZero, FALSE_LABEL);
6912     addptr(limit, 16);
6913     jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6914 
6915     testl(result, result);
6916     jccb(Assembler::zero, TRUE_LABEL);
6917 
6918     movdqu(vec1, Address(ary1, result, Address::times_1, -16));
6919     movdqu(vec2, Address(ary2, result, Address::times_1, -16));
6920     pxor(vec1, vec2);
6921 
6922     ptest(vec1, vec1);
6923     jccb(Assembler::notZero, FALSE_LABEL);
6924     jmpb(TRUE_LABEL);
6925 
6926     bind(COMPARE_TAIL); // limit is zero
6927     movl(limit, result);
6928     // Fallthru to tail compare
6929   }
6930 
6931   // Compare 4-byte vectors
6932   andl(limit, 0xfffffffc); // vector count (in bytes)
6933   jccb(Assembler::zero, COMPARE_CHAR);
6934 
6935   lea(ary1, Address(ary1, limit, Address::times_1));
6936   lea(ary2, Address(ary2, limit, Address::times_1));
6937   negptr(limit);
6938 
6939   bind(COMPARE_VECTORS);
6940   movl(chr, Address(ary1, limit, Address::times_1));
6941   cmpl(chr, Address(ary2, limit, Address::times_1));
6942   jccb(Assembler::notEqual, FALSE_LABEL);
6943   addptr(limit, 4);
6944   jcc(Assembler::notZero, COMPARE_VECTORS);
6945 
6946   // Compare trailing char (final 2 bytes), if any
6947   bind(COMPARE_CHAR);
6948   testl(result, 0x2);   // tail  char
6949   jccb(Assembler::zero, TRUE_LABEL);
6950   load_unsigned_short(chr, Address(ary1, 0));
6951   load_unsigned_short(limit, Address(ary2, 0));
6952   cmpl(chr, limit);
6953   jccb(Assembler::notEqual, FALSE_LABEL);
6954 
6955   bind(TRUE_LABEL);
6956   movl(result, 1);   // return true
6957   jmpb(DONE);
6958 
6959   bind(FALSE_LABEL);
6960   xorl(result, result); // return false
6961 
6962   // That's it
6963   bind(DONE);
6964   if (UseAVX >= 2) {
6965     // clean upper bits of YMM registers
6966     vzeroupper();
6967   }
6968 }
6969 
6970 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6971                                    Register to, Register value, Register count,
6972                                    Register rtmp, XMMRegister xtmp) {
6973   ShortBranchVerifier sbv(this);
6974   assert_different_registers(to, value, count, rtmp);
6975   Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
6976   Label L_fill_2_bytes, L_fill_4_bytes;
6977 
6978   int shift = -1;
6979   switch (t) {
6980     case T_BYTE:
6981       shift = 2;
6982       break;
6983     case T_SHORT:
6984       shift = 1;
6985       break;
6986     case T_INT:
6987       shift = 0;
6988       break;
6989     default: ShouldNotReachHere();
6990   }
6991 
6992   if (t == T_BYTE) {
6993     andl(value, 0xff);
6994     movl(rtmp, value);
6995     shll(rtmp, 8);
6996     orl(value, rtmp);
6997   }
6998   if (t == T_SHORT) {
6999     andl(value, 0xffff);
7000   }
7001   if (t == T_BYTE || t == T_SHORT) {
7002     movl(rtmp, value);
7003     shll(rtmp, 16);
7004     orl(value, rtmp);
7005   }
7006 
7007   cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7008   jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7009   if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7010     // align source address at 4 bytes address boundary
7011     if (t == T_BYTE) {
7012       // One byte misalignment happens only for byte arrays
7013       testptr(to, 1);
7014       jccb(Assembler::zero, L_skip_align1);
7015       movb(Address(to, 0), value);
7016       increment(to);
7017       decrement(count);
7018       BIND(L_skip_align1);
7019     }
7020     // Two bytes misalignment happens only for byte and short (char) arrays
7021     testptr(to, 2);
7022     jccb(Assembler::zero, L_skip_align2);
7023     movw(Address(to, 0), value);
7024     addptr(to, 2);
7025     subl(count, 1<<(shift-1));
7026     BIND(L_skip_align2);
7027   }
7028   if (UseSSE < 2) {
7029     Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7030     // Fill 32-byte chunks
7031     subl(count, 8 << shift);
7032     jcc(Assembler::less, L_check_fill_8_bytes);
7033     align(16);
7034 
7035     BIND(L_fill_32_bytes_loop);
7036 
7037     for (int i = 0; i < 32; i += 4) {
7038       movl(Address(to, i), value);
7039     }
7040 
7041     addptr(to, 32);
7042     subl(count, 8 << shift);
7043     jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7044     BIND(L_check_fill_8_bytes);
7045     addl(count, 8 << shift);
7046     jccb(Assembler::zero, L_exit);
7047     jmpb(L_fill_8_bytes);
7048 
7049     //
7050     // length is too short, just fill qwords
7051     //
7052     BIND(L_fill_8_bytes_loop);
7053     movl(Address(to, 0), value);
7054     movl(Address(to, 4), value);
7055     addptr(to, 8);
7056     BIND(L_fill_8_bytes);
7057     subl(count, 1 << (shift + 1));
7058     jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7059     // fall through to fill 4 bytes
7060   } else {
7061     Label L_fill_32_bytes;
7062     if (!UseUnalignedLoadStores) {
7063       // align to 8 bytes, we know we are 4 byte aligned to start
7064       testptr(to, 4);
7065       jccb(Assembler::zero, L_fill_32_bytes);
7066       movl(Address(to, 0), value);
7067       addptr(to, 4);
7068       subl(count, 1<<shift);
7069     }
7070     BIND(L_fill_32_bytes);
7071     {
7072       assert( UseSSE >= 2, "supported cpu only" );
7073       Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7074       movdl(xtmp, value);
7075       if (UseAVX >= 2 && UseUnalignedLoadStores) {
7076         // Fill 64-byte chunks
7077         Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7078         vpbroadcastd(xtmp, xtmp);
7079 
7080         subl(count, 16 << shift);
7081         jcc(Assembler::less, L_check_fill_32_bytes);
7082         align(16);
7083 
7084         BIND(L_fill_64_bytes_loop);
7085         vmovdqu(Address(to, 0), xtmp);
7086         vmovdqu(Address(to, 32), xtmp);
7087         addptr(to, 64);
7088         subl(count, 16 << shift);
7089         jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7090 
7091         BIND(L_check_fill_32_bytes);
7092         addl(count, 8 << shift);
7093         jccb(Assembler::less, L_check_fill_8_bytes);
7094         vmovdqu(Address(to, 0), xtmp);
7095         addptr(to, 32);
7096         subl(count, 8 << shift);
7097 
7098         BIND(L_check_fill_8_bytes);
7099         // clean upper bits of YMM registers
7100         vzeroupper();
7101       } else {
7102         // Fill 32-byte chunks
7103         pshufd(xtmp, xtmp, 0);
7104 
7105         subl(count, 8 << shift);
7106         jcc(Assembler::less, L_check_fill_8_bytes);
7107         align(16);
7108 
7109         BIND(L_fill_32_bytes_loop);
7110 
7111         if (UseUnalignedLoadStores) {
7112           movdqu(Address(to, 0), xtmp);
7113           movdqu(Address(to, 16), xtmp);
7114         } else {
7115           movq(Address(to, 0), xtmp);
7116           movq(Address(to, 8), xtmp);
7117           movq(Address(to, 16), xtmp);
7118           movq(Address(to, 24), xtmp);
7119         }
7120 
7121         addptr(to, 32);
7122         subl(count, 8 << shift);
7123         jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7124 
7125         BIND(L_check_fill_8_bytes);
7126       }
7127       addl(count, 8 << shift);
7128       jccb(Assembler::zero, L_exit);
7129       jmpb(L_fill_8_bytes);
7130 
7131       //
7132       // length is too short, just fill qwords
7133       //
7134       BIND(L_fill_8_bytes_loop);
7135       movq(Address(to, 0), xtmp);
7136       addptr(to, 8);
7137       BIND(L_fill_8_bytes);
7138       subl(count, 1 << (shift + 1));
7139       jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7140     }
7141   }
7142   // fill trailing 4 bytes
7143   BIND(L_fill_4_bytes);
7144   testl(count, 1<<shift);
7145   jccb(Assembler::zero, L_fill_2_bytes);
7146   movl(Address(to, 0), value);
7147   if (t == T_BYTE || t == T_SHORT) {
7148     addptr(to, 4);
7149     BIND(L_fill_2_bytes);
7150     // fill trailing 2 bytes
7151     testl(count, 1<<(shift-1));
7152     jccb(Assembler::zero, L_fill_byte);
7153     movw(Address(to, 0), value);
7154     if (t == T_BYTE) {
7155       addptr(to, 2);
7156       BIND(L_fill_byte);
7157       // fill trailing byte
7158       testl(count, 1);
7159       jccb(Assembler::zero, L_exit);
7160       movb(Address(to, 0), value);
7161     } else {
7162       BIND(L_fill_byte);
7163     }
7164   } else {
7165     BIND(L_fill_2_bytes);
7166   }
7167   BIND(L_exit);
7168 }
7169 
7170 // encode char[] to byte[] in ISO_8859_1
7171 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7172                                       XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7173                                       XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7174                                       Register tmp5, Register result) {
7175   // rsi: src
7176   // rdi: dst
7177   // rdx: len
7178   // rcx: tmp5
7179   // rax: result
7180   ShortBranchVerifier sbv(this);
7181   assert_different_registers(src, dst, len, tmp5, result);
7182   Label L_done, L_copy_1_char, L_copy_1_char_exit;
7183 
7184   // set result
7185   xorl(result, result);
7186   // check for zero length
7187   testl(len, len);
7188   jcc(Assembler::zero, L_done);
7189   movl(result, len);
7190 
7191   // Setup pointers
7192   lea(src, Address(src, len, Address::times_2)); // char[]
7193   lea(dst, Address(dst, len, Address::times_1)); // byte[]
7194   negptr(len);
7195 
7196   if (UseSSE42Intrinsics || UseAVX >= 2) {
7197     Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
7198     Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7199 
7200     if (UseAVX >= 2) {
7201       Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7202       movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vector
7203       movdl(tmp1Reg, tmp5);
7204       vpbroadcastd(tmp1Reg, tmp1Reg);
7205       jmpb(L_chars_32_check);
7206 
7207       bind(L_copy_32_chars);
7208       vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7209       vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7210       vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ true);
7211       vptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in  vector
7212       jccb(Assembler::notZero, L_copy_32_chars_exit);
7213       vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector256 */ true);
7214       vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector256 */ true);
7215       vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7216 
7217       bind(L_chars_32_check);
7218       addptr(len, 32);
7219       jccb(Assembler::lessEqual, L_copy_32_chars);
7220 
7221       bind(L_copy_32_chars_exit);
7222       subptr(len, 16);
7223       jccb(Assembler::greater, L_copy_16_chars_exit);
7224 
7225     } else if (UseSSE42Intrinsics) {
7226       movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vector
7227       movdl(tmp1Reg, tmp5);
7228       pshufd(tmp1Reg, tmp1Reg, 0);
7229       jmpb(L_chars_16_check);
7230     }
7231 
7232     bind(L_copy_16_chars);
7233     if (UseAVX >= 2) {
7234       vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7235       vptest(tmp2Reg, tmp1Reg);
7236       jccb(Assembler::notZero, L_copy_16_chars_exit);
7237       vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector256 */ true);
7238       vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector256 */ true);
7239     } else {
7240       if (UseAVX > 0) {
7241         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7242         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7243         vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ false);
7244       } else {
7245         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7246         por(tmp2Reg, tmp3Reg);
7247         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7248         por(tmp2Reg, tmp4Reg);
7249       }
7250       ptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in  vector
7251       jccb(Assembler::notZero, L_copy_16_chars_exit);
7252       packuswb(tmp3Reg, tmp4Reg);
7253     }
7254     movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7255 
7256     bind(L_chars_16_check);
7257     addptr(len, 16);
7258     jccb(Assembler::lessEqual, L_copy_16_chars);
7259 
7260     bind(L_copy_16_chars_exit);
7261     if (UseAVX >= 2) {
7262       // clean upper bits of YMM registers
7263       vzeroupper();
7264     }
7265     subptr(len, 8);
7266     jccb(Assembler::greater, L_copy_8_chars_exit);
7267 
7268     bind(L_copy_8_chars);
7269     movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7270     ptest(tmp3Reg, tmp1Reg);
7271     jccb(Assembler::notZero, L_copy_8_chars_exit);
7272     packuswb(tmp3Reg, tmp1Reg);
7273     movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7274     addptr(len, 8);
7275     jccb(Assembler::lessEqual, L_copy_8_chars);
7276 
7277     bind(L_copy_8_chars_exit);
7278     subptr(len, 8);
7279     jccb(Assembler::zero, L_done);
7280   }
7281 
7282   bind(L_copy_1_char);
7283   load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7284   testl(tmp5, 0xff00);      // check if Unicode char
7285   jccb(Assembler::notZero, L_copy_1_char_exit);
7286   movb(Address(dst, len, Address::times_1, 0), tmp5);
7287   addptr(len, 1);
7288   jccb(Assembler::less, L_copy_1_char);
7289 
7290   bind(L_copy_1_char_exit);
7291   addptr(result, len); // len is negative count of not processed elements
7292   bind(L_done);
7293 }
7294 
7295 /**
7296  * Emits code to update CRC-32 with a byte value according to constants in table
7297  *
7298  * @param [in,out]crc   Register containing the crc.
7299  * @param [in]val       Register containing the byte to fold into the CRC.
7300  * @param [in]table     Register containing the table of crc constants.
7301  *
7302  * uint32_t crc;
7303  * val = crc_table[(val ^ crc) & 0xFF];
7304  * crc = val ^ (crc >> 8);
7305  *
7306  */
7307 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
7308   xorl(val, crc);
7309   andl(val, 0xFF);
7310   shrl(crc, 8); // unsigned shift
7311   xorl(crc, Address(table, val, Address::times_4, 0));
7312 }
7313 
7314 /**
7315  * Fold 128-bit data chunk
7316  */
7317 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
7318   vpclmulhdq(xtmp, xK, xcrc); // [123:64]
7319   vpclmulldq(xcrc, xK, xcrc); // [63:0]
7320   vpxor(xcrc, xcrc, Address(buf, offset), false /* vector256 */);
7321   pxor(xcrc, xtmp);
7322 }
7323 
7324 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
7325   vpclmulhdq(xtmp, xK, xcrc);
7326   vpclmulldq(xcrc, xK, xcrc);
7327   pxor(xcrc, xbuf);
7328   pxor(xcrc, xtmp);
7329 }
7330 
7331 /**
7332  * 8-bit folds to compute 32-bit CRC
7333  *
7334  * uint64_t xcrc;
7335  * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
7336  */
7337 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
7338   movdl(tmp, xcrc);
7339   andl(tmp, 0xFF);
7340   movdl(xtmp, Address(table, tmp, Address::times_4, 0));
7341   psrldq(xcrc, 1); // unsigned shift one byte
7342   pxor(xcrc, xtmp);
7343 }
7344 
7345 /**
7346  * uint32_t crc;
7347  * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
7348  */
7349 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
7350   movl(tmp, crc);
7351   andl(tmp, 0xFF);
7352   shrl(crc, 8);
7353   xorl(crc, Address(table, tmp, Address::times_4, 0));
7354 }
7355 
7356 /**
7357  * @param crc   register containing existing CRC (32-bit)
7358  * @param buf   register pointing to input byte buffer (byte*)
7359  * @param len   register containing number of bytes
7360  * @param table register that will contain address of CRC table
7361  * @param tmp   scratch register
7362  */
7363 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
7364   assert_different_registers(crc, buf, len, table, tmp, rax);
7365 
7366   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7367   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7368 
7369   lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
7370   notl(crc); // ~crc
7371   cmpl(len, 16);
7372   jcc(Assembler::less, L_tail);
7373 
7374   // Align buffer to 16 bytes
7375   movl(tmp, buf);
7376   andl(tmp, 0xF);
7377   jccb(Assembler::zero, L_aligned);
7378   subl(tmp,  16);
7379   addl(len, tmp);
7380 
7381   align(4);
7382   BIND(L_align_loop);
7383   movsbl(rax, Address(buf, 0)); // load byte with sign extension
7384   update_byte_crc32(crc, rax, table);
7385   increment(buf);
7386   incrementl(tmp);
7387   jccb(Assembler::less, L_align_loop);
7388 
7389   BIND(L_aligned);
7390   movl(tmp, len); // save
7391   shrl(len, 4);
7392   jcc(Assembler::zero, L_tail_restore);
7393 
7394   // Fold crc into first bytes of vector
7395   movdqa(xmm1, Address(buf, 0));
7396   movdl(rax, xmm1);
7397   xorl(crc, rax);
7398   pinsrd(xmm1, crc, 0);
7399   addptr(buf, 16);
7400   subl(len, 4); // len > 0
7401   jcc(Assembler::less, L_fold_tail);
7402 
7403   movdqa(xmm2, Address(buf,  0));
7404   movdqa(xmm3, Address(buf, 16));
7405   movdqa(xmm4, Address(buf, 32));
7406   addptr(buf, 48);
7407   subl(len, 3);
7408   jcc(Assembler::lessEqual, L_fold_512b);
7409 
7410   // Fold total 512 bits of polynomial on each iteration,
7411   // 128 bits per each of 4 parallel streams.
7412   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
7413 
7414   align(32);
7415   BIND(L_fold_512b_loop);
7416   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
7417   fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
7418   fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
7419   fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
7420   addptr(buf, 64);
7421   subl(len, 4);
7422   jcc(Assembler::greater, L_fold_512b_loop);
7423 
7424   // Fold 512 bits to 128 bits.
7425   BIND(L_fold_512b);
7426   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7427   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
7428   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
7429   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
7430 
7431   // Fold the rest of 128 bits data chunks
7432   BIND(L_fold_tail);
7433   addl(len, 3);
7434   jccb(Assembler::lessEqual, L_fold_128b);
7435   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7436 
7437   BIND(L_fold_tail_loop);
7438   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
7439   addptr(buf, 16);
7440   decrementl(len);
7441   jccb(Assembler::greater, L_fold_tail_loop);
7442 
7443   // Fold 128 bits in xmm1 down into 32 bits in crc register.
7444   BIND(L_fold_128b);
7445   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
7446   vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
7447   vpand(xmm3, xmm0, xmm2, false /* vector256 */);
7448   vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
7449   psrldq(xmm1, 8);
7450   psrldq(xmm2, 4);
7451   pxor(xmm0, xmm1);
7452   pxor(xmm0, xmm2);
7453 
7454   // 8 8-bit folds to compute 32-bit CRC.
7455   for (int j = 0; j < 4; j++) {
7456     fold_8bit_crc32(xmm0, table, xmm1, rax);
7457   }
7458   movdl(crc, xmm0); // mov 32 bits to general register
7459   for (int j = 0; j < 4; j++) {
7460     fold_8bit_crc32(crc, table, rax);
7461   }
7462 
7463   BIND(L_tail_restore);
7464   movl(len, tmp); // restore
7465   BIND(L_tail);
7466   andl(len, 0xf);
7467   jccb(Assembler::zero, L_exit);
7468 
7469   // Fold the rest of bytes
7470   align(4);
7471   BIND(L_tail_loop);
7472   movsbl(rax, Address(buf, 0)); // load byte with sign extension
7473   update_byte_crc32(crc, rax, table);
7474   increment(buf);
7475   decrementl(len);
7476   jccb(Assembler::greater, L_tail_loop);
7477 
7478   BIND(L_exit);
7479   notl(crc); // ~c
7480 }
7481 
7482 #undef BIND
7483 #undef BLOCK_COMMENT
7484 
7485 
7486 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
7487   switch (cond) {
7488     // Note some conditions are synonyms for others
7489     case Assembler::zero:         return Assembler::notZero;
7490     case Assembler::notZero:      return Assembler::zero;
7491     case Assembler::less:         return Assembler::greaterEqual;
7492     case Assembler::lessEqual:    return Assembler::greater;
7493     case Assembler::greater:      return Assembler::lessEqual;
7494     case Assembler::greaterEqual: return Assembler::less;
7495     case Assembler::below:        return Assembler::aboveEqual;
7496     case Assembler::belowEqual:   return Assembler::above;
7497     case Assembler::above:        return Assembler::belowEqual;
7498     case Assembler::aboveEqual:   return Assembler::below;
7499     case Assembler::overflow:     return Assembler::noOverflow;
7500     case Assembler::noOverflow:   return Assembler::overflow;
7501     case Assembler::negative:     return Assembler::positive;
7502     case Assembler::positive:     return Assembler::negative;
7503     case Assembler::parity:       return Assembler::noParity;
7504     case Assembler::noParity:     return Assembler::parity;
7505   }
7506   ShouldNotReachHere(); return Assembler::overflow;
7507 }
7508 
7509 SkipIfEqual::SkipIfEqual(
7510     MacroAssembler* masm, const bool* flag_addr, bool value) {
7511   _masm = masm;
7512   _masm->cmp8(ExternalAddress((address)flag_addr), value);
7513   _masm->jcc(Assembler::equal, _label);
7514 }
7515 
7516 SkipIfEqual::~SkipIfEqual() {
7517   _masm->bind(_label);
7518 }