1 /*
2 * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "code/debugInfoRec.hpp"
29 #include "code/icBuffer.hpp"
30 #include "code/vtableStubs.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "oops/compiledICHolder.hpp"
33 #include "prims/jvmtiRedefineClassesTrace.hpp"
34 #include "runtime/sharedRuntime.hpp"
35 #include "runtime/vframeArray.hpp"
36 #include "vmreg_x86.inline.hpp"
37 #ifdef COMPILER1
38 #include "c1/c1_Runtime1.hpp"
39 #endif
40 #ifdef COMPILER2
41 #include "opto/runtime.hpp"
42 #endif
43
44 #define __ masm->
45
46 const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size;
47
48 class SimpleRuntimeFrame {
49
50 public:
51
52 // Most of the runtime stubs have this simple frame layout.
53 // This class exists to make the layout shared in one place.
54 // Offsets are for compiler stack slots, which are jints.
55 enum layout {
56 // The frame sender code expects that rbp will be in the "natural" place and
57 // will override any oopMap setting for it. We must therefore force the layout
58 // so that it agrees with the frame sender code.
59 rbp_off = frame::arg_reg_save_area_bytes/BytesPerInt,
60 rbp_off2,
61 return_off, return_off2,
62 framesize
63 };
64 };
65
66 class RegisterSaver {
67 // Capture info about frame layout. Layout offsets are in jint
68 // units because compiler frame slots are jints.
69 #define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off
70 enum layout {
71 fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area
72 xmm_off = fpu_state_off + 160/BytesPerInt, // offset in fxsave save area
73 DEF_XMM_OFFS(0),
74 DEF_XMM_OFFS(1),
75 DEF_XMM_OFFS(2),
76 DEF_XMM_OFFS(3),
77 DEF_XMM_OFFS(4),
78 DEF_XMM_OFFS(5),
79 DEF_XMM_OFFS(6),
80 DEF_XMM_OFFS(7),
81 DEF_XMM_OFFS(8),
82 DEF_XMM_OFFS(9),
83 DEF_XMM_OFFS(10),
84 DEF_XMM_OFFS(11),
85 DEF_XMM_OFFS(12),
86 DEF_XMM_OFFS(13),
87 DEF_XMM_OFFS(14),
88 DEF_XMM_OFFS(15),
89 fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt),
90 fpu_stateH_end,
91 r15_off, r15H_off,
92 r14_off, r14H_off,
93 r13_off, r13H_off,
94 r12_off, r12H_off,
95 r11_off, r11H_off,
96 r10_off, r10H_off,
97 r9_off, r9H_off,
98 r8_off, r8H_off,
99 rdi_off, rdiH_off,
100 rsi_off, rsiH_off,
101 ignore_off, ignoreH_off, // extra copy of rbp
102 rsp_off, rspH_off,
103 rbx_off, rbxH_off,
104 rdx_off, rdxH_off,
105 rcx_off, rcxH_off,
106 rax_off, raxH_off,
107 // 16-byte stack alignment fill word: see MacroAssembler::push/pop_IU_state
108 align_off, alignH_off,
109 flags_off, flagsH_off,
110 // The frame sender code expects that rbp will be in the "natural" place and
111 // will override any oopMap setting for it. We must therefore force the layout
112 // so that it agrees with the frame sender code.
113 rbp_off, rbpH_off, // copy of rbp we will restore
114 return_off, returnH_off, // slot for return address
115 reg_save_size // size in compiler stack slots
116 };
117
118 public:
119 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors = false);
120 static void restore_live_registers(MacroAssembler* masm, bool restore_vectors = false);
121
122 // Offsets into the register save area
123 // Used by deoptimization when it is managing result register
124 // values on its own
125
126 static int rax_offset_in_bytes(void) { return BytesPerInt * rax_off; }
127 static int rdx_offset_in_bytes(void) { return BytesPerInt * rdx_off; }
128 static int rbx_offset_in_bytes(void) { return BytesPerInt * rbx_off; }
129 static int xmm0_offset_in_bytes(void) { return BytesPerInt * xmm0_off; }
130 static int return_offset_in_bytes(void) { return BytesPerInt * return_off; }
131
132 // During deoptimization only the result registers need to be restored,
133 // all the other values have already been extracted.
134 static void restore_result_registers(MacroAssembler* masm);
135 };
136
137 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors) {
138 int vect_words = 0;
139 #ifdef COMPILER2
140 if (save_vectors) {
141 assert(UseAVX > 0, "256bit vectors are supported only with AVX");
142 assert(MaxVectorSize == 32, "only 256bit vectors are supported now");
143 // Save upper half of YMM registes
144 vect_words = 16 * 16 / wordSize;
145 additional_frame_words += vect_words;
146 }
147 #else
148 assert(!save_vectors, "vectors are generated only by C2");
149 #endif
150
151 // Always make the frame size 16-byte aligned
152 int frame_size_in_bytes = round_to(additional_frame_words*wordSize +
153 reg_save_size*BytesPerInt, 16);
154 // OopMap frame size is in compiler stack slots (jint's) not bytes or words
155 int frame_size_in_slots = frame_size_in_bytes / BytesPerInt;
156 // The caller will allocate additional_frame_words
157 int additional_frame_slots = additional_frame_words*wordSize / BytesPerInt;
158 // CodeBlob frame size is in words.
159 int frame_size_in_words = frame_size_in_bytes / wordSize;
160 *total_frame_words = frame_size_in_words;
161
162 // Save registers, fpu state, and flags.
163 // We assume caller has already pushed the return address onto the
164 // stack, so rsp is 8-byte aligned here.
165 // We push rpb twice in this sequence because we want the real rbp
166 // to be under the return like a normal enter.
167
168 __ enter(); // rsp becomes 16-byte aligned here
169 __ push_CPU_state(); // Push a multiple of 16 bytes
170
171 if (vect_words > 0) {
172 assert(vect_words*wordSize == 256, "");
173 __ subptr(rsp, 256); // Save upper half of YMM registes
174 __ vextractf128h(Address(rsp, 0),xmm0);
175 __ vextractf128h(Address(rsp, 16),xmm1);
176 __ vextractf128h(Address(rsp, 32),xmm2);
177 __ vextractf128h(Address(rsp, 48),xmm3);
178 __ vextractf128h(Address(rsp, 64),xmm4);
179 __ vextractf128h(Address(rsp, 80),xmm5);
180 __ vextractf128h(Address(rsp, 96),xmm6);
181 __ vextractf128h(Address(rsp,112),xmm7);
182 __ vextractf128h(Address(rsp,128),xmm8);
183 __ vextractf128h(Address(rsp,144),xmm9);
184 __ vextractf128h(Address(rsp,160),xmm10);
185 __ vextractf128h(Address(rsp,176),xmm11);
186 __ vextractf128h(Address(rsp,192),xmm12);
187 __ vextractf128h(Address(rsp,208),xmm13);
188 __ vextractf128h(Address(rsp,224),xmm14);
189 __ vextractf128h(Address(rsp,240),xmm15);
190 }
191 if (frame::arg_reg_save_area_bytes != 0) {
192 // Allocate argument register save area
193 __ subptr(rsp, frame::arg_reg_save_area_bytes);
194 }
195
196 // Set an oopmap for the call site. This oopmap will map all
197 // oop-registers and debug-info registers as callee-saved. This
198 // will allow deoptimization at this safepoint to find all possible
199 // debug-info recordings, as well as let GC find all oops.
200
201 OopMapSet *oop_maps = new OopMapSet();
202 OopMap* map = new OopMap(frame_size_in_slots, 0);
203
204 #define STACK_OFFSET(x) VMRegImpl::stack2reg((x) + additional_frame_slots)
205
206 map->set_callee_saved(STACK_OFFSET( rax_off ), rax->as_VMReg());
207 map->set_callee_saved(STACK_OFFSET( rcx_off ), rcx->as_VMReg());
208 map->set_callee_saved(STACK_OFFSET( rdx_off ), rdx->as_VMReg());
209 map->set_callee_saved(STACK_OFFSET( rbx_off ), rbx->as_VMReg());
210 // rbp location is known implicitly by the frame sender code, needs no oopmap
211 // and the location where rbp was saved by is ignored
212 map->set_callee_saved(STACK_OFFSET( rsi_off ), rsi->as_VMReg());
213 map->set_callee_saved(STACK_OFFSET( rdi_off ), rdi->as_VMReg());
214 map->set_callee_saved(STACK_OFFSET( r8_off ), r8->as_VMReg());
215 map->set_callee_saved(STACK_OFFSET( r9_off ), r9->as_VMReg());
216 map->set_callee_saved(STACK_OFFSET( r10_off ), r10->as_VMReg());
217 map->set_callee_saved(STACK_OFFSET( r11_off ), r11->as_VMReg());
218 map->set_callee_saved(STACK_OFFSET( r12_off ), r12->as_VMReg());
219 map->set_callee_saved(STACK_OFFSET( r13_off ), r13->as_VMReg());
220 map->set_callee_saved(STACK_OFFSET( r14_off ), r14->as_VMReg());
221 map->set_callee_saved(STACK_OFFSET( r15_off ), r15->as_VMReg());
222 map->set_callee_saved(STACK_OFFSET(xmm0_off ), xmm0->as_VMReg());
223 map->set_callee_saved(STACK_OFFSET(xmm1_off ), xmm1->as_VMReg());
224 map->set_callee_saved(STACK_OFFSET(xmm2_off ), xmm2->as_VMReg());
225 map->set_callee_saved(STACK_OFFSET(xmm3_off ), xmm3->as_VMReg());
226 map->set_callee_saved(STACK_OFFSET(xmm4_off ), xmm4->as_VMReg());
227 map->set_callee_saved(STACK_OFFSET(xmm5_off ), xmm5->as_VMReg());
228 map->set_callee_saved(STACK_OFFSET(xmm6_off ), xmm6->as_VMReg());
229 map->set_callee_saved(STACK_OFFSET(xmm7_off ), xmm7->as_VMReg());
230 map->set_callee_saved(STACK_OFFSET(xmm8_off ), xmm8->as_VMReg());
231 map->set_callee_saved(STACK_OFFSET(xmm9_off ), xmm9->as_VMReg());
232 map->set_callee_saved(STACK_OFFSET(xmm10_off), xmm10->as_VMReg());
233 map->set_callee_saved(STACK_OFFSET(xmm11_off), xmm11->as_VMReg());
234 map->set_callee_saved(STACK_OFFSET(xmm12_off), xmm12->as_VMReg());
235 map->set_callee_saved(STACK_OFFSET(xmm13_off), xmm13->as_VMReg());
236 map->set_callee_saved(STACK_OFFSET(xmm14_off), xmm14->as_VMReg());
237 map->set_callee_saved(STACK_OFFSET(xmm15_off), xmm15->as_VMReg());
238
239 // %%% These should all be a waste but we'll keep things as they were for now
240 if (true) {
241 map->set_callee_saved(STACK_OFFSET( raxH_off ), rax->as_VMReg()->next());
242 map->set_callee_saved(STACK_OFFSET( rcxH_off ), rcx->as_VMReg()->next());
243 map->set_callee_saved(STACK_OFFSET( rdxH_off ), rdx->as_VMReg()->next());
244 map->set_callee_saved(STACK_OFFSET( rbxH_off ), rbx->as_VMReg()->next());
245 // rbp location is known implicitly by the frame sender code, needs no oopmap
246 map->set_callee_saved(STACK_OFFSET( rsiH_off ), rsi->as_VMReg()->next());
247 map->set_callee_saved(STACK_OFFSET( rdiH_off ), rdi->as_VMReg()->next());
248 map->set_callee_saved(STACK_OFFSET( r8H_off ), r8->as_VMReg()->next());
249 map->set_callee_saved(STACK_OFFSET( r9H_off ), r9->as_VMReg()->next());
250 map->set_callee_saved(STACK_OFFSET( r10H_off ), r10->as_VMReg()->next());
251 map->set_callee_saved(STACK_OFFSET( r11H_off ), r11->as_VMReg()->next());
252 map->set_callee_saved(STACK_OFFSET( r12H_off ), r12->as_VMReg()->next());
253 map->set_callee_saved(STACK_OFFSET( r13H_off ), r13->as_VMReg()->next());
254 map->set_callee_saved(STACK_OFFSET( r14H_off ), r14->as_VMReg()->next());
255 map->set_callee_saved(STACK_OFFSET( r15H_off ), r15->as_VMReg()->next());
256 map->set_callee_saved(STACK_OFFSET(xmm0H_off ), xmm0->as_VMReg()->next());
257 map->set_callee_saved(STACK_OFFSET(xmm1H_off ), xmm1->as_VMReg()->next());
258 map->set_callee_saved(STACK_OFFSET(xmm2H_off ), xmm2->as_VMReg()->next());
259 map->set_callee_saved(STACK_OFFSET(xmm3H_off ), xmm3->as_VMReg()->next());
260 map->set_callee_saved(STACK_OFFSET(xmm4H_off ), xmm4->as_VMReg()->next());
261 map->set_callee_saved(STACK_OFFSET(xmm5H_off ), xmm5->as_VMReg()->next());
262 map->set_callee_saved(STACK_OFFSET(xmm6H_off ), xmm6->as_VMReg()->next());
263 map->set_callee_saved(STACK_OFFSET(xmm7H_off ), xmm7->as_VMReg()->next());
264 map->set_callee_saved(STACK_OFFSET(xmm8H_off ), xmm8->as_VMReg()->next());
265 map->set_callee_saved(STACK_OFFSET(xmm9H_off ), xmm9->as_VMReg()->next());
266 map->set_callee_saved(STACK_OFFSET(xmm10H_off), xmm10->as_VMReg()->next());
267 map->set_callee_saved(STACK_OFFSET(xmm11H_off), xmm11->as_VMReg()->next());
268 map->set_callee_saved(STACK_OFFSET(xmm12H_off), xmm12->as_VMReg()->next());
269 map->set_callee_saved(STACK_OFFSET(xmm13H_off), xmm13->as_VMReg()->next());
270 map->set_callee_saved(STACK_OFFSET(xmm14H_off), xmm14->as_VMReg()->next());
271 map->set_callee_saved(STACK_OFFSET(xmm15H_off), xmm15->as_VMReg()->next());
272 }
273
274 return map;
275 }
276
277 void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_vectors) {
278 if (frame::arg_reg_save_area_bytes != 0) {
279 // Pop arg register save area
280 __ addptr(rsp, frame::arg_reg_save_area_bytes);
281 }
282 #ifdef COMPILER2
283 if (restore_vectors) {
284 // Restore upper half of YMM registes.
285 assert(UseAVX > 0, "256bit vectors are supported only with AVX");
286 assert(MaxVectorSize == 32, "only 256bit vectors are supported now");
287 __ vinsertf128h(xmm0, Address(rsp, 0));
288 __ vinsertf128h(xmm1, Address(rsp, 16));
289 __ vinsertf128h(xmm2, Address(rsp, 32));
290 __ vinsertf128h(xmm3, Address(rsp, 48));
291 __ vinsertf128h(xmm4, Address(rsp, 64));
292 __ vinsertf128h(xmm5, Address(rsp, 80));
293 __ vinsertf128h(xmm6, Address(rsp, 96));
294 __ vinsertf128h(xmm7, Address(rsp,112));
295 __ vinsertf128h(xmm8, Address(rsp,128));
296 __ vinsertf128h(xmm9, Address(rsp,144));
297 __ vinsertf128h(xmm10, Address(rsp,160));
298 __ vinsertf128h(xmm11, Address(rsp,176));
299 __ vinsertf128h(xmm12, Address(rsp,192));
300 __ vinsertf128h(xmm13, Address(rsp,208));
301 __ vinsertf128h(xmm14, Address(rsp,224));
302 __ vinsertf128h(xmm15, Address(rsp,240));
303 __ addptr(rsp, 256);
304 }
305 #else
306 assert(!restore_vectors, "vectors are generated only by C2");
307 #endif
308 // Recover CPU state
309 __ pop_CPU_state();
310 // Get the rbp described implicitly by the calling convention (no oopMap)
311 __ pop(rbp);
312 }
313
314 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
315
316 // Just restore result register. Only used by deoptimization. By
317 // now any callee save register that needs to be restored to a c2
318 // caller of the deoptee has been extracted into the vframeArray
319 // and will be stuffed into the c2i adapter we create for later
320 // restoration so only result registers need to be restored here.
321
322 // Restore fp result register
323 __ movdbl(xmm0, Address(rsp, xmm0_offset_in_bytes()));
324 // Restore integer result register
325 __ movptr(rax, Address(rsp, rax_offset_in_bytes()));
326 __ movptr(rdx, Address(rsp, rdx_offset_in_bytes()));
327
328 // Pop all of the register save are off the stack except the return address
329 __ addptr(rsp, return_offset_in_bytes());
330 }
331
332 // Is vector's size (in bytes) bigger than a size saved by default?
333 // 16 bytes XMM registers are saved by default using fxsave/fxrstor instructions.
334 bool SharedRuntime::is_wide_vector(int size) {
335 return size > 16;
336 }
337
338 // The java_calling_convention describes stack locations as ideal slots on
339 // a frame with no abi restrictions. Since we must observe abi restrictions
340 // (like the placement of the register window) the slots must be biased by
341 // the following value.
342 static int reg2offset_in(VMReg r) {
343 // Account for saved rbp and return address
344 // This should really be in_preserve_stack_slots
345 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
346 }
347
348 static int reg2offset_out(VMReg r) {
349 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
350 }
351
352 // ---------------------------------------------------------------------------
353 // Read the array of BasicTypes from a signature, and compute where the
354 // arguments should go. Values in the VMRegPair regs array refer to 4-byte
355 // quantities. Values less than VMRegImpl::stack0 are registers, those above
356 // refer to 4-byte stack slots. All stack slots are based off of the stack pointer
357 // as framesizes are fixed.
358 // VMRegImpl::stack0 refers to the first slot 0(sp).
359 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
360 // up to RegisterImpl::number_of_registers) are the 64-bit
361 // integer registers.
362
363 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
364 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
365 // units regardless of build. Of course for i486 there is no 64 bit build
366
367 // The Java calling convention is a "shifted" version of the C ABI.
368 // By skipping the first C ABI register we can call non-static jni methods
369 // with small numbers of arguments without having to shuffle the arguments
370 // at all. Since we control the java ABI we ought to at least get some
371 // advantage out of it.
372
373 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
374 VMRegPair *regs,
375 int total_args_passed,
376 int is_outgoing) {
377
378 // Create the mapping between argument positions and
379 // registers.
380 static const Register INT_ArgReg[Argument::n_int_register_parameters_j] = {
381 j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5
382 };
383 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_j] = {
384 j_farg0, j_farg1, j_farg2, j_farg3,
385 j_farg4, j_farg5, j_farg6, j_farg7
386 };
387
388
389 uint int_args = 0;
390 uint fp_args = 0;
391 uint stk_args = 0; // inc by 2 each time
392
393 for (int i = 0; i < total_args_passed; i++) {
394 switch (sig_bt[i]) {
395 case T_BOOLEAN:
396 case T_CHAR:
397 case T_BYTE:
398 case T_SHORT:
399 case T_INT:
400 if (int_args < Argument::n_int_register_parameters_j) {
401 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
402 } else {
403 regs[i].set1(VMRegImpl::stack2reg(stk_args));
404 stk_args += 2;
405 }
406 break;
407 case T_VOID:
408 // halves of T_LONG or T_DOUBLE
409 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
410 regs[i].set_bad();
411 break;
412 case T_LONG:
413 assert(sig_bt[i + 1] == T_VOID, "expecting half");
414 // fall through
415 case T_OBJECT:
416 case T_ARRAY:
417 case T_ADDRESS:
418 if (int_args < Argument::n_int_register_parameters_j) {
419 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
420 } else {
421 regs[i].set2(VMRegImpl::stack2reg(stk_args));
422 stk_args += 2;
423 }
424 break;
425 case T_FLOAT:
426 if (fp_args < Argument::n_float_register_parameters_j) {
427 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
428 } else {
429 regs[i].set1(VMRegImpl::stack2reg(stk_args));
430 stk_args += 2;
431 }
432 break;
433 case T_DOUBLE:
434 assert(sig_bt[i + 1] == T_VOID, "expecting half");
435 if (fp_args < Argument::n_float_register_parameters_j) {
436 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
437 } else {
438 regs[i].set2(VMRegImpl::stack2reg(stk_args));
439 stk_args += 2;
440 }
441 break;
442 default:
443 ShouldNotReachHere();
444 break;
445 }
446 }
447
448 return round_to(stk_args, 2);
449 }
450
451 // Patch the callers callsite with entry to compiled code if it exists.
452 static void patch_callers_callsite(MacroAssembler *masm) {
453 Label L;
454 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD);
455 __ jcc(Assembler::equal, L);
456
457 // Save the current stack pointer
458 __ mov(r13, rsp);
459 // Schedule the branch target address early.
460 // Call into the VM to patch the caller, then jump to compiled callee
461 // rax isn't live so capture return address while we easily can
462 __ movptr(rax, Address(rsp, 0));
463
464 // align stack so push_CPU_state doesn't fault
465 __ andptr(rsp, -(StackAlignmentInBytes));
466 __ push_CPU_state();
467
468 // VM needs caller's callsite
469 // VM needs target method
470 // This needs to be a long call since we will relocate this adapter to
471 // the codeBuffer and it may not reach
472
473 // Allocate argument register save area
474 if (frame::arg_reg_save_area_bytes != 0) {
475 __ subptr(rsp, frame::arg_reg_save_area_bytes);
476 }
477 __ mov(c_rarg0, rbx);
478 __ mov(c_rarg1, rax);
479 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
480
481 // De-allocate argument register save area
482 if (frame::arg_reg_save_area_bytes != 0) {
483 __ addptr(rsp, frame::arg_reg_save_area_bytes);
484 }
485
486 __ pop_CPU_state();
487 // restore sp
488 __ mov(rsp, r13);
489 __ bind(L);
490 }
491
492
493 static void gen_c2i_adapter(MacroAssembler *masm,
494 int total_args_passed,
495 int comp_args_on_stack,
496 const BasicType *sig_bt,
497 const VMRegPair *regs,
498 Label& skip_fixup) {
499 // Before we get into the guts of the C2I adapter, see if we should be here
500 // at all. We've come from compiled code and are attempting to jump to the
501 // interpreter, which means the caller made a static call to get here
502 // (vcalls always get a compiled target if there is one). Check for a
503 // compiled target. If there is one, we need to patch the caller's call.
504 patch_callers_callsite(masm);
505
506 __ bind(skip_fixup);
507
508 // Since all args are passed on the stack, total_args_passed *
509 // Interpreter::stackElementSize is the space we need. Plus 1 because
510 // we also account for the return address location since
511 // we store it first rather than hold it in rax across all the shuffling
512
513 int extraspace = (total_args_passed * Interpreter::stackElementSize) + wordSize;
514
515 // stack is aligned, keep it that way
516 extraspace = round_to(extraspace, 2*wordSize);
517
518 // Get return address
519 __ pop(rax);
520
521 // set senderSP value
522 __ mov(r13, rsp);
523
524 __ subptr(rsp, extraspace);
525
526 // Store the return address in the expected location
527 __ movptr(Address(rsp, 0), rax);
528
529 // Now write the args into the outgoing interpreter space
530 for (int i = 0; i < total_args_passed; i++) {
531 if (sig_bt[i] == T_VOID) {
532 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
533 continue;
534 }
535
536 // offset to start parameters
537 int st_off = (total_args_passed - i) * Interpreter::stackElementSize;
538 int next_off = st_off - Interpreter::stackElementSize;
539
540 // Say 4 args:
541 // i st_off
542 // 0 32 T_LONG
543 // 1 24 T_VOID
544 // 2 16 T_OBJECT
545 // 3 8 T_BOOL
546 // - 0 return address
547 //
548 // However to make thing extra confusing. Because we can fit a long/double in
549 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
550 // leaves one slot empty and only stores to a single slot. In this case the
551 // slot that is occupied is the T_VOID slot. See I said it was confusing.
552
553 VMReg r_1 = regs[i].first();
554 VMReg r_2 = regs[i].second();
555 if (!r_1->is_valid()) {
556 assert(!r_2->is_valid(), "");
557 continue;
558 }
559 if (r_1->is_stack()) {
560 // memory to memory use rax
561 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
562 if (!r_2->is_valid()) {
563 // sign extend??
564 __ movl(rax, Address(rsp, ld_off));
565 __ movptr(Address(rsp, st_off), rax);
566
567 } else {
568
569 __ movq(rax, Address(rsp, ld_off));
570
571 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
572 // T_DOUBLE and T_LONG use two slots in the interpreter
573 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
574 // ld_off == LSW, ld_off+wordSize == MSW
575 // st_off == MSW, next_off == LSW
576 __ movq(Address(rsp, next_off), rax);
577 #ifdef ASSERT
578 // Overwrite the unused slot with known junk
579 __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
580 __ movptr(Address(rsp, st_off), rax);
581 #endif /* ASSERT */
582 } else {
583 __ movq(Address(rsp, st_off), rax);
584 }
585 }
586 } else if (r_1->is_Register()) {
587 Register r = r_1->as_Register();
588 if (!r_2->is_valid()) {
589 // must be only an int (or less ) so move only 32bits to slot
590 // why not sign extend??
591 __ movl(Address(rsp, st_off), r);
592 } else {
593 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
594 // T_DOUBLE and T_LONG use two slots in the interpreter
595 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
596 // long/double in gpr
597 #ifdef ASSERT
598 // Overwrite the unused slot with known junk
599 __ mov64(rax, CONST64(0xdeadffffdeadaaab));
600 __ movptr(Address(rsp, st_off), rax);
601 #endif /* ASSERT */
602 __ movq(Address(rsp, next_off), r);
603 } else {
604 __ movptr(Address(rsp, st_off), r);
605 }
606 }
607 } else {
608 assert(r_1->is_XMMRegister(), "");
609 if (!r_2->is_valid()) {
610 // only a float use just part of the slot
611 __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
612 } else {
613 #ifdef ASSERT
614 // Overwrite the unused slot with known junk
615 __ mov64(rax, CONST64(0xdeadffffdeadaaac));
616 __ movptr(Address(rsp, st_off), rax);
617 #endif /* ASSERT */
618 __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister());
619 }
620 }
621 }
622
623 // Schedule the branch target address early.
624 __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset())));
625 __ jmp(rcx);
626 }
627
628 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg,
629 address code_start, address code_end,
630 Label& L_ok) {
631 Label L_fail;
632 __ lea(temp_reg, ExternalAddress(code_start));
633 __ cmpptr(pc_reg, temp_reg);
634 __ jcc(Assembler::belowEqual, L_fail);
635 __ lea(temp_reg, ExternalAddress(code_end));
636 __ cmpptr(pc_reg, temp_reg);
637 __ jcc(Assembler::below, L_ok);
638 __ bind(L_fail);
639 }
640
641 static void gen_i2c_adapter(MacroAssembler *masm,
642 int total_args_passed,
643 int comp_args_on_stack,
644 const BasicType *sig_bt,
645 const VMRegPair *regs) {
646
647 // Note: r13 contains the senderSP on entry. We must preserve it since
648 // we may do a i2c -> c2i transition if we lose a race where compiled
649 // code goes non-entrant while we get args ready.
650 // In addition we use r13 to locate all the interpreter args as
651 // we must align the stack to 16 bytes on an i2c entry else we
652 // lose alignment we expect in all compiled code and register
653 // save code can segv when fxsave instructions find improperly
654 // aligned stack pointer.
655
656 // Adapters can be frameless because they do not require the caller
657 // to perform additional cleanup work, such as correcting the stack pointer.
658 // An i2c adapter is frameless because the *caller* frame, which is interpreted,
659 // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
660 // even if a callee has modified the stack pointer.
661 // A c2i adapter is frameless because the *callee* frame, which is interpreted,
662 // routinely repairs its caller's stack pointer (from sender_sp, which is set
663 // up via the senderSP register).
664 // In other words, if *either* the caller or callee is interpreted, we can
665 // get the stack pointer repaired after a call.
666 // This is why c2i and i2c adapters cannot be indefinitely composed.
667 // In particular, if a c2i adapter were to somehow call an i2c adapter,
668 // both caller and callee would be compiled methods, and neither would
669 // clean up the stack pointer changes performed by the two adapters.
670 // If this happens, control eventually transfers back to the compiled
671 // caller, but with an uncorrected stack, causing delayed havoc.
672
673 // Pick up the return address
674 __ movptr(rax, Address(rsp, 0));
675
676 if (VerifyAdapterCalls &&
677 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) {
678 // So, let's test for cascading c2i/i2c adapters right now.
679 // assert(Interpreter::contains($return_addr) ||
680 // StubRoutines::contains($return_addr),
681 // "i2c adapter must return to an interpreter frame");
682 __ block_comment("verify_i2c { ");
683 Label L_ok;
684 if (Interpreter::code() != NULL)
685 range_check(masm, rax, r11,
686 Interpreter::code()->code_start(), Interpreter::code()->code_end(),
687 L_ok);
688 if (StubRoutines::code1() != NULL)
689 range_check(masm, rax, r11,
690 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(),
691 L_ok);
692 if (StubRoutines::code2() != NULL)
693 range_check(masm, rax, r11,
694 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(),
695 L_ok);
696 const char* msg = "i2c adapter must return to an interpreter frame";
697 __ block_comment(msg);
698 __ stop(msg);
699 __ bind(L_ok);
700 __ block_comment("} verify_i2ce ");
701 }
702
703 // Must preserve original SP for loading incoming arguments because
704 // we need to align the outgoing SP for compiled code.
705 __ movptr(r11, rsp);
706
707 // Cut-out for having no stack args. Since up to 2 int/oop args are passed
708 // in registers, we will occasionally have no stack args.
709 int comp_words_on_stack = 0;
710 if (comp_args_on_stack) {
711 // Sig words on the stack are greater-than VMRegImpl::stack0. Those in
712 // registers are below. By subtracting stack0, we either get a negative
713 // number (all values in registers) or the maximum stack slot accessed.
714
715 // Convert 4-byte c2 stack slots to words.
716 comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
717 // Round up to miminum stack alignment, in wordSize
718 comp_words_on_stack = round_to(comp_words_on_stack, 2);
719 __ subptr(rsp, comp_words_on_stack * wordSize);
720 }
721
722
723 // Ensure compiled code always sees stack at proper alignment
724 __ andptr(rsp, -16);
725
726 // push the return address and misalign the stack that youngest frame always sees
727 // as far as the placement of the call instruction
728 __ push(rax);
729
730 // Put saved SP in another register
731 const Register saved_sp = rax;
732 __ movptr(saved_sp, r11);
733
734 // Will jump to the compiled code just as if compiled code was doing it.
735 // Pre-load the register-jump target early, to schedule it better.
736 __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_offset())));
737
738 // Now generate the shuffle code. Pick up all register args and move the
739 // rest through the floating point stack top.
740 for (int i = 0; i < total_args_passed; i++) {
741 if (sig_bt[i] == T_VOID) {
742 // Longs and doubles are passed in native word order, but misaligned
743 // in the 32-bit build.
744 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
745 continue;
746 }
747
748 // Pick up 0, 1 or 2 words from SP+offset.
749
750 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
751 "scrambled load targets?");
752 // Load in argument order going down.
753 int ld_off = (total_args_passed - i)*Interpreter::stackElementSize;
754 // Point to interpreter value (vs. tag)
755 int next_off = ld_off - Interpreter::stackElementSize;
756 //
757 //
758 //
759 VMReg r_1 = regs[i].first();
760 VMReg r_2 = regs[i].second();
761 if (!r_1->is_valid()) {
762 assert(!r_2->is_valid(), "");
763 continue;
764 }
765 if (r_1->is_stack()) {
766 // Convert stack slot to an SP offset (+ wordSize to account for return address )
767 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
768
769 // We can use r13 as a temp here because compiled code doesn't need r13 as an input
770 // and if we end up going thru a c2i because of a miss a reasonable value of r13
771 // will be generated.
772 if (!r_2->is_valid()) {
773 // sign extend???
774 __ movl(r13, Address(saved_sp, ld_off));
775 __ movptr(Address(rsp, st_off), r13);
776 } else {
777 //
778 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
779 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
780 // So we must adjust where to pick up the data to match the interpreter.
781 //
782 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
783 // are accessed as negative so LSW is at LOW address
784
785 // ld_off is MSW so get LSW
786 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
787 next_off : ld_off;
788 __ movq(r13, Address(saved_sp, offset));
789 // st_off is LSW (i.e. reg.first())
790 __ movq(Address(rsp, st_off), r13);
791 }
792 } else if (r_1->is_Register()) { // Register argument
793 Register r = r_1->as_Register();
794 assert(r != rax, "must be different");
795 if (r_2->is_valid()) {
796 //
797 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
798 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
799 // So we must adjust where to pick up the data to match the interpreter.
800
801 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
802 next_off : ld_off;
803
804 // this can be a misaligned move
805 __ movq(r, Address(saved_sp, offset));
806 } else {
807 // sign extend and use a full word?
808 __ movl(r, Address(saved_sp, ld_off));
809 }
810 } else {
811 if (!r_2->is_valid()) {
812 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
813 } else {
814 __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off));
815 }
816 }
817 }
818
819 // 6243940 We might end up in handle_wrong_method if
820 // the callee is deoptimized as we race thru here. If that
821 // happens we don't want to take a safepoint because the
822 // caller frame will look interpreted and arguments are now
823 // "compiled" so it is much better to make this transition
824 // invisible to the stack walking code. Unfortunately if
825 // we try and find the callee by normal means a safepoint
826 // is possible. So we stash the desired callee in the thread
827 // and the vm will find there should this case occur.
828
829 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
830
831 // put Method* where a c2i would expect should we end up there
832 // only needed becaus eof c2 resolve stubs return Method* as a result in
833 // rax
834 __ mov(rax, rbx);
835 __ jmp(r11);
836 }
837
838 // ---------------------------------------------------------------
839 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
840 int total_args_passed,
841 int comp_args_on_stack,
842 const BasicType *sig_bt,
843 const VMRegPair *regs,
844 AdapterFingerPrint* fingerprint) {
845 address i2c_entry = __ pc();
846
847 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
848
849 // -------------------------------------------------------------------------
850 // Generate a C2I adapter. On entry we know rbx holds the Method* during calls
851 // to the interpreter. The args start out packed in the compiled layout. They
852 // need to be unpacked into the interpreter layout. This will almost always
853 // require some stack space. We grow the current (compiled) stack, then repack
854 // the args. We finally end in a jump to the generic interpreter entry point.
855 // On exit from the interpreter, the interpreter will restore our SP (lest the
856 // compiled code, which relys solely on SP and not RBP, get sick).
857
858 address c2i_unverified_entry = __ pc();
859 Label skip_fixup;
860 Label ok;
861
862 Register holder = rax;
863 Register receiver = j_rarg0;
864 Register temp = rbx;
865
866 {
867 __ load_klass(temp, receiver);
868 __ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset()));
869 __ movptr(rbx, Address(holder, CompiledICHolder::holder_method_offset()));
870 __ jcc(Assembler::equal, ok);
871 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
872
873 __ bind(ok);
874 // Method might have been compiled since the call site was patched to
875 // interpreted if that is the case treat it as a miss so we can get
876 // the call site corrected.
877 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD);
878 __ jcc(Assembler::equal, skip_fixup);
879 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
880 }
881
882 address c2i_entry = __ pc();
883
884 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
885
886 __ flush();
887 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
888 }
889
890 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
891 VMRegPair *regs,
892 int total_args_passed) {
893 // We return the amount of VMRegImpl stack slots we need to reserve for all
894 // the arguments NOT counting out_preserve_stack_slots.
895
896 // NOTE: These arrays will have to change when c1 is ported
897 #ifdef _WIN64
898 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
899 c_rarg0, c_rarg1, c_rarg2, c_rarg3
900 };
901 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
902 c_farg0, c_farg1, c_farg2, c_farg3
903 };
904 #else
905 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
906 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5
907 };
908 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
909 c_farg0, c_farg1, c_farg2, c_farg3,
910 c_farg4, c_farg5, c_farg6, c_farg7
911 };
912 #endif // _WIN64
913
914
915 uint int_args = 0;
916 uint fp_args = 0;
917 uint stk_args = 0; // inc by 2 each time
918
919 for (int i = 0; i < total_args_passed; i++) {
920 switch (sig_bt[i]) {
921 case T_BOOLEAN:
922 case T_CHAR:
923 case T_BYTE:
924 case T_SHORT:
925 case T_INT:
926 if (int_args < Argument::n_int_register_parameters_c) {
927 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
928 #ifdef _WIN64
929 fp_args++;
930 // Allocate slots for callee to stuff register args the stack.
931 stk_args += 2;
932 #endif
933 } else {
934 regs[i].set1(VMRegImpl::stack2reg(stk_args));
935 stk_args += 2;
936 }
937 break;
938 case T_LONG:
939 assert(sig_bt[i + 1] == T_VOID, "expecting half");
940 // fall through
941 case T_OBJECT:
942 case T_ARRAY:
943 case T_ADDRESS:
944 case T_METADATA:
945 if (int_args < Argument::n_int_register_parameters_c) {
946 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
947 #ifdef _WIN64
948 fp_args++;
949 stk_args += 2;
950 #endif
951 } else {
952 regs[i].set2(VMRegImpl::stack2reg(stk_args));
953 stk_args += 2;
954 }
955 break;
956 case T_FLOAT:
957 if (fp_args < Argument::n_float_register_parameters_c) {
958 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
959 #ifdef _WIN64
960 int_args++;
961 // Allocate slots for callee to stuff register args the stack.
962 stk_args += 2;
963 #endif
964 } else {
965 regs[i].set1(VMRegImpl::stack2reg(stk_args));
966 stk_args += 2;
967 }
968 break;
969 case T_DOUBLE:
970 assert(sig_bt[i + 1] == T_VOID, "expecting half");
971 if (fp_args < Argument::n_float_register_parameters_c) {
972 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
973 #ifdef _WIN64
974 int_args++;
975 // Allocate slots for callee to stuff register args the stack.
976 stk_args += 2;
977 #endif
978 } else {
979 regs[i].set2(VMRegImpl::stack2reg(stk_args));
980 stk_args += 2;
981 }
982 break;
983 case T_VOID: // Halves of longs and doubles
984 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
985 regs[i].set_bad();
986 break;
987 default:
988 ShouldNotReachHere();
989 break;
990 }
991 }
992 #ifdef _WIN64
993 // windows abi requires that we always allocate enough stack space
994 // for 4 64bit registers to be stored down.
995 if (stk_args < 8) {
996 stk_args = 8;
997 }
998 #endif // _WIN64
999
1000 return stk_args;
1001 }
1002
1003 // On 64 bit we will store integer like items to the stack as
1004 // 64 bits items (sparc abi) even though java would only store
1005 // 32bits for a parameter. On 32bit it will simply be 32 bits
1006 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
1007 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1008 if (src.first()->is_stack()) {
1009 if (dst.first()->is_stack()) {
1010 // stack to stack
1011 __ movslq(rax, Address(rbp, reg2offset_in(src.first())));
1012 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1013 } else {
1014 // stack to reg
1015 __ movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1016 }
1017 } else if (dst.first()->is_stack()) {
1018 // reg to stack
1019 // Do we really have to sign extend???
1020 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1021 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1022 } else {
1023 // Do we really have to sign extend???
1024 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1025 if (dst.first() != src.first()) {
1026 __ movq(dst.first()->as_Register(), src.first()->as_Register());
1027 }
1028 }
1029 }
1030
1031 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1032 if (src.first()->is_stack()) {
1033 if (dst.first()->is_stack()) {
1034 // stack to stack
1035 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1036 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1037 } else {
1038 // stack to reg
1039 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1040 }
1041 } else if (dst.first()->is_stack()) {
1042 // reg to stack
1043 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1044 } else {
1045 if (dst.first() != src.first()) {
1046 __ movq(dst.first()->as_Register(), src.first()->as_Register());
1047 }
1048 }
1049 }
1050
1051 // An oop arg. Must pass a handle not the oop itself
1052 static void object_move(MacroAssembler* masm,
1053 OopMap* map,
1054 int oop_handle_offset,
1055 int framesize_in_slots,
1056 VMRegPair src,
1057 VMRegPair dst,
1058 bool is_receiver,
1059 int* receiver_offset) {
1060
1061 // must pass a handle. First figure out the location we use as a handle
1062
1063 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1064
1065 // See if oop is NULL if it is we need no handle
1066
1067 if (src.first()->is_stack()) {
1068
1069 // Oop is already on the stack as an argument
1070 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1071 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1072 if (is_receiver) {
1073 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1074 }
1075
1076 __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
1077 __ lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1078 // conditionally move a NULL
1079 __ cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1080 } else {
1081
1082 // Oop is in an a register we must store it to the space we reserve
1083 // on the stack for oop_handles and pass a handle if oop is non-NULL
1084
1085 const Register rOop = src.first()->as_Register();
1086 int oop_slot;
1087 if (rOop == j_rarg0)
1088 oop_slot = 0;
1089 else if (rOop == j_rarg1)
1090 oop_slot = 1;
1091 else if (rOop == j_rarg2)
1092 oop_slot = 2;
1093 else if (rOop == j_rarg3)
1094 oop_slot = 3;
1095 else if (rOop == j_rarg4)
1096 oop_slot = 4;
1097 else {
1098 assert(rOop == j_rarg5, "wrong register");
1099 oop_slot = 5;
1100 }
1101
1102 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1103 int offset = oop_slot*VMRegImpl::stack_slot_size;
1104
1105 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1106 // Store oop in handle area, may be NULL
1107 __ movptr(Address(rsp, offset), rOop);
1108 if (is_receiver) {
1109 *receiver_offset = offset;
1110 }
1111
1112 __ cmpptr(rOop, (int32_t)NULL_WORD);
1113 __ lea(rHandle, Address(rsp, offset));
1114 // conditionally move a NULL from the handle area where it was just stored
1115 __ cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1116 }
1117
1118 // If arg is on the stack then place it otherwise it is already in correct reg.
1119 if (dst.first()->is_stack()) {
1120 __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1121 }
1122 }
1123
1124 // A float arg may have to do float reg int reg conversion
1125 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1126 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
1127
1128 // The calling conventions assures us that each VMregpair is either
1129 // all really one physical register or adjacent stack slots.
1130 // This greatly simplifies the cases here compared to sparc.
1131
1132 if (src.first()->is_stack()) {
1133 if (dst.first()->is_stack()) {
1134 __ movl(rax, Address(rbp, reg2offset_in(src.first())));
1135 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
1136 } else {
1137 // stack to reg
1138 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1139 __ movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first())));
1140 }
1141 } else if (dst.first()->is_stack()) {
1142 // reg to stack
1143 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1144 __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1145 } else {
1146 // reg to reg
1147 // In theory these overlap but the ordering is such that this is likely a nop
1148 if ( src.first() != dst.first()) {
1149 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1150 }
1151 }
1152 }
1153
1154 // A long move
1155 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1156
1157 // The calling conventions assures us that each VMregpair is either
1158 // all really one physical register or adjacent stack slots.
1159 // This greatly simplifies the cases here compared to sparc.
1160
1161 if (src.is_single_phys_reg() ) {
1162 if (dst.is_single_phys_reg()) {
1163 if (dst.first() != src.first()) {
1164 __ mov(dst.first()->as_Register(), src.first()->as_Register());
1165 }
1166 } else {
1167 assert(dst.is_single_reg(), "not a stack pair");
1168 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1169 }
1170 } else if (dst.is_single_phys_reg()) {
1171 assert(src.is_single_reg(), "not a stack pair");
1172 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first())));
1173 } else {
1174 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
1175 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1176 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1177 }
1178 }
1179
1180 // A double move
1181 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1182
1183 // The calling conventions assures us that each VMregpair is either
1184 // all really one physical register or adjacent stack slots.
1185 // This greatly simplifies the cases here compared to sparc.
1186
1187 if (src.is_single_phys_reg() ) {
1188 if (dst.is_single_phys_reg()) {
1189 // In theory these overlap but the ordering is such that this is likely a nop
1190 if ( src.first() != dst.first()) {
1191 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1192 }
1193 } else {
1194 assert(dst.is_single_reg(), "not a stack pair");
1195 __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1196 }
1197 } else if (dst.is_single_phys_reg()) {
1198 assert(src.is_single_reg(), "not a stack pair");
1199 __ movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first())));
1200 } else {
1201 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
1202 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1203 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1204 }
1205 }
1206
1207
1208 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1209 // We always ignore the frame_slots arg and just use the space just below frame pointer
1210 // which by this time is free to use
1211 switch (ret_type) {
1212 case T_FLOAT:
1213 __ movflt(Address(rbp, -wordSize), xmm0);
1214 break;
1215 case T_DOUBLE:
1216 __ movdbl(Address(rbp, -wordSize), xmm0);
1217 break;
1218 case T_VOID: break;
1219 default: {
1220 __ movptr(Address(rbp, -wordSize), rax);
1221 }
1222 }
1223 }
1224
1225 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1226 // We always ignore the frame_slots arg and just use the space just below frame pointer
1227 // which by this time is free to use
1228 switch (ret_type) {
1229 case T_FLOAT:
1230 __ movflt(xmm0, Address(rbp, -wordSize));
1231 break;
1232 case T_DOUBLE:
1233 __ movdbl(xmm0, Address(rbp, -wordSize));
1234 break;
1235 case T_VOID: break;
1236 default: {
1237 __ movptr(rax, Address(rbp, -wordSize));
1238 }
1239 }
1240 }
1241
1242 static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
1243 for ( int i = first_arg ; i < arg_count ; i++ ) {
1244 if (args[i].first()->is_Register()) {
1245 __ push(args[i].first()->as_Register());
1246 } else if (args[i].first()->is_XMMRegister()) {
1247 __ subptr(rsp, 2*wordSize);
1248 __ movdbl(Address(rsp, 0), args[i].first()->as_XMMRegister());
1249 }
1250 }
1251 }
1252
1253 static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
1254 for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) {
1255 if (args[i].first()->is_Register()) {
1256 __ pop(args[i].first()->as_Register());
1257 } else if (args[i].first()->is_XMMRegister()) {
1258 __ movdbl(args[i].first()->as_XMMRegister(), Address(rsp, 0));
1259 __ addptr(rsp, 2*wordSize);
1260 }
1261 }
1262 }
1263
1264
1265 static void save_or_restore_arguments(MacroAssembler* masm,
1266 const int stack_slots,
1267 const int total_in_args,
1268 const int arg_save_area,
1269 OopMap* map,
1270 VMRegPair* in_regs,
1271 BasicType* in_sig_bt) {
1272 // if map is non-NULL then the code should store the values,
1273 // otherwise it should load them.
1274 int slot = arg_save_area;
1275 // Save down double word first
1276 for ( int i = 0; i < total_in_args; i++) {
1277 if (in_regs[i].first()->is_XMMRegister() && in_sig_bt[i] == T_DOUBLE) {
1278 int offset = slot * VMRegImpl::stack_slot_size;
1279 slot += VMRegImpl::slots_per_word;
1280 assert(slot <= stack_slots, "overflow");
1281 if (map != NULL) {
1282 __ movdbl(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
1283 } else {
1284 __ movdbl(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
1285 }
1286 }
1287 if (in_regs[i].first()->is_Register() &&
1288 (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_ARRAY)) {
1289 int offset = slot * VMRegImpl::stack_slot_size;
1290 if (map != NULL) {
1291 __ movq(Address(rsp, offset), in_regs[i].first()->as_Register());
1292 if (in_sig_bt[i] == T_ARRAY) {
1293 map->set_oop(VMRegImpl::stack2reg(slot));;
1294 }
1295 } else {
1296 __ movq(in_regs[i].first()->as_Register(), Address(rsp, offset));
1297 }
1298 slot += VMRegImpl::slots_per_word;
1299 }
1300 }
1301 // Save or restore single word registers
1302 for ( int i = 0; i < total_in_args; i++) {
1303 if (in_regs[i].first()->is_Register()) {
1304 int offset = slot * VMRegImpl::stack_slot_size;
1305 slot++;
1306 assert(slot <= stack_slots, "overflow");
1307
1308 // Value is in an input register pass we must flush it to the stack
1309 const Register reg = in_regs[i].first()->as_Register();
1310 switch (in_sig_bt[i]) {
1311 case T_BOOLEAN:
1312 case T_CHAR:
1313 case T_BYTE:
1314 case T_SHORT:
1315 case T_INT:
1316 if (map != NULL) {
1317 __ movl(Address(rsp, offset), reg);
1318 } else {
1319 __ movl(reg, Address(rsp, offset));
1320 }
1321 break;
1322 case T_ARRAY:
1323 case T_LONG:
1324 // handled above
1325 break;
1326 case T_OBJECT:
1327 default: ShouldNotReachHere();
1328 }
1329 } else if (in_regs[i].first()->is_XMMRegister()) {
1330 if (in_sig_bt[i] == T_FLOAT) {
1331 int offset = slot * VMRegImpl::stack_slot_size;
1332 slot++;
1333 assert(slot <= stack_slots, "overflow");
1334 if (map != NULL) {
1335 __ movflt(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
1336 } else {
1337 __ movflt(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
1338 }
1339 }
1340 } else if (in_regs[i].first()->is_stack()) {
1341 if (in_sig_bt[i] == T_ARRAY && map != NULL) {
1342 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1343 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
1344 }
1345 }
1346 }
1347 }
1348
1349
1350 // Check GC_locker::needs_gc and enter the runtime if it's true. This
1351 // keeps a new JNI critical region from starting until a GC has been
1352 // forced. Save down any oops in registers and describe them in an
1353 // OopMap.
1354 static void check_needs_gc_for_critical_native(MacroAssembler* masm,
1355 int stack_slots,
1356 int total_c_args,
1357 int total_in_args,
1358 int arg_save_area,
1359 OopMapSet* oop_maps,
1360 VMRegPair* in_regs,
1361 BasicType* in_sig_bt) {
1362 __ block_comment("check GC_locker::needs_gc");
1363 Label cont;
1364 __ cmp8(ExternalAddress((address)GC_locker::needs_gc_address()), false);
1365 __ jcc(Assembler::equal, cont);
1366
1367 // Save down any incoming oops and call into the runtime to halt for a GC
1368
1369 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1370 save_or_restore_arguments(masm, stack_slots, total_in_args,
1371 arg_save_area, map, in_regs, in_sig_bt);
1372
1373 address the_pc = __ pc();
1374 oop_maps->add_gc_map( __ offset(), map);
1375 __ set_last_Java_frame(rsp, noreg, the_pc);
1376
1377 __ block_comment("block_for_jni_critical");
1378 __ movptr(c_rarg0, r15_thread);
1379 __ mov(r12, rsp); // remember sp
1380 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
1381 __ andptr(rsp, -16); // align stack as required by ABI
1382 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical)));
1383 __ mov(rsp, r12); // restore sp
1384 __ reinit_heapbase();
1385
1386 __ reset_last_Java_frame(false, true);
1387
1388 save_or_restore_arguments(masm, stack_slots, total_in_args,
1389 arg_save_area, NULL, in_regs, in_sig_bt);
1390
1391 __ bind(cont);
1392 #ifdef ASSERT
1393 if (StressCriticalJNINatives) {
1394 // Stress register saving
1395 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1396 save_or_restore_arguments(masm, stack_slots, total_in_args,
1397 arg_save_area, map, in_regs, in_sig_bt);
1398 // Destroy argument registers
1399 for (int i = 0; i < total_in_args - 1; i++) {
1400 if (in_regs[i].first()->is_Register()) {
1401 const Register reg = in_regs[i].first()->as_Register();
1402 __ xorptr(reg, reg);
1403 } else if (in_regs[i].first()->is_XMMRegister()) {
1404 __ xorpd(in_regs[i].first()->as_XMMRegister(), in_regs[i].first()->as_XMMRegister());
1405 } else if (in_regs[i].first()->is_FloatRegister()) {
1406 ShouldNotReachHere();
1407 } else if (in_regs[i].first()->is_stack()) {
1408 // Nothing to do
1409 } else {
1410 ShouldNotReachHere();
1411 }
1412 if (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_DOUBLE) {
1413 i++;
1414 }
1415 }
1416
1417 save_or_restore_arguments(masm, stack_slots, total_in_args,
1418 arg_save_area, NULL, in_regs, in_sig_bt);
1419 }
1420 #endif
1421 }
1422
1423 // Unpack an array argument into a pointer to the body and the length
1424 // if the array is non-null, otherwise pass 0 for both.
1425 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) {
1426 Register tmp_reg = rax;
1427 assert(!body_arg.first()->is_Register() || body_arg.first()->as_Register() != tmp_reg,
1428 "possible collision");
1429 assert(!length_arg.first()->is_Register() || length_arg.first()->as_Register() != tmp_reg,
1430 "possible collision");
1431
1432 __ block_comment("unpack_array_argument {");
1433
1434 // Pass the length, ptr pair
1435 Label is_null, done;
1436 VMRegPair tmp;
1437 tmp.set_ptr(tmp_reg->as_VMReg());
1438 if (reg.first()->is_stack()) {
1439 // Load the arg up from the stack
1440 move_ptr(masm, reg, tmp);
1441 reg = tmp;
1442 }
1443 __ testptr(reg.first()->as_Register(), reg.first()->as_Register());
1444 __ jccb(Assembler::equal, is_null);
1445 __ lea(tmp_reg, Address(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type)));
1446 move_ptr(masm, tmp, body_arg);
1447 // load the length relative to the body.
1448 __ movl(tmp_reg, Address(tmp_reg, arrayOopDesc::length_offset_in_bytes() -
1449 arrayOopDesc::base_offset_in_bytes(in_elem_type)));
1450 move32_64(masm, tmp, length_arg);
1451 __ jmpb(done);
1452 __ bind(is_null);
1453 // Pass zeros
1454 __ xorptr(tmp_reg, tmp_reg);
1455 move_ptr(masm, tmp, body_arg);
1456 move32_64(masm, tmp, length_arg);
1457 __ bind(done);
1458
1459 __ block_comment("} unpack_array_argument");
1460 }
1461
1462
1463 // Different signatures may require very different orders for the move
1464 // to avoid clobbering other arguments. There's no simple way to
1465 // order them safely. Compute a safe order for issuing stores and
1466 // break any cycles in those stores. This code is fairly general but
1467 // it's not necessary on the other platforms so we keep it in the
1468 // platform dependent code instead of moving it into a shared file.
1469 // (See bugs 7013347 & 7145024.)
1470 // Note that this code is specific to LP64.
1471 class ComputeMoveOrder: public StackObj {
1472 class MoveOperation: public ResourceObj {
1473 friend class ComputeMoveOrder;
1474 private:
1475 VMRegPair _src;
1476 VMRegPair _dst;
1477 int _src_index;
1478 int _dst_index;
1479 bool _processed;
1480 MoveOperation* _next;
1481 MoveOperation* _prev;
1482
1483 static int get_id(VMRegPair r) {
1484 return r.first()->value();
1485 }
1486
1487 public:
1488 MoveOperation(int src_index, VMRegPair src, int dst_index, VMRegPair dst):
1489 _src(src)
1490 , _src_index(src_index)
1491 , _dst(dst)
1492 , _dst_index(dst_index)
1493 , _next(NULL)
1494 , _prev(NULL)
1495 , _processed(false) {
1496 }
1497
1498 VMRegPair src() const { return _src; }
1499 int src_id() const { return get_id(src()); }
1500 int src_index() const { return _src_index; }
1501 VMRegPair dst() const { return _dst; }
1502 void set_dst(int i, VMRegPair dst) { _dst_index = i, _dst = dst; }
1503 int dst_index() const { return _dst_index; }
1504 int dst_id() const { return get_id(dst()); }
1505 MoveOperation* next() const { return _next; }
1506 MoveOperation* prev() const { return _prev; }
1507 void set_processed() { _processed = true; }
1508 bool is_processed() const { return _processed; }
1509
1510 // insert
1511 void break_cycle(VMRegPair temp_register) {
1512 // create a new store following the last store
1513 // to move from the temp_register to the original
1514 MoveOperation* new_store = new MoveOperation(-1, temp_register, dst_index(), dst());
1515
1516 // break the cycle of links and insert new_store at the end
1517 // break the reverse link.
1518 MoveOperation* p = prev();
1519 assert(p->next() == this, "must be");
1520 _prev = NULL;
1521 p->_next = new_store;
1522 new_store->_prev = p;
1523
1524 // change the original store to save it's value in the temp.
1525 set_dst(-1, temp_register);
1526 }
1527
1528 void link(GrowableArray<MoveOperation*>& killer) {
1529 // link this store in front the store that it depends on
1530 MoveOperation* n = killer.at_grow(src_id(), NULL);
1531 if (n != NULL) {
1532 assert(_next == NULL && n->_prev == NULL, "shouldn't have been set yet");
1533 _next = n;
1534 n->_prev = this;
1535 }
1536 }
1537 };
1538
1539 private:
1540 GrowableArray<MoveOperation*> edges;
1541
1542 public:
1543 ComputeMoveOrder(int total_in_args, VMRegPair* in_regs, int total_c_args, VMRegPair* out_regs,
1544 BasicType* in_sig_bt, GrowableArray<int>& arg_order, VMRegPair tmp_vmreg) {
1545 // Move operations where the dest is the stack can all be
1546 // scheduled first since they can't interfere with the other moves.
1547 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) {
1548 if (in_sig_bt[i] == T_ARRAY) {
1549 c_arg--;
1550 if (out_regs[c_arg].first()->is_stack() &&
1551 out_regs[c_arg + 1].first()->is_stack()) {
1552 arg_order.push(i);
1553 arg_order.push(c_arg);
1554 } else {
1555 if (out_regs[c_arg].first()->is_stack() ||
1556 in_regs[i].first() == out_regs[c_arg].first()) {
1557 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg + 1]);
1558 } else {
1559 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]);
1560 }
1561 }
1562 } else if (in_sig_bt[i] == T_VOID) {
1563 arg_order.push(i);
1564 arg_order.push(c_arg);
1565 } else {
1566 if (out_regs[c_arg].first()->is_stack() ||
1567 in_regs[i].first() == out_regs[c_arg].first()) {
1568 arg_order.push(i);
1569 arg_order.push(c_arg);
1570 } else {
1571 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]);
1572 }
1573 }
1574 }
1575 // Break any cycles in the register moves and emit the in the
1576 // proper order.
1577 GrowableArray<MoveOperation*>* stores = get_store_order(tmp_vmreg);
1578 for (int i = 0; i < stores->length(); i++) {
1579 arg_order.push(stores->at(i)->src_index());
1580 arg_order.push(stores->at(i)->dst_index());
1581 }
1582 }
1583
1584 // Collected all the move operations
1585 void add_edge(int src_index, VMRegPair src, int dst_index, VMRegPair dst) {
1586 if (src.first() == dst.first()) return;
1587 edges.append(new MoveOperation(src_index, src, dst_index, dst));
1588 }
1589
1590 // Walk the edges breaking cycles between moves. The result list
1591 // can be walked in order to produce the proper set of loads
1592 GrowableArray<MoveOperation*>* get_store_order(VMRegPair temp_register) {
1593 // Record which moves kill which values
1594 GrowableArray<MoveOperation*> killer;
1595 for (int i = 0; i < edges.length(); i++) {
1596 MoveOperation* s = edges.at(i);
1597 assert(killer.at_grow(s->dst_id(), NULL) == NULL, "only one killer");
1598 killer.at_put_grow(s->dst_id(), s, NULL);
1599 }
1600 assert(killer.at_grow(MoveOperation::get_id(temp_register), NULL) == NULL,
1601 "make sure temp isn't in the registers that are killed");
1602
1603 // create links between loads and stores
1604 for (int i = 0; i < edges.length(); i++) {
1605 edges.at(i)->link(killer);
1606 }
1607
1608 // at this point, all the move operations are chained together
1609 // in a doubly linked list. Processing it backwards finds
1610 // the beginning of the chain, forwards finds the end. If there's
1611 // a cycle it can be broken at any point, so pick an edge and walk
1612 // backward until the list ends or we end where we started.
1613 GrowableArray<MoveOperation*>* stores = new GrowableArray<MoveOperation*>();
1614 for (int e = 0; e < edges.length(); e++) {
1615 MoveOperation* s = edges.at(e);
1616 if (!s->is_processed()) {
1617 MoveOperation* start = s;
1618 // search for the beginning of the chain or cycle
1619 while (start->prev() != NULL && start->prev() != s) {
1620 start = start->prev();
1621 }
1622 if (start->prev() == s) {
1623 start->break_cycle(temp_register);
1624 }
1625 // walk the chain forward inserting to store list
1626 while (start != NULL) {
1627 stores->append(start);
1628 start->set_processed();
1629 start = start->next();
1630 }
1631 }
1632 }
1633 return stores;
1634 }
1635 };
1636
1637 static void verify_oop_args(MacroAssembler* masm,
1638 methodHandle method,
1639 const BasicType* sig_bt,
1640 const VMRegPair* regs) {
1641 Register temp_reg = rbx; // not part of any compiled calling seq
1642 if (VerifyOops) {
1643 for (int i = 0; i < method->size_of_parameters(); i++) {
1644 if (sig_bt[i] == T_OBJECT ||
1645 sig_bt[i] == T_ARRAY) {
1646 VMReg r = regs[i].first();
1647 assert(r->is_valid(), "bad oop arg");
1648 if (r->is_stack()) {
1649 __ movptr(temp_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
1650 __ verify_oop(temp_reg);
1651 } else {
1652 __ verify_oop(r->as_Register());
1653 }
1654 }
1655 }
1656 }
1657 }
1658
1659 static void gen_special_dispatch(MacroAssembler* masm,
1660 methodHandle method,
1661 const BasicType* sig_bt,
1662 const VMRegPair* regs) {
1663 verify_oop_args(masm, method, sig_bt, regs);
1664 vmIntrinsics::ID iid = method->intrinsic_id();
1665
1666 // Now write the args into the outgoing interpreter space
1667 bool has_receiver = false;
1668 Register receiver_reg = noreg;
1669 int member_arg_pos = -1;
1670 Register member_reg = noreg;
1671 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid);
1672 if (ref_kind != 0) {
1673 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument
1674 member_reg = rbx; // known to be free at this point
1675 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind);
1676 } else if (iid == vmIntrinsics::_invokeBasic) {
1677 has_receiver = true;
1678 } else {
1679 fatal(err_msg_res("unexpected intrinsic id %d", iid));
1680 }
1681
1682 if (member_reg != noreg) {
1683 // Load the member_arg into register, if necessary.
1684 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs);
1685 VMReg r = regs[member_arg_pos].first();
1686 if (r->is_stack()) {
1687 __ movptr(member_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
1688 } else {
1689 // no data motion is needed
1690 member_reg = r->as_Register();
1691 }
1692 }
1693
1694 if (has_receiver) {
1695 // Make sure the receiver is loaded into a register.
1696 assert(method->size_of_parameters() > 0, "oob");
1697 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object");
1698 VMReg r = regs[0].first();
1699 assert(r->is_valid(), "bad receiver arg");
1700 if (r->is_stack()) {
1701 // Porting note: This assumes that compiled calling conventions always
1702 // pass the receiver oop in a register. If this is not true on some
1703 // platform, pick a temp and load the receiver from stack.
1704 fatal("receiver always in a register");
1705 receiver_reg = j_rarg0; // known to be free at this point
1706 __ movptr(receiver_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
1707 } else {
1708 // no data motion is needed
1709 receiver_reg = r->as_Register();
1710 }
1711 }
1712
1713 // Figure out which address we are really jumping to:
1714 MethodHandles::generate_method_handle_dispatch(masm, iid,
1715 receiver_reg, member_reg, /*for_compiler_entry:*/ true);
1716 }
1717
1718 // ---------------------------------------------------------------------------
1719 // Generate a native wrapper for a given method. The method takes arguments
1720 // in the Java compiled code convention, marshals them to the native
1721 // convention (handlizes oops, etc), transitions to native, makes the call,
1722 // returns to java state (possibly blocking), unhandlizes any result and
1723 // returns.
1724 //
1725 // Critical native functions are a shorthand for the use of
1726 // GetPrimtiveArrayCritical and disallow the use of any other JNI
1727 // functions. The wrapper is expected to unpack the arguments before
1728 // passing them to the callee and perform checks before and after the
1729 // native call to ensure that they GC_locker
1730 // lock_critical/unlock_critical semantics are followed. Some other
1731 // parts of JNI setup are skipped like the tear down of the JNI handle
1732 // block and the check for pending exceptions it's impossible for them
1733 // to be thrown.
1734 //
1735 // They are roughly structured like this:
1736 // if (GC_locker::needs_gc())
1737 // SharedRuntime::block_for_jni_critical();
1738 // tranistion to thread_in_native
1739 // unpack arrray arguments and call native entry point
1740 // check for safepoint in progress
1741 // check if any thread suspend flags are set
1742 // call into JVM and possible unlock the JNI critical
1743 // if a GC was suppressed while in the critical native.
1744 // transition back to thread_in_Java
1745 // return to caller
1746 //
1747 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
1748 methodHandle method,
1749 int compile_id,
1750 BasicType* in_sig_bt,
1751 VMRegPair* in_regs,
1752 BasicType ret_type) {
1753 if (method->is_method_handle_intrinsic()) {
1754 vmIntrinsics::ID iid = method->intrinsic_id();
1755 intptr_t start = (intptr_t)__ pc();
1756 int vep_offset = ((intptr_t)__ pc()) - start;
1757 gen_special_dispatch(masm,
1758 method,
1759 in_sig_bt,
1760 in_regs);
1761 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period
1762 __ flush();
1763 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually
1764 return nmethod::new_native_nmethod(method,
1765 compile_id,
1766 masm->code(),
1767 vep_offset,
1768 frame_complete,
1769 stack_slots / VMRegImpl::slots_per_word,
1770 in_ByteSize(-1),
1771 in_ByteSize(-1),
1772 (OopMapSet*)NULL);
1773 }
1774 bool is_critical_native = true;
1775 address native_func = method->critical_native_function();
1776 if (native_func == NULL) {
1777 native_func = method->native_function();
1778 is_critical_native = false;
1779 }
1780 assert(native_func != NULL, "must have function");
1781
1782 // An OopMap for lock (and class if static)
1783 OopMapSet *oop_maps = new OopMapSet();
1784 intptr_t start = (intptr_t)__ pc();
1785
1786 // We have received a description of where all the java arg are located
1787 // on entry to the wrapper. We need to convert these args to where
1788 // the jni function will expect them. To figure out where they go
1789 // we convert the java signature to a C signature by inserting
1790 // the hidden arguments as arg[0] and possibly arg[1] (static method)
1791
1792 const int total_in_args = method->size_of_parameters();
1793 int total_c_args = total_in_args;
1794 if (!is_critical_native) {
1795 total_c_args += 1;
1796 if (method->is_static()) {
1797 total_c_args++;
1798 }
1799 } else {
1800 for (int i = 0; i < total_in_args; i++) {
1801 if (in_sig_bt[i] == T_ARRAY) {
1802 total_c_args++;
1803 }
1804 }
1805 }
1806
1807 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
1808 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
1809 BasicType* in_elem_bt = NULL;
1810
1811 int argc = 0;
1812 if (!is_critical_native) {
1813 out_sig_bt[argc++] = T_ADDRESS;
1814 if (method->is_static()) {
1815 out_sig_bt[argc++] = T_OBJECT;
1816 }
1817
1818 for (int i = 0; i < total_in_args ; i++ ) {
1819 out_sig_bt[argc++] = in_sig_bt[i];
1820 }
1821 } else {
1822 Thread* THREAD = Thread::current();
1823 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args);
1824 SignatureStream ss(method->signature());
1825 for (int i = 0; i < total_in_args ; i++ ) {
1826 if (in_sig_bt[i] == T_ARRAY) {
1827 // Arrays are passed as int, elem* pair
1828 out_sig_bt[argc++] = T_INT;
1829 out_sig_bt[argc++] = T_ADDRESS;
1830 Symbol* atype = ss.as_symbol(CHECK_NULL);
1831 const char* at = atype->as_C_string();
1832 if (strlen(at) == 2) {
1833 assert(at[0] == '[', "must be");
1834 switch (at[1]) {
1835 case 'B': in_elem_bt[i] = T_BYTE; break;
1836 case 'C': in_elem_bt[i] = T_CHAR; break;
1837 case 'D': in_elem_bt[i] = T_DOUBLE; break;
1838 case 'F': in_elem_bt[i] = T_FLOAT; break;
1839 case 'I': in_elem_bt[i] = T_INT; break;
1840 case 'J': in_elem_bt[i] = T_LONG; break;
1841 case 'S': in_elem_bt[i] = T_SHORT; break;
1842 case 'Z': in_elem_bt[i] = T_BOOLEAN; break;
1843 default: ShouldNotReachHere();
1844 }
1845 }
1846 } else {
1847 out_sig_bt[argc++] = in_sig_bt[i];
1848 in_elem_bt[i] = T_VOID;
1849 }
1850 if (in_sig_bt[i] != T_VOID) {
1851 assert(in_sig_bt[i] == ss.type(), "must match");
1852 ss.next();
1853 }
1854 }
1855 }
1856
1857 // Now figure out where the args must be stored and how much stack space
1858 // they require.
1859 int out_arg_slots;
1860 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
1861
1862 // Compute framesize for the wrapper. We need to handlize all oops in
1863 // incoming registers
1864
1865 // Calculate the total number of stack slots we will need.
1866
1867 // First count the abi requirement plus all of the outgoing args
1868 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
1869
1870 // Now the space for the inbound oop handle area
1871 int total_save_slots = 6 * VMRegImpl::slots_per_word; // 6 arguments passed in registers
1872 if (is_critical_native) {
1873 // Critical natives may have to call out so they need a save area
1874 // for register arguments.
1875 int double_slots = 0;
1876 int single_slots = 0;
1877 for ( int i = 0; i < total_in_args; i++) {
1878 if (in_regs[i].first()->is_Register()) {
1879 const Register reg = in_regs[i].first()->as_Register();
1880 switch (in_sig_bt[i]) {
1881 case T_BOOLEAN:
1882 case T_BYTE:
1883 case T_SHORT:
1884 case T_CHAR:
1885 case T_INT: single_slots++; break;
1886 case T_ARRAY: // specific to LP64 (7145024)
1887 case T_LONG: double_slots++; break;
1888 default: ShouldNotReachHere();
1889 }
1890 } else if (in_regs[i].first()->is_XMMRegister()) {
1891 switch (in_sig_bt[i]) {
1892 case T_FLOAT: single_slots++; break;
1893 case T_DOUBLE: double_slots++; break;
1894 default: ShouldNotReachHere();
1895 }
1896 } else if (in_regs[i].first()->is_FloatRegister()) {
1897 ShouldNotReachHere();
1898 }
1899 }
1900 total_save_slots = double_slots * 2 + single_slots;
1901 // align the save area
1902 if (double_slots != 0) {
1903 stack_slots = round_to(stack_slots, 2);
1904 }
1905 }
1906
1907 int oop_handle_offset = stack_slots;
1908 stack_slots += total_save_slots;
1909
1910 // Now any space we need for handlizing a klass if static method
1911
1912 int klass_slot_offset = 0;
1913 int klass_offset = -1;
1914 int lock_slot_offset = 0;
1915 bool is_static = false;
1916
1917 if (method->is_static()) {
1918 klass_slot_offset = stack_slots;
1919 stack_slots += VMRegImpl::slots_per_word;
1920 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
1921 is_static = true;
1922 }
1923
1924 // Plus a lock if needed
1925
1926 if (method->is_synchronized()) {
1927 lock_slot_offset = stack_slots;
1928 stack_slots += VMRegImpl::slots_per_word;
1929 }
1930
1931 // Now a place (+2) to save return values or temp during shuffling
1932 // + 4 for return address (which we own) and saved rbp
1933 stack_slots += 6;
1934
1935 // Ok The space we have allocated will look like:
1936 //
1937 //
1938 // FP-> | |
1939 // |---------------------|
1940 // | 2 slots for moves |
1941 // |---------------------|
1942 // | lock box (if sync) |
1943 // |---------------------| <- lock_slot_offset
1944 // | klass (if static) |
1945 // |---------------------| <- klass_slot_offset
1946 // | oopHandle area |
1947 // |---------------------| <- oop_handle_offset (6 java arg registers)
1948 // | outbound memory |
1949 // | based arguments |
1950 // | |
1951 // |---------------------|
1952 // | |
1953 // SP-> | out_preserved_slots |
1954 //
1955 //
1956
1957
1958 // Now compute actual number of stack words we need rounding to make
1959 // stack properly aligned.
1960 stack_slots = round_to(stack_slots, StackAlignmentInSlots);
1961
1962 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
1963
1964 // First thing make an ic check to see if we should even be here
1965
1966 // We are free to use all registers as temps without saving them and
1967 // restoring them except rbp. rbp is the only callee save register
1968 // as far as the interpreter and the compiler(s) are concerned.
1969
1970
1971 const Register ic_reg = rax;
1972 const Register receiver = j_rarg0;
1973
1974 Label hit;
1975 Label exception_pending;
1976
1977 assert_different_registers(ic_reg, receiver, rscratch1);
1978 __ verify_oop(receiver);
1979 __ load_klass(rscratch1, receiver);
1980 __ cmpq(ic_reg, rscratch1);
1981 __ jcc(Assembler::equal, hit);
1982
1983 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1984
1985 // Verified entry point must be aligned
1986 __ align(8);
1987
1988 __ bind(hit);
1989
1990 int vep_offset = ((intptr_t)__ pc()) - start;
1991
1992 // The instruction at the verified entry point must be 5 bytes or longer
1993 // because it can be patched on the fly by make_non_entrant. The stack bang
1994 // instruction fits that requirement.
1995
1996 // Generate stack overflow check
1997
1998 if (UseStackBanging) {
1999 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
2000 } else {
2001 // need a 5 byte instruction to allow MT safe patching to non-entrant
2002 __ fat_nop();
2003 }
2004
2005 // Generate a new frame for the wrapper.
2006 __ enter();
2007 // -2 because return address is already present and so is saved rbp
2008 __ subptr(rsp, stack_size - 2*wordSize);
2009
2010 // Frame is now completed as far as size and linkage.
2011 int frame_complete = ((intptr_t)__ pc()) - start;
2012
2013 if (UseRTMLocking) {
2014 // Abort RTM transaction before calling JNI
2015 // because critical section will be large and will be
2016 // aborted anyway. Also nmethod could be deoptimized.
2017 __ xabort(0);
2018 }
2019
2020 #ifdef ASSERT
2021 {
2022 Label L;
2023 __ mov(rax, rsp);
2024 __ andptr(rax, -16); // must be 16 byte boundary (see amd64 ABI)
2025 __ cmpptr(rax, rsp);
2026 __ jcc(Assembler::equal, L);
2027 __ stop("improperly aligned stack");
2028 __ bind(L);
2029 }
2030 #endif /* ASSERT */
2031
2032
2033 // We use r14 as the oop handle for the receiver/klass
2034 // It is callee save so it survives the call to native
2035
2036 const Register oop_handle_reg = r14;
2037
2038 if (is_critical_native) {
2039 check_needs_gc_for_critical_native(masm, stack_slots, total_c_args, total_in_args,
2040 oop_handle_offset, oop_maps, in_regs, in_sig_bt);
2041 }
2042
2043 //
2044 // We immediately shuffle the arguments so that any vm call we have to
2045 // make from here on out (sync slow path, jvmti, etc.) we will have
2046 // captured the oops from our caller and have a valid oopMap for
2047 // them.
2048
2049 // -----------------
2050 // The Grand Shuffle
2051
2052 // The Java calling convention is either equal (linux) or denser (win64) than the
2053 // c calling convention. However the because of the jni_env argument the c calling
2054 // convention always has at least one more (and two for static) arguments than Java.
2055 // Therefore if we move the args from java -> c backwards then we will never have
2056 // a register->register conflict and we don't have to build a dependency graph
2057 // and figure out how to break any cycles.
2058 //
2059
2060 // Record esp-based slot for receiver on stack for non-static methods
2061 int receiver_offset = -1;
2062
2063 // This is a trick. We double the stack slots so we can claim
2064 // the oops in the caller's frame. Since we are sure to have
2065 // more args than the caller doubling is enough to make
2066 // sure we can capture all the incoming oop args from the
2067 // caller.
2068 //
2069 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
2070
2071 // Mark location of rbp (someday)
2072 // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(rbp));
2073
2074 // Use eax, ebx as temporaries during any memory-memory moves we have to do
2075 // All inbound args are referenced based on rbp and all outbound args via rsp.
2076
2077
2078 #ifdef ASSERT
2079 bool reg_destroyed[RegisterImpl::number_of_registers];
2080 bool freg_destroyed[XMMRegisterImpl::number_of_registers];
2081 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
2082 reg_destroyed[r] = false;
2083 }
2084 for ( int f = 0 ; f < XMMRegisterImpl::number_of_registers ; f++ ) {
2085 freg_destroyed[f] = false;
2086 }
2087
2088 #endif /* ASSERT */
2089
2090 // This may iterate in two different directions depending on the
2091 // kind of native it is. The reason is that for regular JNI natives
2092 // the incoming and outgoing registers are offset upwards and for
2093 // critical natives they are offset down.
2094 GrowableArray<int> arg_order(2 * total_in_args);
2095 VMRegPair tmp_vmreg;
2096 tmp_vmreg.set1(rbx->as_VMReg());
2097
2098 if (!is_critical_native) {
2099 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) {
2100 arg_order.push(i);
2101 arg_order.push(c_arg);
2102 }
2103 } else {
2104 // Compute a valid move order, using tmp_vmreg to break any cycles
2105 ComputeMoveOrder cmo(total_in_args, in_regs, total_c_args, out_regs, in_sig_bt, arg_order, tmp_vmreg);
2106 }
2107
2108 int temploc = -1;
2109 for (int ai = 0; ai < arg_order.length(); ai += 2) {
2110 int i = arg_order.at(ai);
2111 int c_arg = arg_order.at(ai + 1);
2112 __ block_comment(err_msg("move %d -> %d", i, c_arg));
2113 if (c_arg == -1) {
2114 assert(is_critical_native, "should only be required for critical natives");
2115 // This arg needs to be moved to a temporary
2116 __ mov(tmp_vmreg.first()->as_Register(), in_regs[i].first()->as_Register());
2117 in_regs[i] = tmp_vmreg;
2118 temploc = i;
2119 continue;
2120 } else if (i == -1) {
2121 assert(is_critical_native, "should only be required for critical natives");
2122 // Read from the temporary location
2123 assert(temploc != -1, "must be valid");
2124 i = temploc;
2125 temploc = -1;
2126 }
2127 #ifdef ASSERT
2128 if (in_regs[i].first()->is_Register()) {
2129 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!");
2130 } else if (in_regs[i].first()->is_XMMRegister()) {
2131 assert(!freg_destroyed[in_regs[i].first()->as_XMMRegister()->encoding()], "destroyed reg!");
2132 }
2133 if (out_regs[c_arg].first()->is_Register()) {
2134 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
2135 } else if (out_regs[c_arg].first()->is_XMMRegister()) {
2136 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
2137 }
2138 #endif /* ASSERT */
2139 switch (in_sig_bt[i]) {
2140 case T_ARRAY:
2141 if (is_critical_native) {
2142 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]);
2143 c_arg++;
2144 #ifdef ASSERT
2145 if (out_regs[c_arg].first()->is_Register()) {
2146 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
2147 } else if (out_regs[c_arg].first()->is_XMMRegister()) {
2148 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
2149 }
2150 #endif
2151 break;
2152 }
2153 case T_OBJECT:
2154 assert(!is_critical_native, "no oop arguments");
2155 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
2156 ((i == 0) && (!is_static)),
2157 &receiver_offset);
2158 break;
2159 case T_VOID:
2160 break;
2161
2162 case T_FLOAT:
2163 float_move(masm, in_regs[i], out_regs[c_arg]);
2164 break;
2165
2166 case T_DOUBLE:
2167 assert( i + 1 < total_in_args &&
2168 in_sig_bt[i + 1] == T_VOID &&
2169 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2170 double_move(masm, in_regs[i], out_regs[c_arg]);
2171 break;
2172
2173 case T_LONG :
2174 long_move(masm, in_regs[i], out_regs[c_arg]);
2175 break;
2176
2177 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2178
2179 default:
2180 move32_64(masm, in_regs[i], out_regs[c_arg]);
2181 }
2182 }
2183
2184 int c_arg;
2185
2186 // Pre-load a static method's oop into r14. Used both by locking code and
2187 // the normal JNI call code.
2188 if (!is_critical_native) {
2189 // point c_arg at the first arg that is already loaded in case we
2190 // need to spill before we call out
2191 c_arg = total_c_args - total_in_args;
2192
2193 if (method->is_static()) {
2194
2195 // load oop into a register
2196 __ movoop(oop_handle_reg, JNIHandles::make_local(method->method_holder()->java_mirror()));
2197
2198 // Now handlize the static class mirror it's known not-null.
2199 __ movptr(Address(rsp, klass_offset), oop_handle_reg);
2200 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
2201
2202 // Now get the handle
2203 __ lea(oop_handle_reg, Address(rsp, klass_offset));
2204 // store the klass handle as second argument
2205 __ movptr(c_rarg1, oop_handle_reg);
2206 // and protect the arg if we must spill
2207 c_arg--;
2208 }
2209 } else {
2210 // For JNI critical methods we need to save all registers in save_args.
2211 c_arg = 0;
2212 }
2213
2214 // Change state to native (we save the return address in the thread, since it might not
2215 // be pushed on the stack when we do a a stack traversal). It is enough that the pc()
2216 // points into the right code segment. It does not have to be the correct return pc.
2217 // We use the same pc/oopMap repeatedly when we call out
2218
2219 intptr_t the_pc = (intptr_t) __ pc();
2220 oop_maps->add_gc_map(the_pc - start, map);
2221
2222 __ set_last_Java_frame(rsp, noreg, (address)the_pc);
2223
2224
2225 // We have all of the arguments setup at this point. We must not touch any register
2226 // argument registers at this point (what if we save/restore them there are no oop?
2227
2228 {
2229 SkipIfEqual skip(masm, &DTraceMethodProbes, false);
2230 // protect the args we've loaded
2231 save_args(masm, total_c_args, c_arg, out_regs);
2232 __ mov_metadata(c_rarg1, method());
2233 __ call_VM_leaf(
2234 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
2235 r15_thread, c_rarg1);
2236 restore_args(masm, total_c_args, c_arg, out_regs);
2237 }
2238
2239 // RedefineClasses() tracing support for obsolete method entry
2240 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
2241 // protect the args we've loaded
2242 save_args(masm, total_c_args, c_arg, out_regs);
2243 __ mov_metadata(c_rarg1, method());
2244 __ call_VM_leaf(
2245 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
2246 r15_thread, c_rarg1);
2247 restore_args(masm, total_c_args, c_arg, out_regs);
2248 }
2249
2250 // Lock a synchronized method
2251
2252 // Register definitions used by locking and unlocking
2253
2254 const Register swap_reg = rax; // Must use rax for cmpxchg instruction
2255 const Register obj_reg = rbx; // Will contain the oop
2256 const Register lock_reg = r13; // Address of compiler lock object (BasicLock)
2257 const Register old_hdr = r13; // value of old header at unlock time
2258
2259 Label slow_path_lock;
2260 Label lock_done;
2261
2262 if (method->is_synchronized()) {
2263 assert(!is_critical_native, "unhandled");
2264
2265
2266 const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
2267
2268 // Get the handle (the 2nd argument)
2269 __ mov(oop_handle_reg, c_rarg1);
2270
2271 // Get address of the box
2272
2273 __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2274
2275 // Load the oop from the handle
2276 __ movptr(obj_reg, Address(oop_handle_reg, 0));
2277
2278 if (UseBiasedLocking) {
2279 __ biased_locking_enter(lock_reg, obj_reg, swap_reg, rscratch1, false, lock_done, &slow_path_lock);
2280 }
2281
2282 // Load immediate 1 into swap_reg %rax
2283 __ movl(swap_reg, 1);
2284
2285 // Load (object->mark() | 1) into swap_reg %rax
2286 __ orptr(swap_reg, Address(obj_reg, 0));
2287
2288 // Save (object->mark() | 1) into BasicLock's displaced header
2289 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
2290
2291 if (os::is_MP()) {
2292 __ lock();
2293 }
2294
2295 // src -> dest iff dest == rax else rax <- dest
2296 __ cmpxchgptr(lock_reg, Address(obj_reg, 0));
2297 __ jcc(Assembler::equal, lock_done);
2298
2299 // Hmm should this move to the slow path code area???
2300
2301 // Test if the oopMark is an obvious stack pointer, i.e.,
2302 // 1) (mark & 3) == 0, and
2303 // 2) rsp <= mark < mark + os::pagesize()
2304 // These 3 tests can be done by evaluating the following
2305 // expression: ((mark - rsp) & (3 - os::vm_page_size())),
2306 // assuming both stack pointer and pagesize have their
2307 // least significant 2 bits clear.
2308 // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg
2309
2310 __ subptr(swap_reg, rsp);
2311 __ andptr(swap_reg, 3 - os::vm_page_size());
2312
2313 // Save the test result, for recursive case, the result is zero
2314 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
2315 __ jcc(Assembler::notEqual, slow_path_lock);
2316
2317 // Slow path will re-enter here
2318
2319 __ bind(lock_done);
2320 }
2321
2322
2323 // Finally just about ready to make the JNI call
2324
2325
2326 // get JNIEnv* which is first argument to native
2327 if (!is_critical_native) {
2328 __ lea(c_rarg0, Address(r15_thread, in_bytes(JavaThread::jni_environment_offset())));
2329 }
2330
2331 // Now set thread in native
2332 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native);
2333
2334 __ call(RuntimeAddress(native_func));
2335
2336 // Verify or restore cpu control state after JNI call
2337 __ restore_cpu_control_state_after_jni();
2338
2339 // Unpack native results.
2340 switch (ret_type) {
2341 case T_BOOLEAN: __ c2bool(rax); break;
2342 case T_CHAR : __ movzwl(rax, rax); break;
2343 case T_BYTE : __ sign_extend_byte (rax); break;
2344 case T_SHORT : __ sign_extend_short(rax); break;
2345 case T_INT : /* nothing to do */ break;
2346 case T_DOUBLE :
2347 case T_FLOAT :
2348 // Result is in xmm0 we'll save as needed
2349 break;
2350 case T_ARRAY: // Really a handle
2351 case T_OBJECT: // Really a handle
2352 break; // can't de-handlize until after safepoint check
2353 case T_VOID: break;
2354 case T_LONG: break;
2355 default : ShouldNotReachHere();
2356 }
2357
2358 // Switch thread to "native transition" state before reading the synchronization state.
2359 // This additional state is necessary because reading and testing the synchronization
2360 // state is not atomic w.r.t. GC, as this scenario demonstrates:
2361 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
2362 // VM thread changes sync state to synchronizing and suspends threads for GC.
2363 // Thread A is resumed to finish this native method, but doesn't block here since it
2364 // didn't see any synchronization is progress, and escapes.
2365 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
2366
2367 if(os::is_MP()) {
2368 if (UseMembar) {
2369 // Force this write out before the read below
2370 __ membar(Assembler::Membar_mask_bits(
2371 Assembler::LoadLoad | Assembler::LoadStore |
2372 Assembler::StoreLoad | Assembler::StoreStore));
2373 } else {
2374 // Write serialization page so VM thread can do a pseudo remote membar.
2375 // We use the current thread pointer to calculate a thread specific
2376 // offset to write to within the page. This minimizes bus traffic
2377 // due to cache line collision.
2378 __ serialize_memory(r15_thread, rcx);
2379 }
2380 }
2381
2382 Label after_transition;
2383
2384 // check for safepoint operation in progress and/or pending suspend requests
2385 {
2386 Label Continue;
2387
2388 __ cmp32(ExternalAddress((address)SafepointSynchronize::address_of_state()),
2389 SafepointSynchronize::_not_synchronized);
2390
2391 Label L;
2392 __ jcc(Assembler::notEqual, L);
2393 __ cmpl(Address(r15_thread, JavaThread::suspend_flags_offset()), 0);
2394 __ jcc(Assembler::equal, Continue);
2395 __ bind(L);
2396
2397 // Don't use call_VM as it will see a possible pending exception and forward it
2398 // and never return here preventing us from clearing _last_native_pc down below.
2399 // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are
2400 // preserved and correspond to the bcp/locals pointers. So we do a runtime call
2401 // by hand.
2402 //
2403 save_native_result(masm, ret_type, stack_slots);
2404 __ mov(c_rarg0, r15_thread);
2405 __ mov(r12, rsp); // remember sp
2406 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2407 __ andptr(rsp, -16); // align stack as required by ABI
2408 if (!is_critical_native) {
2409 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans)));
2410 } else {
2411 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition)));
2412 }
2413 __ mov(rsp, r12); // restore sp
2414 __ reinit_heapbase();
2415 // Restore any method result value
2416 restore_native_result(masm, ret_type, stack_slots);
2417
2418 if (is_critical_native) {
2419 // The call above performed the transition to thread_in_Java so
2420 // skip the transition logic below.
2421 __ jmpb(after_transition);
2422 }
2423
2424 __ bind(Continue);
2425 }
2426
2427 // change thread state
2428 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_Java);
2429 __ bind(after_transition);
2430
2431 Label reguard;
2432 Label reguard_done;
2433 __ cmpl(Address(r15_thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled);
2434 __ jcc(Assembler::equal, reguard);
2435 __ bind(reguard_done);
2436
2437 // native result if any is live
2438
2439 // Unlock
2440 Label unlock_done;
2441 Label slow_path_unlock;
2442 if (method->is_synchronized()) {
2443
2444 // Get locked oop from the handle we passed to jni
2445 __ movptr(obj_reg, Address(oop_handle_reg, 0));
2446
2447 Label done;
2448
2449 if (UseBiasedLocking) {
2450 __ biased_locking_exit(obj_reg, old_hdr, done);
2451 }
2452
2453 // Simple recursive lock?
2454
2455 __ cmpptr(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int32_t)NULL_WORD);
2456 __ jcc(Assembler::equal, done);
2457
2458 // Must save rax if if it is live now because cmpxchg must use it
2459 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
2460 save_native_result(masm, ret_type, stack_slots);
2461 }
2462
2463
2464 // get address of the stack lock
2465 __ lea(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2466 // get old displaced header
2467 __ movptr(old_hdr, Address(rax, 0));
2468
2469 // Atomic swap old header if oop still contains the stack lock
2470 if (os::is_MP()) {
2471 __ lock();
2472 }
2473 __ cmpxchgptr(old_hdr, Address(obj_reg, 0));
2474 __ jcc(Assembler::notEqual, slow_path_unlock);
2475
2476 // slow path re-enters here
2477 __ bind(unlock_done);
2478 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
2479 restore_native_result(masm, ret_type, stack_slots);
2480 }
2481
2482 __ bind(done);
2483
2484 }
2485 {
2486 SkipIfEqual skip(masm, &DTraceMethodProbes, false);
2487 save_native_result(masm, ret_type, stack_slots);
2488 __ mov_metadata(c_rarg1, method());
2489 __ call_VM_leaf(
2490 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
2491 r15_thread, c_rarg1);
2492 restore_native_result(masm, ret_type, stack_slots);
2493 }
2494
2495 __ reset_last_Java_frame(false, true);
2496
2497 // Unpack oop result
2498 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
2499 Label L;
2500 __ testptr(rax, rax);
2501 __ jcc(Assembler::zero, L);
2502 __ movptr(rax, Address(rax, 0));
2503 __ bind(L);
2504 __ verify_oop(rax);
2505 }
2506
2507 if (!is_critical_native) {
2508 // reset handle block
2509 __ movptr(rcx, Address(r15_thread, JavaThread::active_handles_offset()));
2510 __ movptr(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD);
2511 }
2512
2513 // pop our frame
2514
2515 __ leave();
2516
2517 if (!is_critical_native) {
2518 // Any exception pending?
2519 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2520 __ jcc(Assembler::notEqual, exception_pending);
2521 }
2522
2523 // Return
2524
2525 __ ret(0);
2526
2527 // Unexpected paths are out of line and go here
2528
2529 if (!is_critical_native) {
2530 // forward the exception
2531 __ bind(exception_pending);
2532
2533 // and forward the exception
2534 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2535 }
2536
2537 // Slow path locking & unlocking
2538 if (method->is_synchronized()) {
2539
2540 // BEGIN Slow path lock
2541 __ bind(slow_path_lock);
2542
2543 // has last_Java_frame setup. No exceptions so do vanilla call not call_VM
2544 // args are (oop obj, BasicLock* lock, JavaThread* thread)
2545
2546 // protect the args we've loaded
2547 save_args(masm, total_c_args, c_arg, out_regs);
2548
2549 __ mov(c_rarg0, obj_reg);
2550 __ mov(c_rarg1, lock_reg);
2551 __ mov(c_rarg2, r15_thread);
2552
2553 // Not a leaf but we have last_Java_frame setup as we want
2554 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), 3);
2555 restore_args(masm, total_c_args, c_arg, out_regs);
2556
2557 #ifdef ASSERT
2558 { Label L;
2559 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2560 __ jcc(Assembler::equal, L);
2561 __ stop("no pending exception allowed on exit from monitorenter");
2562 __ bind(L);
2563 }
2564 #endif
2565 __ jmp(lock_done);
2566
2567 // END Slow path lock
2568
2569 // BEGIN Slow path unlock
2570 __ bind(slow_path_unlock);
2571
2572 // If we haven't already saved the native result we must save it now as xmm registers
2573 // are still exposed.
2574
2575 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
2576 save_native_result(masm, ret_type, stack_slots);
2577 }
2578
2579 __ lea(c_rarg1, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2580
2581 __ mov(c_rarg0, obj_reg);
2582 __ mov(r12, rsp); // remember sp
2583 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2584 __ andptr(rsp, -16); // align stack as required by ABI
2585
2586 // Save pending exception around call to VM (which contains an EXCEPTION_MARK)
2587 // NOTE that obj_reg == rbx currently
2588 __ movptr(rbx, Address(r15_thread, in_bytes(Thread::pending_exception_offset())));
2589 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2590
2591 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C)));
2592 __ mov(rsp, r12); // restore sp
2593 __ reinit_heapbase();
2594 #ifdef ASSERT
2595 {
2596 Label L;
2597 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
2598 __ jcc(Assembler::equal, L);
2599 __ stop("no pending exception allowed on exit complete_monitor_unlocking_C");
2600 __ bind(L);
2601 }
2602 #endif /* ASSERT */
2603
2604 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), rbx);
2605
2606 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
2607 restore_native_result(masm, ret_type, stack_slots);
2608 }
2609 __ jmp(unlock_done);
2610
2611 // END Slow path unlock
2612
2613 } // synchronized
2614
2615 // SLOW PATH Reguard the stack if needed
2616
2617 __ bind(reguard);
2618 save_native_result(masm, ret_type, stack_slots);
2619 __ mov(r12, rsp); // remember sp
2620 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2621 __ andptr(rsp, -16); // align stack as required by ABI
2622 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
2623 __ mov(rsp, r12); // restore sp
2624 __ reinit_heapbase();
2625 restore_native_result(masm, ret_type, stack_slots);
2626 // and continue
2627 __ jmp(reguard_done);
2628
2629
2630
2631 __ flush();
2632
2633 nmethod *nm = nmethod::new_native_nmethod(method,
2634 compile_id,
2635 masm->code(),
2636 vep_offset,
2637 frame_complete,
2638 stack_slots / VMRegImpl::slots_per_word,
2639 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
2640 in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size),
2641 oop_maps);
2642
2643 if (is_critical_native) {
2644 nm->set_lazy_critical_native(true);
2645 }
2646
2647 return nm;
2648
2649 }
2650
2651 #ifdef HAVE_DTRACE_H
2652 // ---------------------------------------------------------------------------
2653 // Generate a dtrace nmethod for a given signature. The method takes arguments
2654 // in the Java compiled code convention, marshals them to the native
2655 // abi and then leaves nops at the position you would expect to call a native
2656 // function. When the probe is enabled the nops are replaced with a trap
2657 // instruction that dtrace inserts and the trace will cause a notification
2658 // to dtrace.
2659 //
2660 // The probes are only able to take primitive types and java/lang/String as
2661 // arguments. No other java types are allowed. Strings are converted to utf8
2662 // strings so that from dtrace point of view java strings are converted to C
2663 // strings. There is an arbitrary fixed limit on the total space that a method
2664 // can use for converting the strings. (256 chars per string in the signature).
2665 // So any java string larger then this is truncated.
2666
2667 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
2668 static bool offsets_initialized = false;
2669
2670
2671 nmethod *SharedRuntime::generate_dtrace_nmethod(MacroAssembler *masm,
2672 methodHandle method) {
2673
2674
2675 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
2676 // be single threaded in this method.
2677 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
2678
2679 if (!offsets_initialized) {
2680 fp_offset[c_rarg0->as_VMReg()->value()] = -1 * wordSize;
2681 fp_offset[c_rarg1->as_VMReg()->value()] = -2 * wordSize;
2682 fp_offset[c_rarg2->as_VMReg()->value()] = -3 * wordSize;
2683 fp_offset[c_rarg3->as_VMReg()->value()] = -4 * wordSize;
2684 fp_offset[c_rarg4->as_VMReg()->value()] = -5 * wordSize;
2685 fp_offset[c_rarg5->as_VMReg()->value()] = -6 * wordSize;
2686
2687 fp_offset[c_farg0->as_VMReg()->value()] = -7 * wordSize;
2688 fp_offset[c_farg1->as_VMReg()->value()] = -8 * wordSize;
2689 fp_offset[c_farg2->as_VMReg()->value()] = -9 * wordSize;
2690 fp_offset[c_farg3->as_VMReg()->value()] = -10 * wordSize;
2691 fp_offset[c_farg4->as_VMReg()->value()] = -11 * wordSize;
2692 fp_offset[c_farg5->as_VMReg()->value()] = -12 * wordSize;
2693 fp_offset[c_farg6->as_VMReg()->value()] = -13 * wordSize;
2694 fp_offset[c_farg7->as_VMReg()->value()] = -14 * wordSize;
2695
2696 offsets_initialized = true;
2697 }
2698 // Fill in the signature array, for the calling-convention call.
2699 int total_args_passed = method->size_of_parameters();
2700
2701 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
2702 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
2703
2704 // The signature we are going to use for the trap that dtrace will see
2705 // java/lang/String is converted. We drop "this" and any other object
2706 // is converted to NULL. (A one-slot java/lang/Long object reference
2707 // is converted to a two-slot long, which is why we double the allocation).
2708 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
2709 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
2710
2711 int i=0;
2712 int total_strings = 0;
2713 int first_arg_to_pass = 0;
2714 int total_c_args = 0;
2715
2716 // Skip the receiver as dtrace doesn't want to see it
2717 if( !method->is_static() ) {
2718 in_sig_bt[i++] = T_OBJECT;
2719 first_arg_to_pass = 1;
2720 }
2721
2722 // We need to convert the java args to where a native (non-jni) function
2723 // would expect them. To figure out where they go we convert the java
2724 // signature to a C signature.
2725
2726 SignatureStream ss(method->signature());
2727 for ( ; !ss.at_return_type(); ss.next()) {
2728 BasicType bt = ss.type();
2729 in_sig_bt[i++] = bt; // Collect remaining bits of signature
2730 out_sig_bt[total_c_args++] = bt;
2731 if( bt == T_OBJECT) {
2732 Symbol* s = ss.as_symbol_or_null(); // symbol is created
2733 if (s == vmSymbols::java_lang_String()) {
2734 total_strings++;
2735 out_sig_bt[total_c_args-1] = T_ADDRESS;
2736 } else if (s == vmSymbols::java_lang_Boolean() ||
2737 s == vmSymbols::java_lang_Character() ||
2738 s == vmSymbols::java_lang_Byte() ||
2739 s == vmSymbols::java_lang_Short() ||
2740 s == vmSymbols::java_lang_Integer() ||
2741 s == vmSymbols::java_lang_Float()) {
2742 out_sig_bt[total_c_args-1] = T_INT;
2743 } else if (s == vmSymbols::java_lang_Long() ||
2744 s == vmSymbols::java_lang_Double()) {
2745 out_sig_bt[total_c_args-1] = T_LONG;
2746 out_sig_bt[total_c_args++] = T_VOID;
2747 }
2748 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
2749 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
2750 // We convert double to long
2751 out_sig_bt[total_c_args-1] = T_LONG;
2752 out_sig_bt[total_c_args++] = T_VOID;
2753 } else if ( bt == T_FLOAT) {
2754 // We convert float to int
2755 out_sig_bt[total_c_args-1] = T_INT;
2756 }
2757 }
2758
2759 assert(i==total_args_passed, "validly parsed signature");
2760
2761 // Now get the compiled-Java layout as input arguments
2762 int comp_args_on_stack;
2763 comp_args_on_stack = SharedRuntime::java_calling_convention(
2764 in_sig_bt, in_regs, total_args_passed, false);
2765
2766 // Now figure out where the args must be stored and how much stack space
2767 // they require (neglecting out_preserve_stack_slots but space for storing
2768 // the 1st six register arguments). It's weird see int_stk_helper.
2769
2770 int out_arg_slots;
2771 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
2772
2773 // Calculate the total number of stack slots we will need.
2774
2775 // First count the abi requirement plus all of the outgoing args
2776 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2777
2778 // Now space for the string(s) we must convert
2779 int* string_locs = NEW_RESOURCE_ARRAY(int, total_strings + 1);
2780 for (i = 0; i < total_strings ; i++) {
2781 string_locs[i] = stack_slots;
2782 stack_slots += max_dtrace_string_size / VMRegImpl::stack_slot_size;
2783 }
2784
2785 // Plus the temps we might need to juggle register args
2786 // regs take two slots each
2787 stack_slots += (Argument::n_int_register_parameters_c +
2788 Argument::n_float_register_parameters_c) * 2;
2789
2790
2791 // + 4 for return address (which we own) and saved rbp,
2792
2793 stack_slots += 4;
2794
2795 // Ok The space we have allocated will look like:
2796 //
2797 //
2798 // FP-> | |
2799 // |---------------------|
2800 // | string[n] |
2801 // |---------------------| <- string_locs[n]
2802 // | string[n-1] |
2803 // |---------------------| <- string_locs[n-1]
2804 // | ... |
2805 // | ... |
2806 // |---------------------| <- string_locs[1]
2807 // | string[0] |
2808 // |---------------------| <- string_locs[0]
2809 // | outbound memory |
2810 // | based arguments |
2811 // | |
2812 // |---------------------|
2813 // | |
2814 // SP-> | out_preserved_slots |
2815 //
2816 //
2817
2818 // Now compute actual number of stack words we need rounding to make
2819 // stack properly aligned.
2820 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
2821
2822 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2823
2824 intptr_t start = (intptr_t)__ pc();
2825
2826 // First thing make an ic check to see if we should even be here
2827
2828 // We are free to use all registers as temps without saving them and
2829 // restoring them except rbp. rbp, is the only callee save register
2830 // as far as the interpreter and the compiler(s) are concerned.
2831
2832 const Register ic_reg = rax;
2833 const Register receiver = rcx;
2834 Label hit;
2835 Label exception_pending;
2836
2837
2838 __ verify_oop(receiver);
2839 __ cmpl(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes()));
2840 __ jcc(Assembler::equal, hit);
2841
2842 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
2843
2844 // verified entry must be aligned for code patching.
2845 // and the first 5 bytes must be in the same cache line
2846 // if we align at 8 then we will be sure 5 bytes are in the same line
2847 __ align(8);
2848
2849 __ bind(hit);
2850
2851 int vep_offset = ((intptr_t)__ pc()) - start;
2852
2853
2854 // The instruction at the verified entry point must be 5 bytes or longer
2855 // because it can be patched on the fly by make_non_entrant. The stack bang
2856 // instruction fits that requirement.
2857
2858 // Generate stack overflow check
2859
2860 if (UseStackBanging) {
2861 if (stack_size <= StackShadowPages*os::vm_page_size()) {
2862 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
2863 } else {
2864 __ movl(rax, stack_size);
2865 __ bang_stack_size(rax, rbx);
2866 }
2867 } else {
2868 // need a 5 byte instruction to allow MT safe patching to non-entrant
2869 __ fat_nop();
2870 }
2871
2872 assert(((uintptr_t)__ pc() - start - vep_offset) >= 5,
2873 "valid size for make_non_entrant");
2874
2875 // Generate a new frame for the wrapper.
2876 __ enter();
2877
2878 // -4 because return address is already present and so is saved rbp,
2879 if (stack_size - 2*wordSize != 0) {
2880 __ subq(rsp, stack_size - 2*wordSize);
2881 }
2882
2883 // Frame is now completed as far a size and linkage.
2884
2885 int frame_complete = ((intptr_t)__ pc()) - start;
2886
2887 int c_arg, j_arg;
2888
2889 // State of input register args
2890
2891 bool live[ConcreteRegisterImpl::number_of_registers];
2892
2893 live[j_rarg0->as_VMReg()->value()] = false;
2894 live[j_rarg1->as_VMReg()->value()] = false;
2895 live[j_rarg2->as_VMReg()->value()] = false;
2896 live[j_rarg3->as_VMReg()->value()] = false;
2897 live[j_rarg4->as_VMReg()->value()] = false;
2898 live[j_rarg5->as_VMReg()->value()] = false;
2899
2900 live[j_farg0->as_VMReg()->value()] = false;
2901 live[j_farg1->as_VMReg()->value()] = false;
2902 live[j_farg2->as_VMReg()->value()] = false;
2903 live[j_farg3->as_VMReg()->value()] = false;
2904 live[j_farg4->as_VMReg()->value()] = false;
2905 live[j_farg5->as_VMReg()->value()] = false;
2906 live[j_farg6->as_VMReg()->value()] = false;
2907 live[j_farg7->as_VMReg()->value()] = false;
2908
2909
2910 bool rax_is_zero = false;
2911
2912 // All args (except strings) destined for the stack are moved first
2913 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2914 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2915 VMRegPair src = in_regs[j_arg];
2916 VMRegPair dst = out_regs[c_arg];
2917
2918 // Get the real reg value or a dummy (rsp)
2919
2920 int src_reg = src.first()->is_reg() ?
2921 src.first()->value() :
2922 rsp->as_VMReg()->value();
2923
2924 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
2925 (in_sig_bt[j_arg] == T_OBJECT &&
2926 out_sig_bt[c_arg] != T_INT &&
2927 out_sig_bt[c_arg] != T_ADDRESS &&
2928 out_sig_bt[c_arg] != T_LONG);
2929
2930 live[src_reg] = !useless;
2931
2932 if (dst.first()->is_stack()) {
2933
2934 // Even though a string arg in a register is still live after this loop
2935 // after the string conversion loop (next) it will be dead so we take
2936 // advantage of that now for simpler code to manage live.
2937
2938 live[src_reg] = false;
2939 switch (in_sig_bt[j_arg]) {
2940
2941 case T_ARRAY:
2942 case T_OBJECT:
2943 {
2944 Address stack_dst(rsp, reg2offset_out(dst.first()));
2945
2946 if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
2947 // need to unbox a one-word value
2948 Register in_reg = rax;
2949 if ( src.first()->is_reg() ) {
2950 in_reg = src.first()->as_Register();
2951 } else {
2952 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
2953 rax_is_zero = false;
2954 }
2955 Label skipUnbox;
2956 __ movptr(Address(rsp, reg2offset_out(dst.first())),
2957 (int32_t)NULL_WORD);
2958 __ testq(in_reg, in_reg);
2959 __ jcc(Assembler::zero, skipUnbox);
2960
2961 BasicType bt = out_sig_bt[c_arg];
2962 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
2963 Address src1(in_reg, box_offset);
2964 if ( bt == T_LONG ) {
2965 __ movq(in_reg, src1);
2966 __ movq(stack_dst, in_reg);
2967 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2968 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2969 } else {
2970 __ movl(in_reg, src1);
2971 __ movl(stack_dst, in_reg);
2972 }
2973
2974 __ bind(skipUnbox);
2975 } else if (out_sig_bt[c_arg] != T_ADDRESS) {
2976 // Convert the arg to NULL
2977 if (!rax_is_zero) {
2978 __ xorq(rax, rax);
2979 rax_is_zero = true;
2980 }
2981 __ movq(stack_dst, rax);
2982 }
2983 }
2984 break;
2985
2986 case T_VOID:
2987 break;
2988
2989 case T_FLOAT:
2990 // This does the right thing since we know it is destined for the
2991 // stack
2992 float_move(masm, src, dst);
2993 break;
2994
2995 case T_DOUBLE:
2996 // This does the right thing since we know it is destined for the
2997 // stack
2998 double_move(masm, src, dst);
2999 break;
3000
3001 case T_LONG :
3002 long_move(masm, src, dst);
3003 break;
3004
3005 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
3006
3007 default:
3008 move32_64(masm, src, dst);
3009 }
3010 }
3011
3012 }
3013
3014 // If we have any strings we must store any register based arg to the stack
3015 // This includes any still live xmm registers too.
3016
3017 int sid = 0;
3018
3019 if (total_strings > 0 ) {
3020 for (j_arg = first_arg_to_pass, c_arg = 0 ;
3021 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
3022 VMRegPair src = in_regs[j_arg];
3023 VMRegPair dst = out_regs[c_arg];
3024
3025 if (src.first()->is_reg()) {
3026 Address src_tmp(rbp, fp_offset[src.first()->value()]);
3027
3028 // string oops were left untouched by the previous loop even if the
3029 // eventual (converted) arg is destined for the stack so park them
3030 // away now (except for first)
3031
3032 if (out_sig_bt[c_arg] == T_ADDRESS) {
3033 Address utf8_addr = Address(
3034 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
3035 if (sid != 1) {
3036 // The first string arg won't be killed until after the utf8
3037 // conversion
3038 __ movq(utf8_addr, src.first()->as_Register());
3039 }
3040 } else if (dst.first()->is_reg()) {
3041 if (in_sig_bt[j_arg] == T_FLOAT || in_sig_bt[j_arg] == T_DOUBLE) {
3042
3043 // Convert the xmm register to an int and store it in the reserved
3044 // location for the eventual c register arg
3045 XMMRegister f = src.first()->as_XMMRegister();
3046 if (in_sig_bt[j_arg] == T_FLOAT) {
3047 __ movflt(src_tmp, f);
3048 } else {
3049 __ movdbl(src_tmp, f);
3050 }
3051 } else {
3052 // If the arg is an oop type we don't support don't bother to store
3053 // it remember string was handled above.
3054 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
3055 (in_sig_bt[j_arg] == T_OBJECT &&
3056 out_sig_bt[c_arg] != T_INT &&
3057 out_sig_bt[c_arg] != T_LONG);
3058
3059 if (!useless) {
3060 __ movq(src_tmp, src.first()->as_Register());
3061 }
3062 }
3063 }
3064 }
3065 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
3066 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
3067 ++c_arg; // skip over T_VOID to keep the loop indices in sync
3068 }
3069 }
3070
3071 // Now that the volatile registers are safe, convert all the strings
3072 sid = 0;
3073
3074 for (j_arg = first_arg_to_pass, c_arg = 0 ;
3075 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
3076 if (out_sig_bt[c_arg] == T_ADDRESS) {
3077 // It's a string
3078 Address utf8_addr = Address(
3079 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
3080 // The first string we find might still be in the original java arg
3081 // register
3082
3083 VMReg src = in_regs[j_arg].first();
3084
3085 // We will need to eventually save the final argument to the trap
3086 // in the von-volatile location dedicated to src. This is the offset
3087 // from fp we will use.
3088 int src_off = src->is_reg() ?
3089 fp_offset[src->value()] : reg2offset_in(src);
3090
3091 // This is where the argument will eventually reside
3092 VMRegPair dst = out_regs[c_arg];
3093
3094 if (src->is_reg()) {
3095 if (sid == 1) {
3096 __ movq(c_rarg0, src->as_Register());
3097 } else {
3098 __ movq(c_rarg0, utf8_addr);
3099 }
3100 } else {
3101 // arg is still in the original location
3102 __ movq(c_rarg0, Address(rbp, reg2offset_in(src)));
3103 }
3104 Label done, convert;
3105
3106 // see if the oop is NULL
3107 __ testq(c_rarg0, c_rarg0);
3108 __ jcc(Assembler::notEqual, convert);
3109
3110 if (dst.first()->is_reg()) {
3111 // Save the ptr to utf string in the origina src loc or the tmp
3112 // dedicated to it
3113 __ movq(Address(rbp, src_off), c_rarg0);
3114 } else {
3115 __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg0);
3116 }
3117 __ jmp(done);
3118
3119 __ bind(convert);
3120
3121 __ lea(c_rarg1, utf8_addr);
3122 if (dst.first()->is_reg()) {
3123 __ movq(Address(rbp, src_off), c_rarg1);
3124 } else {
3125 __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg1);
3126 }
3127 // And do the conversion
3128 __ call(RuntimeAddress(
3129 CAST_FROM_FN_PTR(address, SharedRuntime::get_utf)));
3130
3131 __ bind(done);
3132 }
3133 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
3134 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
3135 ++c_arg; // skip over T_VOID to keep the loop indices in sync
3136 }
3137 }
3138 // The get_utf call killed all the c_arg registers
3139 live[c_rarg0->as_VMReg()->value()] = false;
3140 live[c_rarg1->as_VMReg()->value()] = false;
3141 live[c_rarg2->as_VMReg()->value()] = false;
3142 live[c_rarg3->as_VMReg()->value()] = false;
3143 live[c_rarg4->as_VMReg()->value()] = false;
3144 live[c_rarg5->as_VMReg()->value()] = false;
3145
3146 live[c_farg0->as_VMReg()->value()] = false;
3147 live[c_farg1->as_VMReg()->value()] = false;
3148 live[c_farg2->as_VMReg()->value()] = false;
3149 live[c_farg3->as_VMReg()->value()] = false;
3150 live[c_farg4->as_VMReg()->value()] = false;
3151 live[c_farg5->as_VMReg()->value()] = false;
3152 live[c_farg6->as_VMReg()->value()] = false;
3153 live[c_farg7->as_VMReg()->value()] = false;
3154 }
3155
3156 // Now we can finally move the register args to their desired locations
3157
3158 rax_is_zero = false;
3159
3160 for (j_arg = first_arg_to_pass, c_arg = 0 ;
3161 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
3162
3163 VMRegPair src = in_regs[j_arg];
3164 VMRegPair dst = out_regs[c_arg];
3165
3166 // Only need to look for args destined for the interger registers (since we
3167 // convert float/double args to look like int/long outbound)
3168 if (dst.first()->is_reg()) {
3169 Register r = dst.first()->as_Register();
3170
3171 // Check if the java arg is unsupported and thereofre useless
3172 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
3173 (in_sig_bt[j_arg] == T_OBJECT &&
3174 out_sig_bt[c_arg] != T_INT &&
3175 out_sig_bt[c_arg] != T_ADDRESS &&
3176 out_sig_bt[c_arg] != T_LONG);
3177
3178
3179 // If we're going to kill an existing arg save it first
3180 if (live[dst.first()->value()]) {
3181 // you can't kill yourself
3182 if (src.first() != dst.first()) {
3183 __ movq(Address(rbp, fp_offset[dst.first()->value()]), r);
3184 }
3185 }
3186 if (src.first()->is_reg()) {
3187 if (live[src.first()->value()] ) {
3188 if (in_sig_bt[j_arg] == T_FLOAT) {
3189 __ movdl(r, src.first()->as_XMMRegister());
3190 } else if (in_sig_bt[j_arg] == T_DOUBLE) {
3191 __ movdq(r, src.first()->as_XMMRegister());
3192 } else if (r != src.first()->as_Register()) {
3193 if (!useless) {
3194 __ movq(r, src.first()->as_Register());
3195 }
3196 }
3197 } else {
3198 // If the arg is an oop type we don't support don't bother to store
3199 // it
3200 if (!useless) {
3201 if (in_sig_bt[j_arg] == T_DOUBLE ||
3202 in_sig_bt[j_arg] == T_LONG ||
3203 in_sig_bt[j_arg] == T_OBJECT ) {
3204 __ movq(r, Address(rbp, fp_offset[src.first()->value()]));
3205 } else {
3206 __ movl(r, Address(rbp, fp_offset[src.first()->value()]));
3207 }
3208 }
3209 }
3210 live[src.first()->value()] = false;
3211 } else if (!useless) {
3212 // full sized move even for int should be ok
3213 __ movq(r, Address(rbp, reg2offset_in(src.first())));
3214 }
3215
3216 // At this point r has the original java arg in the final location
3217 // (assuming it wasn't useless). If the java arg was an oop
3218 // we have a bit more to do
3219
3220 if (in_sig_bt[j_arg] == T_ARRAY || in_sig_bt[j_arg] == T_OBJECT ) {
3221 if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
3222 // need to unbox a one-word value
3223 Label skip;
3224 __ testq(r, r);
3225 __ jcc(Assembler::equal, skip);
3226 BasicType bt = out_sig_bt[c_arg];
3227 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
3228 Address src1(r, box_offset);
3229 if ( bt == T_LONG ) {
3230 __ movq(r, src1);
3231 } else {
3232 __ movl(r, src1);
3233 }
3234 __ bind(skip);
3235
3236 } else if (out_sig_bt[c_arg] != T_ADDRESS) {
3237 // Convert the arg to NULL
3238 __ xorq(r, r);
3239 }
3240 }
3241
3242 // dst can longer be holding an input value
3243 live[dst.first()->value()] = false;
3244 }
3245 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
3246 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
3247 ++c_arg; // skip over T_VOID to keep the loop indices in sync
3248 }
3249 }
3250
3251
3252 // Ok now we are done. Need to place the nop that dtrace wants in order to
3253 // patch in the trap
3254 int patch_offset = ((intptr_t)__ pc()) - start;
3255
3256 __ nop();
3257
3258
3259 // Return
3260
3261 __ leave();
3262 __ ret(0);
3263
3264 __ flush();
3265
3266 nmethod *nm = nmethod::new_dtrace_nmethod(
3267 method, masm->code(), vep_offset, patch_offset, frame_complete,
3268 stack_slots / VMRegImpl::slots_per_word);
3269 return nm;
3270
3271 }
3272
3273 #endif // HAVE_DTRACE_H
3274
3275 // this function returns the adjust size (in number of words) to a c2i adapter
3276 // activation for use during deoptimization
3277 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) {
3278 return (callee_locals - callee_parameters) * Interpreter::stackElementWords;
3279 }
3280
3281
3282 uint SharedRuntime::out_preserve_stack_slots() {
3283 return 0;
3284 }
3285
3286 //------------------------------generate_deopt_blob----------------------------
3287 void SharedRuntime::generate_deopt_blob() {
3288 // Allocate space for the code
3289 ResourceMark rm;
3290 // Setup code generation tools
3291 CodeBuffer buffer("deopt_blob", 2048, 1024);
3292 MacroAssembler* masm = new MacroAssembler(&buffer);
3293 int frame_size_in_words;
3294 OopMap* map = NULL;
3295 OopMapSet *oop_maps = new OopMapSet();
3296
3297 // -------------
3298 // This code enters when returning to a de-optimized nmethod. A return
3299 // address has been pushed on the the stack, and return values are in
3300 // registers.
3301 // If we are doing a normal deopt then we were called from the patched
3302 // nmethod from the point we returned to the nmethod. So the return
3303 // address on the stack is wrong by NativeCall::instruction_size
3304 // We will adjust the value so it looks like we have the original return
3305 // address on the stack (like when we eagerly deoptimized).
3306 // In the case of an exception pending when deoptimizing, we enter
3307 // with a return address on the stack that points after the call we patched
3308 // into the exception handler. We have the following register state from,
3309 // e.g., the forward exception stub (see stubGenerator_x86_64.cpp).
3310 // rax: exception oop
3311 // rbx: exception handler
3312 // rdx: throwing pc
3313 // So in this case we simply jam rdx into the useless return address and
3314 // the stack looks just like we want.
3315 //
3316 // At this point we need to de-opt. We save the argument return
3317 // registers. We call the first C routine, fetch_unroll_info(). This
3318 // routine captures the return values and returns a structure which
3319 // describes the current frame size and the sizes of all replacement frames.
3320 // The current frame is compiled code and may contain many inlined
3321 // functions, each with their own JVM state. We pop the current frame, then
3322 // push all the new frames. Then we call the C routine unpack_frames() to
3323 // populate these frames. Finally unpack_frames() returns us the new target
3324 // address. Notice that callee-save registers are BLOWN here; they have
3325 // already been captured in the vframeArray at the time the return PC was
3326 // patched.
3327 address start = __ pc();
3328 Label cont;
3329
3330 // Prolog for non exception case!
3331
3332 // Save everything in sight.
3333 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3334
3335 // Normal deoptimization. Save exec mode for unpack_frames.
3336 __ movl(r14, Deoptimization::Unpack_deopt); // callee-saved
3337 __ jmp(cont);
3338
3339 int reexecute_offset = __ pc() - start;
3340
3341 // Reexecute case
3342 // return address is the pc describes what bci to do re-execute at
3343
3344 // No need to update map as each call to save_live_registers will produce identical oopmap
3345 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3346
3347 __ movl(r14, Deoptimization::Unpack_reexecute); // callee-saved
3348 __ jmp(cont);
3349
3350 int exception_offset = __ pc() - start;
3351
3352 // Prolog for exception case
3353
3354 // all registers are dead at this entry point, except for rax, and
3355 // rdx which contain the exception oop and exception pc
3356 // respectively. Set them in TLS and fall thru to the
3357 // unpack_with_exception_in_tls entry point.
3358
3359 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
3360 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), rax);
3361
3362 int exception_in_tls_offset = __ pc() - start;
3363
3364 // new implementation because exception oop is now passed in JavaThread
3365
3366 // Prolog for exception case
3367 // All registers must be preserved because they might be used by LinearScan
3368 // Exceptiop oop and throwing PC are passed in JavaThread
3369 // tos: stack at point of call to method that threw the exception (i.e. only
3370 // args are on the stack, no return address)
3371
3372 // make room on stack for the return address
3373 // It will be patched later with the throwing pc. The correct value is not
3374 // available now because loading it from memory would destroy registers.
3375 __ push(0);
3376
3377 // Save everything in sight.
3378 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3379
3380 // Now it is safe to overwrite any register
3381
3382 // Deopt during an exception. Save exec mode for unpack_frames.
3383 __ movl(r14, Deoptimization::Unpack_exception); // callee-saved
3384
3385 // load throwing pc from JavaThread and patch it as the return address
3386 // of the current frame. Then clear the field in JavaThread
3387
3388 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
3389 __ movptr(Address(rbp, wordSize), rdx);
3390 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
3391
3392 #ifdef ASSERT
3393 // verify that there is really an exception oop in JavaThread
3394 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
3395 __ verify_oop(rax);
3396
3397 // verify that there is no pending exception
3398 Label no_pending_exception;
3399 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
3400 __ testptr(rax, rax);
3401 __ jcc(Assembler::zero, no_pending_exception);
3402 __ stop("must not have pending exception here");
3403 __ bind(no_pending_exception);
3404 #endif
3405
3406 __ bind(cont);
3407
3408 // Call C code. Need thread and this frame, but NOT official VM entry
3409 // crud. We cannot block on this call, no GC can happen.
3410 //
3411 // UnrollBlock* fetch_unroll_info(JavaThread* thread)
3412
3413 // fetch_unroll_info needs to call last_java_frame().
3414
3415 __ set_last_Java_frame(noreg, noreg, NULL);
3416 #ifdef ASSERT
3417 { Label L;
3418 __ cmpptr(Address(r15_thread,
3419 JavaThread::last_Java_fp_offset()),
3420 (int32_t)0);
3421 __ jcc(Assembler::equal, L);
3422 __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared");
3423 __ bind(L);
3424 }
3425 #endif // ASSERT
3426 __ mov(c_rarg0, r15_thread);
3427 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info)));
3428
3429 // Need to have an oopmap that tells fetch_unroll_info where to
3430 // find any register it might need.
3431 oop_maps->add_gc_map(__ pc() - start, map);
3432
3433 __ reset_last_Java_frame(false, false);
3434
3435 // Load UnrollBlock* into rdi
3436 __ mov(rdi, rax);
3437
3438 Label noException;
3439 __ cmpl(r14, Deoptimization::Unpack_exception); // Was exception pending?
3440 __ jcc(Assembler::notEqual, noException);
3441 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
3442 // QQQ this is useless it was NULL above
3443 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
3444 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
3445 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
3446
3447 __ verify_oop(rax);
3448
3449 // Overwrite the result registers with the exception results.
3450 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3451 // I think this is useless
3452 __ movptr(Address(rsp, RegisterSaver::rdx_offset_in_bytes()), rdx);
3453
3454 __ bind(noException);
3455
3456 // Only register save data is on the stack.
3457 // Now restore the result registers. Everything else is either dead
3458 // or captured in the vframeArray.
3459 RegisterSaver::restore_result_registers(masm);
3460
3461 // All of the register save area has been popped of the stack. Only the
3462 // return address remains.
3463
3464 // Pop all the frames we must move/replace.
3465 //
3466 // Frame picture (youngest to oldest)
3467 // 1: self-frame (no frame link)
3468 // 2: deopting frame (no frame link)
3469 // 3: caller of deopting frame (could be compiled/interpreted).
3470 //
3471 // Note: by leaving the return address of self-frame on the stack
3472 // and using the size of frame 2 to adjust the stack
3473 // when we are done the return to frame 3 will still be on the stack.
3474
3475 // Pop deoptimized frame
3476 __ movl(rcx, Address(rdi, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
3477 __ addptr(rsp, rcx);
3478
3479 // rsp should be pointing at the return address to the caller (3)
3480
3481 // Pick up the initial fp we should save
3482 // restore rbp before stack bang because if stack overflow is thrown it needs to be pushed (and preserved)
3483 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
3484
3485 // Stack bang to make sure there's enough room for these interpreter frames.
3486 if (UseStackBanging) {
3487 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
3488 __ bang_stack_size(rbx, rcx);
3489 }
3490
3491 // Load address of array of frame pcs into rcx
3492 __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
3493
3494 // Trash the old pc
3495 __ addptr(rsp, wordSize);
3496
3497 // Load address of array of frame sizes into rsi
3498 __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
3499
3500 // Load counter into rdx
3501 __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
3502
3503 // Now adjust the caller's stack to make up for the extra locals
3504 // but record the original sp so that we can save it in the skeletal interpreter
3505 // frame and the stack walking of interpreter_sender will get the unextended sp
3506 // value and not the "real" sp value.
3507
3508 const Register sender_sp = r8;
3509
3510 __ mov(sender_sp, rsp);
3511 __ movl(rbx, Address(rdi,
3512 Deoptimization::UnrollBlock::
3513 caller_adjustment_offset_in_bytes()));
3514 __ subptr(rsp, rbx);
3515
3516 // Push interpreter frames in a loop
3517 Label loop;
3518 __ bind(loop);
3519 __ movptr(rbx, Address(rsi, 0)); // Load frame size
3520 #ifdef CC_INTERP
3521 __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and
3522 #ifdef ASSERT
3523 __ push(0xDEADDEAD); // Make a recognizable pattern
3524 __ push(0xDEADDEAD);
3525 #else /* ASSERT */
3526 __ subptr(rsp, 2*wordSize); // skip the "static long no_param"
3527 #endif /* ASSERT */
3528 #else
3529 __ subptr(rbx, 2*wordSize); // We'll push pc and ebp by hand
3530 #endif // CC_INTERP
3531 __ pushptr(Address(rcx, 0)); // Save return address
3532 __ enter(); // Save old & set new ebp
3533 __ subptr(rsp, rbx); // Prolog
3534 #ifdef CC_INTERP
3535 __ movptr(Address(rbp,
3536 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
3537 sender_sp); // Make it walkable
3538 #else /* CC_INTERP */
3539 // This value is corrected by layout_activation_impl
3540 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
3541 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), sender_sp); // Make it walkable
3542 #endif /* CC_INTERP */
3543 __ mov(sender_sp, rsp); // Pass sender_sp to next frame
3544 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
3545 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
3546 __ decrementl(rdx); // Decrement counter
3547 __ jcc(Assembler::notZero, loop);
3548 __ pushptr(Address(rcx, 0)); // Save final return address
3549
3550 // Re-push self-frame
3551 __ enter(); // Save old & set new ebp
3552
3553 // Allocate a full sized register save area.
3554 // Return address and rbp are in place, so we allocate two less words.
3555 __ subptr(rsp, (frame_size_in_words - 2) * wordSize);
3556
3557 // Restore frame locals after moving the frame
3558 __ movdbl(Address(rsp, RegisterSaver::xmm0_offset_in_bytes()), xmm0);
3559 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3560
3561 // Call C code. Need thread but NOT official VM entry
3562 // crud. We cannot block on this call, no GC can happen. Call should
3563 // restore return values to their stack-slots with the new SP.
3564 //
3565 // void Deoptimization::unpack_frames(JavaThread* thread, int exec_mode)
3566
3567 // Use rbp because the frames look interpreted now
3568 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP.
3569 // Don't need the precise return PC here, just precise enough to point into this code blob.
3570 address the_pc = __ pc();
3571 __ set_last_Java_frame(noreg, rbp, the_pc);
3572
3573 __ andptr(rsp, -(StackAlignmentInBytes)); // Fix stack alignment as required by ABI
3574 __ mov(c_rarg0, r15_thread);
3575 __ movl(c_rarg1, r14); // second arg: exec_mode
3576 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
3577 // Revert SP alignment after call since we're going to do some SP relative addressing below
3578 __ movptr(rsp, Address(r15_thread, JavaThread::last_Java_sp_offset()));
3579
3580 // Set an oopmap for the call site
3581 // Use the same PC we used for the last java frame
3582 oop_maps->add_gc_map(the_pc - start,
3583 new OopMap( frame_size_in_words, 0 ));
3584
3585 // Clear fp AND pc
3586 __ reset_last_Java_frame(true, true);
3587
3588 // Collect return values
3589 __ movdbl(xmm0, Address(rsp, RegisterSaver::xmm0_offset_in_bytes()));
3590 __ movptr(rax, Address(rsp, RegisterSaver::rax_offset_in_bytes()));
3591 // I think this is useless (throwing pc?)
3592 __ movptr(rdx, Address(rsp, RegisterSaver::rdx_offset_in_bytes()));
3593
3594 // Pop self-frame.
3595 __ leave(); // Epilog
3596
3597 // Jump to interpreter
3598 __ ret(0);
3599
3600 // Make sure all code is generated
3601 masm->flush();
3602
3603 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words);
3604 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
3605 }
3606
3607 #ifdef COMPILER2
3608 //------------------------------generate_uncommon_trap_blob--------------------
3609 void SharedRuntime::generate_uncommon_trap_blob() {
3610 // Allocate space for the code
3611 ResourceMark rm;
3612 // Setup code generation tools
3613 CodeBuffer buffer("uncommon_trap_blob", 2048, 1024);
3614 MacroAssembler* masm = new MacroAssembler(&buffer);
3615
3616 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
3617
3618 address start = __ pc();
3619
3620 if (UseRTMLocking) {
3621 // Abort RTM transaction before possible nmethod deoptimization.
3622 __ xabort(0);
3623 }
3624
3625 // Push self-frame. We get here with a return address on the
3626 // stack, so rsp is 8-byte aligned until we allocate our frame.
3627 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog!
3628
3629 // No callee saved registers. rbp is assumed implicitly saved
3630 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
3631
3632 // compiler left unloaded_class_index in j_rarg0 move to where the
3633 // runtime expects it.
3634 __ movl(c_rarg1, j_rarg0);
3635
3636 __ set_last_Java_frame(noreg, noreg, NULL);
3637
3638 // Call C code. Need thread but NOT official VM entry
3639 // crud. We cannot block on this call, no GC can happen. Call should
3640 // capture callee-saved registers as well as return values.
3641 // Thread is in rdi already.
3642 //
3643 // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index);
3644
3645 __ mov(c_rarg0, r15_thread);
3646 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)));
3647
3648 // Set an oopmap for the call site
3649 OopMapSet* oop_maps = new OopMapSet();
3650 OopMap* map = new OopMap(SimpleRuntimeFrame::framesize, 0);
3651
3652 // location of rbp is known implicitly by the frame sender code
3653
3654 oop_maps->add_gc_map(__ pc() - start, map);
3655
3656 __ reset_last_Java_frame(false, false);
3657
3658 // Load UnrollBlock* into rdi
3659 __ mov(rdi, rax);
3660
3661 // Pop all the frames we must move/replace.
3662 //
3663 // Frame picture (youngest to oldest)
3664 // 1: self-frame (no frame link)
3665 // 2: deopting frame (no frame link)
3666 // 3: caller of deopting frame (could be compiled/interpreted).
3667
3668 // Pop self-frame. We have no frame, and must rely only on rax and rsp.
3669 __ addptr(rsp, (SimpleRuntimeFrame::framesize - 2) << LogBytesPerInt); // Epilog!
3670
3671 // Pop deoptimized frame (int)
3672 __ movl(rcx, Address(rdi,
3673 Deoptimization::UnrollBlock::
3674 size_of_deoptimized_frame_offset_in_bytes()));
3675 __ addptr(rsp, rcx);
3676
3677 // rsp should be pointing at the return address to the caller (3)
3678
3679 // Pick up the initial fp we should save
3680 // restore rbp before stack bang because if stack overflow is thrown it needs to be pushed (and preserved)
3681 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
3682
3683 // Stack bang to make sure there's enough room for these interpreter frames.
3684 if (UseStackBanging) {
3685 __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
3686 __ bang_stack_size(rbx, rcx);
3687 }
3688
3689 // Load address of array of frame pcs into rcx (address*)
3690 __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
3691
3692 // Trash the return pc
3693 __ addptr(rsp, wordSize);
3694
3695 // Load address of array of frame sizes into rsi (intptr_t*)
3696 __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock:: frame_sizes_offset_in_bytes()));
3697
3698 // Counter
3699 __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock:: number_of_frames_offset_in_bytes())); // (int)
3700
3701 // Now adjust the caller's stack to make up for the extra locals but
3702 // record the original sp so that we can save it in the skeletal
3703 // interpreter frame and the stack walking of interpreter_sender
3704 // will get the unextended sp value and not the "real" sp value.
3705
3706 const Register sender_sp = r8;
3707
3708 __ mov(sender_sp, rsp);
3709 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock:: caller_adjustment_offset_in_bytes())); // (int)
3710 __ subptr(rsp, rbx);
3711
3712 // Push interpreter frames in a loop
3713 Label loop;
3714 __ bind(loop);
3715 __ movptr(rbx, Address(rsi, 0)); // Load frame size
3716 __ subptr(rbx, 2 * wordSize); // We'll push pc and rbp by hand
3717 __ pushptr(Address(rcx, 0)); // Save return address
3718 __ enter(); // Save old & set new rbp
3719 __ subptr(rsp, rbx); // Prolog
3720 #ifdef CC_INTERP
3721 __ movptr(Address(rbp,
3722 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
3723 sender_sp); // Make it walkable
3724 #else // CC_INTERP
3725 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize),
3726 sender_sp); // Make it walkable
3727 // This value is corrected by layout_activation_impl
3728 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
3729 #endif // CC_INTERP
3730 __ mov(sender_sp, rsp); // Pass sender_sp to next frame
3731 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
3732 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
3733 __ decrementl(rdx); // Decrement counter
3734 __ jcc(Assembler::notZero, loop);
3735 __ pushptr(Address(rcx, 0)); // Save final return address
3736
3737 // Re-push self-frame
3738 __ enter(); // Save old & set new rbp
3739 __ subptr(rsp, (SimpleRuntimeFrame::framesize - 4) << LogBytesPerInt);
3740 // Prolog
3741
3742 // Use rbp because the frames look interpreted now
3743 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP.
3744 // Don't need the precise return PC here, just precise enough to point into this code blob.
3745 address the_pc = __ pc();
3746 __ set_last_Java_frame(noreg, rbp, the_pc);
3747
3748 // Call C code. Need thread but NOT official VM entry
3749 // crud. We cannot block on this call, no GC can happen. Call should
3750 // restore return values to their stack-slots with the new SP.
3751 // Thread is in rdi already.
3752 //
3753 // BasicType unpack_frames(JavaThread* thread, int exec_mode);
3754
3755 __ andptr(rsp, -(StackAlignmentInBytes)); // Align SP as required by ABI
3756 __ mov(c_rarg0, r15_thread);
3757 __ movl(c_rarg1, Deoptimization::Unpack_uncommon_trap);
3758 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
3759
3760 // Set an oopmap for the call site
3761 // Use the same PC we used for the last java frame
3762 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0));
3763
3764 // Clear fp AND pc
3765 __ reset_last_Java_frame(true, true);
3766
3767 // Pop self-frame.
3768 __ leave(); // Epilog
3769
3770 // Jump to interpreter
3771 __ ret(0);
3772
3773 // Make sure all code is generated
3774 masm->flush();
3775
3776 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps,
3777 SimpleRuntimeFrame::framesize >> 1);
3778 }
3779 #endif // COMPILER2
3780
3781
3782 //------------------------------generate_handler_blob------
3783 //
3784 // Generate a special Compile2Runtime blob that saves all registers,
3785 // and setup oopmap.
3786 //
3787 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) {
3788 assert(StubRoutines::forward_exception_entry() != NULL,
3789 "must be generated before");
3790
3791 ResourceMark rm;
3792 OopMapSet *oop_maps = new OopMapSet();
3793 OopMap* map;
3794
3795 // Allocate space for the code. Setup code generation tools.
3796 CodeBuffer buffer("handler_blob", 2048, 1024);
3797 MacroAssembler* masm = new MacroAssembler(&buffer);
3798
3799 address start = __ pc();
3800 address call_pc = NULL;
3801 int frame_size_in_words;
3802 bool cause_return = (poll_type == POLL_AT_RETURN);
3803 bool save_vectors = (poll_type == POLL_AT_VECTOR_LOOP);
3804
3805 if (UseRTMLocking) {
3806 // Abort RTM transaction before calling runtime
3807 // because critical section will be large and will be
3808 // aborted anyway. Also nmethod could be deoptimized.
3809 __ xabort(0);
3810 }
3811
3812 // Make room for return address (or push it again)
3813 if (!cause_return) {
3814 __ push(rbx);
3815 }
3816
3817 // Save registers, fpu state, and flags
3818 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, save_vectors);
3819
3820 // The following is basically a call_VM. However, we need the precise
3821 // address of the call in order to generate an oopmap. Hence, we do all the
3822 // work outselves.
3823
3824 __ set_last_Java_frame(noreg, noreg, NULL);
3825
3826 // The return address must always be correct so that frame constructor never
3827 // sees an invalid pc.
3828
3829 if (!cause_return) {
3830 // overwrite the dummy value we pushed on entry
3831 __ movptr(c_rarg0, Address(r15_thread, JavaThread::saved_exception_pc_offset()));
3832 __ movptr(Address(rbp, wordSize), c_rarg0);
3833 }
3834
3835 // Do the call
3836 __ mov(c_rarg0, r15_thread);
3837 __ call(RuntimeAddress(call_ptr));
3838
3839 // Set an oopmap for the call site. This oopmap will map all
3840 // oop-registers and debug-info registers as callee-saved. This
3841 // will allow deoptimization at this safepoint to find all possible
3842 // debug-info recordings, as well as let GC find all oops.
3843
3844 oop_maps->add_gc_map( __ pc() - start, map);
3845
3846 Label noException;
3847
3848 __ reset_last_Java_frame(false, false);
3849
3850 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3851 __ jcc(Assembler::equal, noException);
3852
3853 // Exception pending
3854
3855 RegisterSaver::restore_live_registers(masm, save_vectors);
3856
3857 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3858
3859 // No exception case
3860 __ bind(noException);
3861
3862 // Normal exit, restore registers and exit.
3863 RegisterSaver::restore_live_registers(masm, save_vectors);
3864
3865 __ ret(0);
3866
3867 // Make sure all code is generated
3868 masm->flush();
3869
3870 // Fill-out other meta info
3871 return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words);
3872 }
3873
3874 //
3875 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
3876 //
3877 // Generate a stub that calls into vm to find out the proper destination
3878 // of a java call. All the argument registers are live at this point
3879 // but since this is generic code we don't know what they are and the caller
3880 // must do any gc of the args.
3881 //
3882 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) {
3883 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3884
3885 // allocate space for the code
3886 ResourceMark rm;
3887
3888 CodeBuffer buffer(name, 1000, 512);
3889 MacroAssembler* masm = new MacroAssembler(&buffer);
3890
3891 int frame_size_in_words;
3892
3893 OopMapSet *oop_maps = new OopMapSet();
3894 OopMap* map = NULL;
3895
3896 int start = __ offset();
3897
3898 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3899
3900 int frame_complete = __ offset();
3901
3902 __ set_last_Java_frame(noreg, noreg, NULL);
3903
3904 __ mov(c_rarg0, r15_thread);
3905
3906 __ call(RuntimeAddress(destination));
3907
3908
3909 // Set an oopmap for the call site.
3910 // We need this not only for callee-saved registers, but also for volatile
3911 // registers that the compiler might be keeping live across a safepoint.
3912
3913 oop_maps->add_gc_map( __ offset() - start, map);
3914
3915 // rax contains the address we are going to jump to assuming no exception got installed
3916
3917 // clear last_Java_sp
3918 __ reset_last_Java_frame(false, false);
3919 // check for pending exceptions
3920 Label pending;
3921 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3922 __ jcc(Assembler::notEqual, pending);
3923
3924 // get the returned Method*
3925 __ get_vm_result_2(rbx, r15_thread);
3926 __ movptr(Address(rsp, RegisterSaver::rbx_offset_in_bytes()), rbx);
3927
3928 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3929
3930 RegisterSaver::restore_live_registers(masm);
3931
3932 // We are back the the original state on entry and ready to go.
3933
3934 __ jmp(rax);
3935
3936 // Pending exception after the safepoint
3937
3938 __ bind(pending);
3939
3940 RegisterSaver::restore_live_registers(masm);
3941
3942 // exception pending => remove activation and forward to exception handler
3943
3944 __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int)NULL_WORD);
3945
3946 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
3947 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3948
3949 // -------------
3950 // make sure all code is generated
3951 masm->flush();
3952
3953 // return the blob
3954 // frame_size_words or bytes??
3955 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_in_words, oop_maps, true);
3956 }
3957
3958
3959 #ifdef COMPILER2
3960 // This is here instead of runtime_x86_64.cpp because it uses SimpleRuntimeFrame
3961 //
3962 //------------------------------generate_exception_blob---------------------------
3963 // creates exception blob at the end
3964 // Using exception blob, this code is jumped from a compiled method.
3965 // (see emit_exception_handler in x86_64.ad file)
3966 //
3967 // Given an exception pc at a call we call into the runtime for the
3968 // handler in this method. This handler might merely restore state
3969 // (i.e. callee save registers) unwind the frame and jump to the
3970 // exception handler for the nmethod if there is no Java level handler
3971 // for the nmethod.
3972 //
3973 // This code is entered with a jmp.
3974 //
3975 // Arguments:
3976 // rax: exception oop
3977 // rdx: exception pc
3978 //
3979 // Results:
3980 // rax: exception oop
3981 // rdx: exception pc in caller or ???
3982 // destination: exception handler of caller
3983 //
3984 // Note: the exception pc MUST be at a call (precise debug information)
3985 // Registers rax, rdx, rcx, rsi, rdi, r8-r11 are not callee saved.
3986 //
3987
3988 void OptoRuntime::generate_exception_blob() {
3989 assert(!OptoRuntime::is_callee_saved_register(RDX_num), "");
3990 assert(!OptoRuntime::is_callee_saved_register(RAX_num), "");
3991 assert(!OptoRuntime::is_callee_saved_register(RCX_num), "");
3992
3993 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
3994
3995 // Allocate space for the code
3996 ResourceMark rm;
3997 // Setup code generation tools
3998 CodeBuffer buffer("exception_blob", 2048, 1024);
3999 MacroAssembler* masm = new MacroAssembler(&buffer);
4000
4001
4002 address start = __ pc();
4003
4004 // Exception pc is 'return address' for stack walker
4005 __ push(rdx);
4006 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Prolog
4007
4008 // Save callee-saved registers. See x86_64.ad.
4009
4010 // rbp is an implicitly saved callee saved register (i.e. the calling
4011 // convention will save restore it in prolog/epilog) Other than that
4012 // there are no callee save registers now that adapter frames are gone.
4013
4014 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
4015
4016 // Store exception in Thread object. We cannot pass any arguments to the
4017 // handle_exception call, since we do not want to make any assumption
4018 // about the size of the frame where the exception happened in.
4019 // c_rarg0 is either rdi (Linux) or rcx (Windows).
4020 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()),rax);
4021 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
4022
4023 // This call does all the hard work. It checks if an exception handler
4024 // exists in the method.
4025 // If so, it returns the handler address.
4026 // If not, it prepares for stack-unwinding, restoring the callee-save
4027 // registers of the frame being removed.
4028 //
4029 // address OptoRuntime::handle_exception_C(JavaThread* thread)
4030
4031 // At a method handle call, the stack may not be properly aligned
4032 // when returning with an exception.
4033 address the_pc = __ pc();
4034 __ set_last_Java_frame(noreg, noreg, the_pc);
4035 __ mov(c_rarg0, r15_thread);
4036 __ andptr(rsp, -(StackAlignmentInBytes)); // Align stack
4037 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C)));
4038
4039 // Set an oopmap for the call site. This oopmap will only be used if we
4040 // are unwinding the stack. Hence, all locations will be dead.
4041 // Callee-saved registers will be the same as the frame above (i.e.,
4042 // handle_exception_stub), since they were restored when we got the
4043 // exception.
4044
4045 OopMapSet* oop_maps = new OopMapSet();
4046
4047 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0));
4048
4049 __ reset_last_Java_frame(false, true);
4050
4051 // Restore callee-saved registers
4052
4053 // rbp is an implicitly saved callee saved register (i.e. the calling
4054 // convention will save restore it in prolog/epilog) Other than that
4055 // there are no callee save registers no that adapter frames are gone.
4056
4057 __ movptr(rbp, Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt));
4058
4059 __ addptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog
4060 __ pop(rdx); // No need for exception pc anymore
4061
4062 // rax: exception handler
4063
4064 // Restore SP from BP if the exception PC is a MethodHandle call site.
4065 __ cmpl(Address(r15_thread, JavaThread::is_method_handle_return_offset()), 0);
4066 __ cmovptr(Assembler::notEqual, rsp, rbp_mh_SP_save);
4067
4068 // We have a handler in rax (could be deopt blob).
4069 __ mov(r8, rax);
4070
4071 // Get the exception oop
4072 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
4073 // Get the exception pc in case we are deoptimized
4074 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
4075 #ifdef ASSERT
4076 __ movptr(Address(r15_thread, JavaThread::exception_handler_pc_offset()), (int)NULL_WORD);
4077 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int)NULL_WORD);
4078 #endif
4079 // Clear the exception oop so GC no longer processes it as a root.
4080 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int)NULL_WORD);
4081
4082 // rax: exception oop
4083 // r8: exception handler
4084 // rdx: exception pc
4085 // Jump to handler
4086
4087 __ jmp(r8);
4088
4089 // Make sure all code is generated
4090 masm->flush();
4091
4092 // Set exception blob
4093 _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1);
4094 }
4095 #endif // COMPILER2