1 //
   2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
   3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4 //
   5 // This code is free software; you can redistribute it and/or modify it
   6 // under the terms of the GNU General Public License version 2 only, as
   7 // published by the Free Software Foundation.
   8 //
   9 // This code is distributed in the hope that it will be useful, but WITHOUT
  10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12 // version 2 for more details (a copy is included in the LICENSE file that
  13 // accompanied this code).
  14 //
  15 // You should have received a copy of the GNU General Public License version
  16 // 2 along with this work; if not, write to the Free Software Foundation,
  17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18 //
  19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20 // or visit www.oracle.com if you need additional information or have any
  21 // questions.
  22 //
  23 //
  24 
  25 // X86 Architecture Description File
  26 
  27 //----------REGISTER DEFINITION BLOCK------------------------------------------
  28 // This information is used by the matcher and the register allocator to
  29 // describe individual registers and classes of registers within the target
  30 // archtecture.
  31 
  32 register %{
  33 //----------Architecture Description Register Definitions----------------------
  34 // General Registers
  35 // "reg_def"  name ( register save type, C convention save type,
  36 //                   ideal register type, encoding );
  37 // Register Save Types:
  38 //
  39 // NS  = No-Save:       The register allocator assumes that these registers
  40 //                      can be used without saving upon entry to the method, &
  41 //                      that they do not need to be saved at call sites.
  42 //
  43 // SOC = Save-On-Call:  The register allocator assumes that these registers
  44 //                      can be used without saving upon entry to the method,
  45 //                      but that they must be saved at call sites.
  46 //
  47 // SOE = Save-On-Entry: The register allocator assumes that these registers
  48 //                      must be saved before using them upon entry to the
  49 //                      method, but they do not need to be saved at call
  50 //                      sites.
  51 //
  52 // AS  = Always-Save:   The register allocator assumes that these registers
  53 //                      must be saved before using them upon entry to the
  54 //                      method, & that they must be saved at call sites.
  55 //
  56 // Ideal Register Type is used to determine how to save & restore a
  57 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  58 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
  59 //
  60 // The encoding number is the actual bit-pattern placed into the opcodes.
  61 
  62 // General Registers
  63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
  64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
  65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
  66 
  67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
  68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
  69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
  70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
  71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
  72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
  73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
  74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
  75 reg_def ESP( NS,  NS, Op_RegI, 4, rsp->as_VMReg());
  76 
  77 // Float registers.  We treat TOS/FPR0 special.  It is invisible to the
  78 // allocator, and only shows up in the encodings.
  79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
  80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
  81 // Ok so here's the trick FPR1 is really st(0) except in the midst
  82 // of emission of assembly for a machnode. During the emission the fpu stack
  83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
  84 // the stack will not have this element so FPR1 == st(0) from the
  85 // oopMap viewpoint. This same weirdness with numbering causes
  86 // instruction encoding to have to play games with the register
  87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
  88 // where it does flt->flt moves to see an example
  89 //
  90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
  91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
  92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
  93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
  94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
  95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
  96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
  97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
  98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
  99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
 100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
 101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
 102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
 103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
 104 
 105 // Specify priority of register selection within phases of register
 106 // allocation.  Highest priority is first.  A useful heuristic is to
 107 // give registers a low priority when they are required by machine
 108 // instructions, like EAX and EDX.  Registers which are used as
 109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
 110 // For the Intel integer registers, the equivalent Long pairs are
 111 // EDX:EAX, EBX:ECX, and EDI:EBP.
 112 alloc_class chunk0( ECX,   EBX,   EBP,   EDI,   EAX,   EDX,   ESI, ESP,
 113                     FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
 114                     FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
 115                     FPR6L, FPR6H, FPR7L, FPR7H );
 116 
 117 
 118 //----------Architecture Description Register Classes--------------------------
 119 // Several register classes are automatically defined based upon information in
 120 // this architecture description.
 121 // 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )
 122 // 2) reg_class compiler_method_oop_reg    ( /* as def'd in frame section */ )
 123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
 124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 125 //
 126 // Class for all registers
 127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
 128 // Class for general registers
 129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
 130 // Class for general registers which may be used for implicit null checks on win95
 131 // Also safe for use by tailjump. We don't want to allocate in rbp,
 132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
 133 // Class of "X" registers
 134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
 135 // Class of registers that can appear in an address with no offset.
 136 // EBP and ESP require an extra instruction byte for zero offset.
 137 // Used in fast-unlock
 138 reg_class p_reg(EDX, EDI, ESI, EBX);
 139 // Class for general registers not including ECX
 140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
 141 // Class for general registers not including EAX
 142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
 143 // Class for general registers not including EAX or EBX.
 144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
 145 // Class of EAX (for multiply and divide operations)
 146 reg_class eax_reg(EAX);
 147 // Class of EBX (for atomic add)
 148 reg_class ebx_reg(EBX);
 149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
 150 reg_class ecx_reg(ECX);
 151 // Class of EDX (for multiply and divide operations)
 152 reg_class edx_reg(EDX);
 153 // Class of EDI (for synchronization)
 154 reg_class edi_reg(EDI);
 155 // Class of ESI (for synchronization)
 156 reg_class esi_reg(ESI);
 157 // Singleton class for interpreter's stack pointer
 158 reg_class ebp_reg(EBP);
 159 // Singleton class for stack pointer
 160 reg_class sp_reg(ESP);
 161 // Singleton class for instruction pointer
 162 // reg_class ip_reg(EIP);
 163 // Class of integer register pairs
 164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
 165 // Class of integer register pairs that aligns with calling convention
 166 reg_class eadx_reg( EAX,EDX );
 167 reg_class ebcx_reg( ECX,EBX );
 168 // Not AX or DX, used in divides
 169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
 170 
 171 // Floating point registers.  Notice FPR0 is not a choice.
 172 // FPR0 is not ever allocated; we use clever encodings to fake
 173 // a 2-address instructions out of Intels FP stack.
 174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
 175 
 176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
 177                       FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
 178                       FPR7L,FPR7H );
 179 
 180 reg_class fp_flt_reg0( FPR1L );
 181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
 182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
 183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
 184                           FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
 185 
 186 %}
 187 
 188 
 189 //----------SOURCE BLOCK-------------------------------------------------------
 190 // This is a block of C++ code which provides values, functions, and
 191 // definitions necessary in the rest of the architecture description
 192 source_hpp %{
 193 // Must be visible to the DFA in dfa_x86_32.cpp
 194 extern bool is_operand_hi32_zero(Node* n);
 195 %}
 196 
 197 source %{
 198 #define   RELOC_IMM32    Assembler::imm_operand
 199 #define   RELOC_DISP32   Assembler::disp32_operand
 200 
 201 #define __ _masm.
 202 
 203 // How to find the high register of a Long pair, given the low register
 204 #define   HIGH_FROM_LOW(x) ((x)+2)
 205 
 206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
 207 // instructions, to allow sign-masking or sign-bit flipping.  They allow
 208 // fast versions of NegF/NegD and AbsF/AbsD.
 209 
 210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
 211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
 212   // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
 213   // of 128-bits operands for SSE instructions.
 214   jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
 215   // Store the value to a 128-bits operand.
 216   operand[0] = lo;
 217   operand[1] = hi;
 218   return operand;
 219 }
 220 
 221 // Buffer for 128-bits masks used by SSE instructions.
 222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
 223 
 224 // Static initialization during VM startup.
 225 static jlong *float_signmask_pool  = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
 226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
 227 static jlong *float_signflip_pool  = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
 228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
 229 
 230 // Offset hacking within calls.
 231 static int pre_call_resets_size() {
 232   int size = 0;
 233   Compile* C = Compile::current();
 234   if (C->in_24_bit_fp_mode()) {
 235     size += 6; // fldcw
 236   }
 237   if (C->max_vector_size() > 16) {
 238     size += 3; // vzeroupper
 239   }
 240   return size;
 241 }
 242 
 243 static int preserve_SP_size() {
 244   return 2;  // op, rm(reg/reg)
 245 }
 246 
 247 // !!!!! Special hack to get all type of calls to specify the byte offset
 248 //       from the start of the call to the point where the return address
 249 //       will point.
 250 int MachCallStaticJavaNode::ret_addr_offset() {
 251   int offset = 5 + pre_call_resets_size();  // 5 bytes from start of call to where return address points
 252   if (_method_handle_invoke)
 253     offset += preserve_SP_size();
 254   return offset;
 255 }
 256 
 257 int MachCallDynamicJavaNode::ret_addr_offset() {
 258   return 10 + pre_call_resets_size();  // 10 bytes from start of call to where return address points
 259 }
 260 
 261 static int sizeof_FFree_Float_Stack_All = -1;
 262 
 263 int MachCallRuntimeNode::ret_addr_offset() {
 264   assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
 265   return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
 266 }
 267 
 268 // Indicate if the safepoint node needs the polling page as an input.
 269 // Since x86 does have absolute addressing, it doesn't.
 270 bool SafePointNode::needs_polling_address_input() {
 271   return false;
 272 }
 273 
 274 //
 275 // Compute padding required for nodes which need alignment
 276 //
 277 
 278 // The address of the call instruction needs to be 4-byte aligned to
 279 // ensure that it does not span a cache line so that it can be patched.
 280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
 281   current_offset += pre_call_resets_size();  // skip fldcw, if any
 282   current_offset += 1;      // skip call opcode byte
 283   return round_to(current_offset, alignment_required()) - current_offset;
 284 }
 285 
 286 // The address of the call instruction needs to be 4-byte aligned to
 287 // ensure that it does not span a cache line so that it can be patched.
 288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
 289   current_offset += pre_call_resets_size();  // skip fldcw, if any
 290   current_offset += preserve_SP_size();   // skip mov rbp, rsp
 291   current_offset += 1;      // skip call opcode byte
 292   return round_to(current_offset, alignment_required()) - current_offset;
 293 }
 294 
 295 // The address of the call instruction needs to be 4-byte aligned to
 296 // ensure that it does not span a cache line so that it can be patched.
 297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
 298   current_offset += pre_call_resets_size();  // skip fldcw, if any
 299   current_offset += 5;      // skip MOV instruction
 300   current_offset += 1;      // skip call opcode byte
 301   return round_to(current_offset, alignment_required()) - current_offset;
 302 }
 303 
 304 // EMIT_RM()
 305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
 306   unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
 307   cbuf.insts()->emit_int8(c);
 308 }
 309 
 310 // EMIT_CC()
 311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
 312   unsigned char c = (unsigned char)( f1 | f2 );
 313   cbuf.insts()->emit_int8(c);
 314 }
 315 
 316 // EMIT_OPCODE()
 317 void emit_opcode(CodeBuffer &cbuf, int code) {
 318   cbuf.insts()->emit_int8((unsigned char) code);
 319 }
 320 
 321 // EMIT_OPCODE() w/ relocation information
 322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
 323   cbuf.relocate(cbuf.insts_mark() + offset, reloc);
 324   emit_opcode(cbuf, code);
 325 }
 326 
 327 // EMIT_D8()
 328 void emit_d8(CodeBuffer &cbuf, int d8) {
 329   cbuf.insts()->emit_int8((unsigned char) d8);
 330 }
 331 
 332 // EMIT_D16()
 333 void emit_d16(CodeBuffer &cbuf, int d16) {
 334   cbuf.insts()->emit_int16(d16);
 335 }
 336 
 337 // EMIT_D32()
 338 void emit_d32(CodeBuffer &cbuf, int d32) {
 339   cbuf.insts()->emit_int32(d32);
 340 }
 341 
 342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
 343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
 344         int format) {
 345   cbuf.relocate(cbuf.insts_mark(), reloc, format);
 346   cbuf.insts()->emit_int32(d32);
 347 }
 348 
 349 // emit 32 bit value and construct relocation entry from RelocationHolder
 350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
 351         int format) {
 352 #ifdef ASSERT
 353   if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
 354     assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
 355   }
 356 #endif
 357   cbuf.relocate(cbuf.insts_mark(), rspec, format);
 358   cbuf.insts()->emit_int32(d32);
 359 }
 360 
 361 // Access stack slot for load or store
 362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
 363   emit_opcode( cbuf, opcode );               // (e.g., FILD   [ESP+src])
 364   if( -128 <= disp && disp <= 127 ) {
 365     emit_rm( cbuf, 0x01, rm_field, ESP_enc );  // R/M byte
 366     emit_rm( cbuf, 0x00, ESP_enc, ESP_enc);    // SIB byte
 367     emit_d8 (cbuf, disp);     // Displacement  // R/M byte
 368   } else {
 369     emit_rm( cbuf, 0x02, rm_field, ESP_enc );  // R/M byte
 370     emit_rm( cbuf, 0x00, ESP_enc, ESP_enc);    // SIB byte
 371     emit_d32(cbuf, disp);     // Displacement  // R/M byte
 372   }
 373 }
 374 
 375    // rRegI ereg, memory mem) %{    // emit_reg_mem
 376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
 377   // There is no index & no scale, use form without SIB byte
 378   if ((index == 0x4) &&
 379       (scale == 0) && (base != ESP_enc)) {
 380     // If no displacement, mode is 0x0; unless base is [EBP]
 381     if ( (displace == 0) && (base != EBP_enc) ) {
 382       emit_rm(cbuf, 0x0, reg_encoding, base);
 383     }
 384     else {                    // If 8-bit displacement, mode 0x1
 385       if ((displace >= -128) && (displace <= 127)
 386           && (disp_reloc == relocInfo::none) ) {
 387         emit_rm(cbuf, 0x1, reg_encoding, base);
 388         emit_d8(cbuf, displace);
 389       }
 390       else {                  // If 32-bit displacement
 391         if (base == -1) { // Special flag for absolute address
 392           emit_rm(cbuf, 0x0, reg_encoding, 0x5);
 393           // (manual lies; no SIB needed here)
 394           if ( disp_reloc != relocInfo::none ) {
 395             emit_d32_reloc(cbuf, displace, disp_reloc, 1);
 396           } else {
 397             emit_d32      (cbuf, displace);
 398           }
 399         }
 400         else {                // Normal base + offset
 401           emit_rm(cbuf, 0x2, reg_encoding, base);
 402           if ( disp_reloc != relocInfo::none ) {
 403             emit_d32_reloc(cbuf, displace, disp_reloc, 1);
 404           } else {
 405             emit_d32      (cbuf, displace);
 406           }
 407         }
 408       }
 409     }
 410   }
 411   else {                      // Else, encode with the SIB byte
 412     // If no displacement, mode is 0x0; unless base is [EBP]
 413     if (displace == 0 && (base != EBP_enc)) {  // If no displacement
 414       emit_rm(cbuf, 0x0, reg_encoding, 0x4);
 415       emit_rm(cbuf, scale, index, base);
 416     }
 417     else {                    // If 8-bit displacement, mode 0x1
 418       if ((displace >= -128) && (displace <= 127)
 419           && (disp_reloc == relocInfo::none) ) {
 420         emit_rm(cbuf, 0x1, reg_encoding, 0x4);
 421         emit_rm(cbuf, scale, index, base);
 422         emit_d8(cbuf, displace);
 423       }
 424       else {                  // If 32-bit displacement
 425         if (base == 0x04 ) {
 426           emit_rm(cbuf, 0x2, reg_encoding, 0x4);
 427           emit_rm(cbuf, scale, index, 0x04);
 428         } else {
 429           emit_rm(cbuf, 0x2, reg_encoding, 0x4);
 430           emit_rm(cbuf, scale, index, base);
 431         }
 432         if ( disp_reloc != relocInfo::none ) {
 433           emit_d32_reloc(cbuf, displace, disp_reloc, 1);
 434         } else {
 435           emit_d32      (cbuf, displace);
 436         }
 437       }
 438     }
 439   }
 440 }
 441 
 442 
 443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
 444   if( dst_encoding == src_encoding ) {
 445     // reg-reg copy, use an empty encoding
 446   } else {
 447     emit_opcode( cbuf, 0x8B );
 448     emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
 449   }
 450 }
 451 
 452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
 453   Label exit;
 454   __ jccb(Assembler::noParity, exit);
 455   __ pushf();
 456   //
 457   // comiss/ucomiss instructions set ZF,PF,CF flags and
 458   // zero OF,AF,SF for NaN values.
 459   // Fixup flags by zeroing ZF,PF so that compare of NaN
 460   // values returns 'less than' result (CF is set).
 461   // Leave the rest of flags unchanged.
 462   //
 463   //    7 6 5 4 3 2 1 0
 464   //   |S|Z|r|A|r|P|r|C|  (r - reserved bit)
 465   //    0 0 1 0 1 0 1 1   (0x2B)
 466   //
 467   __ andl(Address(rsp, 0), 0xffffff2b);
 468   __ popf();
 469   __ bind(exit);
 470 }
 471 
 472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
 473   Label done;
 474   __ movl(dst, -1);
 475   __ jcc(Assembler::parity, done);
 476   __ jcc(Assembler::below, done);
 477   __ setb(Assembler::notEqual, dst);
 478   __ movzbl(dst, dst);
 479   __ bind(done);
 480 }
 481 
 482 
 483 //=============================================================================
 484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
 485 
 486 int Compile::ConstantTable::calculate_table_base_offset() const {
 487   return 0;  // absolute addressing, no offset
 488 }
 489 
 490 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
 491   // Empty encoding
 492 }
 493 
 494 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
 495   return 0;
 496 }
 497 
 498 #ifndef PRODUCT
 499 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 500   st->print("# MachConstantBaseNode (empty encoding)");
 501 }
 502 #endif
 503 
 504 
 505 //=============================================================================
 506 #ifndef PRODUCT
 507 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 508   Compile* C = ra_->C;
 509 
 510   int framesize = C->frame_slots() << LogBytesPerInt;
 511   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 512   // Remove wordSize for return addr which is already pushed.
 513   framesize -= wordSize;
 514 
 515   if (C->need_stack_bang(framesize)) {
 516     framesize -= wordSize;
 517     st->print("# stack bang");
 518     st->print("\n\t");
 519     st->print("PUSH   EBP\t# Save EBP");
 520     if (framesize) {
 521       st->print("\n\t");
 522       st->print("SUB    ESP, #%d\t# Create frame",framesize);
 523     }
 524   } else {
 525     st->print("SUB    ESP, #%d\t# Create frame",framesize);
 526     st->print("\n\t");
 527     framesize -= wordSize;
 528     st->print("MOV    [ESP + #%d], EBP\t# Save EBP",framesize);
 529   }
 530 
 531   if (VerifyStackAtCalls) {
 532     st->print("\n\t");
 533     framesize -= wordSize;
 534     st->print("MOV    [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
 535   }
 536 
 537   if( C->in_24_bit_fp_mode() ) {
 538     st->print("\n\t");
 539     st->print("FLDCW  \t# load 24 bit fpu control word");
 540   }
 541   if (UseSSE >= 2 && VerifyFPU) {
 542     st->print("\n\t");
 543     st->print("# verify FPU stack (must be clean on entry)");
 544   }
 545 
 546 #ifdef ASSERT
 547   if (VerifyStackAtCalls) {
 548     st->print("\n\t");
 549     st->print("# stack alignment check");
 550   }
 551 #endif
 552   st->cr();
 553 }
 554 #endif
 555 
 556 
 557 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 558   Compile* C = ra_->C;
 559   MacroAssembler _masm(&cbuf);
 560 
 561   int framesize = C->frame_slots() << LogBytesPerInt;
 562 
 563   __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
 564 
 565   C->set_frame_complete(cbuf.insts_size());
 566 
 567   if (C->has_mach_constant_base_node()) {
 568     // NOTE: We set the table base offset here because users might be
 569     // emitted before MachConstantBaseNode.
 570     Compile::ConstantTable& constant_table = C->constant_table();
 571     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
 572   }
 573 }
 574 
 575 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
 576   return MachNode::size(ra_); // too many variables; just compute it the hard way
 577 }
 578 
 579 int MachPrologNode::reloc() const {
 580   return 0; // a large enough number
 581 }
 582 
 583 //=============================================================================
 584 #ifndef PRODUCT
 585 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
 586   Compile *C = ra_->C;
 587   int framesize = C->frame_slots() << LogBytesPerInt;
 588   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 589   // Remove two words for return addr and rbp,
 590   framesize -= 2*wordSize;
 591 
 592   if (C->max_vector_size() > 16) {
 593     st->print("VZEROUPPER");
 594     st->cr(); st->print("\t");
 595   }
 596   if (C->in_24_bit_fp_mode()) {
 597     st->print("FLDCW  standard control word");
 598     st->cr(); st->print("\t");
 599   }
 600   if (framesize) {
 601     st->print("ADD    ESP,%d\t# Destroy frame",framesize);
 602     st->cr(); st->print("\t");
 603   }
 604   st->print_cr("POPL   EBP"); st->print("\t");
 605   if (do_polling() && C->is_method_compilation()) {
 606     st->print("TEST   PollPage,EAX\t! Poll Safepoint");
 607     st->cr(); st->print("\t");
 608   }
 609 }
 610 #endif
 611 
 612 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 613   Compile *C = ra_->C;
 614 
 615   if (C->max_vector_size() > 16) {
 616     // Clear upper bits of YMM registers when current compiled code uses
 617     // wide vectors to avoid AVX <-> SSE transition penalty during call.
 618     MacroAssembler masm(&cbuf);
 619     masm.vzeroupper();
 620   }
 621   // If method set FPU control word, restore to standard control word
 622   if (C->in_24_bit_fp_mode()) {
 623     MacroAssembler masm(&cbuf);
 624     masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
 625   }
 626 
 627   int framesize = C->frame_slots() << LogBytesPerInt;
 628   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 629   // Remove two words for return addr and rbp,
 630   framesize -= 2*wordSize;
 631 
 632   // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
 633 
 634   if (framesize >= 128) {
 635     emit_opcode(cbuf, 0x81); // add  SP, #framesize
 636     emit_rm(cbuf, 0x3, 0x00, ESP_enc);
 637     emit_d32(cbuf, framesize);
 638   } else if (framesize) {
 639     emit_opcode(cbuf, 0x83); // add  SP, #framesize
 640     emit_rm(cbuf, 0x3, 0x00, ESP_enc);
 641     emit_d8(cbuf, framesize);
 642   }
 643 
 644   emit_opcode(cbuf, 0x58 | EBP_enc);
 645 
 646   if (do_polling() && C->is_method_compilation()) {
 647     cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
 648     emit_opcode(cbuf,0x85);
 649     emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
 650     emit_d32(cbuf, (intptr_t)os::get_polling_page());
 651   }
 652 }
 653 
 654 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
 655   Compile *C = ra_->C;
 656   // If method set FPU control word, restore to standard control word
 657   int size = C->in_24_bit_fp_mode() ? 6 : 0;
 658   if (C->max_vector_size() > 16) size += 3; // vzeroupper
 659   if (do_polling() && C->is_method_compilation()) size += 6;
 660 
 661   int framesize = C->frame_slots() << LogBytesPerInt;
 662   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 663   // Remove two words for return addr and rbp,
 664   framesize -= 2*wordSize;
 665 
 666   size++; // popl rbp,
 667 
 668   if (framesize >= 128) {
 669     size += 6;
 670   } else {
 671     size += framesize ? 3 : 0;
 672   }
 673   return size;
 674 }
 675 
 676 int MachEpilogNode::reloc() const {
 677   return 0; // a large enough number
 678 }
 679 
 680 const Pipeline * MachEpilogNode::pipeline() const {
 681   return MachNode::pipeline_class();
 682 }
 683 
 684 int MachEpilogNode::safepoint_offset() const { return 0; }
 685 
 686 //=============================================================================
 687 
 688 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
 689 static enum RC rc_class( OptoReg::Name reg ) {
 690 
 691   if( !OptoReg::is_valid(reg)  ) return rc_bad;
 692   if (OptoReg::is_stack(reg)) return rc_stack;
 693 
 694   VMReg r = OptoReg::as_VMReg(reg);
 695   if (r->is_Register()) return rc_int;
 696   if (r->is_FloatRegister()) {
 697     assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
 698     return rc_float;
 699   }
 700   assert(r->is_XMMRegister(), "must be");
 701   return rc_xmm;
 702 }
 703 
 704 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
 705                         int opcode, const char *op_str, int size, outputStream* st ) {
 706   if( cbuf ) {
 707     emit_opcode  (*cbuf, opcode );
 708     encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
 709 #ifndef PRODUCT
 710   } else if( !do_size ) {
 711     if( size != 0 ) st->print("\n\t");
 712     if( opcode == 0x8B || opcode == 0x89 ) { // MOV
 713       if( is_load ) st->print("%s   %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
 714       else          st->print("%s   [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
 715     } else { // FLD, FST, PUSH, POP
 716       st->print("%s [ESP + #%d]",op_str,offset);
 717     }
 718 #endif
 719   }
 720   int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
 721   return size+3+offset_size;
 722 }
 723 
 724 // Helper for XMM registers.  Extra opcode bits, limited syntax.
 725 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
 726                          int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
 727   if (cbuf) {
 728     MacroAssembler _masm(cbuf);
 729     if (reg_lo+1 == reg_hi) { // double move?
 730       if (is_load) {
 731         __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
 732       } else {
 733         __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
 734       }
 735     } else {
 736       if (is_load) {
 737         __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
 738       } else {
 739         __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
 740       }
 741     }
 742 #ifndef PRODUCT
 743   } else if (!do_size) {
 744     if (size != 0) st->print("\n\t");
 745     if (reg_lo+1 == reg_hi) { // double move?
 746       if (is_load) st->print("%s %s,[ESP + #%d]",
 747                               UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
 748                               Matcher::regName[reg_lo], offset);
 749       else         st->print("MOVSD  [ESP + #%d],%s",
 750                               offset, Matcher::regName[reg_lo]);
 751     } else {
 752       if (is_load) st->print("MOVSS  %s,[ESP + #%d]",
 753                               Matcher::regName[reg_lo], offset);
 754       else         st->print("MOVSS  [ESP + #%d],%s",
 755                               offset, Matcher::regName[reg_lo]);
 756     }
 757 #endif
 758   }
 759   int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
 760   // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
 761   return size+5+offset_size;
 762 }
 763 
 764 
 765 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
 766                             int src_hi, int dst_hi, int size, outputStream* st ) {
 767   if (cbuf) {
 768     MacroAssembler _masm(cbuf);
 769     if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
 770       __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
 771                 as_XMMRegister(Matcher::_regEncode[src_lo]));
 772     } else {
 773       __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
 774                 as_XMMRegister(Matcher::_regEncode[src_lo]));
 775     }
 776 #ifndef PRODUCT
 777   } else if (!do_size) {
 778     if (size != 0) st->print("\n\t");
 779     if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
 780       if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
 781         st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
 782       } else {
 783         st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
 784       }
 785     } else {
 786       if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
 787         st->print("MOVSD  %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
 788       } else {
 789         st->print("MOVSS  %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
 790       }
 791     }
 792 #endif
 793   }
 794   // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
 795   // Only MOVAPS SSE prefix uses 1 byte.
 796   int sz = 4;
 797   if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
 798       UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
 799   return size + sz;
 800 }
 801 
 802 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
 803                             int src_hi, int dst_hi, int size, outputStream* st ) {
 804   // 32-bit
 805   if (cbuf) {
 806     MacroAssembler _masm(cbuf);
 807     __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
 808              as_Register(Matcher::_regEncode[src_lo]));
 809 #ifndef PRODUCT
 810   } else if (!do_size) {
 811     st->print("movdl   %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
 812 #endif
 813   }
 814   return 4;
 815 }
 816 
 817 
 818 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
 819                                  int src_hi, int dst_hi, int size, outputStream* st ) {
 820   // 32-bit
 821   if (cbuf) {
 822     MacroAssembler _masm(cbuf);
 823     __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
 824              as_XMMRegister(Matcher::_regEncode[src_lo]));
 825 #ifndef PRODUCT
 826   } else if (!do_size) {
 827     st->print("movdl   %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
 828 #endif
 829   }
 830   return 4;
 831 }
 832 
 833 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
 834   if( cbuf ) {
 835     emit_opcode(*cbuf, 0x8B );
 836     emit_rm    (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
 837 #ifndef PRODUCT
 838   } else if( !do_size ) {
 839     if( size != 0 ) st->print("\n\t");
 840     st->print("MOV    %s,%s",Matcher::regName[dst],Matcher::regName[src]);
 841 #endif
 842   }
 843   return size+2;
 844 }
 845 
 846 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
 847                                  int offset, int size, outputStream* st ) {
 848   if( src_lo != FPR1L_num ) {      // Move value to top of FP stack, if not already there
 849     if( cbuf ) {
 850       emit_opcode( *cbuf, 0xD9 );  // FLD (i.e., push it)
 851       emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
 852 #ifndef PRODUCT
 853     } else if( !do_size ) {
 854       if( size != 0 ) st->print("\n\t");
 855       st->print("FLD    %s",Matcher::regName[src_lo]);
 856 #endif
 857     }
 858     size += 2;
 859   }
 860 
 861   int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
 862   const char *op_str;
 863   int op;
 864   if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
 865     op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
 866     op = 0xDD;
 867   } else {                   // 32-bit store
 868     op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
 869     op = 0xD9;
 870     assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
 871   }
 872 
 873   return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
 874 }
 875 
 876 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
 877 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
 878                           int src_hi, int dst_hi, uint ireg, outputStream* st);
 879 
 880 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
 881                             int stack_offset, int reg, uint ireg, outputStream* st);
 882 
 883 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
 884                                      int dst_offset, uint ireg, outputStream* st) {
 885   int calc_size = 0;
 886   int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
 887   int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
 888   switch (ireg) {
 889   case Op_VecS:
 890     calc_size = 3+src_offset_size + 3+dst_offset_size;
 891     break;
 892   case Op_VecD:
 893     calc_size = 3+src_offset_size + 3+dst_offset_size;
 894     src_offset += 4;
 895     dst_offset += 4;
 896     src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
 897     dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
 898     calc_size += 3+src_offset_size + 3+dst_offset_size;
 899     break;
 900   case Op_VecX:
 901     calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
 902     break;
 903   case Op_VecY:
 904     calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
 905     break;
 906   default:
 907     ShouldNotReachHere();
 908   }
 909   if (cbuf) {
 910     MacroAssembler _masm(cbuf);
 911     int offset = __ offset();
 912     switch (ireg) {
 913     case Op_VecS:
 914       __ pushl(Address(rsp, src_offset));
 915       __ popl (Address(rsp, dst_offset));
 916       break;
 917     case Op_VecD:
 918       __ pushl(Address(rsp, src_offset));
 919       __ popl (Address(rsp, dst_offset));
 920       __ pushl(Address(rsp, src_offset+4));
 921       __ popl (Address(rsp, dst_offset+4));
 922       break;
 923     case Op_VecX:
 924       __ movdqu(Address(rsp, -16), xmm0);
 925       __ movdqu(xmm0, Address(rsp, src_offset));
 926       __ movdqu(Address(rsp, dst_offset), xmm0);
 927       __ movdqu(xmm0, Address(rsp, -16));
 928       break;
 929     case Op_VecY:
 930       __ vmovdqu(Address(rsp, -32), xmm0);
 931       __ vmovdqu(xmm0, Address(rsp, src_offset));
 932       __ vmovdqu(Address(rsp, dst_offset), xmm0);
 933       __ vmovdqu(xmm0, Address(rsp, -32));
 934       break;
 935     default:
 936       ShouldNotReachHere();
 937     }
 938     int size = __ offset() - offset;
 939     assert(size == calc_size, "incorrect size calculattion");
 940     return size;
 941 #ifndef PRODUCT
 942   } else if (!do_size) {
 943     switch (ireg) {
 944     case Op_VecS:
 945       st->print("pushl   [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
 946                 "popl    [rsp + #%d]",
 947                 src_offset, dst_offset);
 948       break;
 949     case Op_VecD:
 950       st->print("pushl   [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
 951                 "popq    [rsp + #%d]\n\t"
 952                 "pushl   [rsp + #%d]\n\t"
 953                 "popq    [rsp + #%d]",
 954                 src_offset, dst_offset, src_offset+4, dst_offset+4);
 955       break;
 956      case Op_VecX:
 957       st->print("movdqu  [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
 958                 "movdqu  xmm0, [rsp + #%d]\n\t"
 959                 "movdqu  [rsp + #%d], xmm0\n\t"
 960                 "movdqu  xmm0, [rsp - #16]",
 961                 src_offset, dst_offset);
 962       break;
 963     case Op_VecY:
 964       st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
 965                 "vmovdqu xmm0, [rsp + #%d]\n\t"
 966                 "vmovdqu [rsp + #%d], xmm0\n\t"
 967                 "vmovdqu xmm0, [rsp - #32]",
 968                 src_offset, dst_offset);
 969       break;
 970     default:
 971       ShouldNotReachHere();
 972     }
 973 #endif
 974   }
 975   return calc_size;
 976 }
 977 
 978 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
 979   // Get registers to move
 980   OptoReg::Name src_second = ra_->get_reg_second(in(1));
 981   OptoReg::Name src_first = ra_->get_reg_first(in(1));
 982   OptoReg::Name dst_second = ra_->get_reg_second(this );
 983   OptoReg::Name dst_first = ra_->get_reg_first(this );
 984 
 985   enum RC src_second_rc = rc_class(src_second);
 986   enum RC src_first_rc = rc_class(src_first);
 987   enum RC dst_second_rc = rc_class(dst_second);
 988   enum RC dst_first_rc = rc_class(dst_first);
 989 
 990   assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
 991 
 992   // Generate spill code!
 993   int size = 0;
 994 
 995   if( src_first == dst_first && src_second == dst_second )
 996     return size;            // Self copy, no move
 997 
 998   if (bottom_type()->isa_vect() != NULL) {
 999     uint ireg = ideal_reg();
1000     assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1001     assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1002     assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1003     if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1004       // mem -> mem
1005       int src_offset = ra_->reg2offset(src_first);
1006       int dst_offset = ra_->reg2offset(dst_first);
1007       return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1008     } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1009       return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1010     } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1011       int stack_offset = ra_->reg2offset(dst_first);
1012       return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1013     } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1014       int stack_offset = ra_->reg2offset(src_first);
1015       return vec_spill_helper(cbuf, do_size, true,  stack_offset, dst_first, ireg, st);
1016     } else {
1017       ShouldNotReachHere();
1018     }
1019   }
1020 
1021   // --------------------------------------
1022   // Check for mem-mem move.  push/pop to move.
1023   if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1024     if( src_second == dst_first ) { // overlapping stack copy ranges
1025       assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1026       size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH  ",size, st);
1027       size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP   ",size, st);
1028       src_second_rc = dst_second_rc = rc_bad;  // flag as already moved the second bits
1029     }
1030     // move low bits
1031     size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH  ",size, st);
1032     size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP   ",size, st);
1033     if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1034       size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH  ",size, st);
1035       size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP   ",size, st);
1036     }
1037     return size;
1038   }
1039 
1040   // --------------------------------------
1041   // Check for integer reg-reg copy
1042   if( src_first_rc == rc_int && dst_first_rc == rc_int )
1043     size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1044 
1045   // Check for integer store
1046   if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1047     size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1048 
1049   // Check for integer load
1050   if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1051     size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1052 
1053   // Check for integer reg-xmm reg copy
1054   if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1055     assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1056             "no 64 bit integer-float reg moves" );
1057     return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1058   }
1059   // --------------------------------------
1060   // Check for float reg-reg copy
1061   if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1062     assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1063             (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1064     if( cbuf ) {
1065 
1066       // Note the mucking with the register encode to compensate for the 0/1
1067       // indexing issue mentioned in a comment in the reg_def sections
1068       // for FPR registers many lines above here.
1069 
1070       if( src_first != FPR1L_num ) {
1071         emit_opcode  (*cbuf, 0xD9 );           // FLD    ST(i)
1072         emit_d8      (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1073         emit_opcode  (*cbuf, 0xDD );           // FSTP   ST(i)
1074         emit_d8      (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1075      } else {
1076         emit_opcode  (*cbuf, 0xDD );           // FST    ST(i)
1077         emit_d8      (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1078      }
1079 #ifndef PRODUCT
1080     } else if( !do_size ) {
1081       if( size != 0 ) st->print("\n\t");
1082       if( src_first != FPR1L_num ) st->print("FLD    %s\n\tFSTP   %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1083       else                      st->print(             "FST    %s",                            Matcher::regName[dst_first]);
1084 #endif
1085     }
1086     return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1087   }
1088 
1089   // Check for float store
1090   if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1091     return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1092   }
1093 
1094   // Check for float load
1095   if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1096     int offset = ra_->reg2offset(src_first);
1097     const char *op_str;
1098     int op;
1099     if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1100       op_str = "FLD_D";
1101       op = 0xDD;
1102     } else {                   // 32-bit load
1103       op_str = "FLD_S";
1104       op = 0xD9;
1105       assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1106     }
1107     if( cbuf ) {
1108       emit_opcode  (*cbuf, op );
1109       encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1110       emit_opcode  (*cbuf, 0xDD );           // FSTP   ST(i)
1111       emit_d8      (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1112 #ifndef PRODUCT
1113     } else if( !do_size ) {
1114       if( size != 0 ) st->print("\n\t");
1115       st->print("%s  ST,[ESP + #%d]\n\tFSTP   %s",op_str, offset,Matcher::regName[dst_first]);
1116 #endif
1117     }
1118     int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1119     return size + 3+offset_size+2;
1120   }
1121 
1122   // Check for xmm reg-reg copy
1123   if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1124     assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1125             (src_first+1 == src_second && dst_first+1 == dst_second),
1126             "no non-adjacent float-moves" );
1127     return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1128   }
1129 
1130   // Check for xmm reg-integer reg copy
1131   if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1132     assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1133             "no 64 bit float-integer reg moves" );
1134     return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1135   }
1136 
1137   // Check for xmm store
1138   if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1139     return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1140   }
1141 
1142   // Check for float xmm load
1143   if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1144     return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1145   }
1146 
1147   // Copy from float reg to xmm reg
1148   if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1149     // copy to the top of stack from floating point reg
1150     // and use LEA to preserve flags
1151     if( cbuf ) {
1152       emit_opcode(*cbuf,0x8D);  // LEA  ESP,[ESP-8]
1153       emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1154       emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1155       emit_d8(*cbuf,0xF8);
1156 #ifndef PRODUCT
1157     } else if( !do_size ) {
1158       if( size != 0 ) st->print("\n\t");
1159       st->print("LEA    ESP,[ESP-8]");
1160 #endif
1161     }
1162     size += 4;
1163 
1164     size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1165 
1166     // Copy from the temp memory to the xmm reg.
1167     size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1168 
1169     if( cbuf ) {
1170       emit_opcode(*cbuf,0x8D);  // LEA  ESP,[ESP+8]
1171       emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1172       emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1173       emit_d8(*cbuf,0x08);
1174 #ifndef PRODUCT
1175     } else if( !do_size ) {
1176       if( size != 0 ) st->print("\n\t");
1177       st->print("LEA    ESP,[ESP+8]");
1178 #endif
1179     }
1180     size += 4;
1181     return size;
1182   }
1183 
1184   assert( size > 0, "missed a case" );
1185 
1186   // --------------------------------------------------------------------
1187   // Check for second bits still needing moving.
1188   if( src_second == dst_second )
1189     return size;               // Self copy; no move
1190   assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1191 
1192   // Check for second word int-int move
1193   if( src_second_rc == rc_int && dst_second_rc == rc_int )
1194     return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1195 
1196   // Check for second word integer store
1197   if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1198     return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1199 
1200   // Check for second word integer load
1201   if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1202     return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1203 
1204 
1205   Unimplemented();
1206 }
1207 
1208 #ifndef PRODUCT
1209 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1210   implementation( NULL, ra_, false, st );
1211 }
1212 #endif
1213 
1214 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1215   implementation( &cbuf, ra_, false, NULL );
1216 }
1217 
1218 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1219   return implementation( NULL, ra_, true, NULL );
1220 }
1221 
1222 
1223 //=============================================================================
1224 #ifndef PRODUCT
1225 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1226   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1227   int reg = ra_->get_reg_first(this);
1228   st->print("LEA    %s,[ESP + #%d]",Matcher::regName[reg],offset);
1229 }
1230 #endif
1231 
1232 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1233   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1234   int reg = ra_->get_encode(this);
1235   if( offset >= 128 ) {
1236     emit_opcode(cbuf, 0x8D);      // LEA  reg,[SP+offset]
1237     emit_rm(cbuf, 0x2, reg, 0x04);
1238     emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1239     emit_d32(cbuf, offset);
1240   }
1241   else {
1242     emit_opcode(cbuf, 0x8D);      // LEA  reg,[SP+offset]
1243     emit_rm(cbuf, 0x1, reg, 0x04);
1244     emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1245     emit_d8(cbuf, offset);
1246   }
1247 }
1248 
1249 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1250   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1251   if( offset >= 128 ) {
1252     return 7;
1253   }
1254   else {
1255     return 4;
1256   }
1257 }
1258 
1259 //=============================================================================
1260 #ifndef PRODUCT
1261 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1262   st->print_cr(  "CMP    EAX,[ECX+4]\t# Inline cache check");
1263   st->print_cr("\tJNE    SharedRuntime::handle_ic_miss_stub");
1264   st->print_cr("\tNOP");
1265   st->print_cr("\tNOP");
1266   if( !OptoBreakpoint )
1267     st->print_cr("\tNOP");
1268 }
1269 #endif
1270 
1271 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1272   MacroAssembler masm(&cbuf);
1273 #ifdef ASSERT
1274   uint insts_size = cbuf.insts_size();
1275 #endif
1276   masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1277   masm.jump_cc(Assembler::notEqual,
1278                RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1279   /* WARNING these NOPs are critical so that verified entry point is properly
1280      aligned for patching by NativeJump::patch_verified_entry() */
1281   int nops_cnt = 2;
1282   if( !OptoBreakpoint ) // Leave space for int3
1283      nops_cnt += 1;
1284   masm.nop(nops_cnt);
1285 
1286   assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1287 }
1288 
1289 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1290   return OptoBreakpoint ? 11 : 12;
1291 }
1292 
1293 
1294 //=============================================================================
1295 uint size_exception_handler() {
1296   // NativeCall instruction size is the same as NativeJump.
1297   // exception handler starts out as jump and can be patched to
1298   // a call be deoptimization.  (4932387)
1299   // Note that this value is also credited (in output.cpp) to
1300   // the size of the code section.
1301   return NativeJump::instruction_size;
1302 }
1303 
1304 // Emit exception handler code.  Stuff framesize into a register
1305 // and call a VM stub routine.
1306 int emit_exception_handler(CodeBuffer& cbuf) {
1307 
1308   // Note that the code buffer's insts_mark is always relative to insts.
1309   // That's why we must use the macroassembler to generate a handler.
1310   MacroAssembler _masm(&cbuf);
1311   address base =
1312   __ start_a_stub(size_exception_handler());
1313   if (base == NULL)  return 0;  // CodeBuffer::expand failed
1314   int offset = __ offset();
1315   __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1316   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1317   __ end_a_stub();
1318   return offset;
1319 }
1320 
1321 uint size_deopt_handler() {
1322   // NativeCall instruction size is the same as NativeJump.
1323   // exception handler starts out as jump and can be patched to
1324   // a call be deoptimization.  (4932387)
1325   // Note that this value is also credited (in output.cpp) to
1326   // the size of the code section.
1327   return 5 + NativeJump::instruction_size; // pushl(); jmp;
1328 }
1329 
1330 // Emit deopt handler code.
1331 int emit_deopt_handler(CodeBuffer& cbuf) {
1332 
1333   // Note that the code buffer's insts_mark is always relative to insts.
1334   // That's why we must use the macroassembler to generate a handler.
1335   MacroAssembler _masm(&cbuf);
1336   address base =
1337   __ start_a_stub(size_exception_handler());
1338   if (base == NULL)  return 0;  // CodeBuffer::expand failed
1339   int offset = __ offset();
1340   InternalAddress here(__ pc());
1341   __ pushptr(here.addr());
1342 
1343   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1344   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1345   __ end_a_stub();
1346   return offset;
1347 }
1348 
1349 int Matcher::regnum_to_fpu_offset(int regnum) {
1350   return regnum - 32; // The FP registers are in the second chunk
1351 }
1352 
1353 // This is UltraSparc specific, true just means we have fast l2f conversion
1354 const bool Matcher::convL2FSupported(void) {
1355   return true;
1356 }
1357 
1358 // Is this branch offset short enough that a short branch can be used?
1359 //
1360 // NOTE: If the platform does not provide any short branch variants, then
1361 //       this method should return false for offset 0.
1362 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1363   // The passed offset is relative to address of the branch.
1364   // On 86 a branch displacement is calculated relative to address
1365   // of a next instruction.
1366   offset -= br_size;
1367 
1368   // the short version of jmpConUCF2 contains multiple branches,
1369   // making the reach slightly less
1370   if (rule == jmpConUCF2_rule)
1371     return (-126 <= offset && offset <= 125);
1372   return (-128 <= offset && offset <= 127);
1373 }
1374 
1375 const bool Matcher::isSimpleConstant64(jlong value) {
1376   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1377   return false;
1378 }
1379 
1380 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1381 const bool Matcher::init_array_count_is_in_bytes = false;
1382 
1383 // Threshold size for cleararray.
1384 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1385 
1386 // Needs 2 CMOV's for longs.
1387 const int Matcher::long_cmove_cost() { return 1; }
1388 
1389 // No CMOVF/CMOVD with SSE/SSE2
1390 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1391 
1392 // Should the Matcher clone shifts on addressing modes, expecting them to
1393 // be subsumed into complex addressing expressions or compute them into
1394 // registers?  True for Intel but false for most RISCs
1395 const bool Matcher::clone_shift_expressions = true;
1396 
1397 // Do we need to mask the count passed to shift instructions or does
1398 // the cpu only look at the lower 5/6 bits anyway?
1399 const bool Matcher::need_masked_shift_count = false;
1400 
1401 bool Matcher::narrow_oop_use_complex_address() {
1402   ShouldNotCallThis();
1403   return true;
1404 }
1405 
1406 bool Matcher::narrow_klass_use_complex_address() {
1407   ShouldNotCallThis();
1408   return true;
1409 }
1410 
1411 
1412 // Is it better to copy float constants, or load them directly from memory?
1413 // Intel can load a float constant from a direct address, requiring no
1414 // extra registers.  Most RISCs will have to materialize an address into a
1415 // register first, so they would do better to copy the constant from stack.
1416 const bool Matcher::rematerialize_float_constants = true;
1417 
1418 // If CPU can load and store mis-aligned doubles directly then no fixup is
1419 // needed.  Else we split the double into 2 integer pieces and move it
1420 // piece-by-piece.  Only happens when passing doubles into C code as the
1421 // Java calling convention forces doubles to be aligned.
1422 const bool Matcher::misaligned_doubles_ok = true;
1423 
1424 
1425 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1426   // Get the memory operand from the node
1427   uint numopnds = node->num_opnds();        // Virtual call for number of operands
1428   uint skipped  = node->oper_input_base();  // Sum of leaves skipped so far
1429   assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1430   uint opcnt     = 1;                 // First operand
1431   uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1432   while( idx >= skipped+num_edges ) {
1433     skipped += num_edges;
1434     opcnt++;                          // Bump operand count
1435     assert( opcnt < numopnds, "Accessing non-existent operand" );
1436     num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1437   }
1438 
1439   MachOper *memory = node->_opnds[opcnt];
1440   MachOper *new_memory = NULL;
1441   switch (memory->opcode()) {
1442   case DIRECT:
1443   case INDOFFSET32X:
1444     // No transformation necessary.
1445     return;
1446   case INDIRECT:
1447     new_memory = new (C) indirect_win95_safeOper( );
1448     break;
1449   case INDOFFSET8:
1450     new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1451     break;
1452   case INDOFFSET32:
1453     new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1454     break;
1455   case INDINDEXOFFSET:
1456     new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1457     break;
1458   case INDINDEXSCALE:
1459     new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1460     break;
1461   case INDINDEXSCALEOFFSET:
1462     new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1463     break;
1464   case LOAD_LONG_INDIRECT:
1465   case LOAD_LONG_INDOFFSET32:
1466     // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1467     return;
1468   default:
1469     assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1470     return;
1471   }
1472   node->_opnds[opcnt] = new_memory;
1473 }
1474 
1475 // Advertise here if the CPU requires explicit rounding operations
1476 // to implement the UseStrictFP mode.
1477 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1478 
1479 // Are floats conerted to double when stored to stack during deoptimization?
1480 // On x32 it is stored with convertion only when FPU is used for floats.
1481 bool Matcher::float_in_double() { return (UseSSE == 0); }
1482 
1483 // Do ints take an entire long register or just half?
1484 const bool Matcher::int_in_long = false;
1485 
1486 // Return whether or not this register is ever used as an argument.  This
1487 // function is used on startup to build the trampoline stubs in generateOptoStub.
1488 // Registers not mentioned will be killed by the VM call in the trampoline, and
1489 // arguments in those registers not be available to the callee.
1490 bool Matcher::can_be_java_arg( int reg ) {
1491   if(  reg == ECX_num   || reg == EDX_num   ) return true;
1492   if( (reg == XMM0_num  || reg == XMM1_num ) && UseSSE>=1 ) return true;
1493   if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1494   return false;
1495 }
1496 
1497 bool Matcher::is_spillable_arg( int reg ) {
1498   return can_be_java_arg(reg);
1499 }
1500 
1501 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1502   // Use hardware integer DIV instruction when
1503   // it is faster than a code which use multiply.
1504   // Only when constant divisor fits into 32 bit
1505   // (min_jint is excluded to get only correct
1506   // positive 32 bit values from negative).
1507   return VM_Version::has_fast_idiv() &&
1508          (divisor == (int)divisor && divisor != min_jint);
1509 }
1510 
1511 // Register for DIVI projection of divmodI
1512 RegMask Matcher::divI_proj_mask() {
1513   return EAX_REG_mask();
1514 }
1515 
1516 // Register for MODI projection of divmodI
1517 RegMask Matcher::modI_proj_mask() {
1518   return EDX_REG_mask();
1519 }
1520 
1521 // Register for DIVL projection of divmodL
1522 RegMask Matcher::divL_proj_mask() {
1523   ShouldNotReachHere();
1524   return RegMask();
1525 }
1526 
1527 // Register for MODL projection of divmodL
1528 RegMask Matcher::modL_proj_mask() {
1529   ShouldNotReachHere();
1530   return RegMask();
1531 }
1532 
1533 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1534   return EBP_REG_mask();
1535 }
1536 
1537 // Returns true if the high 32 bits of the value is known to be zero.
1538 bool is_operand_hi32_zero(Node* n) {
1539   int opc = n->Opcode();
1540   if (opc == Op_AndL) {
1541     Node* o2 = n->in(2);
1542     if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1543       return true;
1544     }
1545   }
1546   if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1547     return true;
1548   }
1549   return false;
1550 }
1551 
1552 %}
1553 
1554 //----------ENCODING BLOCK-----------------------------------------------------
1555 // This block specifies the encoding classes used by the compiler to output
1556 // byte streams.  Encoding classes generate functions which are called by
1557 // Machine Instruction Nodes in order to generate the bit encoding of the
1558 // instruction.  Operands specify their base encoding interface with the
1559 // interface keyword.  There are currently supported four interfaces,
1560 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an
1561 // operand to generate a function which returns its register number when
1562 // queried.   CONST_INTER causes an operand to generate a function which
1563 // returns the value of the constant when queried.  MEMORY_INTER causes an
1564 // operand to generate four functions which return the Base Register, the
1565 // Index Register, the Scale Value, and the Offset Value of the operand when
1566 // queried.  COND_INTER causes an operand to generate six functions which
1567 // return the encoding code (ie - encoding bits for the instruction)
1568 // associated with each basic boolean condition for a conditional instruction.
1569 // Instructions specify two basic values for encoding.  They use the
1570 // ins_encode keyword to specify their encoding class (which must be one of
1571 // the class names specified in the encoding block), and they use the
1572 // opcode keyword to specify, in order, their primary, secondary, and
1573 // tertiary opcode.  Only the opcode sections which a particular instruction
1574 // needs for encoding need to be specified.
1575 encode %{
1576   // Build emit functions for each basic byte or larger field in the intel
1577   // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1578   // code in the enc_class source block.  Emit functions will live in the
1579   // main source block for now.  In future, we can generalize this by
1580   // adding a syntax that specifies the sizes of fields in an order,
1581   // so that the adlc can build the emit functions automagically
1582 
1583   // Emit primary opcode
1584   enc_class OpcP %{
1585     emit_opcode(cbuf, $primary);
1586   %}
1587 
1588   // Emit secondary opcode
1589   enc_class OpcS %{
1590     emit_opcode(cbuf, $secondary);
1591   %}
1592 
1593   // Emit opcode directly
1594   enc_class Opcode(immI d8) %{
1595     emit_opcode(cbuf, $d8$$constant);
1596   %}
1597 
1598   enc_class SizePrefix %{
1599     emit_opcode(cbuf,0x66);
1600   %}
1601 
1602   enc_class RegReg (rRegI dst, rRegI src) %{    // RegReg(Many)
1603     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1604   %}
1605 
1606   enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{    // OpcRegReg(Many)
1607     emit_opcode(cbuf,$opcode$$constant);
1608     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1609   %}
1610 
1611   enc_class mov_r32_imm0( rRegI dst ) %{
1612     emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd   -- MOV r32  ,imm32
1613     emit_d32   ( cbuf, 0x0  );             //                         imm32==0x0
1614   %}
1615 
1616   enc_class cdq_enc %{
1617     // Full implementation of Java idiv and irem; checks for
1618     // special case as described in JVM spec., p.243 & p.271.
1619     //
1620     //         normal case                           special case
1621     //
1622     // input : rax,: dividend                         min_int
1623     //         reg: divisor                          -1
1624     //
1625     // output: rax,: quotient  (= rax, idiv reg)       min_int
1626     //         rdx: remainder (= rax, irem reg)       0
1627     //
1628     //  Code sequnce:
1629     //
1630     //  81 F8 00 00 00 80    cmp         rax,80000000h
1631     //  0F 85 0B 00 00 00    jne         normal_case
1632     //  33 D2                xor         rdx,edx
1633     //  83 F9 FF             cmp         rcx,0FFh
1634     //  0F 84 03 00 00 00    je          done
1635     //                  normal_case:
1636     //  99                   cdq
1637     //  F7 F9                idiv        rax,ecx
1638     //                  done:
1639     //
1640     emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1641     emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1642     emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80);                     // cmp rax,80000000h
1643     emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1644     emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1645     emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);                     // jne normal_case
1646     emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2);                     // xor rdx,edx
1647     emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1648     emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1649     emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1650     emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);                     // je done
1651     // normal_case:
1652     emit_opcode(cbuf,0x99);                                         // cdq
1653     // idiv (note: must be emitted by the user of this rule)
1654     // normal:
1655   %}
1656 
1657   // Dense encoding for older common ops
1658   enc_class Opc_plus(immI opcode, rRegI reg) %{
1659     emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1660   %}
1661 
1662 
1663   // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1664   enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1665     // Check for 8-bit immediate, and set sign extend bit in opcode
1666     if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1667       emit_opcode(cbuf, $primary | 0x02);
1668     }
1669     else {                          // If 32-bit immediate
1670       emit_opcode(cbuf, $primary);
1671     }
1672   %}
1673 
1674   enc_class OpcSErm (rRegI dst, immI imm) %{    // OpcSEr/m
1675     // Emit primary opcode and set sign-extend bit
1676     // Check for 8-bit immediate, and set sign extend bit in opcode
1677     if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1678       emit_opcode(cbuf, $primary | 0x02);    }
1679     else {                          // If 32-bit immediate
1680       emit_opcode(cbuf, $primary);
1681     }
1682     // Emit r/m byte with secondary opcode, after primary opcode.
1683     emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1684   %}
1685 
1686   enc_class Con8or32 (immI imm) %{    // Con8or32(storeImmI), 8 or 32 bits
1687     // Check for 8-bit immediate, and set sign extend bit in opcode
1688     if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1689       $$$emit8$imm$$constant;
1690     }
1691     else {                          // If 32-bit immediate
1692       // Output immediate
1693       $$$emit32$imm$$constant;
1694     }
1695   %}
1696 
1697   enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1698     // Emit primary opcode and set sign-extend bit
1699     // Check for 8-bit immediate, and set sign extend bit in opcode
1700     int con = (int)$imm$$constant; // Throw away top bits
1701     emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1702     // Emit r/m byte with secondary opcode, after primary opcode.
1703     emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1704     if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1705     else                               emit_d32(cbuf,con);
1706   %}
1707 
1708   enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1709     // Emit primary opcode and set sign-extend bit
1710     // Check for 8-bit immediate, and set sign extend bit in opcode
1711     int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1712     emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1713     // Emit r/m byte with tertiary opcode, after primary opcode.
1714     emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1715     if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1716     else                               emit_d32(cbuf,con);
1717   %}
1718 
1719   enc_class OpcSReg (rRegI dst) %{    // BSWAP
1720     emit_cc(cbuf, $secondary, $dst$$reg );
1721   %}
1722 
1723   enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1724     int destlo = $dst$$reg;
1725     int desthi = HIGH_FROM_LOW(destlo);
1726     // bswap lo
1727     emit_opcode(cbuf, 0x0F);
1728     emit_cc(cbuf, 0xC8, destlo);
1729     // bswap hi
1730     emit_opcode(cbuf, 0x0F);
1731     emit_cc(cbuf, 0xC8, desthi);
1732     // xchg lo and hi
1733     emit_opcode(cbuf, 0x87);
1734     emit_rm(cbuf, 0x3, destlo, desthi);
1735   %}
1736 
1737   enc_class RegOpc (rRegI div) %{    // IDIV, IMOD, JMP indirect, ...
1738     emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1739   %}
1740 
1741   enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1742     $$$emit8$primary;
1743     emit_cc(cbuf, $secondary, $cop$$cmpcode);
1744   %}
1745 
1746   enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1747     int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1748     emit_d8(cbuf, op >> 8 );
1749     emit_d8(cbuf, op & 255);
1750   %}
1751 
1752   // emulate a CMOV with a conditional branch around a MOV
1753   enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1754     // Invert sense of branch from sense of CMOV
1755     emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1756     emit_d8( cbuf, $brOffs$$constant );
1757   %}
1758 
1759   enc_class enc_PartialSubtypeCheck( ) %{
1760     Register Redi = as_Register(EDI_enc); // result register
1761     Register Reax = as_Register(EAX_enc); // super class
1762     Register Recx = as_Register(ECX_enc); // killed
1763     Register Resi = as_Register(ESI_enc); // sub class
1764     Label miss;
1765 
1766     MacroAssembler _masm(&cbuf);
1767     __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1768                                      NULL, &miss,
1769                                      /*set_cond_codes:*/ true);
1770     if ($primary) {
1771       __ xorptr(Redi, Redi);
1772     }
1773     __ bind(miss);
1774   %}
1775 
1776   enc_class FFree_Float_Stack_All %{    // Free_Float_Stack_All
1777     MacroAssembler masm(&cbuf);
1778     int start = masm.offset();
1779     if (UseSSE >= 2) {
1780       if (VerifyFPU) {
1781         masm.verify_FPU(0, "must be empty in SSE2+ mode");
1782       }
1783     } else {
1784       // External c_calling_convention expects the FPU stack to be 'clean'.
1785       // Compiled code leaves it dirty.  Do cleanup now.
1786       masm.empty_FPU_stack();
1787     }
1788     if (sizeof_FFree_Float_Stack_All == -1) {
1789       sizeof_FFree_Float_Stack_All = masm.offset() - start;
1790     } else {
1791       assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1792     }
1793   %}
1794 
1795   enc_class Verify_FPU_For_Leaf %{
1796     if( VerifyFPU ) {
1797       MacroAssembler masm(&cbuf);
1798       masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1799     }
1800   %}
1801 
1802   enc_class Java_To_Runtime (method meth) %{    // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1803     // This is the instruction starting address for relocation info.
1804     cbuf.set_insts_mark();
1805     $$$emit8$primary;
1806     // CALL directly to the runtime
1807     emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1808                 runtime_call_Relocation::spec(), RELOC_IMM32 );
1809 
1810     if (UseSSE >= 2) {
1811       MacroAssembler _masm(&cbuf);
1812       BasicType rt = tf()->return_type();
1813 
1814       if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1815         // A C runtime call where the return value is unused.  In SSE2+
1816         // mode the result needs to be removed from the FPU stack.  It's
1817         // likely that this function call could be removed by the
1818         // optimizer if the C function is a pure function.
1819         __ ffree(0);
1820       } else if (rt == T_FLOAT) {
1821         __ lea(rsp, Address(rsp, -4));
1822         __ fstp_s(Address(rsp, 0));
1823         __ movflt(xmm0, Address(rsp, 0));
1824         __ lea(rsp, Address(rsp,  4));
1825       } else if (rt == T_DOUBLE) {
1826         __ lea(rsp, Address(rsp, -8));
1827         __ fstp_d(Address(rsp, 0));
1828         __ movdbl(xmm0, Address(rsp, 0));
1829         __ lea(rsp, Address(rsp,  8));
1830       }
1831     }
1832   %}
1833 
1834 
1835   enc_class pre_call_resets %{
1836     // If method sets FPU control word restore it here
1837     debug_only(int off0 = cbuf.insts_size());
1838     if (ra_->C->in_24_bit_fp_mode()) {
1839       MacroAssembler _masm(&cbuf);
1840       __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1841     }
1842     if (ra_->C->max_vector_size() > 16) {
1843       // Clear upper bits of YMM registers when current compiled code uses
1844       // wide vectors to avoid AVX <-> SSE transition penalty during call.
1845       MacroAssembler _masm(&cbuf);
1846       __ vzeroupper();
1847     }
1848     debug_only(int off1 = cbuf.insts_size());
1849     assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1850   %}
1851 
1852   enc_class post_call_FPU %{
1853     // If method sets FPU control word do it here also
1854     if (Compile::current()->in_24_bit_fp_mode()) {
1855       MacroAssembler masm(&cbuf);
1856       masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1857     }
1858   %}
1859 
1860   enc_class Java_Static_Call (method meth) %{    // JAVA STATIC CALL
1861     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
1862     // who we intended to call.
1863     cbuf.set_insts_mark();
1864     $$$emit8$primary;
1865     if (!_method) {
1866       emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1867                      runtime_call_Relocation::spec(), RELOC_IMM32 );
1868     } else if (_optimized_virtual) {
1869       emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1870                      opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1871     } else {
1872       emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1873                      static_call_Relocation::spec(), RELOC_IMM32 );
1874     }
1875     if (_method) {  // Emit stub for static call.
1876       CompiledStaticCall::emit_to_interp_stub(cbuf);
1877     }
1878   %}
1879 
1880   enc_class Java_Dynamic_Call (method meth) %{    // JAVA DYNAMIC CALL
1881     MacroAssembler _masm(&cbuf);
1882     __ ic_call((address)$meth$$method);
1883   %}
1884 
1885   enc_class Java_Compiled_Call (method meth) %{    // JAVA COMPILED CALL
1886     int disp = in_bytes(Method::from_compiled_offset());
1887     assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1888 
1889     // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1890     cbuf.set_insts_mark();
1891     $$$emit8$primary;
1892     emit_rm(cbuf, 0x01, $secondary, EAX_enc );  // R/M byte
1893     emit_d8(cbuf, disp);             // Displacement
1894 
1895   %}
1896 
1897 //   Following encoding is no longer used, but may be restored if calling
1898 //   convention changes significantly.
1899 //   Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1900 //
1901 //   enc_class Java_Interpreter_Call (label labl) %{    // JAVA INTERPRETER CALL
1902 //     // int ic_reg     = Matcher::inline_cache_reg();
1903 //     // int ic_encode  = Matcher::_regEncode[ic_reg];
1904 //     // int imo_reg    = Matcher::interpreter_method_oop_reg();
1905 //     // int imo_encode = Matcher::_regEncode[imo_reg];
1906 //
1907 //     // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1908 //     // // so we load it immediately before the call
1909 //     // emit_opcode(cbuf, 0x8B);                     // MOV    imo_reg,ic_reg  # method_oop
1910 //     // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1911 //
1912 //     // xor rbp,ebp
1913 //     emit_opcode(cbuf, 0x33);
1914 //     emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1915 //
1916 //     // CALL to interpreter.
1917 //     cbuf.set_insts_mark();
1918 //     $$$emit8$primary;
1919 //     emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1920 //                 runtime_call_Relocation::spec(), RELOC_IMM32 );
1921 //   %}
1922 
1923   enc_class RegOpcImm (rRegI dst, immI8 shift) %{    // SHL, SAR, SHR
1924     $$$emit8$primary;
1925     emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1926     $$$emit8$shift$$constant;
1927   %}
1928 
1929   enc_class LdImmI (rRegI dst, immI src) %{    // Load Immediate
1930     // Load immediate does not have a zero or sign extended version
1931     // for 8-bit immediates
1932     emit_opcode(cbuf, 0xB8 + $dst$$reg);
1933     $$$emit32$src$$constant;
1934   %}
1935 
1936   enc_class LdImmP (rRegI dst, immI src) %{    // Load Immediate
1937     // Load immediate does not have a zero or sign extended version
1938     // for 8-bit immediates
1939     emit_opcode(cbuf, $primary + $dst$$reg);
1940     $$$emit32$src$$constant;
1941   %}
1942 
1943   enc_class LdImmL_Lo( eRegL dst, immL src) %{    // Load Immediate
1944     // Load immediate does not have a zero or sign extended version
1945     // for 8-bit immediates
1946     int dst_enc = $dst$$reg;
1947     int src_con = $src$$constant & 0x0FFFFFFFFL;
1948     if (src_con == 0) {
1949       // xor dst, dst
1950       emit_opcode(cbuf, 0x33);
1951       emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1952     } else {
1953       emit_opcode(cbuf, $primary + dst_enc);
1954       emit_d32(cbuf, src_con);
1955     }
1956   %}
1957 
1958   enc_class LdImmL_Hi( eRegL dst, immL src) %{    // Load Immediate
1959     // Load immediate does not have a zero or sign extended version
1960     // for 8-bit immediates
1961     int dst_enc = $dst$$reg + 2;
1962     int src_con = ((julong)($src$$constant)) >> 32;
1963     if (src_con == 0) {
1964       // xor dst, dst
1965       emit_opcode(cbuf, 0x33);
1966       emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1967     } else {
1968       emit_opcode(cbuf, $primary + dst_enc);
1969       emit_d32(cbuf, src_con);
1970     }
1971   %}
1972 
1973 
1974   // Encode a reg-reg copy.  If it is useless, then empty encoding.
1975   enc_class enc_Copy( rRegI dst, rRegI src ) %{
1976     encode_Copy( cbuf, $dst$$reg, $src$$reg );
1977   %}
1978 
1979   enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
1980     encode_Copy( cbuf, $dst$$reg, $src$$reg );
1981   %}
1982 
1983   enc_class RegReg (rRegI dst, rRegI src) %{    // RegReg(Many)
1984     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1985   %}
1986 
1987   enc_class RegReg_Lo(eRegL dst, eRegL src) %{    // RegReg(Many)
1988     $$$emit8$primary;
1989     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1990   %}
1991 
1992   enc_class RegReg_Hi(eRegL dst, eRegL src) %{    // RegReg(Many)
1993     $$$emit8$secondary;
1994     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
1995   %}
1996 
1997   enc_class RegReg_Lo2(eRegL dst, eRegL src) %{    // RegReg(Many)
1998     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1999   %}
2000 
2001   enc_class RegReg_Hi2(eRegL dst, eRegL src) %{    // RegReg(Many)
2002     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2003   %}
2004 
2005   enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2006     emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2007   %}
2008 
2009   enc_class Con32 (immI src) %{    // Con32(storeImmI)
2010     // Output immediate
2011     $$$emit32$src$$constant;
2012   %}
2013 
2014   enc_class Con32FPR_as_bits(immFPR src) %{        // storeF_imm
2015     // Output Float immediate bits
2016     jfloat jf = $src$$constant;
2017     int    jf_as_bits = jint_cast( jf );
2018     emit_d32(cbuf, jf_as_bits);
2019   %}
2020 
2021   enc_class Con32F_as_bits(immF src) %{      // storeX_imm
2022     // Output Float immediate bits
2023     jfloat jf = $src$$constant;
2024     int    jf_as_bits = jint_cast( jf );
2025     emit_d32(cbuf, jf_as_bits);
2026   %}
2027 
2028   enc_class Con16 (immI src) %{    // Con16(storeImmI)
2029     // Output immediate
2030     $$$emit16$src$$constant;
2031   %}
2032 
2033   enc_class Con_d32(immI src) %{
2034     emit_d32(cbuf,$src$$constant);
2035   %}
2036 
2037   enc_class conmemref (eRegP t1) %{    // Con32(storeImmI)
2038     // Output immediate memory reference
2039     emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2040     emit_d32(cbuf, 0x00);
2041   %}
2042 
2043   enc_class lock_prefix( ) %{
2044     if( os::is_MP() )
2045       emit_opcode(cbuf,0xF0);         // [Lock]
2046   %}
2047 
2048   // Cmp-xchg long value.
2049   // Note: we need to swap rbx, and rcx before and after the
2050   //       cmpxchg8 instruction because the instruction uses
2051   //       rcx as the high order word of the new value to store but
2052   //       our register encoding uses rbx,.
2053   enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2054 
2055     // XCHG  rbx,ecx
2056     emit_opcode(cbuf,0x87);
2057     emit_opcode(cbuf,0xD9);
2058     // [Lock]
2059     if( os::is_MP() )
2060       emit_opcode(cbuf,0xF0);
2061     // CMPXCHG8 [Eptr]
2062     emit_opcode(cbuf,0x0F);
2063     emit_opcode(cbuf,0xC7);
2064     emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2065     // XCHG  rbx,ecx
2066     emit_opcode(cbuf,0x87);
2067     emit_opcode(cbuf,0xD9);
2068   %}
2069 
2070   enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2071     // [Lock]
2072     if( os::is_MP() )
2073       emit_opcode(cbuf,0xF0);
2074 
2075     // CMPXCHG [Eptr]
2076     emit_opcode(cbuf,0x0F);
2077     emit_opcode(cbuf,0xB1);
2078     emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2079   %}
2080 
2081   enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2082     int res_encoding = $res$$reg;
2083 
2084     // MOV  res,0
2085     emit_opcode( cbuf, 0xB8 + res_encoding);
2086     emit_d32( cbuf, 0 );
2087     // JNE,s  fail
2088     emit_opcode(cbuf,0x75);
2089     emit_d8(cbuf, 5 );
2090     // MOV  res,1
2091     emit_opcode( cbuf, 0xB8 + res_encoding);
2092     emit_d32( cbuf, 1 );
2093     // fail:
2094   %}
2095 
2096   enc_class set_instruction_start( ) %{
2097     cbuf.set_insts_mark();            // Mark start of opcode for reloc info in mem operand
2098   %}
2099 
2100   enc_class RegMem (rRegI ereg, memory mem) %{    // emit_reg_mem
2101     int reg_encoding = $ereg$$reg;
2102     int base  = $mem$$base;
2103     int index = $mem$$index;
2104     int scale = $mem$$scale;
2105     int displace = $mem$$disp;
2106     relocInfo::relocType disp_reloc = $mem->disp_reloc();
2107     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2108   %}
2109 
2110   enc_class RegMem_Hi(eRegL ereg, memory mem) %{    // emit_reg_mem
2111     int reg_encoding = HIGH_FROM_LOW($ereg$$reg);  // Hi register of pair, computed from lo
2112     int base  = $mem$$base;
2113     int index = $mem$$index;
2114     int scale = $mem$$scale;
2115     int displace = $mem$$disp + 4;      // Offset is 4 further in memory
2116     assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2117     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2118   %}
2119 
2120   enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2121     int r1, r2;
2122     if( $tertiary == 0xA4 ) { r1 = $dst$$reg;  r2 = HIGH_FROM_LOW($dst$$reg); }
2123     else                    { r2 = $dst$$reg;  r1 = HIGH_FROM_LOW($dst$$reg); }
2124     emit_opcode(cbuf,0x0F);
2125     emit_opcode(cbuf,$tertiary);
2126     emit_rm(cbuf, 0x3, r1, r2);
2127     emit_d8(cbuf,$cnt$$constant);
2128     emit_d8(cbuf,$primary);
2129     emit_rm(cbuf, 0x3, $secondary, r1);
2130     emit_d8(cbuf,$cnt$$constant);
2131   %}
2132 
2133   enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2134     emit_opcode( cbuf, 0x8B ); // Move
2135     emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2136     if( $cnt$$constant > 32 ) { // Shift, if not by zero
2137       emit_d8(cbuf,$primary);
2138       emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2139       emit_d8(cbuf,$cnt$$constant-32);
2140     }
2141     emit_d8(cbuf,$primary);
2142     emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2143     emit_d8(cbuf,31);
2144   %}
2145 
2146   enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2147     int r1, r2;
2148     if( $secondary == 0x5 ) { r1 = $dst$$reg;  r2 = HIGH_FROM_LOW($dst$$reg); }
2149     else                    { r2 = $dst$$reg;  r1 = HIGH_FROM_LOW($dst$$reg); }
2150 
2151     emit_opcode( cbuf, 0x8B ); // Move r1,r2
2152     emit_rm(cbuf, 0x3, r1, r2);
2153     if( $cnt$$constant > 32 ) { // Shift, if not by zero
2154       emit_opcode(cbuf,$primary);
2155       emit_rm(cbuf, 0x3, $secondary, r1);
2156       emit_d8(cbuf,$cnt$$constant-32);
2157     }
2158     emit_opcode(cbuf,0x33);  // XOR r2,r2
2159     emit_rm(cbuf, 0x3, r2, r2);
2160   %}
2161 
2162   // Clone of RegMem but accepts an extra parameter to access each
2163   // half of a double in memory; it never needs relocation info.
2164   enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2165     emit_opcode(cbuf,$opcode$$constant);
2166     int reg_encoding = $rm_reg$$reg;
2167     int base     = $mem$$base;
2168     int index    = $mem$$index;
2169     int scale    = $mem$$scale;
2170     int displace = $mem$$disp + $disp_for_half$$constant;
2171     relocInfo::relocType disp_reloc = relocInfo::none;
2172     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2173   %}
2174 
2175   // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2176   //
2177   // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2178   // and it never needs relocation information.
2179   // Frequently used to move data between FPU's Stack Top and memory.
2180   enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2181     int rm_byte_opcode = $rm_opcode$$constant;
2182     int base     = $mem$$base;
2183     int index    = $mem$$index;
2184     int scale    = $mem$$scale;
2185     int displace = $mem$$disp;
2186     assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2187     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2188   %}
2189 
2190   enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2191     int rm_byte_opcode = $rm_opcode$$constant;
2192     int base     = $mem$$base;
2193     int index    = $mem$$index;
2194     int scale    = $mem$$scale;
2195     int displace = $mem$$disp;
2196     relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2197     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2198   %}
2199 
2200   enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{    // emit_reg_lea
2201     int reg_encoding = $dst$$reg;
2202     int base         = $src0$$reg;      // 0xFFFFFFFF indicates no base
2203     int index        = 0x04;            // 0x04 indicates no index
2204     int scale        = 0x00;            // 0x00 indicates no scale
2205     int displace     = $src1$$constant; // 0x00 indicates no displacement
2206     relocInfo::relocType disp_reloc = relocInfo::none;
2207     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2208   %}
2209 
2210   enc_class min_enc (rRegI dst, rRegI src) %{    // MIN
2211     // Compare dst,src
2212     emit_opcode(cbuf,0x3B);
2213     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2214     // jmp dst < src around move
2215     emit_opcode(cbuf,0x7C);
2216     emit_d8(cbuf,2);
2217     // move dst,src
2218     emit_opcode(cbuf,0x8B);
2219     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2220   %}
2221 
2222   enc_class max_enc (rRegI dst, rRegI src) %{    // MAX
2223     // Compare dst,src
2224     emit_opcode(cbuf,0x3B);
2225     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2226     // jmp dst > src around move
2227     emit_opcode(cbuf,0x7F);
2228     emit_d8(cbuf,2);
2229     // move dst,src
2230     emit_opcode(cbuf,0x8B);
2231     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2232   %}
2233 
2234   enc_class enc_FPR_store(memory mem, regDPR src) %{
2235     // If src is FPR1, we can just FST to store it.
2236     // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2237     int reg_encoding = 0x2; // Just store
2238     int base  = $mem$$base;
2239     int index = $mem$$index;
2240     int scale = $mem$$scale;
2241     int displace = $mem$$disp;
2242     relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2243     if( $src$$reg != FPR1L_enc ) {
2244       reg_encoding = 0x3;  // Store & pop
2245       emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2246       emit_d8( cbuf, 0xC0-1+$src$$reg );
2247     }
2248     cbuf.set_insts_mark();       // Mark start of opcode for reloc info in mem operand
2249     emit_opcode(cbuf,$primary);
2250     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2251   %}
2252 
2253   enc_class neg_reg(rRegI dst) %{
2254     // NEG $dst
2255     emit_opcode(cbuf,0xF7);
2256     emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2257   %}
2258 
2259   enc_class setLT_reg(eCXRegI dst) %{
2260     // SETLT $dst
2261     emit_opcode(cbuf,0x0F);
2262     emit_opcode(cbuf,0x9C);
2263     emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2264   %}
2265 
2266   enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{    // cadd_cmpLT
2267     int tmpReg = $tmp$$reg;
2268 
2269     // SUB $p,$q
2270     emit_opcode(cbuf,0x2B);
2271     emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2272     // SBB $tmp,$tmp
2273     emit_opcode(cbuf,0x1B);
2274     emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2275     // AND $tmp,$y
2276     emit_opcode(cbuf,0x23);
2277     emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2278     // ADD $p,$tmp
2279     emit_opcode(cbuf,0x03);
2280     emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2281   %}
2282 
2283   enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2284     // TEST shift,32
2285     emit_opcode(cbuf,0xF7);
2286     emit_rm(cbuf, 0x3, 0, ECX_enc);
2287     emit_d32(cbuf,0x20);
2288     // JEQ,s small
2289     emit_opcode(cbuf, 0x74);
2290     emit_d8(cbuf, 0x04);
2291     // MOV    $dst.hi,$dst.lo
2292     emit_opcode( cbuf, 0x8B );
2293     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2294     // CLR    $dst.lo
2295     emit_opcode(cbuf, 0x33);
2296     emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2297 // small:
2298     // SHLD   $dst.hi,$dst.lo,$shift
2299     emit_opcode(cbuf,0x0F);
2300     emit_opcode(cbuf,0xA5);
2301     emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2302     // SHL    $dst.lo,$shift"
2303     emit_opcode(cbuf,0xD3);
2304     emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2305   %}
2306 
2307   enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2308     // TEST shift,32
2309     emit_opcode(cbuf,0xF7);
2310     emit_rm(cbuf, 0x3, 0, ECX_enc);
2311     emit_d32(cbuf,0x20);
2312     // JEQ,s small
2313     emit_opcode(cbuf, 0x74);
2314     emit_d8(cbuf, 0x04);
2315     // MOV    $dst.lo,$dst.hi
2316     emit_opcode( cbuf, 0x8B );
2317     emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2318     // CLR    $dst.hi
2319     emit_opcode(cbuf, 0x33);
2320     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2321 // small:
2322     // SHRD   $dst.lo,$dst.hi,$shift
2323     emit_opcode(cbuf,0x0F);
2324     emit_opcode(cbuf,0xAD);
2325     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2326     // SHR    $dst.hi,$shift"
2327     emit_opcode(cbuf,0xD3);
2328     emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2329   %}
2330 
2331   enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2332     // TEST shift,32
2333     emit_opcode(cbuf,0xF7);
2334     emit_rm(cbuf, 0x3, 0, ECX_enc);
2335     emit_d32(cbuf,0x20);
2336     // JEQ,s small
2337     emit_opcode(cbuf, 0x74);
2338     emit_d8(cbuf, 0x05);
2339     // MOV    $dst.lo,$dst.hi
2340     emit_opcode( cbuf, 0x8B );
2341     emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2342     // SAR    $dst.hi,31
2343     emit_opcode(cbuf, 0xC1);
2344     emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2345     emit_d8(cbuf, 0x1F );
2346 // small:
2347     // SHRD   $dst.lo,$dst.hi,$shift
2348     emit_opcode(cbuf,0x0F);
2349     emit_opcode(cbuf,0xAD);
2350     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2351     // SAR    $dst.hi,$shift"
2352     emit_opcode(cbuf,0xD3);
2353     emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2354   %}
2355 
2356 
2357   // ----------------- Encodings for floating point unit -----------------
2358   // May leave result in FPU-TOS or FPU reg depending on opcodes
2359   enc_class OpcReg_FPR(regFPR src) %{    // FMUL, FDIV
2360     $$$emit8$primary;
2361     emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2362   %}
2363 
2364   // Pop argument in FPR0 with FSTP ST(0)
2365   enc_class PopFPU() %{
2366     emit_opcode( cbuf, 0xDD );
2367     emit_d8( cbuf, 0xD8 );
2368   %}
2369 
2370   // !!!!! equivalent to Pop_Reg_F
2371   enc_class Pop_Reg_DPR( regDPR dst ) %{
2372     emit_opcode( cbuf, 0xDD );           // FSTP   ST(i)
2373     emit_d8( cbuf, 0xD8+$dst$$reg );
2374   %}
2375 
2376   enc_class Push_Reg_DPR( regDPR dst ) %{
2377     emit_opcode( cbuf, 0xD9 );
2378     emit_d8( cbuf, 0xC0-1+$dst$$reg );   // FLD ST(i-1)
2379   %}
2380 
2381   enc_class strictfp_bias1( regDPR dst ) %{
2382     emit_opcode( cbuf, 0xDB );           // FLD m80real
2383     emit_opcode( cbuf, 0x2D );
2384     emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2385     emit_opcode( cbuf, 0xDE );           // FMULP ST(dst), ST0
2386     emit_opcode( cbuf, 0xC8+$dst$$reg );
2387   %}
2388 
2389   enc_class strictfp_bias2( regDPR dst ) %{
2390     emit_opcode( cbuf, 0xDB );           // FLD m80real
2391     emit_opcode( cbuf, 0x2D );
2392     emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2393     emit_opcode( cbuf, 0xDE );           // FMULP ST(dst), ST0
2394     emit_opcode( cbuf, 0xC8+$dst$$reg );
2395   %}
2396 
2397   // Special case for moving an integer register to a stack slot.
2398   enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2399     store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2400   %}
2401 
2402   // Special case for moving a register to a stack slot.
2403   enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2404     // Opcode already emitted
2405     emit_rm( cbuf, 0x02, $src$$reg, ESP_enc );   // R/M byte
2406     emit_rm( cbuf, 0x00, ESP_enc, ESP_enc);          // SIB byte
2407     emit_d32(cbuf, $dst$$disp);   // Displacement
2408   %}
2409 
2410   // Push the integer in stackSlot 'src' onto FP-stack
2411   enc_class Push_Mem_I( memory src ) %{    // FILD   [ESP+src]
2412     store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2413   %}
2414 
2415   // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2416   enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2417     store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2418   %}
2419 
2420   // Same as Pop_Mem_F except for opcode
2421   // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2422   enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2423     store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2424   %}
2425 
2426   enc_class Pop_Reg_FPR( regFPR dst ) %{
2427     emit_opcode( cbuf, 0xDD );           // FSTP   ST(i)
2428     emit_d8( cbuf, 0xD8+$dst$$reg );
2429   %}
2430 
2431   enc_class Push_Reg_FPR( regFPR dst ) %{
2432     emit_opcode( cbuf, 0xD9 );           // FLD    ST(i-1)
2433     emit_d8( cbuf, 0xC0-1+$dst$$reg );
2434   %}
2435 
2436   // Push FPU's float to a stack-slot, and pop FPU-stack
2437   enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2438     int pop = 0x02;
2439     if ($src$$reg != FPR1L_enc) {
2440       emit_opcode( cbuf, 0xD9 );         // FLD    ST(i-1)
2441       emit_d8( cbuf, 0xC0-1+$src$$reg );
2442       pop = 0x03;
2443     }
2444     store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S  [ESP+dst]
2445   %}
2446 
2447   // Push FPU's double to a stack-slot, and pop FPU-stack
2448   enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2449     int pop = 0x02;
2450     if ($src$$reg != FPR1L_enc) {
2451       emit_opcode( cbuf, 0xD9 );         // FLD    ST(i-1)
2452       emit_d8( cbuf, 0xC0-1+$src$$reg );
2453       pop = 0x03;
2454     }
2455     store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D  [ESP+dst]
2456   %}
2457 
2458   // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2459   enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2460     int pop = 0xD0 - 1; // -1 since we skip FLD
2461     if ($src$$reg != FPR1L_enc) {
2462       emit_opcode( cbuf, 0xD9 );         // FLD    ST(src-1)
2463       emit_d8( cbuf, 0xC0-1+$src$$reg );
2464       pop = 0xD8;
2465     }
2466     emit_opcode( cbuf, 0xDD );
2467     emit_d8( cbuf, pop+$dst$$reg );      // FST<P> ST(i)
2468   %}
2469 
2470 
2471   enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2472     // load dst in FPR0
2473     emit_opcode( cbuf, 0xD9 );
2474     emit_d8( cbuf, 0xC0-1+$dst$$reg );
2475     if ($src$$reg != FPR1L_enc) {
2476       // fincstp
2477       emit_opcode (cbuf, 0xD9);
2478       emit_opcode (cbuf, 0xF7);
2479       // swap src with FPR1:
2480       // FXCH FPR1 with src
2481       emit_opcode(cbuf, 0xD9);
2482       emit_d8(cbuf, 0xC8-1+$src$$reg );
2483       // fdecstp
2484       emit_opcode (cbuf, 0xD9);
2485       emit_opcode (cbuf, 0xF6);
2486     }
2487   %}
2488 
2489   enc_class Push_ModD_encoding(regD src0, regD src1) %{
2490     MacroAssembler _masm(&cbuf);
2491     __ subptr(rsp, 8);
2492     __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2493     __ fld_d(Address(rsp, 0));
2494     __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2495     __ fld_d(Address(rsp, 0));
2496   %}
2497 
2498   enc_class Push_ModF_encoding(regF src0, regF src1) %{
2499     MacroAssembler _masm(&cbuf);
2500     __ subptr(rsp, 4);
2501     __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2502     __ fld_s(Address(rsp, 0));
2503     __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2504     __ fld_s(Address(rsp, 0));
2505   %}
2506 
2507   enc_class Push_ResultD(regD dst) %{
2508     MacroAssembler _masm(&cbuf);
2509     __ fstp_d(Address(rsp, 0));
2510     __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2511     __ addptr(rsp, 8);
2512   %}
2513 
2514   enc_class Push_ResultF(regF dst, immI d8) %{
2515     MacroAssembler _masm(&cbuf);
2516     __ fstp_s(Address(rsp, 0));
2517     __ movflt($dst$$XMMRegister, Address(rsp, 0));
2518     __ addptr(rsp, $d8$$constant);
2519   %}
2520 
2521   enc_class Push_SrcD(regD src) %{
2522     MacroAssembler _masm(&cbuf);
2523     __ subptr(rsp, 8);
2524     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2525     __ fld_d(Address(rsp, 0));
2526   %}
2527 
2528   enc_class push_stack_temp_qword() %{
2529     MacroAssembler _masm(&cbuf);
2530     __ subptr(rsp, 8);
2531   %}
2532 
2533   enc_class pop_stack_temp_qword() %{
2534     MacroAssembler _masm(&cbuf);
2535     __ addptr(rsp, 8);
2536   %}
2537 
2538   enc_class push_xmm_to_fpr1(regD src) %{
2539     MacroAssembler _masm(&cbuf);
2540     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2541     __ fld_d(Address(rsp, 0));
2542   %}
2543 
2544   enc_class Push_Result_Mod_DPR( regDPR src) %{
2545     if ($src$$reg != FPR1L_enc) {
2546       // fincstp
2547       emit_opcode (cbuf, 0xD9);
2548       emit_opcode (cbuf, 0xF7);
2549       // FXCH FPR1 with src
2550       emit_opcode(cbuf, 0xD9);
2551       emit_d8(cbuf, 0xC8-1+$src$$reg );
2552       // fdecstp
2553       emit_opcode (cbuf, 0xD9);
2554       emit_opcode (cbuf, 0xF6);
2555     }
2556     // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2557     // // FSTP   FPR$dst$$reg
2558     // emit_opcode( cbuf, 0xDD );
2559     // emit_d8( cbuf, 0xD8+$dst$$reg );
2560   %}
2561 
2562   enc_class fnstsw_sahf_skip_parity() %{
2563     // fnstsw ax
2564     emit_opcode( cbuf, 0xDF );
2565     emit_opcode( cbuf, 0xE0 );
2566     // sahf
2567     emit_opcode( cbuf, 0x9E );
2568     // jnp  ::skip
2569     emit_opcode( cbuf, 0x7B );
2570     emit_opcode( cbuf, 0x05 );
2571   %}
2572 
2573   enc_class emitModDPR() %{
2574     // fprem must be iterative
2575     // :: loop
2576     // fprem
2577     emit_opcode( cbuf, 0xD9 );
2578     emit_opcode( cbuf, 0xF8 );
2579     // wait
2580     emit_opcode( cbuf, 0x9b );
2581     // fnstsw ax
2582     emit_opcode( cbuf, 0xDF );
2583     emit_opcode( cbuf, 0xE0 );
2584     // sahf
2585     emit_opcode( cbuf, 0x9E );
2586     // jp  ::loop
2587     emit_opcode( cbuf, 0x0F );
2588     emit_opcode( cbuf, 0x8A );
2589     emit_opcode( cbuf, 0xF4 );
2590     emit_opcode( cbuf, 0xFF );
2591     emit_opcode( cbuf, 0xFF );
2592     emit_opcode( cbuf, 0xFF );
2593   %}
2594 
2595   enc_class fpu_flags() %{
2596     // fnstsw_ax
2597     emit_opcode( cbuf, 0xDF);
2598     emit_opcode( cbuf, 0xE0);
2599     // test ax,0x0400
2600     emit_opcode( cbuf, 0x66 );   // operand-size prefix for 16-bit immediate
2601     emit_opcode( cbuf, 0xA9 );
2602     emit_d16   ( cbuf, 0x0400 );
2603     // // // This sequence works, but stalls for 12-16 cycles on PPro
2604     // // test rax,0x0400
2605     // emit_opcode( cbuf, 0xA9 );
2606     // emit_d32   ( cbuf, 0x00000400 );
2607     //
2608     // jz exit (no unordered comparison)
2609     emit_opcode( cbuf, 0x74 );
2610     emit_d8    ( cbuf, 0x02 );
2611     // mov ah,1 - treat as LT case (set carry flag)
2612     emit_opcode( cbuf, 0xB4 );
2613     emit_d8    ( cbuf, 0x01 );
2614     // sahf
2615     emit_opcode( cbuf, 0x9E);
2616   %}
2617 
2618   enc_class cmpF_P6_fixup() %{
2619     // Fixup the integer flags in case comparison involved a NaN
2620     //
2621     // JNP exit (no unordered comparison, P-flag is set by NaN)
2622     emit_opcode( cbuf, 0x7B );
2623     emit_d8    ( cbuf, 0x03 );
2624     // MOV AH,1 - treat as LT case (set carry flag)
2625     emit_opcode( cbuf, 0xB4 );
2626     emit_d8    ( cbuf, 0x01 );
2627     // SAHF
2628     emit_opcode( cbuf, 0x9E);
2629     // NOP     // target for branch to avoid branch to branch
2630     emit_opcode( cbuf, 0x90);
2631   %}
2632 
2633 //     fnstsw_ax();
2634 //     sahf();
2635 //     movl(dst, nan_result);
2636 //     jcc(Assembler::parity, exit);
2637 //     movl(dst, less_result);
2638 //     jcc(Assembler::below, exit);
2639 //     movl(dst, equal_result);
2640 //     jcc(Assembler::equal, exit);
2641 //     movl(dst, greater_result);
2642 
2643 // less_result     =  1;
2644 // greater_result  = -1;
2645 // equal_result    = 0;
2646 // nan_result      = -1;
2647 
2648   enc_class CmpF_Result(rRegI dst) %{
2649     // fnstsw_ax();
2650     emit_opcode( cbuf, 0xDF);
2651     emit_opcode( cbuf, 0xE0);
2652     // sahf
2653     emit_opcode( cbuf, 0x9E);
2654     // movl(dst, nan_result);
2655     emit_opcode( cbuf, 0xB8 + $dst$$reg);
2656     emit_d32( cbuf, -1 );
2657     // jcc(Assembler::parity, exit);
2658     emit_opcode( cbuf, 0x7A );
2659     emit_d8    ( cbuf, 0x13 );
2660     // movl(dst, less_result);
2661     emit_opcode( cbuf, 0xB8 + $dst$$reg);
2662     emit_d32( cbuf, -1 );
2663     // jcc(Assembler::below, exit);
2664     emit_opcode( cbuf, 0x72 );
2665     emit_d8    ( cbuf, 0x0C );
2666     // movl(dst, equal_result);
2667     emit_opcode( cbuf, 0xB8 + $dst$$reg);
2668     emit_d32( cbuf, 0 );
2669     // jcc(Assembler::equal, exit);
2670     emit_opcode( cbuf, 0x74 );
2671     emit_d8    ( cbuf, 0x05 );
2672     // movl(dst, greater_result);
2673     emit_opcode( cbuf, 0xB8 + $dst$$reg);
2674     emit_d32( cbuf, 1 );
2675   %}
2676 
2677 
2678   // Compare the longs and set flags
2679   // BROKEN!  Do Not use as-is
2680   enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2681     // CMP    $src1.hi,$src2.hi
2682     emit_opcode( cbuf, 0x3B );
2683     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2684     // JNE,s  done
2685     emit_opcode(cbuf,0x75);
2686     emit_d8(cbuf, 2 );
2687     // CMP    $src1.lo,$src2.lo
2688     emit_opcode( cbuf, 0x3B );
2689     emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2690 // done:
2691   %}
2692 
2693   enc_class convert_int_long( regL dst, rRegI src ) %{
2694     // mov $dst.lo,$src
2695     int dst_encoding = $dst$$reg;
2696     int src_encoding = $src$$reg;
2697     encode_Copy( cbuf, dst_encoding  , src_encoding );
2698     // mov $dst.hi,$src
2699     encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2700     // sar $dst.hi,31
2701     emit_opcode( cbuf, 0xC1 );
2702     emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2703     emit_d8(cbuf, 0x1F );
2704   %}
2705 
2706   enc_class convert_long_double( eRegL src ) %{
2707     // push $src.hi
2708     emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2709     // push $src.lo
2710     emit_opcode(cbuf, 0x50+$src$$reg  );
2711     // fild 64-bits at [SP]
2712     emit_opcode(cbuf,0xdf);
2713     emit_d8(cbuf, 0x6C);
2714     emit_d8(cbuf, 0x24);
2715     emit_d8(cbuf, 0x00);
2716     // pop stack
2717     emit_opcode(cbuf, 0x83); // add  SP, #8
2718     emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2719     emit_d8(cbuf, 0x8);
2720   %}
2721 
2722   enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2723     // IMUL   EDX:EAX,$src1
2724     emit_opcode( cbuf, 0xF7 );
2725     emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2726     // SAR    EDX,$cnt-32
2727     int shift_count = ((int)$cnt$$constant) - 32;
2728     if (shift_count > 0) {
2729       emit_opcode(cbuf, 0xC1);
2730       emit_rm(cbuf, 0x3, 7, $dst$$reg );
2731       emit_d8(cbuf, shift_count);
2732     }
2733   %}
2734 
2735   // this version doesn't have add sp, 8
2736   enc_class convert_long_double2( eRegL src ) %{
2737     // push $src.hi
2738     emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2739     // push $src.lo
2740     emit_opcode(cbuf, 0x50+$src$$reg  );
2741     // fild 64-bits at [SP]
2742     emit_opcode(cbuf,0xdf);
2743     emit_d8(cbuf, 0x6C);
2744     emit_d8(cbuf, 0x24);
2745     emit_d8(cbuf, 0x00);
2746   %}
2747 
2748   enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2749     // Basic idea: long = (long)int * (long)int
2750     // IMUL EDX:EAX, src
2751     emit_opcode( cbuf, 0xF7 );
2752     emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2753   %}
2754 
2755   enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2756     // Basic Idea:  long = (int & 0xffffffffL) * (int & 0xffffffffL)
2757     // MUL EDX:EAX, src
2758     emit_opcode( cbuf, 0xF7 );
2759     emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2760   %}
2761 
2762   enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2763     // Basic idea: lo(result) = lo(x_lo * y_lo)
2764     //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2765     // MOV    $tmp,$src.lo
2766     encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2767     // IMUL   $tmp,EDX
2768     emit_opcode( cbuf, 0x0F );
2769     emit_opcode( cbuf, 0xAF );
2770     emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2771     // MOV    EDX,$src.hi
2772     encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2773     // IMUL   EDX,EAX
2774     emit_opcode( cbuf, 0x0F );
2775     emit_opcode( cbuf, 0xAF );
2776     emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2777     // ADD    $tmp,EDX
2778     emit_opcode( cbuf, 0x03 );
2779     emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2780     // MUL   EDX:EAX,$src.lo
2781     emit_opcode( cbuf, 0xF7 );
2782     emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2783     // ADD    EDX,ESI
2784     emit_opcode( cbuf, 0x03 );
2785     emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2786   %}
2787 
2788   enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2789     // Basic idea: lo(result) = lo(src * y_lo)
2790     //             hi(result) = hi(src * y_lo) + lo(src * y_hi)
2791     // IMUL   $tmp,EDX,$src
2792     emit_opcode( cbuf, 0x6B );
2793     emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2794     emit_d8( cbuf, (int)$src$$constant );
2795     // MOV    EDX,$src
2796     emit_opcode(cbuf, 0xB8 + EDX_enc);
2797     emit_d32( cbuf, (int)$src$$constant );
2798     // MUL   EDX:EAX,EDX
2799     emit_opcode( cbuf, 0xF7 );
2800     emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2801     // ADD    EDX,ESI
2802     emit_opcode( cbuf, 0x03 );
2803     emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2804   %}
2805 
2806   enc_class long_div( eRegL src1, eRegL src2 ) %{
2807     // PUSH src1.hi
2808     emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2809     // PUSH src1.lo
2810     emit_opcode(cbuf,               0x50+$src1$$reg  );
2811     // PUSH src2.hi
2812     emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2813     // PUSH src2.lo
2814     emit_opcode(cbuf,               0x50+$src2$$reg  );
2815     // CALL directly to the runtime
2816     cbuf.set_insts_mark();
2817     emit_opcode(cbuf,0xE8);       // Call into runtime
2818     emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2819     // Restore stack
2820     emit_opcode(cbuf, 0x83); // add  SP, #framesize
2821     emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2822     emit_d8(cbuf, 4*4);
2823   %}
2824 
2825   enc_class long_mod( eRegL src1, eRegL src2 ) %{
2826     // PUSH src1.hi
2827     emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2828     // PUSH src1.lo
2829     emit_opcode(cbuf,               0x50+$src1$$reg  );
2830     // PUSH src2.hi
2831     emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2832     // PUSH src2.lo
2833     emit_opcode(cbuf,               0x50+$src2$$reg  );
2834     // CALL directly to the runtime
2835     cbuf.set_insts_mark();
2836     emit_opcode(cbuf,0xE8);       // Call into runtime
2837     emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2838     // Restore stack
2839     emit_opcode(cbuf, 0x83); // add  SP, #framesize
2840     emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2841     emit_d8(cbuf, 4*4);
2842   %}
2843 
2844   enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2845     // MOV   $tmp,$src.lo
2846     emit_opcode(cbuf, 0x8B);
2847     emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2848     // OR    $tmp,$src.hi
2849     emit_opcode(cbuf, 0x0B);
2850     emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2851   %}
2852 
2853   enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2854     // CMP    $src1.lo,$src2.lo
2855     emit_opcode( cbuf, 0x3B );
2856     emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2857     // JNE,s  skip
2858     emit_cc(cbuf, 0x70, 0x5);
2859     emit_d8(cbuf,2);
2860     // CMP    $src1.hi,$src2.hi
2861     emit_opcode( cbuf, 0x3B );
2862     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2863   %}
2864 
2865   enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2866     // CMP    $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2867     emit_opcode( cbuf, 0x3B );
2868     emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2869     // MOV    $tmp,$src1.hi
2870     emit_opcode( cbuf, 0x8B );
2871     emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2872     // SBB   $tmp,$src2.hi\t! Compute flags for long compare
2873     emit_opcode( cbuf, 0x1B );
2874     emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2875   %}
2876 
2877   enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2878     // XOR    $tmp,$tmp
2879     emit_opcode(cbuf,0x33);  // XOR
2880     emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2881     // CMP    $tmp,$src.lo
2882     emit_opcode( cbuf, 0x3B );
2883     emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2884     // SBB    $tmp,$src.hi
2885     emit_opcode( cbuf, 0x1B );
2886     emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2887   %}
2888 
2889  // Sniff, sniff... smells like Gnu Superoptimizer
2890   enc_class neg_long( eRegL dst ) %{
2891     emit_opcode(cbuf,0xF7);    // NEG hi
2892     emit_rm    (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2893     emit_opcode(cbuf,0xF7);    // NEG lo
2894     emit_rm    (cbuf,0x3, 0x3,               $dst$$reg );
2895     emit_opcode(cbuf,0x83);    // SBB hi,0
2896     emit_rm    (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2897     emit_d8    (cbuf,0 );
2898   %}
2899 
2900   enc_class enc_pop_rdx() %{
2901     emit_opcode(cbuf,0x5A);
2902   %}
2903 
2904   enc_class enc_rethrow() %{
2905     cbuf.set_insts_mark();
2906     emit_opcode(cbuf, 0xE9);        // jmp    entry
2907     emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
2908                    runtime_call_Relocation::spec(), RELOC_IMM32 );
2909   %}
2910 
2911 
2912   // Convert a double to an int.  Java semantics require we do complex
2913   // manglelations in the corner cases.  So we set the rounding mode to
2914   // 'zero', store the darned double down as an int, and reset the
2915   // rounding mode to 'nearest'.  The hardware throws an exception which
2916   // patches up the correct value directly to the stack.
2917   enc_class DPR2I_encoding( regDPR src ) %{
2918     // Flip to round-to-zero mode.  We attempted to allow invalid-op
2919     // exceptions here, so that a NAN or other corner-case value will
2920     // thrown an exception (but normal values get converted at full speed).
2921     // However, I2C adapters and other float-stack manglers leave pending
2922     // invalid-op exceptions hanging.  We would have to clear them before
2923     // enabling them and that is more expensive than just testing for the
2924     // invalid value Intel stores down in the corner cases.
2925     emit_opcode(cbuf,0xD9);            // FLDCW  trunc
2926     emit_opcode(cbuf,0x2D);
2927     emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
2928     // Allocate a word
2929     emit_opcode(cbuf,0x83);            // SUB ESP,4
2930     emit_opcode(cbuf,0xEC);
2931     emit_d8(cbuf,0x04);
2932     // Encoding assumes a double has been pushed into FPR0.
2933     // Store down the double as an int, popping the FPU stack
2934     emit_opcode(cbuf,0xDB);            // FISTP [ESP]
2935     emit_opcode(cbuf,0x1C);
2936     emit_d8(cbuf,0x24);
2937     // Restore the rounding mode; mask the exception
2938     emit_opcode(cbuf,0xD9);            // FLDCW   std/24-bit mode
2939     emit_opcode(cbuf,0x2D);
2940     emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
2941         ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
2942         : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
2943 
2944     // Load the converted int; adjust CPU stack
2945     emit_opcode(cbuf,0x58);       // POP EAX
2946     emit_opcode(cbuf,0x3D);       // CMP EAX,imm
2947     emit_d32   (cbuf,0x80000000); //         0x80000000
2948     emit_opcode(cbuf,0x75);       // JNE around_slow_call
2949     emit_d8    (cbuf,0x07);       // Size of slow_call
2950     // Push src onto stack slow-path
2951     emit_opcode(cbuf,0xD9 );      // FLD     ST(i)
2952     emit_d8    (cbuf,0xC0-1+$src$$reg );
2953     // CALL directly to the runtime
2954     cbuf.set_insts_mark();
2955     emit_opcode(cbuf,0xE8);       // Call into runtime
2956     emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2957     // Carry on here...
2958   %}
2959 
2960   enc_class DPR2L_encoding( regDPR src ) %{
2961     emit_opcode(cbuf,0xD9);            // FLDCW  trunc
2962     emit_opcode(cbuf,0x2D);
2963     emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
2964     // Allocate a word
2965     emit_opcode(cbuf,0x83);            // SUB ESP,8
2966     emit_opcode(cbuf,0xEC);
2967     emit_d8(cbuf,0x08);
2968     // Encoding assumes a double has been pushed into FPR0.
2969     // Store down the double as a long, popping the FPU stack
2970     emit_opcode(cbuf,0xDF);            // FISTP [ESP]
2971     emit_opcode(cbuf,0x3C);
2972     emit_d8(cbuf,0x24);
2973     // Restore the rounding mode; mask the exception
2974     emit_opcode(cbuf,0xD9);            // FLDCW   std/24-bit mode
2975     emit_opcode(cbuf,0x2D);
2976     emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
2977         ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
2978         : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
2979 
2980     // Load the converted int; adjust CPU stack
2981     emit_opcode(cbuf,0x58);       // POP EAX
2982     emit_opcode(cbuf,0x5A);       // POP EDX
2983     emit_opcode(cbuf,0x81);       // CMP EDX,imm
2984     emit_d8    (cbuf,0xFA);       // rdx
2985     emit_d32   (cbuf,0x80000000); //         0x80000000
2986     emit_opcode(cbuf,0x75);       // JNE around_slow_call
2987     emit_d8    (cbuf,0x07+4);     // Size of slow_call
2988     emit_opcode(cbuf,0x85);       // TEST EAX,EAX
2989     emit_opcode(cbuf,0xC0);       // 2/rax,/rax,
2990     emit_opcode(cbuf,0x75);       // JNE around_slow_call
2991     emit_d8    (cbuf,0x07);       // Size of slow_call
2992     // Push src onto stack slow-path
2993     emit_opcode(cbuf,0xD9 );      // FLD     ST(i)
2994     emit_d8    (cbuf,0xC0-1+$src$$reg );
2995     // CALL directly to the runtime
2996     cbuf.set_insts_mark();
2997     emit_opcode(cbuf,0xE8);       // Call into runtime
2998     emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2999     // Carry on here...
3000   %}
3001 
3002   enc_class FMul_ST_reg( eRegFPR src1 ) %{
3003     // Operand was loaded from memory into fp ST (stack top)
3004     // FMUL   ST,$src  /* D8 C8+i */
3005     emit_opcode(cbuf, 0xD8);
3006     emit_opcode(cbuf, 0xC8 + $src1$$reg);
3007   %}
3008 
3009   enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3010     // FADDP  ST,src2  /* D8 C0+i */
3011     emit_opcode(cbuf, 0xD8);
3012     emit_opcode(cbuf, 0xC0 + $src2$$reg);
3013     //could use FADDP  src2,fpST  /* DE C0+i */
3014   %}
3015 
3016   enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3017     // FADDP  src2,ST  /* DE C0+i */
3018     emit_opcode(cbuf, 0xDE);
3019     emit_opcode(cbuf, 0xC0 + $src2$$reg);
3020   %}
3021 
3022   enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3023     // Operand has been loaded into fp ST (stack top)
3024       // FSUB   ST,$src1
3025       emit_opcode(cbuf, 0xD8);
3026       emit_opcode(cbuf, 0xE0 + $src1$$reg);
3027 
3028       // FDIV
3029       emit_opcode(cbuf, 0xD8);
3030       emit_opcode(cbuf, 0xF0 + $src2$$reg);
3031   %}
3032 
3033   enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3034     // Operand was loaded from memory into fp ST (stack top)
3035     // FADD   ST,$src  /* D8 C0+i */
3036     emit_opcode(cbuf, 0xD8);
3037     emit_opcode(cbuf, 0xC0 + $src1$$reg);
3038 
3039     // FMUL  ST,src2  /* D8 C*+i */
3040     emit_opcode(cbuf, 0xD8);
3041     emit_opcode(cbuf, 0xC8 + $src2$$reg);
3042   %}
3043 
3044 
3045   enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3046     // Operand was loaded from memory into fp ST (stack top)
3047     // FADD   ST,$src  /* D8 C0+i */
3048     emit_opcode(cbuf, 0xD8);
3049     emit_opcode(cbuf, 0xC0 + $src1$$reg);
3050 
3051     // FMULP  src2,ST  /* DE C8+i */
3052     emit_opcode(cbuf, 0xDE);
3053     emit_opcode(cbuf, 0xC8 + $src2$$reg);
3054   %}
3055 
3056   // Atomically load the volatile long
3057   enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3058     emit_opcode(cbuf,0xDF);
3059     int rm_byte_opcode = 0x05;
3060     int base     = $mem$$base;
3061     int index    = $mem$$index;
3062     int scale    = $mem$$scale;
3063     int displace = $mem$$disp;
3064     relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3065     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3066     store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3067   %}
3068 
3069   // Volatile Store Long.  Must be atomic, so move it into
3070   // the FP TOS and then do a 64-bit FIST.  Has to probe the
3071   // target address before the store (for null-ptr checks)
3072   // so the memory operand is used twice in the encoding.
3073   enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3074     store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3075     cbuf.set_insts_mark();            // Mark start of FIST in case $mem has an oop
3076     emit_opcode(cbuf,0xDF);
3077     int rm_byte_opcode = 0x07;
3078     int base     = $mem$$base;
3079     int index    = $mem$$index;
3080     int scale    = $mem$$scale;
3081     int displace = $mem$$disp;
3082     relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3083     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3084   %}
3085 
3086   // Safepoint Poll.  This polls the safepoint page, and causes an
3087   // exception if it is not readable. Unfortunately, it kills the condition code
3088   // in the process
3089   // We current use TESTL [spp],EDI
3090   // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3091 
3092   enc_class Safepoint_Poll() %{
3093     cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3094     emit_opcode(cbuf,0x85);
3095     emit_rm (cbuf, 0x0, 0x7, 0x5);
3096     emit_d32(cbuf, (intptr_t)os::get_polling_page());
3097   %}
3098 %}
3099 
3100 
3101 //----------FRAME--------------------------------------------------------------
3102 // Definition of frame structure and management information.
3103 //
3104 //  S T A C K   L A Y O U T    Allocators stack-slot number
3105 //                             |   (to get allocators register number
3106 //  G  Owned by    |        |  v    add OptoReg::stack0())
3107 //  r   CALLER     |        |
3108 //  o     |        +--------+      pad to even-align allocators stack-slot
3109 //  w     V        |  pad0  |        numbers; owned by CALLER
3110 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
3111 //  h     ^        |   in   |  5
3112 //        |        |  args  |  4   Holes in incoming args owned by SELF
3113 //  |     |        |        |  3
3114 //  |     |        +--------+
3115 //  V     |        | old out|      Empty on Intel, window on Sparc
3116 //        |    old |preserve|      Must be even aligned.
3117 //        |     SP-+--------+----> Matcher::_old_SP, even aligned
3118 //        |        |   in   |  3   area for Intel ret address
3119 //     Owned by    |preserve|      Empty on Sparc.
3120 //       SELF      +--------+
3121 //        |        |  pad2  |  2   pad to align old SP
3122 //        |        +--------+  1
3123 //        |        | locks  |  0
3124 //        |        +--------+----> OptoReg::stack0(), even aligned
3125 //        |        |  pad1  | 11   pad to align new SP
3126 //        |        +--------+
3127 //        |        |        | 10
3128 //        |        | spills |  9   spills
3129 //        V        |        |  8   (pad0 slot for callee)
3130 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
3131 //        ^        |  out   |  7
3132 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
3133 //     Owned by    +--------+
3134 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
3135 //        |    new |preserve|      Must be even-aligned.
3136 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
3137 //        |        |        |
3138 //
3139 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
3140 //         known from SELF's arguments and the Java calling convention.
3141 //         Region 6-7 is determined per call site.
3142 // Note 2: If the calling convention leaves holes in the incoming argument
3143 //         area, those holes are owned by SELF.  Holes in the outgoing area
3144 //         are owned by the CALLEE.  Holes should not be nessecary in the
3145 //         incoming area, as the Java calling convention is completely under
3146 //         the control of the AD file.  Doubles can be sorted and packed to
3147 //         avoid holes.  Holes in the outgoing arguments may be nessecary for
3148 //         varargs C calling conventions.
3149 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
3150 //         even aligned with pad0 as needed.
3151 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
3152 //         region 6-11 is even aligned; it may be padded out more so that
3153 //         the region from SP to FP meets the minimum stack alignment.
3154 
3155 frame %{
3156   // What direction does stack grow in (assumed to be same for C & Java)
3157   stack_direction(TOWARDS_LOW);
3158 
3159   // These three registers define part of the calling convention
3160   // between compiled code and the interpreter.
3161   inline_cache_reg(EAX);                // Inline Cache Register
3162   interpreter_method_oop_reg(EBX);      // Method Oop Register when calling interpreter
3163 
3164   // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3165   cisc_spilling_operand_name(indOffset32);
3166 
3167   // Number of stack slots consumed by locking an object
3168   sync_stack_slots(1);
3169 
3170   // Compiled code's Frame Pointer
3171   frame_pointer(ESP);
3172   // Interpreter stores its frame pointer in a register which is
3173   // stored to the stack by I2CAdaptors.
3174   // I2CAdaptors convert from interpreted java to compiled java.
3175   interpreter_frame_pointer(EBP);
3176 
3177   // Stack alignment requirement
3178   // Alignment size in bytes (128-bit -> 16 bytes)
3179   stack_alignment(StackAlignmentInBytes);
3180 
3181   // Number of stack slots between incoming argument block and the start of
3182   // a new frame.  The PROLOG must add this many slots to the stack.  The
3183   // EPILOG must remove this many slots.  Intel needs one slot for
3184   // return address and one for rbp, (must save rbp)
3185   in_preserve_stack_slots(2+VerifyStackAtCalls);
3186 
3187   // Number of outgoing stack slots killed above the out_preserve_stack_slots
3188   // for calls to C.  Supports the var-args backing area for register parms.
3189   varargs_C_out_slots_killed(0);
3190 
3191   // The after-PROLOG location of the return address.  Location of
3192   // return address specifies a type (REG or STACK) and a number
3193   // representing the register number (i.e. - use a register name) or
3194   // stack slot.
3195   // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3196   // Otherwise, it is above the locks and verification slot and alignment word
3197   return_addr(STACK - 1 +
3198               round_to((Compile::current()->in_preserve_stack_slots() +
3199                         Compile::current()->fixed_slots()),
3200                        stack_alignment_in_slots()));
3201 
3202   // Body of function which returns an integer array locating
3203   // arguments either in registers or in stack slots.  Passed an array
3204   // of ideal registers called "sig" and a "length" count.  Stack-slot
3205   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3206   // arguments for a CALLEE.  Incoming stack arguments are
3207   // automatically biased by the preserve_stack_slots field above.
3208   calling_convention %{
3209     // No difference between ingoing/outgoing just pass false
3210     SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3211   %}
3212 
3213 
3214   // Body of function which returns an integer array locating
3215   // arguments either in registers or in stack slots.  Passed an array
3216   // of ideal registers called "sig" and a "length" count.  Stack-slot
3217   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3218   // arguments for a CALLEE.  Incoming stack arguments are
3219   // automatically biased by the preserve_stack_slots field above.
3220   c_calling_convention %{
3221     // This is obviously always outgoing
3222     (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3223   %}
3224 
3225   // Location of C & interpreter return values
3226   c_return_value %{
3227     assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3228     static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num,      EAX_num,      FPR1L_num,    FPR1L_num, EAX_num };
3229     static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3230 
3231     // in SSE2+ mode we want to keep the FPU stack clean so pretend
3232     // that C functions return float and double results in XMM0.
3233     if( ideal_reg == Op_RegD && UseSSE>=2 )
3234       return OptoRegPair(XMM0b_num,XMM0_num);
3235     if( ideal_reg == Op_RegF && UseSSE>=2 )
3236       return OptoRegPair(OptoReg::Bad,XMM0_num);
3237 
3238     return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3239   %}
3240 
3241   // Location of return values
3242   return_value %{
3243     assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3244     static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num,      EAX_num,      FPR1L_num,    FPR1L_num, EAX_num };
3245     static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3246     if( ideal_reg == Op_RegD && UseSSE>=2 )
3247       return OptoRegPair(XMM0b_num,XMM0_num);
3248     if( ideal_reg == Op_RegF && UseSSE>=1 )
3249       return OptoRegPair(OptoReg::Bad,XMM0_num);
3250     return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3251   %}
3252 
3253 %}
3254 
3255 //----------ATTRIBUTES---------------------------------------------------------
3256 //----------Operand Attributes-------------------------------------------------
3257 op_attrib op_cost(0);        // Required cost attribute
3258 
3259 //----------Instruction Attributes---------------------------------------------
3260 ins_attrib ins_cost(100);       // Required cost attribute
3261 ins_attrib ins_size(8);         // Required size attribute (in bits)
3262 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3263                                 // non-matching short branch variant of some
3264                                                             // long branch?
3265 ins_attrib ins_alignment(1);    // Required alignment attribute (must be a power of 2)
3266                                 // specifies the alignment that some part of the instruction (not
3267                                 // necessarily the start) requires.  If > 1, a compute_padding()
3268                                 // function must be provided for the instruction
3269 
3270 //----------OPERANDS-----------------------------------------------------------
3271 // Operand definitions must precede instruction definitions for correct parsing
3272 // in the ADLC because operands constitute user defined types which are used in
3273 // instruction definitions.
3274 
3275 //----------Simple Operands----------------------------------------------------
3276 // Immediate Operands
3277 // Integer Immediate
3278 operand immI() %{
3279   match(ConI);
3280 
3281   op_cost(10);
3282   format %{ %}
3283   interface(CONST_INTER);
3284 %}
3285 
3286 // Constant for test vs zero
3287 operand immI0() %{
3288   predicate(n->get_int() == 0);
3289   match(ConI);
3290 
3291   op_cost(0);
3292   format %{ %}
3293   interface(CONST_INTER);
3294 %}
3295 
3296 // Constant for increment
3297 operand immI1() %{
3298   predicate(n->get_int() == 1);
3299   match(ConI);
3300 
3301   op_cost(0);
3302   format %{ %}
3303   interface(CONST_INTER);
3304 %}
3305 
3306 // Constant for decrement
3307 operand immI_M1() %{
3308   predicate(n->get_int() == -1);
3309   match(ConI);
3310 
3311   op_cost(0);
3312   format %{ %}
3313   interface(CONST_INTER);
3314 %}
3315 
3316 // Valid scale values for addressing modes
3317 operand immI2() %{
3318   predicate(0 <= n->get_int() && (n->get_int() <= 3));
3319   match(ConI);
3320 
3321   format %{ %}
3322   interface(CONST_INTER);
3323 %}
3324 
3325 operand immI8() %{
3326   predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3327   match(ConI);
3328 
3329   op_cost(5);
3330   format %{ %}
3331   interface(CONST_INTER);
3332 %}
3333 
3334 operand immI16() %{
3335   predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3336   match(ConI);
3337 
3338   op_cost(10);
3339   format %{ %}
3340   interface(CONST_INTER);
3341 %}
3342 
3343 // Int Immediate non-negative
3344 operand immU31()
3345 %{
3346   predicate(n->get_int() >= 0);
3347   match(ConI);
3348 
3349   op_cost(0);
3350   format %{ %}
3351   interface(CONST_INTER);
3352 %}
3353 
3354 // Constant for long shifts
3355 operand immI_32() %{
3356   predicate( n->get_int() == 32 );
3357   match(ConI);
3358 
3359   op_cost(0);
3360   format %{ %}
3361   interface(CONST_INTER);
3362 %}
3363 
3364 operand immI_1_31() %{
3365   predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3366   match(ConI);
3367 
3368   op_cost(0);
3369   format %{ %}
3370   interface(CONST_INTER);
3371 %}
3372 
3373 operand immI_32_63() %{
3374   predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3375   match(ConI);
3376   op_cost(0);
3377 
3378   format %{ %}
3379   interface(CONST_INTER);
3380 %}
3381 
3382 operand immI_1() %{
3383   predicate( n->get_int() == 1 );
3384   match(ConI);
3385 
3386   op_cost(0);
3387   format %{ %}
3388   interface(CONST_INTER);
3389 %}
3390 
3391 operand immI_2() %{
3392   predicate( n->get_int() == 2 );
3393   match(ConI);
3394 
3395   op_cost(0);
3396   format %{ %}
3397   interface(CONST_INTER);
3398 %}
3399 
3400 operand immI_3() %{
3401   predicate( n->get_int() == 3 );
3402   match(ConI);
3403 
3404   op_cost(0);
3405   format %{ %}
3406   interface(CONST_INTER);
3407 %}
3408 
3409 // Pointer Immediate
3410 operand immP() %{
3411   match(ConP);
3412 
3413   op_cost(10);
3414   format %{ %}
3415   interface(CONST_INTER);
3416 %}
3417 
3418 // NULL Pointer Immediate
3419 operand immP0() %{
3420   predicate( n->get_ptr() == 0 );
3421   match(ConP);
3422   op_cost(0);
3423 
3424   format %{ %}
3425   interface(CONST_INTER);
3426 %}
3427 
3428 // Long Immediate
3429 operand immL() %{
3430   match(ConL);
3431 
3432   op_cost(20);
3433   format %{ %}
3434   interface(CONST_INTER);
3435 %}
3436 
3437 // Long Immediate zero
3438 operand immL0() %{
3439   predicate( n->get_long() == 0L );
3440   match(ConL);
3441   op_cost(0);
3442 
3443   format %{ %}
3444   interface(CONST_INTER);
3445 %}
3446 
3447 // Long Immediate zero
3448 operand immL_M1() %{
3449   predicate( n->get_long() == -1L );
3450   match(ConL);
3451   op_cost(0);
3452 
3453   format %{ %}
3454   interface(CONST_INTER);
3455 %}
3456 
3457 // Long immediate from 0 to 127.
3458 // Used for a shorter form of long mul by 10.
3459 operand immL_127() %{
3460   predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3461   match(ConL);
3462   op_cost(0);
3463 
3464   format %{ %}
3465   interface(CONST_INTER);
3466 %}
3467 
3468 // Long Immediate: low 32-bit mask
3469 operand immL_32bits() %{
3470   predicate(n->get_long() == 0xFFFFFFFFL);
3471   match(ConL);
3472   op_cost(0);
3473 
3474   format %{ %}
3475   interface(CONST_INTER);
3476 %}
3477 
3478 // Long Immediate: low 32-bit mask
3479 operand immL32() %{
3480   predicate(n->get_long() == (int)(n->get_long()));
3481   match(ConL);
3482   op_cost(20);
3483 
3484   format %{ %}
3485   interface(CONST_INTER);
3486 %}
3487 
3488 //Double Immediate zero
3489 operand immDPR0() %{
3490   // Do additional (and counter-intuitive) test against NaN to work around VC++
3491   // bug that generates code such that NaNs compare equal to 0.0
3492   predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
3493   match(ConD);
3494 
3495   op_cost(5);
3496   format %{ %}
3497   interface(CONST_INTER);
3498 %}
3499 
3500 // Double Immediate one
3501 operand immDPR1() %{
3502   predicate( UseSSE<=1 && n->getd() == 1.0 );
3503   match(ConD);
3504 
3505   op_cost(5);
3506   format %{ %}
3507   interface(CONST_INTER);
3508 %}
3509 
3510 // Double Immediate
3511 operand immDPR() %{
3512   predicate(UseSSE<=1);
3513   match(ConD);
3514 
3515   op_cost(5);
3516   format %{ %}
3517   interface(CONST_INTER);
3518 %}
3519 
3520 operand immD() %{
3521   predicate(UseSSE>=2);
3522   match(ConD);
3523 
3524   op_cost(5);
3525   format %{ %}
3526   interface(CONST_INTER);
3527 %}
3528 
3529 // Double Immediate zero
3530 operand immD0() %{
3531   // Do additional (and counter-intuitive) test against NaN to work around VC++
3532   // bug that generates code such that NaNs compare equal to 0.0 AND do not
3533   // compare equal to -0.0.
3534   predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
3535   match(ConD);
3536 
3537   format %{ %}
3538   interface(CONST_INTER);
3539 %}
3540 
3541 // Float Immediate zero
3542 operand immFPR0() %{
3543   predicate(UseSSE == 0 && n->getf() == 0.0F);
3544   match(ConF);
3545 
3546   op_cost(5);
3547   format %{ %}
3548   interface(CONST_INTER);
3549 %}
3550 
3551 // Float Immediate one
3552 operand immFPR1() %{
3553   predicate(UseSSE == 0 && n->getf() == 1.0F);
3554   match(ConF);
3555 
3556   op_cost(5);
3557   format %{ %}
3558   interface(CONST_INTER);
3559 %}
3560 
3561 // Float Immediate
3562 operand immFPR() %{
3563   predicate( UseSSE == 0 );
3564   match(ConF);
3565 
3566   op_cost(5);
3567   format %{ %}
3568   interface(CONST_INTER);
3569 %}
3570 
3571 // Float Immediate
3572 operand immF() %{
3573   predicate(UseSSE >= 1);
3574   match(ConF);
3575 
3576   op_cost(5);
3577   format %{ %}
3578   interface(CONST_INTER);
3579 %}
3580 
3581 // Float Immediate zero.  Zero and not -0.0
3582 operand immF0() %{
3583   predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
3584   match(ConF);
3585 
3586   op_cost(5);
3587   format %{ %}
3588   interface(CONST_INTER);
3589 %}
3590 
3591 // Immediates for special shifts (sign extend)
3592 
3593 // Constants for increment
3594 operand immI_16() %{
3595   predicate( n->get_int() == 16 );
3596   match(ConI);
3597 
3598   format %{ %}
3599   interface(CONST_INTER);
3600 %}
3601 
3602 operand immI_24() %{
3603   predicate( n->get_int() == 24 );
3604   match(ConI);
3605 
3606   format %{ %}
3607   interface(CONST_INTER);
3608 %}
3609 
3610 // Constant for byte-wide masking
3611 operand immI_255() %{
3612   predicate( n->get_int() == 255 );
3613   match(ConI);
3614 
3615   format %{ %}
3616   interface(CONST_INTER);
3617 %}
3618 
3619 // Constant for short-wide masking
3620 operand immI_65535() %{
3621   predicate(n->get_int() == 65535);
3622   match(ConI);
3623 
3624   format %{ %}
3625   interface(CONST_INTER);
3626 %}
3627 
3628 // Register Operands
3629 // Integer Register
3630 operand rRegI() %{
3631   constraint(ALLOC_IN_RC(int_reg));
3632   match(RegI);
3633   match(xRegI);
3634   match(eAXRegI);
3635   match(eBXRegI);
3636   match(eCXRegI);
3637   match(eDXRegI);
3638   match(eDIRegI);
3639   match(eSIRegI);
3640 
3641   format %{ %}
3642   interface(REG_INTER);
3643 %}
3644 
3645 // Subset of Integer Register
3646 operand xRegI(rRegI reg) %{
3647   constraint(ALLOC_IN_RC(int_x_reg));
3648   match(reg);
3649   match(eAXRegI);
3650   match(eBXRegI);
3651   match(eCXRegI);
3652   match(eDXRegI);
3653 
3654   format %{ %}
3655   interface(REG_INTER);
3656 %}
3657 
3658 // Special Registers
3659 operand eAXRegI(xRegI reg) %{
3660   constraint(ALLOC_IN_RC(eax_reg));
3661   match(reg);
3662   match(rRegI);
3663 
3664   format %{ "EAX" %}
3665   interface(REG_INTER);
3666 %}
3667 
3668 // Special Registers
3669 operand eBXRegI(xRegI reg) %{
3670   constraint(ALLOC_IN_RC(ebx_reg));
3671   match(reg);
3672   match(rRegI);
3673 
3674   format %{ "EBX" %}
3675   interface(REG_INTER);
3676 %}
3677 
3678 operand eCXRegI(xRegI reg) %{
3679   constraint(ALLOC_IN_RC(ecx_reg));
3680   match(reg);
3681   match(rRegI);
3682 
3683   format %{ "ECX" %}
3684   interface(REG_INTER);
3685 %}
3686 
3687 operand eDXRegI(xRegI reg) %{
3688   constraint(ALLOC_IN_RC(edx_reg));
3689   match(reg);
3690   match(rRegI);
3691 
3692   format %{ "EDX" %}
3693   interface(REG_INTER);
3694 %}
3695 
3696 operand eDIRegI(xRegI reg) %{
3697   constraint(ALLOC_IN_RC(edi_reg));
3698   match(reg);
3699   match(rRegI);
3700 
3701   format %{ "EDI" %}
3702   interface(REG_INTER);
3703 %}
3704 
3705 operand naxRegI() %{
3706   constraint(ALLOC_IN_RC(nax_reg));
3707   match(RegI);
3708   match(eCXRegI);
3709   match(eDXRegI);
3710   match(eSIRegI);
3711   match(eDIRegI);
3712 
3713   format %{ %}
3714   interface(REG_INTER);
3715 %}
3716 
3717 operand nadxRegI() %{
3718   constraint(ALLOC_IN_RC(nadx_reg));
3719   match(RegI);
3720   match(eBXRegI);
3721   match(eCXRegI);
3722   match(eSIRegI);
3723   match(eDIRegI);
3724 
3725   format %{ %}
3726   interface(REG_INTER);
3727 %}
3728 
3729 operand ncxRegI() %{
3730   constraint(ALLOC_IN_RC(ncx_reg));
3731   match(RegI);
3732   match(eAXRegI);
3733   match(eDXRegI);
3734   match(eSIRegI);
3735   match(eDIRegI);
3736 
3737   format %{ %}
3738   interface(REG_INTER);
3739 %}
3740 
3741 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
3742 // //
3743 operand eSIRegI(xRegI reg) %{
3744    constraint(ALLOC_IN_RC(esi_reg));
3745    match(reg);
3746    match(rRegI);
3747 
3748    format %{ "ESI" %}
3749    interface(REG_INTER);
3750 %}
3751 
3752 // Pointer Register
3753 operand anyRegP() %{
3754   constraint(ALLOC_IN_RC(any_reg));
3755   match(RegP);
3756   match(eAXRegP);
3757   match(eBXRegP);
3758   match(eCXRegP);
3759   match(eDIRegP);
3760   match(eRegP);
3761 
3762   format %{ %}
3763   interface(REG_INTER);
3764 %}
3765 
3766 operand eRegP() %{
3767   constraint(ALLOC_IN_RC(int_reg));
3768   match(RegP);
3769   match(eAXRegP);
3770   match(eBXRegP);
3771   match(eCXRegP);
3772   match(eDIRegP);
3773 
3774   format %{ %}
3775   interface(REG_INTER);
3776 %}
3777 
3778 // On windows95, EBP is not safe to use for implicit null tests.
3779 operand eRegP_no_EBP() %{
3780   constraint(ALLOC_IN_RC(int_reg_no_rbp));
3781   match(RegP);
3782   match(eAXRegP);
3783   match(eBXRegP);
3784   match(eCXRegP);
3785   match(eDIRegP);
3786 
3787   op_cost(100);
3788   format %{ %}
3789   interface(REG_INTER);
3790 %}
3791 
3792 operand naxRegP() %{
3793   constraint(ALLOC_IN_RC(nax_reg));
3794   match(RegP);
3795   match(eBXRegP);
3796   match(eDXRegP);
3797   match(eCXRegP);
3798   match(eSIRegP);
3799   match(eDIRegP);
3800 
3801   format %{ %}
3802   interface(REG_INTER);
3803 %}
3804 
3805 operand nabxRegP() %{
3806   constraint(ALLOC_IN_RC(nabx_reg));
3807   match(RegP);
3808   match(eCXRegP);
3809   match(eDXRegP);
3810   match(eSIRegP);
3811   match(eDIRegP);
3812 
3813   format %{ %}
3814   interface(REG_INTER);
3815 %}
3816 
3817 operand pRegP() %{
3818   constraint(ALLOC_IN_RC(p_reg));
3819   match(RegP);
3820   match(eBXRegP);
3821   match(eDXRegP);
3822   match(eSIRegP);
3823   match(eDIRegP);
3824 
3825   format %{ %}
3826   interface(REG_INTER);
3827 %}
3828 
3829 // Special Registers
3830 // Return a pointer value
3831 operand eAXRegP(eRegP reg) %{
3832   constraint(ALLOC_IN_RC(eax_reg));
3833   match(reg);
3834   format %{ "EAX" %}
3835   interface(REG_INTER);
3836 %}
3837 
3838 // Used in AtomicAdd
3839 operand eBXRegP(eRegP reg) %{
3840   constraint(ALLOC_IN_RC(ebx_reg));
3841   match(reg);
3842   format %{ "EBX" %}
3843   interface(REG_INTER);
3844 %}
3845 
3846 // Tail-call (interprocedural jump) to interpreter
3847 operand eCXRegP(eRegP reg) %{
3848   constraint(ALLOC_IN_RC(ecx_reg));
3849   match(reg);
3850   format %{ "ECX" %}
3851   interface(REG_INTER);
3852 %}
3853 
3854 operand eSIRegP(eRegP reg) %{
3855   constraint(ALLOC_IN_RC(esi_reg));
3856   match(reg);
3857   format %{ "ESI" %}
3858   interface(REG_INTER);
3859 %}
3860 
3861 // Used in rep stosw
3862 operand eDIRegP(eRegP reg) %{
3863   constraint(ALLOC_IN_RC(edi_reg));
3864   match(reg);
3865   format %{ "EDI" %}
3866   interface(REG_INTER);
3867 %}
3868 
3869 operand eBPRegP() %{
3870   constraint(ALLOC_IN_RC(ebp_reg));
3871   match(RegP);
3872   format %{ "EBP" %}
3873   interface(REG_INTER);
3874 %}
3875 
3876 operand eRegL() %{
3877   constraint(ALLOC_IN_RC(long_reg));
3878   match(RegL);
3879   match(eADXRegL);
3880 
3881   format %{ %}
3882   interface(REG_INTER);
3883 %}
3884 
3885 operand eADXRegL( eRegL reg ) %{
3886   constraint(ALLOC_IN_RC(eadx_reg));
3887   match(reg);
3888 
3889   format %{ "EDX:EAX" %}
3890   interface(REG_INTER);
3891 %}
3892 
3893 operand eBCXRegL( eRegL reg ) %{
3894   constraint(ALLOC_IN_RC(ebcx_reg));
3895   match(reg);
3896 
3897   format %{ "EBX:ECX" %}
3898   interface(REG_INTER);
3899 %}
3900 
3901 // Special case for integer high multiply
3902 operand eADXRegL_low_only() %{
3903   constraint(ALLOC_IN_RC(eadx_reg));
3904   match(RegL);
3905 
3906   format %{ "EAX" %}
3907   interface(REG_INTER);
3908 %}
3909 
3910 // Flags register, used as output of compare instructions
3911 operand eFlagsReg() %{
3912   constraint(ALLOC_IN_RC(int_flags));
3913   match(RegFlags);
3914 
3915   format %{ "EFLAGS" %}
3916   interface(REG_INTER);
3917 %}
3918 
3919 // Flags register, used as output of FLOATING POINT compare instructions
3920 operand eFlagsRegU() %{
3921   constraint(ALLOC_IN_RC(int_flags));
3922   match(RegFlags);
3923 
3924   format %{ "EFLAGS_U" %}
3925   interface(REG_INTER);
3926 %}
3927 
3928 operand eFlagsRegUCF() %{
3929   constraint(ALLOC_IN_RC(int_flags));
3930   match(RegFlags);
3931   predicate(false);
3932 
3933   format %{ "EFLAGS_U_CF" %}
3934   interface(REG_INTER);
3935 %}
3936 
3937 // Condition Code Register used by long compare
3938 operand flagsReg_long_LTGE() %{
3939   constraint(ALLOC_IN_RC(int_flags));
3940   match(RegFlags);
3941   format %{ "FLAGS_LTGE" %}
3942   interface(REG_INTER);
3943 %}
3944 operand flagsReg_long_EQNE() %{
3945   constraint(ALLOC_IN_RC(int_flags));
3946   match(RegFlags);
3947   format %{ "FLAGS_EQNE" %}
3948   interface(REG_INTER);
3949 %}
3950 operand flagsReg_long_LEGT() %{
3951   constraint(ALLOC_IN_RC(int_flags));
3952   match(RegFlags);
3953   format %{ "FLAGS_LEGT" %}
3954   interface(REG_INTER);
3955 %}
3956 
3957 // Float register operands
3958 operand regDPR() %{
3959   predicate( UseSSE < 2 );
3960   constraint(ALLOC_IN_RC(fp_dbl_reg));
3961   match(RegD);
3962   match(regDPR1);
3963   match(regDPR2);
3964   format %{ %}
3965   interface(REG_INTER);
3966 %}
3967 
3968 operand regDPR1(regDPR reg) %{
3969   predicate( UseSSE < 2 );
3970   constraint(ALLOC_IN_RC(fp_dbl_reg0));
3971   match(reg);
3972   format %{ "FPR1" %}
3973   interface(REG_INTER);
3974 %}
3975 
3976 operand regDPR2(regDPR reg) %{
3977   predicate( UseSSE < 2 );
3978   constraint(ALLOC_IN_RC(fp_dbl_reg1));
3979   match(reg);
3980   format %{ "FPR2" %}
3981   interface(REG_INTER);
3982 %}
3983 
3984 operand regnotDPR1(regDPR reg) %{
3985   predicate( UseSSE < 2 );
3986   constraint(ALLOC_IN_RC(fp_dbl_notreg0));
3987   match(reg);
3988   format %{ %}
3989   interface(REG_INTER);
3990 %}
3991 
3992 // Float register operands
3993 operand regFPR() %{
3994   predicate( UseSSE < 2 );
3995   constraint(ALLOC_IN_RC(fp_flt_reg));
3996   match(RegF);
3997   match(regFPR1);
3998   format %{ %}
3999   interface(REG_INTER);
4000 %}
4001 
4002 // Float register operands
4003 operand regFPR1(regFPR reg) %{
4004   predicate( UseSSE < 2 );
4005   constraint(ALLOC_IN_RC(fp_flt_reg0));
4006   match(reg);
4007   format %{ "FPR1" %}
4008   interface(REG_INTER);
4009 %}
4010 
4011 // XMM Float register operands
4012 operand regF() %{
4013   predicate( UseSSE>=1 );
4014   constraint(ALLOC_IN_RC(float_reg));
4015   match(RegF);
4016   format %{ %}
4017   interface(REG_INTER);
4018 %}
4019 
4020 // XMM Double register operands
4021 operand regD() %{
4022   predicate( UseSSE>=2 );
4023   constraint(ALLOC_IN_RC(double_reg));
4024   match(RegD);
4025   format %{ %}
4026   interface(REG_INTER);
4027 %}
4028 
4029 
4030 //----------Memory Operands----------------------------------------------------
4031 // Direct Memory Operand
4032 operand direct(immP addr) %{
4033   match(addr);
4034 
4035   format %{ "[$addr]" %}
4036   interface(MEMORY_INTER) %{
4037     base(0xFFFFFFFF);
4038     index(0x4);
4039     scale(0x0);
4040     disp($addr);
4041   %}
4042 %}
4043 
4044 // Indirect Memory Operand
4045 operand indirect(eRegP reg) %{
4046   constraint(ALLOC_IN_RC(int_reg));
4047   match(reg);
4048 
4049   format %{ "[$reg]" %}
4050   interface(MEMORY_INTER) %{
4051     base($reg);
4052     index(0x4);
4053     scale(0x0);
4054     disp(0x0);
4055   %}
4056 %}
4057 
4058 // Indirect Memory Plus Short Offset Operand
4059 operand indOffset8(eRegP reg, immI8 off) %{
4060   match(AddP reg off);
4061 
4062   format %{ "[$reg + $off]" %}
4063   interface(MEMORY_INTER) %{
4064     base($reg);
4065     index(0x4);
4066     scale(0x0);
4067     disp($off);
4068   %}
4069 %}
4070 
4071 // Indirect Memory Plus Long Offset Operand
4072 operand indOffset32(eRegP reg, immI off) %{
4073   match(AddP reg off);
4074 
4075   format %{ "[$reg + $off]" %}
4076   interface(MEMORY_INTER) %{
4077     base($reg);
4078     index(0x4);
4079     scale(0x0);
4080     disp($off);
4081   %}
4082 %}
4083 
4084 // Indirect Memory Plus Long Offset Operand
4085 operand indOffset32X(rRegI reg, immP off) %{
4086   match(AddP off reg);
4087 
4088   format %{ "[$reg + $off]" %}
4089   interface(MEMORY_INTER) %{
4090     base($reg);
4091     index(0x4);
4092     scale(0x0);
4093     disp($off);
4094   %}
4095 %}
4096 
4097 // Indirect Memory Plus Index Register Plus Offset Operand
4098 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4099   match(AddP (AddP reg ireg) off);
4100 
4101   op_cost(10);
4102   format %{"[$reg + $off + $ireg]" %}
4103   interface(MEMORY_INTER) %{
4104     base($reg);
4105     index($ireg);
4106     scale(0x0);
4107     disp($off);
4108   %}
4109 %}
4110 
4111 // Indirect Memory Plus Index Register Plus Offset Operand
4112 operand indIndex(eRegP reg, rRegI ireg) %{
4113   match(AddP reg ireg);
4114 
4115   op_cost(10);
4116   format %{"[$reg + $ireg]" %}
4117   interface(MEMORY_INTER) %{
4118     base($reg);
4119     index($ireg);
4120     scale(0x0);
4121     disp(0x0);
4122   %}
4123 %}
4124 
4125 // // -------------------------------------------------------------------------
4126 // // 486 architecture doesn't support "scale * index + offset" with out a base
4127 // // -------------------------------------------------------------------------
4128 // // Scaled Memory Operands
4129 // // Indirect Memory Times Scale Plus Offset Operand
4130 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4131 //   match(AddP off (LShiftI ireg scale));
4132 //
4133 //   op_cost(10);
4134 //   format %{"[$off + $ireg << $scale]" %}
4135 //   interface(MEMORY_INTER) %{
4136 //     base(0x4);
4137 //     index($ireg);
4138 //     scale($scale);
4139 //     disp($off);
4140 //   %}
4141 // %}
4142 
4143 // Indirect Memory Times Scale Plus Index Register
4144 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4145   match(AddP reg (LShiftI ireg scale));
4146 
4147   op_cost(10);
4148   format %{"[$reg + $ireg << $scale]" %}
4149   interface(MEMORY_INTER) %{
4150     base($reg);
4151     index($ireg);
4152     scale($scale);
4153     disp(0x0);
4154   %}
4155 %}
4156 
4157 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4158 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4159   match(AddP (AddP reg (LShiftI ireg scale)) off);
4160 
4161   op_cost(10);
4162   format %{"[$reg + $off + $ireg << $scale]" %}
4163   interface(MEMORY_INTER) %{
4164     base($reg);
4165     index($ireg);
4166     scale($scale);
4167     disp($off);
4168   %}
4169 %}
4170 
4171 //----------Load Long Memory Operands------------------------------------------
4172 // The load-long idiom will use it's address expression again after loading
4173 // the first word of the long.  If the load-long destination overlaps with
4174 // registers used in the addressing expression, the 2nd half will be loaded
4175 // from a clobbered address.  Fix this by requiring that load-long use
4176 // address registers that do not overlap with the load-long target.
4177 
4178 // load-long support
4179 operand load_long_RegP() %{
4180   constraint(ALLOC_IN_RC(esi_reg));
4181   match(RegP);
4182   match(eSIRegP);
4183   op_cost(100);
4184   format %{  %}
4185   interface(REG_INTER);
4186 %}
4187 
4188 // Indirect Memory Operand Long
4189 operand load_long_indirect(load_long_RegP reg) %{
4190   constraint(ALLOC_IN_RC(esi_reg));
4191   match(reg);
4192 
4193   format %{ "[$reg]" %}
4194   interface(MEMORY_INTER) %{
4195     base($reg);
4196     index(0x4);
4197     scale(0x0);
4198     disp(0x0);
4199   %}
4200 %}
4201 
4202 // Indirect Memory Plus Long Offset Operand
4203 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4204   match(AddP reg off);
4205 
4206   format %{ "[$reg + $off]" %}
4207   interface(MEMORY_INTER) %{
4208     base($reg);
4209     index(0x4);
4210     scale(0x0);
4211     disp($off);
4212   %}
4213 %}
4214 
4215 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4216 
4217 
4218 //----------Special Memory Operands--------------------------------------------
4219 // Stack Slot Operand - This operand is used for loading and storing temporary
4220 //                      values on the stack where a match requires a value to
4221 //                      flow through memory.
4222 operand stackSlotP(sRegP reg) %{
4223   constraint(ALLOC_IN_RC(stack_slots));
4224   // No match rule because this operand is only generated in matching
4225   format %{ "[$reg]" %}
4226   interface(MEMORY_INTER) %{
4227     base(0x4);   // ESP
4228     index(0x4);  // No Index
4229     scale(0x0);  // No Scale
4230     disp($reg);  // Stack Offset
4231   %}
4232 %}
4233 
4234 operand stackSlotI(sRegI reg) %{
4235   constraint(ALLOC_IN_RC(stack_slots));
4236   // No match rule because this operand is only generated in matching
4237   format %{ "[$reg]" %}
4238   interface(MEMORY_INTER) %{
4239     base(0x4);   // ESP
4240     index(0x4);  // No Index
4241     scale(0x0);  // No Scale
4242     disp($reg);  // Stack Offset
4243   %}
4244 %}
4245 
4246 operand stackSlotF(sRegF reg) %{
4247   constraint(ALLOC_IN_RC(stack_slots));
4248   // No match rule because this operand is only generated in matching
4249   format %{ "[$reg]" %}
4250   interface(MEMORY_INTER) %{
4251     base(0x4);   // ESP
4252     index(0x4);  // No Index
4253     scale(0x0);  // No Scale
4254     disp($reg);  // Stack Offset
4255   %}
4256 %}
4257 
4258 operand stackSlotD(sRegD reg) %{
4259   constraint(ALLOC_IN_RC(stack_slots));
4260   // No match rule because this operand is only generated in matching
4261   format %{ "[$reg]" %}
4262   interface(MEMORY_INTER) %{
4263     base(0x4);   // ESP
4264     index(0x4);  // No Index
4265     scale(0x0);  // No Scale
4266     disp($reg);  // Stack Offset
4267   %}
4268 %}
4269 
4270 operand stackSlotL(sRegL reg) %{
4271   constraint(ALLOC_IN_RC(stack_slots));
4272   // No match rule because this operand is only generated in matching
4273   format %{ "[$reg]" %}
4274   interface(MEMORY_INTER) %{
4275     base(0x4);   // ESP
4276     index(0x4);  // No Index
4277     scale(0x0);  // No Scale
4278     disp($reg);  // Stack Offset
4279   %}
4280 %}
4281 
4282 //----------Memory Operands - Win95 Implicit Null Variants----------------
4283 // Indirect Memory Operand
4284 operand indirect_win95_safe(eRegP_no_EBP reg)
4285 %{
4286   constraint(ALLOC_IN_RC(int_reg));
4287   match(reg);
4288 
4289   op_cost(100);
4290   format %{ "[$reg]" %}
4291   interface(MEMORY_INTER) %{
4292     base($reg);
4293     index(0x4);
4294     scale(0x0);
4295     disp(0x0);
4296   %}
4297 %}
4298 
4299 // Indirect Memory Plus Short Offset Operand
4300 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4301 %{
4302   match(AddP reg off);
4303 
4304   op_cost(100);
4305   format %{ "[$reg + $off]" %}
4306   interface(MEMORY_INTER) %{
4307     base($reg);
4308     index(0x4);
4309     scale(0x0);
4310     disp($off);
4311   %}
4312 %}
4313 
4314 // Indirect Memory Plus Long Offset Operand
4315 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4316 %{
4317   match(AddP reg off);
4318 
4319   op_cost(100);
4320   format %{ "[$reg + $off]" %}
4321   interface(MEMORY_INTER) %{
4322     base($reg);
4323     index(0x4);
4324     scale(0x0);
4325     disp($off);
4326   %}
4327 %}
4328 
4329 // Indirect Memory Plus Index Register Plus Offset Operand
4330 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4331 %{
4332   match(AddP (AddP reg ireg) off);
4333 
4334   op_cost(100);
4335   format %{"[$reg + $off + $ireg]" %}
4336   interface(MEMORY_INTER) %{
4337     base($reg);
4338     index($ireg);
4339     scale(0x0);
4340     disp($off);
4341   %}
4342 %}
4343 
4344 // Indirect Memory Times Scale Plus Index Register
4345 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4346 %{
4347   match(AddP reg (LShiftI ireg scale));
4348 
4349   op_cost(100);
4350   format %{"[$reg + $ireg << $scale]" %}
4351   interface(MEMORY_INTER) %{
4352     base($reg);
4353     index($ireg);
4354     scale($scale);
4355     disp(0x0);
4356   %}
4357 %}
4358 
4359 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4360 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4361 %{
4362   match(AddP (AddP reg (LShiftI ireg scale)) off);
4363 
4364   op_cost(100);
4365   format %{"[$reg + $off + $ireg << $scale]" %}
4366   interface(MEMORY_INTER) %{
4367     base($reg);
4368     index($ireg);
4369     scale($scale);
4370     disp($off);
4371   %}
4372 %}
4373 
4374 //----------Conditional Branch Operands----------------------------------------
4375 // Comparison Op  - This is the operation of the comparison, and is limited to
4376 //                  the following set of codes:
4377 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4378 //
4379 // Other attributes of the comparison, such as unsignedness, are specified
4380 // by the comparison instruction that sets a condition code flags register.
4381 // That result is represented by a flags operand whose subtype is appropriate
4382 // to the unsignedness (etc.) of the comparison.
4383 //
4384 // Later, the instruction which matches both the Comparison Op (a Bool) and
4385 // the flags (produced by the Cmp) specifies the coding of the comparison op
4386 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4387 
4388 // Comparision Code
4389 operand cmpOp() %{
4390   match(Bool);
4391 
4392   format %{ "" %}
4393   interface(COND_INTER) %{
4394     equal(0x4, "e");
4395     not_equal(0x5, "ne");
4396     less(0xC, "l");
4397     greater_equal(0xD, "ge");
4398     less_equal(0xE, "le");
4399     greater(0xF, "g");
4400     overflow(0x0, "o");
4401     no_overflow(0x1, "no");
4402   %}
4403 %}
4404 
4405 // Comparison Code, unsigned compare.  Used by FP also, with
4406 // C2 (unordered) turned into GT or LT already.  The other bits
4407 // C0 and C3 are turned into Carry & Zero flags.
4408 operand cmpOpU() %{
4409   match(Bool);
4410 
4411   format %{ "" %}
4412   interface(COND_INTER) %{
4413     equal(0x4, "e");
4414     not_equal(0x5, "ne");
4415     less(0x2, "b");
4416     greater_equal(0x3, "nb");
4417     less_equal(0x6, "be");
4418     greater(0x7, "nbe");
4419     overflow(0x0, "o");
4420     no_overflow(0x1, "no");
4421   %}
4422 %}
4423 
4424 // Floating comparisons that don't require any fixup for the unordered case
4425 operand cmpOpUCF() %{
4426   match(Bool);
4427   predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4428             n->as_Bool()->_test._test == BoolTest::ge ||
4429             n->as_Bool()->_test._test == BoolTest::le ||
4430             n->as_Bool()->_test._test == BoolTest::gt);
4431   format %{ "" %}
4432   interface(COND_INTER) %{
4433     equal(0x4, "e");
4434     not_equal(0x5, "ne");
4435     less(0x2, "b");
4436     greater_equal(0x3, "nb");
4437     less_equal(0x6, "be");
4438     greater(0x7, "nbe");
4439     overflow(0x0, "o");
4440     no_overflow(0x1, "no");
4441   %}
4442 %}
4443 
4444 
4445 // Floating comparisons that can be fixed up with extra conditional jumps
4446 operand cmpOpUCF2() %{
4447   match(Bool);
4448   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4449             n->as_Bool()->_test._test == BoolTest::eq);
4450   format %{ "" %}
4451   interface(COND_INTER) %{
4452     equal(0x4, "e");
4453     not_equal(0x5, "ne");
4454     less(0x2, "b");
4455     greater_equal(0x3, "nb");
4456     less_equal(0x6, "be");
4457     greater(0x7, "nbe");
4458     overflow(0x0, "o");
4459     no_overflow(0x1, "no");
4460   %}
4461 %}
4462 
4463 // Comparison Code for FP conditional move
4464 operand cmpOp_fcmov() %{
4465   match(Bool);
4466 
4467   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4468             n->as_Bool()->_test._test != BoolTest::no_overflow);
4469   format %{ "" %}
4470   interface(COND_INTER) %{
4471     equal        (0x0C8);
4472     not_equal    (0x1C8);
4473     less         (0x0C0);
4474     greater_equal(0x1C0);
4475     less_equal   (0x0D0);
4476     greater      (0x1D0);
4477     overflow(0x0, "o"); // not really supported by the instruction
4478     no_overflow(0x1, "no"); // not really supported by the instruction
4479   %}
4480 %}
4481 
4482 // Comparision Code used in long compares
4483 operand cmpOp_commute() %{
4484   match(Bool);
4485 
4486   format %{ "" %}
4487   interface(COND_INTER) %{
4488     equal(0x4, "e");
4489     not_equal(0x5, "ne");
4490     less(0xF, "g");
4491     greater_equal(0xE, "le");
4492     less_equal(0xD, "ge");
4493     greater(0xC, "l");
4494     overflow(0x0, "o");
4495     no_overflow(0x1, "no");
4496   %}
4497 %}
4498 
4499 //----------OPERAND CLASSES----------------------------------------------------
4500 // Operand Classes are groups of operands that are used as to simplify
4501 // instruction definitions by not requiring the AD writer to specify separate
4502 // instructions for every form of operand when the instruction accepts
4503 // multiple operand types with the same basic encoding and format.  The classic
4504 // case of this is memory operands.
4505 
4506 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
4507                indIndex, indIndexScale, indIndexScaleOffset);
4508 
4509 // Long memory operations are encoded in 2 instructions and a +4 offset.
4510 // This means some kind of offset is always required and you cannot use
4511 // an oop as the offset (done when working on static globals).
4512 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
4513                     indIndex, indIndexScale, indIndexScaleOffset);
4514 
4515 
4516 //----------PIPELINE-----------------------------------------------------------
4517 // Rules which define the behavior of the target architectures pipeline.
4518 pipeline %{
4519 
4520 //----------ATTRIBUTES---------------------------------------------------------
4521 attributes %{
4522   variable_size_instructions;        // Fixed size instructions
4523   max_instructions_per_bundle = 3;   // Up to 3 instructions per bundle
4524   instruction_unit_size = 1;         // An instruction is 1 bytes long
4525   instruction_fetch_unit_size = 16;  // The processor fetches one line
4526   instruction_fetch_units = 1;       // of 16 bytes
4527 
4528   // List of nop instructions
4529   nops( MachNop );
4530 %}
4531 
4532 //----------RESOURCES----------------------------------------------------------
4533 // Resources are the functional units available to the machine
4534 
4535 // Generic P2/P3 pipeline
4536 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4537 // 3 instructions decoded per cycle.
4538 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4539 // 2 ALU op, only ALU0 handles mul/div instructions.
4540 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4541            MS0, MS1, MEM = MS0 | MS1,
4542            BR, FPU,
4543            ALU0, ALU1, ALU = ALU0 | ALU1 );
4544 
4545 //----------PIPELINE DESCRIPTION-----------------------------------------------
4546 // Pipeline Description specifies the stages in the machine's pipeline
4547 
4548 // Generic P2/P3 pipeline
4549 pipe_desc(S0, S1, S2, S3, S4, S5);
4550 
4551 //----------PIPELINE CLASSES---------------------------------------------------
4552 // Pipeline Classes describe the stages in which input and output are
4553 // referenced by the hardware pipeline.
4554 
4555 // Naming convention: ialu or fpu
4556 // Then: _reg
4557 // Then: _reg if there is a 2nd register
4558 // Then: _long if it's a pair of instructions implementing a long
4559 // Then: _fat if it requires the big decoder
4560 //   Or: _mem if it requires the big decoder and a memory unit.
4561 
4562 // Integer ALU reg operation
4563 pipe_class ialu_reg(rRegI dst) %{
4564     single_instruction;
4565     dst    : S4(write);
4566     dst    : S3(read);
4567     DECODE : S0;        // any decoder
4568     ALU    : S3;        // any alu
4569 %}
4570 
4571 // Long ALU reg operation
4572 pipe_class ialu_reg_long(eRegL dst) %{
4573     instruction_count(2);
4574     dst    : S4(write);
4575     dst    : S3(read);
4576     DECODE : S0(2);     // any 2 decoders
4577     ALU    : S3(2);     // both alus
4578 %}
4579 
4580 // Integer ALU reg operation using big decoder
4581 pipe_class ialu_reg_fat(rRegI dst) %{
4582     single_instruction;
4583     dst    : S4(write);
4584     dst    : S3(read);
4585     D0     : S0;        // big decoder only
4586     ALU    : S3;        // any alu
4587 %}
4588 
4589 // Long ALU reg operation using big decoder
4590 pipe_class ialu_reg_long_fat(eRegL dst) %{
4591     instruction_count(2);
4592     dst    : S4(write);
4593     dst    : S3(read);
4594     D0     : S0(2);     // big decoder only; twice
4595     ALU    : S3(2);     // any 2 alus
4596 %}
4597 
4598 // Integer ALU reg-reg operation
4599 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
4600     single_instruction;
4601     dst    : S4(write);
4602     src    : S3(read);
4603     DECODE : S0;        // any decoder
4604     ALU    : S3;        // any alu
4605 %}
4606 
4607 // Long ALU reg-reg operation
4608 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
4609     instruction_count(2);
4610     dst    : S4(write);
4611     src    : S3(read);
4612     DECODE : S0(2);     // any 2 decoders
4613     ALU    : S3(2);     // both alus
4614 %}
4615 
4616 // Integer ALU reg-reg operation
4617 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
4618     single_instruction;
4619     dst    : S4(write);
4620     src    : S3(read);
4621     D0     : S0;        // big decoder only
4622     ALU    : S3;        // any alu
4623 %}
4624 
4625 // Long ALU reg-reg operation
4626 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
4627     instruction_count(2);
4628     dst    : S4(write);
4629     src    : S3(read);
4630     D0     : S0(2);     // big decoder only; twice
4631     ALU    : S3(2);     // both alus
4632 %}
4633 
4634 // Integer ALU reg-mem operation
4635 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
4636     single_instruction;
4637     dst    : S5(write);
4638     mem    : S3(read);
4639     D0     : S0;        // big decoder only
4640     ALU    : S4;        // any alu
4641     MEM    : S3;        // any mem
4642 %}
4643 
4644 // Long ALU reg-mem operation
4645 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
4646     instruction_count(2);
4647     dst    : S5(write);
4648     mem    : S3(read);
4649     D0     : S0(2);     // big decoder only; twice
4650     ALU    : S4(2);     // any 2 alus
4651     MEM    : S3(2);     // both mems
4652 %}
4653 
4654 // Integer mem operation (prefetch)
4655 pipe_class ialu_mem(memory mem)
4656 %{
4657     single_instruction;
4658     mem    : S3(read);
4659     D0     : S0;        // big decoder only
4660     MEM    : S3;        // any mem
4661 %}
4662 
4663 // Integer Store to Memory
4664 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
4665     single_instruction;
4666     mem    : S3(read);
4667     src    : S5(read);
4668     D0     : S0;        // big decoder only
4669     ALU    : S4;        // any alu
4670     MEM    : S3;
4671 %}
4672 
4673 // Long Store to Memory
4674 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
4675     instruction_count(2);
4676     mem    : S3(read);
4677     src    : S5(read);
4678     D0     : S0(2);     // big decoder only; twice
4679     ALU    : S4(2);     // any 2 alus
4680     MEM    : S3(2);     // Both mems
4681 %}
4682 
4683 // Integer Store to Memory
4684 pipe_class ialu_mem_imm(memory mem) %{
4685     single_instruction;
4686     mem    : S3(read);
4687     D0     : S0;        // big decoder only
4688     ALU    : S4;        // any alu
4689     MEM    : S3;
4690 %}
4691 
4692 // Integer ALU0 reg-reg operation
4693 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
4694     single_instruction;
4695     dst    : S4(write);
4696     src    : S3(read);
4697     D0     : S0;        // Big decoder only
4698     ALU0   : S3;        // only alu0
4699 %}
4700 
4701 // Integer ALU0 reg-mem operation
4702 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
4703     single_instruction;
4704     dst    : S5(write);
4705     mem    : S3(read);
4706     D0     : S0;        // big decoder only
4707     ALU0   : S4;        // ALU0 only
4708     MEM    : S3;        // any mem
4709 %}
4710 
4711 // Integer ALU reg-reg operation
4712 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
4713     single_instruction;
4714     cr     : S4(write);
4715     src1   : S3(read);
4716     src2   : S3(read);
4717     DECODE : S0;        // any decoder
4718     ALU    : S3;        // any alu
4719 %}
4720 
4721 // Integer ALU reg-imm operation
4722 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
4723     single_instruction;
4724     cr     : S4(write);
4725     src1   : S3(read);
4726     DECODE : S0;        // any decoder
4727     ALU    : S3;        // any alu
4728 %}
4729 
4730 // Integer ALU reg-mem operation
4731 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
4732     single_instruction;
4733     cr     : S4(write);
4734     src1   : S3(read);
4735     src2   : S3(read);
4736     D0     : S0;        // big decoder only
4737     ALU    : S4;        // any alu
4738     MEM    : S3;
4739 %}
4740 
4741 // Conditional move reg-reg
4742 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
4743     instruction_count(4);
4744     y      : S4(read);
4745     q      : S3(read);
4746     p      : S3(read);
4747     DECODE : S0(4);     // any decoder
4748 %}
4749 
4750 // Conditional move reg-reg
4751 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
4752     single_instruction;
4753     dst    : S4(write);
4754     src    : S3(read);
4755     cr     : S3(read);
4756     DECODE : S0;        // any decoder
4757 %}
4758 
4759 // Conditional move reg-mem
4760 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
4761     single_instruction;
4762     dst    : S4(write);
4763     src    : S3(read);
4764     cr     : S3(read);
4765     DECODE : S0;        // any decoder
4766     MEM    : S3;
4767 %}
4768 
4769 // Conditional move reg-reg long
4770 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
4771     single_instruction;
4772     dst    : S4(write);
4773     src    : S3(read);
4774     cr     : S3(read);
4775     DECODE : S0(2);     // any 2 decoders
4776 %}
4777 
4778 // Conditional move double reg-reg
4779 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
4780     single_instruction;
4781     dst    : S4(write);
4782     src    : S3(read);
4783     cr     : S3(read);
4784     DECODE : S0;        // any decoder
4785 %}
4786 
4787 // Float reg-reg operation
4788 pipe_class fpu_reg(regDPR dst) %{
4789     instruction_count(2);
4790     dst    : S3(read);
4791     DECODE : S0(2);     // any 2 decoders
4792     FPU    : S3;
4793 %}
4794 
4795 // Float reg-reg operation
4796 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
4797     instruction_count(2);
4798     dst    : S4(write);
4799     src    : S3(read);
4800     DECODE : S0(2);     // any 2 decoders
4801     FPU    : S3;
4802 %}
4803 
4804 // Float reg-reg operation
4805 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
4806     instruction_count(3);
4807     dst    : S4(write);
4808     src1   : S3(read);
4809     src2   : S3(read);
4810     DECODE : S0(3);     // any 3 decoders
4811     FPU    : S3(2);
4812 %}
4813 
4814 // Float reg-reg operation
4815 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
4816     instruction_count(4);
4817     dst    : S4(write);
4818     src1   : S3(read);
4819     src2   : S3(read);
4820     src3   : S3(read);
4821     DECODE : S0(4);     // any 3 decoders
4822     FPU    : S3(2);
4823 %}
4824 
4825 // Float reg-reg operation
4826 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
4827     instruction_count(4);
4828     dst    : S4(write);
4829     src1   : S3(read);
4830     src2   : S3(read);
4831     src3   : S3(read);
4832     DECODE : S1(3);     // any 3 decoders
4833     D0     : S0;        // Big decoder only
4834     FPU    : S3(2);
4835     MEM    : S3;
4836 %}
4837 
4838 // Float reg-mem operation
4839 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
4840     instruction_count(2);
4841     dst    : S5(write);
4842     mem    : S3(read);
4843     D0     : S0;        // big decoder only
4844     DECODE : S1;        // any decoder for FPU POP
4845     FPU    : S4;
4846     MEM    : S3;        // any mem
4847 %}
4848 
4849 // Float reg-mem operation
4850 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
4851     instruction_count(3);
4852     dst    : S5(write);
4853     src1   : S3(read);
4854     mem    : S3(read);
4855     D0     : S0;        // big decoder only
4856     DECODE : S1(2);     // any decoder for FPU POP
4857     FPU    : S4;
4858     MEM    : S3;        // any mem
4859 %}
4860 
4861 // Float mem-reg operation
4862 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
4863     instruction_count(2);
4864     src    : S5(read);
4865     mem    : S3(read);
4866     DECODE : S0;        // any decoder for FPU PUSH
4867     D0     : S1;        // big decoder only
4868     FPU    : S4;
4869     MEM    : S3;        // any mem
4870 %}
4871 
4872 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
4873     instruction_count(3);
4874     src1   : S3(read);
4875     src2   : S3(read);
4876     mem    : S3(read);
4877     DECODE : S0(2);     // any decoder for FPU PUSH
4878     D0     : S1;        // big decoder only
4879     FPU    : S4;
4880     MEM    : S3;        // any mem
4881 %}
4882 
4883 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
4884     instruction_count(3);
4885     src1   : S3(read);
4886     src2   : S3(read);
4887     mem    : S4(read);
4888     DECODE : S0;        // any decoder for FPU PUSH
4889     D0     : S0(2);     // big decoder only
4890     FPU    : S4;
4891     MEM    : S3(2);     // any mem
4892 %}
4893 
4894 pipe_class fpu_mem_mem(memory dst, memory src1) %{
4895     instruction_count(2);
4896     src1   : S3(read);
4897     dst    : S4(read);
4898     D0     : S0(2);     // big decoder only
4899     MEM    : S3(2);     // any mem
4900 %}
4901 
4902 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
4903     instruction_count(3);
4904     src1   : S3(read);
4905     src2   : S3(read);
4906     dst    : S4(read);
4907     D0     : S0(3);     // big decoder only
4908     FPU    : S4;
4909     MEM    : S3(3);     // any mem
4910 %}
4911 
4912 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
4913     instruction_count(3);
4914     src1   : S4(read);
4915     mem    : S4(read);
4916     DECODE : S0;        // any decoder for FPU PUSH
4917     D0     : S0(2);     // big decoder only
4918     FPU    : S4;
4919     MEM    : S3(2);     // any mem
4920 %}
4921 
4922 // Float load constant
4923 pipe_class fpu_reg_con(regDPR dst) %{
4924     instruction_count(2);
4925     dst    : S5(write);
4926     D0     : S0;        // big decoder only for the load
4927     DECODE : S1;        // any decoder for FPU POP
4928     FPU    : S4;
4929     MEM    : S3;        // any mem
4930 %}
4931 
4932 // Float load constant
4933 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
4934     instruction_count(3);
4935     dst    : S5(write);
4936     src    : S3(read);
4937     D0     : S0;        // big decoder only for the load
4938     DECODE : S1(2);     // any decoder for FPU POP
4939     FPU    : S4;
4940     MEM    : S3;        // any mem
4941 %}
4942 
4943 // UnConditional branch
4944 pipe_class pipe_jmp( label labl ) %{
4945     single_instruction;
4946     BR   : S3;
4947 %}
4948 
4949 // Conditional branch
4950 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
4951     single_instruction;
4952     cr    : S1(read);
4953     BR    : S3;
4954 %}
4955 
4956 // Allocation idiom
4957 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
4958     instruction_count(1); force_serialization;
4959     fixed_latency(6);
4960     heap_ptr : S3(read);
4961     DECODE   : S0(3);
4962     D0       : S2;
4963     MEM      : S3;
4964     ALU      : S3(2);
4965     dst      : S5(write);
4966     BR       : S5;
4967 %}
4968 
4969 // Generic big/slow expanded idiom
4970 pipe_class pipe_slow(  ) %{
4971     instruction_count(10); multiple_bundles; force_serialization;
4972     fixed_latency(100);
4973     D0  : S0(2);
4974     MEM : S3(2);
4975 %}
4976 
4977 // The real do-nothing guy
4978 pipe_class empty( ) %{
4979     instruction_count(0);
4980 %}
4981 
4982 // Define the class for the Nop node
4983 define %{
4984    MachNop = empty;
4985 %}
4986 
4987 %}
4988 
4989 //----------INSTRUCTIONS-------------------------------------------------------
4990 //
4991 // match      -- States which machine-independent subtree may be replaced
4992 //               by this instruction.
4993 // ins_cost   -- The estimated cost of this instruction is used by instruction
4994 //               selection to identify a minimum cost tree of machine
4995 //               instructions that matches a tree of machine-independent
4996 //               instructions.
4997 // format     -- A string providing the disassembly for this instruction.
4998 //               The value of an instruction's operand may be inserted
4999 //               by referring to it with a '$' prefix.
5000 // opcode     -- Three instruction opcodes may be provided.  These are referred
5001 //               to within an encode class as $primary, $secondary, and $tertiary
5002 //               respectively.  The primary opcode is commonly used to
5003 //               indicate the type of machine instruction, while secondary
5004 //               and tertiary are often used for prefix options or addressing
5005 //               modes.
5006 // ins_encode -- A list of encode classes with parameters. The encode class
5007 //               name must have been defined in an 'enc_class' specification
5008 //               in the encode section of the architecture description.
5009 
5010 //----------BSWAP-Instruction--------------------------------------------------
5011 instruct bytes_reverse_int(rRegI dst) %{
5012   match(Set dst (ReverseBytesI dst));
5013 
5014   format %{ "BSWAP  $dst" %}
5015   opcode(0x0F, 0xC8);
5016   ins_encode( OpcP, OpcSReg(dst) );
5017   ins_pipe( ialu_reg );
5018 %}
5019 
5020 instruct bytes_reverse_long(eRegL dst) %{
5021   match(Set dst (ReverseBytesL dst));
5022 
5023   format %{ "BSWAP  $dst.lo\n\t"
5024             "BSWAP  $dst.hi\n\t"
5025             "XCHG   $dst.lo $dst.hi" %}
5026 
5027   ins_cost(125);
5028   ins_encode( bswap_long_bytes(dst) );
5029   ins_pipe( ialu_reg_reg);
5030 %}
5031 
5032 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5033   match(Set dst (ReverseBytesUS dst));
5034   effect(KILL cr);
5035 
5036   format %{ "BSWAP  $dst\n\t" 
5037             "SHR    $dst,16\n\t" %}
5038   ins_encode %{
5039     __ bswapl($dst$$Register);
5040     __ shrl($dst$$Register, 16); 
5041   %}
5042   ins_pipe( ialu_reg );
5043 %}
5044 
5045 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5046   match(Set dst (ReverseBytesS dst));
5047   effect(KILL cr);
5048 
5049   format %{ "BSWAP  $dst\n\t" 
5050             "SAR    $dst,16\n\t" %}
5051   ins_encode %{
5052     __ bswapl($dst$$Register);
5053     __ sarl($dst$$Register, 16); 
5054   %}
5055   ins_pipe( ialu_reg );
5056 %}
5057 
5058 
5059 //---------- Zeros Count Instructions ------------------------------------------
5060 
5061 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5062   predicate(UseCountLeadingZerosInstruction);
5063   match(Set dst (CountLeadingZerosI src));
5064   effect(KILL cr);
5065 
5066   format %{ "LZCNT  $dst, $src\t# count leading zeros (int)" %}
5067   ins_encode %{
5068     __ lzcntl($dst$$Register, $src$$Register);
5069   %}
5070   ins_pipe(ialu_reg);
5071 %}
5072 
5073 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5074   predicate(!UseCountLeadingZerosInstruction);
5075   match(Set dst (CountLeadingZerosI src));
5076   effect(KILL cr);
5077 
5078   format %{ "BSR    $dst, $src\t# count leading zeros (int)\n\t"
5079             "JNZ    skip\n\t"
5080             "MOV    $dst, -1\n"
5081       "skip:\n\t"
5082             "NEG    $dst\n\t"
5083             "ADD    $dst, 31" %}
5084   ins_encode %{
5085     Register Rdst = $dst$$Register;
5086     Register Rsrc = $src$$Register;
5087     Label skip;
5088     __ bsrl(Rdst, Rsrc);
5089     __ jccb(Assembler::notZero, skip);
5090     __ movl(Rdst, -1);
5091     __ bind(skip);
5092     __ negl(Rdst);
5093     __ addl(Rdst, BitsPerInt - 1);
5094   %}
5095   ins_pipe(ialu_reg);
5096 %}
5097 
5098 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5099   predicate(UseCountLeadingZerosInstruction);
5100   match(Set dst (CountLeadingZerosL src));
5101   effect(TEMP dst, KILL cr);
5102 
5103   format %{ "LZCNT  $dst, $src.hi\t# count leading zeros (long)\n\t"
5104             "JNC    done\n\t"
5105             "LZCNT  $dst, $src.lo\n\t"
5106             "ADD    $dst, 32\n"
5107       "done:" %}
5108   ins_encode %{
5109     Register Rdst = $dst$$Register;
5110     Register Rsrc = $src$$Register;
5111     Label done;
5112     __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5113     __ jccb(Assembler::carryClear, done);
5114     __ lzcntl(Rdst, Rsrc);
5115     __ addl(Rdst, BitsPerInt);
5116     __ bind(done);
5117   %}
5118   ins_pipe(ialu_reg);
5119 %}
5120 
5121 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5122   predicate(!UseCountLeadingZerosInstruction);
5123   match(Set dst (CountLeadingZerosL src));
5124   effect(TEMP dst, KILL cr);
5125 
5126   format %{ "BSR    $dst, $src.hi\t# count leading zeros (long)\n\t"
5127             "JZ     msw_is_zero\n\t"
5128             "ADD    $dst, 32\n\t"
5129             "JMP    not_zero\n"
5130       "msw_is_zero:\n\t"
5131             "BSR    $dst, $src.lo\n\t"
5132             "JNZ    not_zero\n\t"
5133             "MOV    $dst, -1\n"
5134       "not_zero:\n\t"
5135             "NEG    $dst\n\t"
5136             "ADD    $dst, 63\n" %}
5137  ins_encode %{
5138     Register Rdst = $dst$$Register;
5139     Register Rsrc = $src$$Register;
5140     Label msw_is_zero;
5141     Label not_zero;
5142     __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5143     __ jccb(Assembler::zero, msw_is_zero);
5144     __ addl(Rdst, BitsPerInt);
5145     __ jmpb(not_zero);
5146     __ bind(msw_is_zero);
5147     __ bsrl(Rdst, Rsrc);
5148     __ jccb(Assembler::notZero, not_zero);
5149     __ movl(Rdst, -1);
5150     __ bind(not_zero);
5151     __ negl(Rdst);
5152     __ addl(Rdst, BitsPerLong - 1);
5153   %}
5154   ins_pipe(ialu_reg);
5155 %}
5156 
5157 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5158   predicate(UseCountTrailingZerosInstruction);
5159   match(Set dst (CountTrailingZerosI src));
5160   effect(KILL cr);
5161 
5162   format %{ "TZCNT    $dst, $src\t# count trailing zeros (int)" %}
5163   ins_encode %{
5164     __ tzcntl($dst$$Register, $src$$Register);
5165   %}
5166   ins_pipe(ialu_reg);
5167 %}
5168 
5169 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, eFlagsReg cr) %{
5170   predicate(!UseCountTrailingZerosInstruction);
5171   match(Set dst (CountTrailingZerosI src));
5172   effect(KILL cr);
5173 
5174   format %{ "BSF    $dst, $src\t# count trailing zeros (int)\n\t"
5175             "JNZ    done\n\t"
5176             "MOV    $dst, 32\n"
5177       "done:" %}
5178   ins_encode %{
5179     Register Rdst = $dst$$Register;
5180     Label done;
5181     __ bsfl(Rdst, $src$$Register);
5182     __ jccb(Assembler::notZero, done);
5183     __ movl(Rdst, BitsPerInt);
5184     __ bind(done);
5185   %}
5186   ins_pipe(ialu_reg);
5187 %}
5188 
5189 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5190   predicate(UseCountTrailingZerosInstruction);
5191   match(Set dst (CountTrailingZerosL src));
5192   effect(TEMP dst, KILL cr);
5193 
5194   format %{ "TZCNT  $dst, $src.lo\t# count trailing zeros (long) \n\t"
5195             "JNC    done\n\t"
5196             "TZCNT  $dst, $src.hi\n\t"
5197             "ADD    $dst, 32\n"
5198             "done:" %}
5199   ins_encode %{
5200     Register Rdst = $dst$$Register;
5201     Register Rsrc = $src$$Register;
5202     Label done;
5203     __ tzcntl(Rdst, Rsrc);
5204     __ jccb(Assembler::carryClear, done);
5205     __ tzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5206     __ addl(Rdst, BitsPerInt);
5207     __ bind(done);
5208   %}
5209   ins_pipe(ialu_reg);
5210 %}
5211 
5212 instruct countTrailingZerosL_bsf(rRegI dst, eRegL src, eFlagsReg cr) %{
5213   predicate(!UseCountTrailingZerosInstruction);
5214   match(Set dst (CountTrailingZerosL src));
5215   effect(TEMP dst, KILL cr);
5216 
5217   format %{ "BSF    $dst, $src.lo\t# count trailing zeros (long)\n\t"
5218             "JNZ    done\n\t"
5219             "BSF    $dst, $src.hi\n\t"
5220             "JNZ    msw_not_zero\n\t"
5221             "MOV    $dst, 32\n"
5222       "msw_not_zero:\n\t"
5223             "ADD    $dst, 32\n"
5224       "done:" %}
5225   ins_encode %{
5226     Register Rdst = $dst$$Register;
5227     Register Rsrc = $src$$Register;
5228     Label msw_not_zero;
5229     Label done;
5230     __ bsfl(Rdst, Rsrc);
5231     __ jccb(Assembler::notZero, done);
5232     __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5233     __ jccb(Assembler::notZero, msw_not_zero);
5234     __ movl(Rdst, BitsPerInt);
5235     __ bind(msw_not_zero);
5236     __ addl(Rdst, BitsPerInt);
5237     __ bind(done);
5238   %}
5239   ins_pipe(ialu_reg);
5240 %}
5241 
5242 
5243 //---------- Population Count Instructions -------------------------------------
5244 
5245 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5246   predicate(UsePopCountInstruction);
5247   match(Set dst (PopCountI src));
5248   effect(KILL cr);
5249 
5250   format %{ "POPCNT $dst, $src" %}
5251   ins_encode %{
5252     __ popcntl($dst$$Register, $src$$Register);
5253   %}
5254   ins_pipe(ialu_reg);
5255 %}
5256 
5257 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5258   predicate(UsePopCountInstruction);
5259   match(Set dst (PopCountI (LoadI mem)));
5260   effect(KILL cr);
5261 
5262   format %{ "POPCNT $dst, $mem" %}
5263   ins_encode %{
5264     __ popcntl($dst$$Register, $mem$$Address);
5265   %}
5266   ins_pipe(ialu_reg);
5267 %}
5268 
5269 // Note: Long.bitCount(long) returns an int.
5270 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5271   predicate(UsePopCountInstruction);
5272   match(Set dst (PopCountL src));
5273   effect(KILL cr, TEMP tmp, TEMP dst);
5274 
5275   format %{ "POPCNT $dst, $src.lo\n\t"
5276             "POPCNT $tmp, $src.hi\n\t"
5277             "ADD    $dst, $tmp" %}
5278   ins_encode %{
5279     __ popcntl($dst$$Register, $src$$Register);
5280     __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5281     __ addl($dst$$Register, $tmp$$Register);
5282   %}
5283   ins_pipe(ialu_reg);
5284 %}
5285 
5286 // Note: Long.bitCount(long) returns an int.
5287 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5288   predicate(UsePopCountInstruction);
5289   match(Set dst (PopCountL (LoadL mem)));
5290   effect(KILL cr, TEMP tmp, TEMP dst);
5291 
5292   format %{ "POPCNT $dst, $mem\n\t"
5293             "POPCNT $tmp, $mem+4\n\t"
5294             "ADD    $dst, $tmp" %}
5295   ins_encode %{
5296     //__ popcntl($dst$$Register, $mem$$Address$$first);
5297     //__ popcntl($tmp$$Register, $mem$$Address$$second);
5298     __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5299     __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5300     __ addl($dst$$Register, $tmp$$Register);
5301   %}
5302   ins_pipe(ialu_reg);
5303 %}
5304 
5305 
5306 //----------Load/Store/Move Instructions---------------------------------------
5307 //----------Load Instructions--------------------------------------------------
5308 // Load Byte (8bit signed)
5309 instruct loadB(xRegI dst, memory mem) %{
5310   match(Set dst (LoadB mem));
5311 
5312   ins_cost(125);
5313   format %{ "MOVSX8 $dst,$mem\t# byte" %}
5314 
5315   ins_encode %{
5316     __ movsbl($dst$$Register, $mem$$Address);
5317   %}
5318 
5319   ins_pipe(ialu_reg_mem);
5320 %}
5321 
5322 // Load Byte (8bit signed) into Long Register
5323 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5324   match(Set dst (ConvI2L (LoadB mem)));
5325   effect(KILL cr);
5326 
5327   ins_cost(375);
5328   format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5329             "MOV    $dst.hi,$dst.lo\n\t"
5330             "SAR    $dst.hi,7" %}
5331 
5332   ins_encode %{
5333     __ movsbl($dst$$Register, $mem$$Address);
5334     __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5335     __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5336   %}
5337 
5338   ins_pipe(ialu_reg_mem);
5339 %}
5340 
5341 // Load Unsigned Byte (8bit UNsigned)
5342 instruct loadUB(xRegI dst, memory mem) %{
5343   match(Set dst (LoadUB mem));
5344 
5345   ins_cost(125);
5346   format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5347 
5348   ins_encode %{
5349     __ movzbl($dst$$Register, $mem$$Address);
5350   %}
5351 
5352   ins_pipe(ialu_reg_mem);
5353 %}
5354 
5355 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5356 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5357   match(Set dst (ConvI2L (LoadUB mem)));
5358   effect(KILL cr);
5359 
5360   ins_cost(250);
5361   format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5362             "XOR    $dst.hi,$dst.hi" %}
5363 
5364   ins_encode %{
5365     Register Rdst = $dst$$Register;
5366     __ movzbl(Rdst, $mem$$Address);
5367     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5368   %}
5369 
5370   ins_pipe(ialu_reg_mem);
5371 %}
5372 
5373 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5374 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5375   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5376   effect(KILL cr);
5377 
5378   format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5379             "XOR    $dst.hi,$dst.hi\n\t"
5380             "AND    $dst.lo,$mask" %}
5381   ins_encode %{
5382     Register Rdst = $dst$$Register;
5383     __ movzbl(Rdst, $mem$$Address);
5384     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5385     __ andl(Rdst, $mask$$constant);
5386   %}
5387   ins_pipe(ialu_reg_mem);
5388 %}
5389 
5390 // Load Short (16bit signed)
5391 instruct loadS(rRegI dst, memory mem) %{
5392   match(Set dst (LoadS mem));
5393 
5394   ins_cost(125);
5395   format %{ "MOVSX  $dst,$mem\t# short" %}
5396 
5397   ins_encode %{
5398     __ movswl($dst$$Register, $mem$$Address);
5399   %}
5400 
5401   ins_pipe(ialu_reg_mem);
5402 %}
5403 
5404 // Load Short (16 bit signed) to Byte (8 bit signed)
5405 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5406   match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5407 
5408   ins_cost(125);
5409   format %{ "MOVSX  $dst, $mem\t# short -> byte" %}
5410   ins_encode %{
5411     __ movsbl($dst$$Register, $mem$$Address);
5412   %}
5413   ins_pipe(ialu_reg_mem);
5414 %}
5415 
5416 // Load Short (16bit signed) into Long Register
5417 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5418   match(Set dst (ConvI2L (LoadS mem)));
5419   effect(KILL cr);
5420 
5421   ins_cost(375);
5422   format %{ "MOVSX  $dst.lo,$mem\t# short -> long\n\t"
5423             "MOV    $dst.hi,$dst.lo\n\t"
5424             "SAR    $dst.hi,15" %}
5425 
5426   ins_encode %{
5427     __ movswl($dst$$Register, $mem$$Address);
5428     __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5429     __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5430   %}
5431 
5432   ins_pipe(ialu_reg_mem);
5433 %}
5434 
5435 // Load Unsigned Short/Char (16bit unsigned)
5436 instruct loadUS(rRegI dst, memory mem) %{
5437   match(Set dst (LoadUS mem));
5438 
5439   ins_cost(125);
5440   format %{ "MOVZX  $dst,$mem\t# ushort/char -> int" %}
5441 
5442   ins_encode %{
5443     __ movzwl($dst$$Register, $mem$$Address);
5444   %}
5445 
5446   ins_pipe(ialu_reg_mem);
5447 %}
5448 
5449 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5450 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5451   match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5452 
5453   ins_cost(125);
5454   format %{ "MOVSX  $dst, $mem\t# ushort -> byte" %}
5455   ins_encode %{
5456     __ movsbl($dst$$Register, $mem$$Address);
5457   %}
5458   ins_pipe(ialu_reg_mem);
5459 %}
5460 
5461 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5462 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5463   match(Set dst (ConvI2L (LoadUS mem)));
5464   effect(KILL cr);
5465 
5466   ins_cost(250);
5467   format %{ "MOVZX  $dst.lo,$mem\t# ushort/char -> long\n\t"
5468             "XOR    $dst.hi,$dst.hi" %}
5469 
5470   ins_encode %{
5471     __ movzwl($dst$$Register, $mem$$Address);
5472     __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5473   %}
5474 
5475   ins_pipe(ialu_reg_mem);
5476 %}
5477 
5478 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5479 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5480   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5481   effect(KILL cr);
5482 
5483   format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5484             "XOR    $dst.hi,$dst.hi" %}
5485   ins_encode %{
5486     Register Rdst = $dst$$Register;
5487     __ movzbl(Rdst, $mem$$Address);
5488     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5489   %}
5490   ins_pipe(ialu_reg_mem);
5491 %}
5492 
5493 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
5494 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
5495   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5496   effect(KILL cr);
5497 
5498   format %{ "MOVZX  $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
5499             "XOR    $dst.hi,$dst.hi\n\t"
5500             "AND    $dst.lo,$mask" %}
5501   ins_encode %{
5502     Register Rdst = $dst$$Register;
5503     __ movzwl(Rdst, $mem$$Address);
5504     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5505     __ andl(Rdst, $mask$$constant);
5506   %}
5507   ins_pipe(ialu_reg_mem);
5508 %}
5509 
5510 // Load Integer
5511 instruct loadI(rRegI dst, memory mem) %{
5512   match(Set dst (LoadI mem));
5513 
5514   ins_cost(125);
5515   format %{ "MOV    $dst,$mem\t# int" %}
5516 
5517   ins_encode %{
5518     __ movl($dst$$Register, $mem$$Address);
5519   %}
5520 
5521   ins_pipe(ialu_reg_mem);
5522 %}
5523 
5524 // Load Integer (32 bit signed) to Byte (8 bit signed)
5525 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5526   match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5527 
5528   ins_cost(125);
5529   format %{ "MOVSX  $dst, $mem\t# int -> byte" %}
5530   ins_encode %{
5531     __ movsbl($dst$$Register, $mem$$Address);
5532   %}
5533   ins_pipe(ialu_reg_mem);
5534 %}
5535 
5536 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5537 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5538   match(Set dst (AndI (LoadI mem) mask));
5539 
5540   ins_cost(125);
5541   format %{ "MOVZX  $dst, $mem\t# int -> ubyte" %}
5542   ins_encode %{
5543     __ movzbl($dst$$Register, $mem$$Address);
5544   %}
5545   ins_pipe(ialu_reg_mem);
5546 %}
5547 
5548 // Load Integer (32 bit signed) to Short (16 bit signed)
5549 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5550   match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5551 
5552   ins_cost(125);
5553   format %{ "MOVSX  $dst, $mem\t# int -> short" %}
5554   ins_encode %{
5555     __ movswl($dst$$Register, $mem$$Address);
5556   %}
5557   ins_pipe(ialu_reg_mem);
5558 %}
5559 
5560 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5561 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5562   match(Set dst (AndI (LoadI mem) mask));
5563 
5564   ins_cost(125);
5565   format %{ "MOVZX  $dst, $mem\t# int -> ushort/char" %}
5566   ins_encode %{
5567     __ movzwl($dst$$Register, $mem$$Address);
5568   %}
5569   ins_pipe(ialu_reg_mem);
5570 %}
5571 
5572 // Load Integer into Long Register
5573 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
5574   match(Set dst (ConvI2L (LoadI mem)));
5575   effect(KILL cr);
5576 
5577   ins_cost(375);
5578   format %{ "MOV    $dst.lo,$mem\t# int -> long\n\t"
5579             "MOV    $dst.hi,$dst.lo\n\t"
5580             "SAR    $dst.hi,31" %}
5581 
5582   ins_encode %{
5583     __ movl($dst$$Register, $mem$$Address);
5584     __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5585     __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
5586   %}
5587 
5588   ins_pipe(ialu_reg_mem);
5589 %}
5590 
5591 // Load Integer with mask 0xFF into Long Register
5592 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5593   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5594   effect(KILL cr);
5595 
5596   format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
5597             "XOR    $dst.hi,$dst.hi" %}
5598   ins_encode %{
5599     Register Rdst = $dst$$Register;
5600     __ movzbl(Rdst, $mem$$Address);
5601     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5602   %}
5603   ins_pipe(ialu_reg_mem);
5604 %}
5605 
5606 // Load Integer with mask 0xFFFF into Long Register
5607 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
5608   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5609   effect(KILL cr);
5610 
5611   format %{ "MOVZX  $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
5612             "XOR    $dst.hi,$dst.hi" %}
5613   ins_encode %{
5614     Register Rdst = $dst$$Register;
5615     __ movzwl(Rdst, $mem$$Address);
5616     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5617   %}
5618   ins_pipe(ialu_reg_mem);
5619 %}
5620 
5621 // Load Integer with 31-bit mask into Long Register
5622 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{
5623   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5624   effect(KILL cr);
5625 
5626   format %{ "MOV    $dst.lo,$mem\t# int & 31-bit mask -> long\n\t"
5627             "XOR    $dst.hi,$dst.hi\n\t"
5628             "AND    $dst.lo,$mask" %}
5629   ins_encode %{
5630     Register Rdst = $dst$$Register;
5631     __ movl(Rdst, $mem$$Address);
5632     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5633     __ andl(Rdst, $mask$$constant);
5634   %}
5635   ins_pipe(ialu_reg_mem);
5636 %}
5637 
5638 // Load Unsigned Integer into Long Register
5639 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
5640   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5641   effect(KILL cr);
5642 
5643   ins_cost(250);
5644   format %{ "MOV    $dst.lo,$mem\t# uint -> long\n\t"
5645             "XOR    $dst.hi,$dst.hi" %}
5646 
5647   ins_encode %{
5648     __ movl($dst$$Register, $mem$$Address);
5649     __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5650   %}
5651 
5652   ins_pipe(ialu_reg_mem);
5653 %}
5654 
5655 // Load Long.  Cannot clobber address while loading, so restrict address
5656 // register to ESI
5657 instruct loadL(eRegL dst, load_long_memory mem) %{
5658   predicate(!((LoadLNode*)n)->require_atomic_access());
5659   match(Set dst (LoadL mem));
5660 
5661   ins_cost(250);
5662   format %{ "MOV    $dst.lo,$mem\t# long\n\t"
5663             "MOV    $dst.hi,$mem+4" %}
5664 
5665   ins_encode %{
5666     Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
5667     Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
5668     __ movl($dst$$Register, Amemlo);
5669     __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
5670   %}
5671 
5672   ins_pipe(ialu_reg_long_mem);
5673 %}
5674 
5675 // Volatile Load Long.  Must be atomic, so do 64-bit FILD
5676 // then store it down to the stack and reload on the int
5677 // side.
5678 instruct loadL_volatile(stackSlotL dst, memory mem) %{
5679   predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
5680   match(Set dst (LoadL mem));
5681 
5682   ins_cost(200);
5683   format %{ "FILD   $mem\t# Atomic volatile long load\n\t"
5684             "FISTp  $dst" %}
5685   ins_encode(enc_loadL_volatile(mem,dst));
5686   ins_pipe( fpu_reg_mem );
5687 %}
5688 
5689 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
5690   predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
5691   match(Set dst (LoadL mem));
5692   effect(TEMP tmp);
5693   ins_cost(180);
5694   format %{ "MOVSD  $tmp,$mem\t# Atomic volatile long load\n\t"
5695             "MOVSD  $dst,$tmp" %}
5696   ins_encode %{
5697     __ movdbl($tmp$$XMMRegister, $mem$$Address);
5698     __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
5699   %}
5700   ins_pipe( pipe_slow );
5701 %}
5702 
5703 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
5704   predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
5705   match(Set dst (LoadL mem));
5706   effect(TEMP tmp);
5707   ins_cost(160);
5708   format %{ "MOVSD  $tmp,$mem\t# Atomic volatile long load\n\t"
5709             "MOVD   $dst.lo,$tmp\n\t"
5710             "PSRLQ  $tmp,32\n\t"
5711             "MOVD   $dst.hi,$tmp" %}
5712   ins_encode %{
5713     __ movdbl($tmp$$XMMRegister, $mem$$Address);
5714     __ movdl($dst$$Register, $tmp$$XMMRegister);
5715     __ psrlq($tmp$$XMMRegister, 32);
5716     __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
5717   %}
5718   ins_pipe( pipe_slow );
5719 %}
5720 
5721 // Load Range
5722 instruct loadRange(rRegI dst, memory mem) %{
5723   match(Set dst (LoadRange mem));
5724 
5725   ins_cost(125);
5726   format %{ "MOV    $dst,$mem" %}
5727   opcode(0x8B);
5728   ins_encode( OpcP, RegMem(dst,mem));
5729   ins_pipe( ialu_reg_mem );
5730 %}
5731 
5732 
5733 // Load Pointer
5734 instruct loadP(eRegP dst, memory mem) %{
5735   match(Set dst (LoadP mem));
5736 
5737   ins_cost(125);
5738   format %{ "MOV    $dst,$mem" %}
5739   opcode(0x8B);
5740   ins_encode( OpcP, RegMem(dst,mem));
5741   ins_pipe( ialu_reg_mem );
5742 %}
5743 
5744 // Load Klass Pointer
5745 instruct loadKlass(eRegP dst, memory mem) %{
5746   match(Set dst (LoadKlass mem));
5747 
5748   ins_cost(125);
5749   format %{ "MOV    $dst,$mem" %}
5750   opcode(0x8B);
5751   ins_encode( OpcP, RegMem(dst,mem));
5752   ins_pipe( ialu_reg_mem );
5753 %}
5754 
5755 // Load Double
5756 instruct loadDPR(regDPR dst, memory mem) %{
5757   predicate(UseSSE<=1);
5758   match(Set dst (LoadD mem));
5759 
5760   ins_cost(150);
5761   format %{ "FLD_D  ST,$mem\n\t"
5762             "FSTP   $dst" %}
5763   opcode(0xDD);               /* DD /0 */
5764   ins_encode( OpcP, RMopc_Mem(0x00,mem),
5765               Pop_Reg_DPR(dst) );
5766   ins_pipe( fpu_reg_mem );
5767 %}
5768 
5769 // Load Double to XMM
5770 instruct loadD(regD dst, memory mem) %{
5771   predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
5772   match(Set dst (LoadD mem));
5773   ins_cost(145);
5774   format %{ "MOVSD  $dst,$mem" %}
5775   ins_encode %{
5776     __ movdbl ($dst$$XMMRegister, $mem$$Address);
5777   %}
5778   ins_pipe( pipe_slow );
5779 %}
5780 
5781 instruct loadD_partial(regD dst, memory mem) %{
5782   predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
5783   match(Set dst (LoadD mem));
5784   ins_cost(145);
5785   format %{ "MOVLPD $dst,$mem" %}
5786   ins_encode %{
5787     __ movdbl ($dst$$XMMRegister, $mem$$Address);
5788   %}
5789   ins_pipe( pipe_slow );
5790 %}
5791 
5792 // Load to XMM register (single-precision floating point)
5793 // MOVSS instruction
5794 instruct loadF(regF dst, memory mem) %{
5795   predicate(UseSSE>=1);
5796   match(Set dst (LoadF mem));
5797   ins_cost(145);
5798   format %{ "MOVSS  $dst,$mem" %}
5799   ins_encode %{
5800     __ movflt ($dst$$XMMRegister, $mem$$Address);
5801   %}
5802   ins_pipe( pipe_slow );
5803 %}
5804 
5805 // Load Float
5806 instruct loadFPR(regFPR dst, memory mem) %{
5807   predicate(UseSSE==0);
5808   match(Set dst (LoadF mem));
5809 
5810   ins_cost(150);
5811   format %{ "FLD_S  ST,$mem\n\t"
5812             "FSTP   $dst" %}
5813   opcode(0xD9);               /* D9 /0 */
5814   ins_encode( OpcP, RMopc_Mem(0x00,mem),
5815               Pop_Reg_FPR(dst) );
5816   ins_pipe( fpu_reg_mem );
5817 %}
5818 
5819 // Load Effective Address
5820 instruct leaP8(eRegP dst, indOffset8 mem) %{
5821   match(Set dst mem);
5822 
5823   ins_cost(110);
5824   format %{ "LEA    $dst,$mem" %}
5825   opcode(0x8D);
5826   ins_encode( OpcP, RegMem(dst,mem));
5827   ins_pipe( ialu_reg_reg_fat );
5828 %}
5829 
5830 instruct leaP32(eRegP dst, indOffset32 mem) %{
5831   match(Set dst mem);
5832 
5833   ins_cost(110);
5834   format %{ "LEA    $dst,$mem" %}
5835   opcode(0x8D);
5836   ins_encode( OpcP, RegMem(dst,mem));
5837   ins_pipe( ialu_reg_reg_fat );
5838 %}
5839 
5840 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
5841   match(Set dst mem);
5842 
5843   ins_cost(110);
5844   format %{ "LEA    $dst,$mem" %}
5845   opcode(0x8D);
5846   ins_encode( OpcP, RegMem(dst,mem));
5847   ins_pipe( ialu_reg_reg_fat );
5848 %}
5849 
5850 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
5851   match(Set dst mem);
5852 
5853   ins_cost(110);
5854   format %{ "LEA    $dst,$mem" %}
5855   opcode(0x8D);
5856   ins_encode( OpcP, RegMem(dst,mem));
5857   ins_pipe( ialu_reg_reg_fat );
5858 %}
5859 
5860 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
5861   match(Set dst mem);
5862 
5863   ins_cost(110);
5864   format %{ "LEA    $dst,$mem" %}
5865   opcode(0x8D);
5866   ins_encode( OpcP, RegMem(dst,mem));
5867   ins_pipe( ialu_reg_reg_fat );
5868 %}
5869 
5870 // Load Constant
5871 instruct loadConI(rRegI dst, immI src) %{
5872   match(Set dst src);
5873 
5874   format %{ "MOV    $dst,$src" %}
5875   ins_encode( LdImmI(dst, src) );
5876   ins_pipe( ialu_reg_fat );
5877 %}
5878 
5879 // Load Constant zero
5880 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
5881   match(Set dst src);
5882   effect(KILL cr);
5883 
5884   ins_cost(50);
5885   format %{ "XOR    $dst,$dst" %}
5886   opcode(0x33);  /* + rd */
5887   ins_encode( OpcP, RegReg( dst, dst ) );
5888   ins_pipe( ialu_reg );
5889 %}
5890 
5891 instruct loadConP(eRegP dst, immP src) %{
5892   match(Set dst src);
5893 
5894   format %{ "MOV    $dst,$src" %}
5895   opcode(0xB8);  /* + rd */
5896   ins_encode( LdImmP(dst, src) );
5897   ins_pipe( ialu_reg_fat );
5898 %}
5899 
5900 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
5901   match(Set dst src);
5902   effect(KILL cr);
5903   ins_cost(200);
5904   format %{ "MOV    $dst.lo,$src.lo\n\t"
5905             "MOV    $dst.hi,$src.hi" %}
5906   opcode(0xB8);
5907   ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
5908   ins_pipe( ialu_reg_long_fat );
5909 %}
5910 
5911 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
5912   match(Set dst src);
5913   effect(KILL cr);
5914   ins_cost(150);
5915   format %{ "XOR    $dst.lo,$dst.lo\n\t"
5916             "XOR    $dst.hi,$dst.hi" %}
5917   opcode(0x33,0x33);
5918   ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
5919   ins_pipe( ialu_reg_long );
5920 %}
5921 
5922 // The instruction usage is guarded by predicate in operand immFPR().
5923 instruct loadConFPR(regFPR dst, immFPR con) %{
5924   match(Set dst con);
5925   ins_cost(125);
5926   format %{ "FLD_S  ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
5927             "FSTP   $dst" %}
5928   ins_encode %{
5929     __ fld_s($constantaddress($con));
5930     __ fstp_d($dst$$reg);
5931   %}
5932   ins_pipe(fpu_reg_con);
5933 %}
5934 
5935 // The instruction usage is guarded by predicate in operand immFPR0().
5936 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
5937   match(Set dst con);
5938   ins_cost(125);
5939   format %{ "FLDZ   ST\n\t"
5940             "FSTP   $dst" %}
5941   ins_encode %{
5942     __ fldz();
5943     __ fstp_d($dst$$reg);
5944   %}
5945   ins_pipe(fpu_reg_con);
5946 %}
5947 
5948 // The instruction usage is guarded by predicate in operand immFPR1().
5949 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
5950   match(Set dst con);
5951   ins_cost(125);
5952   format %{ "FLD1   ST\n\t"
5953             "FSTP   $dst" %}
5954   ins_encode %{
5955     __ fld1();
5956     __ fstp_d($dst$$reg);
5957   %}
5958   ins_pipe(fpu_reg_con);
5959 %}
5960 
5961 // The instruction usage is guarded by predicate in operand immF().
5962 instruct loadConF(regF dst, immF con) %{
5963   match(Set dst con);
5964   ins_cost(125);
5965   format %{ "MOVSS  $dst,[$constantaddress]\t# load from constant table: float=$con" %}
5966   ins_encode %{
5967     __ movflt($dst$$XMMRegister, $constantaddress($con));
5968   %}
5969   ins_pipe(pipe_slow);
5970 %}
5971 
5972 // The instruction usage is guarded by predicate in operand immF0().
5973 instruct loadConF0(regF dst, immF0 src) %{
5974   match(Set dst src);
5975   ins_cost(100);
5976   format %{ "XORPS  $dst,$dst\t# float 0.0" %}
5977   ins_encode %{
5978     __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5979   %}
5980   ins_pipe(pipe_slow);
5981 %}
5982 
5983 // The instruction usage is guarded by predicate in operand immDPR().
5984 instruct loadConDPR(regDPR dst, immDPR con) %{
5985   match(Set dst con);
5986   ins_cost(125);
5987 
5988   format %{ "FLD_D  ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
5989             "FSTP   $dst" %}
5990   ins_encode %{
5991     __ fld_d($constantaddress($con));
5992     __ fstp_d($dst$$reg);
5993   %}
5994   ins_pipe(fpu_reg_con);
5995 %}
5996 
5997 // The instruction usage is guarded by predicate in operand immDPR0().
5998 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
5999   match(Set dst con);
6000   ins_cost(125);
6001 
6002   format %{ "FLDZ   ST\n\t"
6003             "FSTP   $dst" %}
6004   ins_encode %{
6005     __ fldz();
6006     __ fstp_d($dst$$reg);
6007   %}
6008   ins_pipe(fpu_reg_con);
6009 %}
6010 
6011 // The instruction usage is guarded by predicate in operand immDPR1().
6012 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6013   match(Set dst con);
6014   ins_cost(125);
6015 
6016   format %{ "FLD1   ST\n\t"
6017             "FSTP   $dst" %}
6018   ins_encode %{
6019     __ fld1();
6020     __ fstp_d($dst$$reg);
6021   %}
6022   ins_pipe(fpu_reg_con);
6023 %}
6024 
6025 // The instruction usage is guarded by predicate in operand immD().
6026 instruct loadConD(regD dst, immD con) %{
6027   match(Set dst con);
6028   ins_cost(125);
6029   format %{ "MOVSD  $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6030   ins_encode %{
6031     __ movdbl($dst$$XMMRegister, $constantaddress($con));
6032   %}
6033   ins_pipe(pipe_slow);
6034 %}
6035 
6036 // The instruction usage is guarded by predicate in operand immD0().
6037 instruct loadConD0(regD dst, immD0 src) %{
6038   match(Set dst src);
6039   ins_cost(100);
6040   format %{ "XORPD  $dst,$dst\t# double 0.0" %}
6041   ins_encode %{
6042     __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6043   %}
6044   ins_pipe( pipe_slow );
6045 %}
6046 
6047 // Load Stack Slot
6048 instruct loadSSI(rRegI dst, stackSlotI src) %{
6049   match(Set dst src);
6050   ins_cost(125);
6051 
6052   format %{ "MOV    $dst,$src" %}
6053   opcode(0x8B);
6054   ins_encode( OpcP, RegMem(dst,src));
6055   ins_pipe( ialu_reg_mem );
6056 %}
6057 
6058 instruct loadSSL(eRegL dst, stackSlotL src) %{
6059   match(Set dst src);
6060 
6061   ins_cost(200);
6062   format %{ "MOV    $dst,$src.lo\n\t"
6063             "MOV    $dst+4,$src.hi" %}
6064   opcode(0x8B, 0x8B);
6065   ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6066   ins_pipe( ialu_mem_long_reg );
6067 %}
6068 
6069 // Load Stack Slot
6070 instruct loadSSP(eRegP dst, stackSlotP src) %{
6071   match(Set dst src);
6072   ins_cost(125);
6073 
6074   format %{ "MOV    $dst,$src" %}
6075   opcode(0x8B);
6076   ins_encode( OpcP, RegMem(dst,src));
6077   ins_pipe( ialu_reg_mem );
6078 %}
6079 
6080 // Load Stack Slot
6081 instruct loadSSF(regFPR dst, stackSlotF src) %{
6082   match(Set dst src);
6083   ins_cost(125);
6084 
6085   format %{ "FLD_S  $src\n\t"
6086             "FSTP   $dst" %}
6087   opcode(0xD9);               /* D9 /0, FLD m32real */
6088   ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6089               Pop_Reg_FPR(dst) );
6090   ins_pipe( fpu_reg_mem );
6091 %}
6092 
6093 // Load Stack Slot
6094 instruct loadSSD(regDPR dst, stackSlotD src) %{
6095   match(Set dst src);
6096   ins_cost(125);
6097 
6098   format %{ "FLD_D  $src\n\t"
6099             "FSTP   $dst" %}
6100   opcode(0xDD);               /* DD /0, FLD m64real */
6101   ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6102               Pop_Reg_DPR(dst) );
6103   ins_pipe( fpu_reg_mem );
6104 %}
6105 
6106 // Prefetch instructions.
6107 // Must be safe to execute with invalid address (cannot fault).
6108 
6109 instruct prefetchr0( memory mem ) %{
6110   predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6111   match(PrefetchRead mem);
6112   ins_cost(0);
6113   size(0);
6114   format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6115   ins_encode();
6116   ins_pipe(empty);
6117 %}
6118 
6119 instruct prefetchr( memory mem ) %{
6120   predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6121   match(PrefetchRead mem);
6122   ins_cost(100);
6123 
6124   format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6125   ins_encode %{
6126     __ prefetchr($mem$$Address);
6127   %}
6128   ins_pipe(ialu_mem);
6129 %}
6130 
6131 instruct prefetchrNTA( memory mem ) %{
6132   predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6133   match(PrefetchRead mem);
6134   ins_cost(100);
6135 
6136   format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6137   ins_encode %{
6138     __ prefetchnta($mem$$Address);
6139   %}
6140   ins_pipe(ialu_mem);
6141 %}
6142 
6143 instruct prefetchrT0( memory mem ) %{
6144   predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6145   match(PrefetchRead mem);
6146   ins_cost(100);
6147 
6148   format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6149   ins_encode %{
6150     __ prefetcht0($mem$$Address);
6151   %}
6152   ins_pipe(ialu_mem);
6153 %}
6154 
6155 instruct prefetchrT2( memory mem ) %{
6156   predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6157   match(PrefetchRead mem);
6158   ins_cost(100);
6159 
6160   format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6161   ins_encode %{
6162     __ prefetcht2($mem$$Address);
6163   %}
6164   ins_pipe(ialu_mem);
6165 %}
6166 
6167 instruct prefetchw0( memory mem ) %{
6168   predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6169   match(PrefetchWrite mem);
6170   ins_cost(0);
6171   size(0);
6172   format %{ "Prefetch (non-SSE is empty encoding)" %}
6173   ins_encode();
6174   ins_pipe(empty);
6175 %}
6176 
6177 instruct prefetchw( memory mem ) %{
6178   predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6179   match( PrefetchWrite mem );
6180   ins_cost(100);
6181 
6182   format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6183   ins_encode %{
6184     __ prefetchw($mem$$Address);
6185   %}
6186   ins_pipe(ialu_mem);
6187 %}
6188 
6189 instruct prefetchwNTA( memory mem ) %{
6190   predicate(UseSSE>=1);
6191   match(PrefetchWrite mem);
6192   ins_cost(100);
6193 
6194   format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6195   ins_encode %{
6196     __ prefetchnta($mem$$Address);
6197   %}
6198   ins_pipe(ialu_mem);
6199 %}
6200 
6201 // Prefetch instructions for allocation.
6202 
6203 instruct prefetchAlloc0( memory mem ) %{
6204   predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6205   match(PrefetchAllocation mem);
6206   ins_cost(0);
6207   size(0);
6208   format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6209   ins_encode();
6210   ins_pipe(empty);
6211 %}
6212 
6213 instruct prefetchAlloc( memory mem ) %{
6214   predicate(AllocatePrefetchInstr==3);
6215   match( PrefetchAllocation mem );
6216   ins_cost(100);
6217 
6218   format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6219   ins_encode %{
6220     __ prefetchw($mem$$Address);
6221   %}
6222   ins_pipe(ialu_mem);
6223 %}
6224 
6225 instruct prefetchAllocNTA( memory mem ) %{
6226   predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6227   match(PrefetchAllocation mem);
6228   ins_cost(100);
6229 
6230   format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6231   ins_encode %{
6232     __ prefetchnta($mem$$Address);
6233   %}
6234   ins_pipe(ialu_mem);
6235 %}
6236 
6237 instruct prefetchAllocT0( memory mem ) %{
6238   predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6239   match(PrefetchAllocation mem);
6240   ins_cost(100);
6241 
6242   format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6243   ins_encode %{
6244     __ prefetcht0($mem$$Address);
6245   %}
6246   ins_pipe(ialu_mem);
6247 %}
6248 
6249 instruct prefetchAllocT2( memory mem ) %{
6250   predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6251   match(PrefetchAllocation mem);
6252   ins_cost(100);
6253 
6254   format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6255   ins_encode %{
6256     __ prefetcht2($mem$$Address);
6257   %}
6258   ins_pipe(ialu_mem);
6259 %}
6260 
6261 //----------Store Instructions-------------------------------------------------
6262 
6263 // Store Byte
6264 instruct storeB(memory mem, xRegI src) %{
6265   match(Set mem (StoreB mem src));
6266 
6267   ins_cost(125);
6268   format %{ "MOV8   $mem,$src" %}
6269   opcode(0x88);
6270   ins_encode( OpcP, RegMem( src, mem ) );
6271   ins_pipe( ialu_mem_reg );
6272 %}
6273 
6274 // Store Char/Short
6275 instruct storeC(memory mem, rRegI src) %{
6276   match(Set mem (StoreC mem src));
6277 
6278   ins_cost(125);
6279   format %{ "MOV16  $mem,$src" %}
6280   opcode(0x89, 0x66);
6281   ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6282   ins_pipe( ialu_mem_reg );
6283 %}
6284 
6285 // Store Integer
6286 instruct storeI(memory mem, rRegI src) %{
6287   match(Set mem (StoreI mem src));
6288 
6289   ins_cost(125);
6290   format %{ "MOV    $mem,$src" %}
6291   opcode(0x89);
6292   ins_encode( OpcP, RegMem( src, mem ) );
6293   ins_pipe( ialu_mem_reg );
6294 %}
6295 
6296 // Store Long
6297 instruct storeL(long_memory mem, eRegL src) %{
6298   predicate(!((StoreLNode*)n)->require_atomic_access());
6299   match(Set mem (StoreL mem src));
6300 
6301   ins_cost(200);
6302   format %{ "MOV    $mem,$src.lo\n\t"
6303             "MOV    $mem+4,$src.hi" %}
6304   opcode(0x89, 0x89);
6305   ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6306   ins_pipe( ialu_mem_long_reg );
6307 %}
6308 
6309 // Store Long to Integer
6310 instruct storeL2I(memory mem, eRegL src) %{
6311   match(Set mem (StoreI mem (ConvL2I src)));
6312 
6313   format %{ "MOV    $mem,$src.lo\t# long -> int" %}
6314   ins_encode %{
6315     __ movl($mem$$Address, $src$$Register);
6316   %}
6317   ins_pipe(ialu_mem_reg);
6318 %}
6319 
6320 // Volatile Store Long.  Must be atomic, so move it into
6321 // the FP TOS and then do a 64-bit FIST.  Has to probe the
6322 // target address before the store (for null-ptr checks)
6323 // so the memory operand is used twice in the encoding.
6324 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6325   predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6326   match(Set mem (StoreL mem src));
6327   effect( KILL cr );
6328   ins_cost(400);
6329   format %{ "CMP    $mem,EAX\t# Probe address for implicit null check\n\t"
6330             "FILD   $src\n\t"
6331             "FISTp  $mem\t # 64-bit atomic volatile long store" %}
6332   opcode(0x3B);
6333   ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6334   ins_pipe( fpu_reg_mem );
6335 %}
6336 
6337 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6338   predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6339   match(Set mem (StoreL mem src));
6340   effect( TEMP tmp, KILL cr );
6341   ins_cost(380);
6342   format %{ "CMP    $mem,EAX\t# Probe address for implicit null check\n\t"
6343             "MOVSD  $tmp,$src\n\t"
6344             "MOVSD  $mem,$tmp\t # 64-bit atomic volatile long store" %}
6345   ins_encode %{
6346     __ cmpl(rax, $mem$$Address);
6347     __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6348     __ movdbl($mem$$Address, $tmp$$XMMRegister);
6349   %}
6350   ins_pipe( pipe_slow );
6351 %}
6352 
6353 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6354   predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6355   match(Set mem (StoreL mem src));
6356   effect( TEMP tmp2 , TEMP tmp, KILL cr );
6357   ins_cost(360);
6358   format %{ "CMP    $mem,EAX\t# Probe address for implicit null check\n\t"
6359             "MOVD   $tmp,$src.lo\n\t"
6360             "MOVD   $tmp2,$src.hi\n\t"
6361             "PUNPCKLDQ $tmp,$tmp2\n\t"
6362             "MOVSD  $mem,$tmp\t # 64-bit atomic volatile long store" %}
6363   ins_encode %{
6364     __ cmpl(rax, $mem$$Address);
6365     __ movdl($tmp$$XMMRegister, $src$$Register);
6366     __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6367     __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6368     __ movdbl($mem$$Address, $tmp$$XMMRegister);
6369   %}
6370   ins_pipe( pipe_slow );
6371 %}
6372 
6373 // Store Pointer; for storing unknown oops and raw pointers
6374 instruct storeP(memory mem, anyRegP src) %{
6375   match(Set mem (StoreP mem src));
6376 
6377   ins_cost(125);
6378   format %{ "MOV    $mem,$src" %}
6379   opcode(0x89);
6380   ins_encode( OpcP, RegMem( src, mem ) );
6381   ins_pipe( ialu_mem_reg );
6382 %}
6383 
6384 // Store Integer Immediate
6385 instruct storeImmI(memory mem, immI src) %{
6386   match(Set mem (StoreI mem src));
6387 
6388   ins_cost(150);
6389   format %{ "MOV    $mem,$src" %}
6390   opcode(0xC7);               /* C7 /0 */
6391   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con32( src ));
6392   ins_pipe( ialu_mem_imm );
6393 %}
6394 
6395 // Store Short/Char Immediate
6396 instruct storeImmI16(memory mem, immI16 src) %{
6397   predicate(UseStoreImmI16);
6398   match(Set mem (StoreC mem src));
6399 
6400   ins_cost(150);
6401   format %{ "MOV16  $mem,$src" %}
6402   opcode(0xC7);     /* C7 /0 Same as 32 store immediate with prefix */
6403   ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem),  Con16( src ));
6404   ins_pipe( ialu_mem_imm );
6405 %}
6406 
6407 // Store Pointer Immediate; null pointers or constant oops that do not
6408 // need card-mark barriers.
6409 instruct storeImmP(memory mem, immP src) %{
6410   match(Set mem (StoreP mem src));
6411 
6412   ins_cost(150);
6413   format %{ "MOV    $mem,$src" %}
6414   opcode(0xC7);               /* C7 /0 */
6415   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con32( src ));
6416   ins_pipe( ialu_mem_imm );
6417 %}
6418 
6419 // Store Byte Immediate
6420 instruct storeImmB(memory mem, immI8 src) %{
6421   match(Set mem (StoreB mem src));
6422 
6423   ins_cost(150);
6424   format %{ "MOV8   $mem,$src" %}
6425   opcode(0xC6);               /* C6 /0 */
6426   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con8or32( src ));
6427   ins_pipe( ialu_mem_imm );
6428 %}
6429 
6430 // Store CMS card-mark Immediate
6431 instruct storeImmCM(memory mem, immI8 src) %{
6432   match(Set mem (StoreCM mem src));
6433 
6434   ins_cost(150);
6435   format %{ "MOV8   $mem,$src\t! CMS card-mark imm0" %}
6436   opcode(0xC6);               /* C6 /0 */
6437   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con8or32( src ));
6438   ins_pipe( ialu_mem_imm );
6439 %}
6440 
6441 // Store Double
6442 instruct storeDPR( memory mem, regDPR1 src) %{
6443   predicate(UseSSE<=1);
6444   match(Set mem (StoreD mem src));
6445 
6446   ins_cost(100);
6447   format %{ "FST_D  $mem,$src" %}
6448   opcode(0xDD);       /* DD /2 */
6449   ins_encode( enc_FPR_store(mem,src) );
6450   ins_pipe( fpu_mem_reg );
6451 %}
6452 
6453 // Store double does rounding on x86
6454 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6455   predicate(UseSSE<=1);
6456   match(Set mem (StoreD mem (RoundDouble src)));
6457 
6458   ins_cost(100);
6459   format %{ "FST_D  $mem,$src\t# round" %}
6460   opcode(0xDD);       /* DD /2 */
6461   ins_encode( enc_FPR_store(mem,src) );
6462   ins_pipe( fpu_mem_reg );
6463 %}
6464 
6465 // Store XMM register to memory (double-precision floating points)
6466 // MOVSD instruction
6467 instruct storeD(memory mem, regD src) %{
6468   predicate(UseSSE>=2);
6469   match(Set mem (StoreD mem src));
6470   ins_cost(95);
6471   format %{ "MOVSD  $mem,$src" %}
6472   ins_encode %{
6473     __ movdbl($mem$$Address, $src$$XMMRegister);
6474   %}
6475   ins_pipe( pipe_slow );
6476 %}
6477 
6478 // Store XMM register to memory (single-precision floating point)
6479 // MOVSS instruction
6480 instruct storeF(memory mem, regF src) %{
6481   predicate(UseSSE>=1);
6482   match(Set mem (StoreF mem src));
6483   ins_cost(95);
6484   format %{ "MOVSS  $mem,$src" %}
6485   ins_encode %{
6486     __ movflt($mem$$Address, $src$$XMMRegister);
6487   %}
6488   ins_pipe( pipe_slow );
6489 %}
6490 
6491 // Store Float
6492 instruct storeFPR( memory mem, regFPR1 src) %{
6493   predicate(UseSSE==0);
6494   match(Set mem (StoreF mem src));
6495 
6496   ins_cost(100);
6497   format %{ "FST_S  $mem,$src" %}
6498   opcode(0xD9);       /* D9 /2 */
6499   ins_encode( enc_FPR_store(mem,src) );
6500   ins_pipe( fpu_mem_reg );
6501 %}
6502 
6503 // Store Float does rounding on x86
6504 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
6505   predicate(UseSSE==0);
6506   match(Set mem (StoreF mem (RoundFloat src)));
6507 
6508   ins_cost(100);
6509   format %{ "FST_S  $mem,$src\t# round" %}
6510   opcode(0xD9);       /* D9 /2 */
6511   ins_encode( enc_FPR_store(mem,src) );
6512   ins_pipe( fpu_mem_reg );
6513 %}
6514 
6515 // Store Float does rounding on x86
6516 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
6517   predicate(UseSSE<=1);
6518   match(Set mem (StoreF mem (ConvD2F src)));
6519 
6520   ins_cost(100);
6521   format %{ "FST_S  $mem,$src\t# D-round" %}
6522   opcode(0xD9);       /* D9 /2 */
6523   ins_encode( enc_FPR_store(mem,src) );
6524   ins_pipe( fpu_mem_reg );
6525 %}
6526 
6527 // Store immediate Float value (it is faster than store from FPU register)
6528 // The instruction usage is guarded by predicate in operand immFPR().
6529 instruct storeFPR_imm( memory mem, immFPR src) %{
6530   match(Set mem (StoreF mem src));
6531 
6532   ins_cost(50);
6533   format %{ "MOV    $mem,$src\t# store float" %}
6534   opcode(0xC7);               /* C7 /0 */
6535   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con32FPR_as_bits( src ));
6536   ins_pipe( ialu_mem_imm );
6537 %}
6538 
6539 // Store immediate Float value (it is faster than store from XMM register)
6540 // The instruction usage is guarded by predicate in operand immF().
6541 instruct storeF_imm( memory mem, immF src) %{
6542   match(Set mem (StoreF mem src));
6543 
6544   ins_cost(50);
6545   format %{ "MOV    $mem,$src\t# store float" %}
6546   opcode(0xC7);               /* C7 /0 */
6547   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con32F_as_bits( src ));
6548   ins_pipe( ialu_mem_imm );
6549 %}
6550 
6551 // Store Integer to stack slot
6552 instruct storeSSI(stackSlotI dst, rRegI src) %{
6553   match(Set dst src);
6554 
6555   ins_cost(100);
6556   format %{ "MOV    $dst,$src" %}
6557   opcode(0x89);
6558   ins_encode( OpcPRegSS( dst, src ) );
6559   ins_pipe( ialu_mem_reg );
6560 %}
6561 
6562 // Store Integer to stack slot
6563 instruct storeSSP(stackSlotP dst, eRegP src) %{
6564   match(Set dst src);
6565 
6566   ins_cost(100);
6567   format %{ "MOV    $dst,$src" %}
6568   opcode(0x89);
6569   ins_encode( OpcPRegSS( dst, src ) );
6570   ins_pipe( ialu_mem_reg );
6571 %}
6572 
6573 // Store Long to stack slot
6574 instruct storeSSL(stackSlotL dst, eRegL src) %{
6575   match(Set dst src);
6576 
6577   ins_cost(200);
6578   format %{ "MOV    $dst,$src.lo\n\t"
6579             "MOV    $dst+4,$src.hi" %}
6580   opcode(0x89, 0x89);
6581   ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
6582   ins_pipe( ialu_mem_long_reg );
6583 %}
6584 
6585 //----------MemBar Instructions-----------------------------------------------
6586 // Memory barrier flavors
6587 
6588 instruct membar_acquire() %{
6589   match(MemBarAcquire);
6590   ins_cost(400);
6591 
6592   size(0);
6593   format %{ "MEMBAR-acquire ! (empty encoding)" %}
6594   ins_encode();
6595   ins_pipe(empty);
6596 %}
6597 
6598 instruct membar_acquire_lock() %{
6599   match(MemBarAcquireLock);
6600   ins_cost(0);
6601 
6602   size(0);
6603   format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6604   ins_encode( );
6605   ins_pipe(empty);
6606 %}
6607 
6608 instruct membar_release() %{
6609   match(MemBarRelease);
6610   ins_cost(400);
6611 
6612   size(0);
6613   format %{ "MEMBAR-release ! (empty encoding)" %}
6614   ins_encode( );
6615   ins_pipe(empty);
6616 %}
6617 
6618 instruct membar_release_lock() %{
6619   match(MemBarReleaseLock);
6620   ins_cost(0);
6621 
6622   size(0);
6623   format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6624   ins_encode( );
6625   ins_pipe(empty);
6626 %}
6627 
6628 instruct membar_volatile(eFlagsReg cr) %{
6629   match(MemBarVolatile);
6630   effect(KILL cr);
6631   ins_cost(400);
6632 
6633   format %{ 
6634     $$template
6635     if (os::is_MP()) {
6636       $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
6637     } else {
6638       $$emit$$"MEMBAR-volatile ! (empty encoding)"
6639     }
6640   %}
6641   ins_encode %{
6642     __ membar(Assembler::StoreLoad);
6643   %}
6644   ins_pipe(pipe_slow);
6645 %}
6646 
6647 instruct unnecessary_membar_volatile() %{
6648   match(MemBarVolatile);
6649   predicate(Matcher::post_store_load_barrier(n));
6650   ins_cost(0);
6651 
6652   size(0);
6653   format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6654   ins_encode( );
6655   ins_pipe(empty);
6656 %}
6657 
6658 instruct membar_storestore() %{
6659   match(MemBarStoreStore);
6660   ins_cost(0);
6661 
6662   size(0);
6663   format %{ "MEMBAR-storestore (empty encoding)" %}
6664   ins_encode( );
6665   ins_pipe(empty);
6666 %}
6667 
6668 //----------Move Instructions--------------------------------------------------
6669 instruct castX2P(eAXRegP dst, eAXRegI src) %{
6670   match(Set dst (CastX2P src));
6671   format %{ "# X2P  $dst, $src" %}
6672   ins_encode( /*empty encoding*/ );
6673   ins_cost(0);
6674   ins_pipe(empty);
6675 %}
6676 
6677 instruct castP2X(rRegI dst, eRegP src ) %{
6678   match(Set dst (CastP2X src));
6679   ins_cost(50);
6680   format %{ "MOV    $dst, $src\t# CastP2X" %}
6681   ins_encode( enc_Copy( dst, src) );
6682   ins_pipe( ialu_reg_reg );
6683 %}
6684 
6685 //----------Conditional Move---------------------------------------------------
6686 // Conditional move
6687 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
6688   predicate(!VM_Version::supports_cmov() );
6689   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6690   ins_cost(200);
6691   format %{ "J$cop,us skip\t# signed cmove\n\t"
6692             "MOV    $dst,$src\n"
6693       "skip:" %}
6694   ins_encode %{
6695     Label Lskip;
6696     // Invert sense of branch from sense of CMOV
6697     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6698     __ movl($dst$$Register, $src$$Register);
6699     __ bind(Lskip);
6700   %}
6701   ins_pipe( pipe_cmov_reg );
6702 %}
6703 
6704 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
6705   predicate(!VM_Version::supports_cmov() );
6706   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6707   ins_cost(200);
6708   format %{ "J$cop,us skip\t# unsigned cmove\n\t"
6709             "MOV    $dst,$src\n"
6710       "skip:" %}
6711   ins_encode %{
6712     Label Lskip;
6713     // Invert sense of branch from sense of CMOV
6714     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6715     __ movl($dst$$Register, $src$$Register);
6716     __ bind(Lskip);
6717   %}
6718   ins_pipe( pipe_cmov_reg );
6719 %}
6720 
6721 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
6722   predicate(VM_Version::supports_cmov() );
6723   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6724   ins_cost(200);
6725   format %{ "CMOV$cop $dst,$src" %}
6726   opcode(0x0F,0x40);
6727   ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6728   ins_pipe( pipe_cmov_reg );
6729 %}
6730 
6731 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
6732   predicate(VM_Version::supports_cmov() );
6733   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6734   ins_cost(200);
6735   format %{ "CMOV$cop $dst,$src" %}
6736   opcode(0x0F,0x40);
6737   ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6738   ins_pipe( pipe_cmov_reg );
6739 %}
6740 
6741 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
6742   predicate(VM_Version::supports_cmov() );
6743   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6744   ins_cost(200);
6745   expand %{
6746     cmovI_regU(cop, cr, dst, src);
6747   %}
6748 %}
6749 
6750 // Conditional move
6751 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
6752   predicate(VM_Version::supports_cmov() );
6753   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6754   ins_cost(250);
6755   format %{ "CMOV$cop $dst,$src" %}
6756   opcode(0x0F,0x40);
6757   ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6758   ins_pipe( pipe_cmov_mem );
6759 %}
6760 
6761 // Conditional move
6762 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
6763   predicate(VM_Version::supports_cmov() );
6764   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6765   ins_cost(250);
6766   format %{ "CMOV$cop $dst,$src" %}
6767   opcode(0x0F,0x40);
6768   ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6769   ins_pipe( pipe_cmov_mem );
6770 %}
6771 
6772 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
6773   predicate(VM_Version::supports_cmov() );
6774   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6775   ins_cost(250);
6776   expand %{
6777     cmovI_memU(cop, cr, dst, src);
6778   %}
6779 %}
6780 
6781 // Conditional move
6782 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
6783   predicate(VM_Version::supports_cmov() );
6784   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6785   ins_cost(200);
6786   format %{ "CMOV$cop $dst,$src\t# ptr" %}
6787   opcode(0x0F,0x40);
6788   ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6789   ins_pipe( pipe_cmov_reg );
6790 %}
6791 
6792 // Conditional move (non-P6 version)
6793 // Note:  a CMoveP is generated for  stubs and native wrappers
6794 //        regardless of whether we are on a P6, so we
6795 //        emulate a cmov here
6796 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
6797   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6798   ins_cost(300);
6799   format %{ "Jn$cop   skip\n\t"
6800           "MOV    $dst,$src\t# pointer\n"
6801       "skip:" %}
6802   opcode(0x8b);
6803   ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
6804   ins_pipe( pipe_cmov_reg );
6805 %}
6806 
6807 // Conditional move
6808 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
6809   predicate(VM_Version::supports_cmov() );
6810   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6811   ins_cost(200);
6812   format %{ "CMOV$cop $dst,$src\t# ptr" %}
6813   opcode(0x0F,0x40);
6814   ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6815   ins_pipe( pipe_cmov_reg );
6816 %}
6817 
6818 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
6819   predicate(VM_Version::supports_cmov() );
6820   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6821   ins_cost(200);
6822   expand %{
6823     cmovP_regU(cop, cr, dst, src);
6824   %}
6825 %}
6826 
6827 // DISABLED: Requires the ADLC to emit a bottom_type call that
6828 // correctly meets the two pointer arguments; one is an incoming
6829 // register but the other is a memory operand.  ALSO appears to
6830 // be buggy with implicit null checks.
6831 //
6832 //// Conditional move
6833 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
6834 //  predicate(VM_Version::supports_cmov() );
6835 //  match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6836 //  ins_cost(250);
6837 //  format %{ "CMOV$cop $dst,$src\t# ptr" %}
6838 //  opcode(0x0F,0x40);
6839 //  ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6840 //  ins_pipe( pipe_cmov_mem );
6841 //%}
6842 //
6843 //// Conditional move
6844 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
6845 //  predicate(VM_Version::supports_cmov() );
6846 //  match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6847 //  ins_cost(250);
6848 //  format %{ "CMOV$cop $dst,$src\t# ptr" %}
6849 //  opcode(0x0F,0x40);
6850 //  ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6851 //  ins_pipe( pipe_cmov_mem );
6852 //%}
6853 
6854 // Conditional move
6855 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
6856   predicate(UseSSE<=1);
6857   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6858   ins_cost(200);
6859   format %{ "FCMOV$cop $dst,$src\t# double" %}
6860   opcode(0xDA);
6861   ins_encode( enc_cmov_dpr(cop,src) );
6862   ins_pipe( pipe_cmovDPR_reg );
6863 %}
6864 
6865 // Conditional move
6866 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
6867   predicate(UseSSE==0);
6868   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6869   ins_cost(200);
6870   format %{ "FCMOV$cop $dst,$src\t# float" %}
6871   opcode(0xDA);
6872   ins_encode( enc_cmov_dpr(cop,src) );
6873   ins_pipe( pipe_cmovDPR_reg );
6874 %}
6875 
6876 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
6877 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
6878   predicate(UseSSE<=1);
6879   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6880   ins_cost(200);
6881   format %{ "Jn$cop   skip\n\t"
6882             "MOV    $dst,$src\t# double\n"
6883       "skip:" %}
6884   opcode (0xdd, 0x3);     /* DD D8+i or DD /3 */
6885   ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
6886   ins_pipe( pipe_cmovDPR_reg );
6887 %}
6888 
6889 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
6890 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
6891   predicate(UseSSE==0);
6892   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6893   ins_cost(200);
6894   format %{ "Jn$cop    skip\n\t"
6895             "MOV    $dst,$src\t# float\n"
6896       "skip:" %}
6897   opcode (0xdd, 0x3);     /* DD D8+i or DD /3 */
6898   ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
6899   ins_pipe( pipe_cmovDPR_reg );
6900 %}
6901 
6902 // No CMOVE with SSE/SSE2
6903 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
6904   predicate (UseSSE>=1);
6905   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6906   ins_cost(200);
6907   format %{ "Jn$cop   skip\n\t"
6908             "MOVSS  $dst,$src\t# float\n"
6909       "skip:" %}
6910   ins_encode %{
6911     Label skip;
6912     // Invert sense of branch from sense of CMOV
6913     __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6914     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6915     __ bind(skip);
6916   %}
6917   ins_pipe( pipe_slow );
6918 %}
6919 
6920 // No CMOVE with SSE/SSE2
6921 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
6922   predicate (UseSSE>=2);
6923   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6924   ins_cost(200);
6925   format %{ "Jn$cop   skip\n\t"
6926             "MOVSD  $dst,$src\t# float\n"
6927       "skip:" %}
6928   ins_encode %{
6929     Label skip;
6930     // Invert sense of branch from sense of CMOV
6931     __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6932     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6933     __ bind(skip);
6934   %}
6935   ins_pipe( pipe_slow );
6936 %}
6937 
6938 // unsigned version
6939 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
6940   predicate (UseSSE>=1);
6941   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6942   ins_cost(200);
6943   format %{ "Jn$cop   skip\n\t"
6944             "MOVSS  $dst,$src\t# float\n"
6945       "skip:" %}
6946   ins_encode %{
6947     Label skip;
6948     // Invert sense of branch from sense of CMOV
6949     __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6950     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6951     __ bind(skip);
6952   %}
6953   ins_pipe( pipe_slow );
6954 %}
6955 
6956 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
6957   predicate (UseSSE>=1);
6958   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6959   ins_cost(200);
6960   expand %{
6961     fcmovF_regU(cop, cr, dst, src);
6962   %}
6963 %}
6964 
6965 // unsigned version
6966 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
6967   predicate (UseSSE>=2);
6968   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6969   ins_cost(200);
6970   format %{ "Jn$cop   skip\n\t"
6971             "MOVSD  $dst,$src\t# float\n"
6972       "skip:" %}
6973   ins_encode %{
6974     Label skip;
6975     // Invert sense of branch from sense of CMOV
6976     __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6977     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6978     __ bind(skip);
6979   %}
6980   ins_pipe( pipe_slow );
6981 %}
6982 
6983 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
6984   predicate (UseSSE>=2);
6985   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6986   ins_cost(200);
6987   expand %{
6988     fcmovD_regU(cop, cr, dst, src);
6989   %}
6990 %}
6991 
6992 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
6993   predicate(VM_Version::supports_cmov() );
6994   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6995   ins_cost(200);
6996   format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
6997             "CMOV$cop $dst.hi,$src.hi" %}
6998   opcode(0x0F,0x40);
6999   ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7000   ins_pipe( pipe_cmov_reg_long );
7001 %}
7002 
7003 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7004   predicate(VM_Version::supports_cmov() );
7005   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7006   ins_cost(200);
7007   format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7008             "CMOV$cop $dst.hi,$src.hi" %}
7009   opcode(0x0F,0x40);
7010   ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7011   ins_pipe( pipe_cmov_reg_long );
7012 %}
7013 
7014 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7015   predicate(VM_Version::supports_cmov() );
7016   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7017   ins_cost(200);
7018   expand %{
7019     cmovL_regU(cop, cr, dst, src);
7020   %}
7021 %}
7022 
7023 //----------Arithmetic Instructions--------------------------------------------
7024 //----------Addition Instructions----------------------------------------------
7025 
7026 // Integer Addition Instructions
7027 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7028   match(Set dst (AddI dst src));
7029   effect(KILL cr);
7030 
7031   size(2);
7032   format %{ "ADD    $dst,$src" %}
7033   opcode(0x03);
7034   ins_encode( OpcP, RegReg( dst, src) );
7035   ins_pipe( ialu_reg_reg );
7036 %}
7037 
7038 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7039   match(Set dst (AddI dst src));
7040   effect(KILL cr);
7041 
7042   format %{ "ADD    $dst,$src" %}
7043   opcode(0x81, 0x00); /* /0 id */
7044   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7045   ins_pipe( ialu_reg );
7046 %}
7047 
7048 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7049   predicate(UseIncDec);
7050   match(Set dst (AddI dst src));
7051   effect(KILL cr);
7052 
7053   size(1);
7054   format %{ "INC    $dst" %}
7055   opcode(0x40); /*  */
7056   ins_encode( Opc_plus( primary, dst ) );
7057   ins_pipe( ialu_reg );
7058 %}
7059 
7060 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7061   match(Set dst (AddI src0 src1));
7062   ins_cost(110);
7063 
7064   format %{ "LEA    $dst,[$src0 + $src1]" %}
7065   opcode(0x8D); /* 0x8D /r */
7066   ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7067   ins_pipe( ialu_reg_reg );
7068 %}
7069 
7070 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7071   match(Set dst (AddP src0 src1));
7072   ins_cost(110);
7073 
7074   format %{ "LEA    $dst,[$src0 + $src1]\t# ptr" %}
7075   opcode(0x8D); /* 0x8D /r */
7076   ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7077   ins_pipe( ialu_reg_reg );
7078 %}
7079 
7080 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7081   predicate(UseIncDec);
7082   match(Set dst (AddI dst src));
7083   effect(KILL cr);
7084 
7085   size(1);
7086   format %{ "DEC    $dst" %}
7087   opcode(0x48); /*  */
7088   ins_encode( Opc_plus( primary, dst ) );
7089   ins_pipe( ialu_reg );
7090 %}
7091 
7092 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7093   match(Set dst (AddP dst src));
7094   effect(KILL cr);
7095 
7096   size(2);
7097   format %{ "ADD    $dst,$src" %}
7098   opcode(0x03);
7099   ins_encode( OpcP, RegReg( dst, src) );
7100   ins_pipe( ialu_reg_reg );
7101 %}
7102 
7103 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7104   match(Set dst (AddP dst src));
7105   effect(KILL cr);
7106 
7107   format %{ "ADD    $dst,$src" %}
7108   opcode(0x81,0x00); /* Opcode 81 /0 id */
7109   // ins_encode( RegImm( dst, src) );
7110   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7111   ins_pipe( ialu_reg );
7112 %}
7113 
7114 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7115   match(Set dst (AddI dst (LoadI src)));
7116   effect(KILL cr);
7117 
7118   ins_cost(125);
7119   format %{ "ADD    $dst,$src" %}
7120   opcode(0x03);
7121   ins_encode( OpcP, RegMem( dst, src) );
7122   ins_pipe( ialu_reg_mem );
7123 %}
7124 
7125 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7126   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7127   effect(KILL cr);
7128 
7129   ins_cost(150);
7130   format %{ "ADD    $dst,$src" %}
7131   opcode(0x01);  /* Opcode 01 /r */
7132   ins_encode( OpcP, RegMem( src, dst ) );
7133   ins_pipe( ialu_mem_reg );
7134 %}
7135 
7136 // Add Memory with Immediate
7137 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7138   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7139   effect(KILL cr);
7140 
7141   ins_cost(125);
7142   format %{ "ADD    $dst,$src" %}
7143   opcode(0x81);               /* Opcode 81 /0 id */
7144   ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7145   ins_pipe( ialu_mem_imm );
7146 %}
7147 
7148 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7149   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7150   effect(KILL cr);
7151 
7152   ins_cost(125);
7153   format %{ "INC    $dst" %}
7154   opcode(0xFF);               /* Opcode FF /0 */
7155   ins_encode( OpcP, RMopc_Mem(0x00,dst));
7156   ins_pipe( ialu_mem_imm );
7157 %}
7158 
7159 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7160   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7161   effect(KILL cr);
7162 
7163   ins_cost(125);
7164   format %{ "DEC    $dst" %}
7165   opcode(0xFF);               /* Opcode FF /1 */
7166   ins_encode( OpcP, RMopc_Mem(0x01,dst));
7167   ins_pipe( ialu_mem_imm );
7168 %}
7169 
7170 
7171 instruct checkCastPP( eRegP dst ) %{
7172   match(Set dst (CheckCastPP dst));
7173 
7174   size(0);
7175   format %{ "#checkcastPP of $dst" %}
7176   ins_encode( /*empty encoding*/ );
7177   ins_pipe( empty );
7178 %}
7179 
7180 instruct castPP( eRegP dst ) %{
7181   match(Set dst (CastPP dst));
7182   format %{ "#castPP of $dst" %}
7183   ins_encode( /*empty encoding*/ );
7184   ins_pipe( empty );
7185 %}
7186 
7187 instruct castII( rRegI dst ) %{
7188   match(Set dst (CastII dst));
7189   format %{ "#castII of $dst" %}
7190   ins_encode( /*empty encoding*/ );
7191   ins_cost(0);
7192   ins_pipe( empty );
7193 %}
7194 
7195 
7196 // Load-locked - same as a regular pointer load when used with compare-swap
7197 instruct loadPLocked(eRegP dst, memory mem) %{
7198   match(Set dst (LoadPLocked mem));
7199 
7200   ins_cost(125);
7201   format %{ "MOV    $dst,$mem\t# Load ptr. locked" %}
7202   opcode(0x8B);
7203   ins_encode( OpcP, RegMem(dst,mem));
7204   ins_pipe( ialu_reg_mem );
7205 %}
7206 
7207 // Conditional-store of the updated heap-top.
7208 // Used during allocation of the shared heap.
7209 // Sets flags (EQ) on success.  Implemented with a CMPXCHG on Intel.
7210 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7211   match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7212   // EAX is killed if there is contention, but then it's also unused.
7213   // In the common case of no contention, EAX holds the new oop address.
7214   format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7215   ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7216   ins_pipe( pipe_cmpxchg );
7217 %}
7218 
7219 // Conditional-store of an int value.
7220 // ZF flag is set on success, reset otherwise.  Implemented with a CMPXCHG on Intel.
7221 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7222   match(Set cr (StoreIConditional mem (Binary oldval newval)));
7223   effect(KILL oldval);
7224   format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7225   ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7226   ins_pipe( pipe_cmpxchg );
7227 %}
7228 
7229 // Conditional-store of a long value.
7230 // ZF flag is set on success, reset otherwise.  Implemented with a CMPXCHG8 on Intel.
7231 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7232   match(Set cr (StoreLConditional mem (Binary oldval newval)));
7233   effect(KILL oldval);
7234   format %{ "XCHG   EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7235             "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7236             "XCHG   EBX,ECX"
7237   %}
7238   ins_encode %{
7239     // Note: we need to swap rbx, and rcx before and after the
7240     //       cmpxchg8 instruction because the instruction uses
7241     //       rcx as the high order word of the new value to store but
7242     //       our register encoding uses rbx.
7243     __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7244     if( os::is_MP() )
7245       __ lock();
7246     __ cmpxchg8($mem$$Address);
7247     __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7248   %}
7249   ins_pipe( pipe_cmpxchg );
7250 %}
7251 
7252 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7253 
7254 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7255   predicate(VM_Version::supports_cx8());
7256   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7257   effect(KILL cr, KILL oldval);
7258   format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7259             "MOV    $res,0\n\t"
7260             "JNE,s  fail\n\t"
7261             "MOV    $res,1\n"
7262           "fail:" %}
7263   ins_encode( enc_cmpxchg8(mem_ptr),
7264               enc_flags_ne_to_boolean(res) );
7265   ins_pipe( pipe_cmpxchg );
7266 %}
7267 
7268 instruct compareAndSwapP( rRegI res,  pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7269   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7270   effect(KILL cr, KILL oldval);
7271   format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7272             "MOV    $res,0\n\t"
7273             "JNE,s  fail\n\t"
7274             "MOV    $res,1\n"
7275           "fail:" %}
7276   ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7277   ins_pipe( pipe_cmpxchg );
7278 %}
7279 
7280 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7281   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7282   effect(KILL cr, KILL oldval);
7283   format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7284             "MOV    $res,0\n\t"
7285             "JNE,s  fail\n\t"
7286             "MOV    $res,1\n"
7287           "fail:" %}
7288   ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7289   ins_pipe( pipe_cmpxchg );
7290 %}
7291 
7292 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7293   predicate(n->as_LoadStore()->result_not_used());
7294   match(Set dummy (GetAndAddI mem add));
7295   effect(KILL cr);
7296   format %{ "ADDL  [$mem],$add" %}
7297   ins_encode %{
7298     if (os::is_MP()) { __ lock(); }
7299     __ addl($mem$$Address, $add$$constant);
7300   %}
7301   ins_pipe( pipe_cmpxchg );
7302 %}
7303 
7304 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7305   match(Set newval (GetAndAddI mem newval));
7306   effect(KILL cr);
7307   format %{ "XADDL  [$mem],$newval" %}
7308   ins_encode %{
7309     if (os::is_MP()) { __ lock(); }
7310     __ xaddl($mem$$Address, $newval$$Register);
7311   %}
7312   ins_pipe( pipe_cmpxchg );
7313 %}
7314 
7315 instruct xchgI( memory mem, rRegI newval) %{
7316   match(Set newval (GetAndSetI mem newval));
7317   format %{ "XCHGL  $newval,[$mem]" %}
7318   ins_encode %{
7319     __ xchgl($newval$$Register, $mem$$Address);
7320   %}
7321   ins_pipe( pipe_cmpxchg );
7322 %}
7323 
7324 instruct xchgP( memory mem, pRegP newval) %{
7325   match(Set newval (GetAndSetP mem newval));
7326   format %{ "XCHGL  $newval,[$mem]" %}
7327   ins_encode %{
7328     __ xchgl($newval$$Register, $mem$$Address);
7329   %}
7330   ins_pipe( pipe_cmpxchg );
7331 %}
7332 
7333 //----------Subtraction Instructions-------------------------------------------
7334 
7335 // Integer Subtraction Instructions
7336 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7337   match(Set dst (SubI dst src));
7338   effect(KILL cr);
7339 
7340   size(2);
7341   format %{ "SUB    $dst,$src" %}
7342   opcode(0x2B);
7343   ins_encode( OpcP, RegReg( dst, src) );
7344   ins_pipe( ialu_reg_reg );
7345 %}
7346 
7347 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7348   match(Set dst (SubI dst src));
7349   effect(KILL cr);
7350 
7351   format %{ "SUB    $dst,$src" %}
7352   opcode(0x81,0x05);  /* Opcode 81 /5 */
7353   // ins_encode( RegImm( dst, src) );
7354   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7355   ins_pipe( ialu_reg );
7356 %}
7357 
7358 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7359   match(Set dst (SubI dst (LoadI src)));
7360   effect(KILL cr);
7361 
7362   ins_cost(125);
7363   format %{ "SUB    $dst,$src" %}
7364   opcode(0x2B);
7365   ins_encode( OpcP, RegMem( dst, src) );
7366   ins_pipe( ialu_reg_mem );
7367 %}
7368 
7369 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7370   match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7371   effect(KILL cr);
7372 
7373   ins_cost(150);
7374   format %{ "SUB    $dst,$src" %}
7375   opcode(0x29);  /* Opcode 29 /r */
7376   ins_encode( OpcP, RegMem( src, dst ) );
7377   ins_pipe( ialu_mem_reg );
7378 %}
7379 
7380 // Subtract from a pointer
7381 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7382   match(Set dst (AddP dst (SubI zero src)));
7383   effect(KILL cr);
7384 
7385   size(2);
7386   format %{ "SUB    $dst,$src" %}
7387   opcode(0x2B);
7388   ins_encode( OpcP, RegReg( dst, src) );
7389   ins_pipe( ialu_reg_reg );
7390 %}
7391 
7392 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7393   match(Set dst (SubI zero dst));
7394   effect(KILL cr);
7395 
7396   size(2);
7397   format %{ "NEG    $dst" %}
7398   opcode(0xF7,0x03);  // Opcode F7 /3
7399   ins_encode( OpcP, RegOpc( dst ) );
7400   ins_pipe( ialu_reg );
7401 %}
7402 
7403 //----------Multiplication/Division Instructions-------------------------------
7404 // Integer Multiplication Instructions
7405 // Multiply Register
7406 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7407   match(Set dst (MulI dst src));
7408   effect(KILL cr);
7409 
7410   size(3);
7411   ins_cost(300);
7412   format %{ "IMUL   $dst,$src" %}
7413   opcode(0xAF, 0x0F);
7414   ins_encode( OpcS, OpcP, RegReg( dst, src) );
7415   ins_pipe( ialu_reg_reg_alu0 );
7416 %}
7417 
7418 // Multiply 32-bit Immediate
7419 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7420   match(Set dst (MulI src imm));
7421   effect(KILL cr);
7422 
7423   ins_cost(300);
7424   format %{ "IMUL   $dst,$src,$imm" %}
7425   opcode(0x69);  /* 69 /r id */
7426   ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7427   ins_pipe( ialu_reg_reg_alu0 );
7428 %}
7429 
7430 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7431   match(Set dst src);
7432   effect(KILL cr);
7433 
7434   // Note that this is artificially increased to make it more expensive than loadConL
7435   ins_cost(250);
7436   format %{ "MOV    EAX,$src\t// low word only" %}
7437   opcode(0xB8);
7438   ins_encode( LdImmL_Lo(dst, src) );
7439   ins_pipe( ialu_reg_fat );
7440 %}
7441 
7442 // Multiply by 32-bit Immediate, taking the shifted high order results
7443 //  (special case for shift by 32)
7444 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7445   match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7446   predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7447              _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7448              _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7449   effect(USE src1, KILL cr);
7450 
7451   // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7452   ins_cost(0*100 + 1*400 - 150);
7453   format %{ "IMUL   EDX:EAX,$src1" %}
7454   ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7455   ins_pipe( pipe_slow );
7456 %}
7457 
7458 // Multiply by 32-bit Immediate, taking the shifted high order results
7459 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7460   match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7461   predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7462              _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7463              _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7464   effect(USE src1, KILL cr);
7465 
7466   // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7467   ins_cost(1*100 + 1*400 - 150);
7468   format %{ "IMUL   EDX:EAX,$src1\n\t"
7469             "SAR    EDX,$cnt-32" %}
7470   ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7471   ins_pipe( pipe_slow );
7472 %}
7473 
7474 // Multiply Memory 32-bit Immediate
7475 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7476   match(Set dst (MulI (LoadI src) imm));
7477   effect(KILL cr);
7478 
7479   ins_cost(300);
7480   format %{ "IMUL   $dst,$src,$imm" %}
7481   opcode(0x69);  /* 69 /r id */
7482   ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
7483   ins_pipe( ialu_reg_mem_alu0 );
7484 %}
7485 
7486 // Multiply Memory
7487 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
7488   match(Set dst (MulI dst (LoadI src)));
7489   effect(KILL cr);
7490 
7491   ins_cost(350);
7492   format %{ "IMUL   $dst,$src" %}
7493   opcode(0xAF, 0x0F);
7494   ins_encode( OpcS, OpcP, RegMem( dst, src) );
7495   ins_pipe( ialu_reg_mem_alu0 );
7496 %}
7497 
7498 // Multiply Register Int to Long
7499 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
7500   // Basic Idea: long = (long)int * (long)int
7501   match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
7502   effect(DEF dst, USE src, USE src1, KILL flags);
7503 
7504   ins_cost(300);
7505   format %{ "IMUL   $dst,$src1" %}
7506 
7507   ins_encode( long_int_multiply( dst, src1 ) );
7508   ins_pipe( ialu_reg_reg_alu0 );
7509 %}
7510 
7511 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
7512   // Basic Idea:  long = (int & 0xffffffffL) * (int & 0xffffffffL)
7513   match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
7514   effect(KILL flags);
7515 
7516   ins_cost(300);
7517   format %{ "MUL    $dst,$src1" %}
7518 
7519   ins_encode( long_uint_multiply(dst, src1) );
7520   ins_pipe( ialu_reg_reg_alu0 );
7521 %}
7522 
7523 // Multiply Register Long
7524 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7525   match(Set dst (MulL dst src));
7526   effect(KILL cr, TEMP tmp);
7527   ins_cost(4*100+3*400);
7528 // Basic idea: lo(result) = lo(x_lo * y_lo)
7529 //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
7530   format %{ "MOV    $tmp,$src.lo\n\t"
7531             "IMUL   $tmp,EDX\n\t"
7532             "MOV    EDX,$src.hi\n\t"
7533             "IMUL   EDX,EAX\n\t"
7534             "ADD    $tmp,EDX\n\t"
7535             "MUL    EDX:EAX,$src.lo\n\t"
7536             "ADD    EDX,$tmp" %}
7537   ins_encode( long_multiply( dst, src, tmp ) );
7538   ins_pipe( pipe_slow );
7539 %}
7540 
7541 // Multiply Register Long where the left operand's high 32 bits are zero
7542 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7543   predicate(is_operand_hi32_zero(n->in(1)));
7544   match(Set dst (MulL dst src));
7545   effect(KILL cr, TEMP tmp);
7546   ins_cost(2*100+2*400);
7547 // Basic idea: lo(result) = lo(x_lo * y_lo)
7548 //             hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
7549   format %{ "MOV    $tmp,$src.hi\n\t"
7550             "IMUL   $tmp,EAX\n\t"
7551             "MUL    EDX:EAX,$src.lo\n\t"
7552             "ADD    EDX,$tmp" %}
7553   ins_encode %{
7554     __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
7555     __ imull($tmp$$Register, rax);
7556     __ mull($src$$Register);
7557     __ addl(rdx, $tmp$$Register);
7558   %}
7559   ins_pipe( pipe_slow );
7560 %}
7561 
7562 // Multiply Register Long where the right operand's high 32 bits are zero
7563 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7564   predicate(is_operand_hi32_zero(n->in(2)));
7565   match(Set dst (MulL dst src));
7566   effect(KILL cr, TEMP tmp);
7567   ins_cost(2*100+2*400);
7568 // Basic idea: lo(result) = lo(x_lo * y_lo)
7569 //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
7570   format %{ "MOV    $tmp,$src.lo\n\t"
7571             "IMUL   $tmp,EDX\n\t"
7572             "MUL    EDX:EAX,$src.lo\n\t"
7573             "ADD    EDX,$tmp" %}
7574   ins_encode %{
7575     __ movl($tmp$$Register, $src$$Register);
7576     __ imull($tmp$$Register, rdx);
7577     __ mull($src$$Register);
7578     __ addl(rdx, $tmp$$Register);
7579   %}
7580   ins_pipe( pipe_slow );
7581 %}
7582 
7583 // Multiply Register Long where the left and the right operands' high 32 bits are zero
7584 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
7585   predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
7586   match(Set dst (MulL dst src));
7587   effect(KILL cr);
7588   ins_cost(1*400);
7589 // Basic idea: lo(result) = lo(x_lo * y_lo)
7590 //             hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
7591   format %{ "MUL    EDX:EAX,$src.lo\n\t" %}
7592   ins_encode %{
7593     __ mull($src$$Register);
7594   %}
7595   ins_pipe( pipe_slow );
7596 %}
7597 
7598 // Multiply Register Long by small constant
7599 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
7600   match(Set dst (MulL dst src));
7601   effect(KILL cr, TEMP tmp);
7602   ins_cost(2*100+2*400);
7603   size(12);
7604 // Basic idea: lo(result) = lo(src * EAX)
7605 //             hi(result) = hi(src * EAX) + lo(src * EDX)
7606   format %{ "IMUL   $tmp,EDX,$src\n\t"
7607             "MOV    EDX,$src\n\t"
7608             "MUL    EDX\t# EDX*EAX -> EDX:EAX\n\t"
7609             "ADD    EDX,$tmp" %}
7610   ins_encode( long_multiply_con( dst, src, tmp ) );
7611   ins_pipe( pipe_slow );
7612 %}
7613 
7614 // Integer DIV with Register
7615 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
7616   match(Set rax (DivI rax div));
7617   effect(KILL rdx, KILL cr);
7618   size(26);
7619   ins_cost(30*100+10*100);
7620   format %{ "CMP    EAX,0x80000000\n\t"
7621             "JNE,s  normal\n\t"
7622             "XOR    EDX,EDX\n\t"
7623             "CMP    ECX,-1\n\t"
7624             "JE,s   done\n"
7625     "normal: CDQ\n\t"
7626             "IDIV   $div\n\t"
7627     "done:"        %}
7628   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
7629   ins_encode( cdq_enc, OpcP, RegOpc(div) );
7630   ins_pipe( ialu_reg_reg_alu0 );
7631 %}
7632 
7633 // Divide Register Long
7634 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
7635   match(Set dst (DivL src1 src2));
7636   effect( KILL cr, KILL cx, KILL bx );
7637   ins_cost(10000);
7638   format %{ "PUSH   $src1.hi\n\t"
7639             "PUSH   $src1.lo\n\t"
7640             "PUSH   $src2.hi\n\t"
7641             "PUSH   $src2.lo\n\t"
7642             "CALL   SharedRuntime::ldiv\n\t"
7643             "ADD    ESP,16" %}
7644   ins_encode( long_div(src1,src2) );
7645   ins_pipe( pipe_slow );
7646 %}
7647 
7648 // Integer DIVMOD with Register, both quotient and mod results
7649 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
7650   match(DivModI rax div);
7651   effect(KILL cr);
7652   size(26);
7653   ins_cost(30*100+10*100);
7654   format %{ "CMP    EAX,0x80000000\n\t"
7655             "JNE,s  normal\n\t"
7656             "XOR    EDX,EDX\n\t"
7657             "CMP    ECX,-1\n\t"
7658             "JE,s   done\n"
7659     "normal: CDQ\n\t"
7660             "IDIV   $div\n\t"
7661     "done:"        %}
7662   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
7663   ins_encode( cdq_enc, OpcP, RegOpc(div) );
7664   ins_pipe( pipe_slow );
7665 %}
7666 
7667 // Integer MOD with Register
7668 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
7669   match(Set rdx (ModI rax div));
7670   effect(KILL rax, KILL cr);
7671 
7672   size(26);
7673   ins_cost(300);
7674   format %{ "CDQ\n\t"
7675             "IDIV   $div" %}
7676   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
7677   ins_encode( cdq_enc, OpcP, RegOpc(div) );
7678   ins_pipe( ialu_reg_reg_alu0 );
7679 %}
7680 
7681 // Remainder Register Long
7682 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
7683   match(Set dst (ModL src1 src2));
7684   effect( KILL cr, KILL cx, KILL bx );
7685   ins_cost(10000);
7686   format %{ "PUSH   $src1.hi\n\t"
7687             "PUSH   $src1.lo\n\t"
7688             "PUSH   $src2.hi\n\t"
7689             "PUSH   $src2.lo\n\t"
7690             "CALL   SharedRuntime::lrem\n\t"
7691             "ADD    ESP,16" %}
7692   ins_encode( long_mod(src1,src2) );
7693   ins_pipe( pipe_slow );
7694 %}
7695 
7696 // Divide Register Long (no special case since divisor != -1)
7697 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
7698   match(Set dst (DivL dst imm));
7699   effect( TEMP tmp, TEMP tmp2, KILL cr );
7700   ins_cost(1000);
7701   format %{ "MOV    $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
7702             "XOR    $tmp2,$tmp2\n\t"
7703             "CMP    $tmp,EDX\n\t"
7704             "JA,s   fast\n\t"
7705             "MOV    $tmp2,EAX\n\t"
7706             "MOV    EAX,EDX\n\t"
7707             "MOV    EDX,0\n\t"
7708             "JLE,s  pos\n\t"
7709             "LNEG   EAX : $tmp2\n\t"
7710             "DIV    $tmp # unsigned division\n\t"
7711             "XCHG   EAX,$tmp2\n\t"
7712             "DIV    $tmp\n\t"
7713             "LNEG   $tmp2 : EAX\n\t"
7714             "JMP,s  done\n"
7715     "pos:\n\t"
7716             "DIV    $tmp\n\t"
7717             "XCHG   EAX,$tmp2\n"
7718     "fast:\n\t"
7719             "DIV    $tmp\n"
7720     "done:\n\t"
7721             "MOV    EDX,$tmp2\n\t"
7722             "NEG    EDX:EAX # if $imm < 0" %}
7723   ins_encode %{
7724     int con = (int)$imm$$constant;
7725     assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
7726     int pcon = (con > 0) ? con : -con;
7727     Label Lfast, Lpos, Ldone;
7728 
7729     __ movl($tmp$$Register, pcon);
7730     __ xorl($tmp2$$Register,$tmp2$$Register);
7731     __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
7732     __ jccb(Assembler::above, Lfast); // result fits into 32 bit
7733 
7734     __ movl($tmp2$$Register, $dst$$Register); // save
7735     __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7736     __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
7737     __ jccb(Assembler::lessEqual, Lpos); // result is positive
7738 
7739     // Negative dividend.
7740     // convert value to positive to use unsigned division
7741     __ lneg($dst$$Register, $tmp2$$Register);
7742     __ divl($tmp$$Register);
7743     __ xchgl($dst$$Register, $tmp2$$Register);
7744     __ divl($tmp$$Register);
7745     // revert result back to negative
7746     __ lneg($tmp2$$Register, $dst$$Register);
7747     __ jmpb(Ldone);
7748 
7749     __ bind(Lpos);
7750     __ divl($tmp$$Register); // Use unsigned division
7751     __ xchgl($dst$$Register, $tmp2$$Register);
7752     // Fallthrow for final divide, tmp2 has 32 bit hi result
7753 
7754     __ bind(Lfast);
7755     // fast path: src is positive
7756     __ divl($tmp$$Register); // Use unsigned division
7757 
7758     __ bind(Ldone);
7759     __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
7760     if (con < 0) {
7761       __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
7762     }
7763   %}
7764   ins_pipe( pipe_slow );
7765 %}
7766 
7767 // Remainder Register Long (remainder fit into 32 bits)
7768 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
7769   match(Set dst (ModL dst imm));
7770   effect( TEMP tmp, TEMP tmp2, KILL cr );
7771   ins_cost(1000);
7772   format %{ "MOV    $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
7773             "CMP    $tmp,EDX\n\t"
7774             "JA,s   fast\n\t"
7775             "MOV    $tmp2,EAX\n\t"
7776             "MOV    EAX,EDX\n\t"
7777             "MOV    EDX,0\n\t"
7778             "JLE,s  pos\n\t"
7779             "LNEG   EAX : $tmp2\n\t"
7780             "DIV    $tmp # unsigned division\n\t"
7781             "MOV    EAX,$tmp2\n\t"
7782             "DIV    $tmp\n\t"
7783             "NEG    EDX\n\t"
7784             "JMP,s  done\n"
7785     "pos:\n\t"
7786             "DIV    $tmp\n\t"
7787             "MOV    EAX,$tmp2\n"
7788     "fast:\n\t"
7789             "DIV    $tmp\n"
7790     "done:\n\t"
7791             "MOV    EAX,EDX\n\t"
7792             "SAR    EDX,31\n\t" %}
7793   ins_encode %{
7794     int con = (int)$imm$$constant;
7795     assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
7796     int pcon = (con > 0) ? con : -con;
7797     Label  Lfast, Lpos, Ldone;
7798 
7799     __ movl($tmp$$Register, pcon);
7800     __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
7801     __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
7802 
7803     __ movl($tmp2$$Register, $dst$$Register); // save
7804     __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7805     __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
7806     __ jccb(Assembler::lessEqual, Lpos); // result is positive
7807 
7808     // Negative dividend.
7809     // convert value to positive to use unsigned division
7810     __ lneg($dst$$Register, $tmp2$$Register);
7811     __ divl($tmp$$Register);
7812     __ movl($dst$$Register, $tmp2$$Register);
7813     __ divl($tmp$$Register);
7814     // revert remainder back to negative
7815     __ negl(HIGH_FROM_LOW($dst$$Register));
7816     __ jmpb(Ldone);
7817 
7818     __ bind(Lpos);
7819     __ divl($tmp$$Register);
7820     __ movl($dst$$Register, $tmp2$$Register);
7821 
7822     __ bind(Lfast);
7823     // fast path: src is positive
7824     __ divl($tmp$$Register);
7825 
7826     __ bind(Ldone);
7827     __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7828     __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
7829 
7830   %}
7831   ins_pipe( pipe_slow );
7832 %}
7833 
7834 // Integer Shift Instructions
7835 // Shift Left by one
7836 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7837   match(Set dst (LShiftI dst shift));
7838   effect(KILL cr);
7839 
7840   size(2);
7841   format %{ "SHL    $dst,$shift" %}
7842   opcode(0xD1, 0x4);  /* D1 /4 */
7843   ins_encode( OpcP, RegOpc( dst ) );
7844   ins_pipe( ialu_reg );
7845 %}
7846 
7847 // Shift Left by 8-bit immediate
7848 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7849   match(Set dst (LShiftI dst shift));
7850   effect(KILL cr);
7851 
7852   size(3);
7853   format %{ "SHL    $dst,$shift" %}
7854   opcode(0xC1, 0x4);  /* C1 /4 ib */
7855   ins_encode( RegOpcImm( dst, shift) );
7856   ins_pipe( ialu_reg );
7857 %}
7858 
7859 // Shift Left by variable
7860 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7861   match(Set dst (LShiftI dst shift));
7862   effect(KILL cr);
7863 
7864   size(2);
7865   format %{ "SHL    $dst,$shift" %}
7866   opcode(0xD3, 0x4);  /* D3 /4 */
7867   ins_encode( OpcP, RegOpc( dst ) );
7868   ins_pipe( ialu_reg_reg );
7869 %}
7870 
7871 // Arithmetic shift right by one
7872 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7873   match(Set dst (RShiftI dst shift));
7874   effect(KILL cr);
7875 
7876   size(2);
7877   format %{ "SAR    $dst,$shift" %}
7878   opcode(0xD1, 0x7);  /* D1 /7 */
7879   ins_encode( OpcP, RegOpc( dst ) );
7880   ins_pipe( ialu_reg );
7881 %}
7882 
7883 // Arithmetic shift right by one
7884 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
7885   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7886   effect(KILL cr);
7887   format %{ "SAR    $dst,$shift" %}
7888   opcode(0xD1, 0x7);  /* D1 /7 */
7889   ins_encode( OpcP, RMopc_Mem(secondary,dst) );
7890   ins_pipe( ialu_mem_imm );
7891 %}
7892 
7893 // Arithmetic Shift Right by 8-bit immediate
7894 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7895   match(Set dst (RShiftI dst shift));
7896   effect(KILL cr);
7897 
7898   size(3);
7899   format %{ "SAR    $dst,$shift" %}
7900   opcode(0xC1, 0x7);  /* C1 /7 ib */
7901   ins_encode( RegOpcImm( dst, shift ) );
7902   ins_pipe( ialu_mem_imm );
7903 %}
7904 
7905 // Arithmetic Shift Right by 8-bit immediate
7906 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
7907   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7908   effect(KILL cr);
7909 
7910   format %{ "SAR    $dst,$shift" %}
7911   opcode(0xC1, 0x7);  /* C1 /7 ib */
7912   ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
7913   ins_pipe( ialu_mem_imm );
7914 %}
7915 
7916 // Arithmetic Shift Right by variable
7917 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7918   match(Set dst (RShiftI dst shift));
7919   effect(KILL cr);
7920 
7921   size(2);
7922   format %{ "SAR    $dst,$shift" %}
7923   opcode(0xD3, 0x7);  /* D3 /7 */
7924   ins_encode( OpcP, RegOpc( dst ) );
7925   ins_pipe( ialu_reg_reg );
7926 %}
7927 
7928 // Logical shift right by one
7929 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7930   match(Set dst (URShiftI dst shift));
7931   effect(KILL cr);
7932 
7933   size(2);
7934   format %{ "SHR    $dst,$shift" %}
7935   opcode(0xD1, 0x5);  /* D1 /5 */
7936   ins_encode( OpcP, RegOpc( dst ) );
7937   ins_pipe( ialu_reg );
7938 %}
7939 
7940 // Logical Shift Right by 8-bit immediate
7941 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7942   match(Set dst (URShiftI dst shift));
7943   effect(KILL cr);
7944 
7945   size(3);
7946   format %{ "SHR    $dst,$shift" %}
7947   opcode(0xC1, 0x5);  /* C1 /5 ib */
7948   ins_encode( RegOpcImm( dst, shift) );
7949   ins_pipe( ialu_reg );
7950 %}
7951 
7952 
7953 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
7954 // This idiom is used by the compiler for the i2b bytecode.
7955 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
7956   match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
7957 
7958   size(3);
7959   format %{ "MOVSX  $dst,$src :8" %}
7960   ins_encode %{
7961     __ movsbl($dst$$Register, $src$$Register);
7962   %}
7963   ins_pipe(ialu_reg_reg);
7964 %}
7965 
7966 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
7967 // This idiom is used by the compiler the i2s bytecode.
7968 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
7969   match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
7970 
7971   size(3);
7972   format %{ "MOVSX  $dst,$src :16" %}
7973   ins_encode %{
7974     __ movswl($dst$$Register, $src$$Register);
7975   %}
7976   ins_pipe(ialu_reg_reg);
7977 %}
7978 
7979 
7980 // Logical Shift Right by variable
7981 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7982   match(Set dst (URShiftI dst shift));
7983   effect(KILL cr);
7984 
7985   size(2);
7986   format %{ "SHR    $dst,$shift" %}
7987   opcode(0xD3, 0x5);  /* D3 /5 */
7988   ins_encode( OpcP, RegOpc( dst ) );
7989   ins_pipe( ialu_reg_reg );
7990 %}
7991 
7992 
7993 //----------Logical Instructions-----------------------------------------------
7994 //----------Integer Logical Instructions---------------------------------------
7995 // And Instructions
7996 // And Register with Register
7997 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7998   match(Set dst (AndI dst src));
7999   effect(KILL cr);
8000 
8001   size(2);
8002   format %{ "AND    $dst,$src" %}
8003   opcode(0x23);
8004   ins_encode( OpcP, RegReg( dst, src) );
8005   ins_pipe( ialu_reg_reg );
8006 %}
8007 
8008 // And Register with Immediate
8009 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8010   match(Set dst (AndI dst src));
8011   effect(KILL cr);
8012 
8013   format %{ "AND    $dst,$src" %}
8014   opcode(0x81,0x04);  /* Opcode 81 /4 */
8015   // ins_encode( RegImm( dst, src) );
8016   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8017   ins_pipe( ialu_reg );
8018 %}
8019 
8020 // And Register with Memory
8021 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8022   match(Set dst (AndI dst (LoadI src)));
8023   effect(KILL cr);
8024 
8025   ins_cost(125);
8026   format %{ "AND    $dst,$src" %}
8027   opcode(0x23);
8028   ins_encode( OpcP, RegMem( dst, src) );
8029   ins_pipe( ialu_reg_mem );
8030 %}
8031 
8032 // And Memory with Register
8033 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8034   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8035   effect(KILL cr);
8036 
8037   ins_cost(150);
8038   format %{ "AND    $dst,$src" %}
8039   opcode(0x21);  /* Opcode 21 /r */
8040   ins_encode( OpcP, RegMem( src, dst ) );
8041   ins_pipe( ialu_mem_reg );
8042 %}
8043 
8044 // And Memory with Immediate
8045 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8046   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8047   effect(KILL cr);
8048 
8049   ins_cost(125);
8050   format %{ "AND    $dst,$src" %}
8051   opcode(0x81, 0x4);  /* Opcode 81 /4 id */
8052   // ins_encode( MemImm( dst, src) );
8053   ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8054   ins_pipe( ialu_mem_imm );
8055 %}
8056 
8057 // BMI1 instructions
8058 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, eFlagsReg cr) %{
8059   match(Set dst (AndI (XorI src1 minus_1) src2));
8060   predicate(UseBMI1Instructions);
8061   effect(KILL cr);
8062 
8063   format %{ "ANDNL  $dst, $src1, $src2" %}
8064 
8065   ins_encode %{
8066     __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
8067   %}
8068   ins_pipe(ialu_reg);
8069 %}
8070 
8071 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, eFlagsReg cr) %{
8072   match(Set dst (AndI (XorI src1 minus_1) (LoadI src2) ));
8073   predicate(UseBMI1Instructions);
8074   effect(KILL cr);
8075 
8076   ins_cost(125);
8077   format %{ "ANDNL  $dst, $src1, $src2" %}
8078 
8079   ins_encode %{
8080     __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
8081   %}
8082   ins_pipe(ialu_reg_mem);
8083 %}
8084 
8085 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, eFlagsReg cr) %{
8086   match(Set dst (AndI (SubI imm_zero src) src));
8087   predicate(UseBMI1Instructions);
8088   effect(KILL cr);
8089 
8090   format %{ "BLSIL  $dst, $src" %}
8091 
8092   ins_encode %{
8093     __ blsil($dst$$Register, $src$$Register);
8094   %}
8095   ins_pipe(ialu_reg);
8096 %}
8097 
8098 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, eFlagsReg cr) %{
8099   match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
8100   predicate(UseBMI1Instructions);
8101   effect(KILL cr);
8102 
8103   ins_cost(125);
8104   format %{ "BLSIL  $dst, $src" %}
8105 
8106   ins_encode %{
8107     __ blsil($dst$$Register, $src$$Address);
8108   %}
8109   ins_pipe(ialu_reg_mem);
8110 %}
8111 
8112 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
8113 %{
8114   match(Set dst (XorI (AddI src minus_1) src));
8115   predicate(UseBMI1Instructions);
8116   effect(KILL cr);
8117 
8118   format %{ "BLSMSKL $dst, $src" %}
8119 
8120   ins_encode %{
8121     __ blsmskl($dst$$Register, $src$$Register);
8122   %}
8123 
8124   ins_pipe(ialu_reg);
8125 %}
8126 
8127 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)
8128 %{
8129   match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ));
8130   predicate(UseBMI1Instructions);
8131   effect(KILL cr);
8132 
8133   ins_cost(125);
8134   format %{ "BLSMSKL $dst, $src" %}
8135 
8136   ins_encode %{
8137     __ blsmskl($dst$$Register, $src$$Address);
8138   %}
8139 
8140   ins_pipe(ialu_reg_mem);
8141 %}
8142 
8143 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr)
8144 %{
8145   match(Set dst (AndI (AddI src minus_1) src) );
8146   predicate(UseBMI1Instructions);
8147   effect(KILL cr);
8148 
8149   format %{ "BLSRL  $dst, $src" %}
8150 
8151   ins_encode %{
8152     __ blsrl($dst$$Register, $src$$Register);
8153   %}
8154 
8155   ins_pipe(ialu_reg);
8156 %}
8157 
8158 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr)
8159 %{
8160   match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ));
8161   predicate(UseBMI1Instructions);
8162   effect(KILL cr);
8163 
8164   ins_cost(125);
8165   format %{ "BLSRL  $dst, $src" %}
8166 
8167   ins_encode %{
8168     __ blsrl($dst$$Register, $src$$Address);
8169   %}
8170 
8171   ins_pipe(ialu_reg_mem);
8172 %}
8173 
8174 // Or Instructions
8175 // Or Register with Register
8176 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8177   match(Set dst (OrI dst src));
8178   effect(KILL cr);
8179 
8180   size(2);
8181   format %{ "OR     $dst,$src" %}
8182   opcode(0x0B);
8183   ins_encode( OpcP, RegReg( dst, src) );
8184   ins_pipe( ialu_reg_reg );
8185 %}
8186 
8187 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8188   match(Set dst (OrI dst (CastP2X src)));
8189   effect(KILL cr);
8190 
8191   size(2);
8192   format %{ "OR     $dst,$src" %}
8193   opcode(0x0B);
8194   ins_encode( OpcP, RegReg( dst, src) );
8195   ins_pipe( ialu_reg_reg );
8196 %}
8197 
8198 
8199 // Or Register with Immediate
8200 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8201   match(Set dst (OrI dst src));
8202   effect(KILL cr);
8203 
8204   format %{ "OR     $dst,$src" %}
8205   opcode(0x81,0x01);  /* Opcode 81 /1 id */
8206   // ins_encode( RegImm( dst, src) );
8207   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8208   ins_pipe( ialu_reg );
8209 %}
8210 
8211 // Or Register with Memory
8212 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8213   match(Set dst (OrI dst (LoadI src)));
8214   effect(KILL cr);
8215 
8216   ins_cost(125);
8217   format %{ "OR     $dst,$src" %}
8218   opcode(0x0B);
8219   ins_encode( OpcP, RegMem( dst, src) );
8220   ins_pipe( ialu_reg_mem );
8221 %}
8222 
8223 // Or Memory with Register
8224 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8225   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8226   effect(KILL cr);
8227 
8228   ins_cost(150);
8229   format %{ "OR     $dst,$src" %}
8230   opcode(0x09);  /* Opcode 09 /r */
8231   ins_encode( OpcP, RegMem( src, dst ) );
8232   ins_pipe( ialu_mem_reg );
8233 %}
8234 
8235 // Or Memory with Immediate
8236 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8237   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8238   effect(KILL cr);
8239 
8240   ins_cost(125);
8241   format %{ "OR     $dst,$src" %}
8242   opcode(0x81,0x1);  /* Opcode 81 /1 id */
8243   // ins_encode( MemImm( dst, src) );
8244   ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8245   ins_pipe( ialu_mem_imm );
8246 %}
8247 
8248 // ROL/ROR
8249 // ROL expand
8250 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8251   effect(USE_DEF dst, USE shift, KILL cr);
8252 
8253   format %{ "ROL    $dst, $shift" %}
8254   opcode(0xD1, 0x0); /* Opcode D1 /0 */
8255   ins_encode( OpcP, RegOpc( dst ));
8256   ins_pipe( ialu_reg );
8257 %}
8258 
8259 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8260   effect(USE_DEF dst, USE shift, KILL cr);
8261 
8262   format %{ "ROL    $dst, $shift" %}
8263   opcode(0xC1, 0x0); /*Opcode /C1  /0  */
8264   ins_encode( RegOpcImm(dst, shift) );
8265   ins_pipe(ialu_reg);
8266 %}
8267 
8268 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8269   effect(USE_DEF dst, USE shift, KILL cr);
8270 
8271   format %{ "ROL    $dst, $shift" %}
8272   opcode(0xD3, 0x0);    /* Opcode D3 /0 */
8273   ins_encode(OpcP, RegOpc(dst));
8274   ins_pipe( ialu_reg_reg );
8275 %}
8276 // end of ROL expand
8277 
8278 // ROL 32bit by one once
8279 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8280   match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8281 
8282   expand %{
8283     rolI_eReg_imm1(dst, lshift, cr);
8284   %}
8285 %}
8286 
8287 // ROL 32bit var by imm8 once
8288 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8289   predicate(  0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8290   match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8291 
8292   expand %{
8293     rolI_eReg_imm8(dst, lshift, cr);
8294   %}
8295 %}
8296 
8297 // ROL 32bit var by var once
8298 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8299   match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8300 
8301   expand %{
8302     rolI_eReg_CL(dst, shift, cr);
8303   %}
8304 %}
8305 
8306 // ROL 32bit var by var once
8307 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8308   match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8309 
8310   expand %{
8311     rolI_eReg_CL(dst, shift, cr);
8312   %}
8313 %}
8314 
8315 // ROR expand
8316 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8317   effect(USE_DEF dst, USE shift, KILL cr);
8318 
8319   format %{ "ROR    $dst, $shift" %}
8320   opcode(0xD1,0x1);  /* Opcode D1 /1 */
8321   ins_encode( OpcP, RegOpc( dst ) );
8322   ins_pipe( ialu_reg );
8323 %}
8324 
8325 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8326   effect (USE_DEF dst, USE shift, KILL cr);
8327 
8328   format %{ "ROR    $dst, $shift" %}
8329   opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8330   ins_encode( RegOpcImm(dst, shift) );
8331   ins_pipe( ialu_reg );
8332 %}
8333 
8334 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8335   effect(USE_DEF dst, USE shift, KILL cr);
8336 
8337   format %{ "ROR    $dst, $shift" %}
8338   opcode(0xD3, 0x1);    /* Opcode D3 /1 */
8339   ins_encode(OpcP, RegOpc(dst));
8340   ins_pipe( ialu_reg_reg );
8341 %}
8342 // end of ROR expand
8343 
8344 // ROR right once
8345 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8346   match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8347 
8348   expand %{
8349     rorI_eReg_imm1(dst, rshift, cr);
8350   %}
8351 %}
8352 
8353 // ROR 32bit by immI8 once
8354 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8355   predicate(  0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8356   match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8357 
8358   expand %{
8359     rorI_eReg_imm8(dst, rshift, cr);
8360   %}
8361 %}
8362 
8363 // ROR 32bit var by var once
8364 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8365   match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8366 
8367   expand %{
8368     rorI_eReg_CL(dst, shift, cr);
8369   %}
8370 %}
8371 
8372 // ROR 32bit var by var once
8373 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8374   match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8375 
8376   expand %{
8377     rorI_eReg_CL(dst, shift, cr);
8378   %}
8379 %}
8380 
8381 // Xor Instructions
8382 // Xor Register with Register
8383 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8384   match(Set dst (XorI dst src));
8385   effect(KILL cr);
8386 
8387   size(2);
8388   format %{ "XOR    $dst,$src" %}
8389   opcode(0x33);
8390   ins_encode( OpcP, RegReg( dst, src) );
8391   ins_pipe( ialu_reg_reg );
8392 %}
8393 
8394 // Xor Register with Immediate -1
8395 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8396   match(Set dst (XorI dst imm));  
8397 
8398   size(2);
8399   format %{ "NOT    $dst" %}  
8400   ins_encode %{
8401      __ notl($dst$$Register);
8402   %}
8403   ins_pipe( ialu_reg );
8404 %}
8405 
8406 // Xor Register with Immediate
8407 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8408   match(Set dst (XorI dst src));
8409   effect(KILL cr);
8410 
8411   format %{ "XOR    $dst,$src" %}
8412   opcode(0x81,0x06);  /* Opcode 81 /6 id */
8413   // ins_encode( RegImm( dst, src) );
8414   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8415   ins_pipe( ialu_reg );
8416 %}
8417 
8418 // Xor Register with Memory
8419 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8420   match(Set dst (XorI dst (LoadI src)));
8421   effect(KILL cr);
8422 
8423   ins_cost(125);
8424   format %{ "XOR    $dst,$src" %}
8425   opcode(0x33);
8426   ins_encode( OpcP, RegMem(dst, src) );
8427   ins_pipe( ialu_reg_mem );
8428 %}
8429 
8430 // Xor Memory with Register
8431 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8432   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8433   effect(KILL cr);
8434 
8435   ins_cost(150);
8436   format %{ "XOR    $dst,$src" %}
8437   opcode(0x31);  /* Opcode 31 /r */
8438   ins_encode( OpcP, RegMem( src, dst ) );
8439   ins_pipe( ialu_mem_reg );
8440 %}
8441 
8442 // Xor Memory with Immediate
8443 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8444   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8445   effect(KILL cr);
8446 
8447   ins_cost(125);
8448   format %{ "XOR    $dst,$src" %}
8449   opcode(0x81,0x6);  /* Opcode 81 /6 id */
8450   ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8451   ins_pipe( ialu_mem_imm );
8452 %}
8453 
8454 //----------Convert Int to Boolean---------------------------------------------
8455 
8456 instruct movI_nocopy(rRegI dst, rRegI src) %{
8457   effect( DEF dst, USE src );
8458   format %{ "MOV    $dst,$src" %}
8459   ins_encode( enc_Copy( dst, src) );
8460   ins_pipe( ialu_reg_reg );
8461 %}
8462 
8463 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8464   effect( USE_DEF dst, USE src, KILL cr );
8465 
8466   size(4);
8467   format %{ "NEG    $dst\n\t"
8468             "ADC    $dst,$src" %}
8469   ins_encode( neg_reg(dst),
8470               OpcRegReg(0x13,dst,src) );
8471   ins_pipe( ialu_reg_reg_long );
8472 %}
8473 
8474 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8475   match(Set dst (Conv2B src));
8476 
8477   expand %{
8478     movI_nocopy(dst,src);
8479     ci2b(dst,src,cr);
8480   %}
8481 %}
8482 
8483 instruct movP_nocopy(rRegI dst, eRegP src) %{
8484   effect( DEF dst, USE src );
8485   format %{ "MOV    $dst,$src" %}
8486   ins_encode( enc_Copy( dst, src) );
8487   ins_pipe( ialu_reg_reg );
8488 %}
8489 
8490 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8491   effect( USE_DEF dst, USE src, KILL cr );
8492   format %{ "NEG    $dst\n\t"
8493             "ADC    $dst,$src" %}
8494   ins_encode( neg_reg(dst),
8495               OpcRegReg(0x13,dst,src) );
8496   ins_pipe( ialu_reg_reg_long );
8497 %}
8498 
8499 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8500   match(Set dst (Conv2B src));
8501 
8502   expand %{
8503     movP_nocopy(dst,src);
8504     cp2b(dst,src,cr);
8505   %}
8506 %}
8507 
8508 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
8509   match(Set dst (CmpLTMask p q));
8510   effect(KILL cr);
8511   ins_cost(400);
8512 
8513   // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8514   format %{ "XOR    $dst,$dst\n\t"
8515             "CMP    $p,$q\n\t"
8516             "SETlt  $dst\n\t"
8517             "NEG    $dst" %}
8518   ins_encode %{
8519     Register Rp = $p$$Register;
8520     Register Rq = $q$$Register;
8521     Register Rd = $dst$$Register;
8522     Label done;
8523     __ xorl(Rd, Rd);
8524     __ cmpl(Rp, Rq);
8525     __ setb(Assembler::less, Rd);
8526     __ negl(Rd);
8527   %}
8528 
8529   ins_pipe(pipe_slow);
8530 %}
8531 
8532 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
8533   match(Set dst (CmpLTMask dst zero));
8534   effect(DEF dst, KILL cr);
8535   ins_cost(100);
8536 
8537   format %{ "SAR    $dst,31\t# cmpLTMask0" %}
8538   ins_encode %{
8539   __ sarl($dst$$Register, 31);
8540   %}
8541   ins_pipe(ialu_reg);
8542 %}
8543 
8544 /* better to save a register than avoid a branch */
8545 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8546   match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8547   effect(KILL cr);
8548   ins_cost(400);
8549   format %{ "SUB    $p,$q\t# cadd_cmpLTMask\n\t"
8550             "JGE    done\n\t"
8551             "ADD    $p,$y\n"
8552             "done:  " %}
8553   ins_encode %{
8554     Register Rp = $p$$Register;
8555     Register Rq = $q$$Register;
8556     Register Ry = $y$$Register;
8557     Label done;
8558     __ subl(Rp, Rq);
8559     __ jccb(Assembler::greaterEqual, done);
8560     __ addl(Rp, Ry);
8561     __ bind(done);
8562   %}
8563 
8564   ins_pipe(pipe_cmplt);
8565 %}
8566 
8567 /* better to save a register than avoid a branch */
8568 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8569   match(Set y (AndI (CmpLTMask p q) y));
8570   effect(KILL cr);
8571 
8572   ins_cost(300);
8573 
8574   format %{ "CMPL     $p, $q\t# and_cmpLTMask\n\t"
8575             "JLT      done\n\t"
8576             "XORL     $y, $y\n"
8577             "done:  " %}
8578   ins_encode %{
8579     Register Rp = $p$$Register;
8580     Register Rq = $q$$Register;
8581     Register Ry = $y$$Register;
8582     Label done;
8583     __ cmpl(Rp, Rq);
8584     __ jccb(Assembler::less, done);
8585     __ xorl(Ry, Ry);
8586     __ bind(done);
8587   %}
8588 
8589   ins_pipe(pipe_cmplt);
8590 %}
8591 
8592 /* If I enable this, I encourage spilling in the inner loop of compress.
8593 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
8594   match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8595 */
8596 //----------Overflow Math Instructions-----------------------------------------
8597 
8598 instruct overflowAddI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8599 %{
8600   match(Set cr (OverflowAddI op1 op2));
8601   effect(DEF cr, USE_KILL op1, USE op2);
8602 
8603   format %{ "ADD    $op1, $op2\t# overflow check int" %}
8604 
8605   ins_encode %{
8606     __ addl($op1$$Register, $op2$$Register);
8607   %}
8608   ins_pipe(ialu_reg_reg);
8609 %}
8610 
8611 instruct overflowAddI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2)
8612 %{
8613   match(Set cr (OverflowAddI op1 op2));
8614   effect(DEF cr, USE_KILL op1, USE op2);
8615 
8616   format %{ "ADD    $op1, $op2\t# overflow check int" %}
8617 
8618   ins_encode %{
8619     __ addl($op1$$Register, $op2$$constant);
8620   %}
8621   ins_pipe(ialu_reg_reg);
8622 %}
8623 
8624 instruct overflowSubI_rReg(eFlagsReg cr, rRegI op1, rRegI op2)
8625 %{
8626   match(Set cr (OverflowSubI op1 op2));
8627 
8628   format %{ "CMP    $op1, $op2\t# overflow check int" %}
8629   ins_encode %{
8630     __ cmpl($op1$$Register, $op2$$Register);
8631   %}
8632   ins_pipe(ialu_reg_reg);
8633 %}
8634 
8635 instruct overflowSubI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2)
8636 %{
8637   match(Set cr (OverflowSubI op1 op2));
8638 
8639   format %{ "CMP    $op1, $op2\t# overflow check int" %}
8640   ins_encode %{
8641     __ cmpl($op1$$Register, $op2$$constant);
8642   %}
8643   ins_pipe(ialu_reg_reg);
8644 %}
8645 
8646 instruct overflowNegI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2)
8647 %{
8648   match(Set cr (OverflowSubI zero op2));
8649   effect(DEF cr, USE_KILL op2);
8650 
8651   format %{ "NEG    $op2\t# overflow check int" %}
8652   ins_encode %{
8653     __ negl($op2$$Register);
8654   %}
8655   ins_pipe(ialu_reg_reg);
8656 %}
8657 
8658 instruct overflowMulI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2)
8659 %{
8660   match(Set cr (OverflowMulI op1 op2));
8661   effect(DEF cr, USE_KILL op1, USE op2);
8662 
8663   format %{ "IMUL    $op1, $op2\t# overflow check int" %}
8664   ins_encode %{
8665     __ imull($op1$$Register, $op2$$Register);
8666   %}
8667   ins_pipe(ialu_reg_reg_alu0);
8668 %}
8669 
8670 instruct overflowMulI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
8671 %{
8672   match(Set cr (OverflowMulI op1 op2));
8673   effect(DEF cr, TEMP tmp, USE op1, USE op2);
8674 
8675   format %{ "IMUL    $tmp, $op1, $op2\t# overflow check int" %}
8676   ins_encode %{
8677     __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
8678   %}
8679   ins_pipe(ialu_reg_reg_alu0);
8680 %}
8681 
8682 //----------Long Instructions------------------------------------------------
8683 // Add Long Register with Register
8684 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8685   match(Set dst (AddL dst src));
8686   effect(KILL cr);
8687   ins_cost(200);
8688   format %{ "ADD    $dst.lo,$src.lo\n\t"
8689             "ADC    $dst.hi,$src.hi" %}
8690   opcode(0x03, 0x13);
8691   ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8692   ins_pipe( ialu_reg_reg_long );
8693 %}
8694 
8695 // Add Long Register with Immediate
8696 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8697   match(Set dst (AddL dst src));
8698   effect(KILL cr);
8699   format %{ "ADD    $dst.lo,$src.lo\n\t"
8700             "ADC    $dst.hi,$src.hi" %}
8701   opcode(0x81,0x00,0x02);  /* Opcode 81 /0, 81 /2 */
8702   ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8703   ins_pipe( ialu_reg_long );
8704 %}
8705 
8706 // Add Long Register with Memory
8707 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8708   match(Set dst (AddL dst (LoadL mem)));
8709   effect(KILL cr);
8710   ins_cost(125);
8711   format %{ "ADD    $dst.lo,$mem\n\t"
8712             "ADC    $dst.hi,$mem+4" %}
8713   opcode(0x03, 0x13);
8714   ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8715   ins_pipe( ialu_reg_long_mem );
8716 %}
8717 
8718 // Subtract Long Register with Register.
8719 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8720   match(Set dst (SubL dst src));
8721   effect(KILL cr);
8722   ins_cost(200);
8723   format %{ "SUB    $dst.lo,$src.lo\n\t"
8724             "SBB    $dst.hi,$src.hi" %}
8725   opcode(0x2B, 0x1B);
8726   ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8727   ins_pipe( ialu_reg_reg_long );
8728 %}
8729 
8730 // Subtract Long Register with Immediate
8731 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8732   match(Set dst (SubL dst src));
8733   effect(KILL cr);
8734   format %{ "SUB    $dst.lo,$src.lo\n\t"
8735             "SBB    $dst.hi,$src.hi" %}
8736   opcode(0x81,0x05,0x03);  /* Opcode 81 /5, 81 /3 */
8737   ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8738   ins_pipe( ialu_reg_long );
8739 %}
8740 
8741 // Subtract Long Register with Memory
8742 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8743   match(Set dst (SubL dst (LoadL mem)));
8744   effect(KILL cr);
8745   ins_cost(125);
8746   format %{ "SUB    $dst.lo,$mem\n\t"
8747             "SBB    $dst.hi,$mem+4" %}
8748   opcode(0x2B, 0x1B);
8749   ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8750   ins_pipe( ialu_reg_long_mem );
8751 %}
8752 
8753 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
8754   match(Set dst (SubL zero dst));
8755   effect(KILL cr);
8756   ins_cost(300);
8757   format %{ "NEG    $dst.hi\n\tNEG    $dst.lo\n\tSBB    $dst.hi,0" %}
8758   ins_encode( neg_long(dst) );
8759   ins_pipe( ialu_reg_reg_long );
8760 %}
8761 
8762 // And Long Register with Register
8763 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8764   match(Set dst (AndL dst src));
8765   effect(KILL cr);
8766   format %{ "AND    $dst.lo,$src.lo\n\t"
8767             "AND    $dst.hi,$src.hi" %}
8768   opcode(0x23,0x23);
8769   ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8770   ins_pipe( ialu_reg_reg_long );
8771 %}
8772 
8773 // And Long Register with Immediate
8774 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8775   match(Set dst (AndL dst src));
8776   effect(KILL cr);
8777   format %{ "AND    $dst.lo,$src.lo\n\t"
8778             "AND    $dst.hi,$src.hi" %}
8779   opcode(0x81,0x04,0x04);  /* Opcode 81 /4, 81 /4 */
8780   ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8781   ins_pipe( ialu_reg_long );
8782 %}
8783 
8784 // And Long Register with Memory
8785 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8786   match(Set dst (AndL dst (LoadL mem)));
8787   effect(KILL cr);
8788   ins_cost(125);
8789   format %{ "AND    $dst.lo,$mem\n\t"
8790             "AND    $dst.hi,$mem+4" %}
8791   opcode(0x23, 0x23);
8792   ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8793   ins_pipe( ialu_reg_long_mem );
8794 %}
8795 
8796 // BMI1 instructions
8797 instruct andnL_eReg_eReg_eReg(eRegL dst, eRegL src1, eRegL src2, immL_M1 minus_1, eFlagsReg cr) %{
8798   match(Set dst (AndL (XorL src1 minus_1) src2));
8799   predicate(UseBMI1Instructions);
8800   effect(KILL cr, TEMP dst);
8801 
8802   format %{ "ANDNL  $dst.lo, $src1.lo, $src2.lo\n\t"
8803             "ANDNL  $dst.hi, $src1.hi, $src2.hi"
8804          %}
8805 
8806   ins_encode %{
8807     Register Rdst = $dst$$Register;
8808     Register Rsrc1 = $src1$$Register;
8809     Register Rsrc2 = $src2$$Register;
8810     __ andnl(Rdst, Rsrc1, Rsrc2);
8811     __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), HIGH_FROM_LOW(Rsrc2));
8812   %}
8813   ins_pipe(ialu_reg_reg_long);
8814 %}
8815 
8816 instruct andnL_eReg_eReg_mem(eRegL dst, eRegL src1, memory src2, immL_M1 minus_1, eFlagsReg cr) %{
8817   match(Set dst (AndL (XorL src1 minus_1) (LoadL src2) ));
8818   predicate(UseBMI1Instructions);
8819   effect(KILL cr, TEMP dst);
8820 
8821   ins_cost(125);
8822   format %{ "ANDNL  $dst.lo, $src1.lo, $src2\n\t"
8823             "ANDNL  $dst.hi, $src1.hi, $src2+4"
8824          %}
8825 
8826   ins_encode %{
8827     Register Rdst = $dst$$Register;
8828     Register Rsrc1 = $src1$$Register;
8829     Address src2_hi = Address::make_raw($src2$$base, $src2$$index, $src2$$scale, $src2$$disp + 4, relocInfo::none);
8830 
8831     __ andnl(Rdst, Rsrc1, $src2$$Address);
8832     __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), src2_hi);
8833   %}
8834   ins_pipe(ialu_reg_mem);
8835 %}
8836 
8837 instruct blsiL_eReg_eReg(eRegL dst, eRegL src, immL0 imm_zero, eFlagsReg cr) %{
8838   match(Set dst (AndL (SubL imm_zero src) src));
8839   predicate(UseBMI1Instructions);
8840   effect(KILL cr, TEMP dst);
8841 
8842   format %{ "MOVL   $dst.hi, 0\n\t"
8843             "BLSIL  $dst.lo, $src.lo\n\t"
8844             "JNZ    done\n\t"
8845             "BLSIL  $dst.hi, $src.hi\n"
8846             "done:"
8847          %}
8848 
8849   ins_encode %{
8850     Label done;
8851     Register Rdst = $dst$$Register;
8852     Register Rsrc = $src$$Register;
8853     __ movl(HIGH_FROM_LOW(Rdst), 0);
8854     __ blsil(Rdst, Rsrc);
8855     __ jccb(Assembler::notZero, done);
8856     __ blsil(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8857     __ bind(done);
8858   %}
8859   ins_pipe(ialu_reg);
8860 %}
8861 
8862 instruct blsiL_eReg_mem(eRegL dst, memory src, immL0 imm_zero, eFlagsReg cr) %{
8863   match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
8864   predicate(UseBMI1Instructions);
8865   effect(KILL cr, TEMP dst);
8866 
8867   ins_cost(125);
8868   format %{ "MOVL   $dst.hi, 0\n\t"
8869             "BLSIL  $dst.lo, $src\n\t"
8870             "JNZ    done\n\t"
8871             "BLSIL  $dst.hi, $src+4\n"
8872             "done:"
8873          %}
8874 
8875   ins_encode %{
8876     Label done;
8877     Register Rdst = $dst$$Register;
8878     Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8879 
8880     __ movl(HIGH_FROM_LOW(Rdst), 0);
8881     __ blsil(Rdst, $src$$Address);
8882     __ jccb(Assembler::notZero, done);
8883     __ blsil(HIGH_FROM_LOW(Rdst), src_hi);
8884     __ bind(done);
8885   %}
8886   ins_pipe(ialu_reg_mem);
8887 %}
8888 
8889 instruct blsmskL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)
8890 %{
8891   match(Set dst (XorL (AddL src minus_1) src));
8892   predicate(UseBMI1Instructions);
8893   effect(KILL cr, TEMP dst);
8894 
8895   format %{ "MOVL    $dst.hi, 0\n\t"
8896             "BLSMSKL $dst.lo, $src.lo\n\t"
8897             "JNC     done\n\t"
8898             "BLSMSKL $dst.hi, $src.hi\n"
8899             "done:"
8900          %}
8901 
8902   ins_encode %{
8903     Label done;
8904     Register Rdst = $dst$$Register;
8905     Register Rsrc = $src$$Register;
8906     __ movl(HIGH_FROM_LOW(Rdst), 0);
8907     __ blsmskl(Rdst, Rsrc);
8908     __ jccb(Assembler::carryClear, done);
8909     __ blsmskl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8910     __ bind(done);
8911   %}
8912 
8913   ins_pipe(ialu_reg);
8914 %}
8915 
8916 instruct blsmskL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)
8917 %{
8918   match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ));
8919   predicate(UseBMI1Instructions);
8920   effect(KILL cr, TEMP dst);
8921 
8922   ins_cost(125);
8923   format %{ "MOVL    $dst.hi, 0\n\t"
8924             "BLSMSKL $dst.lo, $src\n\t"
8925             "JNC     done\n\t"
8926             "BLSMSKL $dst.hi, $src+4\n"
8927             "done:"
8928          %}
8929 
8930   ins_encode %{
8931     Label done;
8932     Register Rdst = $dst$$Register;
8933     Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8934 
8935     __ movl(HIGH_FROM_LOW(Rdst), 0);
8936     __ blsmskl(Rdst, $src$$Address);
8937     __ jccb(Assembler::carryClear, done);
8938     __ blsmskl(HIGH_FROM_LOW(Rdst), src_hi);
8939     __ bind(done);
8940   %}
8941 
8942   ins_pipe(ialu_reg_mem);
8943 %}
8944 
8945 instruct blsrL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr)
8946 %{
8947   match(Set dst (AndL (AddL src minus_1) src) );
8948   predicate(UseBMI1Instructions);
8949   effect(KILL cr, TEMP dst);
8950 
8951   format %{ "MOVL   $dst.hi, $src.hi\n\t"
8952             "BLSRL  $dst.lo, $src.lo\n\t"
8953             "JNC    done\n\t"
8954             "BLSRL  $dst.hi, $src.hi\n"
8955             "done:"
8956   %}
8957 
8958   ins_encode %{
8959     Label done;
8960     Register Rdst = $dst$$Register;
8961     Register Rsrc = $src$$Register;
8962     __ movl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8963     __ blsrl(Rdst, Rsrc);
8964     __ jccb(Assembler::carryClear, done);
8965     __ blsrl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc));
8966     __ bind(done);
8967   %}
8968 
8969   ins_pipe(ialu_reg);
8970 %}
8971 
8972 instruct blsrL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr)
8973 %{
8974   match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src) ));
8975   predicate(UseBMI1Instructions);
8976   effect(KILL cr, TEMP dst);
8977 
8978   ins_cost(125);
8979   format %{ "MOVL   $dst.hi, $src+4\n\t"
8980             "BLSRL  $dst.lo, $src\n\t"
8981             "JNC    done\n\t"
8982             "BLSRL  $dst.hi, $src+4\n"
8983             "done:"
8984   %}
8985 
8986   ins_encode %{
8987     Label done;
8988     Register Rdst = $dst$$Register;
8989     Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none);
8990     __ movl(HIGH_FROM_LOW(Rdst), src_hi);
8991     __ blsrl(Rdst, $src$$Address);
8992     __ jccb(Assembler::carryClear, done);
8993     __ blsrl(HIGH_FROM_LOW(Rdst), src_hi);
8994     __ bind(done);
8995   %}
8996 
8997   ins_pipe(ialu_reg_mem);
8998 %}
8999 
9000 // Or Long Register with Register
9001 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9002   match(Set dst (OrL dst src));
9003   effect(KILL cr);
9004   format %{ "OR     $dst.lo,$src.lo\n\t"
9005             "OR     $dst.hi,$src.hi" %}
9006   opcode(0x0B,0x0B);
9007   ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9008   ins_pipe( ialu_reg_reg_long );
9009 %}
9010 
9011 // Or Long Register with Immediate
9012 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9013   match(Set dst (OrL dst src));
9014   effect(KILL cr);
9015   format %{ "OR     $dst.lo,$src.lo\n\t"
9016             "OR     $dst.hi,$src.hi" %}
9017   opcode(0x81,0x01,0x01);  /* Opcode 81 /1, 81 /1 */
9018   ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9019   ins_pipe( ialu_reg_long );
9020 %}
9021 
9022 // Or Long Register with Memory
9023 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9024   match(Set dst (OrL dst (LoadL mem)));
9025   effect(KILL cr);
9026   ins_cost(125);
9027   format %{ "OR     $dst.lo,$mem\n\t"
9028             "OR     $dst.hi,$mem+4" %}
9029   opcode(0x0B,0x0B);
9030   ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9031   ins_pipe( ialu_reg_long_mem );
9032 %}
9033 
9034 // Xor Long Register with Register
9035 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9036   match(Set dst (XorL dst src));
9037   effect(KILL cr);
9038   format %{ "XOR    $dst.lo,$src.lo\n\t"
9039             "XOR    $dst.hi,$src.hi" %}
9040   opcode(0x33,0x33);
9041   ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9042   ins_pipe( ialu_reg_reg_long );
9043 %}
9044 
9045 // Xor Long Register with Immediate -1
9046 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9047   match(Set dst (XorL dst imm));  
9048   format %{ "NOT    $dst.lo\n\t"
9049             "NOT    $dst.hi" %}
9050   ins_encode %{
9051      __ notl($dst$$Register);
9052      __ notl(HIGH_FROM_LOW($dst$$Register));
9053   %}
9054   ins_pipe( ialu_reg_long );
9055 %}
9056 
9057 // Xor Long Register with Immediate
9058 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9059   match(Set dst (XorL dst src));
9060   effect(KILL cr);
9061   format %{ "XOR    $dst.lo,$src.lo\n\t"
9062             "XOR    $dst.hi,$src.hi" %}
9063   opcode(0x81,0x06,0x06);  /* Opcode 81 /6, 81 /6 */
9064   ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9065   ins_pipe( ialu_reg_long );
9066 %}
9067 
9068 // Xor Long Register with Memory
9069 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9070   match(Set dst (XorL dst (LoadL mem)));
9071   effect(KILL cr);
9072   ins_cost(125);
9073   format %{ "XOR    $dst.lo,$mem\n\t"
9074             "XOR    $dst.hi,$mem+4" %}
9075   opcode(0x33,0x33);
9076   ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9077   ins_pipe( ialu_reg_long_mem );
9078 %}
9079 
9080 // Shift Left Long by 1
9081 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9082   predicate(UseNewLongLShift);
9083   match(Set dst (LShiftL dst cnt));
9084   effect(KILL cr);
9085   ins_cost(100);
9086   format %{ "ADD    $dst.lo,$dst.lo\n\t"
9087             "ADC    $dst.hi,$dst.hi" %}
9088   ins_encode %{
9089     __ addl($dst$$Register,$dst$$Register);
9090     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9091   %}
9092   ins_pipe( ialu_reg_long );
9093 %}
9094 
9095 // Shift Left Long by 2
9096 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9097   predicate(UseNewLongLShift);
9098   match(Set dst (LShiftL dst cnt));
9099   effect(KILL cr);
9100   ins_cost(100);
9101   format %{ "ADD    $dst.lo,$dst.lo\n\t"
9102             "ADC    $dst.hi,$dst.hi\n\t" 
9103             "ADD    $dst.lo,$dst.lo\n\t"
9104             "ADC    $dst.hi,$dst.hi" %}
9105   ins_encode %{
9106     __ addl($dst$$Register,$dst$$Register);
9107     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9108     __ addl($dst$$Register,$dst$$Register);
9109     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9110   %}
9111   ins_pipe( ialu_reg_long );
9112 %}
9113 
9114 // Shift Left Long by 3
9115 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9116   predicate(UseNewLongLShift);
9117   match(Set dst (LShiftL dst cnt));
9118   effect(KILL cr);
9119   ins_cost(100);
9120   format %{ "ADD    $dst.lo,$dst.lo\n\t"
9121             "ADC    $dst.hi,$dst.hi\n\t" 
9122             "ADD    $dst.lo,$dst.lo\n\t"
9123             "ADC    $dst.hi,$dst.hi\n\t" 
9124             "ADD    $dst.lo,$dst.lo\n\t"
9125             "ADC    $dst.hi,$dst.hi" %}
9126   ins_encode %{
9127     __ addl($dst$$Register,$dst$$Register);
9128     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9129     __ addl($dst$$Register,$dst$$Register);
9130     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9131     __ addl($dst$$Register,$dst$$Register);
9132     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9133   %}
9134   ins_pipe( ialu_reg_long );
9135 %}
9136 
9137 // Shift Left Long by 1-31
9138 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9139   match(Set dst (LShiftL dst cnt));
9140   effect(KILL cr);
9141   ins_cost(200);
9142   format %{ "SHLD   $dst.hi,$dst.lo,$cnt\n\t"
9143             "SHL    $dst.lo,$cnt" %}
9144   opcode(0xC1, 0x4, 0xA4);  /* 0F/A4, then C1 /4 ib */
9145   ins_encode( move_long_small_shift(dst,cnt) );
9146   ins_pipe( ialu_reg_long );
9147 %}
9148 
9149 // Shift Left Long by 32-63
9150 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9151   match(Set dst (LShiftL dst cnt));
9152   effect(KILL cr);
9153   ins_cost(300);
9154   format %{ "MOV    $dst.hi,$dst.lo\n"
9155           "\tSHL    $dst.hi,$cnt-32\n"
9156           "\tXOR    $dst.lo,$dst.lo" %}
9157   opcode(0xC1, 0x4);  /* C1 /4 ib */
9158   ins_encode( move_long_big_shift_clr(dst,cnt) );
9159   ins_pipe( ialu_reg_long );
9160 %}
9161 
9162 // Shift Left Long by variable
9163 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9164   match(Set dst (LShiftL dst shift));
9165   effect(KILL cr);
9166   ins_cost(500+200);
9167   size(17);
9168   format %{ "TEST   $shift,32\n\t"
9169             "JEQ,s  small\n\t"
9170             "MOV    $dst.hi,$dst.lo\n\t"
9171             "XOR    $dst.lo,$dst.lo\n"
9172     "small:\tSHLD   $dst.hi,$dst.lo,$shift\n\t"
9173             "SHL    $dst.lo,$shift" %}
9174   ins_encode( shift_left_long( dst, shift ) );
9175   ins_pipe( pipe_slow );
9176 %}
9177 
9178 // Shift Right Long by 1-31
9179 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9180   match(Set dst (URShiftL dst cnt));
9181   effect(KILL cr);
9182   ins_cost(200);
9183   format %{ "SHRD   $dst.lo,$dst.hi,$cnt\n\t"
9184             "SHR    $dst.hi,$cnt" %}
9185   opcode(0xC1, 0x5, 0xAC);  /* 0F/AC, then C1 /5 ib */
9186   ins_encode( move_long_small_shift(dst,cnt) );
9187   ins_pipe( ialu_reg_long );
9188 %}
9189 
9190 // Shift Right Long by 32-63
9191 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9192   match(Set dst (URShiftL dst cnt));
9193   effect(KILL cr);
9194   ins_cost(300);
9195   format %{ "MOV    $dst.lo,$dst.hi\n"
9196           "\tSHR    $dst.lo,$cnt-32\n"
9197           "\tXOR    $dst.hi,$dst.hi" %}
9198   opcode(0xC1, 0x5);  /* C1 /5 ib */
9199   ins_encode( move_long_big_shift_clr(dst,cnt) );
9200   ins_pipe( ialu_reg_long );
9201 %}
9202 
9203 // Shift Right Long by variable
9204 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9205   match(Set dst (URShiftL dst shift));
9206   effect(KILL cr);
9207   ins_cost(600);
9208   size(17);
9209   format %{ "TEST   $shift,32\n\t"
9210             "JEQ,s  small\n\t"
9211             "MOV    $dst.lo,$dst.hi\n\t"
9212             "XOR    $dst.hi,$dst.hi\n"
9213     "small:\tSHRD   $dst.lo,$dst.hi,$shift\n\t"
9214             "SHR    $dst.hi,$shift" %}
9215   ins_encode( shift_right_long( dst, shift ) );
9216   ins_pipe( pipe_slow );
9217 %}
9218 
9219 // Shift Right Long by 1-31
9220 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9221   match(Set dst (RShiftL dst cnt));
9222   effect(KILL cr);
9223   ins_cost(200);
9224   format %{ "SHRD   $dst.lo,$dst.hi,$cnt\n\t"
9225             "SAR    $dst.hi,$cnt" %}
9226   opcode(0xC1, 0x7, 0xAC);  /* 0F/AC, then C1 /7 ib */
9227   ins_encode( move_long_small_shift(dst,cnt) );
9228   ins_pipe( ialu_reg_long );
9229 %}
9230 
9231 // Shift Right Long by 32-63
9232 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9233   match(Set dst (RShiftL dst cnt));
9234   effect(KILL cr);
9235   ins_cost(300);
9236   format %{ "MOV    $dst.lo,$dst.hi\n"
9237           "\tSAR    $dst.lo,$cnt-32\n"
9238           "\tSAR    $dst.hi,31" %}
9239   opcode(0xC1, 0x7);  /* C1 /7 ib */
9240   ins_encode( move_long_big_shift_sign(dst,cnt) );
9241   ins_pipe( ialu_reg_long );
9242 %}
9243 
9244 // Shift Right arithmetic Long by variable
9245 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9246   match(Set dst (RShiftL dst shift));
9247   effect(KILL cr);
9248   ins_cost(600);
9249   size(18);
9250   format %{ "TEST   $shift,32\n\t"
9251             "JEQ,s  small\n\t"
9252             "MOV    $dst.lo,$dst.hi\n\t"
9253             "SAR    $dst.hi,31\n"
9254     "small:\tSHRD   $dst.lo,$dst.hi,$shift\n\t"
9255             "SAR    $dst.hi,$shift" %}
9256   ins_encode( shift_right_arith_long( dst, shift ) );
9257   ins_pipe( pipe_slow );
9258 %}
9259 
9260 
9261 //----------Double Instructions------------------------------------------------
9262 // Double Math
9263 
9264 // Compare & branch
9265 
9266 // P6 version of float compare, sets condition codes in EFLAGS
9267 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9268   predicate(VM_Version::supports_cmov() && UseSSE <=1);
9269   match(Set cr (CmpD src1 src2));
9270   effect(KILL rax);
9271   ins_cost(150);
9272   format %{ "FLD    $src1\n\t"
9273             "FUCOMIP ST,$src2  // P6 instruction\n\t"
9274             "JNP    exit\n\t"
9275             "MOV    ah,1       // saw a NaN, set CF\n\t"
9276             "SAHF\n"
9277      "exit:\tNOP               // avoid branch to branch" %}
9278   opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9279   ins_encode( Push_Reg_DPR(src1),
9280               OpcP, RegOpc(src2),
9281               cmpF_P6_fixup );
9282   ins_pipe( pipe_slow );
9283 %}
9284 
9285 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9286   predicate(VM_Version::supports_cmov() && UseSSE <=1);
9287   match(Set cr (CmpD src1 src2));
9288   ins_cost(150);
9289   format %{ "FLD    $src1\n\t"
9290             "FUCOMIP ST,$src2  // P6 instruction" %}
9291   opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9292   ins_encode( Push_Reg_DPR(src1),
9293               OpcP, RegOpc(src2));
9294   ins_pipe( pipe_slow );
9295 %}
9296 
9297 // Compare & branch
9298 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9299   predicate(UseSSE<=1);
9300   match(Set cr (CmpD src1 src2));
9301   effect(KILL rax);
9302   ins_cost(200);
9303   format %{ "FLD    $src1\n\t"
9304             "FCOMp  $src2\n\t"
9305             "FNSTSW AX\n\t"
9306             "TEST   AX,0x400\n\t"
9307             "JZ,s   flags\n\t"
9308             "MOV    AH,1\t# unordered treat as LT\n"
9309     "flags:\tSAHF" %}
9310   opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9311   ins_encode( Push_Reg_DPR(src1),
9312               OpcP, RegOpc(src2),
9313               fpu_flags);
9314   ins_pipe( pipe_slow );
9315 %}
9316 
9317 // Compare vs zero into -1,0,1
9318 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9319   predicate(UseSSE<=1);
9320   match(Set dst (CmpD3 src1 zero));
9321   effect(KILL cr, KILL rax);
9322   ins_cost(280);
9323   format %{ "FTSTD  $dst,$src1" %}
9324   opcode(0xE4, 0xD9);
9325   ins_encode( Push_Reg_DPR(src1),
9326               OpcS, OpcP, PopFPU,
9327               CmpF_Result(dst));
9328   ins_pipe( pipe_slow );
9329 %}
9330 
9331 // Compare into -1,0,1
9332 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9333   predicate(UseSSE<=1);
9334   match(Set dst (CmpD3 src1 src2));
9335   effect(KILL cr, KILL rax);
9336   ins_cost(300);
9337   format %{ "FCMPD  $dst,$src1,$src2" %}
9338   opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9339   ins_encode( Push_Reg_DPR(src1),
9340               OpcP, RegOpc(src2),
9341               CmpF_Result(dst));
9342   ins_pipe( pipe_slow );
9343 %}
9344 
9345 // float compare and set condition codes in EFLAGS by XMM regs
9346 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9347   predicate(UseSSE>=2);
9348   match(Set cr (CmpD src1 src2));
9349   ins_cost(145);
9350   format %{ "UCOMISD $src1,$src2\n\t"
9351             "JNP,s   exit\n\t"
9352             "PUSHF\t# saw NaN, set CF\n\t"
9353             "AND     [rsp], #0xffffff2b\n\t"
9354             "POPF\n"
9355     "exit:" %}
9356   ins_encode %{
9357     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9358     emit_cmpfp_fixup(_masm);
9359   %}
9360   ins_pipe( pipe_slow );
9361 %}
9362 
9363 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9364   predicate(UseSSE>=2);
9365   match(Set cr (CmpD src1 src2));
9366   ins_cost(100);
9367   format %{ "UCOMISD $src1,$src2" %}
9368   ins_encode %{
9369     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9370   %}
9371   ins_pipe( pipe_slow );
9372 %}
9373 
9374 // float compare and set condition codes in EFLAGS by XMM regs
9375 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9376   predicate(UseSSE>=2);
9377   match(Set cr (CmpD src1 (LoadD src2)));
9378   ins_cost(145);
9379   format %{ "UCOMISD $src1,$src2\n\t"
9380             "JNP,s   exit\n\t"
9381             "PUSHF\t# saw NaN, set CF\n\t"
9382             "AND     [rsp], #0xffffff2b\n\t"
9383             "POPF\n"
9384     "exit:" %}
9385   ins_encode %{
9386     __ ucomisd($src1$$XMMRegister, $src2$$Address);
9387     emit_cmpfp_fixup(_masm);
9388   %}
9389   ins_pipe( pipe_slow );
9390 %}
9391 
9392 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9393   predicate(UseSSE>=2);
9394   match(Set cr (CmpD src1 (LoadD src2)));
9395   ins_cost(100);
9396   format %{ "UCOMISD $src1,$src2" %}
9397   ins_encode %{
9398     __ ucomisd($src1$$XMMRegister, $src2$$Address);
9399   %}
9400   ins_pipe( pipe_slow );
9401 %}
9402 
9403 // Compare into -1,0,1 in XMM
9404 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9405   predicate(UseSSE>=2);
9406   match(Set dst (CmpD3 src1 src2));
9407   effect(KILL cr);
9408   ins_cost(255);
9409   format %{ "UCOMISD $src1, $src2\n\t"
9410             "MOV     $dst, #-1\n\t"
9411             "JP,s    done\n\t"
9412             "JB,s    done\n\t"
9413             "SETNE   $dst\n\t"
9414             "MOVZB   $dst, $dst\n"
9415     "done:" %}
9416   ins_encode %{
9417     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9418     emit_cmpfp3(_masm, $dst$$Register);
9419   %}
9420   ins_pipe( pipe_slow );
9421 %}
9422 
9423 // Compare into -1,0,1 in XMM and memory
9424 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9425   predicate(UseSSE>=2);
9426   match(Set dst (CmpD3 src1 (LoadD src2)));
9427   effect(KILL cr);
9428   ins_cost(275);
9429   format %{ "UCOMISD $src1, $src2\n\t"
9430             "MOV     $dst, #-1\n\t"
9431             "JP,s    done\n\t"
9432             "JB,s    done\n\t"
9433             "SETNE   $dst\n\t"
9434             "MOVZB   $dst, $dst\n"
9435     "done:" %}
9436   ins_encode %{
9437     __ ucomisd($src1$$XMMRegister, $src2$$Address);
9438     emit_cmpfp3(_masm, $dst$$Register);
9439   %}
9440   ins_pipe( pipe_slow );
9441 %}
9442 
9443 
9444 instruct subDPR_reg(regDPR dst, regDPR src) %{
9445   predicate (UseSSE <=1);
9446   match(Set dst (SubD dst src));
9447 
9448   format %{ "FLD    $src\n\t"
9449             "DSUBp  $dst,ST" %}
9450   opcode(0xDE, 0x5); /* DE E8+i  or DE /5 */
9451   ins_cost(150);
9452   ins_encode( Push_Reg_DPR(src),
9453               OpcP, RegOpc(dst) );
9454   ins_pipe( fpu_reg_reg );
9455 %}
9456 
9457 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9458   predicate (UseSSE <=1);
9459   match(Set dst (RoundDouble (SubD src1 src2)));
9460   ins_cost(250);
9461 
9462   format %{ "FLD    $src2\n\t"
9463             "DSUB   ST,$src1\n\t"
9464             "FSTP_D $dst\t# D-round" %}
9465   opcode(0xD8, 0x5);
9466   ins_encode( Push_Reg_DPR(src2),
9467               OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9468   ins_pipe( fpu_mem_reg_reg );
9469 %}
9470 
9471 
9472 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9473   predicate (UseSSE <=1);
9474   match(Set dst (SubD dst (LoadD src)));
9475   ins_cost(150);
9476 
9477   format %{ "FLD    $src\n\t"
9478             "DSUBp  $dst,ST" %}
9479   opcode(0xDE, 0x5, 0xDD); /* DE C0+i */  /* LoadD  DD /0 */
9480   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9481               OpcP, RegOpc(dst) );
9482   ins_pipe( fpu_reg_mem );
9483 %}
9484 
9485 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9486   predicate (UseSSE<=1);
9487   match(Set dst (AbsD src));
9488   ins_cost(100);
9489   format %{ "FABS" %}
9490   opcode(0xE1, 0xD9);
9491   ins_encode( OpcS, OpcP );
9492   ins_pipe( fpu_reg_reg );
9493 %}
9494 
9495 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9496   predicate(UseSSE<=1);
9497   match(Set dst (NegD src));
9498   ins_cost(100);
9499   format %{ "FCHS" %}
9500   opcode(0xE0, 0xD9);
9501   ins_encode( OpcS, OpcP );
9502   ins_pipe( fpu_reg_reg );
9503 %}
9504 
9505 instruct addDPR_reg(regDPR dst, regDPR src) %{
9506   predicate(UseSSE<=1);
9507   match(Set dst (AddD dst src));
9508   format %{ "FLD    $src\n\t"
9509             "DADD   $dst,ST" %}
9510   size(4);
9511   ins_cost(150);
9512   opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9513   ins_encode( Push_Reg_DPR(src),
9514               OpcP, RegOpc(dst) );
9515   ins_pipe( fpu_reg_reg );
9516 %}
9517 
9518 
9519 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9520   predicate(UseSSE<=1);
9521   match(Set dst (RoundDouble (AddD src1 src2)));
9522   ins_cost(250);
9523 
9524   format %{ "FLD    $src2\n\t"
9525             "DADD   ST,$src1\n\t"
9526             "FSTP_D $dst\t# D-round" %}
9527   opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9528   ins_encode( Push_Reg_DPR(src2),
9529               OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9530   ins_pipe( fpu_mem_reg_reg );
9531 %}
9532 
9533 
9534 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9535   predicate(UseSSE<=1);
9536   match(Set dst (AddD dst (LoadD src)));
9537   ins_cost(150);
9538 
9539   format %{ "FLD    $src\n\t"
9540             "DADDp  $dst,ST" %}
9541   opcode(0xDE, 0x0, 0xDD); /* DE C0+i */  /* LoadD  DD /0 */
9542   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9543               OpcP, RegOpc(dst) );
9544   ins_pipe( fpu_reg_mem );
9545 %}
9546 
9547 // add-to-memory
9548 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9549   predicate(UseSSE<=1);
9550   match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9551   ins_cost(150);
9552 
9553   format %{ "FLD_D  $dst\n\t"
9554             "DADD   ST,$src\n\t"
9555             "FST_D  $dst" %}
9556   opcode(0xDD, 0x0);
9557   ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9558               Opcode(0xD8), RegOpc(src),
9559               set_instruction_start,
9560               Opcode(0xDD), RMopc_Mem(0x03,dst) );
9561   ins_pipe( fpu_reg_mem );
9562 %}
9563 
9564 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9565   predicate(UseSSE<=1);
9566   match(Set dst (AddD dst con));
9567   ins_cost(125);
9568   format %{ "FLD1\n\t"
9569             "DADDp  $dst,ST" %}
9570   ins_encode %{
9571     __ fld1();
9572     __ faddp($dst$$reg);
9573   %}
9574   ins_pipe(fpu_reg);
9575 %}
9576 
9577 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9578   predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9579   match(Set dst (AddD dst con));
9580   ins_cost(200);
9581   format %{ "FLD_D  [$constantaddress]\t# load from constant table: double=$con\n\t"
9582             "DADDp  $dst,ST" %}
9583   ins_encode %{
9584     __ fld_d($constantaddress($con));
9585     __ faddp($dst$$reg);
9586   %}
9587   ins_pipe(fpu_reg_mem);
9588 %}
9589 
9590 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9591   predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9592   match(Set dst (RoundDouble (AddD src con)));
9593   ins_cost(200);
9594   format %{ "FLD_D  [$constantaddress]\t# load from constant table: double=$con\n\t"
9595             "DADD   ST,$src\n\t"
9596             "FSTP_D $dst\t# D-round" %}
9597   ins_encode %{
9598     __ fld_d($constantaddress($con));
9599     __ fadd($src$$reg);
9600     __ fstp_d(Address(rsp, $dst$$disp));
9601   %}
9602   ins_pipe(fpu_mem_reg_con);
9603 %}
9604 
9605 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9606   predicate(UseSSE<=1);
9607   match(Set dst (MulD dst src));
9608   format %{ "FLD    $src\n\t"
9609             "DMULp  $dst,ST" %}
9610   opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9611   ins_cost(150);
9612   ins_encode( Push_Reg_DPR(src),
9613               OpcP, RegOpc(dst) );
9614   ins_pipe( fpu_reg_reg );
9615 %}
9616 
9617 // Strict FP instruction biases argument before multiply then
9618 // biases result to avoid double rounding of subnormals.
9619 //
9620 // scale arg1 by multiplying arg1 by 2^(-15360)
9621 // load arg2
9622 // multiply scaled arg1 by arg2
9623 // rescale product by 2^(15360)
9624 //
9625 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9626   predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9627   match(Set dst (MulD dst src));
9628   ins_cost(1);   // Select this instruction for all strict FP double multiplies
9629 
9630   format %{ "FLD    StubRoutines::_fpu_subnormal_bias1\n\t"
9631             "DMULp  $dst,ST\n\t"
9632             "FLD    $src\n\t"
9633             "DMULp  $dst,ST\n\t"
9634             "FLD    StubRoutines::_fpu_subnormal_bias2\n\t"
9635             "DMULp  $dst,ST\n\t" %}
9636   opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9637   ins_encode( strictfp_bias1(dst),
9638               Push_Reg_DPR(src),
9639               OpcP, RegOpc(dst),
9640               strictfp_bias2(dst) );
9641   ins_pipe( fpu_reg_reg );
9642 %}
9643 
9644 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9645   predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9646   match(Set dst (MulD dst con));
9647   ins_cost(200);
9648   format %{ "FLD_D  [$constantaddress]\t# load from constant table: double=$con\n\t"
9649             "DMULp  $dst,ST" %}
9650   ins_encode %{
9651     __ fld_d($constantaddress($con));
9652     __ fmulp($dst$$reg);
9653   %}
9654   ins_pipe(fpu_reg_mem);
9655 %}
9656 
9657 
9658 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9659   predicate( UseSSE<=1 );
9660   match(Set dst (MulD dst (LoadD src)));
9661   ins_cost(200);
9662   format %{ "FLD_D  $src\n\t"
9663             "DMULp  $dst,ST" %}
9664   opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/  /* LoadD  DD /0 */
9665   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9666               OpcP, RegOpc(dst) );
9667   ins_pipe( fpu_reg_mem );
9668 %}
9669 
9670 //
9671 // Cisc-alternate to reg-reg multiply
9672 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9673   predicate( UseSSE<=1 );
9674   match(Set dst (MulD src (LoadD mem)));
9675   ins_cost(250);
9676   format %{ "FLD_D  $mem\n\t"
9677             "DMUL   ST,$src\n\t"
9678             "FSTP_D $dst" %}
9679   opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */  /* LoadD D9 /0 */
9680   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9681               OpcReg_FPR(src),
9682               Pop_Reg_DPR(dst) );
9683   ins_pipe( fpu_reg_reg_mem );
9684 %}
9685 
9686 
9687 // MACRO3 -- addDPR a mulDPR
9688 // This instruction is a '2-address' instruction in that the result goes
9689 // back to src2.  This eliminates a move from the macro; possibly the
9690 // register allocator will have to add it back (and maybe not).
9691 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9692   predicate( UseSSE<=1 );
9693   match(Set src2 (AddD (MulD src0 src1) src2));
9694   format %{ "FLD    $src0\t# ===MACRO3d===\n\t"
9695             "DMUL   ST,$src1\n\t"
9696             "DADDp  $src2,ST" %}
9697   ins_cost(250);
9698   opcode(0xDD); /* LoadD DD /0 */
9699   ins_encode( Push_Reg_FPR(src0),
9700               FMul_ST_reg(src1),
9701               FAddP_reg_ST(src2) );
9702   ins_pipe( fpu_reg_reg_reg );
9703 %}
9704 
9705 
9706 // MACRO3 -- subDPR a mulDPR
9707 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9708   predicate( UseSSE<=1 );
9709   match(Set src2 (SubD (MulD src0 src1) src2));
9710   format %{ "FLD    $src0\t# ===MACRO3d===\n\t"
9711             "DMUL   ST,$src1\n\t"
9712             "DSUBRp $src2,ST" %}
9713   ins_cost(250);
9714   ins_encode( Push_Reg_FPR(src0),
9715               FMul_ST_reg(src1),
9716               Opcode(0xDE), Opc_plus(0xE0,src2));
9717   ins_pipe( fpu_reg_reg_reg );
9718 %}
9719 
9720 
9721 instruct divDPR_reg(regDPR dst, regDPR src) %{
9722   predicate( UseSSE<=1 );
9723   match(Set dst (DivD dst src));
9724 
9725   format %{ "FLD    $src\n\t"
9726             "FDIVp  $dst,ST" %}
9727   opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9728   ins_cost(150);
9729   ins_encode( Push_Reg_DPR(src),
9730               OpcP, RegOpc(dst) );
9731   ins_pipe( fpu_reg_reg );
9732 %}
9733 
9734 // Strict FP instruction biases argument before division then
9735 // biases result, to avoid double rounding of subnormals.
9736 //
9737 // scale dividend by multiplying dividend by 2^(-15360)
9738 // load divisor
9739 // divide scaled dividend by divisor
9740 // rescale quotient by 2^(15360)
9741 //
9742 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9743   predicate (UseSSE<=1);
9744   match(Set dst (DivD dst src));
9745   predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9746   ins_cost(01);
9747 
9748   format %{ "FLD    StubRoutines::_fpu_subnormal_bias1\n\t"
9749             "DMULp  $dst,ST\n\t"
9750             "FLD    $src\n\t"
9751             "FDIVp  $dst,ST\n\t"
9752             "FLD    StubRoutines::_fpu_subnormal_bias2\n\t"
9753             "DMULp  $dst,ST\n\t" %}
9754   opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9755   ins_encode( strictfp_bias1(dst),
9756               Push_Reg_DPR(src),
9757               OpcP, RegOpc(dst),
9758               strictfp_bias2(dst) );
9759   ins_pipe( fpu_reg_reg );
9760 %}
9761 
9762 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9763   predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9764   match(Set dst (RoundDouble (DivD src1 src2)));
9765 
9766   format %{ "FLD    $src1\n\t"
9767             "FDIV   ST,$src2\n\t"
9768             "FSTP_D $dst\t# D-round" %}
9769   opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9770   ins_encode( Push_Reg_DPR(src1),
9771               OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9772   ins_pipe( fpu_mem_reg_reg );
9773 %}
9774 
9775 
9776 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9777   predicate(UseSSE<=1);
9778   match(Set dst (ModD dst src));
9779   effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9780 
9781   format %{ "DMOD   $dst,$src" %}
9782   ins_cost(250);
9783   ins_encode(Push_Reg_Mod_DPR(dst, src),
9784               emitModDPR(),
9785               Push_Result_Mod_DPR(src),
9786               Pop_Reg_DPR(dst));
9787   ins_pipe( pipe_slow );
9788 %}
9789 
9790 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9791   predicate(UseSSE>=2);
9792   match(Set dst (ModD src0 src1));
9793   effect(KILL rax, KILL cr);
9794 
9795   format %{ "SUB    ESP,8\t # DMOD\n"
9796           "\tMOVSD  [ESP+0],$src1\n"
9797           "\tFLD_D  [ESP+0]\n"
9798           "\tMOVSD  [ESP+0],$src0\n"
9799           "\tFLD_D  [ESP+0]\n"
9800      "loop:\tFPREM\n"
9801           "\tFWAIT\n"
9802           "\tFNSTSW AX\n"
9803           "\tSAHF\n"
9804           "\tJP     loop\n"
9805           "\tFSTP_D [ESP+0]\n"
9806           "\tMOVSD  $dst,[ESP+0]\n"
9807           "\tADD    ESP,8\n"
9808           "\tFSTP   ST0\t # Restore FPU Stack"
9809     %}
9810   ins_cost(250);
9811   ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9812   ins_pipe( pipe_slow );
9813 %}
9814 
9815 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9816   predicate (UseSSE<=1);
9817   match(Set dst (SinD src));
9818   ins_cost(1800);
9819   format %{ "DSIN   $dst" %}
9820   opcode(0xD9, 0xFE);
9821   ins_encode( OpcP, OpcS );
9822   ins_pipe( pipe_slow );
9823 %}
9824 
9825 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9826   predicate (UseSSE>=2);
9827   match(Set dst (SinD dst));
9828   effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9829   ins_cost(1800);
9830   format %{ "DSIN   $dst" %}
9831   opcode(0xD9, 0xFE);
9832   ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9833   ins_pipe( pipe_slow );
9834 %}
9835 
9836 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9837   predicate (UseSSE<=1);
9838   match(Set dst (CosD src));
9839   ins_cost(1800);
9840   format %{ "DCOS   $dst" %}
9841   opcode(0xD9, 0xFF);
9842   ins_encode( OpcP, OpcS );
9843   ins_pipe( pipe_slow );
9844 %}
9845 
9846 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9847   predicate (UseSSE>=2);
9848   match(Set dst (CosD dst));
9849   effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9850   ins_cost(1800);
9851   format %{ "DCOS   $dst" %}
9852   opcode(0xD9, 0xFF);
9853   ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9854   ins_pipe( pipe_slow );
9855 %}
9856 
9857 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9858   predicate (UseSSE<=1);
9859   match(Set dst(TanD src));
9860   format %{ "DTAN   $dst" %}
9861   ins_encode( Opcode(0xD9), Opcode(0xF2),    // fptan
9862               Opcode(0xDD), Opcode(0xD8));   // fstp st
9863   ins_pipe( pipe_slow );
9864 %}
9865 
9866 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9867   predicate (UseSSE>=2);
9868   match(Set dst(TanD dst));
9869   effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9870   format %{ "DTAN   $dst" %}
9871   ins_encode( Push_SrcD(dst),
9872               Opcode(0xD9), Opcode(0xF2),    // fptan
9873               Opcode(0xDD), Opcode(0xD8),   // fstp st
9874               Push_ResultD(dst) );
9875   ins_pipe( pipe_slow );
9876 %}
9877 
9878 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9879   predicate (UseSSE<=1);
9880   match(Set dst(AtanD dst src));
9881   format %{ "DATA   $dst,$src" %}
9882   opcode(0xD9, 0xF3);
9883   ins_encode( Push_Reg_DPR(src),
9884               OpcP, OpcS, RegOpc(dst) );
9885   ins_pipe( pipe_slow );
9886 %}
9887 
9888 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9889   predicate (UseSSE>=2);
9890   match(Set dst(AtanD dst src));
9891   effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9892   format %{ "DATA   $dst,$src" %}
9893   opcode(0xD9, 0xF3);
9894   ins_encode( Push_SrcD(src),
9895               OpcP, OpcS, Push_ResultD(dst) );
9896   ins_pipe( pipe_slow );
9897 %}
9898 
9899 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9900   predicate (UseSSE<=1);
9901   match(Set dst (SqrtD src));
9902   format %{ "DSQRT  $dst,$src" %}
9903   opcode(0xFA, 0xD9);
9904   ins_encode( Push_Reg_DPR(src),
9905               OpcS, OpcP, Pop_Reg_DPR(dst) );
9906   ins_pipe( pipe_slow );
9907 %}
9908 
9909 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9910   predicate (UseSSE<=1);
9911   match(Set Y (PowD X Y));  // Raise X to the Yth power
9912   effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9913   format %{ "fast_pow $X $Y -> $Y  // KILL $rax, $rcx, $rdx" %}
9914   ins_encode %{
9915     __ subptr(rsp, 8);
9916     __ fld_s($X$$reg - 1);
9917     __ fast_pow();
9918     __ addptr(rsp, 8);
9919   %}
9920   ins_pipe( pipe_slow );
9921 %}
9922 
9923 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9924   predicate (UseSSE>=2);
9925   match(Set dst (PowD src0 src1));  // Raise src0 to the src1'th power
9926   effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9927   format %{ "fast_pow $src0 $src1 -> $dst  // KILL $rax, $rcx, $rdx" %}
9928   ins_encode %{
9929     __ subptr(rsp, 8);
9930     __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9931     __ fld_d(Address(rsp, 0));
9932     __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9933     __ fld_d(Address(rsp, 0));
9934     __ fast_pow();
9935     __ fstp_d(Address(rsp, 0));
9936     __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9937     __ addptr(rsp, 8);
9938   %}
9939   ins_pipe( pipe_slow );
9940 %}
9941 
9942 
9943 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9944   predicate (UseSSE<=1);
9945   match(Set dpr1 (ExpD dpr1));
9946   effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9947   format %{ "fast_exp $dpr1 -> $dpr1  // KILL $rax, $rcx, $rdx" %}
9948   ins_encode %{
9949     __ fast_exp();
9950   %}
9951   ins_pipe( pipe_slow );
9952 %}
9953 
9954 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9955   predicate (UseSSE>=2);
9956   match(Set dst (ExpD src));
9957   effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9958   format %{ "fast_exp $dst -> $src  // KILL $rax, $rcx, $rdx" %}
9959   ins_encode %{
9960     __ subptr(rsp, 8);
9961     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9962     __ fld_d(Address(rsp, 0));
9963     __ fast_exp();
9964     __ fstp_d(Address(rsp, 0));
9965     __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9966     __ addptr(rsp, 8);
9967   %}
9968   ins_pipe( pipe_slow );
9969 %}
9970 
9971 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
9972   predicate (UseSSE<=1);
9973   // The source Double operand on FPU stack
9974   match(Set dst (Log10D src));
9975   // fldlg2       ; push log_10(2) on the FPU stack; full 80-bit number
9976   // fxch         ; swap ST(0) with ST(1)
9977   // fyl2x        ; compute log_10(2) * log_2(x)
9978   format %{ "FLDLG2 \t\t\t#Log10\n\t"
9979             "FXCH   \n\t"
9980             "FYL2X  \t\t\t# Q=Log10*Log_2(x)"
9981          %}
9982   ins_encode( Opcode(0xD9), Opcode(0xEC),   // fldlg2
9983               Opcode(0xD9), Opcode(0xC9),   // fxch
9984               Opcode(0xD9), Opcode(0xF1));  // fyl2x
9985 
9986   ins_pipe( pipe_slow );
9987 %}
9988 
9989 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
9990   predicate (UseSSE>=2);
9991   effect(KILL cr);
9992   match(Set dst (Log10D src));
9993   // fldlg2       ; push log_10(2) on the FPU stack; full 80-bit number
9994   // fyl2x        ; compute log_10(2) * log_2(x)
9995   format %{ "FLDLG2 \t\t\t#Log10\n\t"
9996             "FYL2X  \t\t\t# Q=Log10*Log_2(x)"
9997          %}
9998   ins_encode( Opcode(0xD9), Opcode(0xEC),   // fldlg2
9999               Push_SrcD(src),
10000               Opcode(0xD9), Opcode(0xF1),   // fyl2x
10001               Push_ResultD(dst));
10002 
10003   ins_pipe( pipe_slow );
10004 %}
10005 
10006 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10007   predicate (UseSSE<=1);
10008   // The source Double operand on FPU stack
10009   match(Set dst (LogD src));
10010   // fldln2       ; push log_e(2) on the FPU stack; full 80-bit number
10011   // fxch         ; swap ST(0) with ST(1)
10012   // fyl2x        ; compute log_e(2) * log_2(x)
10013   format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10014             "FXCH   \n\t"
10015             "FYL2X  \t\t\t# Q=Log_e*Log_2(x)"
10016          %}
10017   ins_encode( Opcode(0xD9), Opcode(0xED),   // fldln2
10018               Opcode(0xD9), Opcode(0xC9),   // fxch
10019               Opcode(0xD9), Opcode(0xF1));  // fyl2x
10020 
10021   ins_pipe( pipe_slow );
10022 %}
10023 
10024 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10025   predicate (UseSSE>=2);
10026   effect(KILL cr);
10027   // The source and result Double operands in XMM registers
10028   match(Set dst (LogD src));
10029   // fldln2       ; push log_e(2) on the FPU stack; full 80-bit number
10030   // fyl2x        ; compute log_e(2) * log_2(x)
10031   format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10032             "FYL2X  \t\t\t# Q=Log_e*Log_2(x)"
10033          %}
10034   ins_encode( Opcode(0xD9), Opcode(0xED),   // fldln2
10035               Push_SrcD(src),
10036               Opcode(0xD9), Opcode(0xF1),   // fyl2x
10037               Push_ResultD(dst));
10038   ins_pipe( pipe_slow );
10039 %}
10040 
10041 //-------------Float Instructions-------------------------------
10042 // Float Math
10043 
10044 // Code for float compare:
10045 //     fcompp();
10046 //     fwait(); fnstsw_ax();
10047 //     sahf();
10048 //     movl(dst, unordered_result);
10049 //     jcc(Assembler::parity, exit);
10050 //     movl(dst, less_result);
10051 //     jcc(Assembler::below, exit);
10052 //     movl(dst, equal_result);
10053 //     jcc(Assembler::equal, exit);
10054 //     movl(dst, greater_result);
10055 //   exit:
10056 
10057 // P6 version of float compare, sets condition codes in EFLAGS
10058 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10059   predicate(VM_Version::supports_cmov() && UseSSE == 0);
10060   match(Set cr (CmpF src1 src2));
10061   effect(KILL rax);
10062   ins_cost(150);
10063   format %{ "FLD    $src1\n\t"
10064             "FUCOMIP ST,$src2  // P6 instruction\n\t"
10065             "JNP    exit\n\t"
10066             "MOV    ah,1       // saw a NaN, set CF (treat as LT)\n\t"
10067             "SAHF\n"
10068      "exit:\tNOP               // avoid branch to branch" %}
10069   opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10070   ins_encode( Push_Reg_DPR(src1),
10071               OpcP, RegOpc(src2),
10072               cmpF_P6_fixup );
10073   ins_pipe( pipe_slow );
10074 %}
10075 
10076 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10077   predicate(VM_Version::supports_cmov() && UseSSE == 0);
10078   match(Set cr (CmpF src1 src2));
10079   ins_cost(100);
10080   format %{ "FLD    $src1\n\t"
10081             "FUCOMIP ST,$src2  // P6 instruction" %}
10082   opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10083   ins_encode( Push_Reg_DPR(src1),
10084               OpcP, RegOpc(src2));
10085   ins_pipe( pipe_slow );
10086 %}
10087 
10088 
10089 // Compare & branch
10090 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10091   predicate(UseSSE == 0);
10092   match(Set cr (CmpF src1 src2));
10093   effect(KILL rax);
10094   ins_cost(200);
10095   format %{ "FLD    $src1\n\t"
10096             "FCOMp  $src2\n\t"
10097             "FNSTSW AX\n\t"
10098             "TEST   AX,0x400\n\t"
10099             "JZ,s   flags\n\t"
10100             "MOV    AH,1\t# unordered treat as LT\n"
10101     "flags:\tSAHF" %}
10102   opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10103   ins_encode( Push_Reg_DPR(src1),
10104               OpcP, RegOpc(src2),
10105               fpu_flags);
10106   ins_pipe( pipe_slow );
10107 %}
10108 
10109 // Compare vs zero into -1,0,1
10110 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10111   predicate(UseSSE == 0);
10112   match(Set dst (CmpF3 src1 zero));
10113   effect(KILL cr, KILL rax);
10114   ins_cost(280);
10115   format %{ "FTSTF  $dst,$src1" %}
10116   opcode(0xE4, 0xD9);
10117   ins_encode( Push_Reg_DPR(src1),
10118               OpcS, OpcP, PopFPU,
10119               CmpF_Result(dst));
10120   ins_pipe( pipe_slow );
10121 %}
10122 
10123 // Compare into -1,0,1
10124 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10125   predicate(UseSSE == 0);
10126   match(Set dst (CmpF3 src1 src2));
10127   effect(KILL cr, KILL rax);
10128   ins_cost(300);
10129   format %{ "FCMPF  $dst,$src1,$src2" %}
10130   opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10131   ins_encode( Push_Reg_DPR(src1),
10132               OpcP, RegOpc(src2),
10133               CmpF_Result(dst));
10134   ins_pipe( pipe_slow );
10135 %}
10136 
10137 // float compare and set condition codes in EFLAGS by XMM regs
10138 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10139   predicate(UseSSE>=1);
10140   match(Set cr (CmpF src1 src2));
10141   ins_cost(145);
10142   format %{ "UCOMISS $src1,$src2\n\t"
10143             "JNP,s   exit\n\t"
10144             "PUSHF\t# saw NaN, set CF\n\t"
10145             "AND     [rsp], #0xffffff2b\n\t"
10146             "POPF\n"
10147     "exit:" %}
10148   ins_encode %{
10149     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10150     emit_cmpfp_fixup(_masm);
10151   %}
10152   ins_pipe( pipe_slow );
10153 %}
10154 
10155 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10156   predicate(UseSSE>=1);
10157   match(Set cr (CmpF src1 src2));
10158   ins_cost(100);
10159   format %{ "UCOMISS $src1,$src2" %}
10160   ins_encode %{
10161     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10162   %}
10163   ins_pipe( pipe_slow );
10164 %}
10165 
10166 // float compare and set condition codes in EFLAGS by XMM regs
10167 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10168   predicate(UseSSE>=1);
10169   match(Set cr (CmpF src1 (LoadF src2)));
10170   ins_cost(165);
10171   format %{ "UCOMISS $src1,$src2\n\t"
10172             "JNP,s   exit\n\t"
10173             "PUSHF\t# saw NaN, set CF\n\t"
10174             "AND     [rsp], #0xffffff2b\n\t"
10175             "POPF\n"
10176     "exit:" %}
10177   ins_encode %{
10178     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10179     emit_cmpfp_fixup(_masm);
10180   %}
10181   ins_pipe( pipe_slow );
10182 %}
10183 
10184 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10185   predicate(UseSSE>=1);
10186   match(Set cr (CmpF src1 (LoadF src2)));
10187   ins_cost(100);
10188   format %{ "UCOMISS $src1,$src2" %}
10189   ins_encode %{
10190     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10191   %}
10192   ins_pipe( pipe_slow );
10193 %}
10194 
10195 // Compare into -1,0,1 in XMM
10196 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10197   predicate(UseSSE>=1);
10198   match(Set dst (CmpF3 src1 src2));
10199   effect(KILL cr);
10200   ins_cost(255);
10201   format %{ "UCOMISS $src1, $src2\n\t"
10202             "MOV     $dst, #-1\n\t"
10203             "JP,s    done\n\t"
10204             "JB,s    done\n\t"
10205             "SETNE   $dst\n\t"
10206             "MOVZB   $dst, $dst\n"
10207     "done:" %}
10208   ins_encode %{
10209     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10210     emit_cmpfp3(_masm, $dst$$Register);
10211   %}
10212   ins_pipe( pipe_slow );
10213 %}
10214 
10215 // Compare into -1,0,1 in XMM and memory
10216 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10217   predicate(UseSSE>=1);
10218   match(Set dst (CmpF3 src1 (LoadF src2)));
10219   effect(KILL cr);
10220   ins_cost(275);
10221   format %{ "UCOMISS $src1, $src2\n\t"
10222             "MOV     $dst, #-1\n\t"
10223             "JP,s    done\n\t"
10224             "JB,s    done\n\t"
10225             "SETNE   $dst\n\t"
10226             "MOVZB   $dst, $dst\n"
10227     "done:" %}
10228   ins_encode %{
10229     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10230     emit_cmpfp3(_masm, $dst$$Register);
10231   %}
10232   ins_pipe( pipe_slow );
10233 %}
10234 
10235 // Spill to obtain 24-bit precision
10236 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10237   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10238   match(Set dst (SubF src1 src2));
10239 
10240   format %{ "FSUB   $dst,$src1 - $src2" %}
10241   opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10242   ins_encode( Push_Reg_FPR(src1),
10243               OpcReg_FPR(src2),
10244               Pop_Mem_FPR(dst) );
10245   ins_pipe( fpu_mem_reg_reg );
10246 %}
10247 //
10248 // This instruction does not round to 24-bits
10249 instruct subFPR_reg(regFPR dst, regFPR src) %{
10250   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10251   match(Set dst (SubF dst src));
10252 
10253   format %{ "FSUB   $dst,$src" %}
10254   opcode(0xDE, 0x5); /* DE E8+i  or DE /5 */
10255   ins_encode( Push_Reg_FPR(src),
10256               OpcP, RegOpc(dst) );
10257   ins_pipe( fpu_reg_reg );
10258 %}
10259 
10260 // Spill to obtain 24-bit precision
10261 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10262   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10263   match(Set dst (AddF src1 src2));
10264 
10265   format %{ "FADD   $dst,$src1,$src2" %}
10266   opcode(0xD8, 0x0); /* D8 C0+i */
10267   ins_encode( Push_Reg_FPR(src2),
10268               OpcReg_FPR(src1),
10269               Pop_Mem_FPR(dst) );
10270   ins_pipe( fpu_mem_reg_reg );
10271 %}
10272 //
10273 // This instruction does not round to 24-bits
10274 instruct addFPR_reg(regFPR dst, regFPR src) %{
10275   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10276   match(Set dst (AddF dst src));
10277 
10278   format %{ "FLD    $src\n\t"
10279             "FADDp  $dst,ST" %}
10280   opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10281   ins_encode( Push_Reg_FPR(src),
10282               OpcP, RegOpc(dst) );
10283   ins_pipe( fpu_reg_reg );
10284 %}
10285 
10286 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10287   predicate(UseSSE==0);
10288   match(Set dst (AbsF src));
10289   ins_cost(100);
10290   format %{ "FABS" %}
10291   opcode(0xE1, 0xD9);
10292   ins_encode( OpcS, OpcP );
10293   ins_pipe( fpu_reg_reg );
10294 %}
10295 
10296 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10297   predicate(UseSSE==0);
10298   match(Set dst (NegF src));
10299   ins_cost(100);
10300   format %{ "FCHS" %}
10301   opcode(0xE0, 0xD9);
10302   ins_encode( OpcS, OpcP );
10303   ins_pipe( fpu_reg_reg );
10304 %}
10305 
10306 // Cisc-alternate to addFPR_reg
10307 // Spill to obtain 24-bit precision
10308 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10309   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10310   match(Set dst (AddF src1 (LoadF src2)));
10311 
10312   format %{ "FLD    $src2\n\t"
10313             "FADD   ST,$src1\n\t"
10314             "FSTP_S $dst" %}
10315   opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */  /* LoadF  D9 /0 */
10316   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10317               OpcReg_FPR(src1),
10318               Pop_Mem_FPR(dst) );
10319   ins_pipe( fpu_mem_reg_mem );
10320 %}
10321 //
10322 // Cisc-alternate to addFPR_reg
10323 // This instruction does not round to 24-bits
10324 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10325   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10326   match(Set dst (AddF dst (LoadF src)));
10327 
10328   format %{ "FADD   $dst,$src" %}
10329   opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/  /* LoadF  D9 /0 */
10330   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10331               OpcP, RegOpc(dst) );
10332   ins_pipe( fpu_reg_mem );
10333 %}
10334 
10335 // // Following two instructions for _222_mpegaudio
10336 // Spill to obtain 24-bit precision
10337 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10338   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10339   match(Set dst (AddF src1 src2));
10340 
10341   format %{ "FADD   $dst,$src1,$src2" %}
10342   opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */  /* LoadF  D9 /0 */
10343   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10344               OpcReg_FPR(src2),
10345               Pop_Mem_FPR(dst) );
10346   ins_pipe( fpu_mem_reg_mem );
10347 %}
10348 
10349 // Cisc-spill variant
10350 // Spill to obtain 24-bit precision
10351 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10352   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10353   match(Set dst (AddF src1 (LoadF src2)));
10354 
10355   format %{ "FADD   $dst,$src1,$src2 cisc" %}
10356   opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */  /* LoadF  D9 /0 */
10357   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10358               set_instruction_start,
10359               OpcP, RMopc_Mem(secondary,src1),
10360               Pop_Mem_FPR(dst) );
10361   ins_pipe( fpu_mem_mem_mem );
10362 %}
10363 
10364 // Spill to obtain 24-bit precision
10365 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10366   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10367   match(Set dst (AddF src1 src2));
10368 
10369   format %{ "FADD   $dst,$src1,$src2" %}
10370   opcode(0xD8, 0x0, 0xD9); /* D8 /0 */  /* LoadF  D9 /0 */
10371   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10372               set_instruction_start,
10373               OpcP, RMopc_Mem(secondary,src1),
10374               Pop_Mem_FPR(dst) );
10375   ins_pipe( fpu_mem_mem_mem );
10376 %}
10377 
10378 
10379 // Spill to obtain 24-bit precision
10380 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10381   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10382   match(Set dst (AddF src con));
10383   format %{ "FLD    $src\n\t"
10384             "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10385             "FSTP_S $dst"  %}
10386   ins_encode %{
10387     __ fld_s($src$$reg - 1);  // FLD ST(i-1)
10388     __ fadd_s($constantaddress($con));
10389     __ fstp_s(Address(rsp, $dst$$disp));
10390   %}
10391   ins_pipe(fpu_mem_reg_con);
10392 %}
10393 //
10394 // This instruction does not round to 24-bits
10395 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10396   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10397   match(Set dst (AddF src con));
10398   format %{ "FLD    $src\n\t"
10399             "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10400             "FSTP   $dst"  %}
10401   ins_encode %{
10402     __ fld_s($src$$reg - 1);  // FLD ST(i-1)
10403     __ fadd_s($constantaddress($con));
10404     __ fstp_d($dst$$reg);
10405   %}
10406   ins_pipe(fpu_reg_reg_con);
10407 %}
10408 
10409 // Spill to obtain 24-bit precision
10410 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10411   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10412   match(Set dst (MulF src1 src2));
10413 
10414   format %{ "FLD    $src1\n\t"
10415             "FMUL   $src2\n\t"
10416             "FSTP_S $dst"  %}
10417   opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10418   ins_encode( Push_Reg_FPR(src1),
10419               OpcReg_FPR(src2),
10420               Pop_Mem_FPR(dst) );
10421   ins_pipe( fpu_mem_reg_reg );
10422 %}
10423 //
10424 // This instruction does not round to 24-bits
10425 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10426   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10427   match(Set dst (MulF src1 src2));
10428 
10429   format %{ "FLD    $src1\n\t"
10430             "FMUL   $src2\n\t"
10431             "FSTP_S $dst"  %}
10432   opcode(0xD8, 0x1); /* D8 C8+i */
10433   ins_encode( Push_Reg_FPR(src2),
10434               OpcReg_FPR(src1),
10435               Pop_Reg_FPR(dst) );
10436   ins_pipe( fpu_reg_reg_reg );
10437 %}
10438 
10439 
10440 // Spill to obtain 24-bit precision
10441 // Cisc-alternate to reg-reg multiply
10442 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10443   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10444   match(Set dst (MulF src1 (LoadF src2)));
10445 
10446   format %{ "FLD_S  $src2\n\t"
10447             "FMUL   $src1\n\t"
10448             "FSTP_S $dst"  %}
10449   opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/  /* LoadF D9 /0 */
10450   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10451               OpcReg_FPR(src1),
10452               Pop_Mem_FPR(dst) );
10453   ins_pipe( fpu_mem_reg_mem );
10454 %}
10455 //
10456 // This instruction does not round to 24-bits
10457 // Cisc-alternate to reg-reg multiply
10458 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10459   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10460   match(Set dst (MulF src1 (LoadF src2)));
10461 
10462   format %{ "FMUL   $dst,$src1,$src2" %}
10463   opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */  /* LoadF D9 /0 */
10464   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10465               OpcReg_FPR(src1),
10466               Pop_Reg_FPR(dst) );
10467   ins_pipe( fpu_reg_reg_mem );
10468 %}
10469 
10470 // Spill to obtain 24-bit precision
10471 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10472   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10473   match(Set dst (MulF src1 src2));
10474 
10475   format %{ "FMUL   $dst,$src1,$src2" %}
10476   opcode(0xD8, 0x1, 0xD9); /* D8 /1 */  /* LoadF D9 /0 */
10477   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10478               set_instruction_start,
10479               OpcP, RMopc_Mem(secondary,src1),
10480               Pop_Mem_FPR(dst) );
10481   ins_pipe( fpu_mem_mem_mem );
10482 %}
10483 
10484 // Spill to obtain 24-bit precision
10485 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10486   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10487   match(Set dst (MulF src con));
10488 
10489   format %{ "FLD    $src\n\t"
10490             "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10491             "FSTP_S $dst"  %}
10492   ins_encode %{
10493     __ fld_s($src$$reg - 1);  // FLD ST(i-1)
10494     __ fmul_s($constantaddress($con));
10495     __ fstp_s(Address(rsp, $dst$$disp));
10496   %}
10497   ins_pipe(fpu_mem_reg_con);
10498 %}
10499 //
10500 // This instruction does not round to 24-bits
10501 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10502   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10503   match(Set dst (MulF src con));
10504 
10505   format %{ "FLD    $src\n\t"
10506             "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10507             "FSTP   $dst"  %}
10508   ins_encode %{
10509     __ fld_s($src$$reg - 1);  // FLD ST(i-1)
10510     __ fmul_s($constantaddress($con));
10511     __ fstp_d($dst$$reg);
10512   %}
10513   ins_pipe(fpu_reg_reg_con);
10514 %}
10515 
10516 
10517 //
10518 // MACRO1 -- subsume unshared load into mulFPR
10519 // This instruction does not round to 24-bits
10520 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10521   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10522   match(Set dst (MulF (LoadF mem1) src));
10523 
10524   format %{ "FLD    $mem1    ===MACRO1===\n\t"
10525             "FMUL   ST,$src\n\t"
10526             "FSTP   $dst" %}
10527   opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */  /* LoadF D9 /0 */
10528   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10529               OpcReg_FPR(src),
10530               Pop_Reg_FPR(dst) );
10531   ins_pipe( fpu_reg_reg_mem );
10532 %}
10533 //
10534 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10535 // This instruction does not round to 24-bits
10536 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10537   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10538   match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10539   ins_cost(95);
10540 
10541   format %{ "FLD    $mem1     ===MACRO2===\n\t"
10542             "FMUL   ST,$src1  subsume mulFPR left load\n\t"
10543             "FADD   ST,$src2\n\t"
10544             "FSTP   $dst" %}
10545   opcode(0xD9); /* LoadF D9 /0 */
10546   ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10547               FMul_ST_reg(src1),
10548               FAdd_ST_reg(src2),
10549               Pop_Reg_FPR(dst) );
10550   ins_pipe( fpu_reg_mem_reg_reg );
10551 %}
10552 
10553 // MACRO3 -- addFPR a mulFPR
10554 // This instruction does not round to 24-bits.  It is a '2-address'
10555 // instruction in that the result goes back to src2.  This eliminates
10556 // a move from the macro; possibly the register allocator will have
10557 // to add it back (and maybe not).
10558 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10559   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10560   match(Set src2 (AddF (MulF src0 src1) src2));
10561 
10562   format %{ "FLD    $src0     ===MACRO3===\n\t"
10563             "FMUL   ST,$src1\n\t"
10564             "FADDP  $src2,ST" %}
10565   opcode(0xD9); /* LoadF D9 /0 */
10566   ins_encode( Push_Reg_FPR(src0),
10567               FMul_ST_reg(src1),
10568               FAddP_reg_ST(src2) );
10569   ins_pipe( fpu_reg_reg_reg );
10570 %}
10571 
10572 // MACRO4 -- divFPR subFPR
10573 // This instruction does not round to 24-bits
10574 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10575   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10576   match(Set dst (DivF (SubF src2 src1) src3));
10577 
10578   format %{ "FLD    $src2   ===MACRO4===\n\t"
10579             "FSUB   ST,$src1\n\t"
10580             "FDIV   ST,$src3\n\t"
10581             "FSTP  $dst" %}
10582   opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10583   ins_encode( Push_Reg_FPR(src2),
10584               subFPR_divFPR_encode(src1,src3),
10585               Pop_Reg_FPR(dst) );
10586   ins_pipe( fpu_reg_reg_reg_reg );
10587 %}
10588 
10589 // Spill to obtain 24-bit precision
10590 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10591   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10592   match(Set dst (DivF src1 src2));
10593 
10594   format %{ "FDIV   $dst,$src1,$src2" %}
10595   opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10596   ins_encode( Push_Reg_FPR(src1),
10597               OpcReg_FPR(src2),
10598               Pop_Mem_FPR(dst) );
10599   ins_pipe( fpu_mem_reg_reg );
10600 %}
10601 //
10602 // This instruction does not round to 24-bits
10603 instruct divFPR_reg(regFPR dst, regFPR src) %{
10604   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10605   match(Set dst (DivF dst src));
10606 
10607   format %{ "FDIV   $dst,$src" %}
10608   opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10609   ins_encode( Push_Reg_FPR(src),
10610               OpcP, RegOpc(dst) );
10611   ins_pipe( fpu_reg_reg );
10612 %}
10613 
10614 
10615 // Spill to obtain 24-bit precision
10616 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10617   predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10618   match(Set dst (ModF src1 src2));
10619   effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10620 
10621   format %{ "FMOD   $dst,$src1,$src2" %}
10622   ins_encode( Push_Reg_Mod_DPR(src1, src2),
10623               emitModDPR(),
10624               Push_Result_Mod_DPR(src2),
10625               Pop_Mem_FPR(dst));
10626   ins_pipe( pipe_slow );
10627 %}
10628 //
10629 // This instruction does not round to 24-bits
10630 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10631   predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10632   match(Set dst (ModF dst src));
10633   effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10634 
10635   format %{ "FMOD   $dst,$src" %}
10636   ins_encode(Push_Reg_Mod_DPR(dst, src),
10637               emitModDPR(),
10638               Push_Result_Mod_DPR(src),
10639               Pop_Reg_FPR(dst));
10640   ins_pipe( pipe_slow );
10641 %}
10642 
10643 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10644   predicate(UseSSE>=1);
10645   match(Set dst (ModF src0 src1));
10646   effect(KILL rax, KILL cr);
10647   format %{ "SUB    ESP,4\t # FMOD\n"
10648           "\tMOVSS  [ESP+0],$src1\n"
10649           "\tFLD_S  [ESP+0]\n"
10650           "\tMOVSS  [ESP+0],$src0\n"
10651           "\tFLD_S  [ESP+0]\n"
10652      "loop:\tFPREM\n"
10653           "\tFWAIT\n"
10654           "\tFNSTSW AX\n"
10655           "\tSAHF\n"
10656           "\tJP     loop\n"
10657           "\tFSTP_S [ESP+0]\n"
10658           "\tMOVSS  $dst,[ESP+0]\n"
10659           "\tADD    ESP,4\n"
10660           "\tFSTP   ST0\t # Restore FPU Stack"
10661     %}
10662   ins_cost(250);
10663   ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10664   ins_pipe( pipe_slow );
10665 %}
10666 
10667 
10668 //----------Arithmetic Conversion Instructions---------------------------------
10669 // The conversions operations are all Alpha sorted.  Please keep it that way!
10670 
10671 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10672   predicate(UseSSE==0);
10673   match(Set dst (RoundFloat src));
10674   ins_cost(125);
10675   format %{ "FST_S  $dst,$src\t# F-round" %}
10676   ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10677   ins_pipe( fpu_mem_reg );
10678 %}
10679 
10680 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10681   predicate(UseSSE<=1);
10682   match(Set dst (RoundDouble src));
10683   ins_cost(125);
10684   format %{ "FST_D  $dst,$src\t# D-round" %}
10685   ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10686   ins_pipe( fpu_mem_reg );
10687 %}
10688 
10689 // Force rounding to 24-bit precision and 6-bit exponent
10690 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10691   predicate(UseSSE==0);
10692   match(Set dst (ConvD2F src));
10693   format %{ "FST_S  $dst,$src\t# F-round" %}
10694   expand %{
10695     roundFloat_mem_reg(dst,src);
10696   %}
10697 %}
10698 
10699 // Force rounding to 24-bit precision and 6-bit exponent
10700 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10701   predicate(UseSSE==1);
10702   match(Set dst (ConvD2F src));
10703   effect( KILL cr );
10704   format %{ "SUB    ESP,4\n\t"
10705             "FST_S  [ESP],$src\t# F-round\n\t"
10706             "MOVSS  $dst,[ESP]\n\t"
10707             "ADD ESP,4" %}
10708   ins_encode %{
10709     __ subptr(rsp, 4);
10710     if ($src$$reg != FPR1L_enc) {
10711       __ fld_s($src$$reg-1);
10712       __ fstp_s(Address(rsp, 0));
10713     } else {
10714       __ fst_s(Address(rsp, 0));
10715     }
10716     __ movflt($dst$$XMMRegister, Address(rsp, 0));
10717     __ addptr(rsp, 4);
10718   %}
10719   ins_pipe( pipe_slow );
10720 %}
10721 
10722 // Force rounding double precision to single precision
10723 instruct convD2F_reg(regF dst, regD src) %{
10724   predicate(UseSSE>=2);
10725   match(Set dst (ConvD2F src));
10726   format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10727   ins_encode %{
10728     __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10729   %}
10730   ins_pipe( pipe_slow );
10731 %}
10732 
10733 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10734   predicate(UseSSE==0);
10735   match(Set dst (ConvF2D src));
10736   format %{ "FST_S  $dst,$src\t# D-round" %}
10737   ins_encode( Pop_Reg_Reg_DPR(dst, src));
10738   ins_pipe( fpu_reg_reg );
10739 %}
10740 
10741 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10742   predicate(UseSSE==1);
10743   match(Set dst (ConvF2D src));
10744   format %{ "FST_D  $dst,$src\t# D-round" %}
10745   expand %{
10746     roundDouble_mem_reg(dst,src);
10747   %}
10748 %}
10749 
10750 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10751   predicate(UseSSE==1);
10752   match(Set dst (ConvF2D src));
10753   effect( KILL cr );
10754   format %{ "SUB    ESP,4\n\t"
10755             "MOVSS  [ESP] $src\n\t"
10756             "FLD_S  [ESP]\n\t"
10757             "ADD    ESP,4\n\t"
10758             "FSTP   $dst\t# D-round" %}
10759   ins_encode %{
10760     __ subptr(rsp, 4);
10761     __ movflt(Address(rsp, 0), $src$$XMMRegister);
10762     __ fld_s(Address(rsp, 0));
10763     __ addptr(rsp, 4);
10764     __ fstp_d($dst$$reg);
10765   %}
10766   ins_pipe( pipe_slow );
10767 %}
10768 
10769 instruct convF2D_reg(regD dst, regF src) %{
10770   predicate(UseSSE>=2);
10771   match(Set dst (ConvF2D src));
10772   format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10773   ins_encode %{
10774     __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10775   %}
10776   ins_pipe( pipe_slow );
10777 %}
10778 
10779 // Convert a double to an int.  If the double is a NAN, stuff a zero in instead.
10780 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10781   predicate(UseSSE<=1);
10782   match(Set dst (ConvD2I src));
10783   effect( KILL tmp, KILL cr );
10784   format %{ "FLD    $src\t# Convert double to int \n\t"
10785             "FLDCW  trunc mode\n\t"
10786             "SUB    ESP,4\n\t"
10787             "FISTp  [ESP + #0]\n\t"
10788             "FLDCW  std/24-bit mode\n\t"
10789             "POP    EAX\n\t"
10790             "CMP    EAX,0x80000000\n\t"
10791             "JNE,s  fast\n\t"
10792             "FLD_D  $src\n\t"
10793             "CALL   d2i_wrapper\n"
10794       "fast:" %}
10795   ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10796   ins_pipe( pipe_slow );
10797 %}
10798 
10799 // Convert a double to an int.  If the double is a NAN, stuff a zero in instead.
10800 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10801   predicate(UseSSE>=2);
10802   match(Set dst (ConvD2I src));
10803   effect( KILL tmp, KILL cr );
10804   format %{ "CVTTSD2SI $dst, $src\n\t"
10805             "CMP    $dst,0x80000000\n\t"
10806             "JNE,s  fast\n\t"
10807             "SUB    ESP, 8\n\t"
10808             "MOVSD  [ESP], $src\n\t"
10809             "FLD_D  [ESP]\n\t"
10810             "ADD    ESP, 8\n\t"
10811             "CALL   d2i_wrapper\n"
10812       "fast:" %}
10813   ins_encode %{
10814     Label fast;
10815     __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10816     __ cmpl($dst$$Register, 0x80000000);
10817     __ jccb(Assembler::notEqual, fast);
10818     __ subptr(rsp, 8);
10819     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10820     __ fld_d(Address(rsp, 0));
10821     __ addptr(rsp, 8);
10822     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10823     __ bind(fast);
10824   %}
10825   ins_pipe( pipe_slow );
10826 %}
10827 
10828 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10829   predicate(UseSSE<=1);
10830   match(Set dst (ConvD2L src));
10831   effect( KILL cr );
10832   format %{ "FLD    $src\t# Convert double to long\n\t"
10833             "FLDCW  trunc mode\n\t"
10834             "SUB    ESP,8\n\t"
10835             "FISTp  [ESP + #0]\n\t"
10836             "FLDCW  std/24-bit mode\n\t"
10837             "POP    EAX\n\t"
10838             "POP    EDX\n\t"
10839             "CMP    EDX,0x80000000\n\t"
10840             "JNE,s  fast\n\t"
10841             "TEST   EAX,EAX\n\t"
10842             "JNE,s  fast\n\t"
10843             "FLD    $src\n\t"
10844             "CALL   d2l_wrapper\n"
10845       "fast:" %}
10846   ins_encode( Push_Reg_DPR(src),  DPR2L_encoding(src) );
10847   ins_pipe( pipe_slow );
10848 %}
10849 
10850 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10851 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10852   predicate (UseSSE>=2);
10853   match(Set dst (ConvD2L src));
10854   effect( KILL cr );
10855   format %{ "SUB    ESP,8\t# Convert double to long\n\t"
10856             "MOVSD  [ESP],$src\n\t"
10857             "FLD_D  [ESP]\n\t"
10858             "FLDCW  trunc mode\n\t"
10859             "FISTp  [ESP + #0]\n\t"
10860             "FLDCW  std/24-bit mode\n\t"
10861             "POP    EAX\n\t"
10862             "POP    EDX\n\t"
10863             "CMP    EDX,0x80000000\n\t"
10864             "JNE,s  fast\n\t"
10865             "TEST   EAX,EAX\n\t"
10866             "JNE,s  fast\n\t"
10867             "SUB    ESP,8\n\t"
10868             "MOVSD  [ESP],$src\n\t"
10869             "FLD_D  [ESP]\n\t"
10870             "ADD    ESP,8\n\t"
10871             "CALL   d2l_wrapper\n"
10872       "fast:" %}
10873   ins_encode %{
10874     Label fast;
10875     __ subptr(rsp, 8);
10876     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10877     __ fld_d(Address(rsp, 0));
10878     __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10879     __ fistp_d(Address(rsp, 0));
10880     // Restore the rounding mode, mask the exception
10881     if (Compile::current()->in_24_bit_fp_mode()) {
10882       __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10883     } else {
10884       __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10885     }
10886     // Load the converted long, adjust CPU stack
10887     __ pop(rax);
10888     __ pop(rdx);
10889     __ cmpl(rdx, 0x80000000);
10890     __ jccb(Assembler::notEqual, fast);
10891     __ testl(rax, rax);
10892     __ jccb(Assembler::notEqual, fast);
10893     __ subptr(rsp, 8);
10894     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10895     __ fld_d(Address(rsp, 0));
10896     __ addptr(rsp, 8);
10897     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10898     __ bind(fast);
10899   %}
10900   ins_pipe( pipe_slow );
10901 %}
10902 
10903 // Convert a double to an int.  Java semantics require we do complex
10904 // manglations in the corner cases.  So we set the rounding mode to
10905 // 'zero', store the darned double down as an int, and reset the
10906 // rounding mode to 'nearest'.  The hardware stores a flag value down
10907 // if we would overflow or converted a NAN; we check for this and
10908 // and go the slow path if needed.
10909 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
10910   predicate(UseSSE==0);
10911   match(Set dst (ConvF2I src));
10912   effect( KILL tmp, KILL cr );
10913   format %{ "FLD    $src\t# Convert float to int \n\t"
10914             "FLDCW  trunc mode\n\t"
10915             "SUB    ESP,4\n\t"
10916             "FISTp  [ESP + #0]\n\t"
10917             "FLDCW  std/24-bit mode\n\t"
10918             "POP    EAX\n\t"
10919             "CMP    EAX,0x80000000\n\t"
10920             "JNE,s  fast\n\t"
10921             "FLD    $src\n\t"
10922             "CALL   d2i_wrapper\n"
10923       "fast:" %}
10924   // DPR2I_encoding works for FPR2I
10925   ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
10926   ins_pipe( pipe_slow );
10927 %}
10928 
10929 // Convert a float in xmm to an int reg.
10930 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
10931   predicate(UseSSE>=1);
10932   match(Set dst (ConvF2I src));
10933   effect( KILL tmp, KILL cr );
10934   format %{ "CVTTSS2SI $dst, $src\n\t"
10935             "CMP    $dst,0x80000000\n\t"
10936             "JNE,s  fast\n\t"
10937             "SUB    ESP, 4\n\t"
10938             "MOVSS  [ESP], $src\n\t"
10939             "FLD    [ESP]\n\t"
10940             "ADD    ESP, 4\n\t"
10941             "CALL   d2i_wrapper\n"
10942       "fast:" %}
10943   ins_encode %{
10944     Label fast;
10945     __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10946     __ cmpl($dst$$Register, 0x80000000);
10947     __ jccb(Assembler::notEqual, fast);
10948     __ subptr(rsp, 4);
10949     __ movflt(Address(rsp, 0), $src$$XMMRegister);
10950     __ fld_s(Address(rsp, 0));
10951     __ addptr(rsp, 4);
10952     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10953     __ bind(fast);
10954   %}
10955   ins_pipe( pipe_slow );
10956 %}
10957 
10958 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
10959   predicate(UseSSE==0);
10960   match(Set dst (ConvF2L src));
10961   effect( KILL cr );
10962   format %{ "FLD    $src\t# Convert float to long\n\t"
10963             "FLDCW  trunc mode\n\t"
10964             "SUB    ESP,8\n\t"
10965             "FISTp  [ESP + #0]\n\t"
10966             "FLDCW  std/24-bit mode\n\t"
10967             "POP    EAX\n\t"
10968             "POP    EDX\n\t"
10969             "CMP    EDX,0x80000000\n\t"
10970             "JNE,s  fast\n\t"
10971             "TEST   EAX,EAX\n\t"
10972             "JNE,s  fast\n\t"
10973             "FLD    $src\n\t"
10974             "CALL   d2l_wrapper\n"
10975       "fast:" %}
10976   // DPR2L_encoding works for FPR2L
10977   ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
10978   ins_pipe( pipe_slow );
10979 %}
10980 
10981 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10982 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
10983   predicate (UseSSE>=1);
10984   match(Set dst (ConvF2L src));
10985   effect( KILL cr );
10986   format %{ "SUB    ESP,8\t# Convert float to long\n\t"
10987             "MOVSS  [ESP],$src\n\t"
10988             "FLD_S  [ESP]\n\t"
10989             "FLDCW  trunc mode\n\t"
10990             "FISTp  [ESP + #0]\n\t"
10991             "FLDCW  std/24-bit mode\n\t"
10992             "POP    EAX\n\t"
10993             "POP    EDX\n\t"
10994             "CMP    EDX,0x80000000\n\t"
10995             "JNE,s  fast\n\t"
10996             "TEST   EAX,EAX\n\t"
10997             "JNE,s  fast\n\t"
10998             "SUB    ESP,4\t# Convert float to long\n\t"
10999             "MOVSS  [ESP],$src\n\t"
11000             "FLD_S  [ESP]\n\t"
11001             "ADD    ESP,4\n\t"
11002             "CALL   d2l_wrapper\n"
11003       "fast:" %}
11004   ins_encode %{
11005     Label fast;
11006     __ subptr(rsp, 8);
11007     __ movflt(Address(rsp, 0), $src$$XMMRegister);
11008     __ fld_s(Address(rsp, 0));
11009     __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11010     __ fistp_d(Address(rsp, 0));
11011     // Restore the rounding mode, mask the exception
11012     if (Compile::current()->in_24_bit_fp_mode()) {
11013       __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11014     } else {
11015       __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11016     }
11017     // Load the converted long, adjust CPU stack
11018     __ pop(rax);
11019     __ pop(rdx);
11020     __ cmpl(rdx, 0x80000000);
11021     __ jccb(Assembler::notEqual, fast);
11022     __ testl(rax, rax);
11023     __ jccb(Assembler::notEqual, fast);
11024     __ subptr(rsp, 4);
11025     __ movflt(Address(rsp, 0), $src$$XMMRegister);
11026     __ fld_s(Address(rsp, 0));
11027     __ addptr(rsp, 4);
11028     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11029     __ bind(fast);
11030   %}
11031   ins_pipe( pipe_slow );
11032 %}
11033 
11034 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11035   predicate( UseSSE<=1 );
11036   match(Set dst (ConvI2D src));
11037   format %{ "FILD   $src\n\t"
11038             "FSTP   $dst" %}
11039   opcode(0xDB, 0x0);  /* DB /0 */
11040   ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11041   ins_pipe( fpu_reg_mem );
11042 %}
11043 
11044 instruct convI2D_reg(regD dst, rRegI src) %{
11045   predicate( UseSSE>=2 && !UseXmmI2D );
11046   match(Set dst (ConvI2D src));
11047   format %{ "CVTSI2SD $dst,$src" %}
11048   ins_encode %{
11049     __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11050   %}
11051   ins_pipe( pipe_slow );
11052 %}
11053 
11054 instruct convI2D_mem(regD dst, memory mem) %{
11055   predicate( UseSSE>=2 );
11056   match(Set dst (ConvI2D (LoadI mem)));
11057   format %{ "CVTSI2SD $dst,$mem" %}
11058   ins_encode %{
11059     __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11060   %}
11061   ins_pipe( pipe_slow );
11062 %}
11063 
11064 instruct convXI2D_reg(regD dst, rRegI src)
11065 %{
11066   predicate( UseSSE>=2 && UseXmmI2D );
11067   match(Set dst (ConvI2D src));
11068 
11069   format %{ "MOVD  $dst,$src\n\t"
11070             "CVTDQ2PD $dst,$dst\t# i2d" %}
11071   ins_encode %{
11072     __ movdl($dst$$XMMRegister, $src$$Register);
11073     __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11074   %}
11075   ins_pipe(pipe_slow); // XXX
11076 %}
11077 
11078 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11079   predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11080   match(Set dst (ConvI2D (LoadI mem)));
11081   format %{ "FILD   $mem\n\t"
11082             "FSTP   $dst" %}
11083   opcode(0xDB);      /* DB /0 */
11084   ins_encode( OpcP, RMopc_Mem(0x00,mem),
11085               Pop_Reg_DPR(dst));
11086   ins_pipe( fpu_reg_mem );
11087 %}
11088 
11089 // Convert a byte to a float; no rounding step needed.
11090 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11091   predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11092   match(Set dst (ConvI2F src));
11093   format %{ "FILD   $src\n\t"
11094             "FSTP   $dst" %}
11095 
11096   opcode(0xDB, 0x0);  /* DB /0 */
11097   ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11098   ins_pipe( fpu_reg_mem );
11099 %}
11100 
11101 // In 24-bit mode, force exponent rounding by storing back out
11102 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11103   predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11104   match(Set dst (ConvI2F src));
11105   ins_cost(200);
11106   format %{ "FILD   $src\n\t"
11107             "FSTP_S $dst" %}
11108   opcode(0xDB, 0x0);  /* DB /0 */
11109   ins_encode( Push_Mem_I(src),
11110               Pop_Mem_FPR(dst));
11111   ins_pipe( fpu_mem_mem );
11112 %}
11113 
11114 // In 24-bit mode, force exponent rounding by storing back out
11115 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11116   predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11117   match(Set dst (ConvI2F (LoadI mem)));
11118   ins_cost(200);
11119   format %{ "FILD   $mem\n\t"
11120             "FSTP_S $dst" %}
11121   opcode(0xDB);  /* DB /0 */
11122   ins_encode( OpcP, RMopc_Mem(0x00,mem),
11123               Pop_Mem_FPR(dst));
11124   ins_pipe( fpu_mem_mem );
11125 %}
11126 
11127 // This instruction does not round to 24-bits
11128 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11129   predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11130   match(Set dst (ConvI2F src));
11131   format %{ "FILD   $src\n\t"
11132             "FSTP   $dst" %}
11133   opcode(0xDB, 0x0);  /* DB /0 */
11134   ins_encode( Push_Mem_I(src),
11135               Pop_Reg_FPR(dst));
11136   ins_pipe( fpu_reg_mem );
11137 %}
11138 
11139 // This instruction does not round to 24-bits
11140 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11141   predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11142   match(Set dst (ConvI2F (LoadI mem)));
11143   format %{ "FILD   $mem\n\t"
11144             "FSTP   $dst" %}
11145   opcode(0xDB);      /* DB /0 */
11146   ins_encode( OpcP, RMopc_Mem(0x00,mem),
11147               Pop_Reg_FPR(dst));
11148   ins_pipe( fpu_reg_mem );
11149 %}
11150 
11151 // Convert an int to a float in xmm; no rounding step needed.
11152 instruct convI2F_reg(regF dst, rRegI src) %{
11153   predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11154   match(Set dst (ConvI2F src));
11155   format %{ "CVTSI2SS $dst, $src" %}
11156   ins_encode %{
11157     __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11158   %}
11159   ins_pipe( pipe_slow );
11160 %}
11161 
11162  instruct convXI2F_reg(regF dst, rRegI src)
11163 %{
11164   predicate( UseSSE>=2 && UseXmmI2F );
11165   match(Set dst (ConvI2F src));
11166 
11167   format %{ "MOVD  $dst,$src\n\t"
11168             "CVTDQ2PS $dst,$dst\t# i2f" %}
11169   ins_encode %{
11170     __ movdl($dst$$XMMRegister, $src$$Register);
11171     __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11172   %}
11173   ins_pipe(pipe_slow); // XXX
11174 %}
11175 
11176 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11177   match(Set dst (ConvI2L src));
11178   effect(KILL cr);
11179   ins_cost(375);
11180   format %{ "MOV    $dst.lo,$src\n\t"
11181             "MOV    $dst.hi,$src\n\t"
11182             "SAR    $dst.hi,31" %}
11183   ins_encode(convert_int_long(dst,src));
11184   ins_pipe( ialu_reg_reg_long );
11185 %}
11186 
11187 // Zero-extend convert int to long
11188 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11189   match(Set dst (AndL (ConvI2L src) mask) );
11190   effect( KILL flags );
11191   ins_cost(250);
11192   format %{ "MOV    $dst.lo,$src\n\t"
11193             "XOR    $dst.hi,$dst.hi" %}
11194   opcode(0x33); // XOR
11195   ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11196   ins_pipe( ialu_reg_reg_long );
11197 %}
11198 
11199 // Zero-extend long
11200 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11201   match(Set dst (AndL src mask) );
11202   effect( KILL flags );
11203   ins_cost(250);
11204   format %{ "MOV    $dst.lo,$src.lo\n\t"
11205             "XOR    $dst.hi,$dst.hi\n\t" %}
11206   opcode(0x33); // XOR
11207   ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11208   ins_pipe( ialu_reg_reg_long );
11209 %}
11210 
11211 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11212   predicate (UseSSE<=1);
11213   match(Set dst (ConvL2D src));
11214   effect( KILL cr );
11215   format %{ "PUSH   $src.hi\t# Convert long to double\n\t"
11216             "PUSH   $src.lo\n\t"
11217             "FILD   ST,[ESP + #0]\n\t"
11218             "ADD    ESP,8\n\t"
11219             "FSTP_D $dst\t# D-round" %}
11220   opcode(0xDF, 0x5);  /* DF /5 */
11221   ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11222   ins_pipe( pipe_slow );
11223 %}
11224 
11225 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11226   predicate (UseSSE>=2);
11227   match(Set dst (ConvL2D src));
11228   effect( KILL cr );
11229   format %{ "PUSH   $src.hi\t# Convert long to double\n\t"
11230             "PUSH   $src.lo\n\t"
11231             "FILD_D [ESP]\n\t"
11232             "FSTP_D [ESP]\n\t"
11233             "MOVSD  $dst,[ESP]\n\t"
11234             "ADD    ESP,8" %}
11235   opcode(0xDF, 0x5);  /* DF /5 */
11236   ins_encode(convert_long_double2(src), Push_ResultD(dst));
11237   ins_pipe( pipe_slow );
11238 %}
11239 
11240 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11241   predicate (UseSSE>=1);
11242   match(Set dst (ConvL2F src));
11243   effect( KILL cr );
11244   format %{ "PUSH   $src.hi\t# Convert long to single float\n\t"
11245             "PUSH   $src.lo\n\t"
11246             "FILD_D [ESP]\n\t"
11247             "FSTP_S [ESP]\n\t"
11248             "MOVSS  $dst,[ESP]\n\t"
11249             "ADD    ESP,8" %}
11250   opcode(0xDF, 0x5);  /* DF /5 */
11251   ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11252   ins_pipe( pipe_slow );
11253 %}
11254 
11255 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11256   match(Set dst (ConvL2F src));
11257   effect( KILL cr );
11258   format %{ "PUSH   $src.hi\t# Convert long to single float\n\t"
11259             "PUSH   $src.lo\n\t"
11260             "FILD   ST,[ESP + #0]\n\t"
11261             "ADD    ESP,8\n\t"
11262             "FSTP_S $dst\t# F-round" %}
11263   opcode(0xDF, 0x5);  /* DF /5 */
11264   ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11265   ins_pipe( pipe_slow );
11266 %}
11267 
11268 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11269   match(Set dst (ConvL2I src));
11270   effect( DEF dst, USE src );
11271   format %{ "MOV    $dst,$src.lo" %}
11272   ins_encode(enc_CopyL_Lo(dst,src));
11273   ins_pipe( ialu_reg_reg );
11274 %}
11275 
11276 
11277 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11278   match(Set dst (MoveF2I src));
11279   effect( DEF dst, USE src );
11280   ins_cost(100);
11281   format %{ "MOV    $dst,$src\t# MoveF2I_stack_reg" %}
11282   ins_encode %{
11283     __ movl($dst$$Register, Address(rsp, $src$$disp));
11284   %}
11285   ins_pipe( ialu_reg_mem );
11286 %}
11287 
11288 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11289   predicate(UseSSE==0);
11290   match(Set dst (MoveF2I src));
11291   effect( DEF dst, USE src );
11292 
11293   ins_cost(125);
11294   format %{ "FST_S  $dst,$src\t# MoveF2I_reg_stack" %}
11295   ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11296   ins_pipe( fpu_mem_reg );
11297 %}
11298 
11299 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11300   predicate(UseSSE>=1);
11301   match(Set dst (MoveF2I src));
11302   effect( DEF dst, USE src );
11303 
11304   ins_cost(95);
11305   format %{ "MOVSS  $dst,$src\t# MoveF2I_reg_stack_sse" %}
11306   ins_encode %{
11307     __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11308   %}
11309   ins_pipe( pipe_slow );
11310 %}
11311 
11312 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11313   predicate(UseSSE>=2);
11314   match(Set dst (MoveF2I src));
11315   effect( DEF dst, USE src );
11316   ins_cost(85);
11317   format %{ "MOVD   $dst,$src\t# MoveF2I_reg_reg_sse" %}
11318   ins_encode %{
11319     __ movdl($dst$$Register, $src$$XMMRegister);
11320   %}
11321   ins_pipe( pipe_slow );
11322 %}
11323 
11324 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11325   match(Set dst (MoveI2F src));
11326   effect( DEF dst, USE src );
11327 
11328   ins_cost(100);
11329   format %{ "MOV    $dst,$src\t# MoveI2F_reg_stack" %}
11330   ins_encode %{
11331     __ movl(Address(rsp, $dst$$disp), $src$$Register);
11332   %}
11333   ins_pipe( ialu_mem_reg );
11334 %}
11335 
11336 
11337 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11338   predicate(UseSSE==0);
11339   match(Set dst (MoveI2F src));
11340   effect(DEF dst, USE src);
11341 
11342   ins_cost(125);
11343   format %{ "FLD_S  $src\n\t"
11344             "FSTP   $dst\t# MoveI2F_stack_reg" %}
11345   opcode(0xD9);               /* D9 /0, FLD m32real */
11346   ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11347               Pop_Reg_FPR(dst) );
11348   ins_pipe( fpu_reg_mem );
11349 %}
11350 
11351 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11352   predicate(UseSSE>=1);
11353   match(Set dst (MoveI2F src));
11354   effect( DEF dst, USE src );
11355 
11356   ins_cost(95);
11357   format %{ "MOVSS  $dst,$src\t# MoveI2F_stack_reg_sse" %}
11358   ins_encode %{
11359     __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11360   %}
11361   ins_pipe( pipe_slow );
11362 %}
11363 
11364 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11365   predicate(UseSSE>=2);
11366   match(Set dst (MoveI2F src));
11367   effect( DEF dst, USE src );
11368 
11369   ins_cost(85);
11370   format %{ "MOVD   $dst,$src\t# MoveI2F_reg_reg_sse" %}
11371   ins_encode %{
11372     __ movdl($dst$$XMMRegister, $src$$Register);
11373   %}
11374   ins_pipe( pipe_slow );
11375 %}
11376 
11377 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11378   match(Set dst (MoveD2L src));
11379   effect(DEF dst, USE src);
11380 
11381   ins_cost(250);
11382   format %{ "MOV    $dst.lo,$src\n\t"
11383             "MOV    $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11384   opcode(0x8B, 0x8B);
11385   ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11386   ins_pipe( ialu_mem_long_reg );
11387 %}
11388 
11389 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11390   predicate(UseSSE<=1);
11391   match(Set dst (MoveD2L src));
11392   effect(DEF dst, USE src);
11393 
11394   ins_cost(125);
11395   format %{ "FST_D  $dst,$src\t# MoveD2L_reg_stack" %}
11396   ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11397   ins_pipe( fpu_mem_reg );
11398 %}
11399 
11400 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11401   predicate(UseSSE>=2);
11402   match(Set dst (MoveD2L src));
11403   effect(DEF dst, USE src);
11404   ins_cost(95);
11405   format %{ "MOVSD  $dst,$src\t# MoveD2L_reg_stack_sse" %}
11406   ins_encode %{
11407     __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11408   %}
11409   ins_pipe( pipe_slow );
11410 %}
11411 
11412 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11413   predicate(UseSSE>=2);
11414   match(Set dst (MoveD2L src));
11415   effect(DEF dst, USE src, TEMP tmp);
11416   ins_cost(85);
11417   format %{ "MOVD   $dst.lo,$src\n\t"
11418             "PSHUFLW $tmp,$src,0x4E\n\t"
11419             "MOVD   $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11420   ins_encode %{
11421     __ movdl($dst$$Register, $src$$XMMRegister);
11422     __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11423     __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11424   %}
11425   ins_pipe( pipe_slow );
11426 %}
11427 
11428 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11429   match(Set dst (MoveL2D src));
11430   effect(DEF dst, USE src);
11431 
11432   ins_cost(200);
11433   format %{ "MOV    $dst,$src.lo\n\t"
11434             "MOV    $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11435   opcode(0x89, 0x89);
11436   ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11437   ins_pipe( ialu_mem_long_reg );
11438 %}
11439 
11440 
11441 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11442   predicate(UseSSE<=1);
11443   match(Set dst (MoveL2D src));
11444   effect(DEF dst, USE src);
11445   ins_cost(125);
11446 
11447   format %{ "FLD_D  $src\n\t"
11448             "FSTP   $dst\t# MoveL2D_stack_reg" %}
11449   opcode(0xDD);               /* DD /0, FLD m64real */
11450   ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11451               Pop_Reg_DPR(dst) );
11452   ins_pipe( fpu_reg_mem );
11453 %}
11454 
11455 
11456 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11457   predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11458   match(Set dst (MoveL2D src));
11459   effect(DEF dst, USE src);
11460 
11461   ins_cost(95);
11462   format %{ "MOVSD  $dst,$src\t# MoveL2D_stack_reg_sse" %}
11463   ins_encode %{
11464     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11465   %}
11466   ins_pipe( pipe_slow );
11467 %}
11468 
11469 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11470   predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11471   match(Set dst (MoveL2D src));
11472   effect(DEF dst, USE src);
11473 
11474   ins_cost(95);
11475   format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11476   ins_encode %{
11477     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11478   %}
11479   ins_pipe( pipe_slow );
11480 %}
11481 
11482 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11483   predicate(UseSSE>=2);
11484   match(Set dst (MoveL2D src));
11485   effect(TEMP dst, USE src, TEMP tmp);
11486   ins_cost(85);
11487   format %{ "MOVD   $dst,$src.lo\n\t"
11488             "MOVD   $tmp,$src.hi\n\t"
11489             "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11490   ins_encode %{
11491     __ movdl($dst$$XMMRegister, $src$$Register);
11492     __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11493     __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11494   %}
11495   ins_pipe( pipe_slow );
11496 %}
11497 
11498 
11499 // =======================================================================
11500 // fast clearing of an array
11501 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11502   predicate(!UseFastStosb);
11503   match(Set dummy (ClearArray cnt base));
11504   effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11505   format %{ "XOR    EAX,EAX\t# ClearArray:\n\t"
11506             "SHL    ECX,1\t# Convert doublewords to words\n\t"
11507             "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11508   ins_encode %{ 
11509     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11510   %}
11511   ins_pipe( pipe_slow );
11512 %}
11513 
11514 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11515   predicate(UseFastStosb);
11516   match(Set dummy (ClearArray cnt base));
11517   effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11518   format %{ "XOR    EAX,EAX\t# ClearArray:\n\t"
11519             "SHL    ECX,3\t# Convert doublewords to bytes\n\t"
11520             "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11521   ins_encode %{ 
11522     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11523   %}
11524   ins_pipe( pipe_slow );
11525 %}
11526 
11527 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11528                         eAXRegI result, regD tmp1, eFlagsReg cr) %{
11529   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11530   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11531 
11532   format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11533   ins_encode %{
11534     __ string_compare($str1$$Register, $str2$$Register,
11535                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11536                       $tmp1$$XMMRegister);
11537   %}
11538   ins_pipe( pipe_slow );
11539 %}
11540 
11541 // fast string equals
11542 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11543                        regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11544   match(Set result (StrEquals (Binary str1 str2) cnt));
11545   effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11546 
11547   format %{ "String Equals $str1,$str2,$cnt -> $result    // KILL $tmp1, $tmp2, $tmp3" %}
11548   ins_encode %{
11549     __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11550                           $cnt$$Register, $result$$Register, $tmp3$$Register,
11551                           $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11552   %}
11553   ins_pipe( pipe_slow );
11554 %}
11555 
11556 // fast search of substring with known size.
11557 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11558                             eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11559   predicate(UseSSE42Intrinsics);
11560   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11561   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11562 
11563   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $vec, $cnt1, $cnt2, $tmp" %}
11564   ins_encode %{
11565     int icnt2 = (int)$int_cnt2$$constant;
11566     if (icnt2 >= 8) {
11567       // IndexOf for constant substrings with size >= 8 elements
11568       // which don't need to be loaded through stack.
11569       __ string_indexofC8($str1$$Register, $str2$$Register,
11570                           $cnt1$$Register, $cnt2$$Register,
11571                           icnt2, $result$$Register,
11572                           $vec$$XMMRegister, $tmp$$Register);
11573     } else {
11574       // Small strings are loaded through stack if they cross page boundary.
11575       __ string_indexof($str1$$Register, $str2$$Register,
11576                         $cnt1$$Register, $cnt2$$Register,
11577                         icnt2, $result$$Register,
11578                         $vec$$XMMRegister, $tmp$$Register);
11579     }
11580   %}
11581   ins_pipe( pipe_slow );
11582 %}
11583 
11584 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11585                         eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11586   predicate(UseSSE42Intrinsics);
11587   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11588   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11589 
11590   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11591   ins_encode %{
11592     __ string_indexof($str1$$Register, $str2$$Register,
11593                       $cnt1$$Register, $cnt2$$Register,
11594                       (-1), $result$$Register,
11595                       $vec$$XMMRegister, $tmp$$Register);
11596   %}
11597   ins_pipe( pipe_slow );
11598 %}
11599 
11600 // fast array equals
11601 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11602                       regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11603 %{
11604   match(Set result (AryEq ary1 ary2));
11605   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11606   //ins_cost(300);
11607 
11608   format %{ "Array Equals $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11609   ins_encode %{
11610     __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11611                           $tmp3$$Register, $result$$Register, $tmp4$$Register,
11612                           $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11613   %}
11614   ins_pipe( pipe_slow );
11615 %}
11616 
11617 // encode char[] to byte[] in ISO_8859_1
11618 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11619                           regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11620                           eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11621   match(Set result (EncodeISOArray src (Binary dst len)));
11622   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11623 
11624   format %{ "Encode array $src,$dst,$len -> $result    // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11625   ins_encode %{
11626     __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11627                         $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11628                         $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11629   %}
11630   ins_pipe( pipe_slow );
11631 %}
11632 
11633 
11634 //----------Control Flow Instructions------------------------------------------
11635 // Signed compare Instructions
11636 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11637   match(Set cr (CmpI op1 op2));
11638   effect( DEF cr, USE op1, USE op2 );
11639   format %{ "CMP    $op1,$op2" %}
11640   opcode(0x3B);  /* Opcode 3B /r */
11641   ins_encode( OpcP, RegReg( op1, op2) );
11642   ins_pipe( ialu_cr_reg_reg );
11643 %}
11644 
11645 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11646   match(Set cr (CmpI op1 op2));
11647   effect( DEF cr, USE op1 );
11648   format %{ "CMP    $op1,$op2" %}
11649   opcode(0x81,0x07);  /* Opcode 81 /7 */
11650   // ins_encode( RegImm( op1, op2) );  /* Was CmpImm */
11651   ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11652   ins_pipe( ialu_cr_reg_imm );
11653 %}
11654 
11655 // Cisc-spilled version of cmpI_eReg
11656 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11657   match(Set cr (CmpI op1 (LoadI op2)));
11658 
11659   format %{ "CMP    $op1,$op2" %}
11660   ins_cost(500);
11661   opcode(0x3B);  /* Opcode 3B /r */
11662   ins_encode( OpcP, RegMem( op1, op2) );
11663   ins_pipe( ialu_cr_reg_mem );
11664 %}
11665 
11666 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11667   match(Set cr (CmpI src zero));
11668   effect( DEF cr, USE src );
11669 
11670   format %{ "TEST   $src,$src" %}
11671   opcode(0x85);
11672   ins_encode( OpcP, RegReg( src, src ) );
11673   ins_pipe( ialu_cr_reg_imm );
11674 %}
11675 
11676 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11677   match(Set cr (CmpI (AndI src con) zero));
11678 
11679   format %{ "TEST   $src,$con" %}
11680   opcode(0xF7,0x00);
11681   ins_encode( OpcP, RegOpc(src), Con32(con) );
11682   ins_pipe( ialu_cr_reg_imm );
11683 %}
11684 
11685 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11686   match(Set cr (CmpI (AndI src mem) zero));
11687 
11688   format %{ "TEST   $src,$mem" %}
11689   opcode(0x85);
11690   ins_encode( OpcP, RegMem( src, mem ) );
11691   ins_pipe( ialu_cr_reg_mem );
11692 %}
11693 
11694 // Unsigned compare Instructions; really, same as signed except they
11695 // produce an eFlagsRegU instead of eFlagsReg.
11696 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11697   match(Set cr (CmpU op1 op2));
11698 
11699   format %{ "CMPu   $op1,$op2" %}
11700   opcode(0x3B);  /* Opcode 3B /r */
11701   ins_encode( OpcP, RegReg( op1, op2) );
11702   ins_pipe( ialu_cr_reg_reg );
11703 %}
11704 
11705 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11706   match(Set cr (CmpU op1 op2));
11707 
11708   format %{ "CMPu   $op1,$op2" %}
11709   opcode(0x81,0x07);  /* Opcode 81 /7 */
11710   ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11711   ins_pipe( ialu_cr_reg_imm );
11712 %}
11713 
11714 // // Cisc-spilled version of cmpU_eReg
11715 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11716   match(Set cr (CmpU op1 (LoadI op2)));
11717 
11718   format %{ "CMPu   $op1,$op2" %}
11719   ins_cost(500);
11720   opcode(0x3B);  /* Opcode 3B /r */
11721   ins_encode( OpcP, RegMem( op1, op2) );
11722   ins_pipe( ialu_cr_reg_mem );
11723 %}
11724 
11725 // // Cisc-spilled version of cmpU_eReg
11726 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11727 //  match(Set cr (CmpU (LoadI op1) op2));
11728 //
11729 //  format %{ "CMPu   $op1,$op2" %}
11730 //  ins_cost(500);
11731 //  opcode(0x39);  /* Opcode 39 /r */
11732 //  ins_encode( OpcP, RegMem( op1, op2) );
11733 //%}
11734 
11735 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11736   match(Set cr (CmpU src zero));
11737 
11738   format %{ "TESTu  $src,$src" %}
11739   opcode(0x85);
11740   ins_encode( OpcP, RegReg( src, src ) );
11741   ins_pipe( ialu_cr_reg_imm );
11742 %}
11743 
11744 // Unsigned pointer compare Instructions
11745 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11746   match(Set cr (CmpP op1 op2));
11747 
11748   format %{ "CMPu   $op1,$op2" %}
11749   opcode(0x3B);  /* Opcode 3B /r */
11750   ins_encode( OpcP, RegReg( op1, op2) );
11751   ins_pipe( ialu_cr_reg_reg );
11752 %}
11753 
11754 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11755   match(Set cr (CmpP op1 op2));
11756 
11757   format %{ "CMPu   $op1,$op2" %}
11758   opcode(0x81,0x07);  /* Opcode 81 /7 */
11759   ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11760   ins_pipe( ialu_cr_reg_imm );
11761 %}
11762 
11763 // // Cisc-spilled version of cmpP_eReg
11764 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11765   match(Set cr (CmpP op1 (LoadP op2)));
11766 
11767   format %{ "CMPu   $op1,$op2" %}
11768   ins_cost(500);
11769   opcode(0x3B);  /* Opcode 3B /r */
11770   ins_encode( OpcP, RegMem( op1, op2) );
11771   ins_pipe( ialu_cr_reg_mem );
11772 %}
11773 
11774 // // Cisc-spilled version of cmpP_eReg
11775 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11776 //  match(Set cr (CmpP (LoadP op1) op2));
11777 //
11778 //  format %{ "CMPu   $op1,$op2" %}
11779 //  ins_cost(500);
11780 //  opcode(0x39);  /* Opcode 39 /r */
11781 //  ins_encode( OpcP, RegMem( op1, op2) );
11782 //%}
11783 
11784 // Compare raw pointer (used in out-of-heap check).
11785 // Only works because non-oop pointers must be raw pointers
11786 // and raw pointers have no anti-dependencies.
11787 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11788   predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
11789   match(Set cr (CmpP op1 (LoadP op2)));
11790 
11791   format %{ "CMPu   $op1,$op2" %}
11792   opcode(0x3B);  /* Opcode 3B /r */
11793   ins_encode( OpcP, RegMem( op1, op2) );
11794   ins_pipe( ialu_cr_reg_mem );
11795 %}
11796 
11797 //
11798 // This will generate a signed flags result. This should be ok
11799 // since any compare to a zero should be eq/neq.
11800 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11801   match(Set cr (CmpP src zero));
11802 
11803   format %{ "TEST   $src,$src" %}
11804   opcode(0x85);
11805   ins_encode( OpcP, RegReg( src, src ) );
11806   ins_pipe( ialu_cr_reg_imm );
11807 %}
11808 
11809 // Cisc-spilled version of testP_reg
11810 // This will generate a signed flags result. This should be ok
11811 // since any compare to a zero should be eq/neq.
11812 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11813   match(Set cr (CmpP (LoadP op) zero));
11814 
11815   format %{ "TEST   $op,0xFFFFFFFF" %}
11816   ins_cost(500);
11817   opcode(0xF7);               /* Opcode F7 /0 */
11818   ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11819   ins_pipe( ialu_cr_reg_imm );
11820 %}
11821 
11822 // Yanked all unsigned pointer compare operations.
11823 // Pointer compares are done with CmpP which is already unsigned.
11824 
11825 //----------Max and Min--------------------------------------------------------
11826 // Min Instructions
11827 ////
11828 //   *** Min and Max using the conditional move are slower than the
11829 //   *** branch version on a Pentium III.
11830 // // Conditional move for min
11831 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11832 //  effect( USE_DEF op2, USE op1, USE cr );
11833 //  format %{ "CMOVlt $op2,$op1\t! min" %}
11834 //  opcode(0x4C,0x0F);
11835 //  ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11836 //  ins_pipe( pipe_cmov_reg );
11837 //%}
11838 //
11839 //// Min Register with Register (P6 version)
11840 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11841 //  predicate(VM_Version::supports_cmov() );
11842 //  match(Set op2 (MinI op1 op2));
11843 //  ins_cost(200);
11844 //  expand %{
11845 //    eFlagsReg cr;
11846 //    compI_eReg(cr,op1,op2);
11847 //    cmovI_reg_lt(op2,op1,cr);
11848 //  %}
11849 //%}
11850 
11851 // Min Register with Register (generic version)
11852 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11853   match(Set dst (MinI dst src));
11854   effect(KILL flags);
11855   ins_cost(300);
11856 
11857   format %{ "MIN    $dst,$src" %}
11858   opcode(0xCC);
11859   ins_encode( min_enc(dst,src) );
11860   ins_pipe( pipe_slow );
11861 %}
11862 
11863 // Max Register with Register
11864 //   *** Min and Max using the conditional move are slower than the
11865 //   *** branch version on a Pentium III.
11866 // // Conditional move for max
11867 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11868 //  effect( USE_DEF op2, USE op1, USE cr );
11869 //  format %{ "CMOVgt $op2,$op1\t! max" %}
11870 //  opcode(0x4F,0x0F);
11871 //  ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11872 //  ins_pipe( pipe_cmov_reg );
11873 //%}
11874 //
11875 // // Max Register with Register (P6 version)
11876 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11877 //  predicate(VM_Version::supports_cmov() );
11878 //  match(Set op2 (MaxI op1 op2));
11879 //  ins_cost(200);
11880 //  expand %{
11881 //    eFlagsReg cr;
11882 //    compI_eReg(cr,op1,op2);
11883 //    cmovI_reg_gt(op2,op1,cr);
11884 //  %}
11885 //%}
11886 
11887 // Max Register with Register (generic version)
11888 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11889   match(Set dst (MaxI dst src));
11890   effect(KILL flags);
11891   ins_cost(300);
11892 
11893   format %{ "MAX    $dst,$src" %}
11894   opcode(0xCC);
11895   ins_encode( max_enc(dst,src) );
11896   ins_pipe( pipe_slow );
11897 %}
11898 
11899 // ============================================================================
11900 // Counted Loop limit node which represents exact final iterator value.
11901 // Note: the resulting value should fit into integer range since
11902 // counted loops have limit check on overflow.
11903 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
11904   match(Set limit (LoopLimit (Binary init limit) stride));
11905   effect(TEMP limit_hi, TEMP tmp, KILL flags);
11906   ins_cost(300);
11907 
11908   format %{ "loopLimit $init,$limit,$stride  # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
11909   ins_encode %{
11910     int strd = (int)$stride$$constant;
11911     assert(strd != 1 && strd != -1, "sanity");
11912     int m1 = (strd > 0) ? 1 : -1;
11913     // Convert limit to long (EAX:EDX)
11914     __ cdql();
11915     // Convert init to long (init:tmp)
11916     __ movl($tmp$$Register, $init$$Register);
11917     __ sarl($tmp$$Register, 31);
11918     // $limit - $init
11919     __ subl($limit$$Register, $init$$Register);
11920     __ sbbl($limit_hi$$Register, $tmp$$Register);
11921     // + ($stride - 1)
11922     if (strd > 0) {
11923       __ addl($limit$$Register, (strd - 1));
11924       __ adcl($limit_hi$$Register, 0);
11925       __ movl($tmp$$Register, strd);
11926     } else {
11927       __ addl($limit$$Register, (strd + 1));
11928       __ adcl($limit_hi$$Register, -1);
11929       __ lneg($limit_hi$$Register, $limit$$Register);
11930       __ movl($tmp$$Register, -strd);
11931     }
11932     // signed devision: (EAX:EDX) / pos_stride
11933     __ idivl($tmp$$Register);
11934     if (strd < 0) {
11935       // restore sign
11936       __ negl($tmp$$Register);
11937     }
11938     // (EAX) * stride
11939     __ mull($tmp$$Register);
11940     // + init (ignore upper bits)
11941     __ addl($limit$$Register, $init$$Register);
11942   %}
11943   ins_pipe( pipe_slow );
11944 %}
11945 
11946 // ============================================================================
11947 // Branch Instructions
11948 // Jump Table
11949 instruct jumpXtnd(rRegI switch_val) %{
11950   match(Jump switch_val);
11951   ins_cost(350);
11952   format %{  "JMP    [$constantaddress](,$switch_val,1)\n\t" %}
11953   ins_encode %{
11954     // Jump to Address(table_base + switch_reg)
11955     Address index(noreg, $switch_val$$Register, Address::times_1);
11956     __ jump(ArrayAddress($constantaddress, index));
11957   %}
11958   ins_pipe(pipe_jmp);
11959 %}
11960 
11961 // Jump Direct - Label defines a relative address from JMP+1
11962 instruct jmpDir(label labl) %{
11963   match(Goto);
11964   effect(USE labl);
11965 
11966   ins_cost(300);
11967   format %{ "JMP    $labl" %}
11968   size(5);
11969   ins_encode %{
11970     Label* L = $labl$$label;
11971     __ jmp(*L, false); // Always long jump
11972   %}
11973   ins_pipe( pipe_jmp );
11974 %}
11975 
11976 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11977 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
11978   match(If cop cr);
11979   effect(USE labl);
11980 
11981   ins_cost(300);
11982   format %{ "J$cop    $labl" %}
11983   size(6);
11984   ins_encode %{
11985     Label* L = $labl$$label;
11986     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11987   %}
11988   ins_pipe( pipe_jcc );
11989 %}
11990 
11991 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11992 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
11993   match(CountedLoopEnd cop cr);
11994   effect(USE labl);
11995 
11996   ins_cost(300);
11997   format %{ "J$cop    $labl\t# Loop end" %}
11998   size(6);
11999   ins_encode %{
12000     Label* L = $labl$$label;
12001     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12002   %}
12003   ins_pipe( pipe_jcc );
12004 %}
12005 
12006 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12007 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12008   match(CountedLoopEnd cop cmp);
12009   effect(USE labl);
12010 
12011   ins_cost(300);
12012   format %{ "J$cop,u  $labl\t# Loop end" %}
12013   size(6);
12014   ins_encode %{
12015     Label* L = $labl$$label;
12016     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12017   %}
12018   ins_pipe( pipe_jcc );
12019 %}
12020 
12021 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12022   match(CountedLoopEnd cop cmp);
12023   effect(USE labl);
12024 
12025   ins_cost(200);
12026   format %{ "J$cop,u  $labl\t# Loop end" %}
12027   size(6);
12028   ins_encode %{
12029     Label* L = $labl$$label;
12030     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12031   %}
12032   ins_pipe( pipe_jcc );
12033 %}
12034 
12035 // Jump Direct Conditional - using unsigned comparison
12036 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12037   match(If cop cmp);
12038   effect(USE labl);
12039 
12040   ins_cost(300);
12041   format %{ "J$cop,u  $labl" %}
12042   size(6);
12043   ins_encode %{
12044     Label* L = $labl$$label;
12045     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12046   %}
12047   ins_pipe(pipe_jcc);
12048 %}
12049 
12050 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12051   match(If cop cmp);
12052   effect(USE labl);
12053 
12054   ins_cost(200);
12055   format %{ "J$cop,u  $labl" %}
12056   size(6);
12057   ins_encode %{
12058     Label* L = $labl$$label;
12059     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12060   %}
12061   ins_pipe(pipe_jcc);
12062 %}
12063 
12064 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12065   match(If cop cmp);
12066   effect(USE labl);
12067 
12068   ins_cost(200);
12069   format %{ $$template
12070     if ($cop$$cmpcode == Assembler::notEqual) {
12071       $$emit$$"JP,u   $labl\n\t"
12072       $$emit$$"J$cop,u   $labl"
12073     } else {
12074       $$emit$$"JP,u   done\n\t"
12075       $$emit$$"J$cop,u   $labl\n\t"
12076       $$emit$$"done:"
12077     }
12078   %}
12079   ins_encode %{
12080     Label* l = $labl$$label;
12081     if ($cop$$cmpcode == Assembler::notEqual) {
12082       __ jcc(Assembler::parity, *l, false);
12083       __ jcc(Assembler::notEqual, *l, false);
12084     } else if ($cop$$cmpcode == Assembler::equal) {
12085       Label done;
12086       __ jccb(Assembler::parity, done);
12087       __ jcc(Assembler::equal, *l, false);
12088       __ bind(done);
12089     } else {
12090        ShouldNotReachHere();
12091     }
12092   %}
12093   ins_pipe(pipe_jcc);
12094 %}
12095 
12096 // ============================================================================
12097 // The 2nd slow-half of a subtype check.  Scan the subklass's 2ndary superklass
12098 // array for an instance of the superklass.  Set a hidden internal cache on a
12099 // hit (cache is checked with exposed code in gen_subtype_check()).  Return
12100 // NZ for a miss or zero for a hit.  The encoding ALSO sets flags.
12101 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12102   match(Set result (PartialSubtypeCheck sub super));
12103   effect( KILL rcx, KILL cr );
12104 
12105   ins_cost(1100);  // slightly larger than the next version
12106   format %{ "MOV    EDI,[$sub+Klass::secondary_supers]\n\t"
12107             "MOV    ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12108             "ADD    EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12109             "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12110             "JNE,s  miss\t\t# Missed: EDI not-zero\n\t"
12111             "MOV    [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12112             "XOR    $result,$result\t\t Hit: EDI zero\n\t"
12113      "miss:\t" %}
12114 
12115   opcode(0x1); // Force a XOR of EDI
12116   ins_encode( enc_PartialSubtypeCheck() );
12117   ins_pipe( pipe_slow );
12118 %}
12119 
12120 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12121   match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12122   effect( KILL rcx, KILL result );
12123 
12124   ins_cost(1000);
12125   format %{ "MOV    EDI,[$sub+Klass::secondary_supers]\n\t"
12126             "MOV    ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12127             "ADD    EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12128             "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12129             "JNE,s  miss\t\t# Missed: flags NZ\n\t"
12130             "MOV    [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12131      "miss:\t" %}
12132 
12133   opcode(0x0);  // No need to XOR EDI
12134   ins_encode( enc_PartialSubtypeCheck() );
12135   ins_pipe( pipe_slow );
12136 %}
12137 
12138 // ============================================================================
12139 // Branch Instructions -- short offset versions
12140 //
12141 // These instructions are used to replace jumps of a long offset (the default
12142 // match) with jumps of a shorter offset.  These instructions are all tagged
12143 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12144 // match rules in general matching.  Instead, the ADLC generates a conversion
12145 // method in the MachNode which can be used to do in-place replacement of the
12146 // long variant with the shorter variant.  The compiler will determine if a
12147 // branch can be taken by the is_short_branch_offset() predicate in the machine
12148 // specific code section of the file.
12149 
12150 // Jump Direct - Label defines a relative address from JMP+1
12151 instruct jmpDir_short(label labl) %{
12152   match(Goto);
12153   effect(USE labl);
12154 
12155   ins_cost(300);
12156   format %{ "JMP,s  $labl" %}
12157   size(2);
12158   ins_encode %{
12159     Label* L = $labl$$label;
12160     __ jmpb(*L);
12161   %}
12162   ins_pipe( pipe_jmp );
12163   ins_short_branch(1);
12164 %}
12165 
12166 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12167 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12168   match(If cop cr);
12169   effect(USE labl);
12170 
12171   ins_cost(300);
12172   format %{ "J$cop,s  $labl" %}
12173   size(2);
12174   ins_encode %{
12175     Label* L = $labl$$label;
12176     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12177   %}
12178   ins_pipe( pipe_jcc );
12179   ins_short_branch(1);
12180 %}
12181 
12182 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12183 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12184   match(CountedLoopEnd cop cr);
12185   effect(USE labl);
12186 
12187   ins_cost(300);
12188   format %{ "J$cop,s  $labl\t# Loop end" %}
12189   size(2);
12190   ins_encode %{
12191     Label* L = $labl$$label;
12192     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12193   %}
12194   ins_pipe( pipe_jcc );
12195   ins_short_branch(1);
12196 %}
12197 
12198 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12199 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12200   match(CountedLoopEnd cop cmp);
12201   effect(USE labl);
12202 
12203   ins_cost(300);
12204   format %{ "J$cop,us $labl\t# Loop end" %}
12205   size(2);
12206   ins_encode %{
12207     Label* L = $labl$$label;
12208     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12209   %}
12210   ins_pipe( pipe_jcc );
12211   ins_short_branch(1);
12212 %}
12213 
12214 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12215   match(CountedLoopEnd cop cmp);
12216   effect(USE labl);
12217 
12218   ins_cost(300);
12219   format %{ "J$cop,us $labl\t# Loop end" %}
12220   size(2);
12221   ins_encode %{
12222     Label* L = $labl$$label;
12223     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12224   %}
12225   ins_pipe( pipe_jcc );
12226   ins_short_branch(1);
12227 %}
12228 
12229 // Jump Direct Conditional - using unsigned comparison
12230 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12231   match(If cop cmp);
12232   effect(USE labl);
12233 
12234   ins_cost(300);
12235   format %{ "J$cop,us $labl" %}
12236   size(2);
12237   ins_encode %{
12238     Label* L = $labl$$label;
12239     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12240   %}
12241   ins_pipe( pipe_jcc );
12242   ins_short_branch(1);
12243 %}
12244 
12245 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12246   match(If cop cmp);
12247   effect(USE labl);
12248 
12249   ins_cost(300);
12250   format %{ "J$cop,us $labl" %}
12251   size(2);
12252   ins_encode %{
12253     Label* L = $labl$$label;
12254     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12255   %}
12256   ins_pipe( pipe_jcc );
12257   ins_short_branch(1);
12258 %}
12259 
12260 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12261   match(If cop cmp);
12262   effect(USE labl);
12263 
12264   ins_cost(300);
12265   format %{ $$template
12266     if ($cop$$cmpcode == Assembler::notEqual) {
12267       $$emit$$"JP,u,s   $labl\n\t"
12268       $$emit$$"J$cop,u,s   $labl"
12269     } else {
12270       $$emit$$"JP,u,s   done\n\t"
12271       $$emit$$"J$cop,u,s  $labl\n\t"
12272       $$emit$$"done:"
12273     }
12274   %}
12275   size(4);
12276   ins_encode %{
12277     Label* l = $labl$$label;
12278     if ($cop$$cmpcode == Assembler::notEqual) {
12279       __ jccb(Assembler::parity, *l);
12280       __ jccb(Assembler::notEqual, *l);
12281     } else if ($cop$$cmpcode == Assembler::equal) {
12282       Label done;
12283       __ jccb(Assembler::parity, done);
12284       __ jccb(Assembler::equal, *l);
12285       __ bind(done);
12286     } else {
12287        ShouldNotReachHere();
12288     }
12289   %}
12290   ins_pipe(pipe_jcc);
12291   ins_short_branch(1);
12292 %}
12293 
12294 // ============================================================================
12295 // Long Compare
12296 //
12297 // Currently we hold longs in 2 registers.  Comparing such values efficiently
12298 // is tricky.  The flavor of compare used depends on whether we are testing
12299 // for LT, LE, or EQ.  For a simple LT test we can check just the sign bit.
12300 // The GE test is the negated LT test.  The LE test can be had by commuting
12301 // the operands (yielding a GE test) and then negating; negate again for the
12302 // GT test.  The EQ test is done by ORcc'ing the high and low halves, and the
12303 // NE test is negated from that.
12304 
12305 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12306 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)).  Note the
12307 // difference between 'Y' and '0L'.  The tree-matches for the CmpI sections
12308 // are collapsed internally in the ADLC's dfa-gen code.  The match for
12309 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12310 // foo match ends up with the wrong leaf.  One fix is to not match both
12311 // reg-reg and reg-zero forms of long-compare.  This is unfortunate because
12312 // both forms beat the trinary form of long-compare and both are very useful
12313 // on Intel which has so few registers.
12314 
12315 // Manifest a CmpL result in an integer register.  Very painful.
12316 // This is the test to avoid.
12317 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12318   match(Set dst (CmpL3 src1 src2));
12319   effect( KILL flags );
12320   ins_cost(1000);
12321   format %{ "XOR    $dst,$dst\n\t"
12322             "CMP    $src1.hi,$src2.hi\n\t"
12323             "JLT,s  m_one\n\t"
12324             "JGT,s  p_one\n\t"
12325             "CMP    $src1.lo,$src2.lo\n\t"
12326             "JB,s   m_one\n\t"
12327             "JEQ,s  done\n"
12328     "p_one:\tINC    $dst\n\t"
12329             "JMP,s  done\n"
12330     "m_one:\tDEC    $dst\n"
12331      "done:" %}
12332   ins_encode %{
12333     Label p_one, m_one, done;
12334     __ xorptr($dst$$Register, $dst$$Register);
12335     __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12336     __ jccb(Assembler::less,    m_one);
12337     __ jccb(Assembler::greater, p_one);
12338     __ cmpl($src1$$Register, $src2$$Register);
12339     __ jccb(Assembler::below,   m_one);
12340     __ jccb(Assembler::equal,   done);
12341     __ bind(p_one);
12342     __ incrementl($dst$$Register);
12343     __ jmpb(done);
12344     __ bind(m_one);
12345     __ decrementl($dst$$Register);
12346     __ bind(done);
12347   %}
12348   ins_pipe( pipe_slow );
12349 %}
12350 
12351 //======
12352 // Manifest a CmpL result in the normal flags.  Only good for LT or GE
12353 // compares.  Can be used for LE or GT compares by reversing arguments.
12354 // NOT GOOD FOR EQ/NE tests.
12355 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12356   match( Set flags (CmpL src zero ));
12357   ins_cost(100);
12358   format %{ "TEST   $src.hi,$src.hi" %}
12359   opcode(0x85);
12360   ins_encode( OpcP, RegReg_Hi2( src, src ) );
12361   ins_pipe( ialu_cr_reg_reg );
12362 %}
12363 
12364 // Manifest a CmpL result in the normal flags.  Only good for LT or GE
12365 // compares.  Can be used for LE or GT compares by reversing arguments.
12366 // NOT GOOD FOR EQ/NE tests.
12367 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12368   match( Set flags (CmpL src1 src2 ));
12369   effect( TEMP tmp );
12370   ins_cost(300);
12371   format %{ "CMP    $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12372             "MOV    $tmp,$src1.hi\n\t"
12373             "SBB    $tmp,$src2.hi\t! Compute flags for long compare" %}
12374   ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12375   ins_pipe( ialu_cr_reg_reg );
12376 %}
12377 
12378 // Long compares reg < zero/req OR reg >= zero/req.
12379 // Just a wrapper for a normal branch, plus the predicate test.
12380 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12381   match(If cmp flags);
12382   effect(USE labl);
12383   predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12384   expand %{
12385     jmpCon(cmp,flags,labl);    // JLT or JGE...
12386   %}
12387 %}
12388 
12389 // Compare 2 longs and CMOVE longs.
12390 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12391   match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12392   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12393   ins_cost(400);
12394   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12395             "CMOV$cmp $dst.hi,$src.hi" %}
12396   opcode(0x0F,0x40);
12397   ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12398   ins_pipe( pipe_cmov_reg_long );
12399 %}
12400 
12401 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12402   match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12403   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12404   ins_cost(500);
12405   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12406             "CMOV$cmp $dst.hi,$src.hi" %}
12407   opcode(0x0F,0x40);
12408   ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12409   ins_pipe( pipe_cmov_reg_long );
12410 %}
12411 
12412 // Compare 2 longs and CMOVE ints.
12413 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12414   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12415   match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12416   ins_cost(200);
12417   format %{ "CMOV$cmp $dst,$src" %}
12418   opcode(0x0F,0x40);
12419   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12420   ins_pipe( pipe_cmov_reg );
12421 %}
12422 
12423 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12424   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12425   match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12426   ins_cost(250);
12427   format %{ "CMOV$cmp $dst,$src" %}
12428   opcode(0x0F,0x40);
12429   ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12430   ins_pipe( pipe_cmov_mem );
12431 %}
12432 
12433 // Compare 2 longs and CMOVE ints.
12434 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12435   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12436   match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12437   ins_cost(200);
12438   format %{ "CMOV$cmp $dst,$src" %}
12439   opcode(0x0F,0x40);
12440   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12441   ins_pipe( pipe_cmov_reg );
12442 %}
12443 
12444 // Compare 2 longs and CMOVE doubles
12445 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12446   predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12447   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12448   ins_cost(200);
12449   expand %{
12450     fcmovDPR_regS(cmp,flags,dst,src);
12451   %}
12452 %}
12453 
12454 // Compare 2 longs and CMOVE doubles
12455 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12456   predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12457   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12458   ins_cost(200);
12459   expand %{
12460     fcmovD_regS(cmp,flags,dst,src);
12461   %}
12462 %}
12463 
12464 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12465   predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12466   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12467   ins_cost(200);
12468   expand %{
12469     fcmovFPR_regS(cmp,flags,dst,src);
12470   %}
12471 %}
12472 
12473 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12474   predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12475   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12476   ins_cost(200);
12477   expand %{
12478     fcmovF_regS(cmp,flags,dst,src);
12479   %}
12480 %}
12481 
12482 //======
12483 // Manifest a CmpL result in the normal flags.  Only good for EQ/NE compares.
12484 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12485   match( Set flags (CmpL src zero ));
12486   effect(TEMP tmp);
12487   ins_cost(200);
12488   format %{ "MOV    $tmp,$src.lo\n\t"
12489             "OR     $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12490   ins_encode( long_cmp_flags0( src, tmp ) );
12491   ins_pipe( ialu_reg_reg_long );
12492 %}
12493 
12494 // Manifest a CmpL result in the normal flags.  Only good for EQ/NE compares.
12495 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12496   match( Set flags (CmpL src1 src2 ));
12497   ins_cost(200+300);
12498   format %{ "CMP    $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12499             "JNE,s  skip\n\t"
12500             "CMP    $src1.hi,$src2.hi\n\t"
12501      "skip:\t" %}
12502   ins_encode( long_cmp_flags1( src1, src2 ) );
12503   ins_pipe( ialu_cr_reg_reg );
12504 %}
12505 
12506 // Long compare reg == zero/reg OR reg != zero/reg
12507 // Just a wrapper for a normal branch, plus the predicate test.
12508 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12509   match(If cmp flags);
12510   effect(USE labl);
12511   predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12512   expand %{
12513     jmpCon(cmp,flags,labl);    // JEQ or JNE...
12514   %}
12515 %}
12516 
12517 // Compare 2 longs and CMOVE longs.
12518 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12519   match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12520   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12521   ins_cost(400);
12522   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12523             "CMOV$cmp $dst.hi,$src.hi" %}
12524   opcode(0x0F,0x40);
12525   ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12526   ins_pipe( pipe_cmov_reg_long );
12527 %}
12528 
12529 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12530   match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12531   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12532   ins_cost(500);
12533   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12534             "CMOV$cmp $dst.hi,$src.hi" %}
12535   opcode(0x0F,0x40);
12536   ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12537   ins_pipe( pipe_cmov_reg_long );
12538 %}
12539 
12540 // Compare 2 longs and CMOVE ints.
12541 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12542   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12543   match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12544   ins_cost(200);
12545   format %{ "CMOV$cmp $dst,$src" %}
12546   opcode(0x0F,0x40);
12547   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12548   ins_pipe( pipe_cmov_reg );
12549 %}
12550 
12551 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12552   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12553   match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12554   ins_cost(250);
12555   format %{ "CMOV$cmp $dst,$src" %}
12556   opcode(0x0F,0x40);
12557   ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12558   ins_pipe( pipe_cmov_mem );
12559 %}
12560 
12561 // Compare 2 longs and CMOVE ints.
12562 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12563   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12564   match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12565   ins_cost(200);
12566   format %{ "CMOV$cmp $dst,$src" %}
12567   opcode(0x0F,0x40);
12568   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12569   ins_pipe( pipe_cmov_reg );
12570 %}
12571 
12572 // Compare 2 longs and CMOVE doubles
12573 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12574   predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12575   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12576   ins_cost(200);
12577   expand %{
12578     fcmovDPR_regS(cmp,flags,dst,src);
12579   %}
12580 %}
12581 
12582 // Compare 2 longs and CMOVE doubles
12583 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12584   predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12585   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12586   ins_cost(200);
12587   expand %{
12588     fcmovD_regS(cmp,flags,dst,src);
12589   %}
12590 %}
12591 
12592 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12593   predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12594   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12595   ins_cost(200);
12596   expand %{
12597     fcmovFPR_regS(cmp,flags,dst,src);
12598   %}
12599 %}
12600 
12601 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12602   predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12603   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12604   ins_cost(200);
12605   expand %{
12606     fcmovF_regS(cmp,flags,dst,src);
12607   %}
12608 %}
12609 
12610 //======
12611 // Manifest a CmpL result in the normal flags.  Only good for LE or GT compares.
12612 // Same as cmpL_reg_flags_LEGT except must negate src
12613 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12614   match( Set flags (CmpL src zero ));
12615   effect( TEMP tmp );
12616   ins_cost(300);
12617   format %{ "XOR    $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12618             "CMP    $tmp,$src.lo\n\t"
12619             "SBB    $tmp,$src.hi\n\t" %}
12620   ins_encode( long_cmp_flags3(src, tmp) );
12621   ins_pipe( ialu_reg_reg_long );
12622 %}
12623 
12624 // Manifest a CmpL result in the normal flags.  Only good for LE or GT compares.
12625 // Same as cmpL_reg_flags_LTGE except operands swapped.  Swapping operands
12626 // requires a commuted test to get the same result.
12627 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12628   match( Set flags (CmpL src1 src2 ));
12629   effect( TEMP tmp );
12630   ins_cost(300);
12631   format %{ "CMP    $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12632             "MOV    $tmp,$src2.hi\n\t"
12633             "SBB    $tmp,$src1.hi\t! Compute flags for long compare" %}
12634   ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12635   ins_pipe( ialu_cr_reg_reg );
12636 %}
12637 
12638 // Long compares reg < zero/req OR reg >= zero/req.
12639 // Just a wrapper for a normal branch, plus the predicate test
12640 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12641   match(If cmp flags);
12642   effect(USE labl);
12643   predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12644   ins_cost(300);
12645   expand %{
12646     jmpCon(cmp,flags,labl);    // JGT or JLE...
12647   %}
12648 %}
12649 
12650 // Compare 2 longs and CMOVE longs.
12651 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12652   match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12653   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12654   ins_cost(400);
12655   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12656             "CMOV$cmp $dst.hi,$src.hi" %}
12657   opcode(0x0F,0x40);
12658   ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12659   ins_pipe( pipe_cmov_reg_long );
12660 %}
12661 
12662 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12663   match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12664   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12665   ins_cost(500);
12666   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12667             "CMOV$cmp $dst.hi,$src.hi+4" %}
12668   opcode(0x0F,0x40);
12669   ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12670   ins_pipe( pipe_cmov_reg_long );
12671 %}
12672 
12673 // Compare 2 longs and CMOVE ints.
12674 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12675   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12676   match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12677   ins_cost(200);
12678   format %{ "CMOV$cmp $dst,$src" %}
12679   opcode(0x0F,0x40);
12680   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12681   ins_pipe( pipe_cmov_reg );
12682 %}
12683 
12684 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12685   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12686   match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12687   ins_cost(250);
12688   format %{ "CMOV$cmp $dst,$src" %}
12689   opcode(0x0F,0x40);
12690   ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12691   ins_pipe( pipe_cmov_mem );
12692 %}
12693 
12694 // Compare 2 longs and CMOVE ptrs.
12695 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12696   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12697   match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12698   ins_cost(200);
12699   format %{ "CMOV$cmp $dst,$src" %}
12700   opcode(0x0F,0x40);
12701   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12702   ins_pipe( pipe_cmov_reg );
12703 %}
12704 
12705 // Compare 2 longs and CMOVE doubles
12706 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12707   predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12708   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12709   ins_cost(200);
12710   expand %{
12711     fcmovDPR_regS(cmp,flags,dst,src);
12712   %}
12713 %}
12714 
12715 // Compare 2 longs and CMOVE doubles
12716 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12717   predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12718   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12719   ins_cost(200);
12720   expand %{
12721     fcmovD_regS(cmp,flags,dst,src);
12722   %}
12723 %}
12724 
12725 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12726   predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12727   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12728   ins_cost(200);
12729   expand %{
12730     fcmovFPR_regS(cmp,flags,dst,src);
12731   %}
12732 %}
12733 
12734 
12735 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12736   predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12737   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12738   ins_cost(200);
12739   expand %{
12740     fcmovF_regS(cmp,flags,dst,src);
12741   %}
12742 %}
12743 
12744 
12745 // ============================================================================
12746 // Procedure Call/Return Instructions
12747 // Call Java Static Instruction
12748 // Note: If this code changes, the corresponding ret_addr_offset() and
12749 //       compute_padding() functions will have to be adjusted.
12750 instruct CallStaticJavaDirect(method meth) %{
12751   match(CallStaticJava);
12752   predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12753   effect(USE meth);
12754 
12755   ins_cost(300);
12756   format %{ "CALL,static " %}
12757   opcode(0xE8); /* E8 cd */
12758   ins_encode( pre_call_resets,
12759               Java_Static_Call( meth ),
12760               call_epilog,
12761               post_call_FPU );
12762   ins_pipe( pipe_slow );
12763   ins_alignment(4);
12764 %}
12765 
12766 // Call Java Static Instruction (method handle version)
12767 // Note: If this code changes, the corresponding ret_addr_offset() and
12768 //       compute_padding() functions will have to be adjusted.
12769 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12770   match(CallStaticJava);
12771   predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12772   effect(USE meth);
12773   // EBP is saved by all callees (for interpreter stack correction).
12774   // We use it here for a similar purpose, in {preserve,restore}_SP.
12775 
12776   ins_cost(300);
12777   format %{ "CALL,static/MethodHandle " %}
12778   opcode(0xE8); /* E8 cd */
12779   ins_encode( pre_call_resets,
12780               preserve_SP,
12781               Java_Static_Call( meth ),
12782               restore_SP,
12783               call_epilog,
12784               post_call_FPU );
12785   ins_pipe( pipe_slow );
12786   ins_alignment(4);
12787 %}
12788 
12789 // Call Java Dynamic Instruction
12790 // Note: If this code changes, the corresponding ret_addr_offset() and
12791 //       compute_padding() functions will have to be adjusted.
12792 instruct CallDynamicJavaDirect(method meth) %{
12793   match(CallDynamicJava);
12794   effect(USE meth);
12795 
12796   ins_cost(300);
12797   format %{ "MOV    EAX,(oop)-1\n\t"
12798             "CALL,dynamic" %}
12799   opcode(0xE8); /* E8 cd */
12800   ins_encode( pre_call_resets,
12801               Java_Dynamic_Call( meth ),
12802               call_epilog,
12803               post_call_FPU );
12804   ins_pipe( pipe_slow );
12805   ins_alignment(4);
12806 %}
12807 
12808 // Call Runtime Instruction
12809 instruct CallRuntimeDirect(method meth) %{
12810   match(CallRuntime );
12811   effect(USE meth);
12812 
12813   ins_cost(300);
12814   format %{ "CALL,runtime " %}
12815   opcode(0xE8); /* E8 cd */
12816   // Use FFREEs to clear entries in float stack
12817   ins_encode( pre_call_resets,
12818               FFree_Float_Stack_All,
12819               Java_To_Runtime( meth ),
12820               post_call_FPU );
12821   ins_pipe( pipe_slow );
12822 %}
12823 
12824 // Call runtime without safepoint
12825 instruct CallLeafDirect(method meth) %{
12826   match(CallLeaf);
12827   effect(USE meth);
12828 
12829   ins_cost(300);
12830   format %{ "CALL_LEAF,runtime " %}
12831   opcode(0xE8); /* E8 cd */
12832   ins_encode( pre_call_resets,
12833               FFree_Float_Stack_All,
12834               Java_To_Runtime( meth ),
12835               Verify_FPU_For_Leaf, post_call_FPU );
12836   ins_pipe( pipe_slow );
12837 %}
12838 
12839 instruct CallLeafNoFPDirect(method meth) %{
12840   match(CallLeafNoFP);
12841   effect(USE meth);
12842 
12843   ins_cost(300);
12844   format %{ "CALL_LEAF_NOFP,runtime " %}
12845   opcode(0xE8); /* E8 cd */
12846   ins_encode(Java_To_Runtime(meth));
12847   ins_pipe( pipe_slow );
12848 %}
12849 
12850 
12851 // Return Instruction
12852 // Remove the return address & jump to it.
12853 instruct Ret() %{
12854   match(Return);
12855   format %{ "RET" %}
12856   opcode(0xC3);
12857   ins_encode(OpcP);
12858   ins_pipe( pipe_jmp );
12859 %}
12860 
12861 // Tail Call; Jump from runtime stub to Java code.
12862 // Also known as an 'interprocedural jump'.
12863 // Target of jump will eventually return to caller.
12864 // TailJump below removes the return address.
12865 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12866   match(TailCall jump_target method_oop );
12867   ins_cost(300);
12868   format %{ "JMP    $jump_target \t# EBX holds method oop" %}
12869   opcode(0xFF, 0x4);  /* Opcode FF /4 */
12870   ins_encode( OpcP, RegOpc(jump_target) );
12871   ins_pipe( pipe_jmp );
12872 %}
12873 
12874 
12875 // Tail Jump; remove the return address; jump to target.
12876 // TailCall above leaves the return address around.
12877 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12878   match( TailJump jump_target ex_oop );
12879   ins_cost(300);
12880   format %{ "POP    EDX\t# pop return address into dummy\n\t"
12881             "JMP    $jump_target " %}
12882   opcode(0xFF, 0x4);  /* Opcode FF /4 */
12883   ins_encode( enc_pop_rdx,
12884               OpcP, RegOpc(jump_target) );
12885   ins_pipe( pipe_jmp );
12886 %}
12887 
12888 // Create exception oop: created by stack-crawling runtime code.
12889 // Created exception is now available to this handler, and is setup
12890 // just prior to jumping to this handler.  No code emitted.
12891 instruct CreateException( eAXRegP ex_oop )
12892 %{
12893   match(Set ex_oop (CreateEx));
12894 
12895   size(0);
12896   // use the following format syntax
12897   format %{ "# exception oop is in EAX; no code emitted" %}
12898   ins_encode();
12899   ins_pipe( empty );
12900 %}
12901 
12902 
12903 // Rethrow exception:
12904 // The exception oop will come in the first argument position.
12905 // Then JUMP (not call) to the rethrow stub code.
12906 instruct RethrowException()
12907 %{
12908   match(Rethrow);
12909 
12910   // use the following format syntax
12911   format %{ "JMP    rethrow_stub" %}
12912   ins_encode(enc_rethrow);
12913   ins_pipe( pipe_jmp );
12914 %}
12915 
12916 // inlined locking and unlocking
12917 
12918 instruct cmpFastLockRTM(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eDXRegI scr, rRegI cx1, rRegI cx2) %{
12919   predicate(Compile::current()->use_rtm());
12920   match(Set cr (FastLock object box));
12921   effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12922   ins_cost(300);
12923   format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12924   ins_encode %{
12925     __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12926                  $scr$$Register, $cx1$$Register, $cx2$$Register,
12927                  _counters, _rtm_counters, _stack_rtm_counters,
12928                  ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12929                  true, ra_->C->profile_rtm());
12930   %}
12931   ins_pipe(pipe_slow);
12932 %}
12933 
12934 instruct cmpFastLock(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
12935   predicate(!Compile::current()->use_rtm());
12936   match(Set cr (FastLock object box));
12937   effect(TEMP tmp, TEMP scr, USE_KILL box);
12938   ins_cost(300);
12939   format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
12940   ins_encode %{
12941     __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12942                  $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12943   %}
12944   ins_pipe(pipe_slow);
12945 %}
12946 
12947 instruct cmpFastUnlock(eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12948   match(Set cr (FastUnlock object box));
12949   effect(TEMP tmp, USE_KILL box);
12950   ins_cost(300);
12951   format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
12952   ins_encode %{
12953     __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12954   %}
12955   ins_pipe(pipe_slow);
12956 %}
12957 
12958 
12959 
12960 // ============================================================================
12961 // Safepoint Instruction
12962 instruct safePoint_poll(eFlagsReg cr) %{
12963   match(SafePoint);
12964   effect(KILL cr);
12965 
12966   // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
12967   // On SPARC that might be acceptable as we can generate the address with
12968   // just a sethi, saving an or.  By polling at offset 0 we can end up
12969   // putting additional pressure on the index-0 in the D$.  Because of
12970   // alignment (just like the situation at hand) the lower indices tend
12971   // to see more traffic.  It'd be better to change the polling address
12972   // to offset 0 of the last $line in the polling page.
12973 
12974   format %{ "TSTL   #polladdr,EAX\t! Safepoint: poll for GC" %}
12975   ins_cost(125);
12976   size(6) ;
12977   ins_encode( Safepoint_Poll() );
12978   ins_pipe( ialu_reg_mem );
12979 %}
12980 
12981 
12982 // ============================================================================
12983 // This name is KNOWN by the ADLC and cannot be changed.
12984 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12985 // for this guy.
12986 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
12987   match(Set dst (ThreadLocal));
12988   effect(DEF dst, KILL cr);
12989 
12990   format %{ "MOV    $dst, Thread::current()" %}
12991   ins_encode %{
12992     Register dstReg = as_Register($dst$$reg);
12993     __ get_thread(dstReg);
12994   %}
12995   ins_pipe( ialu_reg_fat );
12996 %}
12997 
12998 
12999 
13000 //----------PEEPHOLE RULES-----------------------------------------------------
13001 // These must follow all instruction definitions as they use the names
13002 // defined in the instructions definitions.
13003 //
13004 // peepmatch ( root_instr_name [preceding_instruction]* );
13005 //
13006 // peepconstraint %{
13007 // (instruction_number.operand_name relational_op instruction_number.operand_name
13008 //  [, ...] );
13009 // // instruction numbers are zero-based using left to right order in peepmatch
13010 //
13011 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
13012 // // provide an instruction_number.operand_name for each operand that appears
13013 // // in the replacement instruction's match rule
13014 //
13015 // ---------VM FLAGS---------------------------------------------------------
13016 //
13017 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13018 //
13019 // Each peephole rule is given an identifying number starting with zero and
13020 // increasing by one in the order seen by the parser.  An individual peephole
13021 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13022 // on the command-line.
13023 //
13024 // ---------CURRENT LIMITATIONS----------------------------------------------
13025 //
13026 // Only match adjacent instructions in same basic block
13027 // Only equality constraints
13028 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13029 // Only one replacement instruction
13030 //
13031 // ---------EXAMPLE----------------------------------------------------------
13032 //
13033 // // pertinent parts of existing instructions in architecture description
13034 // instruct movI(rRegI dst, rRegI src) %{
13035 //   match(Set dst (CopyI src));
13036 // %}
13037 //
13038 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13039 //   match(Set dst (AddI dst src));
13040 //   effect(KILL cr);
13041 // %}
13042 //
13043 // // Change (inc mov) to lea
13044 // peephole %{
13045 //   // increment preceeded by register-register move
13046 //   peepmatch ( incI_eReg movI );
13047 //   // require that the destination register of the increment
13048 //   // match the destination register of the move
13049 //   peepconstraint ( 0.dst == 1.dst );
13050 //   // construct a replacement instruction that sets
13051 //   // the destination to ( move's source register + one )
13052 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13053 // %}
13054 //
13055 // Implementation no longer uses movX instructions since
13056 // machine-independent system no longer uses CopyX nodes.
13057 //
13058 // peephole %{
13059 //   peepmatch ( incI_eReg movI );
13060 //   peepconstraint ( 0.dst == 1.dst );
13061 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13062 // %}
13063 //
13064 // peephole %{
13065 //   peepmatch ( decI_eReg movI );
13066 //   peepconstraint ( 0.dst == 1.dst );
13067 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13068 // %}
13069 //
13070 // peephole %{
13071 //   peepmatch ( addI_eReg_imm movI );
13072 //   peepconstraint ( 0.dst == 1.dst );
13073 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13074 // %}
13075 //
13076 // peephole %{
13077 //   peepmatch ( addP_eReg_imm movP );
13078 //   peepconstraint ( 0.dst == 1.dst );
13079 //   peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13080 // %}
13081 
13082 // // Change load of spilled value to only a spill
13083 // instruct storeI(memory mem, rRegI src) %{
13084 //   match(Set mem (StoreI mem src));
13085 // %}
13086 //
13087 // instruct loadI(rRegI dst, memory mem) %{
13088 //   match(Set dst (LoadI mem));
13089 // %}
13090 //
13091 peephole %{
13092   peepmatch ( loadI storeI );
13093   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13094   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13095 %}
13096 
13097 //----------SMARTSPILL RULES---------------------------------------------------
13098 // These must follow all instruction definitions as they use the names
13099 // defined in the instructions definitions.