458 _cpuFeatures &= ~CPU_SSE2;
459
460 if (UseSSE < 1)
461 _cpuFeatures &= ~CPU_SSE;
462
463 if (UseAVX < 2)
464 _cpuFeatures &= ~CPU_AVX2;
465
466 if (UseAVX < 1)
467 _cpuFeatures &= ~CPU_AVX;
468
469 if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
470 _cpuFeatures &= ~CPU_AES;
471
472 if (logical_processors_per_package() == 1) {
473 // HT processor could be installed on a system which doesn't support HT.
474 _cpuFeatures &= ~CPU_HT;
475 }
476
477 char buf[256];
478 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
479 cores_per_cpu(), threads_per_core(),
480 cpu_family(), _model, _stepping,
481 (supports_cmov() ? ", cmov" : ""),
482 (supports_cmpxchg8() ? ", cx8" : ""),
483 (supports_fxsr() ? ", fxsr" : ""),
484 (supports_mmx() ? ", mmx" : ""),
485 (supports_sse() ? ", sse" : ""),
486 (supports_sse2() ? ", sse2" : ""),
487 (supports_sse3() ? ", sse3" : ""),
488 (supports_ssse3()? ", ssse3": ""),
489 (supports_sse4_1() ? ", sse4.1" : ""),
490 (supports_sse4_2() ? ", sse4.2" : ""),
491 (supports_popcnt() ? ", popcnt" : ""),
492 (supports_avx() ? ", avx" : ""),
493 (supports_avx2() ? ", avx2" : ""),
494 (supports_aes() ? ", aes" : ""),
495 (supports_clmul() ? ", clmul" : ""),
496 (supports_erms() ? ", erms" : ""),
497 (supports_mmx_ext() ? ", mmxext" : ""),
498 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
499 (supports_lzcnt() ? ", lzcnt": ""),
500 (supports_sse4a() ? ", sse4a": ""),
501 (supports_ht() ? ", ht": ""),
502 (supports_tsc() ? ", tsc": ""),
503 (supports_tscinv_bit() ? ", tscinvbit": ""),
504 (supports_tscinv() ? ", tscinv": ""),
505 (supports_bmi1() ? ", bmi1" : ""),
506 (supports_bmi2() ? ", bmi2" : ""));
507 _features_str = strdup(buf);
508
509 // UseSSE is set to the smaller of what hardware supports and what
510 // the command line requires. I.e., you cannot set UseSSE to 2 on
511 // older Pentiums which do not support it.
512 if (UseSSE > 4) UseSSE=4;
513 if (UseSSE < 0) UseSSE=0;
514 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
515 UseSSE = MIN2((intx)3,UseSSE);
516 if (!supports_sse3()) // Drop to 2 if no SSE3 support
517 UseSSE = MIN2((intx)2,UseSSE);
518 if (!supports_sse2()) // Drop to 1 if no SSE2 support
519 UseSSE = MIN2((intx)1,UseSSE);
520 if (!supports_sse ()) // Drop to 0 if no SSE support
521 UseSSE = 0;
522
523 if (UseAVX > 2) UseAVX=2;
524 if (UseAVX < 0) UseAVX=0;
525 if (!supports_avx2()) // Drop to 1 if no AVX2 support
526 UseAVX = MIN2((intx)1,UseAVX);
527 if (!supports_avx ()) // Drop to 0 if no AVX support
528 UseAVX = 0;
529
530 // Use AES instructions if available.
531 if (supports_aes()) {
532 if (FLAG_IS_DEFAULT(UseAES)) {
533 UseAES = true;
534 }
535 } else if (UseAES) {
536 if (!FLAG_IS_DEFAULT(UseAES))
537 warning("AES instructions not available on this CPU");
538 FLAG_SET_DEFAULT(UseAES, false);
539 }
540
541 // Use CLMUL instructions if available.
542 if (supports_clmul()) {
543 if (FLAG_IS_DEFAULT(UseCLMUL)) {
544 UseCLMUL = true;
545 }
546 } else if (UseCLMUL) {
547 if (!FLAG_IS_DEFAULT(UseCLMUL))
548 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
549 FLAG_SET_DEFAULT(UseCLMUL, false);
550 }
551
552 if (UseCLMUL && (UseAVX > 0) && (UseSSE > 2)) {
553 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
554 UseCRC32Intrinsics = true;
555 }
556 } else if (UseCRC32Intrinsics) {
557 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
558 warning("CRC32 Intrinsics requires AVX and CLMUL instructions (not available on this CPU)");
559 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
560 }
561
562 // The AES intrinsic stubs require AES instruction support (of course)
563 // but also require sse3 mode for instructions it use.
564 if (UseAES && (UseSSE > 2)) {
565 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
566 UseAESIntrinsics = true;
567 }
568 } else if (UseAESIntrinsics) {
569 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
570 warning("AES intrinsics not available on this CPU");
571 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
572 }
573
574 #ifdef COMPILER2
575 if (UseFPUForSpilling) {
576 if (UseSSE < 2) {
577 // Only supported with SSE2+
578 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
579 }
580 }
581 if (MaxVectorSize > 0) {
582 if (!is_power_of_2(MaxVectorSize)) {
583 warning("MaxVectorSize must be a power of 2");
584 FLAG_SET_DEFAULT(MaxVectorSize, 32);
585 }
586 if (MaxVectorSize > 32) {
587 FLAG_SET_DEFAULT(MaxVectorSize, 32);
588 }
589 if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) {
590 // 32 bytes vectors (in YMM) are only supported with AVX+
591 FLAG_SET_DEFAULT(MaxVectorSize, 16);
592 }
593 if (UseSSE < 2) {
896 tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
897 }
898 }
899
900 if (PrefetchCopyIntervalInBytes > 0) {
901 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
902 }
903 if (PrefetchScanIntervalInBytes > 0) {
904 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
905 }
906 if (PrefetchFieldsAhead > 0) {
907 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
908 }
909 if (ContendedPaddingWidth > 0) {
910 tty->print_cr("ContendedPaddingWidth %d", ContendedPaddingWidth);
911 }
912 }
913 #endif // !PRODUCT
914 }
915
916 void VM_Version::initialize() {
917 ResourceMark rm;
918 // Making this stub must be FIRST use of assembler
919
920 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
921 if (stub_blob == NULL) {
922 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
923 }
924 CodeBuffer c(stub_blob);
925 VM_Version_StubGenerator g(&c);
926 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
927 g.generate_getPsrInfo());
928
929 get_processor_features();
930 }
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458 _cpuFeatures &= ~CPU_SSE2;
459
460 if (UseSSE < 1)
461 _cpuFeatures &= ~CPU_SSE;
462
463 if (UseAVX < 2)
464 _cpuFeatures &= ~CPU_AVX2;
465
466 if (UseAVX < 1)
467 _cpuFeatures &= ~CPU_AVX;
468
469 if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
470 _cpuFeatures &= ~CPU_AES;
471
472 if (logical_processors_per_package() == 1) {
473 // HT processor could be installed on a system which doesn't support HT.
474 _cpuFeatures &= ~CPU_HT;
475 }
476
477 char buf[256];
478 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
479 cores_per_cpu(), threads_per_core(),
480 cpu_family(), _model, _stepping,
481 (supports_cmov() ? ", cmov" : ""),
482 (supports_cmpxchg8() ? ", cx8" : ""),
483 (supports_fxsr() ? ", fxsr" : ""),
484 (supports_mmx() ? ", mmx" : ""),
485 (supports_sse() ? ", sse" : ""),
486 (supports_sse2() ? ", sse2" : ""),
487 (supports_sse3() ? ", sse3" : ""),
488 (supports_ssse3()? ", ssse3": ""),
489 (supports_sse4_1() ? ", sse4.1" : ""),
490 (supports_sse4_2() ? ", sse4.2" : ""),
491 (supports_popcnt() ? ", popcnt" : ""),
492 (supports_avx() ? ", avx" : ""),
493 (supports_avx2() ? ", avx2" : ""),
494 (supports_aes() ? ", aes" : ""),
495 (supports_clmul() ? ", clmul" : ""),
496 (supports_erms() ? ", erms" : ""),
497 (supports_rtm() ? ", rtm" : ""),
498 (supports_mmx_ext() ? ", mmxext" : ""),
499 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
500 (supports_lzcnt() ? ", lzcnt": ""),
501 (supports_sse4a() ? ", sse4a": ""),
502 (supports_ht() ? ", ht": ""),
503 (supports_tsc() ? ", tsc": ""),
504 (supports_tscinv_bit() ? ", tscinvbit": ""),
505 (supports_tscinv() ? ", tscinv": ""),
506 (supports_bmi1() ? ", bmi1" : ""),
507 (supports_bmi2() ? ", bmi2" : ""));
508 _features_str = strdup(buf);
509
510 // UseSSE is set to the smaller of what hardware supports and what
511 // the command line requires. I.e., you cannot set UseSSE to 2 on
512 // older Pentiums which do not support it.
513 if (UseSSE > 4) UseSSE=4;
514 if (UseSSE < 0) UseSSE=0;
515 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
516 UseSSE = MIN2((intx)3,UseSSE);
517 if (!supports_sse3()) // Drop to 2 if no SSE3 support
518 UseSSE = MIN2((intx)2,UseSSE);
519 if (!supports_sse2()) // Drop to 1 if no SSE2 support
520 UseSSE = MIN2((intx)1,UseSSE);
521 if (!supports_sse ()) // Drop to 0 if no SSE support
522 UseSSE = 0;
523
524 if (UseAVX > 2) UseAVX=2;
525 if (UseAVX < 0) UseAVX=0;
526 if (!supports_avx2()) // Drop to 1 if no AVX2 support
527 UseAVX = MIN2((intx)1,UseAVX);
528 if (!supports_avx ()) // Drop to 0 if no AVX support
529 UseAVX = 0;
530
531 // Use AES instructions if available.
532 if (supports_aes()) {
533 if (FLAG_IS_DEFAULT(UseAES)) {
534 UseAES = true;
535 }
536 } else if (UseAES) {
537 if (!FLAG_IS_DEFAULT(UseAES))
538 warning("AES instructions are not available on this CPU");
539 FLAG_SET_DEFAULT(UseAES, false);
540 }
541
542 // Use CLMUL instructions if available.
543 if (supports_clmul()) {
544 if (FLAG_IS_DEFAULT(UseCLMUL)) {
545 UseCLMUL = true;
546 }
547 } else if (UseCLMUL) {
548 if (!FLAG_IS_DEFAULT(UseCLMUL))
549 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
550 FLAG_SET_DEFAULT(UseCLMUL, false);
551 }
552
553 if (UseCLMUL && (UseAVX > 0) && (UseSSE > 2)) {
554 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
555 UseCRC32Intrinsics = true;
556 }
557 } else if (UseCRC32Intrinsics) {
558 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
559 warning("CRC32 Intrinsics requires AVX and CLMUL instructions (not available on this CPU)");
560 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
561 }
562
563 // The AES intrinsic stubs require AES instruction support (of course)
564 // but also require sse3 mode for instructions it use.
565 if (UseAES && (UseSSE > 2)) {
566 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
567 UseAESIntrinsics = true;
568 }
569 } else if (UseAESIntrinsics) {
570 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
571 warning("AES intrinsics are not available on this CPU");
572 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
573 }
574
575 // Adjust RTM (Restricted Transactional Memory) flags
576 if (!supports_rtm() && UseRTMLocking) {
577 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
578 // setting during arguments processing. See use_biased_locking().
579 // VM_Version_init() is executed after UseBiasedLocking is used
580 // in Thread::allocate().
581 vm_exit_during_initialization("RTM instructions are not available on this CPU");
582 }
583
584 #if INCLUDE_RTM_OPT
585 if (UseRTMLocking) {
586 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
587 // RTM locking should be used only for applications with
588 // high lock contention. For now we do not use it by default.
589 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
590 }
591 if (!is_power_of_2(RTMTotalCountIncrRate)) {
592 warning("RTMTotalCountIncrRate must be a power of 2, reseting it to 64");
593 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
594 }
595 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
596 warning("RTMAbortRatio must be in the range 0 to 100, reseting it to 50");
597 FLAG_SET_DEFAULT(RTMAbortRatio, 50);
598 }
599 } else { // !UseRTMLocking
600 if (UseRTMForStackLocks) {
601 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
602 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
603 }
604 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
605 }
606 if (UseRTMDeopt) {
607 FLAG_SET_DEFAULT(UseRTMDeopt, false);
608 }
609 if (PrintPreciseRTMLockingStatistics) {
610 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
611 }
612 }
613 #else
614 if (UseRTMLocking) {
615 // Only C2 does RTM locking optimization.
616 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
617 // setting during arguments processing. See use_biased_locking().
618 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
619 }
620 #endif
621
622 #ifdef COMPILER2
623 if (UseFPUForSpilling) {
624 if (UseSSE < 2) {
625 // Only supported with SSE2+
626 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
627 }
628 }
629 if (MaxVectorSize > 0) {
630 if (!is_power_of_2(MaxVectorSize)) {
631 warning("MaxVectorSize must be a power of 2");
632 FLAG_SET_DEFAULT(MaxVectorSize, 32);
633 }
634 if (MaxVectorSize > 32) {
635 FLAG_SET_DEFAULT(MaxVectorSize, 32);
636 }
637 if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) {
638 // 32 bytes vectors (in YMM) are only supported with AVX+
639 FLAG_SET_DEFAULT(MaxVectorSize, 16);
640 }
641 if (UseSSE < 2) {
944 tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
945 }
946 }
947
948 if (PrefetchCopyIntervalInBytes > 0) {
949 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
950 }
951 if (PrefetchScanIntervalInBytes > 0) {
952 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
953 }
954 if (PrefetchFieldsAhead > 0) {
955 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
956 }
957 if (ContendedPaddingWidth > 0) {
958 tty->print_cr("ContendedPaddingWidth %d", ContendedPaddingWidth);
959 }
960 }
961 #endif // !PRODUCT
962 }
963
964 bool VM_Version::use_biased_locking() {
965 #if INCLUDE_RTM_OPT
966 // RTM locking is most useful when there is high lock contention and
967 // low data contention. With high lock contention the lock is usually
968 // inflated and biased locking is not suitable for that case.
969 // RTM locking code requires that biased locking is off.
970 if (UseRTMLocking && UseBiasedLocking) {
971 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
972 FLAG_SET_DEFAULT(UseBiasedLocking, false);
973 } else {
974 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
975 UseBiasedLocking = false;
976 }
977 }
978 #endif
979 return UseBiasedLocking;
980 }
981
982 void VM_Version::initialize() {
983 ResourceMark rm;
984 // Making this stub must be FIRST use of assembler
985
986 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
987 if (stub_blob == NULL) {
988 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
989 }
990 CodeBuffer c(stub_blob);
991 VM_Version_StubGenerator g(&c);
992 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
993 g.generate_getPsrInfo());
994
995 get_processor_features();
996 }
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