1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
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23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 protected:
42
43 Address as_Address(AddressLiteral adr);
44 Address as_Address(ArrayAddress adr);
45
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51 #ifdef CC_INTERP
52 // c++ interpreter never wants to use interp_masm version of call_VM
53 #define VIRTUAL
54 #else
55 #define VIRTUAL virtual
56 #endif
57
58 VIRTUAL void call_VM_leaf_base(
59 address entry_point, // the entry point
60 int number_of_arguments // the number of arguments to pop after the call
61 );
62
63 // This is the base routine called by the different versions of call_VM. The interpreter
64 // may customize this version by overriding it for its purposes (e.g., to save/restore
65 // additional registers when doing a VM call).
66 //
67 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
68 // returns the register which contains the thread upon return. If a thread register has been
69 // specified, the return value will correspond to that register. If no last_java_sp is specified
70 // (noreg) than rsp will be used instead.
71 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
72 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
73 Register java_thread, // the thread if computed before ; use noreg otherwise
74 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
75 address entry_point, // the entry point
76 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
77 bool check_exceptions // whether to check for pending exceptions after return
78 );
79
80 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
81 // The implementation is only non-empty for the InterpreterMacroAssembler,
82 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
83 virtual void check_and_handle_popframe(Register java_thread);
84 virtual void check_and_handle_earlyret(Register java_thread);
85
86 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
87
88 // helpers for FPU flag access
89 // tmp is a temporary register, if none is available use noreg
90 void save_rax (Register tmp);
91 void restore_rax(Register tmp);
92
93 public:
94 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
95
96 // Support for NULL-checks
97 //
98 // Generates code that causes a NULL OS exception if the content of reg is NULL.
99 // If the accessed location is M[reg + offset] and the offset is known, provide the
100 // offset. No explicit code generation is needed if the offset is within a certain
101 // range (0 <= offset <= page_size).
102
103 void null_check(Register reg, int offset = -1);
104 static bool needs_explicit_null_check(intptr_t offset);
105
106 // Required platform-specific helpers for Label::patch_instructions.
107 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
108 void pd_patch_instruction(address branch, address target) {
109 unsigned char op = branch[0];
110 assert(op == 0xE8 /* call */ ||
111 op == 0xE9 /* jmp */ ||
112 op == 0xEB /* short jmp */ ||
113 (op & 0xF0) == 0x70 /* short jcc */ ||
114 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */,
115 "Invalid opcode at patch point");
116
117 if (op == 0xEB || (op & 0xF0) == 0x70) {
118 // short offset operators (jmp and jcc)
119 char* disp = (char*) &branch[1];
120 int imm8 = target - (address) &disp[1];
121 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
122 *disp = imm8;
123 } else {
124 int* disp = (int*) &branch[(op == 0x0F)? 2: 1];
125 int imm32 = target - (address) &disp[1];
126 *disp = imm32;
127 }
128 }
129
130 // The following 4 methods return the offset of the appropriate move instruction
131
132 // Support for fast byte/short loading with zero extension (depending on particular CPU)
133 int load_unsigned_byte(Register dst, Address src);
134 int load_unsigned_short(Register dst, Address src);
135
136 // Support for fast byte/short loading with sign extension (depending on particular CPU)
137 int load_signed_byte(Register dst, Address src);
138 int load_signed_short(Register dst, Address src);
139
140 // Support for sign-extension (hi:lo = extend_sign(lo))
141 void extend_sign(Register hi, Register lo);
142
143 // Load and store values by size and signed-ness
144 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
145 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
146
147 // Support for inc/dec with optimal instruction selection depending on value
148
149 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
150 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
151
152 void decrementl(Address dst, int value = 1);
153 void decrementl(Register reg, int value = 1);
154
155 void decrementq(Register reg, int value = 1);
156 void decrementq(Address dst, int value = 1);
157
158 void incrementl(Address dst, int value = 1);
159 void incrementl(Register reg, int value = 1);
160
161 void incrementq(Register reg, int value = 1);
162 void incrementq(Address dst, int value = 1);
163
164
165 // Support optimal SSE move instructions.
166 void movflt(XMMRegister dst, XMMRegister src) {
167 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
168 else { movss (dst, src); return; }
169 }
170 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
171 void movflt(XMMRegister dst, AddressLiteral src);
172 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
173
174 void movdbl(XMMRegister dst, XMMRegister src) {
175 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
176 else { movsd (dst, src); return; }
177 }
178
179 void movdbl(XMMRegister dst, AddressLiteral src);
180
181 void movdbl(XMMRegister dst, Address src) {
182 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
183 else { movlpd(dst, src); return; }
184 }
185 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
186
187 void incrementl(AddressLiteral dst);
188 void incrementl(ArrayAddress dst);
189
190 // Alignment
191 void align(int modulus);
192
193 // A 5 byte nop that is safe for patching (see patch_verified_entry)
194 void fat_nop();
195
196 // Stack frame creation/removal
197 void enter();
198 void leave();
199
200 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
201 // The pointer will be loaded into the thread register.
202 void get_thread(Register thread);
203
204
205 // Support for VM calls
206 //
207 // It is imperative that all calls into the VM are handled via the call_VM macros.
208 // They make sure that the stack linkage is setup correctly. call_VM's correspond
209 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
210
211
212 void call_VM(Register oop_result,
213 address entry_point,
214 bool check_exceptions = true);
215 void call_VM(Register oop_result,
216 address entry_point,
217 Register arg_1,
218 bool check_exceptions = true);
219 void call_VM(Register oop_result,
220 address entry_point,
221 Register arg_1, Register arg_2,
222 bool check_exceptions = true);
223 void call_VM(Register oop_result,
224 address entry_point,
225 Register arg_1, Register arg_2, Register arg_3,
226 bool check_exceptions = true);
227
228 // Overloadings with last_Java_sp
229 void call_VM(Register oop_result,
230 Register last_java_sp,
231 address entry_point,
232 int number_of_arguments = 0,
233 bool check_exceptions = true);
234 void call_VM(Register oop_result,
235 Register last_java_sp,
236 address entry_point,
237 Register arg_1, bool
238 check_exceptions = true);
239 void call_VM(Register oop_result,
240 Register last_java_sp,
241 address entry_point,
242 Register arg_1, Register arg_2,
243 bool check_exceptions = true);
244 void call_VM(Register oop_result,
245 Register last_java_sp,
246 address entry_point,
247 Register arg_1, Register arg_2, Register arg_3,
248 bool check_exceptions = true);
249
250 void get_vm_result (Register oop_result, Register thread);
251 void get_vm_result_2(Register metadata_result, Register thread);
252
253 // These always tightly bind to MacroAssembler::call_VM_base
254 // bypassing the virtual implementation
255 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
257 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
258 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
260
261 void call_VM_leaf(address entry_point,
262 int number_of_arguments = 0);
263 void call_VM_leaf(address entry_point,
264 Register arg_1);
265 void call_VM_leaf(address entry_point,
266 Register arg_1, Register arg_2);
267 void call_VM_leaf(address entry_point,
268 Register arg_1, Register arg_2, Register arg_3);
269
270 // These always tightly bind to MacroAssembler::call_VM_leaf_base
271 // bypassing the virtual implementation
272 void super_call_VM_leaf(address entry_point);
273 void super_call_VM_leaf(address entry_point, Register arg_1);
274 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
275 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
276 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
277
278 // last Java Frame (fills frame anchor)
279 void set_last_Java_frame(Register thread,
280 Register last_java_sp,
281 Register last_java_fp,
282 address last_java_pc);
283
284 // thread in the default location (r15_thread on 64bit)
285 void set_last_Java_frame(Register last_java_sp,
286 Register last_java_fp,
287 address last_java_pc);
288
289 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
290
291 // thread in the default location (r15_thread on 64bit)
292 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
293
294 // Stores
295 void store_check(Register obj); // store check for obj - register is destroyed afterwards
296 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
297
298 #if INCLUDE_ALL_GCS
299
300 void g1_write_barrier_pre(Register obj,
301 Register pre_val,
302 Register thread,
303 Register tmp,
304 bool tosca_live,
305 bool expand_call);
306
307 void g1_write_barrier_post(Register store_addr,
308 Register new_val,
309 Register thread,
310 Register tmp,
311 Register tmp2);
312
313 #endif // INCLUDE_ALL_GCS
314
315 // split store_check(Register obj) to enhance instruction interleaving
316 void store_check_part_1(Register obj);
317 void store_check_part_2(Register obj);
318
319 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
320 void c2bool(Register x);
321
322 // C++ bool manipulation
323
324 void movbool(Register dst, Address src);
325 void movbool(Address dst, bool boolconst);
326 void movbool(Address dst, Register src);
327 void testbool(Register dst);
328
329 // oop manipulations
330 void load_klass(Register dst, Register src);
331 void store_klass(Register dst, Register src);
332
333 void load_heap_oop(Register dst, Address src);
334 void load_heap_oop_not_null(Register dst, Address src);
335 void store_heap_oop(Address dst, Register src);
336 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
337
338 // Used for storing NULL. All other oop constants should be
339 // stored using routines that take a jobject.
340 void store_heap_oop_null(Address dst);
341
342 void load_prototype_header(Register dst, Register src);
343
344 #ifdef _LP64
345 void store_klass_gap(Register dst, Register src);
346
347 // This dummy is to prevent a call to store_heap_oop from
348 // converting a zero (like NULL) into a Register by giving
349 // the compiler two choices it can't resolve
350
351 void store_heap_oop(Address dst, void* dummy);
352
353 void encode_heap_oop(Register r);
354 void decode_heap_oop(Register r);
355 void encode_heap_oop_not_null(Register r);
356 void decode_heap_oop_not_null(Register r);
357 void encode_heap_oop_not_null(Register dst, Register src);
358 void decode_heap_oop_not_null(Register dst, Register src);
359
360 void set_narrow_oop(Register dst, jobject obj);
361 void set_narrow_oop(Address dst, jobject obj);
362 void cmp_narrow_oop(Register dst, jobject obj);
363 void cmp_narrow_oop(Address dst, jobject obj);
364
365 void encode_klass_not_null(Register r);
366 void decode_klass_not_null(Register r);
367 void encode_klass_not_null(Register dst, Register src);
368 void decode_klass_not_null(Register dst, Register src);
369 void set_narrow_klass(Register dst, Klass* k);
370 void set_narrow_klass(Address dst, Klass* k);
371 void cmp_narrow_klass(Register dst, Klass* k);
372 void cmp_narrow_klass(Address dst, Klass* k);
373
374 // Returns the byte size of the instructions generated by decode_klass_not_null()
375 // when compressed klass pointers are being used.
376 static int instr_size_for_decode_klass_not_null();
377
378 // if heap base register is used - reinit it with the correct value
379 void reinit_heapbase();
380
381 DEBUG_ONLY(void verify_heapbase(const char* msg);)
382
383 #endif // _LP64
384
385 // Int division/remainder for Java
386 // (as idivl, but checks for special case as described in JVM spec.)
387 // returns idivl instruction offset for implicit exception handling
388 int corrected_idivl(Register reg);
389
390 // Long division/remainder for Java
391 // (as idivq, but checks for special case as described in JVM spec.)
392 // returns idivq instruction offset for implicit exception handling
393 int corrected_idivq(Register reg);
394
395 void int3();
396
397 // Long operation macros for a 32bit cpu
398 // Long negation for Java
399 void lneg(Register hi, Register lo);
400
401 // Long multiplication for Java
402 // (destroys contents of eax, ebx, ecx and edx)
403 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
404
405 // Long shifts for Java
406 // (semantics as described in JVM spec.)
407 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
408 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
409
410 // Long compare for Java
411 // (semantics as described in JVM spec.)
412 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
413
414
415 // misc
416
417 // Sign extension
418 void sign_extend_short(Register reg);
419 void sign_extend_byte(Register reg);
420
421 // Division by power of 2, rounding towards 0
422 void division_with_shift(Register reg, int shift_value);
423
424 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
425 //
426 // CF (corresponds to C0) if x < y
427 // PF (corresponds to C2) if unordered
428 // ZF (corresponds to C3) if x = y
429 //
430 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
431 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
432 void fcmp(Register tmp);
433 // Variant of the above which allows y to be further down the stack
434 // and which only pops x and y if specified. If pop_right is
435 // specified then pop_left must also be specified.
436 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
437
438 // Floating-point comparison for Java
439 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
440 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
441 // (semantics as described in JVM spec.)
442 void fcmp2int(Register dst, bool unordered_is_less);
443 // Variant of the above which allows y to be further down the stack
444 // and which only pops x and y if specified. If pop_right is
445 // specified then pop_left must also be specified.
446 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
447
448 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
449 // tmp is a temporary register, if none is available use noreg
450 void fremr(Register tmp);
451
452
453 // same as fcmp2int, but using SSE2
454 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
455 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
456
457 // Inlined sin/cos generator for Java; must not use CPU instruction
458 // directly on Intel as it does not have high enough precision
459 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
460 // number of FPU stack slots in use; all but the topmost will
461 // require saving if a slow case is necessary. Assumes argument is
462 // on FP TOS; result is on FP TOS. No cpu registers are changed by
463 // this code.
464 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
465
466 // branch to L if FPU flag C2 is set/not set
467 // tmp is a temporary register, if none is available use noreg
468 void jC2 (Register tmp, Label& L);
469 void jnC2(Register tmp, Label& L);
470
471 // Pop ST (ffree & fincstp combined)
472 void fpop();
473
474 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
475 void push_fTOS();
476
477 // pops double TOS element from CPU stack and pushes on FPU stack
478 void pop_fTOS();
479
480 void empty_FPU_stack();
481
482 void push_IU_state();
483 void pop_IU_state();
484
485 void push_FPU_state();
486 void pop_FPU_state();
487
488 void push_CPU_state();
489 void pop_CPU_state();
490
491 // Round up to a power of two
492 void round_to(Register reg, int modulus);
493
494 // Callee saved registers handling
495 void push_callee_saved_registers();
496 void pop_callee_saved_registers();
497
498 // allocation
499 void eden_allocate(
500 Register obj, // result: pointer to object after successful allocation
501 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
502 int con_size_in_bytes, // object size in bytes if known at compile time
503 Register t1, // temp register
504 Label& slow_case // continuation point if fast allocation fails
505 );
506 void tlab_allocate(
507 Register obj, // result: pointer to object after successful allocation
508 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
509 int con_size_in_bytes, // object size in bytes if known at compile time
510 Register t1, // temp register
511 Register t2, // temp register
512 Label& slow_case // continuation point if fast allocation fails
513 );
514 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
515 void incr_allocated_bytes(Register thread,
516 Register var_size_in_bytes, int con_size_in_bytes,
517 Register t1 = noreg);
518
519 // interface method calling
520 void lookup_interface_method(Register recv_klass,
521 Register intf_klass,
522 RegisterOrConstant itable_index,
523 Register method_result,
524 Register scan_temp,
525 Label& no_such_interface);
526
527 // virtual method calling
528 void lookup_virtual_method(Register recv_klass,
529 RegisterOrConstant vtable_index,
530 Register method_result);
531
532 // Test sub_klass against super_klass, with fast and slow paths.
533
534 // The fast path produces a tri-state answer: yes / no / maybe-slow.
535 // One of the three labels can be NULL, meaning take the fall-through.
536 // If super_check_offset is -1, the value is loaded up from super_klass.
537 // No registers are killed, except temp_reg.
538 void check_klass_subtype_fast_path(Register sub_klass,
539 Register super_klass,
540 Register temp_reg,
541 Label* L_success,
542 Label* L_failure,
543 Label* L_slow_path,
544 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
545
546 // The rest of the type check; must be wired to a corresponding fast path.
547 // It does not repeat the fast path logic, so don't use it standalone.
548 // The temp_reg and temp2_reg can be noreg, if no temps are available.
549 // Updates the sub's secondary super cache as necessary.
550 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
551 void check_klass_subtype_slow_path(Register sub_klass,
552 Register super_klass,
553 Register temp_reg,
554 Register temp2_reg,
555 Label* L_success,
556 Label* L_failure,
557 bool set_cond_codes = false);
558
559 // Simplified, combined version, good for typical uses.
560 // Falls through on failure.
561 void check_klass_subtype(Register sub_klass,
562 Register super_klass,
563 Register temp_reg,
564 Label& L_success);
565
566 // method handles (JSR 292)
567 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
568
569 //----
570 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
571
572 // Debugging
573
574 // only if +VerifyOops
575 // TODO: Make these macros with file and line like sparc version!
576 void verify_oop(Register reg, const char* s = "broken oop");
577 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
578
579 // TODO: verify method and klass metadata (compare against vptr?)
580 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
581 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
582
583 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
584 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
585
586 // only if +VerifyFPU
587 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
588
589 // Verify or restore cpu control state after JNI call
590 void restore_cpu_control_state_after_jni();
591
592 // prints msg, dumps registers and stops execution
593 void stop(const char* msg);
594
595 // prints msg and continues
596 void warn(const char* msg);
597
598 // dumps registers and other state
599 void print_state();
600
601 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
602 static void debug64(char* msg, int64_t pc, int64_t regs[]);
603 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
604 static void print_state64(int64_t pc, int64_t regs[]);
605
606 void os_breakpoint();
607
608 void untested() { stop("untested"); }
609
610 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
611
612 void should_not_reach_here() { stop("should not reach here"); }
613
614 void print_CPU_state();
615
616 // Stack overflow checking
617 void bang_stack_with_offset(int offset) {
618 // stack grows down, caller passes positive offset
619 assert(offset > 0, "must bang with negative offset");
620 movl(Address(rsp, (-offset)), rax);
621 }
622
623 // Writes to stack successive pages until offset reached to check for
624 // stack overflow + shadow pages. Also, clobbers tmp
625 void bang_stack_size(Register size, Register tmp);
626
627 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
628 Register tmp,
629 int offset);
630
631 // Support for serializing memory accesses between threads
632 void serialize_memory(Register thread, Register tmp);
633
634 void verify_tlab();
635
636 // Biased locking support
637 // lock_reg and obj_reg must be loaded up with the appropriate values.
638 // swap_reg must be rax, and is killed.
639 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
640 // be killed; if not supplied, push/pop will be used internally to
641 // allocate a temporary (inefficient, avoid if possible).
642 // Optional slow case is for implementations (interpreter and C1) which branch to
643 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
644 // Returns offset of first potentially-faulting instruction for null
645 // check info (currently consumed only by C1). If
646 // swap_reg_contains_mark is true then returns -1 as it is assumed
647 // the calling code has already passed any potential faults.
648 int biased_locking_enter(Register lock_reg, Register obj_reg,
649 Register swap_reg, Register tmp_reg,
650 bool swap_reg_contains_mark,
651 Label& done, Label* slow_case = NULL,
652 BiasedLockingCounters* counters = NULL);
653 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
654
655
656 Condition negate_condition(Condition cond);
657
658 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
659 // operands. In general the names are modified to avoid hiding the instruction in Assembler
660 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
661 // here in MacroAssembler. The major exception to this rule is call
662
663 // Arithmetics
664
665
666 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
667 void addptr(Address dst, Register src);
668
669 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
670 void addptr(Register dst, int32_t src);
671 void addptr(Register dst, Register src);
672 void addptr(Register dst, RegisterOrConstant src) {
673 if (src.is_constant()) addptr(dst, (int) src.as_constant());
674 else addptr(dst, src.as_register());
675 }
676
677 void andptr(Register dst, int32_t src);
678 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
679
680 void cmp8(AddressLiteral src1, int imm);
681
682 // renamed to drag out the casting of address to int32_t/intptr_t
683 void cmp32(Register src1, int32_t imm);
684
685 void cmp32(AddressLiteral src1, int32_t imm);
686 // compare reg - mem, or reg - &mem
687 void cmp32(Register src1, AddressLiteral src2);
688
689 void cmp32(Register src1, Address src2);
690
691 #ifndef _LP64
692 void cmpklass(Address dst, Metadata* obj);
693 void cmpklass(Register dst, Metadata* obj);
694 void cmpoop(Address dst, jobject obj);
695 void cmpoop(Register dst, jobject obj);
696 #endif // _LP64
697
698 // NOTE src2 must be the lval. This is NOT an mem-mem compare
699 void cmpptr(Address src1, AddressLiteral src2);
700
701 void cmpptr(Register src1, AddressLiteral src2);
702
703 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
704 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
705 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
706
707 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
708 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
709
710 // cmp64 to avoild hiding cmpq
711 void cmp64(Register src1, AddressLiteral src);
712
713 void cmpxchgptr(Register reg, Address adr);
714
715 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
716
717
718 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
719
720
721 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
722
723 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
724
725 void shlptr(Register dst, int32_t shift);
726 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
727
728 void shrptr(Register dst, int32_t shift);
729 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
730
731 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
732 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
733
734 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
735
736 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
737 void subptr(Register dst, int32_t src);
738 // Force generation of a 4 byte immediate value even if it fits into 8bit
739 void subptr_imm32(Register dst, int32_t src);
740 void subptr(Register dst, Register src);
741 void subptr(Register dst, RegisterOrConstant src) {
742 if (src.is_constant()) subptr(dst, (int) src.as_constant());
743 else subptr(dst, src.as_register());
744 }
745
746 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
747 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
748
749 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
750 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
751
752 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
753
754
755
756 // Helper functions for statistics gathering.
757 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
758 void cond_inc32(Condition cond, AddressLiteral counter_addr);
759 // Unconditional atomic increment.
760 void atomic_incl(AddressLiteral counter_addr);
761
762 void lea(Register dst, AddressLiteral adr);
763 void lea(Address dst, AddressLiteral adr);
764 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
765
766 void leal32(Register dst, Address src) { leal(dst, src); }
767
768 // Import other testl() methods from the parent class or else
769 // they will be hidden by the following overriding declaration.
770 using Assembler::testl;
771 void testl(Register dst, AddressLiteral src);
772
773 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
774 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
775 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
776 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
777
778 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
779 void testptr(Register src1, Register src2);
780
781 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
782 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
783
784 // Calls
785
786 void call(Label& L, relocInfo::relocType rtype);
787 void call(Register entry);
788
789 // NOTE: this call tranfers to the effective address of entry NOT
790 // the address contained by entry. This is because this is more natural
791 // for jumps/calls.
792 void call(AddressLiteral entry);
793
794 // Emit the CompiledIC call idiom
795 void ic_call(address entry);
796
797 // Jumps
798
799 // NOTE: these jumps tranfer to the effective address of dst NOT
800 // the address contained by dst. This is because this is more natural
801 // for jumps/calls.
802 void jump(AddressLiteral dst);
803 void jump_cc(Condition cc, AddressLiteral dst);
804
805 // 32bit can do a case table jump in one instruction but we no longer allow the base
806 // to be installed in the Address class. This jump will tranfers to the address
807 // contained in the location described by entry (not the address of entry)
808 void jump(ArrayAddress entry);
809
810 // Floating
811
812 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
813 void andpd(XMMRegister dst, AddressLiteral src);
814
815 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
816 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
817 void andps(XMMRegister dst, AddressLiteral src);
818
819 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
820 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
821 void comiss(XMMRegister dst, AddressLiteral src);
822
823 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
824 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
825 void comisd(XMMRegister dst, AddressLiteral src);
826
827 void fadd_s(Address src) { Assembler::fadd_s(src); }
828 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
829
830 void fldcw(Address src) { Assembler::fldcw(src); }
831 void fldcw(AddressLiteral src);
832
833 void fld_s(int index) { Assembler::fld_s(index); }
834 void fld_s(Address src) { Assembler::fld_s(src); }
835 void fld_s(AddressLiteral src);
836
837 void fld_d(Address src) { Assembler::fld_d(src); }
838 void fld_d(AddressLiteral src);
839
840 void fld_x(Address src) { Assembler::fld_x(src); }
841 void fld_x(AddressLiteral src);
842
843 void fmul_s(Address src) { Assembler::fmul_s(src); }
844 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
845
846 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
847 void ldmxcsr(AddressLiteral src);
848
849 // compute pow(x,y) and exp(x) with x86 instructions. Don't cover
850 // all corner cases and may result in NaN and require fallback to a
851 // runtime call.
852 void fast_pow();
853 void fast_exp();
854 void increase_precision();
855 void restore_precision();
856
857 // computes exp(x). Fallback to runtime call included.
858 void exp_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(true, num_fpu_regs_in_use); }
859 // computes pow(x,y). Fallback to runtime call included.
860 void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(false, num_fpu_regs_in_use); }
861
862 private:
863
864 // call runtime as a fallback for trig functions and pow/exp.
865 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
866
867 // computes 2^(Ylog2X); Ylog2X in ST(0)
868 void pow_exp_core_encoding();
869
870 // computes pow(x,y) or exp(x). Fallback to runtime call included.
871 void pow_or_exp(bool is_exp, int num_fpu_regs_in_use);
872
873 // these are private because users should be doing movflt/movdbl
874
875 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
876 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
877 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
878 void movss(XMMRegister dst, AddressLiteral src);
879
880 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
881 void movlpd(XMMRegister dst, AddressLiteral src);
882
883 public:
884
885 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
886 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
887 void addsd(XMMRegister dst, AddressLiteral src);
888
889 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
890 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
891 void addss(XMMRegister dst, AddressLiteral src);
892
893 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
894 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
895 void divsd(XMMRegister dst, AddressLiteral src);
896
897 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
898 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
899 void divss(XMMRegister dst, AddressLiteral src);
900
901 // Move Unaligned Double Quadword
902 void movdqu(Address dst, XMMRegister src) { Assembler::movdqu(dst, src); }
903 void movdqu(XMMRegister dst, Address src) { Assembler::movdqu(dst, src); }
904 void movdqu(XMMRegister dst, XMMRegister src) { Assembler::movdqu(dst, src); }
905 void movdqu(XMMRegister dst, AddressLiteral src);
906
907 // Move Aligned Double Quadword
908 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
909 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
910 void movdqa(XMMRegister dst, AddressLiteral src);
911
912 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
913 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
914 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
915 void movsd(XMMRegister dst, AddressLiteral src);
916
917 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
918 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
919 void mulsd(XMMRegister dst, AddressLiteral src);
920
921 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
922 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
923 void mulss(XMMRegister dst, AddressLiteral src);
924
925 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
926 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
927 void sqrtsd(XMMRegister dst, AddressLiteral src);
928
929 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
930 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
931 void sqrtss(XMMRegister dst, AddressLiteral src);
932
933 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
934 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
935 void subsd(XMMRegister dst, AddressLiteral src);
936
937 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
938 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
939 void subss(XMMRegister dst, AddressLiteral src);
940
941 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
942 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
943 void ucomiss(XMMRegister dst, AddressLiteral src);
944
945 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
946 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
947 void ucomisd(XMMRegister dst, AddressLiteral src);
948
949 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
950 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
951 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
952 void xorpd(XMMRegister dst, AddressLiteral src);
953
954 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
955 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
956 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
957 void xorps(XMMRegister dst, AddressLiteral src);
958
959 // Shuffle Bytes
960 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
961 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
962 void pshufb(XMMRegister dst, AddressLiteral src);
963 // AVX 3-operands instructions
964
965 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
966 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
967 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
968
969 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
970 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
971 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
972
973 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
974 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
975 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
976
977 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
978 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
979 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
980
981 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
982 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
983 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
984
985 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
986 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
987 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
988
989 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
990 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
991 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
992
993 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
994 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
995 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
996
997 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
998 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
999 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1000
1001 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1002 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1003 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1004
1005 // AVX Vector instructions
1006
1007 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
1008 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
1009 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
1010
1011 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
1012 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
1013 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
1014
1015 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1016 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
1017 Assembler::vpxor(dst, nds, src, vector256);
1018 else
1019 Assembler::vxorpd(dst, nds, src, vector256);
1020 }
1021 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1022 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
1023 Assembler::vpxor(dst, nds, src, vector256);
1024 else
1025 Assembler::vxorpd(dst, nds, src, vector256);
1026 }
1027
1028 // Simple version for AVX2 256bit vectors
1029 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1030 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1031
1032 // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector.
1033 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1034 if (UseAVX > 1) // vinserti128h is available only in AVX2
1035 Assembler::vinserti128h(dst, nds, src);
1036 else
1037 Assembler::vinsertf128h(dst, nds, src);
1038 }
1039
1040 // Carry-Less Multiplication Quadword
1041 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1042 // 0x00 - multiply lower 64 bits [0:63]
1043 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1044 }
1045 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1046 // 0x11 - multiply upper 64 bits [64:127]
1047 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1048 }
1049
1050 // Data
1051
1052 void cmov32( Condition cc, Register dst, Address src);
1053 void cmov32( Condition cc, Register dst, Register src);
1054
1055 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1056
1057 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1058 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1059
1060 void movoop(Register dst, jobject obj);
1061 void movoop(Address dst, jobject obj);
1062
1063 void mov_metadata(Register dst, Metadata* obj);
1064 void mov_metadata(Address dst, Metadata* obj);
1065
1066 void movptr(ArrayAddress dst, Register src);
1067 // can this do an lea?
1068 void movptr(Register dst, ArrayAddress src);
1069
1070 void movptr(Register dst, Address src);
1071
1072 void movptr(Register dst, AddressLiteral src);
1073
1074 void movptr(Register dst, intptr_t src);
1075 void movptr(Register dst, Register src);
1076 void movptr(Address dst, intptr_t src);
1077
1078 void movptr(Address dst, Register src);
1079
1080 void movptr(Register dst, RegisterOrConstant src) {
1081 if (src.is_constant()) movptr(dst, src.as_constant());
1082 else movptr(dst, src.as_register());
1083 }
1084
1085 #ifdef _LP64
1086 // Generally the next two are only used for moving NULL
1087 // Although there are situations in initializing the mark word where
1088 // they could be used. They are dangerous.
1089
1090 // They only exist on LP64 so that int32_t and intptr_t are not the same
1091 // and we have ambiguous declarations.
1092
1093 void movptr(Address dst, int32_t imm32);
1094 void movptr(Register dst, int32_t imm32);
1095 #endif // _LP64
1096
1097 // to avoid hiding movl
1098 void mov32(AddressLiteral dst, Register src);
1099 void mov32(Register dst, AddressLiteral src);
1100
1101 // to avoid hiding movb
1102 void movbyte(ArrayAddress dst, int src);
1103
1104 // Import other mov() methods from the parent class or else
1105 // they will be hidden by the following overriding declaration.
1106 using Assembler::movdl;
1107 using Assembler::movq;
1108 void movdl(XMMRegister dst, AddressLiteral src);
1109 void movq(XMMRegister dst, AddressLiteral src);
1110
1111 // Can push value or effective address
1112 void pushptr(AddressLiteral src);
1113
1114 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1115 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1116
1117 void pushoop(jobject obj);
1118 void pushklass(Metadata* obj);
1119
1120 // sign extend as need a l to ptr sized element
1121 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1122 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1123
1124 // C2 compiled method's prolog code.
1125 void verified_entry(int framesize, bool stack_bang, bool fp_mode_24b);
1126
1127 // clear memory of size 'cnt' qwords, starting at 'base'.
1128 void clear_mem(Register base, Register cnt, Register rtmp);
1129
1130 // IndexOf strings.
1131 // Small strings are loaded through stack if they cross page boundary.
1132 void string_indexof(Register str1, Register str2,
1133 Register cnt1, Register cnt2,
1134 int int_cnt2, Register result,
1135 XMMRegister vec, Register tmp);
1136
1137 // IndexOf for constant substrings with size >= 8 elements
1138 // which don't need to be loaded through stack.
1139 void string_indexofC8(Register str1, Register str2,
1140 Register cnt1, Register cnt2,
1141 int int_cnt2, Register result,
1142 XMMRegister vec, Register tmp);
1143
1144 // Smallest code: we don't need to load through stack,
1145 // check string tail.
1146
1147 // Compare strings.
1148 void string_compare(Register str1, Register str2,
1149 Register cnt1, Register cnt2, Register result,
1150 XMMRegister vec1);
1151
1152 // Compare char[] arrays.
1153 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1154 Register limit, Register result, Register chr,
1155 XMMRegister vec1, XMMRegister vec2);
1156
1157 // Fill primitive arrays
1158 void generate_fill(BasicType t, bool aligned,
1159 Register to, Register value, Register count,
1160 Register rtmp, XMMRegister xtmp);
1161
1162 void encode_iso_array(Register src, Register dst, Register len,
1163 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1164 XMMRegister tmp4, Register tmp5, Register result);
1165
1166 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1167 void update_byte_crc32(Register crc, Register val, Register table);
1168 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1169 // Fold 128-bit data chunk
1170 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1171 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1172 // Fold 8-bit data
1173 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1174 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1175
1176 #undef VIRTUAL
1177
1178 };
1179
1180 /**
1181 * class SkipIfEqual:
1182 *
1183 * Instantiating this class will result in assembly code being output that will
1184 * jump around any code emitted between the creation of the instance and it's
1185 * automatic destruction at the end of a scope block, depending on the value of
1186 * the flag passed to the constructor, which will be checked at run-time.
1187 */
1188 class SkipIfEqual {
1189 private:
1190 MacroAssembler* _masm;
1191 Label _label;
1192
1193 public:
1194 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1195 ~SkipIfEqual();
1196 };
1197
1198 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP