1 //
2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_resets_size() {
232 int size = 0;
233 Compile* C = Compile::current();
234 if (C->in_24_bit_fp_mode()) {
235 size += 6; // fldcw
236 }
237 if (C->max_vector_size() > 16) {
238 size += 3; // vzeroupper
239 }
240 return size;
241 }
242
243 static int preserve_SP_size() {
244 return 2; // op, rm(reg/reg)
245 }
246
247 // !!!!! Special hack to get all type of calls to specify the byte offset
248 // from the start of the call to the point where the return address
249 // will point.
250 int MachCallStaticJavaNode::ret_addr_offset() {
251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
252 if (_method_handle_invoke)
253 offset += preserve_SP_size();
254 return offset;
255 }
256
257 int MachCallDynamicJavaNode::ret_addr_offset() {
258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
259 }
260
261 static int sizeof_FFree_Float_Stack_All = -1;
262
263 int MachCallRuntimeNode::ret_addr_offset() {
264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
266 }
267
268 // Indicate if the safepoint node needs the polling page as an input.
269 // Since x86 does have absolute addressing, it doesn't.
270 bool SafePointNode::needs_polling_address_input() {
271 return false;
272 }
273
274 //
275 // Compute padding required for nodes which need alignment
276 //
277
278 // The address of the call instruction needs to be 4-byte aligned to
279 // ensure that it does not span a cache line so that it can be patched.
280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
281 current_offset += pre_call_resets_size(); // skip fldcw, if any
282 current_offset += 1; // skip call opcode byte
283 return round_to(current_offset, alignment_required()) - current_offset;
284 }
285
286 // The address of the call instruction needs to be 4-byte aligned to
287 // ensure that it does not span a cache line so that it can be patched.
288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
289 current_offset += pre_call_resets_size(); // skip fldcw, if any
290 current_offset += preserve_SP_size(); // skip mov rbp, rsp
291 current_offset += 1; // skip call opcode byte
292 return round_to(current_offset, alignment_required()) - current_offset;
293 }
294
295 // The address of the call instruction needs to be 4-byte aligned to
296 // ensure that it does not span a cache line so that it can be patched.
297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
298 current_offset += pre_call_resets_size(); // skip fldcw, if any
299 current_offset += 5; // skip MOV instruction
300 current_offset += 1; // skip call opcode byte
301 return round_to(current_offset, alignment_required()) - current_offset;
302 }
303
304 // EMIT_RM()
305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_CC()
311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
312 unsigned char c = (unsigned char)( f1 | f2 );
313 cbuf.insts()->emit_int8(c);
314 }
315
316 // EMIT_OPCODE()
317 void emit_opcode(CodeBuffer &cbuf, int code) {
318 cbuf.insts()->emit_int8((unsigned char) code);
319 }
320
321 // EMIT_OPCODE() w/ relocation information
322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
323 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
324 emit_opcode(cbuf, code);
325 }
326
327 // EMIT_D8()
328 void emit_d8(CodeBuffer &cbuf, int d8) {
329 cbuf.insts()->emit_int8((unsigned char) d8);
330 }
331
332 // EMIT_D16()
333 void emit_d16(CodeBuffer &cbuf, int d16) {
334 cbuf.insts()->emit_int16(d16);
335 }
336
337 // EMIT_D32()
338 void emit_d32(CodeBuffer &cbuf, int d32) {
339 cbuf.insts()->emit_int32(d32);
340 }
341
342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
344 int format) {
345 cbuf.relocate(cbuf.insts_mark(), reloc, format);
346 cbuf.insts()->emit_int32(d32);
347 }
348
349 // emit 32 bit value and construct relocation entry from RelocationHolder
350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
351 int format) {
352 #ifdef ASSERT
353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
354 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
355 }
356 #endif
357 cbuf.relocate(cbuf.insts_mark(), rspec, format);
358 cbuf.insts()->emit_int32(d32);
359 }
360
361 // Access stack slot for load or store
362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
364 if( -128 <= disp && disp <= 127 ) {
365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
367 emit_d8 (cbuf, disp); // Displacement // R/M byte
368 } else {
369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
371 emit_d32(cbuf, disp); // Displacement // R/M byte
372 }
373 }
374
375 // rRegI ereg, memory mem) %{ // emit_reg_mem
376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
377 // There is no index & no scale, use form without SIB byte
378 if ((index == 0x4) &&
379 (scale == 0) && (base != ESP_enc)) {
380 // If no displacement, mode is 0x0; unless base is [EBP]
381 if ( (displace == 0) && (base != EBP_enc) ) {
382 emit_rm(cbuf, 0x0, reg_encoding, base);
383 }
384 else { // If 8-bit displacement, mode 0x1
385 if ((displace >= -128) && (displace <= 127)
386 && (disp_reloc == relocInfo::none) ) {
387 emit_rm(cbuf, 0x1, reg_encoding, base);
388 emit_d8(cbuf, displace);
389 }
390 else { // If 32-bit displacement
391 if (base == -1) { // Special flag for absolute address
392 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
393 // (manual lies; no SIB needed here)
394 if ( disp_reloc != relocInfo::none ) {
395 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
396 } else {
397 emit_d32 (cbuf, displace);
398 }
399 }
400 else { // Normal base + offset
401 emit_rm(cbuf, 0x2, reg_encoding, base);
402 if ( disp_reloc != relocInfo::none ) {
403 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
404 } else {
405 emit_d32 (cbuf, displace);
406 }
407 }
408 }
409 }
410 }
411 else { // Else, encode with the SIB byte
412 // If no displacement, mode is 0x0; unless base is [EBP]
413 if (displace == 0 && (base != EBP_enc)) { // If no displacement
414 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 }
417 else { // If 8-bit displacement, mode 0x1
418 if ((displace >= -128) && (displace <= 127)
419 && (disp_reloc == relocInfo::none) ) {
420 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, base);
422 emit_d8(cbuf, displace);
423 }
424 else { // If 32-bit displacement
425 if (base == 0x04 ) {
426 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
427 emit_rm(cbuf, scale, index, 0x04);
428 } else {
429 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
430 emit_rm(cbuf, scale, index, base);
431 }
432 if ( disp_reloc != relocInfo::none ) {
433 emit_d32_reloc(cbuf, displace, disp_reloc, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441
442
443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
444 if( dst_encoding == src_encoding ) {
445 // reg-reg copy, use an empty encoding
446 } else {
447 emit_opcode( cbuf, 0x8B );
448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
449 }
450 }
451
452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
453 Label exit;
454 __ jccb(Assembler::noParity, exit);
455 __ pushf();
456 //
457 // comiss/ucomiss instructions set ZF,PF,CF flags and
458 // zero OF,AF,SF for NaN values.
459 // Fixup flags by zeroing ZF,PF so that compare of NaN
460 // values returns 'less than' result (CF is set).
461 // Leave the rest of flags unchanged.
462 //
463 // 7 6 5 4 3 2 1 0
464 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
465 // 0 0 1 0 1 0 1 1 (0x2B)
466 //
467 __ andl(Address(rsp, 0), 0xffffff2b);
468 __ popf();
469 __ bind(exit);
470 }
471
472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
473 Label done;
474 __ movl(dst, -1);
475 __ jcc(Assembler::parity, done);
476 __ jcc(Assembler::below, done);
477 __ setb(Assembler::notEqual, dst);
478 __ movzbl(dst, dst);
479 __ bind(done);
480 }
481
482
483 //=============================================================================
484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
485
486 int Compile::ConstantTable::calculate_table_base_offset() const {
487 return 0; // absolute addressing, no offset
488 }
489
490 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
491 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
492 ShouldNotReachHere();
493 }
494
495 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
496 // Empty encoding
497 }
498
499 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
500 return 0;
501 }
502
503 #ifndef PRODUCT
504 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
505 st->print("# MachConstantBaseNode (empty encoding)");
506 }
507 #endif
508
509
510 //=============================================================================
511 #ifndef PRODUCT
512 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
513 Compile* C = ra_->C;
514
515 int framesize = C->frame_slots() << LogBytesPerInt;
516 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
517 // Remove wordSize for return addr which is already pushed.
518 framesize -= wordSize;
519
520 if (C->need_stack_bang(framesize)) {
521 framesize -= wordSize;
522 st->print("# stack bang");
523 st->print("\n\t");
524 st->print("PUSH EBP\t# Save EBP");
525 if (framesize) {
526 st->print("\n\t");
527 st->print("SUB ESP, #%d\t# Create frame",framesize);
528 }
529 } else {
530 st->print("SUB ESP, #%d\t# Create frame",framesize);
531 st->print("\n\t");
532 framesize -= wordSize;
533 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
534 }
535
536 if (VerifyStackAtCalls) {
537 st->print("\n\t");
538 framesize -= wordSize;
539 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
540 }
541
542 if( C->in_24_bit_fp_mode() ) {
543 st->print("\n\t");
544 st->print("FLDCW \t# load 24 bit fpu control word");
545 }
546 if (UseSSE >= 2 && VerifyFPU) {
547 st->print("\n\t");
548 st->print("# verify FPU stack (must be clean on entry)");
549 }
550
551 #ifdef ASSERT
552 if (VerifyStackAtCalls) {
553 st->print("\n\t");
554 st->print("# stack alignment check");
555 }
556 #endif
557 st->cr();
558 }
559 #endif
560
561
562 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
563 Compile* C = ra_->C;
564 MacroAssembler _masm(&cbuf);
565
566 int framesize = C->frame_slots() << LogBytesPerInt;
567
568 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
569
570 C->set_frame_complete(cbuf.insts_size());
571
572 if (C->has_mach_constant_base_node()) {
573 // NOTE: We set the table base offset here because users might be
574 // emitted before MachConstantBaseNode.
575 Compile::ConstantTable& constant_table = C->constant_table();
576 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
577 }
578 }
579
580 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
581 return MachNode::size(ra_); // too many variables; just compute it the hard way
582 }
583
584 int MachPrologNode::reloc() const {
585 return 0; // a large enough number
586 }
587
588 //=============================================================================
589 #ifndef PRODUCT
590 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
591 Compile *C = ra_->C;
592 int framesize = C->frame_slots() << LogBytesPerInt;
593 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
594 // Remove two words for return addr and rbp,
595 framesize -= 2*wordSize;
596
597 if (C->max_vector_size() > 16) {
598 st->print("VZEROUPPER");
599 st->cr(); st->print("\t");
600 }
601 if (C->in_24_bit_fp_mode()) {
602 st->print("FLDCW standard control word");
603 st->cr(); st->print("\t");
604 }
605 if (framesize) {
606 st->print("ADD ESP,%d\t# Destroy frame",framesize);
607 st->cr(); st->print("\t");
608 }
609 st->print_cr("POPL EBP"); st->print("\t");
610 if (do_polling() && C->is_method_compilation()) {
611 st->print("TEST PollPage,EAX\t! Poll Safepoint");
612 st->cr(); st->print("\t");
613 }
614 }
615 #endif
616
617 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
618 Compile *C = ra_->C;
619
620 if (C->max_vector_size() > 16) {
621 // Clear upper bits of YMM registers when current compiled code uses
622 // wide vectors to avoid AVX <-> SSE transition penalty during call.
623 MacroAssembler masm(&cbuf);
624 masm.vzeroupper();
625 }
626 // If method set FPU control word, restore to standard control word
627 if (C->in_24_bit_fp_mode()) {
628 MacroAssembler masm(&cbuf);
629 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
630 }
631
632 int framesize = C->frame_slots() << LogBytesPerInt;
633 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
634 // Remove two words for return addr and rbp,
635 framesize -= 2*wordSize;
636
637 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
638
639 if (framesize >= 128) {
640 emit_opcode(cbuf, 0x81); // add SP, #framesize
641 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
642 emit_d32(cbuf, framesize);
643 } else if (framesize) {
644 emit_opcode(cbuf, 0x83); // add SP, #framesize
645 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
646 emit_d8(cbuf, framesize);
647 }
648
649 emit_opcode(cbuf, 0x58 | EBP_enc);
650
651 if (do_polling() && C->is_method_compilation()) {
652 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
653 emit_opcode(cbuf,0x85);
654 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
655 emit_d32(cbuf, (intptr_t)os::get_polling_page());
656 }
657 }
658
659 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
660 Compile *C = ra_->C;
661 // If method set FPU control word, restore to standard control word
662 int size = C->in_24_bit_fp_mode() ? 6 : 0;
663 if (C->max_vector_size() > 16) size += 3; // vzeroupper
664 if (do_polling() && C->is_method_compilation()) size += 6;
665
666 int framesize = C->frame_slots() << LogBytesPerInt;
667 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
668 // Remove two words for return addr and rbp,
669 framesize -= 2*wordSize;
670
671 size++; // popl rbp,
672
673 if (framesize >= 128) {
674 size += 6;
675 } else {
676 size += framesize ? 3 : 0;
677 }
678 return size;
679 }
680
681 int MachEpilogNode::reloc() const {
682 return 0; // a large enough number
683 }
684
685 const Pipeline * MachEpilogNode::pipeline() const {
686 return MachNode::pipeline_class();
687 }
688
689 int MachEpilogNode::safepoint_offset() const { return 0; }
690
691 //=============================================================================
692
693 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
694 static enum RC rc_class( OptoReg::Name reg ) {
695
696 if( !OptoReg::is_valid(reg) ) return rc_bad;
697 if (OptoReg::is_stack(reg)) return rc_stack;
698
699 VMReg r = OptoReg::as_VMReg(reg);
700 if (r->is_Register()) return rc_int;
701 if (r->is_FloatRegister()) {
702 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
703 return rc_float;
704 }
705 assert(r->is_XMMRegister(), "must be");
706 return rc_xmm;
707 }
708
709 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
710 int opcode, const char *op_str, int size, outputStream* st ) {
711 if( cbuf ) {
712 emit_opcode (*cbuf, opcode );
713 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
714 #ifndef PRODUCT
715 } else if( !do_size ) {
716 if( size != 0 ) st->print("\n\t");
717 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
718 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
719 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
720 } else { // FLD, FST, PUSH, POP
721 st->print("%s [ESP + #%d]",op_str,offset);
722 }
723 #endif
724 }
725 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
726 return size+3+offset_size;
727 }
728
729 // Helper for XMM registers. Extra opcode bits, limited syntax.
730 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
731 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
732 if (cbuf) {
733 MacroAssembler _masm(cbuf);
734 if (reg_lo+1 == reg_hi) { // double move?
735 if (is_load) {
736 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
737 } else {
738 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
739 }
740 } else {
741 if (is_load) {
742 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
743 } else {
744 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
745 }
746 }
747 #ifndef PRODUCT
748 } else if (!do_size) {
749 if (size != 0) st->print("\n\t");
750 if (reg_lo+1 == reg_hi) { // double move?
751 if (is_load) st->print("%s %s,[ESP + #%d]",
752 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
753 Matcher::regName[reg_lo], offset);
754 else st->print("MOVSD [ESP + #%d],%s",
755 offset, Matcher::regName[reg_lo]);
756 } else {
757 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
758 Matcher::regName[reg_lo], offset);
759 else st->print("MOVSS [ESP + #%d],%s",
760 offset, Matcher::regName[reg_lo]);
761 }
762 #endif
763 }
764 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
765 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
766 return size+5+offset_size;
767 }
768
769
770 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
771 int src_hi, int dst_hi, int size, outputStream* st ) {
772 if (cbuf) {
773 MacroAssembler _masm(cbuf);
774 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
775 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
776 as_XMMRegister(Matcher::_regEncode[src_lo]));
777 } else {
778 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
779 as_XMMRegister(Matcher::_regEncode[src_lo]));
780 }
781 #ifndef PRODUCT
782 } else if (!do_size) {
783 if (size != 0) st->print("\n\t");
784 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
785 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
786 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
787 } else {
788 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
789 }
790 } else {
791 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
792 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
793 } else {
794 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
795 }
796 }
797 #endif
798 }
799 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
800 // Only MOVAPS SSE prefix uses 1 byte.
801 int sz = 4;
802 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
803 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
804 return size + sz;
805 }
806
807 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
808 int src_hi, int dst_hi, int size, outputStream* st ) {
809 // 32-bit
810 if (cbuf) {
811 MacroAssembler _masm(cbuf);
812 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
813 as_Register(Matcher::_regEncode[src_lo]));
814 #ifndef PRODUCT
815 } else if (!do_size) {
816 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
817 #endif
818 }
819 return 4;
820 }
821
822
823 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
824 int src_hi, int dst_hi, int size, outputStream* st ) {
825 // 32-bit
826 if (cbuf) {
827 MacroAssembler _masm(cbuf);
828 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
829 as_XMMRegister(Matcher::_regEncode[src_lo]));
830 #ifndef PRODUCT
831 } else if (!do_size) {
832 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
833 #endif
834 }
835 return 4;
836 }
837
838 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
839 if( cbuf ) {
840 emit_opcode(*cbuf, 0x8B );
841 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
842 #ifndef PRODUCT
843 } else if( !do_size ) {
844 if( size != 0 ) st->print("\n\t");
845 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
846 #endif
847 }
848 return size+2;
849 }
850
851 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
852 int offset, int size, outputStream* st ) {
853 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
854 if( cbuf ) {
855 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
856 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
857 #ifndef PRODUCT
858 } else if( !do_size ) {
859 if( size != 0 ) st->print("\n\t");
860 st->print("FLD %s",Matcher::regName[src_lo]);
861 #endif
862 }
863 size += 2;
864 }
865
866 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
867 const char *op_str;
868 int op;
869 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
870 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
871 op = 0xDD;
872 } else { // 32-bit store
873 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
874 op = 0xD9;
875 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
876 }
877
878 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
879 }
880
881 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
882 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
883 int src_hi, int dst_hi, uint ireg, outputStream* st);
884
885 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
886 int stack_offset, int reg, uint ireg, outputStream* st);
887
888 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
889 int dst_offset, uint ireg, outputStream* st) {
890 int calc_size = 0;
891 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
892 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
893 switch (ireg) {
894 case Op_VecS:
895 calc_size = 3+src_offset_size + 3+dst_offset_size;
896 break;
897 case Op_VecD:
898 calc_size = 3+src_offset_size + 3+dst_offset_size;
899 src_offset += 4;
900 dst_offset += 4;
901 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
902 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
903 calc_size += 3+src_offset_size + 3+dst_offset_size;
904 break;
905 case Op_VecX:
906 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
907 break;
908 case Op_VecY:
909 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
910 break;
911 default:
912 ShouldNotReachHere();
913 }
914 if (cbuf) {
915 MacroAssembler _masm(cbuf);
916 int offset = __ offset();
917 switch (ireg) {
918 case Op_VecS:
919 __ pushl(Address(rsp, src_offset));
920 __ popl (Address(rsp, dst_offset));
921 break;
922 case Op_VecD:
923 __ pushl(Address(rsp, src_offset));
924 __ popl (Address(rsp, dst_offset));
925 __ pushl(Address(rsp, src_offset+4));
926 __ popl (Address(rsp, dst_offset+4));
927 break;
928 case Op_VecX:
929 __ movdqu(Address(rsp, -16), xmm0);
930 __ movdqu(xmm0, Address(rsp, src_offset));
931 __ movdqu(Address(rsp, dst_offset), xmm0);
932 __ movdqu(xmm0, Address(rsp, -16));
933 break;
934 case Op_VecY:
935 __ vmovdqu(Address(rsp, -32), xmm0);
936 __ vmovdqu(xmm0, Address(rsp, src_offset));
937 __ vmovdqu(Address(rsp, dst_offset), xmm0);
938 __ vmovdqu(xmm0, Address(rsp, -32));
939 break;
940 default:
941 ShouldNotReachHere();
942 }
943 int size = __ offset() - offset;
944 assert(size == calc_size, "incorrect size calculattion");
945 return size;
946 #ifndef PRODUCT
947 } else if (!do_size) {
948 switch (ireg) {
949 case Op_VecS:
950 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
951 "popl [rsp + #%d]",
952 src_offset, dst_offset);
953 break;
954 case Op_VecD:
955 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
956 "popq [rsp + #%d]\n\t"
957 "pushl [rsp + #%d]\n\t"
958 "popq [rsp + #%d]",
959 src_offset, dst_offset, src_offset+4, dst_offset+4);
960 break;
961 case Op_VecX:
962 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
963 "movdqu xmm0, [rsp + #%d]\n\t"
964 "movdqu [rsp + #%d], xmm0\n\t"
965 "movdqu xmm0, [rsp - #16]",
966 src_offset, dst_offset);
967 break;
968 case Op_VecY:
969 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
970 "vmovdqu xmm0, [rsp + #%d]\n\t"
971 "vmovdqu [rsp + #%d], xmm0\n\t"
972 "vmovdqu xmm0, [rsp - #32]",
973 src_offset, dst_offset);
974 break;
975 default:
976 ShouldNotReachHere();
977 }
978 #endif
979 }
980 return calc_size;
981 }
982
983 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
984 // Get registers to move
985 OptoReg::Name src_second = ra_->get_reg_second(in(1));
986 OptoReg::Name src_first = ra_->get_reg_first(in(1));
987 OptoReg::Name dst_second = ra_->get_reg_second(this );
988 OptoReg::Name dst_first = ra_->get_reg_first(this );
989
990 enum RC src_second_rc = rc_class(src_second);
991 enum RC src_first_rc = rc_class(src_first);
992 enum RC dst_second_rc = rc_class(dst_second);
993 enum RC dst_first_rc = rc_class(dst_first);
994
995 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
996
997 // Generate spill code!
998 int size = 0;
999
1000 if( src_first == dst_first && src_second == dst_second )
1001 return size; // Self copy, no move
1002
1003 if (bottom_type()->isa_vect() != NULL) {
1004 uint ireg = ideal_reg();
1005 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1006 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1007 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1008 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1009 // mem -> mem
1010 int src_offset = ra_->reg2offset(src_first);
1011 int dst_offset = ra_->reg2offset(dst_first);
1012 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1013 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1014 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1015 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1016 int stack_offset = ra_->reg2offset(dst_first);
1017 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1018 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1019 int stack_offset = ra_->reg2offset(src_first);
1020 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1021 } else {
1022 ShouldNotReachHere();
1023 }
1024 }
1025
1026 // --------------------------------------
1027 // Check for mem-mem move. push/pop to move.
1028 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1029 if( src_second == dst_first ) { // overlapping stack copy ranges
1030 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1031 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1032 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1033 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1034 }
1035 // move low bits
1036 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1037 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1038 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1039 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1040 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1041 }
1042 return size;
1043 }
1044
1045 // --------------------------------------
1046 // Check for integer reg-reg copy
1047 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1048 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1049
1050 // Check for integer store
1051 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1052 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1053
1054 // Check for integer load
1055 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1056 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1057
1058 // Check for integer reg-xmm reg copy
1059 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1060 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1061 "no 64 bit integer-float reg moves" );
1062 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1063 }
1064 // --------------------------------------
1065 // Check for float reg-reg copy
1066 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1067 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1068 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1069 if( cbuf ) {
1070
1071 // Note the mucking with the register encode to compensate for the 0/1
1072 // indexing issue mentioned in a comment in the reg_def sections
1073 // for FPR registers many lines above here.
1074
1075 if( src_first != FPR1L_num ) {
1076 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1077 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1078 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1079 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1080 } else {
1081 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1082 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1083 }
1084 #ifndef PRODUCT
1085 } else if( !do_size ) {
1086 if( size != 0 ) st->print("\n\t");
1087 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1088 else st->print( "FST %s", Matcher::regName[dst_first]);
1089 #endif
1090 }
1091 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1092 }
1093
1094 // Check for float store
1095 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1096 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1097 }
1098
1099 // Check for float load
1100 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1101 int offset = ra_->reg2offset(src_first);
1102 const char *op_str;
1103 int op;
1104 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1105 op_str = "FLD_D";
1106 op = 0xDD;
1107 } else { // 32-bit load
1108 op_str = "FLD_S";
1109 op = 0xD9;
1110 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1111 }
1112 if( cbuf ) {
1113 emit_opcode (*cbuf, op );
1114 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1115 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1116 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1117 #ifndef PRODUCT
1118 } else if( !do_size ) {
1119 if( size != 0 ) st->print("\n\t");
1120 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1121 #endif
1122 }
1123 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1124 return size + 3+offset_size+2;
1125 }
1126
1127 // Check for xmm reg-reg copy
1128 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1129 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1130 (src_first+1 == src_second && dst_first+1 == dst_second),
1131 "no non-adjacent float-moves" );
1132 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1133 }
1134
1135 // Check for xmm reg-integer reg copy
1136 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1137 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1138 "no 64 bit float-integer reg moves" );
1139 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1140 }
1141
1142 // Check for xmm store
1143 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1144 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1145 }
1146
1147 // Check for float xmm load
1148 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1149 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1150 }
1151
1152 // Copy from float reg to xmm reg
1153 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1154 // copy to the top of stack from floating point reg
1155 // and use LEA to preserve flags
1156 if( cbuf ) {
1157 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1158 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1159 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1160 emit_d8(*cbuf,0xF8);
1161 #ifndef PRODUCT
1162 } else if( !do_size ) {
1163 if( size != 0 ) st->print("\n\t");
1164 st->print("LEA ESP,[ESP-8]");
1165 #endif
1166 }
1167 size += 4;
1168
1169 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1170
1171 // Copy from the temp memory to the xmm reg.
1172 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1173
1174 if( cbuf ) {
1175 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1176 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1177 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1178 emit_d8(*cbuf,0x08);
1179 #ifndef PRODUCT
1180 } else if( !do_size ) {
1181 if( size != 0 ) st->print("\n\t");
1182 st->print("LEA ESP,[ESP+8]");
1183 #endif
1184 }
1185 size += 4;
1186 return size;
1187 }
1188
1189 assert( size > 0, "missed a case" );
1190
1191 // --------------------------------------------------------------------
1192 // Check for second bits still needing moving.
1193 if( src_second == dst_second )
1194 return size; // Self copy; no move
1195 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1196
1197 // Check for second word int-int move
1198 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1199 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1200
1201 // Check for second word integer store
1202 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1203 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1204
1205 // Check for second word integer load
1206 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1207 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1208
1209
1210 Unimplemented();
1211 }
1212
1213 #ifndef PRODUCT
1214 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1215 implementation( NULL, ra_, false, st );
1216 }
1217 #endif
1218
1219 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1220 implementation( &cbuf, ra_, false, NULL );
1221 }
1222
1223 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1224 return implementation( NULL, ra_, true, NULL );
1225 }
1226
1227
1228 //=============================================================================
1229 #ifndef PRODUCT
1230 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1231 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1232 int reg = ra_->get_reg_first(this);
1233 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1234 }
1235 #endif
1236
1237 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1238 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1239 int reg = ra_->get_encode(this);
1240 if( offset >= 128 ) {
1241 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1242 emit_rm(cbuf, 0x2, reg, 0x04);
1243 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1244 emit_d32(cbuf, offset);
1245 }
1246 else {
1247 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1248 emit_rm(cbuf, 0x1, reg, 0x04);
1249 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1250 emit_d8(cbuf, offset);
1251 }
1252 }
1253
1254 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1255 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1256 if( offset >= 128 ) {
1257 return 7;
1258 }
1259 else {
1260 return 4;
1261 }
1262 }
1263
1264 //=============================================================================
1265 #ifndef PRODUCT
1266 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1267 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1268 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1269 st->print_cr("\tNOP");
1270 st->print_cr("\tNOP");
1271 if( !OptoBreakpoint )
1272 st->print_cr("\tNOP");
1273 }
1274 #endif
1275
1276 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1277 MacroAssembler masm(&cbuf);
1278 #ifdef ASSERT
1279 uint insts_size = cbuf.insts_size();
1280 #endif
1281 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1282 masm.jump_cc(Assembler::notEqual,
1283 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1284 /* WARNING these NOPs are critical so that verified entry point is properly
1285 aligned for patching by NativeJump::patch_verified_entry() */
1286 int nops_cnt = 2;
1287 if( !OptoBreakpoint ) // Leave space for int3
1288 nops_cnt += 1;
1289 masm.nop(nops_cnt);
1290
1291 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1292 }
1293
1294 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1295 return OptoBreakpoint ? 11 : 12;
1296 }
1297
1298
1299 //=============================================================================
1300 uint size_exception_handler() {
1301 // NativeCall instruction size is the same as NativeJump.
1302 // exception handler starts out as jump and can be patched to
1303 // a call be deoptimization. (4932387)
1304 // Note that this value is also credited (in output.cpp) to
1305 // the size of the code section.
1306 return NativeJump::instruction_size;
1307 }
1308
1309 // Emit exception handler code. Stuff framesize into a register
1310 // and call a VM stub routine.
1311 int emit_exception_handler(CodeBuffer& cbuf) {
1312
1313 // Note that the code buffer's insts_mark is always relative to insts.
1314 // That's why we must use the macroassembler to generate a handler.
1315 MacroAssembler _masm(&cbuf);
1316 address base =
1317 __ start_a_stub(size_exception_handler());
1318 if (base == NULL) return 0; // CodeBuffer::expand failed
1319 int offset = __ offset();
1320 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1321 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1322 __ end_a_stub();
1323 return offset;
1324 }
1325
1326 uint size_deopt_handler() {
1327 // NativeCall instruction size is the same as NativeJump.
1328 // exception handler starts out as jump and can be patched to
1329 // a call be deoptimization. (4932387)
1330 // Note that this value is also credited (in output.cpp) to
1331 // the size of the code section.
1332 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1333 }
1334
1335 // Emit deopt handler code.
1336 int emit_deopt_handler(CodeBuffer& cbuf) {
1337
1338 // Note that the code buffer's insts_mark is always relative to insts.
1339 // That's why we must use the macroassembler to generate a handler.
1340 MacroAssembler _masm(&cbuf);
1341 address base =
1342 __ start_a_stub(size_exception_handler());
1343 if (base == NULL) return 0; // CodeBuffer::expand failed
1344 int offset = __ offset();
1345 InternalAddress here(__ pc());
1346 __ pushptr(here.addr());
1347
1348 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1349 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1350 __ end_a_stub();
1351 return offset;
1352 }
1353
1354 int Matcher::regnum_to_fpu_offset(int regnum) {
1355 return regnum - 32; // The FP registers are in the second chunk
1356 }
1357
1358 // This is UltraSparc specific, true just means we have fast l2f conversion
1359 const bool Matcher::convL2FSupported(void) {
1360 return true;
1361 }
1362
1363 // Is this branch offset short enough that a short branch can be used?
1364 //
1365 // NOTE: If the platform does not provide any short branch variants, then
1366 // this method should return false for offset 0.
1367 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1368 // The passed offset is relative to address of the branch.
1369 // On 86 a branch displacement is calculated relative to address
1370 // of a next instruction.
1371 offset -= br_size;
1372
1373 // the short version of jmpConUCF2 contains multiple branches,
1374 // making the reach slightly less
1375 if (rule == jmpConUCF2_rule)
1376 return (-126 <= offset && offset <= 125);
1377 return (-128 <= offset && offset <= 127);
1378 }
1379
1380 const bool Matcher::isSimpleConstant64(jlong value) {
1381 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1382 return false;
1383 }
1384
1385 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1386 const bool Matcher::init_array_count_is_in_bytes = false;
1387
1388 // Threshold size for cleararray.
1389 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1390
1391 // Needs 2 CMOV's for longs.
1392 const int Matcher::long_cmove_cost() { return 1; }
1393
1394 // No CMOVF/CMOVD with SSE/SSE2
1395 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1396
1397 // Does the CPU require late expand (see block.cpp for description of late expand)?
1398 const bool Matcher::require_postalloc_expand = false;
1399
1400 // Should the Matcher clone shifts on addressing modes, expecting them to
1401 // be subsumed into complex addressing expressions or compute them into
1402 // registers? True for Intel but false for most RISCs
1403 const bool Matcher::clone_shift_expressions = true;
1404
1405 // Do we need to mask the count passed to shift instructions or does
1406 // the cpu only look at the lower 5/6 bits anyway?
1407 const bool Matcher::need_masked_shift_count = false;
1408
1409 bool Matcher::narrow_oop_use_complex_address() {
1410 ShouldNotCallThis();
1411 return true;
1412 }
1413
1414 bool Matcher::narrow_klass_use_complex_address() {
1415 ShouldNotCallThis();
1416 return true;
1417 }
1418
1419
1420 // Is it better to copy float constants, or load them directly from memory?
1421 // Intel can load a float constant from a direct address, requiring no
1422 // extra registers. Most RISCs will have to materialize an address into a
1423 // register first, so they would do better to copy the constant from stack.
1424 const bool Matcher::rematerialize_float_constants = true;
1425
1426 // If CPU can load and store mis-aligned doubles directly then no fixup is
1427 // needed. Else we split the double into 2 integer pieces and move it
1428 // piece-by-piece. Only happens when passing doubles into C code as the
1429 // Java calling convention forces doubles to be aligned.
1430 const bool Matcher::misaligned_doubles_ok = true;
1431
1432
1433 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1434 // Get the memory operand from the node
1435 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1436 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1437 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1438 uint opcnt = 1; // First operand
1439 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1440 while( idx >= skipped+num_edges ) {
1441 skipped += num_edges;
1442 opcnt++; // Bump operand count
1443 assert( opcnt < numopnds, "Accessing non-existent operand" );
1444 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1445 }
1446
1447 MachOper *memory = node->_opnds[opcnt];
1448 MachOper *new_memory = NULL;
1449 switch (memory->opcode()) {
1450 case DIRECT:
1451 case INDOFFSET32X:
1452 // No transformation necessary.
1453 return;
1454 case INDIRECT:
1455 new_memory = new (C) indirect_win95_safeOper( );
1456 break;
1457 case INDOFFSET8:
1458 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1459 break;
1460 case INDOFFSET32:
1461 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1462 break;
1463 case INDINDEXOFFSET:
1464 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1465 break;
1466 case INDINDEXSCALE:
1467 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1468 break;
1469 case INDINDEXSCALEOFFSET:
1470 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1471 break;
1472 case LOAD_LONG_INDIRECT:
1473 case LOAD_LONG_INDOFFSET32:
1474 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1475 return;
1476 default:
1477 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1478 return;
1479 }
1480 node->_opnds[opcnt] = new_memory;
1481 }
1482
1483 // Advertise here if the CPU requires explicit rounding operations
1484 // to implement the UseStrictFP mode.
1485 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1486
1487 // Are floats conerted to double when stored to stack during deoptimization?
1488 // On x32 it is stored with convertion only when FPU is used for floats.
1489 bool Matcher::float_in_double() { return (UseSSE == 0); }
1490
1491 // Do ints take an entire long register or just half?
1492 const bool Matcher::int_in_long = false;
1493
1494 // Return whether or not this register is ever used as an argument. This
1495 // function is used on startup to build the trampoline stubs in generateOptoStub.
1496 // Registers not mentioned will be killed by the VM call in the trampoline, and
1497 // arguments in those registers not be available to the callee.
1498 bool Matcher::can_be_java_arg( int reg ) {
1499 if( reg == ECX_num || reg == EDX_num ) return true;
1500 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1501 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1502 return false;
1503 }
1504
1505 bool Matcher::is_spillable_arg( int reg ) {
1506 return can_be_java_arg(reg);
1507 }
1508
1509 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1510 // Use hardware integer DIV instruction when
1511 // it is faster than a code which use multiply.
1512 // Only when constant divisor fits into 32 bit
1513 // (min_jint is excluded to get only correct
1514 // positive 32 bit values from negative).
1515 return VM_Version::has_fast_idiv() &&
1516 (divisor == (int)divisor && divisor != min_jint);
1517 }
1518
1519 // Register for DIVI projection of divmodI
1520 RegMask Matcher::divI_proj_mask() {
1521 return EAX_REG_mask();
1522 }
1523
1524 // Register for MODI projection of divmodI
1525 RegMask Matcher::modI_proj_mask() {
1526 return EDX_REG_mask();
1527 }
1528
1529 // Register for DIVL projection of divmodL
1530 RegMask Matcher::divL_proj_mask() {
1531 ShouldNotReachHere();
1532 return RegMask();
1533 }
1534
1535 // Register for MODL projection of divmodL
1536 RegMask Matcher::modL_proj_mask() {
1537 ShouldNotReachHere();
1538 return RegMask();
1539 }
1540
1541 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1542 return EBP_REG_mask();
1543 }
1544
1545 const RegMask Matcher::mathExactI_result_proj_mask() {
1546 return EAX_REG_mask();
1547 }
1548
1549 const RegMask Matcher::mathExactL_result_proj_mask() {
1550 ShouldNotReachHere();
1551 return RegMask();
1552 }
1553
1554 const RegMask Matcher::mathExactI_flags_proj_mask() {
1555 return INT_FLAGS_mask();
1556 }
1557
1558 // Returns true if the high 32 bits of the value is known to be zero.
1559 bool is_operand_hi32_zero(Node* n) {
1560 int opc = n->Opcode();
1561 if (opc == Op_AndL) {
1562 Node* o2 = n->in(2);
1563 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1564 return true;
1565 }
1566 }
1567 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1568 return true;
1569 }
1570 return false;
1571 }
1572
1573 %}
1574
1575 //----------ENCODING BLOCK-----------------------------------------------------
1576 // This block specifies the encoding classes used by the compiler to output
1577 // byte streams. Encoding classes generate functions which are called by
1578 // Machine Instruction Nodes in order to generate the bit encoding of the
1579 // instruction. Operands specify their base encoding interface with the
1580 // interface keyword. There are currently supported four interfaces,
1581 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1582 // operand to generate a function which returns its register number when
1583 // queried. CONST_INTER causes an operand to generate a function which
1584 // returns the value of the constant when queried. MEMORY_INTER causes an
1585 // operand to generate four functions which return the Base Register, the
1586 // Index Register, the Scale Value, and the Offset Value of the operand when
1587 // queried. COND_INTER causes an operand to generate six functions which
1588 // return the encoding code (ie - encoding bits for the instruction)
1589 // associated with each basic boolean condition for a conditional instruction.
1590 // Instructions specify two basic values for encoding. They use the
1591 // ins_encode keyword to specify their encoding class (which must be one of
1592 // the class names specified in the encoding block), and they use the
1593 // opcode keyword to specify, in order, their primary, secondary, and
1594 // tertiary opcode. Only the opcode sections which a particular instruction
1595 // needs for encoding need to be specified.
1596 encode %{
1597 // Build emit functions for each basic byte or larger field in the intel
1598 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1599 // code in the enc_class source block. Emit functions will live in the
1600 // main source block for now. In future, we can generalize this by
1601 // adding a syntax that specifies the sizes of fields in an order,
1602 // so that the adlc can build the emit functions automagically
1603
1604 // Emit primary opcode
1605 enc_class OpcP %{
1606 emit_opcode(cbuf, $primary);
1607 %}
1608
1609 // Emit secondary opcode
1610 enc_class OpcS %{
1611 emit_opcode(cbuf, $secondary);
1612 %}
1613
1614 // Emit opcode directly
1615 enc_class Opcode(immI d8) %{
1616 emit_opcode(cbuf, $d8$$constant);
1617 %}
1618
1619 enc_class SizePrefix %{
1620 emit_opcode(cbuf,0x66);
1621 %}
1622
1623 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1624 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1625 %}
1626
1627 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1628 emit_opcode(cbuf,$opcode$$constant);
1629 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1630 %}
1631
1632 enc_class mov_r32_imm0( rRegI dst ) %{
1633 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1634 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1635 %}
1636
1637 enc_class cdq_enc %{
1638 // Full implementation of Java idiv and irem; checks for
1639 // special case as described in JVM spec., p.243 & p.271.
1640 //
1641 // normal case special case
1642 //
1643 // input : rax,: dividend min_int
1644 // reg: divisor -1
1645 //
1646 // output: rax,: quotient (= rax, idiv reg) min_int
1647 // rdx: remainder (= rax, irem reg) 0
1648 //
1649 // Code sequnce:
1650 //
1651 // 81 F8 00 00 00 80 cmp rax,80000000h
1652 // 0F 85 0B 00 00 00 jne normal_case
1653 // 33 D2 xor rdx,edx
1654 // 83 F9 FF cmp rcx,0FFh
1655 // 0F 84 03 00 00 00 je done
1656 // normal_case:
1657 // 99 cdq
1658 // F7 F9 idiv rax,ecx
1659 // done:
1660 //
1661 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1662 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1663 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1664 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1665 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1666 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1667 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1668 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1669 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1670 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1671 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1672 // normal_case:
1673 emit_opcode(cbuf,0x99); // cdq
1674 // idiv (note: must be emitted by the user of this rule)
1675 // normal:
1676 %}
1677
1678 // Dense encoding for older common ops
1679 enc_class Opc_plus(immI opcode, rRegI reg) %{
1680 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1681 %}
1682
1683
1684 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1685 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1686 // Check for 8-bit immediate, and set sign extend bit in opcode
1687 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1688 emit_opcode(cbuf, $primary | 0x02);
1689 }
1690 else { // If 32-bit immediate
1691 emit_opcode(cbuf, $primary);
1692 }
1693 %}
1694
1695 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1696 // Emit primary opcode and set sign-extend bit
1697 // Check for 8-bit immediate, and set sign extend bit in opcode
1698 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1699 emit_opcode(cbuf, $primary | 0x02); }
1700 else { // If 32-bit immediate
1701 emit_opcode(cbuf, $primary);
1702 }
1703 // Emit r/m byte with secondary opcode, after primary opcode.
1704 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1705 %}
1706
1707 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1708 // Check for 8-bit immediate, and set sign extend bit in opcode
1709 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1710 $$$emit8$imm$$constant;
1711 }
1712 else { // If 32-bit immediate
1713 // Output immediate
1714 $$$emit32$imm$$constant;
1715 }
1716 %}
1717
1718 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1719 // Emit primary opcode and set sign-extend bit
1720 // Check for 8-bit immediate, and set sign extend bit in opcode
1721 int con = (int)$imm$$constant; // Throw away top bits
1722 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1723 // Emit r/m byte with secondary opcode, after primary opcode.
1724 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1725 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1726 else emit_d32(cbuf,con);
1727 %}
1728
1729 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1730 // Emit primary opcode and set sign-extend bit
1731 // Check for 8-bit immediate, and set sign extend bit in opcode
1732 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1733 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1734 // Emit r/m byte with tertiary opcode, after primary opcode.
1735 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1736 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1737 else emit_d32(cbuf,con);
1738 %}
1739
1740 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1741 emit_cc(cbuf, $secondary, $dst$$reg );
1742 %}
1743
1744 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1745 int destlo = $dst$$reg;
1746 int desthi = HIGH_FROM_LOW(destlo);
1747 // bswap lo
1748 emit_opcode(cbuf, 0x0F);
1749 emit_cc(cbuf, 0xC8, destlo);
1750 // bswap hi
1751 emit_opcode(cbuf, 0x0F);
1752 emit_cc(cbuf, 0xC8, desthi);
1753 // xchg lo and hi
1754 emit_opcode(cbuf, 0x87);
1755 emit_rm(cbuf, 0x3, destlo, desthi);
1756 %}
1757
1758 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1759 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1760 %}
1761
1762 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1763 $$$emit8$primary;
1764 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1765 %}
1766
1767 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1768 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1769 emit_d8(cbuf, op >> 8 );
1770 emit_d8(cbuf, op & 255);
1771 %}
1772
1773 // emulate a CMOV with a conditional branch around a MOV
1774 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1775 // Invert sense of branch from sense of CMOV
1776 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1777 emit_d8( cbuf, $brOffs$$constant );
1778 %}
1779
1780 enc_class enc_PartialSubtypeCheck( ) %{
1781 Register Redi = as_Register(EDI_enc); // result register
1782 Register Reax = as_Register(EAX_enc); // super class
1783 Register Recx = as_Register(ECX_enc); // killed
1784 Register Resi = as_Register(ESI_enc); // sub class
1785 Label miss;
1786
1787 MacroAssembler _masm(&cbuf);
1788 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1789 NULL, &miss,
1790 /*set_cond_codes:*/ true);
1791 if ($primary) {
1792 __ xorptr(Redi, Redi);
1793 }
1794 __ bind(miss);
1795 %}
1796
1797 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1798 MacroAssembler masm(&cbuf);
1799 int start = masm.offset();
1800 if (UseSSE >= 2) {
1801 if (VerifyFPU) {
1802 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1803 }
1804 } else {
1805 // External c_calling_convention expects the FPU stack to be 'clean'.
1806 // Compiled code leaves it dirty. Do cleanup now.
1807 masm.empty_FPU_stack();
1808 }
1809 if (sizeof_FFree_Float_Stack_All == -1) {
1810 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1811 } else {
1812 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1813 }
1814 %}
1815
1816 enc_class Verify_FPU_For_Leaf %{
1817 if( VerifyFPU ) {
1818 MacroAssembler masm(&cbuf);
1819 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1820 }
1821 %}
1822
1823 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1824 // This is the instruction starting address for relocation info.
1825 cbuf.set_insts_mark();
1826 $$$emit8$primary;
1827 // CALL directly to the runtime
1828 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1829 runtime_call_Relocation::spec(), RELOC_IMM32 );
1830
1831 if (UseSSE >= 2) {
1832 MacroAssembler _masm(&cbuf);
1833 BasicType rt = tf()->return_type();
1834
1835 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1836 // A C runtime call where the return value is unused. In SSE2+
1837 // mode the result needs to be removed from the FPU stack. It's
1838 // likely that this function call could be removed by the
1839 // optimizer if the C function is a pure function.
1840 __ ffree(0);
1841 } else if (rt == T_FLOAT) {
1842 __ lea(rsp, Address(rsp, -4));
1843 __ fstp_s(Address(rsp, 0));
1844 __ movflt(xmm0, Address(rsp, 0));
1845 __ lea(rsp, Address(rsp, 4));
1846 } else if (rt == T_DOUBLE) {
1847 __ lea(rsp, Address(rsp, -8));
1848 __ fstp_d(Address(rsp, 0));
1849 __ movdbl(xmm0, Address(rsp, 0));
1850 __ lea(rsp, Address(rsp, 8));
1851 }
1852 }
1853 %}
1854
1855
1856 enc_class pre_call_resets %{
1857 // If method sets FPU control word restore it here
1858 debug_only(int off0 = cbuf.insts_size());
1859 if (ra_->C->in_24_bit_fp_mode()) {
1860 MacroAssembler _masm(&cbuf);
1861 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1862 }
1863 if (ra_->C->max_vector_size() > 16) {
1864 // Clear upper bits of YMM registers when current compiled code uses
1865 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1866 MacroAssembler _masm(&cbuf);
1867 __ vzeroupper();
1868 }
1869 debug_only(int off1 = cbuf.insts_size());
1870 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1871 %}
1872
1873 enc_class post_call_FPU %{
1874 // If method sets FPU control word do it here also
1875 if (Compile::current()->in_24_bit_fp_mode()) {
1876 MacroAssembler masm(&cbuf);
1877 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1878 }
1879 %}
1880
1881 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1882 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1883 // who we intended to call.
1884 cbuf.set_insts_mark();
1885 $$$emit8$primary;
1886 if (!_method) {
1887 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1888 runtime_call_Relocation::spec(), RELOC_IMM32 );
1889 } else if (_optimized_virtual) {
1890 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1891 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1892 } else {
1893 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1894 static_call_Relocation::spec(), RELOC_IMM32 );
1895 }
1896 if (_method) { // Emit stub for static call.
1897 CompiledStaticCall::emit_to_interp_stub(cbuf);
1898 }
1899 %}
1900
1901 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1902 MacroAssembler _masm(&cbuf);
1903 __ ic_call((address)$meth$$method);
1904 %}
1905
1906 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1907 int disp = in_bytes(Method::from_compiled_offset());
1908 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1909
1910 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1911 cbuf.set_insts_mark();
1912 $$$emit8$primary;
1913 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1914 emit_d8(cbuf, disp); // Displacement
1915
1916 %}
1917
1918 // Following encoding is no longer used, but may be restored if calling
1919 // convention changes significantly.
1920 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1921 //
1922 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1923 // // int ic_reg = Matcher::inline_cache_reg();
1924 // // int ic_encode = Matcher::_regEncode[ic_reg];
1925 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1926 // // int imo_encode = Matcher::_regEncode[imo_reg];
1927 //
1928 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1929 // // // so we load it immediately before the call
1930 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1931 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1932 //
1933 // // xor rbp,ebp
1934 // emit_opcode(cbuf, 0x33);
1935 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1936 //
1937 // // CALL to interpreter.
1938 // cbuf.set_insts_mark();
1939 // $$$emit8$primary;
1940 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1941 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1942 // %}
1943
1944 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1945 $$$emit8$primary;
1946 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1947 $$$emit8$shift$$constant;
1948 %}
1949
1950 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1951 // Load immediate does not have a zero or sign extended version
1952 // for 8-bit immediates
1953 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1954 $$$emit32$src$$constant;
1955 %}
1956
1957 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1958 // Load immediate does not have a zero or sign extended version
1959 // for 8-bit immediates
1960 emit_opcode(cbuf, $primary + $dst$$reg);
1961 $$$emit32$src$$constant;
1962 %}
1963
1964 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1965 // Load immediate does not have a zero or sign extended version
1966 // for 8-bit immediates
1967 int dst_enc = $dst$$reg;
1968 int src_con = $src$$constant & 0x0FFFFFFFFL;
1969 if (src_con == 0) {
1970 // xor dst, dst
1971 emit_opcode(cbuf, 0x33);
1972 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1973 } else {
1974 emit_opcode(cbuf, $primary + dst_enc);
1975 emit_d32(cbuf, src_con);
1976 }
1977 %}
1978
1979 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1980 // Load immediate does not have a zero or sign extended version
1981 // for 8-bit immediates
1982 int dst_enc = $dst$$reg + 2;
1983 int src_con = ((julong)($src$$constant)) >> 32;
1984 if (src_con == 0) {
1985 // xor dst, dst
1986 emit_opcode(cbuf, 0x33);
1987 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1988 } else {
1989 emit_opcode(cbuf, $primary + dst_enc);
1990 emit_d32(cbuf, src_con);
1991 }
1992 %}
1993
1994
1995 // Encode a reg-reg copy. If it is useless, then empty encoding.
1996 enc_class enc_Copy( rRegI dst, rRegI src ) %{
1997 encode_Copy( cbuf, $dst$$reg, $src$$reg );
1998 %}
1999
2000 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
2001 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2002 %}
2003
2004 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
2005 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2006 %}
2007
2008 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2009 $$$emit8$primary;
2010 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2011 %}
2012
2013 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2014 $$$emit8$secondary;
2015 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2016 %}
2017
2018 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2019 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2020 %}
2021
2022 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2023 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2024 %}
2025
2026 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2027 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2028 %}
2029
2030 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2031 // Output immediate
2032 $$$emit32$src$$constant;
2033 %}
2034
2035 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2036 // Output Float immediate bits
2037 jfloat jf = $src$$constant;
2038 int jf_as_bits = jint_cast( jf );
2039 emit_d32(cbuf, jf_as_bits);
2040 %}
2041
2042 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2043 // Output Float immediate bits
2044 jfloat jf = $src$$constant;
2045 int jf_as_bits = jint_cast( jf );
2046 emit_d32(cbuf, jf_as_bits);
2047 %}
2048
2049 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2050 // Output immediate
2051 $$$emit16$src$$constant;
2052 %}
2053
2054 enc_class Con_d32(immI src) %{
2055 emit_d32(cbuf,$src$$constant);
2056 %}
2057
2058 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2059 // Output immediate memory reference
2060 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2061 emit_d32(cbuf, 0x00);
2062 %}
2063
2064 enc_class lock_prefix( ) %{
2065 if( os::is_MP() )
2066 emit_opcode(cbuf,0xF0); // [Lock]
2067 %}
2068
2069 // Cmp-xchg long value.
2070 // Note: we need to swap rbx, and rcx before and after the
2071 // cmpxchg8 instruction because the instruction uses
2072 // rcx as the high order word of the new value to store but
2073 // our register encoding uses rbx,.
2074 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2075
2076 // XCHG rbx,ecx
2077 emit_opcode(cbuf,0x87);
2078 emit_opcode(cbuf,0xD9);
2079 // [Lock]
2080 if( os::is_MP() )
2081 emit_opcode(cbuf,0xF0);
2082 // CMPXCHG8 [Eptr]
2083 emit_opcode(cbuf,0x0F);
2084 emit_opcode(cbuf,0xC7);
2085 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2086 // XCHG rbx,ecx
2087 emit_opcode(cbuf,0x87);
2088 emit_opcode(cbuf,0xD9);
2089 %}
2090
2091 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2092 // [Lock]
2093 if( os::is_MP() )
2094 emit_opcode(cbuf,0xF0);
2095
2096 // CMPXCHG [Eptr]
2097 emit_opcode(cbuf,0x0F);
2098 emit_opcode(cbuf,0xB1);
2099 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2100 %}
2101
2102 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2103 int res_encoding = $res$$reg;
2104
2105 // MOV res,0
2106 emit_opcode( cbuf, 0xB8 + res_encoding);
2107 emit_d32( cbuf, 0 );
2108 // JNE,s fail
2109 emit_opcode(cbuf,0x75);
2110 emit_d8(cbuf, 5 );
2111 // MOV res,1
2112 emit_opcode( cbuf, 0xB8 + res_encoding);
2113 emit_d32( cbuf, 1 );
2114 // fail:
2115 %}
2116
2117 enc_class set_instruction_start( ) %{
2118 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2119 %}
2120
2121 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2122 int reg_encoding = $ereg$$reg;
2123 int base = $mem$$base;
2124 int index = $mem$$index;
2125 int scale = $mem$$scale;
2126 int displace = $mem$$disp;
2127 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2128 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2129 %}
2130
2131 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2132 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2133 int base = $mem$$base;
2134 int index = $mem$$index;
2135 int scale = $mem$$scale;
2136 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2137 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2138 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2139 %}
2140
2141 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2142 int r1, r2;
2143 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2144 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2145 emit_opcode(cbuf,0x0F);
2146 emit_opcode(cbuf,$tertiary);
2147 emit_rm(cbuf, 0x3, r1, r2);
2148 emit_d8(cbuf,$cnt$$constant);
2149 emit_d8(cbuf,$primary);
2150 emit_rm(cbuf, 0x3, $secondary, r1);
2151 emit_d8(cbuf,$cnt$$constant);
2152 %}
2153
2154 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2155 emit_opcode( cbuf, 0x8B ); // Move
2156 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2157 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2158 emit_d8(cbuf,$primary);
2159 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2160 emit_d8(cbuf,$cnt$$constant-32);
2161 }
2162 emit_d8(cbuf,$primary);
2163 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2164 emit_d8(cbuf,31);
2165 %}
2166
2167 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2168 int r1, r2;
2169 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2170 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2171
2172 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2173 emit_rm(cbuf, 0x3, r1, r2);
2174 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2175 emit_opcode(cbuf,$primary);
2176 emit_rm(cbuf, 0x3, $secondary, r1);
2177 emit_d8(cbuf,$cnt$$constant-32);
2178 }
2179 emit_opcode(cbuf,0x33); // XOR r2,r2
2180 emit_rm(cbuf, 0x3, r2, r2);
2181 %}
2182
2183 // Clone of RegMem but accepts an extra parameter to access each
2184 // half of a double in memory; it never needs relocation info.
2185 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2186 emit_opcode(cbuf,$opcode$$constant);
2187 int reg_encoding = $rm_reg$$reg;
2188 int base = $mem$$base;
2189 int index = $mem$$index;
2190 int scale = $mem$$scale;
2191 int displace = $mem$$disp + $disp_for_half$$constant;
2192 relocInfo::relocType disp_reloc = relocInfo::none;
2193 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2194 %}
2195
2196 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2197 //
2198 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2199 // and it never needs relocation information.
2200 // Frequently used to move data between FPU's Stack Top and memory.
2201 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2202 int rm_byte_opcode = $rm_opcode$$constant;
2203 int base = $mem$$base;
2204 int index = $mem$$index;
2205 int scale = $mem$$scale;
2206 int displace = $mem$$disp;
2207 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2208 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2209 %}
2210
2211 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2212 int rm_byte_opcode = $rm_opcode$$constant;
2213 int base = $mem$$base;
2214 int index = $mem$$index;
2215 int scale = $mem$$scale;
2216 int displace = $mem$$disp;
2217 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2218 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2219 %}
2220
2221 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2222 int reg_encoding = $dst$$reg;
2223 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2224 int index = 0x04; // 0x04 indicates no index
2225 int scale = 0x00; // 0x00 indicates no scale
2226 int displace = $src1$$constant; // 0x00 indicates no displacement
2227 relocInfo::relocType disp_reloc = relocInfo::none;
2228 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2229 %}
2230
2231 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2232 // Compare dst,src
2233 emit_opcode(cbuf,0x3B);
2234 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2235 // jmp dst < src around move
2236 emit_opcode(cbuf,0x7C);
2237 emit_d8(cbuf,2);
2238 // move dst,src
2239 emit_opcode(cbuf,0x8B);
2240 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2241 %}
2242
2243 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2244 // Compare dst,src
2245 emit_opcode(cbuf,0x3B);
2246 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2247 // jmp dst > src around move
2248 emit_opcode(cbuf,0x7F);
2249 emit_d8(cbuf,2);
2250 // move dst,src
2251 emit_opcode(cbuf,0x8B);
2252 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2253 %}
2254
2255 enc_class enc_FPR_store(memory mem, regDPR src) %{
2256 // If src is FPR1, we can just FST to store it.
2257 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2258 int reg_encoding = 0x2; // Just store
2259 int base = $mem$$base;
2260 int index = $mem$$index;
2261 int scale = $mem$$scale;
2262 int displace = $mem$$disp;
2263 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2264 if( $src$$reg != FPR1L_enc ) {
2265 reg_encoding = 0x3; // Store & pop
2266 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2267 emit_d8( cbuf, 0xC0-1+$src$$reg );
2268 }
2269 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2270 emit_opcode(cbuf,$primary);
2271 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2272 %}
2273
2274 enc_class neg_reg(rRegI dst) %{
2275 // NEG $dst
2276 emit_opcode(cbuf,0xF7);
2277 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2278 %}
2279
2280 enc_class setLT_reg(eCXRegI dst) %{
2281 // SETLT $dst
2282 emit_opcode(cbuf,0x0F);
2283 emit_opcode(cbuf,0x9C);
2284 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2285 %}
2286
2287 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2288 int tmpReg = $tmp$$reg;
2289
2290 // SUB $p,$q
2291 emit_opcode(cbuf,0x2B);
2292 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2293 // SBB $tmp,$tmp
2294 emit_opcode(cbuf,0x1B);
2295 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2296 // AND $tmp,$y
2297 emit_opcode(cbuf,0x23);
2298 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2299 // ADD $p,$tmp
2300 emit_opcode(cbuf,0x03);
2301 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2302 %}
2303
2304 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2305 // TEST shift,32
2306 emit_opcode(cbuf,0xF7);
2307 emit_rm(cbuf, 0x3, 0, ECX_enc);
2308 emit_d32(cbuf,0x20);
2309 // JEQ,s small
2310 emit_opcode(cbuf, 0x74);
2311 emit_d8(cbuf, 0x04);
2312 // MOV $dst.hi,$dst.lo
2313 emit_opcode( cbuf, 0x8B );
2314 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2315 // CLR $dst.lo
2316 emit_opcode(cbuf, 0x33);
2317 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2318 // small:
2319 // SHLD $dst.hi,$dst.lo,$shift
2320 emit_opcode(cbuf,0x0F);
2321 emit_opcode(cbuf,0xA5);
2322 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2323 // SHL $dst.lo,$shift"
2324 emit_opcode(cbuf,0xD3);
2325 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2326 %}
2327
2328 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2329 // TEST shift,32
2330 emit_opcode(cbuf,0xF7);
2331 emit_rm(cbuf, 0x3, 0, ECX_enc);
2332 emit_d32(cbuf,0x20);
2333 // JEQ,s small
2334 emit_opcode(cbuf, 0x74);
2335 emit_d8(cbuf, 0x04);
2336 // MOV $dst.lo,$dst.hi
2337 emit_opcode( cbuf, 0x8B );
2338 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2339 // CLR $dst.hi
2340 emit_opcode(cbuf, 0x33);
2341 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2342 // small:
2343 // SHRD $dst.lo,$dst.hi,$shift
2344 emit_opcode(cbuf,0x0F);
2345 emit_opcode(cbuf,0xAD);
2346 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2347 // SHR $dst.hi,$shift"
2348 emit_opcode(cbuf,0xD3);
2349 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2350 %}
2351
2352 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2353 // TEST shift,32
2354 emit_opcode(cbuf,0xF7);
2355 emit_rm(cbuf, 0x3, 0, ECX_enc);
2356 emit_d32(cbuf,0x20);
2357 // JEQ,s small
2358 emit_opcode(cbuf, 0x74);
2359 emit_d8(cbuf, 0x05);
2360 // MOV $dst.lo,$dst.hi
2361 emit_opcode( cbuf, 0x8B );
2362 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2363 // SAR $dst.hi,31
2364 emit_opcode(cbuf, 0xC1);
2365 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2366 emit_d8(cbuf, 0x1F );
2367 // small:
2368 // SHRD $dst.lo,$dst.hi,$shift
2369 emit_opcode(cbuf,0x0F);
2370 emit_opcode(cbuf,0xAD);
2371 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2372 // SAR $dst.hi,$shift"
2373 emit_opcode(cbuf,0xD3);
2374 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2375 %}
2376
2377
2378 // ----------------- Encodings for floating point unit -----------------
2379 // May leave result in FPU-TOS or FPU reg depending on opcodes
2380 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2381 $$$emit8$primary;
2382 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2383 %}
2384
2385 // Pop argument in FPR0 with FSTP ST(0)
2386 enc_class PopFPU() %{
2387 emit_opcode( cbuf, 0xDD );
2388 emit_d8( cbuf, 0xD8 );
2389 %}
2390
2391 // !!!!! equivalent to Pop_Reg_F
2392 enc_class Pop_Reg_DPR( regDPR dst ) %{
2393 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2394 emit_d8( cbuf, 0xD8+$dst$$reg );
2395 %}
2396
2397 enc_class Push_Reg_DPR( regDPR dst ) %{
2398 emit_opcode( cbuf, 0xD9 );
2399 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2400 %}
2401
2402 enc_class strictfp_bias1( regDPR dst ) %{
2403 emit_opcode( cbuf, 0xDB ); // FLD m80real
2404 emit_opcode( cbuf, 0x2D );
2405 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2406 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2407 emit_opcode( cbuf, 0xC8+$dst$$reg );
2408 %}
2409
2410 enc_class strictfp_bias2( regDPR dst ) %{
2411 emit_opcode( cbuf, 0xDB ); // FLD m80real
2412 emit_opcode( cbuf, 0x2D );
2413 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2414 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2415 emit_opcode( cbuf, 0xC8+$dst$$reg );
2416 %}
2417
2418 // Special case for moving an integer register to a stack slot.
2419 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2420 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2421 %}
2422
2423 // Special case for moving a register to a stack slot.
2424 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2425 // Opcode already emitted
2426 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2427 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2428 emit_d32(cbuf, $dst$$disp); // Displacement
2429 %}
2430
2431 // Push the integer in stackSlot 'src' onto FP-stack
2432 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2433 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2434 %}
2435
2436 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2437 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2438 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2439 %}
2440
2441 // Same as Pop_Mem_F except for opcode
2442 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2443 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2444 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2445 %}
2446
2447 enc_class Pop_Reg_FPR( regFPR dst ) %{
2448 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2449 emit_d8( cbuf, 0xD8+$dst$$reg );
2450 %}
2451
2452 enc_class Push_Reg_FPR( regFPR dst ) %{
2453 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2454 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2455 %}
2456
2457 // Push FPU's float to a stack-slot, and pop FPU-stack
2458 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2459 int pop = 0x02;
2460 if ($src$$reg != FPR1L_enc) {
2461 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2462 emit_d8( cbuf, 0xC0-1+$src$$reg );
2463 pop = 0x03;
2464 }
2465 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2466 %}
2467
2468 // Push FPU's double to a stack-slot, and pop FPU-stack
2469 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2470 int pop = 0x02;
2471 if ($src$$reg != FPR1L_enc) {
2472 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2473 emit_d8( cbuf, 0xC0-1+$src$$reg );
2474 pop = 0x03;
2475 }
2476 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2477 %}
2478
2479 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2480 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2481 int pop = 0xD0 - 1; // -1 since we skip FLD
2482 if ($src$$reg != FPR1L_enc) {
2483 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2484 emit_d8( cbuf, 0xC0-1+$src$$reg );
2485 pop = 0xD8;
2486 }
2487 emit_opcode( cbuf, 0xDD );
2488 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2489 %}
2490
2491
2492 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2493 // load dst in FPR0
2494 emit_opcode( cbuf, 0xD9 );
2495 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2496 if ($src$$reg != FPR1L_enc) {
2497 // fincstp
2498 emit_opcode (cbuf, 0xD9);
2499 emit_opcode (cbuf, 0xF7);
2500 // swap src with FPR1:
2501 // FXCH FPR1 with src
2502 emit_opcode(cbuf, 0xD9);
2503 emit_d8(cbuf, 0xC8-1+$src$$reg );
2504 // fdecstp
2505 emit_opcode (cbuf, 0xD9);
2506 emit_opcode (cbuf, 0xF6);
2507 }
2508 %}
2509
2510 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2511 MacroAssembler _masm(&cbuf);
2512 __ subptr(rsp, 8);
2513 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2514 __ fld_d(Address(rsp, 0));
2515 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2516 __ fld_d(Address(rsp, 0));
2517 %}
2518
2519 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2520 MacroAssembler _masm(&cbuf);
2521 __ subptr(rsp, 4);
2522 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2523 __ fld_s(Address(rsp, 0));
2524 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2525 __ fld_s(Address(rsp, 0));
2526 %}
2527
2528 enc_class Push_ResultD(regD dst) %{
2529 MacroAssembler _masm(&cbuf);
2530 __ fstp_d(Address(rsp, 0));
2531 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2532 __ addptr(rsp, 8);
2533 %}
2534
2535 enc_class Push_ResultF(regF dst, immI d8) %{
2536 MacroAssembler _masm(&cbuf);
2537 __ fstp_s(Address(rsp, 0));
2538 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2539 __ addptr(rsp, $d8$$constant);
2540 %}
2541
2542 enc_class Push_SrcD(regD src) %{
2543 MacroAssembler _masm(&cbuf);
2544 __ subptr(rsp, 8);
2545 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2546 __ fld_d(Address(rsp, 0));
2547 %}
2548
2549 enc_class push_stack_temp_qword() %{
2550 MacroAssembler _masm(&cbuf);
2551 __ subptr(rsp, 8);
2552 %}
2553
2554 enc_class pop_stack_temp_qword() %{
2555 MacroAssembler _masm(&cbuf);
2556 __ addptr(rsp, 8);
2557 %}
2558
2559 enc_class push_xmm_to_fpr1(regD src) %{
2560 MacroAssembler _masm(&cbuf);
2561 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2562 __ fld_d(Address(rsp, 0));
2563 %}
2564
2565 enc_class Push_Result_Mod_DPR( regDPR src) %{
2566 if ($src$$reg != FPR1L_enc) {
2567 // fincstp
2568 emit_opcode (cbuf, 0xD9);
2569 emit_opcode (cbuf, 0xF7);
2570 // FXCH FPR1 with src
2571 emit_opcode(cbuf, 0xD9);
2572 emit_d8(cbuf, 0xC8-1+$src$$reg );
2573 // fdecstp
2574 emit_opcode (cbuf, 0xD9);
2575 emit_opcode (cbuf, 0xF6);
2576 }
2577 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2578 // // FSTP FPR$dst$$reg
2579 // emit_opcode( cbuf, 0xDD );
2580 // emit_d8( cbuf, 0xD8+$dst$$reg );
2581 %}
2582
2583 enc_class fnstsw_sahf_skip_parity() %{
2584 // fnstsw ax
2585 emit_opcode( cbuf, 0xDF );
2586 emit_opcode( cbuf, 0xE0 );
2587 // sahf
2588 emit_opcode( cbuf, 0x9E );
2589 // jnp ::skip
2590 emit_opcode( cbuf, 0x7B );
2591 emit_opcode( cbuf, 0x05 );
2592 %}
2593
2594 enc_class emitModDPR() %{
2595 // fprem must be iterative
2596 // :: loop
2597 // fprem
2598 emit_opcode( cbuf, 0xD9 );
2599 emit_opcode( cbuf, 0xF8 );
2600 // wait
2601 emit_opcode( cbuf, 0x9b );
2602 // fnstsw ax
2603 emit_opcode( cbuf, 0xDF );
2604 emit_opcode( cbuf, 0xE0 );
2605 // sahf
2606 emit_opcode( cbuf, 0x9E );
2607 // jp ::loop
2608 emit_opcode( cbuf, 0x0F );
2609 emit_opcode( cbuf, 0x8A );
2610 emit_opcode( cbuf, 0xF4 );
2611 emit_opcode( cbuf, 0xFF );
2612 emit_opcode( cbuf, 0xFF );
2613 emit_opcode( cbuf, 0xFF );
2614 %}
2615
2616 enc_class fpu_flags() %{
2617 // fnstsw_ax
2618 emit_opcode( cbuf, 0xDF);
2619 emit_opcode( cbuf, 0xE0);
2620 // test ax,0x0400
2621 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2622 emit_opcode( cbuf, 0xA9 );
2623 emit_d16 ( cbuf, 0x0400 );
2624 // // // This sequence works, but stalls for 12-16 cycles on PPro
2625 // // test rax,0x0400
2626 // emit_opcode( cbuf, 0xA9 );
2627 // emit_d32 ( cbuf, 0x00000400 );
2628 //
2629 // jz exit (no unordered comparison)
2630 emit_opcode( cbuf, 0x74 );
2631 emit_d8 ( cbuf, 0x02 );
2632 // mov ah,1 - treat as LT case (set carry flag)
2633 emit_opcode( cbuf, 0xB4 );
2634 emit_d8 ( cbuf, 0x01 );
2635 // sahf
2636 emit_opcode( cbuf, 0x9E);
2637 %}
2638
2639 enc_class cmpF_P6_fixup() %{
2640 // Fixup the integer flags in case comparison involved a NaN
2641 //
2642 // JNP exit (no unordered comparison, P-flag is set by NaN)
2643 emit_opcode( cbuf, 0x7B );
2644 emit_d8 ( cbuf, 0x03 );
2645 // MOV AH,1 - treat as LT case (set carry flag)
2646 emit_opcode( cbuf, 0xB4 );
2647 emit_d8 ( cbuf, 0x01 );
2648 // SAHF
2649 emit_opcode( cbuf, 0x9E);
2650 // NOP // target for branch to avoid branch to branch
2651 emit_opcode( cbuf, 0x90);
2652 %}
2653
2654 // fnstsw_ax();
2655 // sahf();
2656 // movl(dst, nan_result);
2657 // jcc(Assembler::parity, exit);
2658 // movl(dst, less_result);
2659 // jcc(Assembler::below, exit);
2660 // movl(dst, equal_result);
2661 // jcc(Assembler::equal, exit);
2662 // movl(dst, greater_result);
2663
2664 // less_result = 1;
2665 // greater_result = -1;
2666 // equal_result = 0;
2667 // nan_result = -1;
2668
2669 enc_class CmpF_Result(rRegI dst) %{
2670 // fnstsw_ax();
2671 emit_opcode( cbuf, 0xDF);
2672 emit_opcode( cbuf, 0xE0);
2673 // sahf
2674 emit_opcode( cbuf, 0x9E);
2675 // movl(dst, nan_result);
2676 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2677 emit_d32( cbuf, -1 );
2678 // jcc(Assembler::parity, exit);
2679 emit_opcode( cbuf, 0x7A );
2680 emit_d8 ( cbuf, 0x13 );
2681 // movl(dst, less_result);
2682 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2683 emit_d32( cbuf, -1 );
2684 // jcc(Assembler::below, exit);
2685 emit_opcode( cbuf, 0x72 );
2686 emit_d8 ( cbuf, 0x0C );
2687 // movl(dst, equal_result);
2688 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2689 emit_d32( cbuf, 0 );
2690 // jcc(Assembler::equal, exit);
2691 emit_opcode( cbuf, 0x74 );
2692 emit_d8 ( cbuf, 0x05 );
2693 // movl(dst, greater_result);
2694 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2695 emit_d32( cbuf, 1 );
2696 %}
2697
2698
2699 // Compare the longs and set flags
2700 // BROKEN! Do Not use as-is
2701 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2702 // CMP $src1.hi,$src2.hi
2703 emit_opcode( cbuf, 0x3B );
2704 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2705 // JNE,s done
2706 emit_opcode(cbuf,0x75);
2707 emit_d8(cbuf, 2 );
2708 // CMP $src1.lo,$src2.lo
2709 emit_opcode( cbuf, 0x3B );
2710 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2711 // done:
2712 %}
2713
2714 enc_class convert_int_long( regL dst, rRegI src ) %{
2715 // mov $dst.lo,$src
2716 int dst_encoding = $dst$$reg;
2717 int src_encoding = $src$$reg;
2718 encode_Copy( cbuf, dst_encoding , src_encoding );
2719 // mov $dst.hi,$src
2720 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2721 // sar $dst.hi,31
2722 emit_opcode( cbuf, 0xC1 );
2723 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2724 emit_d8(cbuf, 0x1F );
2725 %}
2726
2727 enc_class convert_long_double( eRegL src ) %{
2728 // push $src.hi
2729 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2730 // push $src.lo
2731 emit_opcode(cbuf, 0x50+$src$$reg );
2732 // fild 64-bits at [SP]
2733 emit_opcode(cbuf,0xdf);
2734 emit_d8(cbuf, 0x6C);
2735 emit_d8(cbuf, 0x24);
2736 emit_d8(cbuf, 0x00);
2737 // pop stack
2738 emit_opcode(cbuf, 0x83); // add SP, #8
2739 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2740 emit_d8(cbuf, 0x8);
2741 %}
2742
2743 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2744 // IMUL EDX:EAX,$src1
2745 emit_opcode( cbuf, 0xF7 );
2746 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2747 // SAR EDX,$cnt-32
2748 int shift_count = ((int)$cnt$$constant) - 32;
2749 if (shift_count > 0) {
2750 emit_opcode(cbuf, 0xC1);
2751 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2752 emit_d8(cbuf, shift_count);
2753 }
2754 %}
2755
2756 // this version doesn't have add sp, 8
2757 enc_class convert_long_double2( eRegL src ) %{
2758 // push $src.hi
2759 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2760 // push $src.lo
2761 emit_opcode(cbuf, 0x50+$src$$reg );
2762 // fild 64-bits at [SP]
2763 emit_opcode(cbuf,0xdf);
2764 emit_d8(cbuf, 0x6C);
2765 emit_d8(cbuf, 0x24);
2766 emit_d8(cbuf, 0x00);
2767 %}
2768
2769 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2770 // Basic idea: long = (long)int * (long)int
2771 // IMUL EDX:EAX, src
2772 emit_opcode( cbuf, 0xF7 );
2773 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2774 %}
2775
2776 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2777 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2778 // MUL EDX:EAX, src
2779 emit_opcode( cbuf, 0xF7 );
2780 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2781 %}
2782
2783 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2784 // Basic idea: lo(result) = lo(x_lo * y_lo)
2785 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2786 // MOV $tmp,$src.lo
2787 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2788 // IMUL $tmp,EDX
2789 emit_opcode( cbuf, 0x0F );
2790 emit_opcode( cbuf, 0xAF );
2791 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2792 // MOV EDX,$src.hi
2793 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2794 // IMUL EDX,EAX
2795 emit_opcode( cbuf, 0x0F );
2796 emit_opcode( cbuf, 0xAF );
2797 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2798 // ADD $tmp,EDX
2799 emit_opcode( cbuf, 0x03 );
2800 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2801 // MUL EDX:EAX,$src.lo
2802 emit_opcode( cbuf, 0xF7 );
2803 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2804 // ADD EDX,ESI
2805 emit_opcode( cbuf, 0x03 );
2806 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2807 %}
2808
2809 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2810 // Basic idea: lo(result) = lo(src * y_lo)
2811 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2812 // IMUL $tmp,EDX,$src
2813 emit_opcode( cbuf, 0x6B );
2814 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2815 emit_d8( cbuf, (int)$src$$constant );
2816 // MOV EDX,$src
2817 emit_opcode(cbuf, 0xB8 + EDX_enc);
2818 emit_d32( cbuf, (int)$src$$constant );
2819 // MUL EDX:EAX,EDX
2820 emit_opcode( cbuf, 0xF7 );
2821 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2822 // ADD EDX,ESI
2823 emit_opcode( cbuf, 0x03 );
2824 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2825 %}
2826
2827 enc_class long_div( eRegL src1, eRegL src2 ) %{
2828 // PUSH src1.hi
2829 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2830 // PUSH src1.lo
2831 emit_opcode(cbuf, 0x50+$src1$$reg );
2832 // PUSH src2.hi
2833 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2834 // PUSH src2.lo
2835 emit_opcode(cbuf, 0x50+$src2$$reg );
2836 // CALL directly to the runtime
2837 cbuf.set_insts_mark();
2838 emit_opcode(cbuf,0xE8); // Call into runtime
2839 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2840 // Restore stack
2841 emit_opcode(cbuf, 0x83); // add SP, #framesize
2842 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2843 emit_d8(cbuf, 4*4);
2844 %}
2845
2846 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2847 // PUSH src1.hi
2848 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2849 // PUSH src1.lo
2850 emit_opcode(cbuf, 0x50+$src1$$reg );
2851 // PUSH src2.hi
2852 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2853 // PUSH src2.lo
2854 emit_opcode(cbuf, 0x50+$src2$$reg );
2855 // CALL directly to the runtime
2856 cbuf.set_insts_mark();
2857 emit_opcode(cbuf,0xE8); // Call into runtime
2858 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2859 // Restore stack
2860 emit_opcode(cbuf, 0x83); // add SP, #framesize
2861 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2862 emit_d8(cbuf, 4*4);
2863 %}
2864
2865 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2866 // MOV $tmp,$src.lo
2867 emit_opcode(cbuf, 0x8B);
2868 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2869 // OR $tmp,$src.hi
2870 emit_opcode(cbuf, 0x0B);
2871 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2872 %}
2873
2874 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2875 // CMP $src1.lo,$src2.lo
2876 emit_opcode( cbuf, 0x3B );
2877 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2878 // JNE,s skip
2879 emit_cc(cbuf, 0x70, 0x5);
2880 emit_d8(cbuf,2);
2881 // CMP $src1.hi,$src2.hi
2882 emit_opcode( cbuf, 0x3B );
2883 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2884 %}
2885
2886 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2887 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2888 emit_opcode( cbuf, 0x3B );
2889 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2890 // MOV $tmp,$src1.hi
2891 emit_opcode( cbuf, 0x8B );
2892 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2893 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2894 emit_opcode( cbuf, 0x1B );
2895 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2896 %}
2897
2898 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2899 // XOR $tmp,$tmp
2900 emit_opcode(cbuf,0x33); // XOR
2901 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2902 // CMP $tmp,$src.lo
2903 emit_opcode( cbuf, 0x3B );
2904 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2905 // SBB $tmp,$src.hi
2906 emit_opcode( cbuf, 0x1B );
2907 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2908 %}
2909
2910 // Sniff, sniff... smells like Gnu Superoptimizer
2911 enc_class neg_long( eRegL dst ) %{
2912 emit_opcode(cbuf,0xF7); // NEG hi
2913 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2914 emit_opcode(cbuf,0xF7); // NEG lo
2915 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2916 emit_opcode(cbuf,0x83); // SBB hi,0
2917 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2918 emit_d8 (cbuf,0 );
2919 %}
2920
2921 enc_class enc_pop_rdx() %{
2922 emit_opcode(cbuf,0x5A);
2923 %}
2924
2925 enc_class enc_rethrow() %{
2926 cbuf.set_insts_mark();
2927 emit_opcode(cbuf, 0xE9); // jmp entry
2928 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
2929 runtime_call_Relocation::spec(), RELOC_IMM32 );
2930 %}
2931
2932
2933 // Convert a double to an int. Java semantics require we do complex
2934 // manglelations in the corner cases. So we set the rounding mode to
2935 // 'zero', store the darned double down as an int, and reset the
2936 // rounding mode to 'nearest'. The hardware throws an exception which
2937 // patches up the correct value directly to the stack.
2938 enc_class DPR2I_encoding( regDPR src ) %{
2939 // Flip to round-to-zero mode. We attempted to allow invalid-op
2940 // exceptions here, so that a NAN or other corner-case value will
2941 // thrown an exception (but normal values get converted at full speed).
2942 // However, I2C adapters and other float-stack manglers leave pending
2943 // invalid-op exceptions hanging. We would have to clear them before
2944 // enabling them and that is more expensive than just testing for the
2945 // invalid value Intel stores down in the corner cases.
2946 emit_opcode(cbuf,0xD9); // FLDCW trunc
2947 emit_opcode(cbuf,0x2D);
2948 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
2949 // Allocate a word
2950 emit_opcode(cbuf,0x83); // SUB ESP,4
2951 emit_opcode(cbuf,0xEC);
2952 emit_d8(cbuf,0x04);
2953 // Encoding assumes a double has been pushed into FPR0.
2954 // Store down the double as an int, popping the FPU stack
2955 emit_opcode(cbuf,0xDB); // FISTP [ESP]
2956 emit_opcode(cbuf,0x1C);
2957 emit_d8(cbuf,0x24);
2958 // Restore the rounding mode; mask the exception
2959 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
2960 emit_opcode(cbuf,0x2D);
2961 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
2962 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
2963 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
2964
2965 // Load the converted int; adjust CPU stack
2966 emit_opcode(cbuf,0x58); // POP EAX
2967 emit_opcode(cbuf,0x3D); // CMP EAX,imm
2968 emit_d32 (cbuf,0x80000000); // 0x80000000
2969 emit_opcode(cbuf,0x75); // JNE around_slow_call
2970 emit_d8 (cbuf,0x07); // Size of slow_call
2971 // Push src onto stack slow-path
2972 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
2973 emit_d8 (cbuf,0xC0-1+$src$$reg );
2974 // CALL directly to the runtime
2975 cbuf.set_insts_mark();
2976 emit_opcode(cbuf,0xE8); // Call into runtime
2977 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2978 // Carry on here...
2979 %}
2980
2981 enc_class DPR2L_encoding( regDPR src ) %{
2982 emit_opcode(cbuf,0xD9); // FLDCW trunc
2983 emit_opcode(cbuf,0x2D);
2984 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
2985 // Allocate a word
2986 emit_opcode(cbuf,0x83); // SUB ESP,8
2987 emit_opcode(cbuf,0xEC);
2988 emit_d8(cbuf,0x08);
2989 // Encoding assumes a double has been pushed into FPR0.
2990 // Store down the double as a long, popping the FPU stack
2991 emit_opcode(cbuf,0xDF); // FISTP [ESP]
2992 emit_opcode(cbuf,0x3C);
2993 emit_d8(cbuf,0x24);
2994 // Restore the rounding mode; mask the exception
2995 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
2996 emit_opcode(cbuf,0x2D);
2997 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
2998 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
2999 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3000
3001 // Load the converted int; adjust CPU stack
3002 emit_opcode(cbuf,0x58); // POP EAX
3003 emit_opcode(cbuf,0x5A); // POP EDX
3004 emit_opcode(cbuf,0x81); // CMP EDX,imm
3005 emit_d8 (cbuf,0xFA); // rdx
3006 emit_d32 (cbuf,0x80000000); // 0x80000000
3007 emit_opcode(cbuf,0x75); // JNE around_slow_call
3008 emit_d8 (cbuf,0x07+4); // Size of slow_call
3009 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3010 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3011 emit_opcode(cbuf,0x75); // JNE around_slow_call
3012 emit_d8 (cbuf,0x07); // Size of slow_call
3013 // Push src onto stack slow-path
3014 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3015 emit_d8 (cbuf,0xC0-1+$src$$reg );
3016 // CALL directly to the runtime
3017 cbuf.set_insts_mark();
3018 emit_opcode(cbuf,0xE8); // Call into runtime
3019 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3020 // Carry on here...
3021 %}
3022
3023 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3024 // Operand was loaded from memory into fp ST (stack top)
3025 // FMUL ST,$src /* D8 C8+i */
3026 emit_opcode(cbuf, 0xD8);
3027 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3028 %}
3029
3030 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3031 // FADDP ST,src2 /* D8 C0+i */
3032 emit_opcode(cbuf, 0xD8);
3033 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3034 //could use FADDP src2,fpST /* DE C0+i */
3035 %}
3036
3037 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3038 // FADDP src2,ST /* DE C0+i */
3039 emit_opcode(cbuf, 0xDE);
3040 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3041 %}
3042
3043 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3044 // Operand has been loaded into fp ST (stack top)
3045 // FSUB ST,$src1
3046 emit_opcode(cbuf, 0xD8);
3047 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3048
3049 // FDIV
3050 emit_opcode(cbuf, 0xD8);
3051 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3052 %}
3053
3054 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3055 // Operand was loaded from memory into fp ST (stack top)
3056 // FADD ST,$src /* D8 C0+i */
3057 emit_opcode(cbuf, 0xD8);
3058 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3059
3060 // FMUL ST,src2 /* D8 C*+i */
3061 emit_opcode(cbuf, 0xD8);
3062 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3063 %}
3064
3065
3066 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3067 // Operand was loaded from memory into fp ST (stack top)
3068 // FADD ST,$src /* D8 C0+i */
3069 emit_opcode(cbuf, 0xD8);
3070 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3071
3072 // FMULP src2,ST /* DE C8+i */
3073 emit_opcode(cbuf, 0xDE);
3074 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3075 %}
3076
3077 // Atomically load the volatile long
3078 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3079 emit_opcode(cbuf,0xDF);
3080 int rm_byte_opcode = 0x05;
3081 int base = $mem$$base;
3082 int index = $mem$$index;
3083 int scale = $mem$$scale;
3084 int displace = $mem$$disp;
3085 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3086 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3087 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3088 %}
3089
3090 // Volatile Store Long. Must be atomic, so move it into
3091 // the FP TOS and then do a 64-bit FIST. Has to probe the
3092 // target address before the store (for null-ptr checks)
3093 // so the memory operand is used twice in the encoding.
3094 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3095 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3096 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3097 emit_opcode(cbuf,0xDF);
3098 int rm_byte_opcode = 0x07;
3099 int base = $mem$$base;
3100 int index = $mem$$index;
3101 int scale = $mem$$scale;
3102 int displace = $mem$$disp;
3103 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3104 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3105 %}
3106
3107 // Safepoint Poll. This polls the safepoint page, and causes an
3108 // exception if it is not readable. Unfortunately, it kills the condition code
3109 // in the process
3110 // We current use TESTL [spp],EDI
3111 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3112
3113 enc_class Safepoint_Poll() %{
3114 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3115 emit_opcode(cbuf,0x85);
3116 emit_rm (cbuf, 0x0, 0x7, 0x5);
3117 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3118 %}
3119 %}
3120
3121
3122 //----------FRAME--------------------------------------------------------------
3123 // Definition of frame structure and management information.
3124 //
3125 // S T A C K L A Y O U T Allocators stack-slot number
3126 // | (to get allocators register number
3127 // G Owned by | | v add OptoReg::stack0())
3128 // r CALLER | |
3129 // o | +--------+ pad to even-align allocators stack-slot
3130 // w V | pad0 | numbers; owned by CALLER
3131 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3132 // h ^ | in | 5
3133 // | | args | 4 Holes in incoming args owned by SELF
3134 // | | | | 3
3135 // | | +--------+
3136 // V | | old out| Empty on Intel, window on Sparc
3137 // | old |preserve| Must be even aligned.
3138 // | SP-+--------+----> Matcher::_old_SP, even aligned
3139 // | | in | 3 area for Intel ret address
3140 // Owned by |preserve| Empty on Sparc.
3141 // SELF +--------+
3142 // | | pad2 | 2 pad to align old SP
3143 // | +--------+ 1
3144 // | | locks | 0
3145 // | +--------+----> OptoReg::stack0(), even aligned
3146 // | | pad1 | 11 pad to align new SP
3147 // | +--------+
3148 // | | | 10
3149 // | | spills | 9 spills
3150 // V | | 8 (pad0 slot for callee)
3151 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3152 // ^ | out | 7
3153 // | | args | 6 Holes in outgoing args owned by CALLEE
3154 // Owned by +--------+
3155 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3156 // | new |preserve| Must be even-aligned.
3157 // | SP-+--------+----> Matcher::_new_SP, even aligned
3158 // | | |
3159 //
3160 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3161 // known from SELF's arguments and the Java calling convention.
3162 // Region 6-7 is determined per call site.
3163 // Note 2: If the calling convention leaves holes in the incoming argument
3164 // area, those holes are owned by SELF. Holes in the outgoing area
3165 // are owned by the CALLEE. Holes should not be nessecary in the
3166 // incoming area, as the Java calling convention is completely under
3167 // the control of the AD file. Doubles can be sorted and packed to
3168 // avoid holes. Holes in the outgoing arguments may be nessecary for
3169 // varargs C calling conventions.
3170 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3171 // even aligned with pad0 as needed.
3172 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3173 // region 6-11 is even aligned; it may be padded out more so that
3174 // the region from SP to FP meets the minimum stack alignment.
3175
3176 frame %{
3177 // What direction does stack grow in (assumed to be same for C & Java)
3178 stack_direction(TOWARDS_LOW);
3179
3180 // These three registers define part of the calling convention
3181 // between compiled code and the interpreter.
3182 inline_cache_reg(EAX); // Inline Cache Register
3183 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3184
3185 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3186 cisc_spilling_operand_name(indOffset32);
3187
3188 // Number of stack slots consumed by locking an object
3189 sync_stack_slots(1);
3190
3191 // Compiled code's Frame Pointer
3192 frame_pointer(ESP);
3193 // Interpreter stores its frame pointer in a register which is
3194 // stored to the stack by I2CAdaptors.
3195 // I2CAdaptors convert from interpreted java to compiled java.
3196 interpreter_frame_pointer(EBP);
3197
3198 // Stack alignment requirement
3199 // Alignment size in bytes (128-bit -> 16 bytes)
3200 stack_alignment(StackAlignmentInBytes);
3201
3202 // Number of stack slots between incoming argument block and the start of
3203 // a new frame. The PROLOG must add this many slots to the stack. The
3204 // EPILOG must remove this many slots. Intel needs one slot for
3205 // return address and one for rbp, (must save rbp)
3206 in_preserve_stack_slots(2+VerifyStackAtCalls);
3207
3208 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3209 // for calls to C. Supports the var-args backing area for register parms.
3210 varargs_C_out_slots_killed(0);
3211
3212 // The after-PROLOG location of the return address. Location of
3213 // return address specifies a type (REG or STACK) and a number
3214 // representing the register number (i.e. - use a register name) or
3215 // stack slot.
3216 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3217 // Otherwise, it is above the locks and verification slot and alignment word
3218 return_addr(STACK - 1 +
3219 round_to((Compile::current()->in_preserve_stack_slots() +
3220 Compile::current()->fixed_slots()),
3221 stack_alignment_in_slots()));
3222
3223 // Body of function which returns an integer array locating
3224 // arguments either in registers or in stack slots. Passed an array
3225 // of ideal registers called "sig" and a "length" count. Stack-slot
3226 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3227 // arguments for a CALLEE. Incoming stack arguments are
3228 // automatically biased by the preserve_stack_slots field above.
3229 calling_convention %{
3230 // No difference between ingoing/outgoing just pass false
3231 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3232 %}
3233
3234
3235 // Body of function which returns an integer array locating
3236 // arguments either in registers or in stack slots. Passed an array
3237 // of ideal registers called "sig" and a "length" count. Stack-slot
3238 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3239 // arguments for a CALLEE. Incoming stack arguments are
3240 // automatically biased by the preserve_stack_slots field above.
3241 c_calling_convention %{
3242 // This is obviously always outgoing
3243 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3244 %}
3245
3246 // Location of C & interpreter return values
3247 c_return_value %{
3248 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3249 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3250 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3251
3252 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3253 // that C functions return float and double results in XMM0.
3254 if( ideal_reg == Op_RegD && UseSSE>=2 )
3255 return OptoRegPair(XMM0b_num,XMM0_num);
3256 if( ideal_reg == Op_RegF && UseSSE>=2 )
3257 return OptoRegPair(OptoReg::Bad,XMM0_num);
3258
3259 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3260 %}
3261
3262 // Location of return values
3263 return_value %{
3264 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3265 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3266 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3267 if( ideal_reg == Op_RegD && UseSSE>=2 )
3268 return OptoRegPair(XMM0b_num,XMM0_num);
3269 if( ideal_reg == Op_RegF && UseSSE>=1 )
3270 return OptoRegPair(OptoReg::Bad,XMM0_num);
3271 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3272 %}
3273
3274 %}
3275
3276 //----------ATTRIBUTES---------------------------------------------------------
3277 //----------Operand Attributes-------------------------------------------------
3278 op_attrib op_cost(0); // Required cost attribute
3279
3280 //----------Instruction Attributes---------------------------------------------
3281 ins_attrib ins_cost(100); // Required cost attribute
3282 ins_attrib ins_size(8); // Required size attribute (in bits)
3283 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3284 // non-matching short branch variant of some
3285 // long branch?
3286 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3287 // specifies the alignment that some part of the instruction (not
3288 // necessarily the start) requires. If > 1, a compute_padding()
3289 // function must be provided for the instruction
3290
3291 //----------OPERANDS-----------------------------------------------------------
3292 // Operand definitions must precede instruction definitions for correct parsing
3293 // in the ADLC because operands constitute user defined types which are used in
3294 // instruction definitions.
3295
3296 //----------Simple Operands----------------------------------------------------
3297 // Immediate Operands
3298 // Integer Immediate
3299 operand immI() %{
3300 match(ConI);
3301
3302 op_cost(10);
3303 format %{ %}
3304 interface(CONST_INTER);
3305 %}
3306
3307 // Constant for test vs zero
3308 operand immI0() %{
3309 predicate(n->get_int() == 0);
3310 match(ConI);
3311
3312 op_cost(0);
3313 format %{ %}
3314 interface(CONST_INTER);
3315 %}
3316
3317 // Constant for increment
3318 operand immI1() %{
3319 predicate(n->get_int() == 1);
3320 match(ConI);
3321
3322 op_cost(0);
3323 format %{ %}
3324 interface(CONST_INTER);
3325 %}
3326
3327 // Constant for decrement
3328 operand immI_M1() %{
3329 predicate(n->get_int() == -1);
3330 match(ConI);
3331
3332 op_cost(0);
3333 format %{ %}
3334 interface(CONST_INTER);
3335 %}
3336
3337 // Valid scale values for addressing modes
3338 operand immI2() %{
3339 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3340 match(ConI);
3341
3342 format %{ %}
3343 interface(CONST_INTER);
3344 %}
3345
3346 operand immI8() %{
3347 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3348 match(ConI);
3349
3350 op_cost(5);
3351 format %{ %}
3352 interface(CONST_INTER);
3353 %}
3354
3355 operand immI16() %{
3356 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3357 match(ConI);
3358
3359 op_cost(10);
3360 format %{ %}
3361 interface(CONST_INTER);
3362 %}
3363
3364 // Int Immediate non-negative
3365 operand immU31()
3366 %{
3367 predicate(n->get_int() >= 0);
3368 match(ConI);
3369
3370 op_cost(0);
3371 format %{ %}
3372 interface(CONST_INTER);
3373 %}
3374
3375 // Constant for long shifts
3376 operand immI_32() %{
3377 predicate( n->get_int() == 32 );
3378 match(ConI);
3379
3380 op_cost(0);
3381 format %{ %}
3382 interface(CONST_INTER);
3383 %}
3384
3385 operand immI_1_31() %{
3386 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3387 match(ConI);
3388
3389 op_cost(0);
3390 format %{ %}
3391 interface(CONST_INTER);
3392 %}
3393
3394 operand immI_32_63() %{
3395 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3396 match(ConI);
3397 op_cost(0);
3398
3399 format %{ %}
3400 interface(CONST_INTER);
3401 %}
3402
3403 operand immI_1() %{
3404 predicate( n->get_int() == 1 );
3405 match(ConI);
3406
3407 op_cost(0);
3408 format %{ %}
3409 interface(CONST_INTER);
3410 %}
3411
3412 operand immI_2() %{
3413 predicate( n->get_int() == 2 );
3414 match(ConI);
3415
3416 op_cost(0);
3417 format %{ %}
3418 interface(CONST_INTER);
3419 %}
3420
3421 operand immI_3() %{
3422 predicate( n->get_int() == 3 );
3423 match(ConI);
3424
3425 op_cost(0);
3426 format %{ %}
3427 interface(CONST_INTER);
3428 %}
3429
3430 // Pointer Immediate
3431 operand immP() %{
3432 match(ConP);
3433
3434 op_cost(10);
3435 format %{ %}
3436 interface(CONST_INTER);
3437 %}
3438
3439 // NULL Pointer Immediate
3440 operand immP0() %{
3441 predicate( n->get_ptr() == 0 );
3442 match(ConP);
3443 op_cost(0);
3444
3445 format %{ %}
3446 interface(CONST_INTER);
3447 %}
3448
3449 // Long Immediate
3450 operand immL() %{
3451 match(ConL);
3452
3453 op_cost(20);
3454 format %{ %}
3455 interface(CONST_INTER);
3456 %}
3457
3458 // Long Immediate zero
3459 operand immL0() %{
3460 predicate( n->get_long() == 0L );
3461 match(ConL);
3462 op_cost(0);
3463
3464 format %{ %}
3465 interface(CONST_INTER);
3466 %}
3467
3468 // Long Immediate zero
3469 operand immL_M1() %{
3470 predicate( n->get_long() == -1L );
3471 match(ConL);
3472 op_cost(0);
3473
3474 format %{ %}
3475 interface(CONST_INTER);
3476 %}
3477
3478 // Long immediate from 0 to 127.
3479 // Used for a shorter form of long mul by 10.
3480 operand immL_127() %{
3481 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
3482 match(ConL);
3483 op_cost(0);
3484
3485 format %{ %}
3486 interface(CONST_INTER);
3487 %}
3488
3489 // Long Immediate: low 32-bit mask
3490 operand immL_32bits() %{
3491 predicate(n->get_long() == 0xFFFFFFFFL);
3492 match(ConL);
3493 op_cost(0);
3494
3495 format %{ %}
3496 interface(CONST_INTER);
3497 %}
3498
3499 // Long Immediate: low 32-bit mask
3500 operand immL32() %{
3501 predicate(n->get_long() == (int)(n->get_long()));
3502 match(ConL);
3503 op_cost(20);
3504
3505 format %{ %}
3506 interface(CONST_INTER);
3507 %}
3508
3509 //Double Immediate zero
3510 operand immDPR0() %{
3511 // Do additional (and counter-intuitive) test against NaN to work around VC++
3512 // bug that generates code such that NaNs compare equal to 0.0
3513 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
3514 match(ConD);
3515
3516 op_cost(5);
3517 format %{ %}
3518 interface(CONST_INTER);
3519 %}
3520
3521 // Double Immediate one
3522 operand immDPR1() %{
3523 predicate( UseSSE<=1 && n->getd() == 1.0 );
3524 match(ConD);
3525
3526 op_cost(5);
3527 format %{ %}
3528 interface(CONST_INTER);
3529 %}
3530
3531 // Double Immediate
3532 operand immDPR() %{
3533 predicate(UseSSE<=1);
3534 match(ConD);
3535
3536 op_cost(5);
3537 format %{ %}
3538 interface(CONST_INTER);
3539 %}
3540
3541 operand immD() %{
3542 predicate(UseSSE>=2);
3543 match(ConD);
3544
3545 op_cost(5);
3546 format %{ %}
3547 interface(CONST_INTER);
3548 %}
3549
3550 // Double Immediate zero
3551 operand immD0() %{
3552 // Do additional (and counter-intuitive) test against NaN to work around VC++
3553 // bug that generates code such that NaNs compare equal to 0.0 AND do not
3554 // compare equal to -0.0.
3555 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
3556 match(ConD);
3557
3558 format %{ %}
3559 interface(CONST_INTER);
3560 %}
3561
3562 // Float Immediate zero
3563 operand immFPR0() %{
3564 predicate(UseSSE == 0 && n->getf() == 0.0F);
3565 match(ConF);
3566
3567 op_cost(5);
3568 format %{ %}
3569 interface(CONST_INTER);
3570 %}
3571
3572 // Float Immediate one
3573 operand immFPR1() %{
3574 predicate(UseSSE == 0 && n->getf() == 1.0F);
3575 match(ConF);
3576
3577 op_cost(5);
3578 format %{ %}
3579 interface(CONST_INTER);
3580 %}
3581
3582 // Float Immediate
3583 operand immFPR() %{
3584 predicate( UseSSE == 0 );
3585 match(ConF);
3586
3587 op_cost(5);
3588 format %{ %}
3589 interface(CONST_INTER);
3590 %}
3591
3592 // Float Immediate
3593 operand immF() %{
3594 predicate(UseSSE >= 1);
3595 match(ConF);
3596
3597 op_cost(5);
3598 format %{ %}
3599 interface(CONST_INTER);
3600 %}
3601
3602 // Float Immediate zero. Zero and not -0.0
3603 operand immF0() %{
3604 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
3605 match(ConF);
3606
3607 op_cost(5);
3608 format %{ %}
3609 interface(CONST_INTER);
3610 %}
3611
3612 // Immediates for special shifts (sign extend)
3613
3614 // Constants for increment
3615 operand immI_16() %{
3616 predicate( n->get_int() == 16 );
3617 match(ConI);
3618
3619 format %{ %}
3620 interface(CONST_INTER);
3621 %}
3622
3623 operand immI_24() %{
3624 predicate( n->get_int() == 24 );
3625 match(ConI);
3626
3627 format %{ %}
3628 interface(CONST_INTER);
3629 %}
3630
3631 // Constant for byte-wide masking
3632 operand immI_255() %{
3633 predicate( n->get_int() == 255 );
3634 match(ConI);
3635
3636 format %{ %}
3637 interface(CONST_INTER);
3638 %}
3639
3640 // Constant for short-wide masking
3641 operand immI_65535() %{
3642 predicate(n->get_int() == 65535);
3643 match(ConI);
3644
3645 format %{ %}
3646 interface(CONST_INTER);
3647 %}
3648
3649 // Register Operands
3650 // Integer Register
3651 operand rRegI() %{
3652 constraint(ALLOC_IN_RC(int_reg));
3653 match(RegI);
3654 match(xRegI);
3655 match(eAXRegI);
3656 match(eBXRegI);
3657 match(eCXRegI);
3658 match(eDXRegI);
3659 match(eDIRegI);
3660 match(eSIRegI);
3661
3662 format %{ %}
3663 interface(REG_INTER);
3664 %}
3665
3666 // Subset of Integer Register
3667 operand xRegI(rRegI reg) %{
3668 constraint(ALLOC_IN_RC(int_x_reg));
3669 match(reg);
3670 match(eAXRegI);
3671 match(eBXRegI);
3672 match(eCXRegI);
3673 match(eDXRegI);
3674
3675 format %{ %}
3676 interface(REG_INTER);
3677 %}
3678
3679 // Special Registers
3680 operand eAXRegI(xRegI reg) %{
3681 constraint(ALLOC_IN_RC(eax_reg));
3682 match(reg);
3683 match(rRegI);
3684
3685 format %{ "EAX" %}
3686 interface(REG_INTER);
3687 %}
3688
3689 // Special Registers
3690 operand eBXRegI(xRegI reg) %{
3691 constraint(ALLOC_IN_RC(ebx_reg));
3692 match(reg);
3693 match(rRegI);
3694
3695 format %{ "EBX" %}
3696 interface(REG_INTER);
3697 %}
3698
3699 operand eCXRegI(xRegI reg) %{
3700 constraint(ALLOC_IN_RC(ecx_reg));
3701 match(reg);
3702 match(rRegI);
3703
3704 format %{ "ECX" %}
3705 interface(REG_INTER);
3706 %}
3707
3708 operand eDXRegI(xRegI reg) %{
3709 constraint(ALLOC_IN_RC(edx_reg));
3710 match(reg);
3711 match(rRegI);
3712
3713 format %{ "EDX" %}
3714 interface(REG_INTER);
3715 %}
3716
3717 operand eDIRegI(xRegI reg) %{
3718 constraint(ALLOC_IN_RC(edi_reg));
3719 match(reg);
3720 match(rRegI);
3721
3722 format %{ "EDI" %}
3723 interface(REG_INTER);
3724 %}
3725
3726 operand naxRegI() %{
3727 constraint(ALLOC_IN_RC(nax_reg));
3728 match(RegI);
3729 match(eCXRegI);
3730 match(eDXRegI);
3731 match(eSIRegI);
3732 match(eDIRegI);
3733
3734 format %{ %}
3735 interface(REG_INTER);
3736 %}
3737
3738 operand nadxRegI() %{
3739 constraint(ALLOC_IN_RC(nadx_reg));
3740 match(RegI);
3741 match(eBXRegI);
3742 match(eCXRegI);
3743 match(eSIRegI);
3744 match(eDIRegI);
3745
3746 format %{ %}
3747 interface(REG_INTER);
3748 %}
3749
3750 operand ncxRegI() %{
3751 constraint(ALLOC_IN_RC(ncx_reg));
3752 match(RegI);
3753 match(eAXRegI);
3754 match(eDXRegI);
3755 match(eSIRegI);
3756 match(eDIRegI);
3757
3758 format %{ %}
3759 interface(REG_INTER);
3760 %}
3761
3762 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
3763 // //
3764 operand eSIRegI(xRegI reg) %{
3765 constraint(ALLOC_IN_RC(esi_reg));
3766 match(reg);
3767 match(rRegI);
3768
3769 format %{ "ESI" %}
3770 interface(REG_INTER);
3771 %}
3772
3773 // Pointer Register
3774 operand anyRegP() %{
3775 constraint(ALLOC_IN_RC(any_reg));
3776 match(RegP);
3777 match(eAXRegP);
3778 match(eBXRegP);
3779 match(eCXRegP);
3780 match(eDIRegP);
3781 match(eRegP);
3782
3783 format %{ %}
3784 interface(REG_INTER);
3785 %}
3786
3787 operand eRegP() %{
3788 constraint(ALLOC_IN_RC(int_reg));
3789 match(RegP);
3790 match(eAXRegP);
3791 match(eBXRegP);
3792 match(eCXRegP);
3793 match(eDIRegP);
3794
3795 format %{ %}
3796 interface(REG_INTER);
3797 %}
3798
3799 // On windows95, EBP is not safe to use for implicit null tests.
3800 operand eRegP_no_EBP() %{
3801 constraint(ALLOC_IN_RC(int_reg_no_rbp));
3802 match(RegP);
3803 match(eAXRegP);
3804 match(eBXRegP);
3805 match(eCXRegP);
3806 match(eDIRegP);
3807
3808 op_cost(100);
3809 format %{ %}
3810 interface(REG_INTER);
3811 %}
3812
3813 operand naxRegP() %{
3814 constraint(ALLOC_IN_RC(nax_reg));
3815 match(RegP);
3816 match(eBXRegP);
3817 match(eDXRegP);
3818 match(eCXRegP);
3819 match(eSIRegP);
3820 match(eDIRegP);
3821
3822 format %{ %}
3823 interface(REG_INTER);
3824 %}
3825
3826 operand nabxRegP() %{
3827 constraint(ALLOC_IN_RC(nabx_reg));
3828 match(RegP);
3829 match(eCXRegP);
3830 match(eDXRegP);
3831 match(eSIRegP);
3832 match(eDIRegP);
3833
3834 format %{ %}
3835 interface(REG_INTER);
3836 %}
3837
3838 operand pRegP() %{
3839 constraint(ALLOC_IN_RC(p_reg));
3840 match(RegP);
3841 match(eBXRegP);
3842 match(eDXRegP);
3843 match(eSIRegP);
3844 match(eDIRegP);
3845
3846 format %{ %}
3847 interface(REG_INTER);
3848 %}
3849
3850 // Special Registers
3851 // Return a pointer value
3852 operand eAXRegP(eRegP reg) %{
3853 constraint(ALLOC_IN_RC(eax_reg));
3854 match(reg);
3855 format %{ "EAX" %}
3856 interface(REG_INTER);
3857 %}
3858
3859 // Used in AtomicAdd
3860 operand eBXRegP(eRegP reg) %{
3861 constraint(ALLOC_IN_RC(ebx_reg));
3862 match(reg);
3863 format %{ "EBX" %}
3864 interface(REG_INTER);
3865 %}
3866
3867 // Tail-call (interprocedural jump) to interpreter
3868 operand eCXRegP(eRegP reg) %{
3869 constraint(ALLOC_IN_RC(ecx_reg));
3870 match(reg);
3871 format %{ "ECX" %}
3872 interface(REG_INTER);
3873 %}
3874
3875 operand eSIRegP(eRegP reg) %{
3876 constraint(ALLOC_IN_RC(esi_reg));
3877 match(reg);
3878 format %{ "ESI" %}
3879 interface(REG_INTER);
3880 %}
3881
3882 // Used in rep stosw
3883 operand eDIRegP(eRegP reg) %{
3884 constraint(ALLOC_IN_RC(edi_reg));
3885 match(reg);
3886 format %{ "EDI" %}
3887 interface(REG_INTER);
3888 %}
3889
3890 operand eBPRegP() %{
3891 constraint(ALLOC_IN_RC(ebp_reg));
3892 match(RegP);
3893 format %{ "EBP" %}
3894 interface(REG_INTER);
3895 %}
3896
3897 operand eRegL() %{
3898 constraint(ALLOC_IN_RC(long_reg));
3899 match(RegL);
3900 match(eADXRegL);
3901
3902 format %{ %}
3903 interface(REG_INTER);
3904 %}
3905
3906 operand eADXRegL( eRegL reg ) %{
3907 constraint(ALLOC_IN_RC(eadx_reg));
3908 match(reg);
3909
3910 format %{ "EDX:EAX" %}
3911 interface(REG_INTER);
3912 %}
3913
3914 operand eBCXRegL( eRegL reg ) %{
3915 constraint(ALLOC_IN_RC(ebcx_reg));
3916 match(reg);
3917
3918 format %{ "EBX:ECX" %}
3919 interface(REG_INTER);
3920 %}
3921
3922 // Special case for integer high multiply
3923 operand eADXRegL_low_only() %{
3924 constraint(ALLOC_IN_RC(eadx_reg));
3925 match(RegL);
3926
3927 format %{ "EAX" %}
3928 interface(REG_INTER);
3929 %}
3930
3931 // Flags register, used as output of compare instructions
3932 operand eFlagsReg() %{
3933 constraint(ALLOC_IN_RC(int_flags));
3934 match(RegFlags);
3935
3936 format %{ "EFLAGS" %}
3937 interface(REG_INTER);
3938 %}
3939
3940 // Flags register, used as output of FLOATING POINT compare instructions
3941 operand eFlagsRegU() %{
3942 constraint(ALLOC_IN_RC(int_flags));
3943 match(RegFlags);
3944
3945 format %{ "EFLAGS_U" %}
3946 interface(REG_INTER);
3947 %}
3948
3949 operand eFlagsRegUCF() %{
3950 constraint(ALLOC_IN_RC(int_flags));
3951 match(RegFlags);
3952 predicate(false);
3953
3954 format %{ "EFLAGS_U_CF" %}
3955 interface(REG_INTER);
3956 %}
3957
3958 // Condition Code Register used by long compare
3959 operand flagsReg_long_LTGE() %{
3960 constraint(ALLOC_IN_RC(int_flags));
3961 match(RegFlags);
3962 format %{ "FLAGS_LTGE" %}
3963 interface(REG_INTER);
3964 %}
3965 operand flagsReg_long_EQNE() %{
3966 constraint(ALLOC_IN_RC(int_flags));
3967 match(RegFlags);
3968 format %{ "FLAGS_EQNE" %}
3969 interface(REG_INTER);
3970 %}
3971 operand flagsReg_long_LEGT() %{
3972 constraint(ALLOC_IN_RC(int_flags));
3973 match(RegFlags);
3974 format %{ "FLAGS_LEGT" %}
3975 interface(REG_INTER);
3976 %}
3977
3978 // Float register operands
3979 operand regDPR() %{
3980 predicate( UseSSE < 2 );
3981 constraint(ALLOC_IN_RC(fp_dbl_reg));
3982 match(RegD);
3983 match(regDPR1);
3984 match(regDPR2);
3985 format %{ %}
3986 interface(REG_INTER);
3987 %}
3988
3989 operand regDPR1(regDPR reg) %{
3990 predicate( UseSSE < 2 );
3991 constraint(ALLOC_IN_RC(fp_dbl_reg0));
3992 match(reg);
3993 format %{ "FPR1" %}
3994 interface(REG_INTER);
3995 %}
3996
3997 operand regDPR2(regDPR reg) %{
3998 predicate( UseSSE < 2 );
3999 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4000 match(reg);
4001 format %{ "FPR2" %}
4002 interface(REG_INTER);
4003 %}
4004
4005 operand regnotDPR1(regDPR reg) %{
4006 predicate( UseSSE < 2 );
4007 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4008 match(reg);
4009 format %{ %}
4010 interface(REG_INTER);
4011 %}
4012
4013 // Float register operands
4014 operand regFPR() %{
4015 predicate( UseSSE < 2 );
4016 constraint(ALLOC_IN_RC(fp_flt_reg));
4017 match(RegF);
4018 match(regFPR1);
4019 format %{ %}
4020 interface(REG_INTER);
4021 %}
4022
4023 // Float register operands
4024 operand regFPR1(regFPR reg) %{
4025 predicate( UseSSE < 2 );
4026 constraint(ALLOC_IN_RC(fp_flt_reg0));
4027 match(reg);
4028 format %{ "FPR1" %}
4029 interface(REG_INTER);
4030 %}
4031
4032 // XMM Float register operands
4033 operand regF() %{
4034 predicate( UseSSE>=1 );
4035 constraint(ALLOC_IN_RC(float_reg));
4036 match(RegF);
4037 format %{ %}
4038 interface(REG_INTER);
4039 %}
4040
4041 // XMM Double register operands
4042 operand regD() %{
4043 predicate( UseSSE>=2 );
4044 constraint(ALLOC_IN_RC(double_reg));
4045 match(RegD);
4046 format %{ %}
4047 interface(REG_INTER);
4048 %}
4049
4050
4051 //----------Memory Operands----------------------------------------------------
4052 // Direct Memory Operand
4053 operand direct(immP addr) %{
4054 match(addr);
4055
4056 format %{ "[$addr]" %}
4057 interface(MEMORY_INTER) %{
4058 base(0xFFFFFFFF);
4059 index(0x4);
4060 scale(0x0);
4061 disp($addr);
4062 %}
4063 %}
4064
4065 // Indirect Memory Operand
4066 operand indirect(eRegP reg) %{
4067 constraint(ALLOC_IN_RC(int_reg));
4068 match(reg);
4069
4070 format %{ "[$reg]" %}
4071 interface(MEMORY_INTER) %{
4072 base($reg);
4073 index(0x4);
4074 scale(0x0);
4075 disp(0x0);
4076 %}
4077 %}
4078
4079 // Indirect Memory Plus Short Offset Operand
4080 operand indOffset8(eRegP reg, immI8 off) %{
4081 match(AddP reg off);
4082
4083 format %{ "[$reg + $off]" %}
4084 interface(MEMORY_INTER) %{
4085 base($reg);
4086 index(0x4);
4087 scale(0x0);
4088 disp($off);
4089 %}
4090 %}
4091
4092 // Indirect Memory Plus Long Offset Operand
4093 operand indOffset32(eRegP reg, immI off) %{
4094 match(AddP reg off);
4095
4096 format %{ "[$reg + $off]" %}
4097 interface(MEMORY_INTER) %{
4098 base($reg);
4099 index(0x4);
4100 scale(0x0);
4101 disp($off);
4102 %}
4103 %}
4104
4105 // Indirect Memory Plus Long Offset Operand
4106 operand indOffset32X(rRegI reg, immP off) %{
4107 match(AddP off reg);
4108
4109 format %{ "[$reg + $off]" %}
4110 interface(MEMORY_INTER) %{
4111 base($reg);
4112 index(0x4);
4113 scale(0x0);
4114 disp($off);
4115 %}
4116 %}
4117
4118 // Indirect Memory Plus Index Register Plus Offset Operand
4119 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4120 match(AddP (AddP reg ireg) off);
4121
4122 op_cost(10);
4123 format %{"[$reg + $off + $ireg]" %}
4124 interface(MEMORY_INTER) %{
4125 base($reg);
4126 index($ireg);
4127 scale(0x0);
4128 disp($off);
4129 %}
4130 %}
4131
4132 // Indirect Memory Plus Index Register Plus Offset Operand
4133 operand indIndex(eRegP reg, rRegI ireg) %{
4134 match(AddP reg ireg);
4135
4136 op_cost(10);
4137 format %{"[$reg + $ireg]" %}
4138 interface(MEMORY_INTER) %{
4139 base($reg);
4140 index($ireg);
4141 scale(0x0);
4142 disp(0x0);
4143 %}
4144 %}
4145
4146 // // -------------------------------------------------------------------------
4147 // // 486 architecture doesn't support "scale * index + offset" with out a base
4148 // // -------------------------------------------------------------------------
4149 // // Scaled Memory Operands
4150 // // Indirect Memory Times Scale Plus Offset Operand
4151 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4152 // match(AddP off (LShiftI ireg scale));
4153 //
4154 // op_cost(10);
4155 // format %{"[$off + $ireg << $scale]" %}
4156 // interface(MEMORY_INTER) %{
4157 // base(0x4);
4158 // index($ireg);
4159 // scale($scale);
4160 // disp($off);
4161 // %}
4162 // %}
4163
4164 // Indirect Memory Times Scale Plus Index Register
4165 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4166 match(AddP reg (LShiftI ireg scale));
4167
4168 op_cost(10);
4169 format %{"[$reg + $ireg << $scale]" %}
4170 interface(MEMORY_INTER) %{
4171 base($reg);
4172 index($ireg);
4173 scale($scale);
4174 disp(0x0);
4175 %}
4176 %}
4177
4178 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4179 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4180 match(AddP (AddP reg (LShiftI ireg scale)) off);
4181
4182 op_cost(10);
4183 format %{"[$reg + $off + $ireg << $scale]" %}
4184 interface(MEMORY_INTER) %{
4185 base($reg);
4186 index($ireg);
4187 scale($scale);
4188 disp($off);
4189 %}
4190 %}
4191
4192 //----------Load Long Memory Operands------------------------------------------
4193 // The load-long idiom will use it's address expression again after loading
4194 // the first word of the long. If the load-long destination overlaps with
4195 // registers used in the addressing expression, the 2nd half will be loaded
4196 // from a clobbered address. Fix this by requiring that load-long use
4197 // address registers that do not overlap with the load-long target.
4198
4199 // load-long support
4200 operand load_long_RegP() %{
4201 constraint(ALLOC_IN_RC(esi_reg));
4202 match(RegP);
4203 match(eSIRegP);
4204 op_cost(100);
4205 format %{ %}
4206 interface(REG_INTER);
4207 %}
4208
4209 // Indirect Memory Operand Long
4210 operand load_long_indirect(load_long_RegP reg) %{
4211 constraint(ALLOC_IN_RC(esi_reg));
4212 match(reg);
4213
4214 format %{ "[$reg]" %}
4215 interface(MEMORY_INTER) %{
4216 base($reg);
4217 index(0x4);
4218 scale(0x0);
4219 disp(0x0);
4220 %}
4221 %}
4222
4223 // Indirect Memory Plus Long Offset Operand
4224 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4225 match(AddP reg off);
4226
4227 format %{ "[$reg + $off]" %}
4228 interface(MEMORY_INTER) %{
4229 base($reg);
4230 index(0x4);
4231 scale(0x0);
4232 disp($off);
4233 %}
4234 %}
4235
4236 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4237
4238
4239 //----------Special Memory Operands--------------------------------------------
4240 // Stack Slot Operand - This operand is used for loading and storing temporary
4241 // values on the stack where a match requires a value to
4242 // flow through memory.
4243 operand stackSlotP(sRegP reg) %{
4244 constraint(ALLOC_IN_RC(stack_slots));
4245 // No match rule because this operand is only generated in matching
4246 format %{ "[$reg]" %}
4247 interface(MEMORY_INTER) %{
4248 base(0x4); // ESP
4249 index(0x4); // No Index
4250 scale(0x0); // No Scale
4251 disp($reg); // Stack Offset
4252 %}
4253 %}
4254
4255 operand stackSlotI(sRegI reg) %{
4256 constraint(ALLOC_IN_RC(stack_slots));
4257 // No match rule because this operand is only generated in matching
4258 format %{ "[$reg]" %}
4259 interface(MEMORY_INTER) %{
4260 base(0x4); // ESP
4261 index(0x4); // No Index
4262 scale(0x0); // No Scale
4263 disp($reg); // Stack Offset
4264 %}
4265 %}
4266
4267 operand stackSlotF(sRegF reg) %{
4268 constraint(ALLOC_IN_RC(stack_slots));
4269 // No match rule because this operand is only generated in matching
4270 format %{ "[$reg]" %}
4271 interface(MEMORY_INTER) %{
4272 base(0x4); // ESP
4273 index(0x4); // No Index
4274 scale(0x0); // No Scale
4275 disp($reg); // Stack Offset
4276 %}
4277 %}
4278
4279 operand stackSlotD(sRegD reg) %{
4280 constraint(ALLOC_IN_RC(stack_slots));
4281 // No match rule because this operand is only generated in matching
4282 format %{ "[$reg]" %}
4283 interface(MEMORY_INTER) %{
4284 base(0x4); // ESP
4285 index(0x4); // No Index
4286 scale(0x0); // No Scale
4287 disp($reg); // Stack Offset
4288 %}
4289 %}
4290
4291 operand stackSlotL(sRegL reg) %{
4292 constraint(ALLOC_IN_RC(stack_slots));
4293 // No match rule because this operand is only generated in matching
4294 format %{ "[$reg]" %}
4295 interface(MEMORY_INTER) %{
4296 base(0x4); // ESP
4297 index(0x4); // No Index
4298 scale(0x0); // No Scale
4299 disp($reg); // Stack Offset
4300 %}
4301 %}
4302
4303 //----------Memory Operands - Win95 Implicit Null Variants----------------
4304 // Indirect Memory Operand
4305 operand indirect_win95_safe(eRegP_no_EBP reg)
4306 %{
4307 constraint(ALLOC_IN_RC(int_reg));
4308 match(reg);
4309
4310 op_cost(100);
4311 format %{ "[$reg]" %}
4312 interface(MEMORY_INTER) %{
4313 base($reg);
4314 index(0x4);
4315 scale(0x0);
4316 disp(0x0);
4317 %}
4318 %}
4319
4320 // Indirect Memory Plus Short Offset Operand
4321 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4322 %{
4323 match(AddP reg off);
4324
4325 op_cost(100);
4326 format %{ "[$reg + $off]" %}
4327 interface(MEMORY_INTER) %{
4328 base($reg);
4329 index(0x4);
4330 scale(0x0);
4331 disp($off);
4332 %}
4333 %}
4334
4335 // Indirect Memory Plus Long Offset Operand
4336 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4337 %{
4338 match(AddP reg off);
4339
4340 op_cost(100);
4341 format %{ "[$reg + $off]" %}
4342 interface(MEMORY_INTER) %{
4343 base($reg);
4344 index(0x4);
4345 scale(0x0);
4346 disp($off);
4347 %}
4348 %}
4349
4350 // Indirect Memory Plus Index Register Plus Offset Operand
4351 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4352 %{
4353 match(AddP (AddP reg ireg) off);
4354
4355 op_cost(100);
4356 format %{"[$reg + $off + $ireg]" %}
4357 interface(MEMORY_INTER) %{
4358 base($reg);
4359 index($ireg);
4360 scale(0x0);
4361 disp($off);
4362 %}
4363 %}
4364
4365 // Indirect Memory Times Scale Plus Index Register
4366 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4367 %{
4368 match(AddP reg (LShiftI ireg scale));
4369
4370 op_cost(100);
4371 format %{"[$reg + $ireg << $scale]" %}
4372 interface(MEMORY_INTER) %{
4373 base($reg);
4374 index($ireg);
4375 scale($scale);
4376 disp(0x0);
4377 %}
4378 %}
4379
4380 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4381 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4382 %{
4383 match(AddP (AddP reg (LShiftI ireg scale)) off);
4384
4385 op_cost(100);
4386 format %{"[$reg + $off + $ireg << $scale]" %}
4387 interface(MEMORY_INTER) %{
4388 base($reg);
4389 index($ireg);
4390 scale($scale);
4391 disp($off);
4392 %}
4393 %}
4394
4395 //----------Conditional Branch Operands----------------------------------------
4396 // Comparison Op - This is the operation of the comparison, and is limited to
4397 // the following set of codes:
4398 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4399 //
4400 // Other attributes of the comparison, such as unsignedness, are specified
4401 // by the comparison instruction that sets a condition code flags register.
4402 // That result is represented by a flags operand whose subtype is appropriate
4403 // to the unsignedness (etc.) of the comparison.
4404 //
4405 // Later, the instruction which matches both the Comparison Op (a Bool) and
4406 // the flags (produced by the Cmp) specifies the coding of the comparison op
4407 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4408
4409 // Comparision Code
4410 operand cmpOp() %{
4411 match(Bool);
4412
4413 format %{ "" %}
4414 interface(COND_INTER) %{
4415 equal(0x4, "e");
4416 not_equal(0x5, "ne");
4417 less(0xC, "l");
4418 greater_equal(0xD, "ge");
4419 less_equal(0xE, "le");
4420 greater(0xF, "g");
4421 overflow(0x0, "o");
4422 no_overflow(0x1, "no");
4423 %}
4424 %}
4425
4426 // Comparison Code, unsigned compare. Used by FP also, with
4427 // C2 (unordered) turned into GT or LT already. The other bits
4428 // C0 and C3 are turned into Carry & Zero flags.
4429 operand cmpOpU() %{
4430 match(Bool);
4431
4432 format %{ "" %}
4433 interface(COND_INTER) %{
4434 equal(0x4, "e");
4435 not_equal(0x5, "ne");
4436 less(0x2, "b");
4437 greater_equal(0x3, "nb");
4438 less_equal(0x6, "be");
4439 greater(0x7, "nbe");
4440 overflow(0x0, "o");
4441 no_overflow(0x1, "no");
4442 %}
4443 %}
4444
4445 // Floating comparisons that don't require any fixup for the unordered case
4446 operand cmpOpUCF() %{
4447 match(Bool);
4448 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4449 n->as_Bool()->_test._test == BoolTest::ge ||
4450 n->as_Bool()->_test._test == BoolTest::le ||
4451 n->as_Bool()->_test._test == BoolTest::gt);
4452 format %{ "" %}
4453 interface(COND_INTER) %{
4454 equal(0x4, "e");
4455 not_equal(0x5, "ne");
4456 less(0x2, "b");
4457 greater_equal(0x3, "nb");
4458 less_equal(0x6, "be");
4459 greater(0x7, "nbe");
4460 overflow(0x0, "o");
4461 no_overflow(0x1, "no");
4462 %}
4463 %}
4464
4465
4466 // Floating comparisons that can be fixed up with extra conditional jumps
4467 operand cmpOpUCF2() %{
4468 match(Bool);
4469 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4470 n->as_Bool()->_test._test == BoolTest::eq);
4471 format %{ "" %}
4472 interface(COND_INTER) %{
4473 equal(0x4, "e");
4474 not_equal(0x5, "ne");
4475 less(0x2, "b");
4476 greater_equal(0x3, "nb");
4477 less_equal(0x6, "be");
4478 greater(0x7, "nbe");
4479 overflow(0x0, "o");
4480 no_overflow(0x1, "no");
4481 %}
4482 %}
4483
4484 // Comparison Code for FP conditional move
4485 operand cmpOp_fcmov() %{
4486 match(Bool);
4487
4488 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4489 n->as_Bool()->_test._test != BoolTest::no_overflow);
4490 format %{ "" %}
4491 interface(COND_INTER) %{
4492 equal (0x0C8);
4493 not_equal (0x1C8);
4494 less (0x0C0);
4495 greater_equal(0x1C0);
4496 less_equal (0x0D0);
4497 greater (0x1D0);
4498 overflow(0x0, "o"); // not really supported by the instruction
4499 no_overflow(0x1, "no"); // not really supported by the instruction
4500 %}
4501 %}
4502
4503 // Comparision Code used in long compares
4504 operand cmpOp_commute() %{
4505 match(Bool);
4506
4507 format %{ "" %}
4508 interface(COND_INTER) %{
4509 equal(0x4, "e");
4510 not_equal(0x5, "ne");
4511 less(0xF, "g");
4512 greater_equal(0xE, "le");
4513 less_equal(0xD, "ge");
4514 greater(0xC, "l");
4515 overflow(0x0, "o");
4516 no_overflow(0x1, "no");
4517 %}
4518 %}
4519
4520 //----------OPERAND CLASSES----------------------------------------------------
4521 // Operand Classes are groups of operands that are used as to simplify
4522 // instruction definitions by not requiring the AD writer to specify separate
4523 // instructions for every form of operand when the instruction accepts
4524 // multiple operand types with the same basic encoding and format. The classic
4525 // case of this is memory operands.
4526
4527 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
4528 indIndex, indIndexScale, indIndexScaleOffset);
4529
4530 // Long memory operations are encoded in 2 instructions and a +4 offset.
4531 // This means some kind of offset is always required and you cannot use
4532 // an oop as the offset (done when working on static globals).
4533 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
4534 indIndex, indIndexScale, indIndexScaleOffset);
4535
4536
4537 //----------PIPELINE-----------------------------------------------------------
4538 // Rules which define the behavior of the target architectures pipeline.
4539 pipeline %{
4540
4541 //----------ATTRIBUTES---------------------------------------------------------
4542 attributes %{
4543 variable_size_instructions; // Fixed size instructions
4544 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4545 instruction_unit_size = 1; // An instruction is 1 bytes long
4546 instruction_fetch_unit_size = 16; // The processor fetches one line
4547 instruction_fetch_units = 1; // of 16 bytes
4548
4549 // List of nop instructions
4550 nops( MachNop );
4551 %}
4552
4553 //----------RESOURCES----------------------------------------------------------
4554 // Resources are the functional units available to the machine
4555
4556 // Generic P2/P3 pipeline
4557 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4558 // 3 instructions decoded per cycle.
4559 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4560 // 2 ALU op, only ALU0 handles mul/div instructions.
4561 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4562 MS0, MS1, MEM = MS0 | MS1,
4563 BR, FPU,
4564 ALU0, ALU1, ALU = ALU0 | ALU1 );
4565
4566 //----------PIPELINE DESCRIPTION-----------------------------------------------
4567 // Pipeline Description specifies the stages in the machine's pipeline
4568
4569 // Generic P2/P3 pipeline
4570 pipe_desc(S0, S1, S2, S3, S4, S5);
4571
4572 //----------PIPELINE CLASSES---------------------------------------------------
4573 // Pipeline Classes describe the stages in which input and output are
4574 // referenced by the hardware pipeline.
4575
4576 // Naming convention: ialu or fpu
4577 // Then: _reg
4578 // Then: _reg if there is a 2nd register
4579 // Then: _long if it's a pair of instructions implementing a long
4580 // Then: _fat if it requires the big decoder
4581 // Or: _mem if it requires the big decoder and a memory unit.
4582
4583 // Integer ALU reg operation
4584 pipe_class ialu_reg(rRegI dst) %{
4585 single_instruction;
4586 dst : S4(write);
4587 dst : S3(read);
4588 DECODE : S0; // any decoder
4589 ALU : S3; // any alu
4590 %}
4591
4592 // Long ALU reg operation
4593 pipe_class ialu_reg_long(eRegL dst) %{
4594 instruction_count(2);
4595 dst : S4(write);
4596 dst : S3(read);
4597 DECODE : S0(2); // any 2 decoders
4598 ALU : S3(2); // both alus
4599 %}
4600
4601 // Integer ALU reg operation using big decoder
4602 pipe_class ialu_reg_fat(rRegI dst) %{
4603 single_instruction;
4604 dst : S4(write);
4605 dst : S3(read);
4606 D0 : S0; // big decoder only
4607 ALU : S3; // any alu
4608 %}
4609
4610 // Long ALU reg operation using big decoder
4611 pipe_class ialu_reg_long_fat(eRegL dst) %{
4612 instruction_count(2);
4613 dst : S4(write);
4614 dst : S3(read);
4615 D0 : S0(2); // big decoder only; twice
4616 ALU : S3(2); // any 2 alus
4617 %}
4618
4619 // Integer ALU reg-reg operation
4620 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
4621 single_instruction;
4622 dst : S4(write);
4623 src : S3(read);
4624 DECODE : S0; // any decoder
4625 ALU : S3; // any alu
4626 %}
4627
4628 // Long ALU reg-reg operation
4629 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
4630 instruction_count(2);
4631 dst : S4(write);
4632 src : S3(read);
4633 DECODE : S0(2); // any 2 decoders
4634 ALU : S3(2); // both alus
4635 %}
4636
4637 // Integer ALU reg-reg operation
4638 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
4639 single_instruction;
4640 dst : S4(write);
4641 src : S3(read);
4642 D0 : S0; // big decoder only
4643 ALU : S3; // any alu
4644 %}
4645
4646 // Long ALU reg-reg operation
4647 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
4648 instruction_count(2);
4649 dst : S4(write);
4650 src : S3(read);
4651 D0 : S0(2); // big decoder only; twice
4652 ALU : S3(2); // both alus
4653 %}
4654
4655 // Integer ALU reg-mem operation
4656 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
4657 single_instruction;
4658 dst : S5(write);
4659 mem : S3(read);
4660 D0 : S0; // big decoder only
4661 ALU : S4; // any alu
4662 MEM : S3; // any mem
4663 %}
4664
4665 // Long ALU reg-mem operation
4666 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
4667 instruction_count(2);
4668 dst : S5(write);
4669 mem : S3(read);
4670 D0 : S0(2); // big decoder only; twice
4671 ALU : S4(2); // any 2 alus
4672 MEM : S3(2); // both mems
4673 %}
4674
4675 // Integer mem operation (prefetch)
4676 pipe_class ialu_mem(memory mem)
4677 %{
4678 single_instruction;
4679 mem : S3(read);
4680 D0 : S0; // big decoder only
4681 MEM : S3; // any mem
4682 %}
4683
4684 // Integer Store to Memory
4685 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
4686 single_instruction;
4687 mem : S3(read);
4688 src : S5(read);
4689 D0 : S0; // big decoder only
4690 ALU : S4; // any alu
4691 MEM : S3;
4692 %}
4693
4694 // Long Store to Memory
4695 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
4696 instruction_count(2);
4697 mem : S3(read);
4698 src : S5(read);
4699 D0 : S0(2); // big decoder only; twice
4700 ALU : S4(2); // any 2 alus
4701 MEM : S3(2); // Both mems
4702 %}
4703
4704 // Integer Store to Memory
4705 pipe_class ialu_mem_imm(memory mem) %{
4706 single_instruction;
4707 mem : S3(read);
4708 D0 : S0; // big decoder only
4709 ALU : S4; // any alu
4710 MEM : S3;
4711 %}
4712
4713 // Integer ALU0 reg-reg operation
4714 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
4715 single_instruction;
4716 dst : S4(write);
4717 src : S3(read);
4718 D0 : S0; // Big decoder only
4719 ALU0 : S3; // only alu0
4720 %}
4721
4722 // Integer ALU0 reg-mem operation
4723 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
4724 single_instruction;
4725 dst : S5(write);
4726 mem : S3(read);
4727 D0 : S0; // big decoder only
4728 ALU0 : S4; // ALU0 only
4729 MEM : S3; // any mem
4730 %}
4731
4732 // Integer ALU reg-reg operation
4733 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
4734 single_instruction;
4735 cr : S4(write);
4736 src1 : S3(read);
4737 src2 : S3(read);
4738 DECODE : S0; // any decoder
4739 ALU : S3; // any alu
4740 %}
4741
4742 // Integer ALU reg-imm operation
4743 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
4744 single_instruction;
4745 cr : S4(write);
4746 src1 : S3(read);
4747 DECODE : S0; // any decoder
4748 ALU : S3; // any alu
4749 %}
4750
4751 // Integer ALU reg-mem operation
4752 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
4753 single_instruction;
4754 cr : S4(write);
4755 src1 : S3(read);
4756 src2 : S3(read);
4757 D0 : S0; // big decoder only
4758 ALU : S4; // any alu
4759 MEM : S3;
4760 %}
4761
4762 // Conditional move reg-reg
4763 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
4764 instruction_count(4);
4765 y : S4(read);
4766 q : S3(read);
4767 p : S3(read);
4768 DECODE : S0(4); // any decoder
4769 %}
4770
4771 // Conditional move reg-reg
4772 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
4773 single_instruction;
4774 dst : S4(write);
4775 src : S3(read);
4776 cr : S3(read);
4777 DECODE : S0; // any decoder
4778 %}
4779
4780 // Conditional move reg-mem
4781 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
4782 single_instruction;
4783 dst : S4(write);
4784 src : S3(read);
4785 cr : S3(read);
4786 DECODE : S0; // any decoder
4787 MEM : S3;
4788 %}
4789
4790 // Conditional move reg-reg long
4791 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
4792 single_instruction;
4793 dst : S4(write);
4794 src : S3(read);
4795 cr : S3(read);
4796 DECODE : S0(2); // any 2 decoders
4797 %}
4798
4799 // Conditional move double reg-reg
4800 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
4801 single_instruction;
4802 dst : S4(write);
4803 src : S3(read);
4804 cr : S3(read);
4805 DECODE : S0; // any decoder
4806 %}
4807
4808 // Float reg-reg operation
4809 pipe_class fpu_reg(regDPR dst) %{
4810 instruction_count(2);
4811 dst : S3(read);
4812 DECODE : S0(2); // any 2 decoders
4813 FPU : S3;
4814 %}
4815
4816 // Float reg-reg operation
4817 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
4818 instruction_count(2);
4819 dst : S4(write);
4820 src : S3(read);
4821 DECODE : S0(2); // any 2 decoders
4822 FPU : S3;
4823 %}
4824
4825 // Float reg-reg operation
4826 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
4827 instruction_count(3);
4828 dst : S4(write);
4829 src1 : S3(read);
4830 src2 : S3(read);
4831 DECODE : S0(3); // any 3 decoders
4832 FPU : S3(2);
4833 %}
4834
4835 // Float reg-reg operation
4836 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
4837 instruction_count(4);
4838 dst : S4(write);
4839 src1 : S3(read);
4840 src2 : S3(read);
4841 src3 : S3(read);
4842 DECODE : S0(4); // any 3 decoders
4843 FPU : S3(2);
4844 %}
4845
4846 // Float reg-reg operation
4847 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
4848 instruction_count(4);
4849 dst : S4(write);
4850 src1 : S3(read);
4851 src2 : S3(read);
4852 src3 : S3(read);
4853 DECODE : S1(3); // any 3 decoders
4854 D0 : S0; // Big decoder only
4855 FPU : S3(2);
4856 MEM : S3;
4857 %}
4858
4859 // Float reg-mem operation
4860 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
4861 instruction_count(2);
4862 dst : S5(write);
4863 mem : S3(read);
4864 D0 : S0; // big decoder only
4865 DECODE : S1; // any decoder for FPU POP
4866 FPU : S4;
4867 MEM : S3; // any mem
4868 %}
4869
4870 // Float reg-mem operation
4871 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
4872 instruction_count(3);
4873 dst : S5(write);
4874 src1 : S3(read);
4875 mem : S3(read);
4876 D0 : S0; // big decoder only
4877 DECODE : S1(2); // any decoder for FPU POP
4878 FPU : S4;
4879 MEM : S3; // any mem
4880 %}
4881
4882 // Float mem-reg operation
4883 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
4884 instruction_count(2);
4885 src : S5(read);
4886 mem : S3(read);
4887 DECODE : S0; // any decoder for FPU PUSH
4888 D0 : S1; // big decoder only
4889 FPU : S4;
4890 MEM : S3; // any mem
4891 %}
4892
4893 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
4894 instruction_count(3);
4895 src1 : S3(read);
4896 src2 : S3(read);
4897 mem : S3(read);
4898 DECODE : S0(2); // any decoder for FPU PUSH
4899 D0 : S1; // big decoder only
4900 FPU : S4;
4901 MEM : S3; // any mem
4902 %}
4903
4904 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
4905 instruction_count(3);
4906 src1 : S3(read);
4907 src2 : S3(read);
4908 mem : S4(read);
4909 DECODE : S0; // any decoder for FPU PUSH
4910 D0 : S0(2); // big decoder only
4911 FPU : S4;
4912 MEM : S3(2); // any mem
4913 %}
4914
4915 pipe_class fpu_mem_mem(memory dst, memory src1) %{
4916 instruction_count(2);
4917 src1 : S3(read);
4918 dst : S4(read);
4919 D0 : S0(2); // big decoder only
4920 MEM : S3(2); // any mem
4921 %}
4922
4923 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
4924 instruction_count(3);
4925 src1 : S3(read);
4926 src2 : S3(read);
4927 dst : S4(read);
4928 D0 : S0(3); // big decoder only
4929 FPU : S4;
4930 MEM : S3(3); // any mem
4931 %}
4932
4933 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
4934 instruction_count(3);
4935 src1 : S4(read);
4936 mem : S4(read);
4937 DECODE : S0; // any decoder for FPU PUSH
4938 D0 : S0(2); // big decoder only
4939 FPU : S4;
4940 MEM : S3(2); // any mem
4941 %}
4942
4943 // Float load constant
4944 pipe_class fpu_reg_con(regDPR dst) %{
4945 instruction_count(2);
4946 dst : S5(write);
4947 D0 : S0; // big decoder only for the load
4948 DECODE : S1; // any decoder for FPU POP
4949 FPU : S4;
4950 MEM : S3; // any mem
4951 %}
4952
4953 // Float load constant
4954 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
4955 instruction_count(3);
4956 dst : S5(write);
4957 src : S3(read);
4958 D0 : S0; // big decoder only for the load
4959 DECODE : S1(2); // any decoder for FPU POP
4960 FPU : S4;
4961 MEM : S3; // any mem
4962 %}
4963
4964 // UnConditional branch
4965 pipe_class pipe_jmp( label labl ) %{
4966 single_instruction;
4967 BR : S3;
4968 %}
4969
4970 // Conditional branch
4971 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
4972 single_instruction;
4973 cr : S1(read);
4974 BR : S3;
4975 %}
4976
4977 // Allocation idiom
4978 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
4979 instruction_count(1); force_serialization;
4980 fixed_latency(6);
4981 heap_ptr : S3(read);
4982 DECODE : S0(3);
4983 D0 : S2;
4984 MEM : S3;
4985 ALU : S3(2);
4986 dst : S5(write);
4987 BR : S5;
4988 %}
4989
4990 // Generic big/slow expanded idiom
4991 pipe_class pipe_slow( ) %{
4992 instruction_count(10); multiple_bundles; force_serialization;
4993 fixed_latency(100);
4994 D0 : S0(2);
4995 MEM : S3(2);
4996 %}
4997
4998 // The real do-nothing guy
4999 pipe_class empty( ) %{
5000 instruction_count(0);
5001 %}
5002
5003 // Define the class for the Nop node
5004 define %{
5005 MachNop = empty;
5006 %}
5007
5008 %}
5009
5010 //----------INSTRUCTIONS-------------------------------------------------------
5011 //
5012 // match -- States which machine-independent subtree may be replaced
5013 // by this instruction.
5014 // ins_cost -- The estimated cost of this instruction is used by instruction
5015 // selection to identify a minimum cost tree of machine
5016 // instructions that matches a tree of machine-independent
5017 // instructions.
5018 // format -- A string providing the disassembly for this instruction.
5019 // The value of an instruction's operand may be inserted
5020 // by referring to it with a '$' prefix.
5021 // opcode -- Three instruction opcodes may be provided. These are referred
5022 // to within an encode class as $primary, $secondary, and $tertiary
5023 // respectively. The primary opcode is commonly used to
5024 // indicate the type of machine instruction, while secondary
5025 // and tertiary are often used for prefix options or addressing
5026 // modes.
5027 // ins_encode -- A list of encode classes with parameters. The encode class
5028 // name must have been defined in an 'enc_class' specification
5029 // in the encode section of the architecture description.
5030
5031 //----------BSWAP-Instruction--------------------------------------------------
5032 instruct bytes_reverse_int(rRegI dst) %{
5033 match(Set dst (ReverseBytesI dst));
5034
5035 format %{ "BSWAP $dst" %}
5036 opcode(0x0F, 0xC8);
5037 ins_encode( OpcP, OpcSReg(dst) );
5038 ins_pipe( ialu_reg );
5039 %}
5040
5041 instruct bytes_reverse_long(eRegL dst) %{
5042 match(Set dst (ReverseBytesL dst));
5043
5044 format %{ "BSWAP $dst.lo\n\t"
5045 "BSWAP $dst.hi\n\t"
5046 "XCHG $dst.lo $dst.hi" %}
5047
5048 ins_cost(125);
5049 ins_encode( bswap_long_bytes(dst) );
5050 ins_pipe( ialu_reg_reg);
5051 %}
5052
5053 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5054 match(Set dst (ReverseBytesUS dst));
5055 effect(KILL cr);
5056
5057 format %{ "BSWAP $dst\n\t"
5058 "SHR $dst,16\n\t" %}
5059 ins_encode %{
5060 __ bswapl($dst$$Register);
5061 __ shrl($dst$$Register, 16);
5062 %}
5063 ins_pipe( ialu_reg );
5064 %}
5065
5066 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5067 match(Set dst (ReverseBytesS dst));
5068 effect(KILL cr);
5069
5070 format %{ "BSWAP $dst\n\t"
5071 "SAR $dst,16\n\t" %}
5072 ins_encode %{
5073 __ bswapl($dst$$Register);
5074 __ sarl($dst$$Register, 16);
5075 %}
5076 ins_pipe( ialu_reg );
5077 %}
5078
5079
5080 //---------- Zeros Count Instructions ------------------------------------------
5081
5082 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5083 predicate(UseCountLeadingZerosInstruction);
5084 match(Set dst (CountLeadingZerosI src));
5085 effect(KILL cr);
5086
5087 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5088 ins_encode %{
5089 __ lzcntl($dst$$Register, $src$$Register);
5090 %}
5091 ins_pipe(ialu_reg);
5092 %}
5093
5094 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5095 predicate(!UseCountLeadingZerosInstruction);
5096 match(Set dst (CountLeadingZerosI src));
5097 effect(KILL cr);
5098
5099 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5100 "JNZ skip\n\t"
5101 "MOV $dst, -1\n"
5102 "skip:\n\t"
5103 "NEG $dst\n\t"
5104 "ADD $dst, 31" %}
5105 ins_encode %{
5106 Register Rdst = $dst$$Register;
5107 Register Rsrc = $src$$Register;
5108 Label skip;
5109 __ bsrl(Rdst, Rsrc);
5110 __ jccb(Assembler::notZero, skip);
5111 __ movl(Rdst, -1);
5112 __ bind(skip);
5113 __ negl(Rdst);
5114 __ addl(Rdst, BitsPerInt - 1);
5115 %}
5116 ins_pipe(ialu_reg);
5117 %}
5118
5119 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5120 predicate(UseCountLeadingZerosInstruction);
5121 match(Set dst (CountLeadingZerosL src));
5122 effect(TEMP dst, KILL cr);
5123
5124 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5125 "JNC done\n\t"
5126 "LZCNT $dst, $src.lo\n\t"
5127 "ADD $dst, 32\n"
5128 "done:" %}
5129 ins_encode %{
5130 Register Rdst = $dst$$Register;
5131 Register Rsrc = $src$$Register;
5132 Label done;
5133 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5134 __ jccb(Assembler::carryClear, done);
5135 __ lzcntl(Rdst, Rsrc);
5136 __ addl(Rdst, BitsPerInt);
5137 __ bind(done);
5138 %}
5139 ins_pipe(ialu_reg);
5140 %}
5141
5142 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5143 predicate(!UseCountLeadingZerosInstruction);
5144 match(Set dst (CountLeadingZerosL src));
5145 effect(TEMP dst, KILL cr);
5146
5147 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5148 "JZ msw_is_zero\n\t"
5149 "ADD $dst, 32\n\t"
5150 "JMP not_zero\n"
5151 "msw_is_zero:\n\t"
5152 "BSR $dst, $src.lo\n\t"
5153 "JNZ not_zero\n\t"
5154 "MOV $dst, -1\n"
5155 "not_zero:\n\t"
5156 "NEG $dst\n\t"
5157 "ADD $dst, 63\n" %}
5158 ins_encode %{
5159 Register Rdst = $dst$$Register;
5160 Register Rsrc = $src$$Register;
5161 Label msw_is_zero;
5162 Label not_zero;
5163 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5164 __ jccb(Assembler::zero, msw_is_zero);
5165 __ addl(Rdst, BitsPerInt);
5166 __ jmpb(not_zero);
5167 __ bind(msw_is_zero);
5168 __ bsrl(Rdst, Rsrc);
5169 __ jccb(Assembler::notZero, not_zero);
5170 __ movl(Rdst, -1);
5171 __ bind(not_zero);
5172 __ negl(Rdst);
5173 __ addl(Rdst, BitsPerLong - 1);
5174 %}
5175 ins_pipe(ialu_reg);
5176 %}
5177
5178 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5179 match(Set dst (CountTrailingZerosI src));
5180 effect(KILL cr);
5181
5182 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5183 "JNZ done\n\t"
5184 "MOV $dst, 32\n"
5185 "done:" %}
5186 ins_encode %{
5187 Register Rdst = $dst$$Register;
5188 Label done;
5189 __ bsfl(Rdst, $src$$Register);
5190 __ jccb(Assembler::notZero, done);
5191 __ movl(Rdst, BitsPerInt);
5192 __ bind(done);
5193 %}
5194 ins_pipe(ialu_reg);
5195 %}
5196
5197 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5198 match(Set dst (CountTrailingZerosL src));
5199 effect(TEMP dst, KILL cr);
5200
5201 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5202 "JNZ done\n\t"
5203 "BSF $dst, $src.hi\n\t"
5204 "JNZ msw_not_zero\n\t"
5205 "MOV $dst, 32\n"
5206 "msw_not_zero:\n\t"
5207 "ADD $dst, 32\n"
5208 "done:" %}
5209 ins_encode %{
5210 Register Rdst = $dst$$Register;
5211 Register Rsrc = $src$$Register;
5212 Label msw_not_zero;
5213 Label done;
5214 __ bsfl(Rdst, Rsrc);
5215 __ jccb(Assembler::notZero, done);
5216 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5217 __ jccb(Assembler::notZero, msw_not_zero);
5218 __ movl(Rdst, BitsPerInt);
5219 __ bind(msw_not_zero);
5220 __ addl(Rdst, BitsPerInt);
5221 __ bind(done);
5222 %}
5223 ins_pipe(ialu_reg);
5224 %}
5225
5226
5227 //---------- Population Count Instructions -------------------------------------
5228
5229 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5230 predicate(UsePopCountInstruction);
5231 match(Set dst (PopCountI src));
5232 effect(KILL cr);
5233
5234 format %{ "POPCNT $dst, $src" %}
5235 ins_encode %{
5236 __ popcntl($dst$$Register, $src$$Register);
5237 %}
5238 ins_pipe(ialu_reg);
5239 %}
5240
5241 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5242 predicate(UsePopCountInstruction);
5243 match(Set dst (PopCountI (LoadI mem)));
5244 effect(KILL cr);
5245
5246 format %{ "POPCNT $dst, $mem" %}
5247 ins_encode %{
5248 __ popcntl($dst$$Register, $mem$$Address);
5249 %}
5250 ins_pipe(ialu_reg);
5251 %}
5252
5253 // Note: Long.bitCount(long) returns an int.
5254 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5255 predicate(UsePopCountInstruction);
5256 match(Set dst (PopCountL src));
5257 effect(KILL cr, TEMP tmp, TEMP dst);
5258
5259 format %{ "POPCNT $dst, $src.lo\n\t"
5260 "POPCNT $tmp, $src.hi\n\t"
5261 "ADD $dst, $tmp" %}
5262 ins_encode %{
5263 __ popcntl($dst$$Register, $src$$Register);
5264 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5265 __ addl($dst$$Register, $tmp$$Register);
5266 %}
5267 ins_pipe(ialu_reg);
5268 %}
5269
5270 // Note: Long.bitCount(long) returns an int.
5271 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5272 predicate(UsePopCountInstruction);
5273 match(Set dst (PopCountL (LoadL mem)));
5274 effect(KILL cr, TEMP tmp, TEMP dst);
5275
5276 format %{ "POPCNT $dst, $mem\n\t"
5277 "POPCNT $tmp, $mem+4\n\t"
5278 "ADD $dst, $tmp" %}
5279 ins_encode %{
5280 //__ popcntl($dst$$Register, $mem$$Address$$first);
5281 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5282 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5283 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5284 __ addl($dst$$Register, $tmp$$Register);
5285 %}
5286 ins_pipe(ialu_reg);
5287 %}
5288
5289
5290 //----------Load/Store/Move Instructions---------------------------------------
5291 //----------Load Instructions--------------------------------------------------
5292 // Load Byte (8bit signed)
5293 instruct loadB(xRegI dst, memory mem) %{
5294 match(Set dst (LoadB mem));
5295
5296 ins_cost(125);
5297 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5298
5299 ins_encode %{
5300 __ movsbl($dst$$Register, $mem$$Address);
5301 %}
5302
5303 ins_pipe(ialu_reg_mem);
5304 %}
5305
5306 // Load Byte (8bit signed) into Long Register
5307 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5308 match(Set dst (ConvI2L (LoadB mem)));
5309 effect(KILL cr);
5310
5311 ins_cost(375);
5312 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5313 "MOV $dst.hi,$dst.lo\n\t"
5314 "SAR $dst.hi,7" %}
5315
5316 ins_encode %{
5317 __ movsbl($dst$$Register, $mem$$Address);
5318 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5319 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5320 %}
5321
5322 ins_pipe(ialu_reg_mem);
5323 %}
5324
5325 // Load Unsigned Byte (8bit UNsigned)
5326 instruct loadUB(xRegI dst, memory mem) %{
5327 match(Set dst (LoadUB mem));
5328
5329 ins_cost(125);
5330 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5331
5332 ins_encode %{
5333 __ movzbl($dst$$Register, $mem$$Address);
5334 %}
5335
5336 ins_pipe(ialu_reg_mem);
5337 %}
5338
5339 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5340 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5341 match(Set dst (ConvI2L (LoadUB mem)));
5342 effect(KILL cr);
5343
5344 ins_cost(250);
5345 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5346 "XOR $dst.hi,$dst.hi" %}
5347
5348 ins_encode %{
5349 Register Rdst = $dst$$Register;
5350 __ movzbl(Rdst, $mem$$Address);
5351 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5352 %}
5353
5354 ins_pipe(ialu_reg_mem);
5355 %}
5356
5357 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5358 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5359 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5360 effect(KILL cr);
5361
5362 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5363 "XOR $dst.hi,$dst.hi\n\t"
5364 "AND $dst.lo,$mask" %}
5365 ins_encode %{
5366 Register Rdst = $dst$$Register;
5367 __ movzbl(Rdst, $mem$$Address);
5368 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5369 __ andl(Rdst, $mask$$constant);
5370 %}
5371 ins_pipe(ialu_reg_mem);
5372 %}
5373
5374 // Load Short (16bit signed)
5375 instruct loadS(rRegI dst, memory mem) %{
5376 match(Set dst (LoadS mem));
5377
5378 ins_cost(125);
5379 format %{ "MOVSX $dst,$mem\t# short" %}
5380
5381 ins_encode %{
5382 __ movswl($dst$$Register, $mem$$Address);
5383 %}
5384
5385 ins_pipe(ialu_reg_mem);
5386 %}
5387
5388 // Load Short (16 bit signed) to Byte (8 bit signed)
5389 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5390 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5391
5392 ins_cost(125);
5393 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5394 ins_encode %{
5395 __ movsbl($dst$$Register, $mem$$Address);
5396 %}
5397 ins_pipe(ialu_reg_mem);
5398 %}
5399
5400 // Load Short (16bit signed) into Long Register
5401 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5402 match(Set dst (ConvI2L (LoadS mem)));
5403 effect(KILL cr);
5404
5405 ins_cost(375);
5406 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5407 "MOV $dst.hi,$dst.lo\n\t"
5408 "SAR $dst.hi,15" %}
5409
5410 ins_encode %{
5411 __ movswl($dst$$Register, $mem$$Address);
5412 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5413 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5414 %}
5415
5416 ins_pipe(ialu_reg_mem);
5417 %}
5418
5419 // Load Unsigned Short/Char (16bit unsigned)
5420 instruct loadUS(rRegI dst, memory mem) %{
5421 match(Set dst (LoadUS mem));
5422
5423 ins_cost(125);
5424 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5425
5426 ins_encode %{
5427 __ movzwl($dst$$Register, $mem$$Address);
5428 %}
5429
5430 ins_pipe(ialu_reg_mem);
5431 %}
5432
5433 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5434 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5435 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5436
5437 ins_cost(125);
5438 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5439 ins_encode %{
5440 __ movsbl($dst$$Register, $mem$$Address);
5441 %}
5442 ins_pipe(ialu_reg_mem);
5443 %}
5444
5445 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5446 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5447 match(Set dst (ConvI2L (LoadUS mem)));
5448 effect(KILL cr);
5449
5450 ins_cost(250);
5451 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5452 "XOR $dst.hi,$dst.hi" %}
5453
5454 ins_encode %{
5455 __ movzwl($dst$$Register, $mem$$Address);
5456 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5457 %}
5458
5459 ins_pipe(ialu_reg_mem);
5460 %}
5461
5462 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5463 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5464 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5465 effect(KILL cr);
5466
5467 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
5468 "XOR $dst.hi,$dst.hi" %}
5469 ins_encode %{
5470 Register Rdst = $dst$$Register;
5471 __ movzbl(Rdst, $mem$$Address);
5472 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5473 %}
5474 ins_pipe(ialu_reg_mem);
5475 %}
5476
5477 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
5478 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
5479 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5480 effect(KILL cr);
5481
5482 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
5483 "XOR $dst.hi,$dst.hi\n\t"
5484 "AND $dst.lo,$mask" %}
5485 ins_encode %{
5486 Register Rdst = $dst$$Register;
5487 __ movzwl(Rdst, $mem$$Address);
5488 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5489 __ andl(Rdst, $mask$$constant);
5490 %}
5491 ins_pipe(ialu_reg_mem);
5492 %}
5493
5494 // Load Integer
5495 instruct loadI(rRegI dst, memory mem) %{
5496 match(Set dst (LoadI mem));
5497
5498 ins_cost(125);
5499 format %{ "MOV $dst,$mem\t# int" %}
5500
5501 ins_encode %{
5502 __ movl($dst$$Register, $mem$$Address);
5503 %}
5504
5505 ins_pipe(ialu_reg_mem);
5506 %}
5507
5508 // Load Integer (32 bit signed) to Byte (8 bit signed)
5509 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5510 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5511
5512 ins_cost(125);
5513 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
5514 ins_encode %{
5515 __ movsbl($dst$$Register, $mem$$Address);
5516 %}
5517 ins_pipe(ialu_reg_mem);
5518 %}
5519
5520 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5521 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5522 match(Set dst (AndI (LoadI mem) mask));
5523
5524 ins_cost(125);
5525 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
5526 ins_encode %{
5527 __ movzbl($dst$$Register, $mem$$Address);
5528 %}
5529 ins_pipe(ialu_reg_mem);
5530 %}
5531
5532 // Load Integer (32 bit signed) to Short (16 bit signed)
5533 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5534 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5535
5536 ins_cost(125);
5537 format %{ "MOVSX $dst, $mem\t# int -> short" %}
5538 ins_encode %{
5539 __ movswl($dst$$Register, $mem$$Address);
5540 %}
5541 ins_pipe(ialu_reg_mem);
5542 %}
5543
5544 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5545 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5546 match(Set dst (AndI (LoadI mem) mask));
5547
5548 ins_cost(125);
5549 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
5550 ins_encode %{
5551 __ movzwl($dst$$Register, $mem$$Address);
5552 %}
5553 ins_pipe(ialu_reg_mem);
5554 %}
5555
5556 // Load Integer into Long Register
5557 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
5558 match(Set dst (ConvI2L (LoadI mem)));
5559 effect(KILL cr);
5560
5561 ins_cost(375);
5562 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
5563 "MOV $dst.hi,$dst.lo\n\t"
5564 "SAR $dst.hi,31" %}
5565
5566 ins_encode %{
5567 __ movl($dst$$Register, $mem$$Address);
5568 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5569 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
5570 %}
5571
5572 ins_pipe(ialu_reg_mem);
5573 %}
5574
5575 // Load Integer with mask 0xFF into Long Register
5576 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
5577 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5578 effect(KILL cr);
5579
5580 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
5581 "XOR $dst.hi,$dst.hi" %}
5582 ins_encode %{
5583 Register Rdst = $dst$$Register;
5584 __ movzbl(Rdst, $mem$$Address);
5585 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5586 %}
5587 ins_pipe(ialu_reg_mem);
5588 %}
5589
5590 // Load Integer with mask 0xFFFF into Long Register
5591 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
5592 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5593 effect(KILL cr);
5594
5595 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
5596 "XOR $dst.hi,$dst.hi" %}
5597 ins_encode %{
5598 Register Rdst = $dst$$Register;
5599 __ movzwl(Rdst, $mem$$Address);
5600 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5601 %}
5602 ins_pipe(ialu_reg_mem);
5603 %}
5604
5605 // Load Integer with 31-bit mask into Long Register
5606 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{
5607 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5608 effect(KILL cr);
5609
5610 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t"
5611 "XOR $dst.hi,$dst.hi\n\t"
5612 "AND $dst.lo,$mask" %}
5613 ins_encode %{
5614 Register Rdst = $dst$$Register;
5615 __ movl(Rdst, $mem$$Address);
5616 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5617 __ andl(Rdst, $mask$$constant);
5618 %}
5619 ins_pipe(ialu_reg_mem);
5620 %}
5621
5622 // Load Unsigned Integer into Long Register
5623 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
5624 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5625 effect(KILL cr);
5626
5627 ins_cost(250);
5628 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
5629 "XOR $dst.hi,$dst.hi" %}
5630
5631 ins_encode %{
5632 __ movl($dst$$Register, $mem$$Address);
5633 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5634 %}
5635
5636 ins_pipe(ialu_reg_mem);
5637 %}
5638
5639 // Load Long. Cannot clobber address while loading, so restrict address
5640 // register to ESI
5641 instruct loadL(eRegL dst, load_long_memory mem) %{
5642 predicate(!((LoadLNode*)n)->require_atomic_access());
5643 match(Set dst (LoadL mem));
5644
5645 ins_cost(250);
5646 format %{ "MOV $dst.lo,$mem\t# long\n\t"
5647 "MOV $dst.hi,$mem+4" %}
5648
5649 ins_encode %{
5650 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
5651 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
5652 __ movl($dst$$Register, Amemlo);
5653 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
5654 %}
5655
5656 ins_pipe(ialu_reg_long_mem);
5657 %}
5658
5659 // Volatile Load Long. Must be atomic, so do 64-bit FILD
5660 // then store it down to the stack and reload on the int
5661 // side.
5662 instruct loadL_volatile(stackSlotL dst, memory mem) %{
5663 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
5664 match(Set dst (LoadL mem));
5665
5666 ins_cost(200);
5667 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
5668 "FISTp $dst" %}
5669 ins_encode(enc_loadL_volatile(mem,dst));
5670 ins_pipe( fpu_reg_mem );
5671 %}
5672
5673 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
5674 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
5675 match(Set dst (LoadL mem));
5676 effect(TEMP tmp);
5677 ins_cost(180);
5678 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
5679 "MOVSD $dst,$tmp" %}
5680 ins_encode %{
5681 __ movdbl($tmp$$XMMRegister, $mem$$Address);
5682 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
5683 %}
5684 ins_pipe( pipe_slow );
5685 %}
5686
5687 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
5688 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
5689 match(Set dst (LoadL mem));
5690 effect(TEMP tmp);
5691 ins_cost(160);
5692 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
5693 "MOVD $dst.lo,$tmp\n\t"
5694 "PSRLQ $tmp,32\n\t"
5695 "MOVD $dst.hi,$tmp" %}
5696 ins_encode %{
5697 __ movdbl($tmp$$XMMRegister, $mem$$Address);
5698 __ movdl($dst$$Register, $tmp$$XMMRegister);
5699 __ psrlq($tmp$$XMMRegister, 32);
5700 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
5701 %}
5702 ins_pipe( pipe_slow );
5703 %}
5704
5705 // Load Range
5706 instruct loadRange(rRegI dst, memory mem) %{
5707 match(Set dst (LoadRange mem));
5708
5709 ins_cost(125);
5710 format %{ "MOV $dst,$mem" %}
5711 opcode(0x8B);
5712 ins_encode( OpcP, RegMem(dst,mem));
5713 ins_pipe( ialu_reg_mem );
5714 %}
5715
5716
5717 // Load Pointer
5718 instruct loadP(eRegP dst, memory mem) %{
5719 match(Set dst (LoadP mem));
5720
5721 ins_cost(125);
5722 format %{ "MOV $dst,$mem" %}
5723 opcode(0x8B);
5724 ins_encode( OpcP, RegMem(dst,mem));
5725 ins_pipe( ialu_reg_mem );
5726 %}
5727
5728 // Load Klass Pointer
5729 instruct loadKlass(eRegP dst, memory mem) %{
5730 match(Set dst (LoadKlass mem));
5731
5732 ins_cost(125);
5733 format %{ "MOV $dst,$mem" %}
5734 opcode(0x8B);
5735 ins_encode( OpcP, RegMem(dst,mem));
5736 ins_pipe( ialu_reg_mem );
5737 %}
5738
5739 // Load Double
5740 instruct loadDPR(regDPR dst, memory mem) %{
5741 predicate(UseSSE<=1);
5742 match(Set dst (LoadD mem));
5743
5744 ins_cost(150);
5745 format %{ "FLD_D ST,$mem\n\t"
5746 "FSTP $dst" %}
5747 opcode(0xDD); /* DD /0 */
5748 ins_encode( OpcP, RMopc_Mem(0x00,mem),
5749 Pop_Reg_DPR(dst) );
5750 ins_pipe( fpu_reg_mem );
5751 %}
5752
5753 // Load Double to XMM
5754 instruct loadD(regD dst, memory mem) %{
5755 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
5756 match(Set dst (LoadD mem));
5757 ins_cost(145);
5758 format %{ "MOVSD $dst,$mem" %}
5759 ins_encode %{
5760 __ movdbl ($dst$$XMMRegister, $mem$$Address);
5761 %}
5762 ins_pipe( pipe_slow );
5763 %}
5764
5765 instruct loadD_partial(regD dst, memory mem) %{
5766 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
5767 match(Set dst (LoadD mem));
5768 ins_cost(145);
5769 format %{ "MOVLPD $dst,$mem" %}
5770 ins_encode %{
5771 __ movdbl ($dst$$XMMRegister, $mem$$Address);
5772 %}
5773 ins_pipe( pipe_slow );
5774 %}
5775
5776 // Load to XMM register (single-precision floating point)
5777 // MOVSS instruction
5778 instruct loadF(regF dst, memory mem) %{
5779 predicate(UseSSE>=1);
5780 match(Set dst (LoadF mem));
5781 ins_cost(145);
5782 format %{ "MOVSS $dst,$mem" %}
5783 ins_encode %{
5784 __ movflt ($dst$$XMMRegister, $mem$$Address);
5785 %}
5786 ins_pipe( pipe_slow );
5787 %}
5788
5789 // Load Float
5790 instruct loadFPR(regFPR dst, memory mem) %{
5791 predicate(UseSSE==0);
5792 match(Set dst (LoadF mem));
5793
5794 ins_cost(150);
5795 format %{ "FLD_S ST,$mem\n\t"
5796 "FSTP $dst" %}
5797 opcode(0xD9); /* D9 /0 */
5798 ins_encode( OpcP, RMopc_Mem(0x00,mem),
5799 Pop_Reg_FPR(dst) );
5800 ins_pipe( fpu_reg_mem );
5801 %}
5802
5803 // Load Effective Address
5804 instruct leaP8(eRegP dst, indOffset8 mem) %{
5805 match(Set dst mem);
5806
5807 ins_cost(110);
5808 format %{ "LEA $dst,$mem" %}
5809 opcode(0x8D);
5810 ins_encode( OpcP, RegMem(dst,mem));
5811 ins_pipe( ialu_reg_reg_fat );
5812 %}
5813
5814 instruct leaP32(eRegP dst, indOffset32 mem) %{
5815 match(Set dst mem);
5816
5817 ins_cost(110);
5818 format %{ "LEA $dst,$mem" %}
5819 opcode(0x8D);
5820 ins_encode( OpcP, RegMem(dst,mem));
5821 ins_pipe( ialu_reg_reg_fat );
5822 %}
5823
5824 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
5825 match(Set dst mem);
5826
5827 ins_cost(110);
5828 format %{ "LEA $dst,$mem" %}
5829 opcode(0x8D);
5830 ins_encode( OpcP, RegMem(dst,mem));
5831 ins_pipe( ialu_reg_reg_fat );
5832 %}
5833
5834 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
5835 match(Set dst mem);
5836
5837 ins_cost(110);
5838 format %{ "LEA $dst,$mem" %}
5839 opcode(0x8D);
5840 ins_encode( OpcP, RegMem(dst,mem));
5841 ins_pipe( ialu_reg_reg_fat );
5842 %}
5843
5844 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
5845 match(Set dst mem);
5846
5847 ins_cost(110);
5848 format %{ "LEA $dst,$mem" %}
5849 opcode(0x8D);
5850 ins_encode( OpcP, RegMem(dst,mem));
5851 ins_pipe( ialu_reg_reg_fat );
5852 %}
5853
5854 // Load Constant
5855 instruct loadConI(rRegI dst, immI src) %{
5856 match(Set dst src);
5857
5858 format %{ "MOV $dst,$src" %}
5859 ins_encode( LdImmI(dst, src) );
5860 ins_pipe( ialu_reg_fat );
5861 %}
5862
5863 // Load Constant zero
5864 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
5865 match(Set dst src);
5866 effect(KILL cr);
5867
5868 ins_cost(50);
5869 format %{ "XOR $dst,$dst" %}
5870 opcode(0x33); /* + rd */
5871 ins_encode( OpcP, RegReg( dst, dst ) );
5872 ins_pipe( ialu_reg );
5873 %}
5874
5875 instruct loadConP(eRegP dst, immP src) %{
5876 match(Set dst src);
5877
5878 format %{ "MOV $dst,$src" %}
5879 opcode(0xB8); /* + rd */
5880 ins_encode( LdImmP(dst, src) );
5881 ins_pipe( ialu_reg_fat );
5882 %}
5883
5884 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
5885 match(Set dst src);
5886 effect(KILL cr);
5887 ins_cost(200);
5888 format %{ "MOV $dst.lo,$src.lo\n\t"
5889 "MOV $dst.hi,$src.hi" %}
5890 opcode(0xB8);
5891 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
5892 ins_pipe( ialu_reg_long_fat );
5893 %}
5894
5895 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
5896 match(Set dst src);
5897 effect(KILL cr);
5898 ins_cost(150);
5899 format %{ "XOR $dst.lo,$dst.lo\n\t"
5900 "XOR $dst.hi,$dst.hi" %}
5901 opcode(0x33,0x33);
5902 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
5903 ins_pipe( ialu_reg_long );
5904 %}
5905
5906 // The instruction usage is guarded by predicate in operand immFPR().
5907 instruct loadConFPR(regFPR dst, immFPR con) %{
5908 match(Set dst con);
5909 ins_cost(125);
5910 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
5911 "FSTP $dst" %}
5912 ins_encode %{
5913 __ fld_s($constantaddress($con));
5914 __ fstp_d($dst$$reg);
5915 %}
5916 ins_pipe(fpu_reg_con);
5917 %}
5918
5919 // The instruction usage is guarded by predicate in operand immFPR0().
5920 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
5921 match(Set dst con);
5922 ins_cost(125);
5923 format %{ "FLDZ ST\n\t"
5924 "FSTP $dst" %}
5925 ins_encode %{
5926 __ fldz();
5927 __ fstp_d($dst$$reg);
5928 %}
5929 ins_pipe(fpu_reg_con);
5930 %}
5931
5932 // The instruction usage is guarded by predicate in operand immFPR1().
5933 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
5934 match(Set dst con);
5935 ins_cost(125);
5936 format %{ "FLD1 ST\n\t"
5937 "FSTP $dst" %}
5938 ins_encode %{
5939 __ fld1();
5940 __ fstp_d($dst$$reg);
5941 %}
5942 ins_pipe(fpu_reg_con);
5943 %}
5944
5945 // The instruction usage is guarded by predicate in operand immF().
5946 instruct loadConF(regF dst, immF con) %{
5947 match(Set dst con);
5948 ins_cost(125);
5949 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
5950 ins_encode %{
5951 __ movflt($dst$$XMMRegister, $constantaddress($con));
5952 %}
5953 ins_pipe(pipe_slow);
5954 %}
5955
5956 // The instruction usage is guarded by predicate in operand immF0().
5957 instruct loadConF0(regF dst, immF0 src) %{
5958 match(Set dst src);
5959 ins_cost(100);
5960 format %{ "XORPS $dst,$dst\t# float 0.0" %}
5961 ins_encode %{
5962 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5963 %}
5964 ins_pipe(pipe_slow);
5965 %}
5966
5967 // The instruction usage is guarded by predicate in operand immDPR().
5968 instruct loadConDPR(regDPR dst, immDPR con) %{
5969 match(Set dst con);
5970 ins_cost(125);
5971
5972 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
5973 "FSTP $dst" %}
5974 ins_encode %{
5975 __ fld_d($constantaddress($con));
5976 __ fstp_d($dst$$reg);
5977 %}
5978 ins_pipe(fpu_reg_con);
5979 %}
5980
5981 // The instruction usage is guarded by predicate in operand immDPR0().
5982 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
5983 match(Set dst con);
5984 ins_cost(125);
5985
5986 format %{ "FLDZ ST\n\t"
5987 "FSTP $dst" %}
5988 ins_encode %{
5989 __ fldz();
5990 __ fstp_d($dst$$reg);
5991 %}
5992 ins_pipe(fpu_reg_con);
5993 %}
5994
5995 // The instruction usage is guarded by predicate in operand immDPR1().
5996 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
5997 match(Set dst con);
5998 ins_cost(125);
5999
6000 format %{ "FLD1 ST\n\t"
6001 "FSTP $dst" %}
6002 ins_encode %{
6003 __ fld1();
6004 __ fstp_d($dst$$reg);
6005 %}
6006 ins_pipe(fpu_reg_con);
6007 %}
6008
6009 // The instruction usage is guarded by predicate in operand immD().
6010 instruct loadConD(regD dst, immD con) %{
6011 match(Set dst con);
6012 ins_cost(125);
6013 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6014 ins_encode %{
6015 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6016 %}
6017 ins_pipe(pipe_slow);
6018 %}
6019
6020 // The instruction usage is guarded by predicate in operand immD0().
6021 instruct loadConD0(regD dst, immD0 src) %{
6022 match(Set dst src);
6023 ins_cost(100);
6024 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6025 ins_encode %{
6026 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6027 %}
6028 ins_pipe( pipe_slow );
6029 %}
6030
6031 // Load Stack Slot
6032 instruct loadSSI(rRegI dst, stackSlotI src) %{
6033 match(Set dst src);
6034 ins_cost(125);
6035
6036 format %{ "MOV $dst,$src" %}
6037 opcode(0x8B);
6038 ins_encode( OpcP, RegMem(dst,src));
6039 ins_pipe( ialu_reg_mem );
6040 %}
6041
6042 instruct loadSSL(eRegL dst, stackSlotL src) %{
6043 match(Set dst src);
6044
6045 ins_cost(200);
6046 format %{ "MOV $dst,$src.lo\n\t"
6047 "MOV $dst+4,$src.hi" %}
6048 opcode(0x8B, 0x8B);
6049 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6050 ins_pipe( ialu_mem_long_reg );
6051 %}
6052
6053 // Load Stack Slot
6054 instruct loadSSP(eRegP dst, stackSlotP src) %{
6055 match(Set dst src);
6056 ins_cost(125);
6057
6058 format %{ "MOV $dst,$src" %}
6059 opcode(0x8B);
6060 ins_encode( OpcP, RegMem(dst,src));
6061 ins_pipe( ialu_reg_mem );
6062 %}
6063
6064 // Load Stack Slot
6065 instruct loadSSF(regFPR dst, stackSlotF src) %{
6066 match(Set dst src);
6067 ins_cost(125);
6068
6069 format %{ "FLD_S $src\n\t"
6070 "FSTP $dst" %}
6071 opcode(0xD9); /* D9 /0, FLD m32real */
6072 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6073 Pop_Reg_FPR(dst) );
6074 ins_pipe( fpu_reg_mem );
6075 %}
6076
6077 // Load Stack Slot
6078 instruct loadSSD(regDPR dst, stackSlotD src) %{
6079 match(Set dst src);
6080 ins_cost(125);
6081
6082 format %{ "FLD_D $src\n\t"
6083 "FSTP $dst" %}
6084 opcode(0xDD); /* DD /0, FLD m64real */
6085 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6086 Pop_Reg_DPR(dst) );
6087 ins_pipe( fpu_reg_mem );
6088 %}
6089
6090 // Prefetch instructions.
6091 // Must be safe to execute with invalid address (cannot fault).
6092
6093 instruct prefetchr0( memory mem ) %{
6094 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6095 match(PrefetchRead mem);
6096 ins_cost(0);
6097 size(0);
6098 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6099 ins_encode();
6100 ins_pipe(empty);
6101 %}
6102
6103 instruct prefetchr( memory mem ) %{
6104 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6105 match(PrefetchRead mem);
6106 ins_cost(100);
6107
6108 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6109 ins_encode %{
6110 __ prefetchr($mem$$Address);
6111 %}
6112 ins_pipe(ialu_mem);
6113 %}
6114
6115 instruct prefetchrNTA( memory mem ) %{
6116 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6117 match(PrefetchRead mem);
6118 ins_cost(100);
6119
6120 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6121 ins_encode %{
6122 __ prefetchnta($mem$$Address);
6123 %}
6124 ins_pipe(ialu_mem);
6125 %}
6126
6127 instruct prefetchrT0( memory mem ) %{
6128 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6129 match(PrefetchRead mem);
6130 ins_cost(100);
6131
6132 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6133 ins_encode %{
6134 __ prefetcht0($mem$$Address);
6135 %}
6136 ins_pipe(ialu_mem);
6137 %}
6138
6139 instruct prefetchrT2( memory mem ) %{
6140 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6141 match(PrefetchRead mem);
6142 ins_cost(100);
6143
6144 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6145 ins_encode %{
6146 __ prefetcht2($mem$$Address);
6147 %}
6148 ins_pipe(ialu_mem);
6149 %}
6150
6151 instruct prefetchw0( memory mem ) %{
6152 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6153 match(PrefetchWrite mem);
6154 ins_cost(0);
6155 size(0);
6156 format %{ "Prefetch (non-SSE is empty encoding)" %}
6157 ins_encode();
6158 ins_pipe(empty);
6159 %}
6160
6161 instruct prefetchw( memory mem ) %{
6162 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6163 match( PrefetchWrite mem );
6164 ins_cost(100);
6165
6166 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6167 ins_encode %{
6168 __ prefetchw($mem$$Address);
6169 %}
6170 ins_pipe(ialu_mem);
6171 %}
6172
6173 instruct prefetchwNTA( memory mem ) %{
6174 predicate(UseSSE>=1);
6175 match(PrefetchWrite mem);
6176 ins_cost(100);
6177
6178 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6179 ins_encode %{
6180 __ prefetchnta($mem$$Address);
6181 %}
6182 ins_pipe(ialu_mem);
6183 %}
6184
6185 // Prefetch instructions for allocation.
6186
6187 instruct prefetchAlloc0( memory mem ) %{
6188 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6189 match(PrefetchAllocation mem);
6190 ins_cost(0);
6191 size(0);
6192 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6193 ins_encode();
6194 ins_pipe(empty);
6195 %}
6196
6197 instruct prefetchAlloc( memory mem ) %{
6198 predicate(AllocatePrefetchInstr==3);
6199 match( PrefetchAllocation mem );
6200 ins_cost(100);
6201
6202 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6203 ins_encode %{
6204 __ prefetchw($mem$$Address);
6205 %}
6206 ins_pipe(ialu_mem);
6207 %}
6208
6209 instruct prefetchAllocNTA( memory mem ) %{
6210 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6211 match(PrefetchAllocation mem);
6212 ins_cost(100);
6213
6214 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6215 ins_encode %{
6216 __ prefetchnta($mem$$Address);
6217 %}
6218 ins_pipe(ialu_mem);
6219 %}
6220
6221 instruct prefetchAllocT0( memory mem ) %{
6222 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6223 match(PrefetchAllocation mem);
6224 ins_cost(100);
6225
6226 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6227 ins_encode %{
6228 __ prefetcht0($mem$$Address);
6229 %}
6230 ins_pipe(ialu_mem);
6231 %}
6232
6233 instruct prefetchAllocT2( memory mem ) %{
6234 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6235 match(PrefetchAllocation mem);
6236 ins_cost(100);
6237
6238 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6239 ins_encode %{
6240 __ prefetcht2($mem$$Address);
6241 %}
6242 ins_pipe(ialu_mem);
6243 %}
6244
6245 //----------Store Instructions-------------------------------------------------
6246
6247 // Store Byte
6248 instruct storeB(memory mem, xRegI src) %{
6249 match(Set mem (StoreB mem src));
6250
6251 ins_cost(125);
6252 format %{ "MOV8 $mem,$src" %}
6253 opcode(0x88);
6254 ins_encode( OpcP, RegMem( src, mem ) );
6255 ins_pipe( ialu_mem_reg );
6256 %}
6257
6258 // Store Char/Short
6259 instruct storeC(memory mem, rRegI src) %{
6260 match(Set mem (StoreC mem src));
6261
6262 ins_cost(125);
6263 format %{ "MOV16 $mem,$src" %}
6264 opcode(0x89, 0x66);
6265 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6266 ins_pipe( ialu_mem_reg );
6267 %}
6268
6269 // Store Integer
6270 instruct storeI(memory mem, rRegI src) %{
6271 match(Set mem (StoreI mem src));
6272
6273 ins_cost(125);
6274 format %{ "MOV $mem,$src" %}
6275 opcode(0x89);
6276 ins_encode( OpcP, RegMem( src, mem ) );
6277 ins_pipe( ialu_mem_reg );
6278 %}
6279
6280 // Store Long
6281 instruct storeL(long_memory mem, eRegL src) %{
6282 predicate(!((StoreLNode*)n)->require_atomic_access());
6283 match(Set mem (StoreL mem src));
6284
6285 ins_cost(200);
6286 format %{ "MOV $mem,$src.lo\n\t"
6287 "MOV $mem+4,$src.hi" %}
6288 opcode(0x89, 0x89);
6289 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6290 ins_pipe( ialu_mem_long_reg );
6291 %}
6292
6293 // Store Long to Integer
6294 instruct storeL2I(memory mem, eRegL src) %{
6295 match(Set mem (StoreI mem (ConvL2I src)));
6296
6297 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6298 ins_encode %{
6299 __ movl($mem$$Address, $src$$Register);
6300 %}
6301 ins_pipe(ialu_mem_reg);
6302 %}
6303
6304 // Volatile Store Long. Must be atomic, so move it into
6305 // the FP TOS and then do a 64-bit FIST. Has to probe the
6306 // target address before the store (for null-ptr checks)
6307 // so the memory operand is used twice in the encoding.
6308 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6309 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6310 match(Set mem (StoreL mem src));
6311 effect( KILL cr );
6312 ins_cost(400);
6313 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6314 "FILD $src\n\t"
6315 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6316 opcode(0x3B);
6317 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6318 ins_pipe( fpu_reg_mem );
6319 %}
6320
6321 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6322 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6323 match(Set mem (StoreL mem src));
6324 effect( TEMP tmp, KILL cr );
6325 ins_cost(380);
6326 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6327 "MOVSD $tmp,$src\n\t"
6328 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6329 ins_encode %{
6330 __ cmpl(rax, $mem$$Address);
6331 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6332 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6333 %}
6334 ins_pipe( pipe_slow );
6335 %}
6336
6337 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6338 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6339 match(Set mem (StoreL mem src));
6340 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6341 ins_cost(360);
6342 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6343 "MOVD $tmp,$src.lo\n\t"
6344 "MOVD $tmp2,$src.hi\n\t"
6345 "PUNPCKLDQ $tmp,$tmp2\n\t"
6346 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6347 ins_encode %{
6348 __ cmpl(rax, $mem$$Address);
6349 __ movdl($tmp$$XMMRegister, $src$$Register);
6350 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6351 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6352 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6353 %}
6354 ins_pipe( pipe_slow );
6355 %}
6356
6357 // Store Pointer; for storing unknown oops and raw pointers
6358 instruct storeP(memory mem, anyRegP src) %{
6359 match(Set mem (StoreP mem src));
6360
6361 ins_cost(125);
6362 format %{ "MOV $mem,$src" %}
6363 opcode(0x89);
6364 ins_encode( OpcP, RegMem( src, mem ) );
6365 ins_pipe( ialu_mem_reg );
6366 %}
6367
6368 // Store Integer Immediate
6369 instruct storeImmI(memory mem, immI src) %{
6370 match(Set mem (StoreI mem src));
6371
6372 ins_cost(150);
6373 format %{ "MOV $mem,$src" %}
6374 opcode(0xC7); /* C7 /0 */
6375 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6376 ins_pipe( ialu_mem_imm );
6377 %}
6378
6379 // Store Short/Char Immediate
6380 instruct storeImmI16(memory mem, immI16 src) %{
6381 predicate(UseStoreImmI16);
6382 match(Set mem (StoreC mem src));
6383
6384 ins_cost(150);
6385 format %{ "MOV16 $mem,$src" %}
6386 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6387 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6388 ins_pipe( ialu_mem_imm );
6389 %}
6390
6391 // Store Pointer Immediate; null pointers or constant oops that do not
6392 // need card-mark barriers.
6393 instruct storeImmP(memory mem, immP src) %{
6394 match(Set mem (StoreP mem src));
6395
6396 ins_cost(150);
6397 format %{ "MOV $mem,$src" %}
6398 opcode(0xC7); /* C7 /0 */
6399 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6400 ins_pipe( ialu_mem_imm );
6401 %}
6402
6403 // Store Byte Immediate
6404 instruct storeImmB(memory mem, immI8 src) %{
6405 match(Set mem (StoreB mem src));
6406
6407 ins_cost(150);
6408 format %{ "MOV8 $mem,$src" %}
6409 opcode(0xC6); /* C6 /0 */
6410 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6411 ins_pipe( ialu_mem_imm );
6412 %}
6413
6414 // Store CMS card-mark Immediate
6415 instruct storeImmCM(memory mem, immI8 src) %{
6416 match(Set mem (StoreCM mem src));
6417
6418 ins_cost(150);
6419 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6420 opcode(0xC6); /* C6 /0 */
6421 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6422 ins_pipe( ialu_mem_imm );
6423 %}
6424
6425 // Store Double
6426 instruct storeDPR( memory mem, regDPR1 src) %{
6427 predicate(UseSSE<=1);
6428 match(Set mem (StoreD mem src));
6429
6430 ins_cost(100);
6431 format %{ "FST_D $mem,$src" %}
6432 opcode(0xDD); /* DD /2 */
6433 ins_encode( enc_FPR_store(mem,src) );
6434 ins_pipe( fpu_mem_reg );
6435 %}
6436
6437 // Store double does rounding on x86
6438 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6439 predicate(UseSSE<=1);
6440 match(Set mem (StoreD mem (RoundDouble src)));
6441
6442 ins_cost(100);
6443 format %{ "FST_D $mem,$src\t# round" %}
6444 opcode(0xDD); /* DD /2 */
6445 ins_encode( enc_FPR_store(mem,src) );
6446 ins_pipe( fpu_mem_reg );
6447 %}
6448
6449 // Store XMM register to memory (double-precision floating points)
6450 // MOVSD instruction
6451 instruct storeD(memory mem, regD src) %{
6452 predicate(UseSSE>=2);
6453 match(Set mem (StoreD mem src));
6454 ins_cost(95);
6455 format %{ "MOVSD $mem,$src" %}
6456 ins_encode %{
6457 __ movdbl($mem$$Address, $src$$XMMRegister);
6458 %}
6459 ins_pipe( pipe_slow );
6460 %}
6461
6462 // Store XMM register to memory (single-precision floating point)
6463 // MOVSS instruction
6464 instruct storeF(memory mem, regF src) %{
6465 predicate(UseSSE>=1);
6466 match(Set mem (StoreF mem src));
6467 ins_cost(95);
6468 format %{ "MOVSS $mem,$src" %}
6469 ins_encode %{
6470 __ movflt($mem$$Address, $src$$XMMRegister);
6471 %}
6472 ins_pipe( pipe_slow );
6473 %}
6474
6475 // Store Float
6476 instruct storeFPR( memory mem, regFPR1 src) %{
6477 predicate(UseSSE==0);
6478 match(Set mem (StoreF mem src));
6479
6480 ins_cost(100);
6481 format %{ "FST_S $mem,$src" %}
6482 opcode(0xD9); /* D9 /2 */
6483 ins_encode( enc_FPR_store(mem,src) );
6484 ins_pipe( fpu_mem_reg );
6485 %}
6486
6487 // Store Float does rounding on x86
6488 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
6489 predicate(UseSSE==0);
6490 match(Set mem (StoreF mem (RoundFloat src)));
6491
6492 ins_cost(100);
6493 format %{ "FST_S $mem,$src\t# round" %}
6494 opcode(0xD9); /* D9 /2 */
6495 ins_encode( enc_FPR_store(mem,src) );
6496 ins_pipe( fpu_mem_reg );
6497 %}
6498
6499 // Store Float does rounding on x86
6500 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
6501 predicate(UseSSE<=1);
6502 match(Set mem (StoreF mem (ConvD2F src)));
6503
6504 ins_cost(100);
6505 format %{ "FST_S $mem,$src\t# D-round" %}
6506 opcode(0xD9); /* D9 /2 */
6507 ins_encode( enc_FPR_store(mem,src) );
6508 ins_pipe( fpu_mem_reg );
6509 %}
6510
6511 // Store immediate Float value (it is faster than store from FPU register)
6512 // The instruction usage is guarded by predicate in operand immFPR().
6513 instruct storeFPR_imm( memory mem, immFPR src) %{
6514 match(Set mem (StoreF mem src));
6515
6516 ins_cost(50);
6517 format %{ "MOV $mem,$src\t# store float" %}
6518 opcode(0xC7); /* C7 /0 */
6519 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
6520 ins_pipe( ialu_mem_imm );
6521 %}
6522
6523 // Store immediate Float value (it is faster than store from XMM register)
6524 // The instruction usage is guarded by predicate in operand immF().
6525 instruct storeF_imm( memory mem, immF src) %{
6526 match(Set mem (StoreF mem src));
6527
6528 ins_cost(50);
6529 format %{ "MOV $mem,$src\t# store float" %}
6530 opcode(0xC7); /* C7 /0 */
6531 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
6532 ins_pipe( ialu_mem_imm );
6533 %}
6534
6535 // Store Integer to stack slot
6536 instruct storeSSI(stackSlotI dst, rRegI src) %{
6537 match(Set dst src);
6538
6539 ins_cost(100);
6540 format %{ "MOV $dst,$src" %}
6541 opcode(0x89);
6542 ins_encode( OpcPRegSS( dst, src ) );
6543 ins_pipe( ialu_mem_reg );
6544 %}
6545
6546 // Store Integer to stack slot
6547 instruct storeSSP(stackSlotP dst, eRegP src) %{
6548 match(Set dst src);
6549
6550 ins_cost(100);
6551 format %{ "MOV $dst,$src" %}
6552 opcode(0x89);
6553 ins_encode( OpcPRegSS( dst, src ) );
6554 ins_pipe( ialu_mem_reg );
6555 %}
6556
6557 // Store Long to stack slot
6558 instruct storeSSL(stackSlotL dst, eRegL src) %{
6559 match(Set dst src);
6560
6561 ins_cost(200);
6562 format %{ "MOV $dst,$src.lo\n\t"
6563 "MOV $dst+4,$src.hi" %}
6564 opcode(0x89, 0x89);
6565 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
6566 ins_pipe( ialu_mem_long_reg );
6567 %}
6568
6569 //----------MemBar Instructions-----------------------------------------------
6570 // Memory barrier flavors
6571
6572 instruct membar_acquire() %{
6573 match(MemBarAcquire);
6574 match(LoadFence);
6575 ins_cost(400);
6576
6577 size(0);
6578 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6579 ins_encode();
6580 ins_pipe(empty);
6581 %}
6582
6583 instruct membar_acquire_lock() %{
6584 match(MemBarAcquireLock);
6585 ins_cost(0);
6586
6587 size(0);
6588 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6589 ins_encode( );
6590 ins_pipe(empty);
6591 %}
6592
6593 instruct membar_release() %{
6594 match(MemBarRelease);
6595 match(StoreFence);
6596 ins_cost(400);
6597
6598 size(0);
6599 format %{ "MEMBAR-release ! (empty encoding)" %}
6600 ins_encode( );
6601 ins_pipe(empty);
6602 %}
6603
6604 instruct membar_release_lock() %{
6605 match(MemBarReleaseLock);
6606 ins_cost(0);
6607
6608 size(0);
6609 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6610 ins_encode( );
6611 ins_pipe(empty);
6612 %}
6613
6614 instruct membar_volatile(eFlagsReg cr) %{
6615 match(MemBarVolatile);
6616 effect(KILL cr);
6617 ins_cost(400);
6618
6619 format %{
6620 $$template
6621 if (os::is_MP()) {
6622 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
6623 } else {
6624 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6625 }
6626 %}
6627 ins_encode %{
6628 __ membar(Assembler::StoreLoad);
6629 %}
6630 ins_pipe(pipe_slow);
6631 %}
6632
6633 instruct unnecessary_membar_volatile() %{
6634 match(MemBarVolatile);
6635 predicate(Matcher::post_store_load_barrier(n));
6636 ins_cost(0);
6637
6638 size(0);
6639 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6640 ins_encode( );
6641 ins_pipe(empty);
6642 %}
6643
6644 instruct membar_storestore() %{
6645 match(MemBarStoreStore);
6646 ins_cost(0);
6647
6648 size(0);
6649 format %{ "MEMBAR-storestore (empty encoding)" %}
6650 ins_encode( );
6651 ins_pipe(empty);
6652 %}
6653
6654 //----------Move Instructions--------------------------------------------------
6655 instruct castX2P(eAXRegP dst, eAXRegI src) %{
6656 match(Set dst (CastX2P src));
6657 format %{ "# X2P $dst, $src" %}
6658 ins_encode( /*empty encoding*/ );
6659 ins_cost(0);
6660 ins_pipe(empty);
6661 %}
6662
6663 instruct castP2X(rRegI dst, eRegP src ) %{
6664 match(Set dst (CastP2X src));
6665 ins_cost(50);
6666 format %{ "MOV $dst, $src\t# CastP2X" %}
6667 ins_encode( enc_Copy( dst, src) );
6668 ins_pipe( ialu_reg_reg );
6669 %}
6670
6671 //----------Conditional Move---------------------------------------------------
6672 // Conditional move
6673 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
6674 predicate(!VM_Version::supports_cmov() );
6675 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6676 ins_cost(200);
6677 format %{ "J$cop,us skip\t# signed cmove\n\t"
6678 "MOV $dst,$src\n"
6679 "skip:" %}
6680 ins_encode %{
6681 Label Lskip;
6682 // Invert sense of branch from sense of CMOV
6683 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6684 __ movl($dst$$Register, $src$$Register);
6685 __ bind(Lskip);
6686 %}
6687 ins_pipe( pipe_cmov_reg );
6688 %}
6689
6690 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
6691 predicate(!VM_Version::supports_cmov() );
6692 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6693 ins_cost(200);
6694 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
6695 "MOV $dst,$src\n"
6696 "skip:" %}
6697 ins_encode %{
6698 Label Lskip;
6699 // Invert sense of branch from sense of CMOV
6700 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6701 __ movl($dst$$Register, $src$$Register);
6702 __ bind(Lskip);
6703 %}
6704 ins_pipe( pipe_cmov_reg );
6705 %}
6706
6707 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
6708 predicate(VM_Version::supports_cmov() );
6709 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6710 ins_cost(200);
6711 format %{ "CMOV$cop $dst,$src" %}
6712 opcode(0x0F,0x40);
6713 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6714 ins_pipe( pipe_cmov_reg );
6715 %}
6716
6717 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
6718 predicate(VM_Version::supports_cmov() );
6719 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6720 ins_cost(200);
6721 format %{ "CMOV$cop $dst,$src" %}
6722 opcode(0x0F,0x40);
6723 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6724 ins_pipe( pipe_cmov_reg );
6725 %}
6726
6727 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
6728 predicate(VM_Version::supports_cmov() );
6729 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6730 ins_cost(200);
6731 expand %{
6732 cmovI_regU(cop, cr, dst, src);
6733 %}
6734 %}
6735
6736 // Conditional move
6737 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
6738 predicate(VM_Version::supports_cmov() );
6739 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6740 ins_cost(250);
6741 format %{ "CMOV$cop $dst,$src" %}
6742 opcode(0x0F,0x40);
6743 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6744 ins_pipe( pipe_cmov_mem );
6745 %}
6746
6747 // Conditional move
6748 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
6749 predicate(VM_Version::supports_cmov() );
6750 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6751 ins_cost(250);
6752 format %{ "CMOV$cop $dst,$src" %}
6753 opcode(0x0F,0x40);
6754 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6755 ins_pipe( pipe_cmov_mem );
6756 %}
6757
6758 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
6759 predicate(VM_Version::supports_cmov() );
6760 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6761 ins_cost(250);
6762 expand %{
6763 cmovI_memU(cop, cr, dst, src);
6764 %}
6765 %}
6766
6767 // Conditional move
6768 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
6769 predicate(VM_Version::supports_cmov() );
6770 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6771 ins_cost(200);
6772 format %{ "CMOV$cop $dst,$src\t# ptr" %}
6773 opcode(0x0F,0x40);
6774 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6775 ins_pipe( pipe_cmov_reg );
6776 %}
6777
6778 // Conditional move (non-P6 version)
6779 // Note: a CMoveP is generated for stubs and native wrappers
6780 // regardless of whether we are on a P6, so we
6781 // emulate a cmov here
6782 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
6783 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6784 ins_cost(300);
6785 format %{ "Jn$cop skip\n\t"
6786 "MOV $dst,$src\t# pointer\n"
6787 "skip:" %}
6788 opcode(0x8b);
6789 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
6790 ins_pipe( pipe_cmov_reg );
6791 %}
6792
6793 // Conditional move
6794 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
6795 predicate(VM_Version::supports_cmov() );
6796 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6797 ins_cost(200);
6798 format %{ "CMOV$cop $dst,$src\t# ptr" %}
6799 opcode(0x0F,0x40);
6800 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
6801 ins_pipe( pipe_cmov_reg );
6802 %}
6803
6804 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
6805 predicate(VM_Version::supports_cmov() );
6806 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6807 ins_cost(200);
6808 expand %{
6809 cmovP_regU(cop, cr, dst, src);
6810 %}
6811 %}
6812
6813 // DISABLED: Requires the ADLC to emit a bottom_type call that
6814 // correctly meets the two pointer arguments; one is an incoming
6815 // register but the other is a memory operand. ALSO appears to
6816 // be buggy with implicit null checks.
6817 //
6818 //// Conditional move
6819 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
6820 // predicate(VM_Version::supports_cmov() );
6821 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6822 // ins_cost(250);
6823 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6824 // opcode(0x0F,0x40);
6825 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6826 // ins_pipe( pipe_cmov_mem );
6827 //%}
6828 //
6829 //// Conditional move
6830 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
6831 // predicate(VM_Version::supports_cmov() );
6832 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6833 // ins_cost(250);
6834 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6835 // opcode(0x0F,0x40);
6836 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
6837 // ins_pipe( pipe_cmov_mem );
6838 //%}
6839
6840 // Conditional move
6841 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
6842 predicate(UseSSE<=1);
6843 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6844 ins_cost(200);
6845 format %{ "FCMOV$cop $dst,$src\t# double" %}
6846 opcode(0xDA);
6847 ins_encode( enc_cmov_dpr(cop,src) );
6848 ins_pipe( pipe_cmovDPR_reg );
6849 %}
6850
6851 // Conditional move
6852 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
6853 predicate(UseSSE==0);
6854 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6855 ins_cost(200);
6856 format %{ "FCMOV$cop $dst,$src\t# float" %}
6857 opcode(0xDA);
6858 ins_encode( enc_cmov_dpr(cop,src) );
6859 ins_pipe( pipe_cmovDPR_reg );
6860 %}
6861
6862 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
6863 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
6864 predicate(UseSSE<=1);
6865 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6866 ins_cost(200);
6867 format %{ "Jn$cop skip\n\t"
6868 "MOV $dst,$src\t# double\n"
6869 "skip:" %}
6870 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
6871 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
6872 ins_pipe( pipe_cmovDPR_reg );
6873 %}
6874
6875 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
6876 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
6877 predicate(UseSSE==0);
6878 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6879 ins_cost(200);
6880 format %{ "Jn$cop skip\n\t"
6881 "MOV $dst,$src\t# float\n"
6882 "skip:" %}
6883 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
6884 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
6885 ins_pipe( pipe_cmovDPR_reg );
6886 %}
6887
6888 // No CMOVE with SSE/SSE2
6889 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
6890 predicate (UseSSE>=1);
6891 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6892 ins_cost(200);
6893 format %{ "Jn$cop skip\n\t"
6894 "MOVSS $dst,$src\t# float\n"
6895 "skip:" %}
6896 ins_encode %{
6897 Label skip;
6898 // Invert sense of branch from sense of CMOV
6899 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6900 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6901 __ bind(skip);
6902 %}
6903 ins_pipe( pipe_slow );
6904 %}
6905
6906 // No CMOVE with SSE/SSE2
6907 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
6908 predicate (UseSSE>=2);
6909 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6910 ins_cost(200);
6911 format %{ "Jn$cop skip\n\t"
6912 "MOVSD $dst,$src\t# float\n"
6913 "skip:" %}
6914 ins_encode %{
6915 Label skip;
6916 // Invert sense of branch from sense of CMOV
6917 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6918 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6919 __ bind(skip);
6920 %}
6921 ins_pipe( pipe_slow );
6922 %}
6923
6924 // unsigned version
6925 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
6926 predicate (UseSSE>=1);
6927 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6928 ins_cost(200);
6929 format %{ "Jn$cop skip\n\t"
6930 "MOVSS $dst,$src\t# float\n"
6931 "skip:" %}
6932 ins_encode %{
6933 Label skip;
6934 // Invert sense of branch from sense of CMOV
6935 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6936 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6937 __ bind(skip);
6938 %}
6939 ins_pipe( pipe_slow );
6940 %}
6941
6942 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
6943 predicate (UseSSE>=1);
6944 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6945 ins_cost(200);
6946 expand %{
6947 fcmovF_regU(cop, cr, dst, src);
6948 %}
6949 %}
6950
6951 // unsigned version
6952 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
6953 predicate (UseSSE>=2);
6954 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6955 ins_cost(200);
6956 format %{ "Jn$cop skip\n\t"
6957 "MOVSD $dst,$src\t# float\n"
6958 "skip:" %}
6959 ins_encode %{
6960 Label skip;
6961 // Invert sense of branch from sense of CMOV
6962 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
6963 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6964 __ bind(skip);
6965 %}
6966 ins_pipe( pipe_slow );
6967 %}
6968
6969 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
6970 predicate (UseSSE>=2);
6971 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6972 ins_cost(200);
6973 expand %{
6974 fcmovD_regU(cop, cr, dst, src);
6975 %}
6976 %}
6977
6978 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
6979 predicate(VM_Version::supports_cmov() );
6980 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6981 ins_cost(200);
6982 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
6983 "CMOV$cop $dst.hi,$src.hi" %}
6984 opcode(0x0F,0x40);
6985 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
6986 ins_pipe( pipe_cmov_reg_long );
6987 %}
6988
6989 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
6990 predicate(VM_Version::supports_cmov() );
6991 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6992 ins_cost(200);
6993 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
6994 "CMOV$cop $dst.hi,$src.hi" %}
6995 opcode(0x0F,0x40);
6996 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
6997 ins_pipe( pipe_cmov_reg_long );
6998 %}
6999
7000 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7001 predicate(VM_Version::supports_cmov() );
7002 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7003 ins_cost(200);
7004 expand %{
7005 cmovL_regU(cop, cr, dst, src);
7006 %}
7007 %}
7008
7009 //----------Arithmetic Instructions--------------------------------------------
7010 //----------Addition Instructions----------------------------------------------
7011
7012 instruct addExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7013 %{
7014 match(AddExactI dst src);
7015 effect(DEF cr);
7016
7017 format %{ "ADD $dst, $src\t# addExact int" %}
7018 ins_encode %{
7019 __ addl($dst$$Register, $src$$Register);
7020 %}
7021 ins_pipe(ialu_reg_reg);
7022 %}
7023
7024 instruct addExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7025 %{
7026 match(AddExactI dst src);
7027 effect(DEF cr);
7028
7029 format %{ "ADD $dst, $src\t# addExact int" %}
7030 ins_encode %{
7031 __ addl($dst$$Register, $src$$constant);
7032 %}
7033 ins_pipe(ialu_reg_reg);
7034 %}
7035
7036 instruct addExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7037 %{
7038 match(AddExactI dst (LoadI src));
7039 effect(DEF cr);
7040
7041 ins_cost(125);
7042 format %{ "ADD $dst,$src\t# addExact int" %}
7043 ins_encode %{
7044 __ addl($dst$$Register, $src$$Address);
7045 %}
7046 ins_pipe( ialu_reg_mem );
7047 %}
7048
7049
7050 // Integer Addition Instructions
7051 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7052 match(Set dst (AddI dst src));
7053 effect(KILL cr);
7054
7055 size(2);
7056 format %{ "ADD $dst,$src" %}
7057 opcode(0x03);
7058 ins_encode( OpcP, RegReg( dst, src) );
7059 ins_pipe( ialu_reg_reg );
7060 %}
7061
7062 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7063 match(Set dst (AddI dst src));
7064 effect(KILL cr);
7065
7066 format %{ "ADD $dst,$src" %}
7067 opcode(0x81, 0x00); /* /0 id */
7068 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7069 ins_pipe( ialu_reg );
7070 %}
7071
7072 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7073 predicate(UseIncDec);
7074 match(Set dst (AddI dst src));
7075 effect(KILL cr);
7076
7077 size(1);
7078 format %{ "INC $dst" %}
7079 opcode(0x40); /* */
7080 ins_encode( Opc_plus( primary, dst ) );
7081 ins_pipe( ialu_reg );
7082 %}
7083
7084 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7085 match(Set dst (AddI src0 src1));
7086 ins_cost(110);
7087
7088 format %{ "LEA $dst,[$src0 + $src1]" %}
7089 opcode(0x8D); /* 0x8D /r */
7090 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7091 ins_pipe( ialu_reg_reg );
7092 %}
7093
7094 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7095 match(Set dst (AddP src0 src1));
7096 ins_cost(110);
7097
7098 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7099 opcode(0x8D); /* 0x8D /r */
7100 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7101 ins_pipe( ialu_reg_reg );
7102 %}
7103
7104 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7105 predicate(UseIncDec);
7106 match(Set dst (AddI dst src));
7107 effect(KILL cr);
7108
7109 size(1);
7110 format %{ "DEC $dst" %}
7111 opcode(0x48); /* */
7112 ins_encode( Opc_plus( primary, dst ) );
7113 ins_pipe( ialu_reg );
7114 %}
7115
7116 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7117 match(Set dst (AddP dst src));
7118 effect(KILL cr);
7119
7120 size(2);
7121 format %{ "ADD $dst,$src" %}
7122 opcode(0x03);
7123 ins_encode( OpcP, RegReg( dst, src) );
7124 ins_pipe( ialu_reg_reg );
7125 %}
7126
7127 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7128 match(Set dst (AddP dst src));
7129 effect(KILL cr);
7130
7131 format %{ "ADD $dst,$src" %}
7132 opcode(0x81,0x00); /* Opcode 81 /0 id */
7133 // ins_encode( RegImm( dst, src) );
7134 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7135 ins_pipe( ialu_reg );
7136 %}
7137
7138 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7139 match(Set dst (AddI dst (LoadI src)));
7140 effect(KILL cr);
7141
7142 ins_cost(125);
7143 format %{ "ADD $dst,$src" %}
7144 opcode(0x03);
7145 ins_encode( OpcP, RegMem( dst, src) );
7146 ins_pipe( ialu_reg_mem );
7147 %}
7148
7149 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7150 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7151 effect(KILL cr);
7152
7153 ins_cost(150);
7154 format %{ "ADD $dst,$src" %}
7155 opcode(0x01); /* Opcode 01 /r */
7156 ins_encode( OpcP, RegMem( src, dst ) );
7157 ins_pipe( ialu_mem_reg );
7158 %}
7159
7160 // Add Memory with Immediate
7161 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7162 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7163 effect(KILL cr);
7164
7165 ins_cost(125);
7166 format %{ "ADD $dst,$src" %}
7167 opcode(0x81); /* Opcode 81 /0 id */
7168 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7169 ins_pipe( ialu_mem_imm );
7170 %}
7171
7172 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7173 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7174 effect(KILL cr);
7175
7176 ins_cost(125);
7177 format %{ "INC $dst" %}
7178 opcode(0xFF); /* Opcode FF /0 */
7179 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7180 ins_pipe( ialu_mem_imm );
7181 %}
7182
7183 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7184 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7185 effect(KILL cr);
7186
7187 ins_cost(125);
7188 format %{ "DEC $dst" %}
7189 opcode(0xFF); /* Opcode FF /1 */
7190 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7191 ins_pipe( ialu_mem_imm );
7192 %}
7193
7194
7195 instruct checkCastPP( eRegP dst ) %{
7196 match(Set dst (CheckCastPP dst));
7197
7198 size(0);
7199 format %{ "#checkcastPP of $dst" %}
7200 ins_encode( /*empty encoding*/ );
7201 ins_pipe( empty );
7202 %}
7203
7204 instruct castPP( eRegP dst ) %{
7205 match(Set dst (CastPP dst));
7206 format %{ "#castPP of $dst" %}
7207 ins_encode( /*empty encoding*/ );
7208 ins_pipe( empty );
7209 %}
7210
7211 instruct castII( rRegI dst ) %{
7212 match(Set dst (CastII dst));
7213 format %{ "#castII of $dst" %}
7214 ins_encode( /*empty encoding*/ );
7215 ins_cost(0);
7216 ins_pipe( empty );
7217 %}
7218
7219
7220 // Load-locked - same as a regular pointer load when used with compare-swap
7221 instruct loadPLocked(eRegP dst, memory mem) %{
7222 match(Set dst (LoadPLocked mem));
7223
7224 ins_cost(125);
7225 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7226 opcode(0x8B);
7227 ins_encode( OpcP, RegMem(dst,mem));
7228 ins_pipe( ialu_reg_mem );
7229 %}
7230
7231 // Conditional-store of the updated heap-top.
7232 // Used during allocation of the shared heap.
7233 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7234 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7235 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7236 // EAX is killed if there is contention, but then it's also unused.
7237 // In the common case of no contention, EAX holds the new oop address.
7238 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7239 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7240 ins_pipe( pipe_cmpxchg );
7241 %}
7242
7243 // Conditional-store of an int value.
7244 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7245 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7246 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7247 effect(KILL oldval);
7248 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7249 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7250 ins_pipe( pipe_cmpxchg );
7251 %}
7252
7253 // Conditional-store of a long value.
7254 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7255 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7256 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7257 effect(KILL oldval);
7258 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7259 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7260 "XCHG EBX,ECX"
7261 %}
7262 ins_encode %{
7263 // Note: we need to swap rbx, and rcx before and after the
7264 // cmpxchg8 instruction because the instruction uses
7265 // rcx as the high order word of the new value to store but
7266 // our register encoding uses rbx.
7267 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7268 if( os::is_MP() )
7269 __ lock();
7270 __ cmpxchg8($mem$$Address);
7271 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7272 %}
7273 ins_pipe( pipe_cmpxchg );
7274 %}
7275
7276 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7277
7278 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7279 predicate(VM_Version::supports_cx8());
7280 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7281 effect(KILL cr, KILL oldval);
7282 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7283 "MOV $res,0\n\t"
7284 "JNE,s fail\n\t"
7285 "MOV $res,1\n"
7286 "fail:" %}
7287 ins_encode( enc_cmpxchg8(mem_ptr),
7288 enc_flags_ne_to_boolean(res) );
7289 ins_pipe( pipe_cmpxchg );
7290 %}
7291
7292 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7293 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7294 effect(KILL cr, KILL oldval);
7295 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7296 "MOV $res,0\n\t"
7297 "JNE,s fail\n\t"
7298 "MOV $res,1\n"
7299 "fail:" %}
7300 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7301 ins_pipe( pipe_cmpxchg );
7302 %}
7303
7304 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7305 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7306 effect(KILL cr, KILL oldval);
7307 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7308 "MOV $res,0\n\t"
7309 "JNE,s fail\n\t"
7310 "MOV $res,1\n"
7311 "fail:" %}
7312 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7313 ins_pipe( pipe_cmpxchg );
7314 %}
7315
7316 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7317 predicate(n->as_LoadStore()->result_not_used());
7318 match(Set dummy (GetAndAddI mem add));
7319 effect(KILL cr);
7320 format %{ "ADDL [$mem],$add" %}
7321 ins_encode %{
7322 if (os::is_MP()) { __ lock(); }
7323 __ addl($mem$$Address, $add$$constant);
7324 %}
7325 ins_pipe( pipe_cmpxchg );
7326 %}
7327
7328 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7329 match(Set newval (GetAndAddI mem newval));
7330 effect(KILL cr);
7331 format %{ "XADDL [$mem],$newval" %}
7332 ins_encode %{
7333 if (os::is_MP()) { __ lock(); }
7334 __ xaddl($mem$$Address, $newval$$Register);
7335 %}
7336 ins_pipe( pipe_cmpxchg );
7337 %}
7338
7339 instruct xchgI( memory mem, rRegI newval) %{
7340 match(Set newval (GetAndSetI mem newval));
7341 format %{ "XCHGL $newval,[$mem]" %}
7342 ins_encode %{
7343 __ xchgl($newval$$Register, $mem$$Address);
7344 %}
7345 ins_pipe( pipe_cmpxchg );
7346 %}
7347
7348 instruct xchgP( memory mem, pRegP newval) %{
7349 match(Set newval (GetAndSetP mem newval));
7350 format %{ "XCHGL $newval,[$mem]" %}
7351 ins_encode %{
7352 __ xchgl($newval$$Register, $mem$$Address);
7353 %}
7354 ins_pipe( pipe_cmpxchg );
7355 %}
7356
7357 //----------Subtraction Instructions-------------------------------------------
7358
7359 instruct subExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7360 %{
7361 match(SubExactI dst src);
7362 effect(DEF cr);
7363
7364 format %{ "SUB $dst, $src\t# subExact int" %}
7365 ins_encode %{
7366 __ subl($dst$$Register, $src$$Register);
7367 %}
7368 ins_pipe(ialu_reg_reg);
7369 %}
7370
7371 instruct subExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7372 %{
7373 match(SubExactI dst src);
7374 effect(DEF cr);
7375
7376 format %{ "SUB $dst, $src\t# subExact int" %}
7377 ins_encode %{
7378 __ subl($dst$$Register, $src$$constant);
7379 %}
7380 ins_pipe(ialu_reg_reg);
7381 %}
7382
7383 instruct subExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7384 %{
7385 match(SubExactI dst (LoadI src));
7386 effect(DEF cr);
7387
7388 ins_cost(125);
7389 format %{ "SUB $dst,$src\t# subExact int" %}
7390 ins_encode %{
7391 __ subl($dst$$Register, $src$$Address);
7392 %}
7393 ins_pipe( ialu_reg_mem );
7394 %}
7395
7396 // Integer Subtraction Instructions
7397 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7398 match(Set dst (SubI dst src));
7399 effect(KILL cr);
7400
7401 size(2);
7402 format %{ "SUB $dst,$src" %}
7403 opcode(0x2B);
7404 ins_encode( OpcP, RegReg( dst, src) );
7405 ins_pipe( ialu_reg_reg );
7406 %}
7407
7408 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7409 match(Set dst (SubI dst src));
7410 effect(KILL cr);
7411
7412 format %{ "SUB $dst,$src" %}
7413 opcode(0x81,0x05); /* Opcode 81 /5 */
7414 // ins_encode( RegImm( dst, src) );
7415 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7416 ins_pipe( ialu_reg );
7417 %}
7418
7419 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7420 match(Set dst (SubI dst (LoadI src)));
7421 effect(KILL cr);
7422
7423 ins_cost(125);
7424 format %{ "SUB $dst,$src" %}
7425 opcode(0x2B);
7426 ins_encode( OpcP, RegMem( dst, src) );
7427 ins_pipe( ialu_reg_mem );
7428 %}
7429
7430 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7431 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7432 effect(KILL cr);
7433
7434 ins_cost(150);
7435 format %{ "SUB $dst,$src" %}
7436 opcode(0x29); /* Opcode 29 /r */
7437 ins_encode( OpcP, RegMem( src, dst ) );
7438 ins_pipe( ialu_mem_reg );
7439 %}
7440
7441 // Subtract from a pointer
7442 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7443 match(Set dst (AddP dst (SubI zero src)));
7444 effect(KILL cr);
7445
7446 size(2);
7447 format %{ "SUB $dst,$src" %}
7448 opcode(0x2B);
7449 ins_encode( OpcP, RegReg( dst, src) );
7450 ins_pipe( ialu_reg_reg );
7451 %}
7452
7453 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7454 match(Set dst (SubI zero dst));
7455 effect(KILL cr);
7456
7457 size(2);
7458 format %{ "NEG $dst" %}
7459 opcode(0xF7,0x03); // Opcode F7 /3
7460 ins_encode( OpcP, RegOpc( dst ) );
7461 ins_pipe( ialu_reg );
7462 %}
7463
7464 instruct negExactI_eReg(eAXRegI dst, eFlagsReg cr) %{
7465 match(NegExactI dst);
7466 effect(DEF cr);
7467
7468 format %{ "NEG $dst\t# negExact int"%}
7469 ins_encode %{
7470 __ negl($dst$$Register);
7471 %}
7472 ins_pipe(ialu_reg);
7473 %}
7474
7475 //----------Multiplication/Division Instructions-------------------------------
7476 // Integer Multiplication Instructions
7477 // Multiply Register
7478 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7479 match(Set dst (MulI dst src));
7480 effect(KILL cr);
7481
7482 size(3);
7483 ins_cost(300);
7484 format %{ "IMUL $dst,$src" %}
7485 opcode(0xAF, 0x0F);
7486 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7487 ins_pipe( ialu_reg_reg_alu0 );
7488 %}
7489
7490 // Multiply 32-bit Immediate
7491 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7492 match(Set dst (MulI src imm));
7493 effect(KILL cr);
7494
7495 ins_cost(300);
7496 format %{ "IMUL $dst,$src,$imm" %}
7497 opcode(0x69); /* 69 /r id */
7498 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7499 ins_pipe( ialu_reg_reg_alu0 );
7500 %}
7501
7502 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7503 match(Set dst src);
7504 effect(KILL cr);
7505
7506 // Note that this is artificially increased to make it more expensive than loadConL
7507 ins_cost(250);
7508 format %{ "MOV EAX,$src\t// low word only" %}
7509 opcode(0xB8);
7510 ins_encode( LdImmL_Lo(dst, src) );
7511 ins_pipe( ialu_reg_fat );
7512 %}
7513
7514 // Multiply by 32-bit Immediate, taking the shifted high order results
7515 // (special case for shift by 32)
7516 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7517 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7518 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7519 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7520 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7521 effect(USE src1, KILL cr);
7522
7523 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7524 ins_cost(0*100 + 1*400 - 150);
7525 format %{ "IMUL EDX:EAX,$src1" %}
7526 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7527 ins_pipe( pipe_slow );
7528 %}
7529
7530 // Multiply by 32-bit Immediate, taking the shifted high order results
7531 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7532 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7533 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7534 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7535 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7536 effect(USE src1, KILL cr);
7537
7538 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7539 ins_cost(1*100 + 1*400 - 150);
7540 format %{ "IMUL EDX:EAX,$src1\n\t"
7541 "SAR EDX,$cnt-32" %}
7542 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7543 ins_pipe( pipe_slow );
7544 %}
7545
7546 // Multiply Memory 32-bit Immediate
7547 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7548 match(Set dst (MulI (LoadI src) imm));
7549 effect(KILL cr);
7550
7551 ins_cost(300);
7552 format %{ "IMUL $dst,$src,$imm" %}
7553 opcode(0x69); /* 69 /r id */
7554 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
7555 ins_pipe( ialu_reg_mem_alu0 );
7556 %}
7557
7558 // Multiply Memory
7559 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
7560 match(Set dst (MulI dst (LoadI src)));
7561 effect(KILL cr);
7562
7563 ins_cost(350);
7564 format %{ "IMUL $dst,$src" %}
7565 opcode(0xAF, 0x0F);
7566 ins_encode( OpcS, OpcP, RegMem( dst, src) );
7567 ins_pipe( ialu_reg_mem_alu0 );
7568 %}
7569
7570 // Multiply Register Int to Long
7571 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
7572 // Basic Idea: long = (long)int * (long)int
7573 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
7574 effect(DEF dst, USE src, USE src1, KILL flags);
7575
7576 ins_cost(300);
7577 format %{ "IMUL $dst,$src1" %}
7578
7579 ins_encode( long_int_multiply( dst, src1 ) );
7580 ins_pipe( ialu_reg_reg_alu0 );
7581 %}
7582
7583 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
7584 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
7585 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
7586 effect(KILL flags);
7587
7588 ins_cost(300);
7589 format %{ "MUL $dst,$src1" %}
7590
7591 ins_encode( long_uint_multiply(dst, src1) );
7592 ins_pipe( ialu_reg_reg_alu0 );
7593 %}
7594
7595 // Multiply Register Long
7596 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7597 match(Set dst (MulL dst src));
7598 effect(KILL cr, TEMP tmp);
7599 ins_cost(4*100+3*400);
7600 // Basic idea: lo(result) = lo(x_lo * y_lo)
7601 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
7602 format %{ "MOV $tmp,$src.lo\n\t"
7603 "IMUL $tmp,EDX\n\t"
7604 "MOV EDX,$src.hi\n\t"
7605 "IMUL EDX,EAX\n\t"
7606 "ADD $tmp,EDX\n\t"
7607 "MUL EDX:EAX,$src.lo\n\t"
7608 "ADD EDX,$tmp" %}
7609 ins_encode( long_multiply( dst, src, tmp ) );
7610 ins_pipe( pipe_slow );
7611 %}
7612
7613 // Multiply Register Long where the left operand's high 32 bits are zero
7614 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7615 predicate(is_operand_hi32_zero(n->in(1)));
7616 match(Set dst (MulL dst src));
7617 effect(KILL cr, TEMP tmp);
7618 ins_cost(2*100+2*400);
7619 // Basic idea: lo(result) = lo(x_lo * y_lo)
7620 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
7621 format %{ "MOV $tmp,$src.hi\n\t"
7622 "IMUL $tmp,EAX\n\t"
7623 "MUL EDX:EAX,$src.lo\n\t"
7624 "ADD EDX,$tmp" %}
7625 ins_encode %{
7626 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
7627 __ imull($tmp$$Register, rax);
7628 __ mull($src$$Register);
7629 __ addl(rdx, $tmp$$Register);
7630 %}
7631 ins_pipe( pipe_slow );
7632 %}
7633
7634 // Multiply Register Long where the right operand's high 32 bits are zero
7635 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
7636 predicate(is_operand_hi32_zero(n->in(2)));
7637 match(Set dst (MulL dst src));
7638 effect(KILL cr, TEMP tmp);
7639 ins_cost(2*100+2*400);
7640 // Basic idea: lo(result) = lo(x_lo * y_lo)
7641 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
7642 format %{ "MOV $tmp,$src.lo\n\t"
7643 "IMUL $tmp,EDX\n\t"
7644 "MUL EDX:EAX,$src.lo\n\t"
7645 "ADD EDX,$tmp" %}
7646 ins_encode %{
7647 __ movl($tmp$$Register, $src$$Register);
7648 __ imull($tmp$$Register, rdx);
7649 __ mull($src$$Register);
7650 __ addl(rdx, $tmp$$Register);
7651 %}
7652 ins_pipe( pipe_slow );
7653 %}
7654
7655 // Multiply Register Long where the left and the right operands' high 32 bits are zero
7656 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
7657 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
7658 match(Set dst (MulL dst src));
7659 effect(KILL cr);
7660 ins_cost(1*400);
7661 // Basic idea: lo(result) = lo(x_lo * y_lo)
7662 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
7663 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
7664 ins_encode %{
7665 __ mull($src$$Register);
7666 %}
7667 ins_pipe( pipe_slow );
7668 %}
7669
7670 // Multiply Register Long by small constant
7671 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
7672 match(Set dst (MulL dst src));
7673 effect(KILL cr, TEMP tmp);
7674 ins_cost(2*100+2*400);
7675 size(12);
7676 // Basic idea: lo(result) = lo(src * EAX)
7677 // hi(result) = hi(src * EAX) + lo(src * EDX)
7678 format %{ "IMUL $tmp,EDX,$src\n\t"
7679 "MOV EDX,$src\n\t"
7680 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
7681 "ADD EDX,$tmp" %}
7682 ins_encode( long_multiply_con( dst, src, tmp ) );
7683 ins_pipe( pipe_slow );
7684 %}
7685
7686 instruct mulExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7687 %{
7688 match(MulExactI dst src);
7689 effect(DEF cr);
7690
7691 ins_cost(300);
7692 format %{ "IMUL $dst, $src\t# mulExact int" %}
7693 ins_encode %{
7694 __ imull($dst$$Register, $src$$Register);
7695 %}
7696 ins_pipe(ialu_reg_reg_alu0);
7697 %}
7698
7699 instruct mulExactI_eReg_imm(eAXRegI dst, rRegI src, immI imm, eFlagsReg cr)
7700 %{
7701 match(MulExactI src imm);
7702 effect(DEF cr);
7703
7704 ins_cost(300);
7705 format %{ "IMUL $dst, $src, $imm\t# mulExact int" %}
7706 ins_encode %{
7707 __ imull($dst$$Register, $src$$Register, $imm$$constant);
7708 %}
7709 ins_pipe(ialu_reg_reg_alu0);
7710 %}
7711
7712 instruct mulExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7713 %{
7714 match(MulExactI dst (LoadI src));
7715 effect(DEF cr);
7716
7717 ins_cost(350);
7718 format %{ "IMUL $dst, $src\t# mulExact int" %}
7719 ins_encode %{
7720 __ imull($dst$$Register, $src$$Address);
7721 %}
7722 ins_pipe(ialu_reg_mem_alu0);
7723 %}
7724
7725
7726 // Integer DIV with Register
7727 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
7728 match(Set rax (DivI rax div));
7729 effect(KILL rdx, KILL cr);
7730 size(26);
7731 ins_cost(30*100+10*100);
7732 format %{ "CMP EAX,0x80000000\n\t"
7733 "JNE,s normal\n\t"
7734 "XOR EDX,EDX\n\t"
7735 "CMP ECX,-1\n\t"
7736 "JE,s done\n"
7737 "normal: CDQ\n\t"
7738 "IDIV $div\n\t"
7739 "done:" %}
7740 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7741 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7742 ins_pipe( ialu_reg_reg_alu0 );
7743 %}
7744
7745 // Divide Register Long
7746 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
7747 match(Set dst (DivL src1 src2));
7748 effect( KILL cr, KILL cx, KILL bx );
7749 ins_cost(10000);
7750 format %{ "PUSH $src1.hi\n\t"
7751 "PUSH $src1.lo\n\t"
7752 "PUSH $src2.hi\n\t"
7753 "PUSH $src2.lo\n\t"
7754 "CALL SharedRuntime::ldiv\n\t"
7755 "ADD ESP,16" %}
7756 ins_encode( long_div(src1,src2) );
7757 ins_pipe( pipe_slow );
7758 %}
7759
7760 // Integer DIVMOD with Register, both quotient and mod results
7761 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
7762 match(DivModI rax div);
7763 effect(KILL cr);
7764 size(26);
7765 ins_cost(30*100+10*100);
7766 format %{ "CMP EAX,0x80000000\n\t"
7767 "JNE,s normal\n\t"
7768 "XOR EDX,EDX\n\t"
7769 "CMP ECX,-1\n\t"
7770 "JE,s done\n"
7771 "normal: CDQ\n\t"
7772 "IDIV $div\n\t"
7773 "done:" %}
7774 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7775 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7776 ins_pipe( pipe_slow );
7777 %}
7778
7779 // Integer MOD with Register
7780 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
7781 match(Set rdx (ModI rax div));
7782 effect(KILL rax, KILL cr);
7783
7784 size(26);
7785 ins_cost(300);
7786 format %{ "CDQ\n\t"
7787 "IDIV $div" %}
7788 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7789 ins_encode( cdq_enc, OpcP, RegOpc(div) );
7790 ins_pipe( ialu_reg_reg_alu0 );
7791 %}
7792
7793 // Remainder Register Long
7794 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
7795 match(Set dst (ModL src1 src2));
7796 effect( KILL cr, KILL cx, KILL bx );
7797 ins_cost(10000);
7798 format %{ "PUSH $src1.hi\n\t"
7799 "PUSH $src1.lo\n\t"
7800 "PUSH $src2.hi\n\t"
7801 "PUSH $src2.lo\n\t"
7802 "CALL SharedRuntime::lrem\n\t"
7803 "ADD ESP,16" %}
7804 ins_encode( long_mod(src1,src2) );
7805 ins_pipe( pipe_slow );
7806 %}
7807
7808 // Divide Register Long (no special case since divisor != -1)
7809 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
7810 match(Set dst (DivL dst imm));
7811 effect( TEMP tmp, TEMP tmp2, KILL cr );
7812 ins_cost(1000);
7813 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
7814 "XOR $tmp2,$tmp2\n\t"
7815 "CMP $tmp,EDX\n\t"
7816 "JA,s fast\n\t"
7817 "MOV $tmp2,EAX\n\t"
7818 "MOV EAX,EDX\n\t"
7819 "MOV EDX,0\n\t"
7820 "JLE,s pos\n\t"
7821 "LNEG EAX : $tmp2\n\t"
7822 "DIV $tmp # unsigned division\n\t"
7823 "XCHG EAX,$tmp2\n\t"
7824 "DIV $tmp\n\t"
7825 "LNEG $tmp2 : EAX\n\t"
7826 "JMP,s done\n"
7827 "pos:\n\t"
7828 "DIV $tmp\n\t"
7829 "XCHG EAX,$tmp2\n"
7830 "fast:\n\t"
7831 "DIV $tmp\n"
7832 "done:\n\t"
7833 "MOV EDX,$tmp2\n\t"
7834 "NEG EDX:EAX # if $imm < 0" %}
7835 ins_encode %{
7836 int con = (int)$imm$$constant;
7837 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
7838 int pcon = (con > 0) ? con : -con;
7839 Label Lfast, Lpos, Ldone;
7840
7841 __ movl($tmp$$Register, pcon);
7842 __ xorl($tmp2$$Register,$tmp2$$Register);
7843 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
7844 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
7845
7846 __ movl($tmp2$$Register, $dst$$Register); // save
7847 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7848 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
7849 __ jccb(Assembler::lessEqual, Lpos); // result is positive
7850
7851 // Negative dividend.
7852 // convert value to positive to use unsigned division
7853 __ lneg($dst$$Register, $tmp2$$Register);
7854 __ divl($tmp$$Register);
7855 __ xchgl($dst$$Register, $tmp2$$Register);
7856 __ divl($tmp$$Register);
7857 // revert result back to negative
7858 __ lneg($tmp2$$Register, $dst$$Register);
7859 __ jmpb(Ldone);
7860
7861 __ bind(Lpos);
7862 __ divl($tmp$$Register); // Use unsigned division
7863 __ xchgl($dst$$Register, $tmp2$$Register);
7864 // Fallthrow for final divide, tmp2 has 32 bit hi result
7865
7866 __ bind(Lfast);
7867 // fast path: src is positive
7868 __ divl($tmp$$Register); // Use unsigned division
7869
7870 __ bind(Ldone);
7871 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
7872 if (con < 0) {
7873 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
7874 }
7875 %}
7876 ins_pipe( pipe_slow );
7877 %}
7878
7879 // Remainder Register Long (remainder fit into 32 bits)
7880 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
7881 match(Set dst (ModL dst imm));
7882 effect( TEMP tmp, TEMP tmp2, KILL cr );
7883 ins_cost(1000);
7884 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
7885 "CMP $tmp,EDX\n\t"
7886 "JA,s fast\n\t"
7887 "MOV $tmp2,EAX\n\t"
7888 "MOV EAX,EDX\n\t"
7889 "MOV EDX,0\n\t"
7890 "JLE,s pos\n\t"
7891 "LNEG EAX : $tmp2\n\t"
7892 "DIV $tmp # unsigned division\n\t"
7893 "MOV EAX,$tmp2\n\t"
7894 "DIV $tmp\n\t"
7895 "NEG EDX\n\t"
7896 "JMP,s done\n"
7897 "pos:\n\t"
7898 "DIV $tmp\n\t"
7899 "MOV EAX,$tmp2\n"
7900 "fast:\n\t"
7901 "DIV $tmp\n"
7902 "done:\n\t"
7903 "MOV EAX,EDX\n\t"
7904 "SAR EDX,31\n\t" %}
7905 ins_encode %{
7906 int con = (int)$imm$$constant;
7907 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
7908 int pcon = (con > 0) ? con : -con;
7909 Label Lfast, Lpos, Ldone;
7910
7911 __ movl($tmp$$Register, pcon);
7912 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
7913 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
7914
7915 __ movl($tmp2$$Register, $dst$$Register); // save
7916 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7917 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
7918 __ jccb(Assembler::lessEqual, Lpos); // result is positive
7919
7920 // Negative dividend.
7921 // convert value to positive to use unsigned division
7922 __ lneg($dst$$Register, $tmp2$$Register);
7923 __ divl($tmp$$Register);
7924 __ movl($dst$$Register, $tmp2$$Register);
7925 __ divl($tmp$$Register);
7926 // revert remainder back to negative
7927 __ negl(HIGH_FROM_LOW($dst$$Register));
7928 __ jmpb(Ldone);
7929
7930 __ bind(Lpos);
7931 __ divl($tmp$$Register);
7932 __ movl($dst$$Register, $tmp2$$Register);
7933
7934 __ bind(Lfast);
7935 // fast path: src is positive
7936 __ divl($tmp$$Register);
7937
7938 __ bind(Ldone);
7939 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
7940 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
7941
7942 %}
7943 ins_pipe( pipe_slow );
7944 %}
7945
7946 // Integer Shift Instructions
7947 // Shift Left by one
7948 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7949 match(Set dst (LShiftI dst shift));
7950 effect(KILL cr);
7951
7952 size(2);
7953 format %{ "SHL $dst,$shift" %}
7954 opcode(0xD1, 0x4); /* D1 /4 */
7955 ins_encode( OpcP, RegOpc( dst ) );
7956 ins_pipe( ialu_reg );
7957 %}
7958
7959 // Shift Left by 8-bit immediate
7960 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
7961 match(Set dst (LShiftI dst shift));
7962 effect(KILL cr);
7963
7964 size(3);
7965 format %{ "SHL $dst,$shift" %}
7966 opcode(0xC1, 0x4); /* C1 /4 ib */
7967 ins_encode( RegOpcImm( dst, shift) );
7968 ins_pipe( ialu_reg );
7969 %}
7970
7971 // Shift Left by variable
7972 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
7973 match(Set dst (LShiftI dst shift));
7974 effect(KILL cr);
7975
7976 size(2);
7977 format %{ "SHL $dst,$shift" %}
7978 opcode(0xD3, 0x4); /* D3 /4 */
7979 ins_encode( OpcP, RegOpc( dst ) );
7980 ins_pipe( ialu_reg_reg );
7981 %}
7982
7983 // Arithmetic shift right by one
7984 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
7985 match(Set dst (RShiftI dst shift));
7986 effect(KILL cr);
7987
7988 size(2);
7989 format %{ "SAR $dst,$shift" %}
7990 opcode(0xD1, 0x7); /* D1 /7 */
7991 ins_encode( OpcP, RegOpc( dst ) );
7992 ins_pipe( ialu_reg );
7993 %}
7994
7995 // Arithmetic shift right by one
7996 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
7997 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7998 effect(KILL cr);
7999 format %{ "SAR $dst,$shift" %}
8000 opcode(0xD1, 0x7); /* D1 /7 */
8001 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8002 ins_pipe( ialu_mem_imm );
8003 %}
8004
8005 // Arithmetic Shift Right by 8-bit immediate
8006 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8007 match(Set dst (RShiftI dst shift));
8008 effect(KILL cr);
8009
8010 size(3);
8011 format %{ "SAR $dst,$shift" %}
8012 opcode(0xC1, 0x7); /* C1 /7 ib */
8013 ins_encode( RegOpcImm( dst, shift ) );
8014 ins_pipe( ialu_mem_imm );
8015 %}
8016
8017 // Arithmetic Shift Right by 8-bit immediate
8018 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8019 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8020 effect(KILL cr);
8021
8022 format %{ "SAR $dst,$shift" %}
8023 opcode(0xC1, 0x7); /* C1 /7 ib */
8024 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8025 ins_pipe( ialu_mem_imm );
8026 %}
8027
8028 // Arithmetic Shift Right by variable
8029 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8030 match(Set dst (RShiftI dst shift));
8031 effect(KILL cr);
8032
8033 size(2);
8034 format %{ "SAR $dst,$shift" %}
8035 opcode(0xD3, 0x7); /* D3 /7 */
8036 ins_encode( OpcP, RegOpc( dst ) );
8037 ins_pipe( ialu_reg_reg );
8038 %}
8039
8040 // Logical shift right by one
8041 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8042 match(Set dst (URShiftI dst shift));
8043 effect(KILL cr);
8044
8045 size(2);
8046 format %{ "SHR $dst,$shift" %}
8047 opcode(0xD1, 0x5); /* D1 /5 */
8048 ins_encode( OpcP, RegOpc( dst ) );
8049 ins_pipe( ialu_reg );
8050 %}
8051
8052 // Logical Shift Right by 8-bit immediate
8053 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8054 match(Set dst (URShiftI dst shift));
8055 effect(KILL cr);
8056
8057 size(3);
8058 format %{ "SHR $dst,$shift" %}
8059 opcode(0xC1, 0x5); /* C1 /5 ib */
8060 ins_encode( RegOpcImm( dst, shift) );
8061 ins_pipe( ialu_reg );
8062 %}
8063
8064
8065 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8066 // This idiom is used by the compiler for the i2b bytecode.
8067 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8068 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8069
8070 size(3);
8071 format %{ "MOVSX $dst,$src :8" %}
8072 ins_encode %{
8073 __ movsbl($dst$$Register, $src$$Register);
8074 %}
8075 ins_pipe(ialu_reg_reg);
8076 %}
8077
8078 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8079 // This idiom is used by the compiler the i2s bytecode.
8080 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8081 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8082
8083 size(3);
8084 format %{ "MOVSX $dst,$src :16" %}
8085 ins_encode %{
8086 __ movswl($dst$$Register, $src$$Register);
8087 %}
8088 ins_pipe(ialu_reg_reg);
8089 %}
8090
8091
8092 // Logical Shift Right by variable
8093 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8094 match(Set dst (URShiftI dst shift));
8095 effect(KILL cr);
8096
8097 size(2);
8098 format %{ "SHR $dst,$shift" %}
8099 opcode(0xD3, 0x5); /* D3 /5 */
8100 ins_encode( OpcP, RegOpc( dst ) );
8101 ins_pipe( ialu_reg_reg );
8102 %}
8103
8104
8105 //----------Logical Instructions-----------------------------------------------
8106 //----------Integer Logical Instructions---------------------------------------
8107 // And Instructions
8108 // And Register with Register
8109 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8110 match(Set dst (AndI dst src));
8111 effect(KILL cr);
8112
8113 size(2);
8114 format %{ "AND $dst,$src" %}
8115 opcode(0x23);
8116 ins_encode( OpcP, RegReg( dst, src) );
8117 ins_pipe( ialu_reg_reg );
8118 %}
8119
8120 // And Register with Immediate
8121 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8122 match(Set dst (AndI dst src));
8123 effect(KILL cr);
8124
8125 format %{ "AND $dst,$src" %}
8126 opcode(0x81,0x04); /* Opcode 81 /4 */
8127 // ins_encode( RegImm( dst, src) );
8128 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8129 ins_pipe( ialu_reg );
8130 %}
8131
8132 // And Register with Memory
8133 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8134 match(Set dst (AndI dst (LoadI src)));
8135 effect(KILL cr);
8136
8137 ins_cost(125);
8138 format %{ "AND $dst,$src" %}
8139 opcode(0x23);
8140 ins_encode( OpcP, RegMem( dst, src) );
8141 ins_pipe( ialu_reg_mem );
8142 %}
8143
8144 // And Memory with Register
8145 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8146 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8147 effect(KILL cr);
8148
8149 ins_cost(150);
8150 format %{ "AND $dst,$src" %}
8151 opcode(0x21); /* Opcode 21 /r */
8152 ins_encode( OpcP, RegMem( src, dst ) );
8153 ins_pipe( ialu_mem_reg );
8154 %}
8155
8156 // And Memory with Immediate
8157 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8158 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8159 effect(KILL cr);
8160
8161 ins_cost(125);
8162 format %{ "AND $dst,$src" %}
8163 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8164 // ins_encode( MemImm( dst, src) );
8165 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8166 ins_pipe( ialu_mem_imm );
8167 %}
8168
8169 // Or Instructions
8170 // Or Register with Register
8171 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8172 match(Set dst (OrI dst src));
8173 effect(KILL cr);
8174
8175 size(2);
8176 format %{ "OR $dst,$src" %}
8177 opcode(0x0B);
8178 ins_encode( OpcP, RegReg( dst, src) );
8179 ins_pipe( ialu_reg_reg );
8180 %}
8181
8182 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8183 match(Set dst (OrI dst (CastP2X src)));
8184 effect(KILL cr);
8185
8186 size(2);
8187 format %{ "OR $dst,$src" %}
8188 opcode(0x0B);
8189 ins_encode( OpcP, RegReg( dst, src) );
8190 ins_pipe( ialu_reg_reg );
8191 %}
8192
8193
8194 // Or Register with Immediate
8195 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8196 match(Set dst (OrI dst src));
8197 effect(KILL cr);
8198
8199 format %{ "OR $dst,$src" %}
8200 opcode(0x81,0x01); /* Opcode 81 /1 id */
8201 // ins_encode( RegImm( dst, src) );
8202 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8203 ins_pipe( ialu_reg );
8204 %}
8205
8206 // Or Register with Memory
8207 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8208 match(Set dst (OrI dst (LoadI src)));
8209 effect(KILL cr);
8210
8211 ins_cost(125);
8212 format %{ "OR $dst,$src" %}
8213 opcode(0x0B);
8214 ins_encode( OpcP, RegMem( dst, src) );
8215 ins_pipe( ialu_reg_mem );
8216 %}
8217
8218 // Or Memory with Register
8219 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8220 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8221 effect(KILL cr);
8222
8223 ins_cost(150);
8224 format %{ "OR $dst,$src" %}
8225 opcode(0x09); /* Opcode 09 /r */
8226 ins_encode( OpcP, RegMem( src, dst ) );
8227 ins_pipe( ialu_mem_reg );
8228 %}
8229
8230 // Or Memory with Immediate
8231 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8232 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8233 effect(KILL cr);
8234
8235 ins_cost(125);
8236 format %{ "OR $dst,$src" %}
8237 opcode(0x81,0x1); /* Opcode 81 /1 id */
8238 // ins_encode( MemImm( dst, src) );
8239 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8240 ins_pipe( ialu_mem_imm );
8241 %}
8242
8243 // ROL/ROR
8244 // ROL expand
8245 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8246 effect(USE_DEF dst, USE shift, KILL cr);
8247
8248 format %{ "ROL $dst, $shift" %}
8249 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8250 ins_encode( OpcP, RegOpc( dst ));
8251 ins_pipe( ialu_reg );
8252 %}
8253
8254 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8255 effect(USE_DEF dst, USE shift, KILL cr);
8256
8257 format %{ "ROL $dst, $shift" %}
8258 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8259 ins_encode( RegOpcImm(dst, shift) );
8260 ins_pipe(ialu_reg);
8261 %}
8262
8263 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8264 effect(USE_DEF dst, USE shift, KILL cr);
8265
8266 format %{ "ROL $dst, $shift" %}
8267 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8268 ins_encode(OpcP, RegOpc(dst));
8269 ins_pipe( ialu_reg_reg );
8270 %}
8271 // end of ROL expand
8272
8273 // ROL 32bit by one once
8274 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8275 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8276
8277 expand %{
8278 rolI_eReg_imm1(dst, lshift, cr);
8279 %}
8280 %}
8281
8282 // ROL 32bit var by imm8 once
8283 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8284 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8285 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8286
8287 expand %{
8288 rolI_eReg_imm8(dst, lshift, cr);
8289 %}
8290 %}
8291
8292 // ROL 32bit var by var once
8293 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8294 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8295
8296 expand %{
8297 rolI_eReg_CL(dst, shift, cr);
8298 %}
8299 %}
8300
8301 // ROL 32bit var by var once
8302 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8303 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8304
8305 expand %{
8306 rolI_eReg_CL(dst, shift, cr);
8307 %}
8308 %}
8309
8310 // ROR expand
8311 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8312 effect(USE_DEF dst, USE shift, KILL cr);
8313
8314 format %{ "ROR $dst, $shift" %}
8315 opcode(0xD1,0x1); /* Opcode D1 /1 */
8316 ins_encode( OpcP, RegOpc( dst ) );
8317 ins_pipe( ialu_reg );
8318 %}
8319
8320 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8321 effect (USE_DEF dst, USE shift, KILL cr);
8322
8323 format %{ "ROR $dst, $shift" %}
8324 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8325 ins_encode( RegOpcImm(dst, shift) );
8326 ins_pipe( ialu_reg );
8327 %}
8328
8329 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8330 effect(USE_DEF dst, USE shift, KILL cr);
8331
8332 format %{ "ROR $dst, $shift" %}
8333 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8334 ins_encode(OpcP, RegOpc(dst));
8335 ins_pipe( ialu_reg_reg );
8336 %}
8337 // end of ROR expand
8338
8339 // ROR right once
8340 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8341 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8342
8343 expand %{
8344 rorI_eReg_imm1(dst, rshift, cr);
8345 %}
8346 %}
8347
8348 // ROR 32bit by immI8 once
8349 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8350 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8351 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8352
8353 expand %{
8354 rorI_eReg_imm8(dst, rshift, cr);
8355 %}
8356 %}
8357
8358 // ROR 32bit var by var once
8359 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8360 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8361
8362 expand %{
8363 rorI_eReg_CL(dst, shift, cr);
8364 %}
8365 %}
8366
8367 // ROR 32bit var by var once
8368 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8369 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8370
8371 expand %{
8372 rorI_eReg_CL(dst, shift, cr);
8373 %}
8374 %}
8375
8376 // Xor Instructions
8377 // Xor Register with Register
8378 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8379 match(Set dst (XorI dst src));
8380 effect(KILL cr);
8381
8382 size(2);
8383 format %{ "XOR $dst,$src" %}
8384 opcode(0x33);
8385 ins_encode( OpcP, RegReg( dst, src) );
8386 ins_pipe( ialu_reg_reg );
8387 %}
8388
8389 // Xor Register with Immediate -1
8390 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8391 match(Set dst (XorI dst imm));
8392
8393 size(2);
8394 format %{ "NOT $dst" %}
8395 ins_encode %{
8396 __ notl($dst$$Register);
8397 %}
8398 ins_pipe( ialu_reg );
8399 %}
8400
8401 // Xor Register with Immediate
8402 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8403 match(Set dst (XorI dst src));
8404 effect(KILL cr);
8405
8406 format %{ "XOR $dst,$src" %}
8407 opcode(0x81,0x06); /* Opcode 81 /6 id */
8408 // ins_encode( RegImm( dst, src) );
8409 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8410 ins_pipe( ialu_reg );
8411 %}
8412
8413 // Xor Register with Memory
8414 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8415 match(Set dst (XorI dst (LoadI src)));
8416 effect(KILL cr);
8417
8418 ins_cost(125);
8419 format %{ "XOR $dst,$src" %}
8420 opcode(0x33);
8421 ins_encode( OpcP, RegMem(dst, src) );
8422 ins_pipe( ialu_reg_mem );
8423 %}
8424
8425 // Xor Memory with Register
8426 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8427 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8428 effect(KILL cr);
8429
8430 ins_cost(150);
8431 format %{ "XOR $dst,$src" %}
8432 opcode(0x31); /* Opcode 31 /r */
8433 ins_encode( OpcP, RegMem( src, dst ) );
8434 ins_pipe( ialu_mem_reg );
8435 %}
8436
8437 // Xor Memory with Immediate
8438 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8439 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8440 effect(KILL cr);
8441
8442 ins_cost(125);
8443 format %{ "XOR $dst,$src" %}
8444 opcode(0x81,0x6); /* Opcode 81 /6 id */
8445 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8446 ins_pipe( ialu_mem_imm );
8447 %}
8448
8449 //----------Convert Int to Boolean---------------------------------------------
8450
8451 instruct movI_nocopy(rRegI dst, rRegI src) %{
8452 effect( DEF dst, USE src );
8453 format %{ "MOV $dst,$src" %}
8454 ins_encode( enc_Copy( dst, src) );
8455 ins_pipe( ialu_reg_reg );
8456 %}
8457
8458 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8459 effect( USE_DEF dst, USE src, KILL cr );
8460
8461 size(4);
8462 format %{ "NEG $dst\n\t"
8463 "ADC $dst,$src" %}
8464 ins_encode( neg_reg(dst),
8465 OpcRegReg(0x13,dst,src) );
8466 ins_pipe( ialu_reg_reg_long );
8467 %}
8468
8469 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8470 match(Set dst (Conv2B src));
8471
8472 expand %{
8473 movI_nocopy(dst,src);
8474 ci2b(dst,src,cr);
8475 %}
8476 %}
8477
8478 instruct movP_nocopy(rRegI dst, eRegP src) %{
8479 effect( DEF dst, USE src );
8480 format %{ "MOV $dst,$src" %}
8481 ins_encode( enc_Copy( dst, src) );
8482 ins_pipe( ialu_reg_reg );
8483 %}
8484
8485 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8486 effect( USE_DEF dst, USE src, KILL cr );
8487 format %{ "NEG $dst\n\t"
8488 "ADC $dst,$src" %}
8489 ins_encode( neg_reg(dst),
8490 OpcRegReg(0x13,dst,src) );
8491 ins_pipe( ialu_reg_reg_long );
8492 %}
8493
8494 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8495 match(Set dst (Conv2B src));
8496
8497 expand %{
8498 movP_nocopy(dst,src);
8499 cp2b(dst,src,cr);
8500 %}
8501 %}
8502
8503 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
8504 match(Set dst (CmpLTMask p q));
8505 effect(KILL cr);
8506 ins_cost(400);
8507
8508 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8509 format %{ "XOR $dst,$dst\n\t"
8510 "CMP $p,$q\n\t"
8511 "SETlt $dst\n\t"
8512 "NEG $dst" %}
8513 ins_encode %{
8514 Register Rp = $p$$Register;
8515 Register Rq = $q$$Register;
8516 Register Rd = $dst$$Register;
8517 Label done;
8518 __ xorl(Rd, Rd);
8519 __ cmpl(Rp, Rq);
8520 __ setb(Assembler::less, Rd);
8521 __ negl(Rd);
8522 %}
8523
8524 ins_pipe(pipe_slow);
8525 %}
8526
8527 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
8528 match(Set dst (CmpLTMask dst zero));
8529 effect(DEF dst, KILL cr);
8530 ins_cost(100);
8531
8532 format %{ "SAR $dst,31\t# cmpLTMask0" %}
8533 ins_encode %{
8534 __ sarl($dst$$Register, 31);
8535 %}
8536 ins_pipe(ialu_reg);
8537 %}
8538
8539 /* better to save a register than avoid a branch */
8540 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8541 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8542 effect(KILL cr);
8543 ins_cost(400);
8544 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
8545 "JGE done\n\t"
8546 "ADD $p,$y\n"
8547 "done: " %}
8548 ins_encode %{
8549 Register Rp = $p$$Register;
8550 Register Rq = $q$$Register;
8551 Register Ry = $y$$Register;
8552 Label done;
8553 __ subl(Rp, Rq);
8554 __ jccb(Assembler::greaterEqual, done);
8555 __ addl(Rp, Ry);
8556 __ bind(done);
8557 %}
8558
8559 ins_pipe(pipe_cmplt);
8560 %}
8561
8562 /* better to save a register than avoid a branch */
8563 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
8564 match(Set y (AndI (CmpLTMask p q) y));
8565 effect(KILL cr);
8566
8567 ins_cost(300);
8568
8569 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t"
8570 "JLT done\n\t"
8571 "XORL $y, $y\n"
8572 "done: " %}
8573 ins_encode %{
8574 Register Rp = $p$$Register;
8575 Register Rq = $q$$Register;
8576 Register Ry = $y$$Register;
8577 Label done;
8578 __ cmpl(Rp, Rq);
8579 __ jccb(Assembler::less, done);
8580 __ xorl(Ry, Ry);
8581 __ bind(done);
8582 %}
8583
8584 ins_pipe(pipe_cmplt);
8585 %}
8586
8587 /* If I enable this, I encourage spilling in the inner loop of compress.
8588 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
8589 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8590 */
8591
8592 //----------Long Instructions------------------------------------------------
8593 // Add Long Register with Register
8594 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8595 match(Set dst (AddL dst src));
8596 effect(KILL cr);
8597 ins_cost(200);
8598 format %{ "ADD $dst.lo,$src.lo\n\t"
8599 "ADC $dst.hi,$src.hi" %}
8600 opcode(0x03, 0x13);
8601 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8602 ins_pipe( ialu_reg_reg_long );
8603 %}
8604
8605 // Add Long Register with Immediate
8606 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8607 match(Set dst (AddL dst src));
8608 effect(KILL cr);
8609 format %{ "ADD $dst.lo,$src.lo\n\t"
8610 "ADC $dst.hi,$src.hi" %}
8611 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
8612 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8613 ins_pipe( ialu_reg_long );
8614 %}
8615
8616 // Add Long Register with Memory
8617 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8618 match(Set dst (AddL dst (LoadL mem)));
8619 effect(KILL cr);
8620 ins_cost(125);
8621 format %{ "ADD $dst.lo,$mem\n\t"
8622 "ADC $dst.hi,$mem+4" %}
8623 opcode(0x03, 0x13);
8624 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8625 ins_pipe( ialu_reg_long_mem );
8626 %}
8627
8628 // Subtract Long Register with Register.
8629 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8630 match(Set dst (SubL dst src));
8631 effect(KILL cr);
8632 ins_cost(200);
8633 format %{ "SUB $dst.lo,$src.lo\n\t"
8634 "SBB $dst.hi,$src.hi" %}
8635 opcode(0x2B, 0x1B);
8636 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8637 ins_pipe( ialu_reg_reg_long );
8638 %}
8639
8640 // Subtract Long Register with Immediate
8641 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8642 match(Set dst (SubL dst src));
8643 effect(KILL cr);
8644 format %{ "SUB $dst.lo,$src.lo\n\t"
8645 "SBB $dst.hi,$src.hi" %}
8646 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
8647 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8648 ins_pipe( ialu_reg_long );
8649 %}
8650
8651 // Subtract Long Register with Memory
8652 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8653 match(Set dst (SubL dst (LoadL mem)));
8654 effect(KILL cr);
8655 ins_cost(125);
8656 format %{ "SUB $dst.lo,$mem\n\t"
8657 "SBB $dst.hi,$mem+4" %}
8658 opcode(0x2B, 0x1B);
8659 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8660 ins_pipe( ialu_reg_long_mem );
8661 %}
8662
8663 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
8664 match(Set dst (SubL zero dst));
8665 effect(KILL cr);
8666 ins_cost(300);
8667 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
8668 ins_encode( neg_long(dst) );
8669 ins_pipe( ialu_reg_reg_long );
8670 %}
8671
8672 // And Long Register with Register
8673 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8674 match(Set dst (AndL dst src));
8675 effect(KILL cr);
8676 format %{ "AND $dst.lo,$src.lo\n\t"
8677 "AND $dst.hi,$src.hi" %}
8678 opcode(0x23,0x23);
8679 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8680 ins_pipe( ialu_reg_reg_long );
8681 %}
8682
8683 // And Long Register with Immediate
8684 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8685 match(Set dst (AndL dst src));
8686 effect(KILL cr);
8687 format %{ "AND $dst.lo,$src.lo\n\t"
8688 "AND $dst.hi,$src.hi" %}
8689 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
8690 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8691 ins_pipe( ialu_reg_long );
8692 %}
8693
8694 // And Long Register with Memory
8695 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8696 match(Set dst (AndL dst (LoadL mem)));
8697 effect(KILL cr);
8698 ins_cost(125);
8699 format %{ "AND $dst.lo,$mem\n\t"
8700 "AND $dst.hi,$mem+4" %}
8701 opcode(0x23, 0x23);
8702 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8703 ins_pipe( ialu_reg_long_mem );
8704 %}
8705
8706 // Or Long Register with Register
8707 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8708 match(Set dst (OrL dst src));
8709 effect(KILL cr);
8710 format %{ "OR $dst.lo,$src.lo\n\t"
8711 "OR $dst.hi,$src.hi" %}
8712 opcode(0x0B,0x0B);
8713 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8714 ins_pipe( ialu_reg_reg_long );
8715 %}
8716
8717 // Or Long Register with Immediate
8718 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8719 match(Set dst (OrL dst src));
8720 effect(KILL cr);
8721 format %{ "OR $dst.lo,$src.lo\n\t"
8722 "OR $dst.hi,$src.hi" %}
8723 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
8724 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8725 ins_pipe( ialu_reg_long );
8726 %}
8727
8728 // Or Long Register with Memory
8729 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8730 match(Set dst (OrL dst (LoadL mem)));
8731 effect(KILL cr);
8732 ins_cost(125);
8733 format %{ "OR $dst.lo,$mem\n\t"
8734 "OR $dst.hi,$mem+4" %}
8735 opcode(0x0B,0x0B);
8736 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8737 ins_pipe( ialu_reg_long_mem );
8738 %}
8739
8740 // Xor Long Register with Register
8741 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8742 match(Set dst (XorL dst src));
8743 effect(KILL cr);
8744 format %{ "XOR $dst.lo,$src.lo\n\t"
8745 "XOR $dst.hi,$src.hi" %}
8746 opcode(0x33,0x33);
8747 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8748 ins_pipe( ialu_reg_reg_long );
8749 %}
8750
8751 // Xor Long Register with Immediate -1
8752 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
8753 match(Set dst (XorL dst imm));
8754 format %{ "NOT $dst.lo\n\t"
8755 "NOT $dst.hi" %}
8756 ins_encode %{
8757 __ notl($dst$$Register);
8758 __ notl(HIGH_FROM_LOW($dst$$Register));
8759 %}
8760 ins_pipe( ialu_reg_long );
8761 %}
8762
8763 // Xor Long Register with Immediate
8764 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8765 match(Set dst (XorL dst src));
8766 effect(KILL cr);
8767 format %{ "XOR $dst.lo,$src.lo\n\t"
8768 "XOR $dst.hi,$src.hi" %}
8769 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
8770 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8771 ins_pipe( ialu_reg_long );
8772 %}
8773
8774 // Xor Long Register with Memory
8775 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8776 match(Set dst (XorL dst (LoadL mem)));
8777 effect(KILL cr);
8778 ins_cost(125);
8779 format %{ "XOR $dst.lo,$mem\n\t"
8780 "XOR $dst.hi,$mem+4" %}
8781 opcode(0x33,0x33);
8782 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8783 ins_pipe( ialu_reg_long_mem );
8784 %}
8785
8786 // Shift Left Long by 1
8787 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
8788 predicate(UseNewLongLShift);
8789 match(Set dst (LShiftL dst cnt));
8790 effect(KILL cr);
8791 ins_cost(100);
8792 format %{ "ADD $dst.lo,$dst.lo\n\t"
8793 "ADC $dst.hi,$dst.hi" %}
8794 ins_encode %{
8795 __ addl($dst$$Register,$dst$$Register);
8796 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8797 %}
8798 ins_pipe( ialu_reg_long );
8799 %}
8800
8801 // Shift Left Long by 2
8802 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
8803 predicate(UseNewLongLShift);
8804 match(Set dst (LShiftL dst cnt));
8805 effect(KILL cr);
8806 ins_cost(100);
8807 format %{ "ADD $dst.lo,$dst.lo\n\t"
8808 "ADC $dst.hi,$dst.hi\n\t"
8809 "ADD $dst.lo,$dst.lo\n\t"
8810 "ADC $dst.hi,$dst.hi" %}
8811 ins_encode %{
8812 __ addl($dst$$Register,$dst$$Register);
8813 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8814 __ addl($dst$$Register,$dst$$Register);
8815 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8816 %}
8817 ins_pipe( ialu_reg_long );
8818 %}
8819
8820 // Shift Left Long by 3
8821 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
8822 predicate(UseNewLongLShift);
8823 match(Set dst (LShiftL dst cnt));
8824 effect(KILL cr);
8825 ins_cost(100);
8826 format %{ "ADD $dst.lo,$dst.lo\n\t"
8827 "ADC $dst.hi,$dst.hi\n\t"
8828 "ADD $dst.lo,$dst.lo\n\t"
8829 "ADC $dst.hi,$dst.hi\n\t"
8830 "ADD $dst.lo,$dst.lo\n\t"
8831 "ADC $dst.hi,$dst.hi" %}
8832 ins_encode %{
8833 __ addl($dst$$Register,$dst$$Register);
8834 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8835 __ addl($dst$$Register,$dst$$Register);
8836 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8837 __ addl($dst$$Register,$dst$$Register);
8838 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8839 %}
8840 ins_pipe( ialu_reg_long );
8841 %}
8842
8843 // Shift Left Long by 1-31
8844 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
8845 match(Set dst (LShiftL dst cnt));
8846 effect(KILL cr);
8847 ins_cost(200);
8848 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
8849 "SHL $dst.lo,$cnt" %}
8850 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
8851 ins_encode( move_long_small_shift(dst,cnt) );
8852 ins_pipe( ialu_reg_long );
8853 %}
8854
8855 // Shift Left Long by 32-63
8856 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
8857 match(Set dst (LShiftL dst cnt));
8858 effect(KILL cr);
8859 ins_cost(300);
8860 format %{ "MOV $dst.hi,$dst.lo\n"
8861 "\tSHL $dst.hi,$cnt-32\n"
8862 "\tXOR $dst.lo,$dst.lo" %}
8863 opcode(0xC1, 0x4); /* C1 /4 ib */
8864 ins_encode( move_long_big_shift_clr(dst,cnt) );
8865 ins_pipe( ialu_reg_long );
8866 %}
8867
8868 // Shift Left Long by variable
8869 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
8870 match(Set dst (LShiftL dst shift));
8871 effect(KILL cr);
8872 ins_cost(500+200);
8873 size(17);
8874 format %{ "TEST $shift,32\n\t"
8875 "JEQ,s small\n\t"
8876 "MOV $dst.hi,$dst.lo\n\t"
8877 "XOR $dst.lo,$dst.lo\n"
8878 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
8879 "SHL $dst.lo,$shift" %}
8880 ins_encode( shift_left_long( dst, shift ) );
8881 ins_pipe( pipe_slow );
8882 %}
8883
8884 // Shift Right Long by 1-31
8885 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
8886 match(Set dst (URShiftL dst cnt));
8887 effect(KILL cr);
8888 ins_cost(200);
8889 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
8890 "SHR $dst.hi,$cnt" %}
8891 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
8892 ins_encode( move_long_small_shift(dst,cnt) );
8893 ins_pipe( ialu_reg_long );
8894 %}
8895
8896 // Shift Right Long by 32-63
8897 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
8898 match(Set dst (URShiftL dst cnt));
8899 effect(KILL cr);
8900 ins_cost(300);
8901 format %{ "MOV $dst.lo,$dst.hi\n"
8902 "\tSHR $dst.lo,$cnt-32\n"
8903 "\tXOR $dst.hi,$dst.hi" %}
8904 opcode(0xC1, 0x5); /* C1 /5 ib */
8905 ins_encode( move_long_big_shift_clr(dst,cnt) );
8906 ins_pipe( ialu_reg_long );
8907 %}
8908
8909 // Shift Right Long by variable
8910 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
8911 match(Set dst (URShiftL dst shift));
8912 effect(KILL cr);
8913 ins_cost(600);
8914 size(17);
8915 format %{ "TEST $shift,32\n\t"
8916 "JEQ,s small\n\t"
8917 "MOV $dst.lo,$dst.hi\n\t"
8918 "XOR $dst.hi,$dst.hi\n"
8919 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
8920 "SHR $dst.hi,$shift" %}
8921 ins_encode( shift_right_long( dst, shift ) );
8922 ins_pipe( pipe_slow );
8923 %}
8924
8925 // Shift Right Long by 1-31
8926 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
8927 match(Set dst (RShiftL dst cnt));
8928 effect(KILL cr);
8929 ins_cost(200);
8930 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
8931 "SAR $dst.hi,$cnt" %}
8932 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
8933 ins_encode( move_long_small_shift(dst,cnt) );
8934 ins_pipe( ialu_reg_long );
8935 %}
8936
8937 // Shift Right Long by 32-63
8938 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
8939 match(Set dst (RShiftL dst cnt));
8940 effect(KILL cr);
8941 ins_cost(300);
8942 format %{ "MOV $dst.lo,$dst.hi\n"
8943 "\tSAR $dst.lo,$cnt-32\n"
8944 "\tSAR $dst.hi,31" %}
8945 opcode(0xC1, 0x7); /* C1 /7 ib */
8946 ins_encode( move_long_big_shift_sign(dst,cnt) );
8947 ins_pipe( ialu_reg_long );
8948 %}
8949
8950 // Shift Right arithmetic Long by variable
8951 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
8952 match(Set dst (RShiftL dst shift));
8953 effect(KILL cr);
8954 ins_cost(600);
8955 size(18);
8956 format %{ "TEST $shift,32\n\t"
8957 "JEQ,s small\n\t"
8958 "MOV $dst.lo,$dst.hi\n\t"
8959 "SAR $dst.hi,31\n"
8960 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
8961 "SAR $dst.hi,$shift" %}
8962 ins_encode( shift_right_arith_long( dst, shift ) );
8963 ins_pipe( pipe_slow );
8964 %}
8965
8966
8967 //----------Double Instructions------------------------------------------------
8968 // Double Math
8969
8970 // Compare & branch
8971
8972 // P6 version of float compare, sets condition codes in EFLAGS
8973 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
8974 predicate(VM_Version::supports_cmov() && UseSSE <=1);
8975 match(Set cr (CmpD src1 src2));
8976 effect(KILL rax);
8977 ins_cost(150);
8978 format %{ "FLD $src1\n\t"
8979 "FUCOMIP ST,$src2 // P6 instruction\n\t"
8980 "JNP exit\n\t"
8981 "MOV ah,1 // saw a NaN, set CF\n\t"
8982 "SAHF\n"
8983 "exit:\tNOP // avoid branch to branch" %}
8984 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
8985 ins_encode( Push_Reg_DPR(src1),
8986 OpcP, RegOpc(src2),
8987 cmpF_P6_fixup );
8988 ins_pipe( pipe_slow );
8989 %}
8990
8991 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
8992 predicate(VM_Version::supports_cmov() && UseSSE <=1);
8993 match(Set cr (CmpD src1 src2));
8994 ins_cost(150);
8995 format %{ "FLD $src1\n\t"
8996 "FUCOMIP ST,$src2 // P6 instruction" %}
8997 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
8998 ins_encode( Push_Reg_DPR(src1),
8999 OpcP, RegOpc(src2));
9000 ins_pipe( pipe_slow );
9001 %}
9002
9003 // Compare & branch
9004 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9005 predicate(UseSSE<=1);
9006 match(Set cr (CmpD src1 src2));
9007 effect(KILL rax);
9008 ins_cost(200);
9009 format %{ "FLD $src1\n\t"
9010 "FCOMp $src2\n\t"
9011 "FNSTSW AX\n\t"
9012 "TEST AX,0x400\n\t"
9013 "JZ,s flags\n\t"
9014 "MOV AH,1\t# unordered treat as LT\n"
9015 "flags:\tSAHF" %}
9016 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9017 ins_encode( Push_Reg_DPR(src1),
9018 OpcP, RegOpc(src2),
9019 fpu_flags);
9020 ins_pipe( pipe_slow );
9021 %}
9022
9023 // Compare vs zero into -1,0,1
9024 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9025 predicate(UseSSE<=1);
9026 match(Set dst (CmpD3 src1 zero));
9027 effect(KILL cr, KILL rax);
9028 ins_cost(280);
9029 format %{ "FTSTD $dst,$src1" %}
9030 opcode(0xE4, 0xD9);
9031 ins_encode( Push_Reg_DPR(src1),
9032 OpcS, OpcP, PopFPU,
9033 CmpF_Result(dst));
9034 ins_pipe( pipe_slow );
9035 %}
9036
9037 // Compare into -1,0,1
9038 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9039 predicate(UseSSE<=1);
9040 match(Set dst (CmpD3 src1 src2));
9041 effect(KILL cr, KILL rax);
9042 ins_cost(300);
9043 format %{ "FCMPD $dst,$src1,$src2" %}
9044 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9045 ins_encode( Push_Reg_DPR(src1),
9046 OpcP, RegOpc(src2),
9047 CmpF_Result(dst));
9048 ins_pipe( pipe_slow );
9049 %}
9050
9051 // float compare and set condition codes in EFLAGS by XMM regs
9052 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9053 predicate(UseSSE>=2);
9054 match(Set cr (CmpD src1 src2));
9055 ins_cost(145);
9056 format %{ "UCOMISD $src1,$src2\n\t"
9057 "JNP,s exit\n\t"
9058 "PUSHF\t# saw NaN, set CF\n\t"
9059 "AND [rsp], #0xffffff2b\n\t"
9060 "POPF\n"
9061 "exit:" %}
9062 ins_encode %{
9063 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9064 emit_cmpfp_fixup(_masm);
9065 %}
9066 ins_pipe( pipe_slow );
9067 %}
9068
9069 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9070 predicate(UseSSE>=2);
9071 match(Set cr (CmpD src1 src2));
9072 ins_cost(100);
9073 format %{ "UCOMISD $src1,$src2" %}
9074 ins_encode %{
9075 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9076 %}
9077 ins_pipe( pipe_slow );
9078 %}
9079
9080 // float compare and set condition codes in EFLAGS by XMM regs
9081 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9082 predicate(UseSSE>=2);
9083 match(Set cr (CmpD src1 (LoadD src2)));
9084 ins_cost(145);
9085 format %{ "UCOMISD $src1,$src2\n\t"
9086 "JNP,s exit\n\t"
9087 "PUSHF\t# saw NaN, set CF\n\t"
9088 "AND [rsp], #0xffffff2b\n\t"
9089 "POPF\n"
9090 "exit:" %}
9091 ins_encode %{
9092 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9093 emit_cmpfp_fixup(_masm);
9094 %}
9095 ins_pipe( pipe_slow );
9096 %}
9097
9098 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9099 predicate(UseSSE>=2);
9100 match(Set cr (CmpD src1 (LoadD src2)));
9101 ins_cost(100);
9102 format %{ "UCOMISD $src1,$src2" %}
9103 ins_encode %{
9104 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9105 %}
9106 ins_pipe( pipe_slow );
9107 %}
9108
9109 // Compare into -1,0,1 in XMM
9110 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9111 predicate(UseSSE>=2);
9112 match(Set dst (CmpD3 src1 src2));
9113 effect(KILL cr);
9114 ins_cost(255);
9115 format %{ "UCOMISD $src1, $src2\n\t"
9116 "MOV $dst, #-1\n\t"
9117 "JP,s done\n\t"
9118 "JB,s done\n\t"
9119 "SETNE $dst\n\t"
9120 "MOVZB $dst, $dst\n"
9121 "done:" %}
9122 ins_encode %{
9123 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9124 emit_cmpfp3(_masm, $dst$$Register);
9125 %}
9126 ins_pipe( pipe_slow );
9127 %}
9128
9129 // Compare into -1,0,1 in XMM and memory
9130 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9131 predicate(UseSSE>=2);
9132 match(Set dst (CmpD3 src1 (LoadD src2)));
9133 effect(KILL cr);
9134 ins_cost(275);
9135 format %{ "UCOMISD $src1, $src2\n\t"
9136 "MOV $dst, #-1\n\t"
9137 "JP,s done\n\t"
9138 "JB,s done\n\t"
9139 "SETNE $dst\n\t"
9140 "MOVZB $dst, $dst\n"
9141 "done:" %}
9142 ins_encode %{
9143 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9144 emit_cmpfp3(_masm, $dst$$Register);
9145 %}
9146 ins_pipe( pipe_slow );
9147 %}
9148
9149
9150 instruct subDPR_reg(regDPR dst, regDPR src) %{
9151 predicate (UseSSE <=1);
9152 match(Set dst (SubD dst src));
9153
9154 format %{ "FLD $src\n\t"
9155 "DSUBp $dst,ST" %}
9156 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9157 ins_cost(150);
9158 ins_encode( Push_Reg_DPR(src),
9159 OpcP, RegOpc(dst) );
9160 ins_pipe( fpu_reg_reg );
9161 %}
9162
9163 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9164 predicate (UseSSE <=1);
9165 match(Set dst (RoundDouble (SubD src1 src2)));
9166 ins_cost(250);
9167
9168 format %{ "FLD $src2\n\t"
9169 "DSUB ST,$src1\n\t"
9170 "FSTP_D $dst\t# D-round" %}
9171 opcode(0xD8, 0x5);
9172 ins_encode( Push_Reg_DPR(src2),
9173 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9174 ins_pipe( fpu_mem_reg_reg );
9175 %}
9176
9177
9178 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9179 predicate (UseSSE <=1);
9180 match(Set dst (SubD dst (LoadD src)));
9181 ins_cost(150);
9182
9183 format %{ "FLD $src\n\t"
9184 "DSUBp $dst,ST" %}
9185 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9186 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9187 OpcP, RegOpc(dst) );
9188 ins_pipe( fpu_reg_mem );
9189 %}
9190
9191 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9192 predicate (UseSSE<=1);
9193 match(Set dst (AbsD src));
9194 ins_cost(100);
9195 format %{ "FABS" %}
9196 opcode(0xE1, 0xD9);
9197 ins_encode( OpcS, OpcP );
9198 ins_pipe( fpu_reg_reg );
9199 %}
9200
9201 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9202 predicate(UseSSE<=1);
9203 match(Set dst (NegD src));
9204 ins_cost(100);
9205 format %{ "FCHS" %}
9206 opcode(0xE0, 0xD9);
9207 ins_encode( OpcS, OpcP );
9208 ins_pipe( fpu_reg_reg );
9209 %}
9210
9211 instruct addDPR_reg(regDPR dst, regDPR src) %{
9212 predicate(UseSSE<=1);
9213 match(Set dst (AddD dst src));
9214 format %{ "FLD $src\n\t"
9215 "DADD $dst,ST" %}
9216 size(4);
9217 ins_cost(150);
9218 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9219 ins_encode( Push_Reg_DPR(src),
9220 OpcP, RegOpc(dst) );
9221 ins_pipe( fpu_reg_reg );
9222 %}
9223
9224
9225 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9226 predicate(UseSSE<=1);
9227 match(Set dst (RoundDouble (AddD src1 src2)));
9228 ins_cost(250);
9229
9230 format %{ "FLD $src2\n\t"
9231 "DADD ST,$src1\n\t"
9232 "FSTP_D $dst\t# D-round" %}
9233 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9234 ins_encode( Push_Reg_DPR(src2),
9235 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9236 ins_pipe( fpu_mem_reg_reg );
9237 %}
9238
9239
9240 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9241 predicate(UseSSE<=1);
9242 match(Set dst (AddD dst (LoadD src)));
9243 ins_cost(150);
9244
9245 format %{ "FLD $src\n\t"
9246 "DADDp $dst,ST" %}
9247 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9248 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9249 OpcP, RegOpc(dst) );
9250 ins_pipe( fpu_reg_mem );
9251 %}
9252
9253 // add-to-memory
9254 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9255 predicate(UseSSE<=1);
9256 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9257 ins_cost(150);
9258
9259 format %{ "FLD_D $dst\n\t"
9260 "DADD ST,$src\n\t"
9261 "FST_D $dst" %}
9262 opcode(0xDD, 0x0);
9263 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9264 Opcode(0xD8), RegOpc(src),
9265 set_instruction_start,
9266 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9267 ins_pipe( fpu_reg_mem );
9268 %}
9269
9270 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9271 predicate(UseSSE<=1);
9272 match(Set dst (AddD dst con));
9273 ins_cost(125);
9274 format %{ "FLD1\n\t"
9275 "DADDp $dst,ST" %}
9276 ins_encode %{
9277 __ fld1();
9278 __ faddp($dst$$reg);
9279 %}
9280 ins_pipe(fpu_reg);
9281 %}
9282
9283 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9284 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9285 match(Set dst (AddD dst con));
9286 ins_cost(200);
9287 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9288 "DADDp $dst,ST" %}
9289 ins_encode %{
9290 __ fld_d($constantaddress($con));
9291 __ faddp($dst$$reg);
9292 %}
9293 ins_pipe(fpu_reg_mem);
9294 %}
9295
9296 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9297 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9298 match(Set dst (RoundDouble (AddD src con)));
9299 ins_cost(200);
9300 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9301 "DADD ST,$src\n\t"
9302 "FSTP_D $dst\t# D-round" %}
9303 ins_encode %{
9304 __ fld_d($constantaddress($con));
9305 __ fadd($src$$reg);
9306 __ fstp_d(Address(rsp, $dst$$disp));
9307 %}
9308 ins_pipe(fpu_mem_reg_con);
9309 %}
9310
9311 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9312 predicate(UseSSE<=1);
9313 match(Set dst (MulD dst src));
9314 format %{ "FLD $src\n\t"
9315 "DMULp $dst,ST" %}
9316 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9317 ins_cost(150);
9318 ins_encode( Push_Reg_DPR(src),
9319 OpcP, RegOpc(dst) );
9320 ins_pipe( fpu_reg_reg );
9321 %}
9322
9323 // Strict FP instruction biases argument before multiply then
9324 // biases result to avoid double rounding of subnormals.
9325 //
9326 // scale arg1 by multiplying arg1 by 2^(-15360)
9327 // load arg2
9328 // multiply scaled arg1 by arg2
9329 // rescale product by 2^(15360)
9330 //
9331 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9332 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9333 match(Set dst (MulD dst src));
9334 ins_cost(1); // Select this instruction for all strict FP double multiplies
9335
9336 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9337 "DMULp $dst,ST\n\t"
9338 "FLD $src\n\t"
9339 "DMULp $dst,ST\n\t"
9340 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9341 "DMULp $dst,ST\n\t" %}
9342 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9343 ins_encode( strictfp_bias1(dst),
9344 Push_Reg_DPR(src),
9345 OpcP, RegOpc(dst),
9346 strictfp_bias2(dst) );
9347 ins_pipe( fpu_reg_reg );
9348 %}
9349
9350 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9351 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9352 match(Set dst (MulD dst con));
9353 ins_cost(200);
9354 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9355 "DMULp $dst,ST" %}
9356 ins_encode %{
9357 __ fld_d($constantaddress($con));
9358 __ fmulp($dst$$reg);
9359 %}
9360 ins_pipe(fpu_reg_mem);
9361 %}
9362
9363
9364 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9365 predicate( UseSSE<=1 );
9366 match(Set dst (MulD dst (LoadD src)));
9367 ins_cost(200);
9368 format %{ "FLD_D $src\n\t"
9369 "DMULp $dst,ST" %}
9370 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9371 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9372 OpcP, RegOpc(dst) );
9373 ins_pipe( fpu_reg_mem );
9374 %}
9375
9376 //
9377 // Cisc-alternate to reg-reg multiply
9378 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9379 predicate( UseSSE<=1 );
9380 match(Set dst (MulD src (LoadD mem)));
9381 ins_cost(250);
9382 format %{ "FLD_D $mem\n\t"
9383 "DMUL ST,$src\n\t"
9384 "FSTP_D $dst" %}
9385 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9386 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9387 OpcReg_FPR(src),
9388 Pop_Reg_DPR(dst) );
9389 ins_pipe( fpu_reg_reg_mem );
9390 %}
9391
9392
9393 // MACRO3 -- addDPR a mulDPR
9394 // This instruction is a '2-address' instruction in that the result goes
9395 // back to src2. This eliminates a move from the macro; possibly the
9396 // register allocator will have to add it back (and maybe not).
9397 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9398 predicate( UseSSE<=1 );
9399 match(Set src2 (AddD (MulD src0 src1) src2));
9400 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9401 "DMUL ST,$src1\n\t"
9402 "DADDp $src2,ST" %}
9403 ins_cost(250);
9404 opcode(0xDD); /* LoadD DD /0 */
9405 ins_encode( Push_Reg_FPR(src0),
9406 FMul_ST_reg(src1),
9407 FAddP_reg_ST(src2) );
9408 ins_pipe( fpu_reg_reg_reg );
9409 %}
9410
9411
9412 // MACRO3 -- subDPR a mulDPR
9413 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9414 predicate( UseSSE<=1 );
9415 match(Set src2 (SubD (MulD src0 src1) src2));
9416 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9417 "DMUL ST,$src1\n\t"
9418 "DSUBRp $src2,ST" %}
9419 ins_cost(250);
9420 ins_encode( Push_Reg_FPR(src0),
9421 FMul_ST_reg(src1),
9422 Opcode(0xDE), Opc_plus(0xE0,src2));
9423 ins_pipe( fpu_reg_reg_reg );
9424 %}
9425
9426
9427 instruct divDPR_reg(regDPR dst, regDPR src) %{
9428 predicate( UseSSE<=1 );
9429 match(Set dst (DivD dst src));
9430
9431 format %{ "FLD $src\n\t"
9432 "FDIVp $dst,ST" %}
9433 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9434 ins_cost(150);
9435 ins_encode( Push_Reg_DPR(src),
9436 OpcP, RegOpc(dst) );
9437 ins_pipe( fpu_reg_reg );
9438 %}
9439
9440 // Strict FP instruction biases argument before division then
9441 // biases result, to avoid double rounding of subnormals.
9442 //
9443 // scale dividend by multiplying dividend by 2^(-15360)
9444 // load divisor
9445 // divide scaled dividend by divisor
9446 // rescale quotient by 2^(15360)
9447 //
9448 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9449 predicate (UseSSE<=1);
9450 match(Set dst (DivD dst src));
9451 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9452 ins_cost(01);
9453
9454 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9455 "DMULp $dst,ST\n\t"
9456 "FLD $src\n\t"
9457 "FDIVp $dst,ST\n\t"
9458 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9459 "DMULp $dst,ST\n\t" %}
9460 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9461 ins_encode( strictfp_bias1(dst),
9462 Push_Reg_DPR(src),
9463 OpcP, RegOpc(dst),
9464 strictfp_bias2(dst) );
9465 ins_pipe( fpu_reg_reg );
9466 %}
9467
9468 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9469 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9470 match(Set dst (RoundDouble (DivD src1 src2)));
9471
9472 format %{ "FLD $src1\n\t"
9473 "FDIV ST,$src2\n\t"
9474 "FSTP_D $dst\t# D-round" %}
9475 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9476 ins_encode( Push_Reg_DPR(src1),
9477 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9478 ins_pipe( fpu_mem_reg_reg );
9479 %}
9480
9481
9482 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9483 predicate(UseSSE<=1);
9484 match(Set dst (ModD dst src));
9485 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9486
9487 format %{ "DMOD $dst,$src" %}
9488 ins_cost(250);
9489 ins_encode(Push_Reg_Mod_DPR(dst, src),
9490 emitModDPR(),
9491 Push_Result_Mod_DPR(src),
9492 Pop_Reg_DPR(dst));
9493 ins_pipe( pipe_slow );
9494 %}
9495
9496 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9497 predicate(UseSSE>=2);
9498 match(Set dst (ModD src0 src1));
9499 effect(KILL rax, KILL cr);
9500
9501 format %{ "SUB ESP,8\t # DMOD\n"
9502 "\tMOVSD [ESP+0],$src1\n"
9503 "\tFLD_D [ESP+0]\n"
9504 "\tMOVSD [ESP+0],$src0\n"
9505 "\tFLD_D [ESP+0]\n"
9506 "loop:\tFPREM\n"
9507 "\tFWAIT\n"
9508 "\tFNSTSW AX\n"
9509 "\tSAHF\n"
9510 "\tJP loop\n"
9511 "\tFSTP_D [ESP+0]\n"
9512 "\tMOVSD $dst,[ESP+0]\n"
9513 "\tADD ESP,8\n"
9514 "\tFSTP ST0\t # Restore FPU Stack"
9515 %}
9516 ins_cost(250);
9517 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9518 ins_pipe( pipe_slow );
9519 %}
9520
9521 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9522 predicate (UseSSE<=1);
9523 match(Set dst (SinD src));
9524 ins_cost(1800);
9525 format %{ "DSIN $dst" %}
9526 opcode(0xD9, 0xFE);
9527 ins_encode( OpcP, OpcS );
9528 ins_pipe( pipe_slow );
9529 %}
9530
9531 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9532 predicate (UseSSE>=2);
9533 match(Set dst (SinD dst));
9534 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9535 ins_cost(1800);
9536 format %{ "DSIN $dst" %}
9537 opcode(0xD9, 0xFE);
9538 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9539 ins_pipe( pipe_slow );
9540 %}
9541
9542 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9543 predicate (UseSSE<=1);
9544 match(Set dst (CosD src));
9545 ins_cost(1800);
9546 format %{ "DCOS $dst" %}
9547 opcode(0xD9, 0xFF);
9548 ins_encode( OpcP, OpcS );
9549 ins_pipe( pipe_slow );
9550 %}
9551
9552 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9553 predicate (UseSSE>=2);
9554 match(Set dst (CosD dst));
9555 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9556 ins_cost(1800);
9557 format %{ "DCOS $dst" %}
9558 opcode(0xD9, 0xFF);
9559 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9560 ins_pipe( pipe_slow );
9561 %}
9562
9563 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9564 predicate (UseSSE<=1);
9565 match(Set dst(TanD src));
9566 format %{ "DTAN $dst" %}
9567 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9568 Opcode(0xDD), Opcode(0xD8)); // fstp st
9569 ins_pipe( pipe_slow );
9570 %}
9571
9572 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9573 predicate (UseSSE>=2);
9574 match(Set dst(TanD dst));
9575 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9576 format %{ "DTAN $dst" %}
9577 ins_encode( Push_SrcD(dst),
9578 Opcode(0xD9), Opcode(0xF2), // fptan
9579 Opcode(0xDD), Opcode(0xD8), // fstp st
9580 Push_ResultD(dst) );
9581 ins_pipe( pipe_slow );
9582 %}
9583
9584 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9585 predicate (UseSSE<=1);
9586 match(Set dst(AtanD dst src));
9587 format %{ "DATA $dst,$src" %}
9588 opcode(0xD9, 0xF3);
9589 ins_encode( Push_Reg_DPR(src),
9590 OpcP, OpcS, RegOpc(dst) );
9591 ins_pipe( pipe_slow );
9592 %}
9593
9594 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9595 predicate (UseSSE>=2);
9596 match(Set dst(AtanD dst src));
9597 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9598 format %{ "DATA $dst,$src" %}
9599 opcode(0xD9, 0xF3);
9600 ins_encode( Push_SrcD(src),
9601 OpcP, OpcS, Push_ResultD(dst) );
9602 ins_pipe( pipe_slow );
9603 %}
9604
9605 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9606 predicate (UseSSE<=1);
9607 match(Set dst (SqrtD src));
9608 format %{ "DSQRT $dst,$src" %}
9609 opcode(0xFA, 0xD9);
9610 ins_encode( Push_Reg_DPR(src),
9611 OpcS, OpcP, Pop_Reg_DPR(dst) );
9612 ins_pipe( pipe_slow );
9613 %}
9614
9615 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9616 predicate (UseSSE<=1);
9617 match(Set Y (PowD X Y)); // Raise X to the Yth power
9618 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9619 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
9620 ins_encode %{
9621 __ subptr(rsp, 8);
9622 __ fld_s($X$$reg - 1);
9623 __ fast_pow();
9624 __ addptr(rsp, 8);
9625 %}
9626 ins_pipe( pipe_slow );
9627 %}
9628
9629 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9630 predicate (UseSSE>=2);
9631 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9632 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9633 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9634 ins_encode %{
9635 __ subptr(rsp, 8);
9636 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9637 __ fld_d(Address(rsp, 0));
9638 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9639 __ fld_d(Address(rsp, 0));
9640 __ fast_pow();
9641 __ fstp_d(Address(rsp, 0));
9642 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9643 __ addptr(rsp, 8);
9644 %}
9645 ins_pipe( pipe_slow );
9646 %}
9647
9648
9649 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9650 predicate (UseSSE<=1);
9651 match(Set dpr1 (ExpD dpr1));
9652 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9653 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
9654 ins_encode %{
9655 __ fast_exp();
9656 %}
9657 ins_pipe( pipe_slow );
9658 %}
9659
9660 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9661 predicate (UseSSE>=2);
9662 match(Set dst (ExpD src));
9663 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9664 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9665 ins_encode %{
9666 __ subptr(rsp, 8);
9667 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9668 __ fld_d(Address(rsp, 0));
9669 __ fast_exp();
9670 __ fstp_d(Address(rsp, 0));
9671 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9672 __ addptr(rsp, 8);
9673 %}
9674 ins_pipe( pipe_slow );
9675 %}
9676
9677 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
9678 predicate (UseSSE<=1);
9679 // The source Double operand on FPU stack
9680 match(Set dst (Log10D src));
9681 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9682 // fxch ; swap ST(0) with ST(1)
9683 // fyl2x ; compute log_10(2) * log_2(x)
9684 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9685 "FXCH \n\t"
9686 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9687 %}
9688 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9689 Opcode(0xD9), Opcode(0xC9), // fxch
9690 Opcode(0xD9), Opcode(0xF1)); // fyl2x
9691
9692 ins_pipe( pipe_slow );
9693 %}
9694
9695 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
9696 predicate (UseSSE>=2);
9697 effect(KILL cr);
9698 match(Set dst (Log10D src));
9699 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9700 // fyl2x ; compute log_10(2) * log_2(x)
9701 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9702 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9703 %}
9704 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9705 Push_SrcD(src),
9706 Opcode(0xD9), Opcode(0xF1), // fyl2x
9707 Push_ResultD(dst));
9708
9709 ins_pipe( pipe_slow );
9710 %}
9711
9712 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
9713 predicate (UseSSE<=1);
9714 // The source Double operand on FPU stack
9715 match(Set dst (LogD src));
9716 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9717 // fxch ; swap ST(0) with ST(1)
9718 // fyl2x ; compute log_e(2) * log_2(x)
9719 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
9720 "FXCH \n\t"
9721 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
9722 %}
9723 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9724 Opcode(0xD9), Opcode(0xC9), // fxch
9725 Opcode(0xD9), Opcode(0xF1)); // fyl2x
9726
9727 ins_pipe( pipe_slow );
9728 %}
9729
9730 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
9731 predicate (UseSSE>=2);
9732 effect(KILL cr);
9733 // The source and result Double operands in XMM registers
9734 match(Set dst (LogD src));
9735 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9736 // fyl2x ; compute log_e(2) * log_2(x)
9737 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
9738 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
9739 %}
9740 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9741 Push_SrcD(src),
9742 Opcode(0xD9), Opcode(0xF1), // fyl2x
9743 Push_ResultD(dst));
9744 ins_pipe( pipe_slow );
9745 %}
9746
9747 //-------------Float Instructions-------------------------------
9748 // Float Math
9749
9750 // Code for float compare:
9751 // fcompp();
9752 // fwait(); fnstsw_ax();
9753 // sahf();
9754 // movl(dst, unordered_result);
9755 // jcc(Assembler::parity, exit);
9756 // movl(dst, less_result);
9757 // jcc(Assembler::below, exit);
9758 // movl(dst, equal_result);
9759 // jcc(Assembler::equal, exit);
9760 // movl(dst, greater_result);
9761 // exit:
9762
9763 // P6 version of float compare, sets condition codes in EFLAGS
9764 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
9765 predicate(VM_Version::supports_cmov() && UseSSE == 0);
9766 match(Set cr (CmpF src1 src2));
9767 effect(KILL rax);
9768 ins_cost(150);
9769 format %{ "FLD $src1\n\t"
9770 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9771 "JNP exit\n\t"
9772 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
9773 "SAHF\n"
9774 "exit:\tNOP // avoid branch to branch" %}
9775 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9776 ins_encode( Push_Reg_DPR(src1),
9777 OpcP, RegOpc(src2),
9778 cmpF_P6_fixup );
9779 ins_pipe( pipe_slow );
9780 %}
9781
9782 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
9783 predicate(VM_Version::supports_cmov() && UseSSE == 0);
9784 match(Set cr (CmpF src1 src2));
9785 ins_cost(100);
9786 format %{ "FLD $src1\n\t"
9787 "FUCOMIP ST,$src2 // P6 instruction" %}
9788 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9789 ins_encode( Push_Reg_DPR(src1),
9790 OpcP, RegOpc(src2));
9791 ins_pipe( pipe_slow );
9792 %}
9793
9794
9795 // Compare & branch
9796 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
9797 predicate(UseSSE == 0);
9798 match(Set cr (CmpF src1 src2));
9799 effect(KILL rax);
9800 ins_cost(200);
9801 format %{ "FLD $src1\n\t"
9802 "FCOMp $src2\n\t"
9803 "FNSTSW AX\n\t"
9804 "TEST AX,0x400\n\t"
9805 "JZ,s flags\n\t"
9806 "MOV AH,1\t# unordered treat as LT\n"
9807 "flags:\tSAHF" %}
9808 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9809 ins_encode( Push_Reg_DPR(src1),
9810 OpcP, RegOpc(src2),
9811 fpu_flags);
9812 ins_pipe( pipe_slow );
9813 %}
9814
9815 // Compare vs zero into -1,0,1
9816 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9817 predicate(UseSSE == 0);
9818 match(Set dst (CmpF3 src1 zero));
9819 effect(KILL cr, KILL rax);
9820 ins_cost(280);
9821 format %{ "FTSTF $dst,$src1" %}
9822 opcode(0xE4, 0xD9);
9823 ins_encode( Push_Reg_DPR(src1),
9824 OpcS, OpcP, PopFPU,
9825 CmpF_Result(dst));
9826 ins_pipe( pipe_slow );
9827 %}
9828
9829 // Compare into -1,0,1
9830 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
9831 predicate(UseSSE == 0);
9832 match(Set dst (CmpF3 src1 src2));
9833 effect(KILL cr, KILL rax);
9834 ins_cost(300);
9835 format %{ "FCMPF $dst,$src1,$src2" %}
9836 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9837 ins_encode( Push_Reg_DPR(src1),
9838 OpcP, RegOpc(src2),
9839 CmpF_Result(dst));
9840 ins_pipe( pipe_slow );
9841 %}
9842
9843 // float compare and set condition codes in EFLAGS by XMM regs
9844 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
9845 predicate(UseSSE>=1);
9846 match(Set cr (CmpF src1 src2));
9847 ins_cost(145);
9848 format %{ "UCOMISS $src1,$src2\n\t"
9849 "JNP,s exit\n\t"
9850 "PUSHF\t# saw NaN, set CF\n\t"
9851 "AND [rsp], #0xffffff2b\n\t"
9852 "POPF\n"
9853 "exit:" %}
9854 ins_encode %{
9855 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9856 emit_cmpfp_fixup(_masm);
9857 %}
9858 ins_pipe( pipe_slow );
9859 %}
9860
9861 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
9862 predicate(UseSSE>=1);
9863 match(Set cr (CmpF src1 src2));
9864 ins_cost(100);
9865 format %{ "UCOMISS $src1,$src2" %}
9866 ins_encode %{
9867 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9868 %}
9869 ins_pipe( pipe_slow );
9870 %}
9871
9872 // float compare and set condition codes in EFLAGS by XMM regs
9873 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
9874 predicate(UseSSE>=1);
9875 match(Set cr (CmpF src1 (LoadF src2)));
9876 ins_cost(165);
9877 format %{ "UCOMISS $src1,$src2\n\t"
9878 "JNP,s exit\n\t"
9879 "PUSHF\t# saw NaN, set CF\n\t"
9880 "AND [rsp], #0xffffff2b\n\t"
9881 "POPF\n"
9882 "exit:" %}
9883 ins_encode %{
9884 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9885 emit_cmpfp_fixup(_masm);
9886 %}
9887 ins_pipe( pipe_slow );
9888 %}
9889
9890 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
9891 predicate(UseSSE>=1);
9892 match(Set cr (CmpF src1 (LoadF src2)));
9893 ins_cost(100);
9894 format %{ "UCOMISS $src1,$src2" %}
9895 ins_encode %{
9896 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9897 %}
9898 ins_pipe( pipe_slow );
9899 %}
9900
9901 // Compare into -1,0,1 in XMM
9902 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
9903 predicate(UseSSE>=1);
9904 match(Set dst (CmpF3 src1 src2));
9905 effect(KILL cr);
9906 ins_cost(255);
9907 format %{ "UCOMISS $src1, $src2\n\t"
9908 "MOV $dst, #-1\n\t"
9909 "JP,s done\n\t"
9910 "JB,s done\n\t"
9911 "SETNE $dst\n\t"
9912 "MOVZB $dst, $dst\n"
9913 "done:" %}
9914 ins_encode %{
9915 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9916 emit_cmpfp3(_masm, $dst$$Register);
9917 %}
9918 ins_pipe( pipe_slow );
9919 %}
9920
9921 // Compare into -1,0,1 in XMM and memory
9922 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
9923 predicate(UseSSE>=1);
9924 match(Set dst (CmpF3 src1 (LoadF src2)));
9925 effect(KILL cr);
9926 ins_cost(275);
9927 format %{ "UCOMISS $src1, $src2\n\t"
9928 "MOV $dst, #-1\n\t"
9929 "JP,s done\n\t"
9930 "JB,s done\n\t"
9931 "SETNE $dst\n\t"
9932 "MOVZB $dst, $dst\n"
9933 "done:" %}
9934 ins_encode %{
9935 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9936 emit_cmpfp3(_masm, $dst$$Register);
9937 %}
9938 ins_pipe( pipe_slow );
9939 %}
9940
9941 // Spill to obtain 24-bit precision
9942 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
9943 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
9944 match(Set dst (SubF src1 src2));
9945
9946 format %{ "FSUB $dst,$src1 - $src2" %}
9947 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
9948 ins_encode( Push_Reg_FPR(src1),
9949 OpcReg_FPR(src2),
9950 Pop_Mem_FPR(dst) );
9951 ins_pipe( fpu_mem_reg_reg );
9952 %}
9953 //
9954 // This instruction does not round to 24-bits
9955 instruct subFPR_reg(regFPR dst, regFPR src) %{
9956 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
9957 match(Set dst (SubF dst src));
9958
9959 format %{ "FSUB $dst,$src" %}
9960 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9961 ins_encode( Push_Reg_FPR(src),
9962 OpcP, RegOpc(dst) );
9963 ins_pipe( fpu_reg_reg );
9964 %}
9965
9966 // Spill to obtain 24-bit precision
9967 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
9968 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
9969 match(Set dst (AddF src1 src2));
9970
9971 format %{ "FADD $dst,$src1,$src2" %}
9972 opcode(0xD8, 0x0); /* D8 C0+i */
9973 ins_encode( Push_Reg_FPR(src2),
9974 OpcReg_FPR(src1),
9975 Pop_Mem_FPR(dst) );
9976 ins_pipe( fpu_mem_reg_reg );
9977 %}
9978 //
9979 // This instruction does not round to 24-bits
9980 instruct addFPR_reg(regFPR dst, regFPR src) %{
9981 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
9982 match(Set dst (AddF dst src));
9983
9984 format %{ "FLD $src\n\t"
9985 "FADDp $dst,ST" %}
9986 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9987 ins_encode( Push_Reg_FPR(src),
9988 OpcP, RegOpc(dst) );
9989 ins_pipe( fpu_reg_reg );
9990 %}
9991
9992 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
9993 predicate(UseSSE==0);
9994 match(Set dst (AbsF src));
9995 ins_cost(100);
9996 format %{ "FABS" %}
9997 opcode(0xE1, 0xD9);
9998 ins_encode( OpcS, OpcP );
9999 ins_pipe( fpu_reg_reg );
10000 %}
10001
10002 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10003 predicate(UseSSE==0);
10004 match(Set dst (NegF src));
10005 ins_cost(100);
10006 format %{ "FCHS" %}
10007 opcode(0xE0, 0xD9);
10008 ins_encode( OpcS, OpcP );
10009 ins_pipe( fpu_reg_reg );
10010 %}
10011
10012 // Cisc-alternate to addFPR_reg
10013 // Spill to obtain 24-bit precision
10014 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10015 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10016 match(Set dst (AddF src1 (LoadF src2)));
10017
10018 format %{ "FLD $src2\n\t"
10019 "FADD ST,$src1\n\t"
10020 "FSTP_S $dst" %}
10021 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10022 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10023 OpcReg_FPR(src1),
10024 Pop_Mem_FPR(dst) );
10025 ins_pipe( fpu_mem_reg_mem );
10026 %}
10027 //
10028 // Cisc-alternate to addFPR_reg
10029 // This instruction does not round to 24-bits
10030 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10031 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10032 match(Set dst (AddF dst (LoadF src)));
10033
10034 format %{ "FADD $dst,$src" %}
10035 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10036 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10037 OpcP, RegOpc(dst) );
10038 ins_pipe( fpu_reg_mem );
10039 %}
10040
10041 // // Following two instructions for _222_mpegaudio
10042 // Spill to obtain 24-bit precision
10043 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10044 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10045 match(Set dst (AddF src1 src2));
10046
10047 format %{ "FADD $dst,$src1,$src2" %}
10048 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10049 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10050 OpcReg_FPR(src2),
10051 Pop_Mem_FPR(dst) );
10052 ins_pipe( fpu_mem_reg_mem );
10053 %}
10054
10055 // Cisc-spill variant
10056 // Spill to obtain 24-bit precision
10057 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10058 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10059 match(Set dst (AddF src1 (LoadF src2)));
10060
10061 format %{ "FADD $dst,$src1,$src2 cisc" %}
10062 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10063 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10064 set_instruction_start,
10065 OpcP, RMopc_Mem(secondary,src1),
10066 Pop_Mem_FPR(dst) );
10067 ins_pipe( fpu_mem_mem_mem );
10068 %}
10069
10070 // Spill to obtain 24-bit precision
10071 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10072 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10073 match(Set dst (AddF src1 src2));
10074
10075 format %{ "FADD $dst,$src1,$src2" %}
10076 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10077 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10078 set_instruction_start,
10079 OpcP, RMopc_Mem(secondary,src1),
10080 Pop_Mem_FPR(dst) );
10081 ins_pipe( fpu_mem_mem_mem );
10082 %}
10083
10084
10085 // Spill to obtain 24-bit precision
10086 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10087 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10088 match(Set dst (AddF src con));
10089 format %{ "FLD $src\n\t"
10090 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10091 "FSTP_S $dst" %}
10092 ins_encode %{
10093 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10094 __ fadd_s($constantaddress($con));
10095 __ fstp_s(Address(rsp, $dst$$disp));
10096 %}
10097 ins_pipe(fpu_mem_reg_con);
10098 %}
10099 //
10100 // This instruction does not round to 24-bits
10101 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10102 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10103 match(Set dst (AddF src con));
10104 format %{ "FLD $src\n\t"
10105 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10106 "FSTP $dst" %}
10107 ins_encode %{
10108 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10109 __ fadd_s($constantaddress($con));
10110 __ fstp_d($dst$$reg);
10111 %}
10112 ins_pipe(fpu_reg_reg_con);
10113 %}
10114
10115 // Spill to obtain 24-bit precision
10116 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10117 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10118 match(Set dst (MulF src1 src2));
10119
10120 format %{ "FLD $src1\n\t"
10121 "FMUL $src2\n\t"
10122 "FSTP_S $dst" %}
10123 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10124 ins_encode( Push_Reg_FPR(src1),
10125 OpcReg_FPR(src2),
10126 Pop_Mem_FPR(dst) );
10127 ins_pipe( fpu_mem_reg_reg );
10128 %}
10129 //
10130 // This instruction does not round to 24-bits
10131 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10132 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10133 match(Set dst (MulF src1 src2));
10134
10135 format %{ "FLD $src1\n\t"
10136 "FMUL $src2\n\t"
10137 "FSTP_S $dst" %}
10138 opcode(0xD8, 0x1); /* D8 C8+i */
10139 ins_encode( Push_Reg_FPR(src2),
10140 OpcReg_FPR(src1),
10141 Pop_Reg_FPR(dst) );
10142 ins_pipe( fpu_reg_reg_reg );
10143 %}
10144
10145
10146 // Spill to obtain 24-bit precision
10147 // Cisc-alternate to reg-reg multiply
10148 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10149 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10150 match(Set dst (MulF src1 (LoadF src2)));
10151
10152 format %{ "FLD_S $src2\n\t"
10153 "FMUL $src1\n\t"
10154 "FSTP_S $dst" %}
10155 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10156 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10157 OpcReg_FPR(src1),
10158 Pop_Mem_FPR(dst) );
10159 ins_pipe( fpu_mem_reg_mem );
10160 %}
10161 //
10162 // This instruction does not round to 24-bits
10163 // Cisc-alternate to reg-reg multiply
10164 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10165 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10166 match(Set dst (MulF src1 (LoadF src2)));
10167
10168 format %{ "FMUL $dst,$src1,$src2" %}
10169 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10170 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10171 OpcReg_FPR(src1),
10172 Pop_Reg_FPR(dst) );
10173 ins_pipe( fpu_reg_reg_mem );
10174 %}
10175
10176 // Spill to obtain 24-bit precision
10177 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10178 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10179 match(Set dst (MulF src1 src2));
10180
10181 format %{ "FMUL $dst,$src1,$src2" %}
10182 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10183 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10184 set_instruction_start,
10185 OpcP, RMopc_Mem(secondary,src1),
10186 Pop_Mem_FPR(dst) );
10187 ins_pipe( fpu_mem_mem_mem );
10188 %}
10189
10190 // Spill to obtain 24-bit precision
10191 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10192 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10193 match(Set dst (MulF src con));
10194
10195 format %{ "FLD $src\n\t"
10196 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10197 "FSTP_S $dst" %}
10198 ins_encode %{
10199 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10200 __ fmul_s($constantaddress($con));
10201 __ fstp_s(Address(rsp, $dst$$disp));
10202 %}
10203 ins_pipe(fpu_mem_reg_con);
10204 %}
10205 //
10206 // This instruction does not round to 24-bits
10207 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10208 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10209 match(Set dst (MulF src con));
10210
10211 format %{ "FLD $src\n\t"
10212 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10213 "FSTP $dst" %}
10214 ins_encode %{
10215 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10216 __ fmul_s($constantaddress($con));
10217 __ fstp_d($dst$$reg);
10218 %}
10219 ins_pipe(fpu_reg_reg_con);
10220 %}
10221
10222
10223 //
10224 // MACRO1 -- subsume unshared load into mulFPR
10225 // This instruction does not round to 24-bits
10226 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10227 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10228 match(Set dst (MulF (LoadF mem1) src));
10229
10230 format %{ "FLD $mem1 ===MACRO1===\n\t"
10231 "FMUL ST,$src\n\t"
10232 "FSTP $dst" %}
10233 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10234 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10235 OpcReg_FPR(src),
10236 Pop_Reg_FPR(dst) );
10237 ins_pipe( fpu_reg_reg_mem );
10238 %}
10239 //
10240 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10241 // This instruction does not round to 24-bits
10242 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10243 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10244 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10245 ins_cost(95);
10246
10247 format %{ "FLD $mem1 ===MACRO2===\n\t"
10248 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10249 "FADD ST,$src2\n\t"
10250 "FSTP $dst" %}
10251 opcode(0xD9); /* LoadF D9 /0 */
10252 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10253 FMul_ST_reg(src1),
10254 FAdd_ST_reg(src2),
10255 Pop_Reg_FPR(dst) );
10256 ins_pipe( fpu_reg_mem_reg_reg );
10257 %}
10258
10259 // MACRO3 -- addFPR a mulFPR
10260 // This instruction does not round to 24-bits. It is a '2-address'
10261 // instruction in that the result goes back to src2. This eliminates
10262 // a move from the macro; possibly the register allocator will have
10263 // to add it back (and maybe not).
10264 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10265 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10266 match(Set src2 (AddF (MulF src0 src1) src2));
10267
10268 format %{ "FLD $src0 ===MACRO3===\n\t"
10269 "FMUL ST,$src1\n\t"
10270 "FADDP $src2,ST" %}
10271 opcode(0xD9); /* LoadF D9 /0 */
10272 ins_encode( Push_Reg_FPR(src0),
10273 FMul_ST_reg(src1),
10274 FAddP_reg_ST(src2) );
10275 ins_pipe( fpu_reg_reg_reg );
10276 %}
10277
10278 // MACRO4 -- divFPR subFPR
10279 // This instruction does not round to 24-bits
10280 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10281 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10282 match(Set dst (DivF (SubF src2 src1) src3));
10283
10284 format %{ "FLD $src2 ===MACRO4===\n\t"
10285 "FSUB ST,$src1\n\t"
10286 "FDIV ST,$src3\n\t"
10287 "FSTP $dst" %}
10288 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10289 ins_encode( Push_Reg_FPR(src2),
10290 subFPR_divFPR_encode(src1,src3),
10291 Pop_Reg_FPR(dst) );
10292 ins_pipe( fpu_reg_reg_reg_reg );
10293 %}
10294
10295 // Spill to obtain 24-bit precision
10296 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10297 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10298 match(Set dst (DivF src1 src2));
10299
10300 format %{ "FDIV $dst,$src1,$src2" %}
10301 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10302 ins_encode( Push_Reg_FPR(src1),
10303 OpcReg_FPR(src2),
10304 Pop_Mem_FPR(dst) );
10305 ins_pipe( fpu_mem_reg_reg );
10306 %}
10307 //
10308 // This instruction does not round to 24-bits
10309 instruct divFPR_reg(regFPR dst, regFPR src) %{
10310 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10311 match(Set dst (DivF dst src));
10312
10313 format %{ "FDIV $dst,$src" %}
10314 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10315 ins_encode( Push_Reg_FPR(src),
10316 OpcP, RegOpc(dst) );
10317 ins_pipe( fpu_reg_reg );
10318 %}
10319
10320
10321 // Spill to obtain 24-bit precision
10322 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10323 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10324 match(Set dst (ModF src1 src2));
10325 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10326
10327 format %{ "FMOD $dst,$src1,$src2" %}
10328 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10329 emitModDPR(),
10330 Push_Result_Mod_DPR(src2),
10331 Pop_Mem_FPR(dst));
10332 ins_pipe( pipe_slow );
10333 %}
10334 //
10335 // This instruction does not round to 24-bits
10336 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10337 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10338 match(Set dst (ModF dst src));
10339 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10340
10341 format %{ "FMOD $dst,$src" %}
10342 ins_encode(Push_Reg_Mod_DPR(dst, src),
10343 emitModDPR(),
10344 Push_Result_Mod_DPR(src),
10345 Pop_Reg_FPR(dst));
10346 ins_pipe( pipe_slow );
10347 %}
10348
10349 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10350 predicate(UseSSE>=1);
10351 match(Set dst (ModF src0 src1));
10352 effect(KILL rax, KILL cr);
10353 format %{ "SUB ESP,4\t # FMOD\n"
10354 "\tMOVSS [ESP+0],$src1\n"
10355 "\tFLD_S [ESP+0]\n"
10356 "\tMOVSS [ESP+0],$src0\n"
10357 "\tFLD_S [ESP+0]\n"
10358 "loop:\tFPREM\n"
10359 "\tFWAIT\n"
10360 "\tFNSTSW AX\n"
10361 "\tSAHF\n"
10362 "\tJP loop\n"
10363 "\tFSTP_S [ESP+0]\n"
10364 "\tMOVSS $dst,[ESP+0]\n"
10365 "\tADD ESP,4\n"
10366 "\tFSTP ST0\t # Restore FPU Stack"
10367 %}
10368 ins_cost(250);
10369 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10370 ins_pipe( pipe_slow );
10371 %}
10372
10373
10374 //----------Arithmetic Conversion Instructions---------------------------------
10375 // The conversions operations are all Alpha sorted. Please keep it that way!
10376
10377 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10378 predicate(UseSSE==0);
10379 match(Set dst (RoundFloat src));
10380 ins_cost(125);
10381 format %{ "FST_S $dst,$src\t# F-round" %}
10382 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10383 ins_pipe( fpu_mem_reg );
10384 %}
10385
10386 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10387 predicate(UseSSE<=1);
10388 match(Set dst (RoundDouble src));
10389 ins_cost(125);
10390 format %{ "FST_D $dst,$src\t# D-round" %}
10391 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10392 ins_pipe( fpu_mem_reg );
10393 %}
10394
10395 // Force rounding to 24-bit precision and 6-bit exponent
10396 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10397 predicate(UseSSE==0);
10398 match(Set dst (ConvD2F src));
10399 format %{ "FST_S $dst,$src\t# F-round" %}
10400 expand %{
10401 roundFloat_mem_reg(dst,src);
10402 %}
10403 %}
10404
10405 // Force rounding to 24-bit precision and 6-bit exponent
10406 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10407 predicate(UseSSE==1);
10408 match(Set dst (ConvD2F src));
10409 effect( KILL cr );
10410 format %{ "SUB ESP,4\n\t"
10411 "FST_S [ESP],$src\t# F-round\n\t"
10412 "MOVSS $dst,[ESP]\n\t"
10413 "ADD ESP,4" %}
10414 ins_encode %{
10415 __ subptr(rsp, 4);
10416 if ($src$$reg != FPR1L_enc) {
10417 __ fld_s($src$$reg-1);
10418 __ fstp_s(Address(rsp, 0));
10419 } else {
10420 __ fst_s(Address(rsp, 0));
10421 }
10422 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10423 __ addptr(rsp, 4);
10424 %}
10425 ins_pipe( pipe_slow );
10426 %}
10427
10428 // Force rounding double precision to single precision
10429 instruct convD2F_reg(regF dst, regD src) %{
10430 predicate(UseSSE>=2);
10431 match(Set dst (ConvD2F src));
10432 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10433 ins_encode %{
10434 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10435 %}
10436 ins_pipe( pipe_slow );
10437 %}
10438
10439 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10440 predicate(UseSSE==0);
10441 match(Set dst (ConvF2D src));
10442 format %{ "FST_S $dst,$src\t# D-round" %}
10443 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10444 ins_pipe( fpu_reg_reg );
10445 %}
10446
10447 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10448 predicate(UseSSE==1);
10449 match(Set dst (ConvF2D src));
10450 format %{ "FST_D $dst,$src\t# D-round" %}
10451 expand %{
10452 roundDouble_mem_reg(dst,src);
10453 %}
10454 %}
10455
10456 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10457 predicate(UseSSE==1);
10458 match(Set dst (ConvF2D src));
10459 effect( KILL cr );
10460 format %{ "SUB ESP,4\n\t"
10461 "MOVSS [ESP] $src\n\t"
10462 "FLD_S [ESP]\n\t"
10463 "ADD ESP,4\n\t"
10464 "FSTP $dst\t# D-round" %}
10465 ins_encode %{
10466 __ subptr(rsp, 4);
10467 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10468 __ fld_s(Address(rsp, 0));
10469 __ addptr(rsp, 4);
10470 __ fstp_d($dst$$reg);
10471 %}
10472 ins_pipe( pipe_slow );
10473 %}
10474
10475 instruct convF2D_reg(regD dst, regF src) %{
10476 predicate(UseSSE>=2);
10477 match(Set dst (ConvF2D src));
10478 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10479 ins_encode %{
10480 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10481 %}
10482 ins_pipe( pipe_slow );
10483 %}
10484
10485 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10486 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10487 predicate(UseSSE<=1);
10488 match(Set dst (ConvD2I src));
10489 effect( KILL tmp, KILL cr );
10490 format %{ "FLD $src\t# Convert double to int \n\t"
10491 "FLDCW trunc mode\n\t"
10492 "SUB ESP,4\n\t"
10493 "FISTp [ESP + #0]\n\t"
10494 "FLDCW std/24-bit mode\n\t"
10495 "POP EAX\n\t"
10496 "CMP EAX,0x80000000\n\t"
10497 "JNE,s fast\n\t"
10498 "FLD_D $src\n\t"
10499 "CALL d2i_wrapper\n"
10500 "fast:" %}
10501 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10502 ins_pipe( pipe_slow );
10503 %}
10504
10505 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10506 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10507 predicate(UseSSE>=2);
10508 match(Set dst (ConvD2I src));
10509 effect( KILL tmp, KILL cr );
10510 format %{ "CVTTSD2SI $dst, $src\n\t"
10511 "CMP $dst,0x80000000\n\t"
10512 "JNE,s fast\n\t"
10513 "SUB ESP, 8\n\t"
10514 "MOVSD [ESP], $src\n\t"
10515 "FLD_D [ESP]\n\t"
10516 "ADD ESP, 8\n\t"
10517 "CALL d2i_wrapper\n"
10518 "fast:" %}
10519 ins_encode %{
10520 Label fast;
10521 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10522 __ cmpl($dst$$Register, 0x80000000);
10523 __ jccb(Assembler::notEqual, fast);
10524 __ subptr(rsp, 8);
10525 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10526 __ fld_d(Address(rsp, 0));
10527 __ addptr(rsp, 8);
10528 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10529 __ bind(fast);
10530 %}
10531 ins_pipe( pipe_slow );
10532 %}
10533
10534 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10535 predicate(UseSSE<=1);
10536 match(Set dst (ConvD2L src));
10537 effect( KILL cr );
10538 format %{ "FLD $src\t# Convert double to long\n\t"
10539 "FLDCW trunc mode\n\t"
10540 "SUB ESP,8\n\t"
10541 "FISTp [ESP + #0]\n\t"
10542 "FLDCW std/24-bit mode\n\t"
10543 "POP EAX\n\t"
10544 "POP EDX\n\t"
10545 "CMP EDX,0x80000000\n\t"
10546 "JNE,s fast\n\t"
10547 "TEST EAX,EAX\n\t"
10548 "JNE,s fast\n\t"
10549 "FLD $src\n\t"
10550 "CALL d2l_wrapper\n"
10551 "fast:" %}
10552 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
10553 ins_pipe( pipe_slow );
10554 %}
10555
10556 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10557 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10558 predicate (UseSSE>=2);
10559 match(Set dst (ConvD2L src));
10560 effect( KILL cr );
10561 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10562 "MOVSD [ESP],$src\n\t"
10563 "FLD_D [ESP]\n\t"
10564 "FLDCW trunc mode\n\t"
10565 "FISTp [ESP + #0]\n\t"
10566 "FLDCW std/24-bit mode\n\t"
10567 "POP EAX\n\t"
10568 "POP EDX\n\t"
10569 "CMP EDX,0x80000000\n\t"
10570 "JNE,s fast\n\t"
10571 "TEST EAX,EAX\n\t"
10572 "JNE,s fast\n\t"
10573 "SUB ESP,8\n\t"
10574 "MOVSD [ESP],$src\n\t"
10575 "FLD_D [ESP]\n\t"
10576 "ADD ESP,8\n\t"
10577 "CALL d2l_wrapper\n"
10578 "fast:" %}
10579 ins_encode %{
10580 Label fast;
10581 __ subptr(rsp, 8);
10582 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10583 __ fld_d(Address(rsp, 0));
10584 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10585 __ fistp_d(Address(rsp, 0));
10586 // Restore the rounding mode, mask the exception
10587 if (Compile::current()->in_24_bit_fp_mode()) {
10588 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10589 } else {
10590 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10591 }
10592 // Load the converted long, adjust CPU stack
10593 __ pop(rax);
10594 __ pop(rdx);
10595 __ cmpl(rdx, 0x80000000);
10596 __ jccb(Assembler::notEqual, fast);
10597 __ testl(rax, rax);
10598 __ jccb(Assembler::notEqual, fast);
10599 __ subptr(rsp, 8);
10600 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10601 __ fld_d(Address(rsp, 0));
10602 __ addptr(rsp, 8);
10603 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10604 __ bind(fast);
10605 %}
10606 ins_pipe( pipe_slow );
10607 %}
10608
10609 // Convert a double to an int. Java semantics require we do complex
10610 // manglations in the corner cases. So we set the rounding mode to
10611 // 'zero', store the darned double down as an int, and reset the
10612 // rounding mode to 'nearest'. The hardware stores a flag value down
10613 // if we would overflow or converted a NAN; we check for this and
10614 // and go the slow path if needed.
10615 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
10616 predicate(UseSSE==0);
10617 match(Set dst (ConvF2I src));
10618 effect( KILL tmp, KILL cr );
10619 format %{ "FLD $src\t# Convert float to int \n\t"
10620 "FLDCW trunc mode\n\t"
10621 "SUB ESP,4\n\t"
10622 "FISTp [ESP + #0]\n\t"
10623 "FLDCW std/24-bit mode\n\t"
10624 "POP EAX\n\t"
10625 "CMP EAX,0x80000000\n\t"
10626 "JNE,s fast\n\t"
10627 "FLD $src\n\t"
10628 "CALL d2i_wrapper\n"
10629 "fast:" %}
10630 // DPR2I_encoding works for FPR2I
10631 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
10632 ins_pipe( pipe_slow );
10633 %}
10634
10635 // Convert a float in xmm to an int reg.
10636 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
10637 predicate(UseSSE>=1);
10638 match(Set dst (ConvF2I src));
10639 effect( KILL tmp, KILL cr );
10640 format %{ "CVTTSS2SI $dst, $src\n\t"
10641 "CMP $dst,0x80000000\n\t"
10642 "JNE,s fast\n\t"
10643 "SUB ESP, 4\n\t"
10644 "MOVSS [ESP], $src\n\t"
10645 "FLD [ESP]\n\t"
10646 "ADD ESP, 4\n\t"
10647 "CALL d2i_wrapper\n"
10648 "fast:" %}
10649 ins_encode %{
10650 Label fast;
10651 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10652 __ cmpl($dst$$Register, 0x80000000);
10653 __ jccb(Assembler::notEqual, fast);
10654 __ subptr(rsp, 4);
10655 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10656 __ fld_s(Address(rsp, 0));
10657 __ addptr(rsp, 4);
10658 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10659 __ bind(fast);
10660 %}
10661 ins_pipe( pipe_slow );
10662 %}
10663
10664 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
10665 predicate(UseSSE==0);
10666 match(Set dst (ConvF2L src));
10667 effect( KILL cr );
10668 format %{ "FLD $src\t# Convert float to long\n\t"
10669 "FLDCW trunc mode\n\t"
10670 "SUB ESP,8\n\t"
10671 "FISTp [ESP + #0]\n\t"
10672 "FLDCW std/24-bit mode\n\t"
10673 "POP EAX\n\t"
10674 "POP EDX\n\t"
10675 "CMP EDX,0x80000000\n\t"
10676 "JNE,s fast\n\t"
10677 "TEST EAX,EAX\n\t"
10678 "JNE,s fast\n\t"
10679 "FLD $src\n\t"
10680 "CALL d2l_wrapper\n"
10681 "fast:" %}
10682 // DPR2L_encoding works for FPR2L
10683 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
10684 ins_pipe( pipe_slow );
10685 %}
10686
10687 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10688 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
10689 predicate (UseSSE>=1);
10690 match(Set dst (ConvF2L src));
10691 effect( KILL cr );
10692 format %{ "SUB ESP,8\t# Convert float to long\n\t"
10693 "MOVSS [ESP],$src\n\t"
10694 "FLD_S [ESP]\n\t"
10695 "FLDCW trunc mode\n\t"
10696 "FISTp [ESP + #0]\n\t"
10697 "FLDCW std/24-bit mode\n\t"
10698 "POP EAX\n\t"
10699 "POP EDX\n\t"
10700 "CMP EDX,0x80000000\n\t"
10701 "JNE,s fast\n\t"
10702 "TEST EAX,EAX\n\t"
10703 "JNE,s fast\n\t"
10704 "SUB ESP,4\t# Convert float to long\n\t"
10705 "MOVSS [ESP],$src\n\t"
10706 "FLD_S [ESP]\n\t"
10707 "ADD ESP,4\n\t"
10708 "CALL d2l_wrapper\n"
10709 "fast:" %}
10710 ins_encode %{
10711 Label fast;
10712 __ subptr(rsp, 8);
10713 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10714 __ fld_s(Address(rsp, 0));
10715 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10716 __ fistp_d(Address(rsp, 0));
10717 // Restore the rounding mode, mask the exception
10718 if (Compile::current()->in_24_bit_fp_mode()) {
10719 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10720 } else {
10721 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10722 }
10723 // Load the converted long, adjust CPU stack
10724 __ pop(rax);
10725 __ pop(rdx);
10726 __ cmpl(rdx, 0x80000000);
10727 __ jccb(Assembler::notEqual, fast);
10728 __ testl(rax, rax);
10729 __ jccb(Assembler::notEqual, fast);
10730 __ subptr(rsp, 4);
10731 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10732 __ fld_s(Address(rsp, 0));
10733 __ addptr(rsp, 4);
10734 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10735 __ bind(fast);
10736 %}
10737 ins_pipe( pipe_slow );
10738 %}
10739
10740 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
10741 predicate( UseSSE<=1 );
10742 match(Set dst (ConvI2D src));
10743 format %{ "FILD $src\n\t"
10744 "FSTP $dst" %}
10745 opcode(0xDB, 0x0); /* DB /0 */
10746 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
10747 ins_pipe( fpu_reg_mem );
10748 %}
10749
10750 instruct convI2D_reg(regD dst, rRegI src) %{
10751 predicate( UseSSE>=2 && !UseXmmI2D );
10752 match(Set dst (ConvI2D src));
10753 format %{ "CVTSI2SD $dst,$src" %}
10754 ins_encode %{
10755 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10756 %}
10757 ins_pipe( pipe_slow );
10758 %}
10759
10760 instruct convI2D_mem(regD dst, memory mem) %{
10761 predicate( UseSSE>=2 );
10762 match(Set dst (ConvI2D (LoadI mem)));
10763 format %{ "CVTSI2SD $dst,$mem" %}
10764 ins_encode %{
10765 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
10766 %}
10767 ins_pipe( pipe_slow );
10768 %}
10769
10770 instruct convXI2D_reg(regD dst, rRegI src)
10771 %{
10772 predicate( UseSSE>=2 && UseXmmI2D );
10773 match(Set dst (ConvI2D src));
10774
10775 format %{ "MOVD $dst,$src\n\t"
10776 "CVTDQ2PD $dst,$dst\t# i2d" %}
10777 ins_encode %{
10778 __ movdl($dst$$XMMRegister, $src$$Register);
10779 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10780 %}
10781 ins_pipe(pipe_slow); // XXX
10782 %}
10783
10784 instruct convI2DPR_mem(regDPR dst, memory mem) %{
10785 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
10786 match(Set dst (ConvI2D (LoadI mem)));
10787 format %{ "FILD $mem\n\t"
10788 "FSTP $dst" %}
10789 opcode(0xDB); /* DB /0 */
10790 ins_encode( OpcP, RMopc_Mem(0x00,mem),
10791 Pop_Reg_DPR(dst));
10792 ins_pipe( fpu_reg_mem );
10793 %}
10794
10795 // Convert a byte to a float; no rounding step needed.
10796 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
10797 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
10798 match(Set dst (ConvI2F src));
10799 format %{ "FILD $src\n\t"
10800 "FSTP $dst" %}
10801
10802 opcode(0xDB, 0x0); /* DB /0 */
10803 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
10804 ins_pipe( fpu_reg_mem );
10805 %}
10806
10807 // In 24-bit mode, force exponent rounding by storing back out
10808 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
10809 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10810 match(Set dst (ConvI2F src));
10811 ins_cost(200);
10812 format %{ "FILD $src\n\t"
10813 "FSTP_S $dst" %}
10814 opcode(0xDB, 0x0); /* DB /0 */
10815 ins_encode( Push_Mem_I(src),
10816 Pop_Mem_FPR(dst));
10817 ins_pipe( fpu_mem_mem );
10818 %}
10819
10820 // In 24-bit mode, force exponent rounding by storing back out
10821 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
10822 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10823 match(Set dst (ConvI2F (LoadI mem)));
10824 ins_cost(200);
10825 format %{ "FILD $mem\n\t"
10826 "FSTP_S $dst" %}
10827 opcode(0xDB); /* DB /0 */
10828 ins_encode( OpcP, RMopc_Mem(0x00,mem),
10829 Pop_Mem_FPR(dst));
10830 ins_pipe( fpu_mem_mem );
10831 %}
10832
10833 // This instruction does not round to 24-bits
10834 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
10835 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10836 match(Set dst (ConvI2F src));
10837 format %{ "FILD $src\n\t"
10838 "FSTP $dst" %}
10839 opcode(0xDB, 0x0); /* DB /0 */
10840 ins_encode( Push_Mem_I(src),
10841 Pop_Reg_FPR(dst));
10842 ins_pipe( fpu_reg_mem );
10843 %}
10844
10845 // This instruction does not round to 24-bits
10846 instruct convI2FPR_mem(regFPR dst, memory mem) %{
10847 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10848 match(Set dst (ConvI2F (LoadI mem)));
10849 format %{ "FILD $mem\n\t"
10850 "FSTP $dst" %}
10851 opcode(0xDB); /* DB /0 */
10852 ins_encode( OpcP, RMopc_Mem(0x00,mem),
10853 Pop_Reg_FPR(dst));
10854 ins_pipe( fpu_reg_mem );
10855 %}
10856
10857 // Convert an int to a float in xmm; no rounding step needed.
10858 instruct convI2F_reg(regF dst, rRegI src) %{
10859 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
10860 match(Set dst (ConvI2F src));
10861 format %{ "CVTSI2SS $dst, $src" %}
10862 ins_encode %{
10863 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10864 %}
10865 ins_pipe( pipe_slow );
10866 %}
10867
10868 instruct convXI2F_reg(regF dst, rRegI src)
10869 %{
10870 predicate( UseSSE>=2 && UseXmmI2F );
10871 match(Set dst (ConvI2F src));
10872
10873 format %{ "MOVD $dst,$src\n\t"
10874 "CVTDQ2PS $dst,$dst\t# i2f" %}
10875 ins_encode %{
10876 __ movdl($dst$$XMMRegister, $src$$Register);
10877 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10878 %}
10879 ins_pipe(pipe_slow); // XXX
10880 %}
10881
10882 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
10883 match(Set dst (ConvI2L src));
10884 effect(KILL cr);
10885 ins_cost(375);
10886 format %{ "MOV $dst.lo,$src\n\t"
10887 "MOV $dst.hi,$src\n\t"
10888 "SAR $dst.hi,31" %}
10889 ins_encode(convert_int_long(dst,src));
10890 ins_pipe( ialu_reg_reg_long );
10891 %}
10892
10893 // Zero-extend convert int to long
10894 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
10895 match(Set dst (AndL (ConvI2L src) mask) );
10896 effect( KILL flags );
10897 ins_cost(250);
10898 format %{ "MOV $dst.lo,$src\n\t"
10899 "XOR $dst.hi,$dst.hi" %}
10900 opcode(0x33); // XOR
10901 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
10902 ins_pipe( ialu_reg_reg_long );
10903 %}
10904
10905 // Zero-extend long
10906 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
10907 match(Set dst (AndL src mask) );
10908 effect( KILL flags );
10909 ins_cost(250);
10910 format %{ "MOV $dst.lo,$src.lo\n\t"
10911 "XOR $dst.hi,$dst.hi\n\t" %}
10912 opcode(0x33); // XOR
10913 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
10914 ins_pipe( ialu_reg_reg_long );
10915 %}
10916
10917 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
10918 predicate (UseSSE<=1);
10919 match(Set dst (ConvL2D src));
10920 effect( KILL cr );
10921 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
10922 "PUSH $src.lo\n\t"
10923 "FILD ST,[ESP + #0]\n\t"
10924 "ADD ESP,8\n\t"
10925 "FSTP_D $dst\t# D-round" %}
10926 opcode(0xDF, 0x5); /* DF /5 */
10927 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
10928 ins_pipe( pipe_slow );
10929 %}
10930
10931 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
10932 predicate (UseSSE>=2);
10933 match(Set dst (ConvL2D src));
10934 effect( KILL cr );
10935 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
10936 "PUSH $src.lo\n\t"
10937 "FILD_D [ESP]\n\t"
10938 "FSTP_D [ESP]\n\t"
10939 "MOVSD $dst,[ESP]\n\t"
10940 "ADD ESP,8" %}
10941 opcode(0xDF, 0x5); /* DF /5 */
10942 ins_encode(convert_long_double2(src), Push_ResultD(dst));
10943 ins_pipe( pipe_slow );
10944 %}
10945
10946 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
10947 predicate (UseSSE>=1);
10948 match(Set dst (ConvL2F src));
10949 effect( KILL cr );
10950 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
10951 "PUSH $src.lo\n\t"
10952 "FILD_D [ESP]\n\t"
10953 "FSTP_S [ESP]\n\t"
10954 "MOVSS $dst,[ESP]\n\t"
10955 "ADD ESP,8" %}
10956 opcode(0xDF, 0x5); /* DF /5 */
10957 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
10958 ins_pipe( pipe_slow );
10959 %}
10960
10961 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
10962 match(Set dst (ConvL2F src));
10963 effect( KILL cr );
10964 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
10965 "PUSH $src.lo\n\t"
10966 "FILD ST,[ESP + #0]\n\t"
10967 "ADD ESP,8\n\t"
10968 "FSTP_S $dst\t# F-round" %}
10969 opcode(0xDF, 0x5); /* DF /5 */
10970 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
10971 ins_pipe( pipe_slow );
10972 %}
10973
10974 instruct convL2I_reg( rRegI dst, eRegL src ) %{
10975 match(Set dst (ConvL2I src));
10976 effect( DEF dst, USE src );
10977 format %{ "MOV $dst,$src.lo" %}
10978 ins_encode(enc_CopyL_Lo(dst,src));
10979 ins_pipe( ialu_reg_reg );
10980 %}
10981
10982
10983 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10984 match(Set dst (MoveF2I src));
10985 effect( DEF dst, USE src );
10986 ins_cost(100);
10987 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
10988 ins_encode %{
10989 __ movl($dst$$Register, Address(rsp, $src$$disp));
10990 %}
10991 ins_pipe( ialu_reg_mem );
10992 %}
10993
10994 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
10995 predicate(UseSSE==0);
10996 match(Set dst (MoveF2I src));
10997 effect( DEF dst, USE src );
10998
10999 ins_cost(125);
11000 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11001 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11002 ins_pipe( fpu_mem_reg );
11003 %}
11004
11005 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11006 predicate(UseSSE>=1);
11007 match(Set dst (MoveF2I src));
11008 effect( DEF dst, USE src );
11009
11010 ins_cost(95);
11011 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11012 ins_encode %{
11013 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11014 %}
11015 ins_pipe( pipe_slow );
11016 %}
11017
11018 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11019 predicate(UseSSE>=2);
11020 match(Set dst (MoveF2I src));
11021 effect( DEF dst, USE src );
11022 ins_cost(85);
11023 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11024 ins_encode %{
11025 __ movdl($dst$$Register, $src$$XMMRegister);
11026 %}
11027 ins_pipe( pipe_slow );
11028 %}
11029
11030 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11031 match(Set dst (MoveI2F src));
11032 effect( DEF dst, USE src );
11033
11034 ins_cost(100);
11035 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11036 ins_encode %{
11037 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11038 %}
11039 ins_pipe( ialu_mem_reg );
11040 %}
11041
11042
11043 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11044 predicate(UseSSE==0);
11045 match(Set dst (MoveI2F src));
11046 effect(DEF dst, USE src);
11047
11048 ins_cost(125);
11049 format %{ "FLD_S $src\n\t"
11050 "FSTP $dst\t# MoveI2F_stack_reg" %}
11051 opcode(0xD9); /* D9 /0, FLD m32real */
11052 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11053 Pop_Reg_FPR(dst) );
11054 ins_pipe( fpu_reg_mem );
11055 %}
11056
11057 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11058 predicate(UseSSE>=1);
11059 match(Set dst (MoveI2F src));
11060 effect( DEF dst, USE src );
11061
11062 ins_cost(95);
11063 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11064 ins_encode %{
11065 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11066 %}
11067 ins_pipe( pipe_slow );
11068 %}
11069
11070 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11071 predicate(UseSSE>=2);
11072 match(Set dst (MoveI2F src));
11073 effect( DEF dst, USE src );
11074
11075 ins_cost(85);
11076 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11077 ins_encode %{
11078 __ movdl($dst$$XMMRegister, $src$$Register);
11079 %}
11080 ins_pipe( pipe_slow );
11081 %}
11082
11083 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11084 match(Set dst (MoveD2L src));
11085 effect(DEF dst, USE src);
11086
11087 ins_cost(250);
11088 format %{ "MOV $dst.lo,$src\n\t"
11089 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11090 opcode(0x8B, 0x8B);
11091 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11092 ins_pipe( ialu_mem_long_reg );
11093 %}
11094
11095 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11096 predicate(UseSSE<=1);
11097 match(Set dst (MoveD2L src));
11098 effect(DEF dst, USE src);
11099
11100 ins_cost(125);
11101 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11102 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11103 ins_pipe( fpu_mem_reg );
11104 %}
11105
11106 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11107 predicate(UseSSE>=2);
11108 match(Set dst (MoveD2L src));
11109 effect(DEF dst, USE src);
11110 ins_cost(95);
11111 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11112 ins_encode %{
11113 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11114 %}
11115 ins_pipe( pipe_slow );
11116 %}
11117
11118 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11119 predicate(UseSSE>=2);
11120 match(Set dst (MoveD2L src));
11121 effect(DEF dst, USE src, TEMP tmp);
11122 ins_cost(85);
11123 format %{ "MOVD $dst.lo,$src\n\t"
11124 "PSHUFLW $tmp,$src,0x4E\n\t"
11125 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11126 ins_encode %{
11127 __ movdl($dst$$Register, $src$$XMMRegister);
11128 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11129 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11130 %}
11131 ins_pipe( pipe_slow );
11132 %}
11133
11134 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11135 match(Set dst (MoveL2D src));
11136 effect(DEF dst, USE src);
11137
11138 ins_cost(200);
11139 format %{ "MOV $dst,$src.lo\n\t"
11140 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11141 opcode(0x89, 0x89);
11142 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11143 ins_pipe( ialu_mem_long_reg );
11144 %}
11145
11146
11147 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11148 predicate(UseSSE<=1);
11149 match(Set dst (MoveL2D src));
11150 effect(DEF dst, USE src);
11151 ins_cost(125);
11152
11153 format %{ "FLD_D $src\n\t"
11154 "FSTP $dst\t# MoveL2D_stack_reg" %}
11155 opcode(0xDD); /* DD /0, FLD m64real */
11156 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11157 Pop_Reg_DPR(dst) );
11158 ins_pipe( fpu_reg_mem );
11159 %}
11160
11161
11162 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11163 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11164 match(Set dst (MoveL2D src));
11165 effect(DEF dst, USE src);
11166
11167 ins_cost(95);
11168 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11169 ins_encode %{
11170 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11171 %}
11172 ins_pipe( pipe_slow );
11173 %}
11174
11175 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11176 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11177 match(Set dst (MoveL2D src));
11178 effect(DEF dst, USE src);
11179
11180 ins_cost(95);
11181 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11182 ins_encode %{
11183 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11184 %}
11185 ins_pipe( pipe_slow );
11186 %}
11187
11188 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11189 predicate(UseSSE>=2);
11190 match(Set dst (MoveL2D src));
11191 effect(TEMP dst, USE src, TEMP tmp);
11192 ins_cost(85);
11193 format %{ "MOVD $dst,$src.lo\n\t"
11194 "MOVD $tmp,$src.hi\n\t"
11195 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11196 ins_encode %{
11197 __ movdl($dst$$XMMRegister, $src$$Register);
11198 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11199 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11200 %}
11201 ins_pipe( pipe_slow );
11202 %}
11203
11204
11205 // =======================================================================
11206 // fast clearing of an array
11207 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11208 predicate(!UseFastStosb);
11209 match(Set dummy (ClearArray cnt base));
11210 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11211 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11212 "SHL ECX,1\t# Convert doublewords to words\n\t"
11213 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11214 ins_encode %{
11215 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11216 %}
11217 ins_pipe( pipe_slow );
11218 %}
11219
11220 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11221 predicate(UseFastStosb);
11222 match(Set dummy (ClearArray cnt base));
11223 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11224 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11225 "SHL ECX,3\t# Convert doublewords to bytes\n\t"
11226 "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11227 ins_encode %{
11228 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11229 %}
11230 ins_pipe( pipe_slow );
11231 %}
11232
11233 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11234 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11235 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11236 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11237
11238 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11239 ins_encode %{
11240 __ string_compare($str1$$Register, $str2$$Register,
11241 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11242 $tmp1$$XMMRegister);
11243 %}
11244 ins_pipe( pipe_slow );
11245 %}
11246
11247 // fast string equals
11248 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11249 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11250 match(Set result (StrEquals (Binary str1 str2) cnt));
11251 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11252
11253 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11254 ins_encode %{
11255 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11256 $cnt$$Register, $result$$Register, $tmp3$$Register,
11257 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11258 %}
11259 ins_pipe( pipe_slow );
11260 %}
11261
11262 // fast search of substring with known size.
11263 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11264 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11265 predicate(UseSSE42Intrinsics);
11266 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11267 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11268
11269 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11270 ins_encode %{
11271 int icnt2 = (int)$int_cnt2$$constant;
11272 if (icnt2 >= 8) {
11273 // IndexOf for constant substrings with size >= 8 elements
11274 // which don't need to be loaded through stack.
11275 __ string_indexofC8($str1$$Register, $str2$$Register,
11276 $cnt1$$Register, $cnt2$$Register,
11277 icnt2, $result$$Register,
11278 $vec$$XMMRegister, $tmp$$Register);
11279 } else {
11280 // Small strings are loaded through stack if they cross page boundary.
11281 __ string_indexof($str1$$Register, $str2$$Register,
11282 $cnt1$$Register, $cnt2$$Register,
11283 icnt2, $result$$Register,
11284 $vec$$XMMRegister, $tmp$$Register);
11285 }
11286 %}
11287 ins_pipe( pipe_slow );
11288 %}
11289
11290 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11291 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11292 predicate(UseSSE42Intrinsics);
11293 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11294 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11295
11296 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11297 ins_encode %{
11298 __ string_indexof($str1$$Register, $str2$$Register,
11299 $cnt1$$Register, $cnt2$$Register,
11300 (-1), $result$$Register,
11301 $vec$$XMMRegister, $tmp$$Register);
11302 %}
11303 ins_pipe( pipe_slow );
11304 %}
11305
11306 // fast array equals
11307 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11308 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11309 %{
11310 match(Set result (AryEq ary1 ary2));
11311 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11312 //ins_cost(300);
11313
11314 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11315 ins_encode %{
11316 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11317 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11318 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11319 %}
11320 ins_pipe( pipe_slow );
11321 %}
11322
11323 // encode char[] to byte[] in ISO_8859_1
11324 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11325 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11326 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11327 match(Set result (EncodeISOArray src (Binary dst len)));
11328 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11329
11330 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11331 ins_encode %{
11332 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11333 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11334 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11335 %}
11336 ins_pipe( pipe_slow );
11337 %}
11338
11339
11340 //----------Control Flow Instructions------------------------------------------
11341 // Signed compare Instructions
11342 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11343 match(Set cr (CmpI op1 op2));
11344 effect( DEF cr, USE op1, USE op2 );
11345 format %{ "CMP $op1,$op2" %}
11346 opcode(0x3B); /* Opcode 3B /r */
11347 ins_encode( OpcP, RegReg( op1, op2) );
11348 ins_pipe( ialu_cr_reg_reg );
11349 %}
11350
11351 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11352 match(Set cr (CmpI op1 op2));
11353 effect( DEF cr, USE op1 );
11354 format %{ "CMP $op1,$op2" %}
11355 opcode(0x81,0x07); /* Opcode 81 /7 */
11356 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11357 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11358 ins_pipe( ialu_cr_reg_imm );
11359 %}
11360
11361 // Cisc-spilled version of cmpI_eReg
11362 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11363 match(Set cr (CmpI op1 (LoadI op2)));
11364
11365 format %{ "CMP $op1,$op2" %}
11366 ins_cost(500);
11367 opcode(0x3B); /* Opcode 3B /r */
11368 ins_encode( OpcP, RegMem( op1, op2) );
11369 ins_pipe( ialu_cr_reg_mem );
11370 %}
11371
11372 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11373 match(Set cr (CmpI src zero));
11374 effect( DEF cr, USE src );
11375
11376 format %{ "TEST $src,$src" %}
11377 opcode(0x85);
11378 ins_encode( OpcP, RegReg( src, src ) );
11379 ins_pipe( ialu_cr_reg_imm );
11380 %}
11381
11382 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11383 match(Set cr (CmpI (AndI src con) zero));
11384
11385 format %{ "TEST $src,$con" %}
11386 opcode(0xF7,0x00);
11387 ins_encode( OpcP, RegOpc(src), Con32(con) );
11388 ins_pipe( ialu_cr_reg_imm );
11389 %}
11390
11391 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11392 match(Set cr (CmpI (AndI src mem) zero));
11393
11394 format %{ "TEST $src,$mem" %}
11395 opcode(0x85);
11396 ins_encode( OpcP, RegMem( src, mem ) );
11397 ins_pipe( ialu_cr_reg_mem );
11398 %}
11399
11400 // Unsigned compare Instructions; really, same as signed except they
11401 // produce an eFlagsRegU instead of eFlagsReg.
11402 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11403 match(Set cr (CmpU op1 op2));
11404
11405 format %{ "CMPu $op1,$op2" %}
11406 opcode(0x3B); /* Opcode 3B /r */
11407 ins_encode( OpcP, RegReg( op1, op2) );
11408 ins_pipe( ialu_cr_reg_reg );
11409 %}
11410
11411 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11412 match(Set cr (CmpU op1 op2));
11413
11414 format %{ "CMPu $op1,$op2" %}
11415 opcode(0x81,0x07); /* Opcode 81 /7 */
11416 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11417 ins_pipe( ialu_cr_reg_imm );
11418 %}
11419
11420 // // Cisc-spilled version of cmpU_eReg
11421 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11422 match(Set cr (CmpU op1 (LoadI op2)));
11423
11424 format %{ "CMPu $op1,$op2" %}
11425 ins_cost(500);
11426 opcode(0x3B); /* Opcode 3B /r */
11427 ins_encode( OpcP, RegMem( op1, op2) );
11428 ins_pipe( ialu_cr_reg_mem );
11429 %}
11430
11431 // // Cisc-spilled version of cmpU_eReg
11432 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11433 // match(Set cr (CmpU (LoadI op1) op2));
11434 //
11435 // format %{ "CMPu $op1,$op2" %}
11436 // ins_cost(500);
11437 // opcode(0x39); /* Opcode 39 /r */
11438 // ins_encode( OpcP, RegMem( op1, op2) );
11439 //%}
11440
11441 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11442 match(Set cr (CmpU src zero));
11443
11444 format %{ "TESTu $src,$src" %}
11445 opcode(0x85);
11446 ins_encode( OpcP, RegReg( src, src ) );
11447 ins_pipe( ialu_cr_reg_imm );
11448 %}
11449
11450 // Unsigned pointer compare Instructions
11451 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11452 match(Set cr (CmpP op1 op2));
11453
11454 format %{ "CMPu $op1,$op2" %}
11455 opcode(0x3B); /* Opcode 3B /r */
11456 ins_encode( OpcP, RegReg( op1, op2) );
11457 ins_pipe( ialu_cr_reg_reg );
11458 %}
11459
11460 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11461 match(Set cr (CmpP op1 op2));
11462
11463 format %{ "CMPu $op1,$op2" %}
11464 opcode(0x81,0x07); /* Opcode 81 /7 */
11465 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11466 ins_pipe( ialu_cr_reg_imm );
11467 %}
11468
11469 // // Cisc-spilled version of cmpP_eReg
11470 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11471 match(Set cr (CmpP op1 (LoadP op2)));
11472
11473 format %{ "CMPu $op1,$op2" %}
11474 ins_cost(500);
11475 opcode(0x3B); /* Opcode 3B /r */
11476 ins_encode( OpcP, RegMem( op1, op2) );
11477 ins_pipe( ialu_cr_reg_mem );
11478 %}
11479
11480 // // Cisc-spilled version of cmpP_eReg
11481 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11482 // match(Set cr (CmpP (LoadP op1) op2));
11483 //
11484 // format %{ "CMPu $op1,$op2" %}
11485 // ins_cost(500);
11486 // opcode(0x39); /* Opcode 39 /r */
11487 // ins_encode( OpcP, RegMem( op1, op2) );
11488 //%}
11489
11490 // Compare raw pointer (used in out-of-heap check).
11491 // Only works because non-oop pointers must be raw pointers
11492 // and raw pointers have no anti-dependencies.
11493 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11494 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
11495 match(Set cr (CmpP op1 (LoadP op2)));
11496
11497 format %{ "CMPu $op1,$op2" %}
11498 opcode(0x3B); /* Opcode 3B /r */
11499 ins_encode( OpcP, RegMem( op1, op2) );
11500 ins_pipe( ialu_cr_reg_mem );
11501 %}
11502
11503 //
11504 // This will generate a signed flags result. This should be ok
11505 // since any compare to a zero should be eq/neq.
11506 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11507 match(Set cr (CmpP src zero));
11508
11509 format %{ "TEST $src,$src" %}
11510 opcode(0x85);
11511 ins_encode( OpcP, RegReg( src, src ) );
11512 ins_pipe( ialu_cr_reg_imm );
11513 %}
11514
11515 // Cisc-spilled version of testP_reg
11516 // This will generate a signed flags result. This should be ok
11517 // since any compare to a zero should be eq/neq.
11518 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11519 match(Set cr (CmpP (LoadP op) zero));
11520
11521 format %{ "TEST $op,0xFFFFFFFF" %}
11522 ins_cost(500);
11523 opcode(0xF7); /* Opcode F7 /0 */
11524 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11525 ins_pipe( ialu_cr_reg_imm );
11526 %}
11527
11528 // Yanked all unsigned pointer compare operations.
11529 // Pointer compares are done with CmpP which is already unsigned.
11530
11531 //----------Max and Min--------------------------------------------------------
11532 // Min Instructions
11533 ////
11534 // *** Min and Max using the conditional move are slower than the
11535 // *** branch version on a Pentium III.
11536 // // Conditional move for min
11537 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11538 // effect( USE_DEF op2, USE op1, USE cr );
11539 // format %{ "CMOVlt $op2,$op1\t! min" %}
11540 // opcode(0x4C,0x0F);
11541 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11542 // ins_pipe( pipe_cmov_reg );
11543 //%}
11544 //
11545 //// Min Register with Register (P6 version)
11546 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11547 // predicate(VM_Version::supports_cmov() );
11548 // match(Set op2 (MinI op1 op2));
11549 // ins_cost(200);
11550 // expand %{
11551 // eFlagsReg cr;
11552 // compI_eReg(cr,op1,op2);
11553 // cmovI_reg_lt(op2,op1,cr);
11554 // %}
11555 //%}
11556
11557 // Min Register with Register (generic version)
11558 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11559 match(Set dst (MinI dst src));
11560 effect(KILL flags);
11561 ins_cost(300);
11562
11563 format %{ "MIN $dst,$src" %}
11564 opcode(0xCC);
11565 ins_encode( min_enc(dst,src) );
11566 ins_pipe( pipe_slow );
11567 %}
11568
11569 // Max Register with Register
11570 // *** Min and Max using the conditional move are slower than the
11571 // *** branch version on a Pentium III.
11572 // // Conditional move for max
11573 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11574 // effect( USE_DEF op2, USE op1, USE cr );
11575 // format %{ "CMOVgt $op2,$op1\t! max" %}
11576 // opcode(0x4F,0x0F);
11577 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11578 // ins_pipe( pipe_cmov_reg );
11579 //%}
11580 //
11581 // // Max Register with Register (P6 version)
11582 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11583 // predicate(VM_Version::supports_cmov() );
11584 // match(Set op2 (MaxI op1 op2));
11585 // ins_cost(200);
11586 // expand %{
11587 // eFlagsReg cr;
11588 // compI_eReg(cr,op1,op2);
11589 // cmovI_reg_gt(op2,op1,cr);
11590 // %}
11591 //%}
11592
11593 // Max Register with Register (generic version)
11594 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11595 match(Set dst (MaxI dst src));
11596 effect(KILL flags);
11597 ins_cost(300);
11598
11599 format %{ "MAX $dst,$src" %}
11600 opcode(0xCC);
11601 ins_encode( max_enc(dst,src) );
11602 ins_pipe( pipe_slow );
11603 %}
11604
11605 // ============================================================================
11606 // Counted Loop limit node which represents exact final iterator value.
11607 // Note: the resulting value should fit into integer range since
11608 // counted loops have limit check on overflow.
11609 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
11610 match(Set limit (LoopLimit (Binary init limit) stride));
11611 effect(TEMP limit_hi, TEMP tmp, KILL flags);
11612 ins_cost(300);
11613
11614 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
11615 ins_encode %{
11616 int strd = (int)$stride$$constant;
11617 assert(strd != 1 && strd != -1, "sanity");
11618 int m1 = (strd > 0) ? 1 : -1;
11619 // Convert limit to long (EAX:EDX)
11620 __ cdql();
11621 // Convert init to long (init:tmp)
11622 __ movl($tmp$$Register, $init$$Register);
11623 __ sarl($tmp$$Register, 31);
11624 // $limit - $init
11625 __ subl($limit$$Register, $init$$Register);
11626 __ sbbl($limit_hi$$Register, $tmp$$Register);
11627 // + ($stride - 1)
11628 if (strd > 0) {
11629 __ addl($limit$$Register, (strd - 1));
11630 __ adcl($limit_hi$$Register, 0);
11631 __ movl($tmp$$Register, strd);
11632 } else {
11633 __ addl($limit$$Register, (strd + 1));
11634 __ adcl($limit_hi$$Register, -1);
11635 __ lneg($limit_hi$$Register, $limit$$Register);
11636 __ movl($tmp$$Register, -strd);
11637 }
11638 // signed devision: (EAX:EDX) / pos_stride
11639 __ idivl($tmp$$Register);
11640 if (strd < 0) {
11641 // restore sign
11642 __ negl($tmp$$Register);
11643 }
11644 // (EAX) * stride
11645 __ mull($tmp$$Register);
11646 // + init (ignore upper bits)
11647 __ addl($limit$$Register, $init$$Register);
11648 %}
11649 ins_pipe( pipe_slow );
11650 %}
11651
11652 // ============================================================================
11653 // Branch Instructions
11654 // Jump Table
11655 instruct jumpXtnd(rRegI switch_val) %{
11656 match(Jump switch_val);
11657 ins_cost(350);
11658 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
11659 ins_encode %{
11660 // Jump to Address(table_base + switch_reg)
11661 Address index(noreg, $switch_val$$Register, Address::times_1);
11662 __ jump(ArrayAddress($constantaddress, index));
11663 %}
11664 ins_pipe(pipe_jmp);
11665 %}
11666
11667 // Jump Direct - Label defines a relative address from JMP+1
11668 instruct jmpDir(label labl) %{
11669 match(Goto);
11670 effect(USE labl);
11671
11672 ins_cost(300);
11673 format %{ "JMP $labl" %}
11674 size(5);
11675 ins_encode %{
11676 Label* L = $labl$$label;
11677 __ jmp(*L, false); // Always long jump
11678 %}
11679 ins_pipe( pipe_jmp );
11680 %}
11681
11682 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11683 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
11684 match(If cop cr);
11685 effect(USE labl);
11686
11687 ins_cost(300);
11688 format %{ "J$cop $labl" %}
11689 size(6);
11690 ins_encode %{
11691 Label* L = $labl$$label;
11692 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11693 %}
11694 ins_pipe( pipe_jcc );
11695 %}
11696
11697 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11698 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
11699 match(CountedLoopEnd cop cr);
11700 effect(USE labl);
11701
11702 ins_cost(300);
11703 format %{ "J$cop $labl\t# Loop end" %}
11704 size(6);
11705 ins_encode %{
11706 Label* L = $labl$$label;
11707 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11708 %}
11709 ins_pipe( pipe_jcc );
11710 %}
11711
11712 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11713 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
11714 match(CountedLoopEnd cop cmp);
11715 effect(USE labl);
11716
11717 ins_cost(300);
11718 format %{ "J$cop,u $labl\t# Loop end" %}
11719 size(6);
11720 ins_encode %{
11721 Label* L = $labl$$label;
11722 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11723 %}
11724 ins_pipe( pipe_jcc );
11725 %}
11726
11727 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
11728 match(CountedLoopEnd cop cmp);
11729 effect(USE labl);
11730
11731 ins_cost(200);
11732 format %{ "J$cop,u $labl\t# Loop end" %}
11733 size(6);
11734 ins_encode %{
11735 Label* L = $labl$$label;
11736 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11737 %}
11738 ins_pipe( pipe_jcc );
11739 %}
11740
11741 // Jump Direct Conditional - using unsigned comparison
11742 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
11743 match(If cop cmp);
11744 effect(USE labl);
11745
11746 ins_cost(300);
11747 format %{ "J$cop,u $labl" %}
11748 size(6);
11749 ins_encode %{
11750 Label* L = $labl$$label;
11751 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11752 %}
11753 ins_pipe(pipe_jcc);
11754 %}
11755
11756 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
11757 match(If cop cmp);
11758 effect(USE labl);
11759
11760 ins_cost(200);
11761 format %{ "J$cop,u $labl" %}
11762 size(6);
11763 ins_encode %{
11764 Label* L = $labl$$label;
11765 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11766 %}
11767 ins_pipe(pipe_jcc);
11768 %}
11769
11770 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
11771 match(If cop cmp);
11772 effect(USE labl);
11773
11774 ins_cost(200);
11775 format %{ $$template
11776 if ($cop$$cmpcode == Assembler::notEqual) {
11777 $$emit$$"JP,u $labl\n\t"
11778 $$emit$$"J$cop,u $labl"
11779 } else {
11780 $$emit$$"JP,u done\n\t"
11781 $$emit$$"J$cop,u $labl\n\t"
11782 $$emit$$"done:"
11783 }
11784 %}
11785 ins_encode %{
11786 Label* l = $labl$$label;
11787 if ($cop$$cmpcode == Assembler::notEqual) {
11788 __ jcc(Assembler::parity, *l, false);
11789 __ jcc(Assembler::notEqual, *l, false);
11790 } else if ($cop$$cmpcode == Assembler::equal) {
11791 Label done;
11792 __ jccb(Assembler::parity, done);
11793 __ jcc(Assembler::equal, *l, false);
11794 __ bind(done);
11795 } else {
11796 ShouldNotReachHere();
11797 }
11798 %}
11799 ins_pipe(pipe_jcc);
11800 %}
11801
11802 // ============================================================================
11803 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
11804 // array for an instance of the superklass. Set a hidden internal cache on a
11805 // hit (cache is checked with exposed code in gen_subtype_check()). Return
11806 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
11807 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
11808 match(Set result (PartialSubtypeCheck sub super));
11809 effect( KILL rcx, KILL cr );
11810
11811 ins_cost(1100); // slightly larger than the next version
11812 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
11813 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
11814 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
11815 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
11816 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
11817 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
11818 "XOR $result,$result\t\t Hit: EDI zero\n\t"
11819 "miss:\t" %}
11820
11821 opcode(0x1); // Force a XOR of EDI
11822 ins_encode( enc_PartialSubtypeCheck() );
11823 ins_pipe( pipe_slow );
11824 %}
11825
11826 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
11827 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11828 effect( KILL rcx, KILL result );
11829
11830 ins_cost(1000);
11831 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
11832 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
11833 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
11834 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
11835 "JNE,s miss\t\t# Missed: flags NZ\n\t"
11836 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
11837 "miss:\t" %}
11838
11839 opcode(0x0); // No need to XOR EDI
11840 ins_encode( enc_PartialSubtypeCheck() );
11841 ins_pipe( pipe_slow );
11842 %}
11843
11844 // ============================================================================
11845 // Branch Instructions -- short offset versions
11846 //
11847 // These instructions are used to replace jumps of a long offset (the default
11848 // match) with jumps of a shorter offset. These instructions are all tagged
11849 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11850 // match rules in general matching. Instead, the ADLC generates a conversion
11851 // method in the MachNode which can be used to do in-place replacement of the
11852 // long variant with the shorter variant. The compiler will determine if a
11853 // branch can be taken by the is_short_branch_offset() predicate in the machine
11854 // specific code section of the file.
11855
11856 // Jump Direct - Label defines a relative address from JMP+1
11857 instruct jmpDir_short(label labl) %{
11858 match(Goto);
11859 effect(USE labl);
11860
11861 ins_cost(300);
11862 format %{ "JMP,s $labl" %}
11863 size(2);
11864 ins_encode %{
11865 Label* L = $labl$$label;
11866 __ jmpb(*L);
11867 %}
11868 ins_pipe( pipe_jmp );
11869 ins_short_branch(1);
11870 %}
11871
11872 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11873 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
11874 match(If cop cr);
11875 effect(USE labl);
11876
11877 ins_cost(300);
11878 format %{ "J$cop,s $labl" %}
11879 size(2);
11880 ins_encode %{
11881 Label* L = $labl$$label;
11882 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11883 %}
11884 ins_pipe( pipe_jcc );
11885 ins_short_branch(1);
11886 %}
11887
11888 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11889 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
11890 match(CountedLoopEnd cop cr);
11891 effect(USE labl);
11892
11893 ins_cost(300);
11894 format %{ "J$cop,s $labl\t# Loop end" %}
11895 size(2);
11896 ins_encode %{
11897 Label* L = $labl$$label;
11898 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11899 %}
11900 ins_pipe( pipe_jcc );
11901 ins_short_branch(1);
11902 %}
11903
11904 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11905 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
11906 match(CountedLoopEnd cop cmp);
11907 effect(USE labl);
11908
11909 ins_cost(300);
11910 format %{ "J$cop,us $labl\t# Loop end" %}
11911 size(2);
11912 ins_encode %{
11913 Label* L = $labl$$label;
11914 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11915 %}
11916 ins_pipe( pipe_jcc );
11917 ins_short_branch(1);
11918 %}
11919
11920 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
11921 match(CountedLoopEnd cop cmp);
11922 effect(USE labl);
11923
11924 ins_cost(300);
11925 format %{ "J$cop,us $labl\t# Loop end" %}
11926 size(2);
11927 ins_encode %{
11928 Label* L = $labl$$label;
11929 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11930 %}
11931 ins_pipe( pipe_jcc );
11932 ins_short_branch(1);
11933 %}
11934
11935 // Jump Direct Conditional - using unsigned comparison
11936 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
11937 match(If cop cmp);
11938 effect(USE labl);
11939
11940 ins_cost(300);
11941 format %{ "J$cop,us $labl" %}
11942 size(2);
11943 ins_encode %{
11944 Label* L = $labl$$label;
11945 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11946 %}
11947 ins_pipe( pipe_jcc );
11948 ins_short_branch(1);
11949 %}
11950
11951 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
11952 match(If cop cmp);
11953 effect(USE labl);
11954
11955 ins_cost(300);
11956 format %{ "J$cop,us $labl" %}
11957 size(2);
11958 ins_encode %{
11959 Label* L = $labl$$label;
11960 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11961 %}
11962 ins_pipe( pipe_jcc );
11963 ins_short_branch(1);
11964 %}
11965
11966 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
11967 match(If cop cmp);
11968 effect(USE labl);
11969
11970 ins_cost(300);
11971 format %{ $$template
11972 if ($cop$$cmpcode == Assembler::notEqual) {
11973 $$emit$$"JP,u,s $labl\n\t"
11974 $$emit$$"J$cop,u,s $labl"
11975 } else {
11976 $$emit$$"JP,u,s done\n\t"
11977 $$emit$$"J$cop,u,s $labl\n\t"
11978 $$emit$$"done:"
11979 }
11980 %}
11981 size(4);
11982 ins_encode %{
11983 Label* l = $labl$$label;
11984 if ($cop$$cmpcode == Assembler::notEqual) {
11985 __ jccb(Assembler::parity, *l);
11986 __ jccb(Assembler::notEqual, *l);
11987 } else if ($cop$$cmpcode == Assembler::equal) {
11988 Label done;
11989 __ jccb(Assembler::parity, done);
11990 __ jccb(Assembler::equal, *l);
11991 __ bind(done);
11992 } else {
11993 ShouldNotReachHere();
11994 }
11995 %}
11996 ins_pipe(pipe_jcc);
11997 ins_short_branch(1);
11998 %}
11999
12000 // ============================================================================
12001 // Long Compare
12002 //
12003 // Currently we hold longs in 2 registers. Comparing such values efficiently
12004 // is tricky. The flavor of compare used depends on whether we are testing
12005 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12006 // The GE test is the negated LT test. The LE test can be had by commuting
12007 // the operands (yielding a GE test) and then negating; negate again for the
12008 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12009 // NE test is negated from that.
12010
12011 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12012 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12013 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12014 // are collapsed internally in the ADLC's dfa-gen code. The match for
12015 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12016 // foo match ends up with the wrong leaf. One fix is to not match both
12017 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12018 // both forms beat the trinary form of long-compare and both are very useful
12019 // on Intel which has so few registers.
12020
12021 // Manifest a CmpL result in an integer register. Very painful.
12022 // This is the test to avoid.
12023 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12024 match(Set dst (CmpL3 src1 src2));
12025 effect( KILL flags );
12026 ins_cost(1000);
12027 format %{ "XOR $dst,$dst\n\t"
12028 "CMP $src1.hi,$src2.hi\n\t"
12029 "JLT,s m_one\n\t"
12030 "JGT,s p_one\n\t"
12031 "CMP $src1.lo,$src2.lo\n\t"
12032 "JB,s m_one\n\t"
12033 "JEQ,s done\n"
12034 "p_one:\tINC $dst\n\t"
12035 "JMP,s done\n"
12036 "m_one:\tDEC $dst\n"
12037 "done:" %}
12038 ins_encode %{
12039 Label p_one, m_one, done;
12040 __ xorptr($dst$$Register, $dst$$Register);
12041 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12042 __ jccb(Assembler::less, m_one);
12043 __ jccb(Assembler::greater, p_one);
12044 __ cmpl($src1$$Register, $src2$$Register);
12045 __ jccb(Assembler::below, m_one);
12046 __ jccb(Assembler::equal, done);
12047 __ bind(p_one);
12048 __ incrementl($dst$$Register);
12049 __ jmpb(done);
12050 __ bind(m_one);
12051 __ decrementl($dst$$Register);
12052 __ bind(done);
12053 %}
12054 ins_pipe( pipe_slow );
12055 %}
12056
12057 //======
12058 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12059 // compares. Can be used for LE or GT compares by reversing arguments.
12060 // NOT GOOD FOR EQ/NE tests.
12061 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12062 match( Set flags (CmpL src zero ));
12063 ins_cost(100);
12064 format %{ "TEST $src.hi,$src.hi" %}
12065 opcode(0x85);
12066 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12067 ins_pipe( ialu_cr_reg_reg );
12068 %}
12069
12070 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12071 // compares. Can be used for LE or GT compares by reversing arguments.
12072 // NOT GOOD FOR EQ/NE tests.
12073 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12074 match( Set flags (CmpL src1 src2 ));
12075 effect( TEMP tmp );
12076 ins_cost(300);
12077 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12078 "MOV $tmp,$src1.hi\n\t"
12079 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12080 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12081 ins_pipe( ialu_cr_reg_reg );
12082 %}
12083
12084 // Long compares reg < zero/req OR reg >= zero/req.
12085 // Just a wrapper for a normal branch, plus the predicate test.
12086 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12087 match(If cmp flags);
12088 effect(USE labl);
12089 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12090 expand %{
12091 jmpCon(cmp,flags,labl); // JLT or JGE...
12092 %}
12093 %}
12094
12095 // Compare 2 longs and CMOVE longs.
12096 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12097 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12098 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12099 ins_cost(400);
12100 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12101 "CMOV$cmp $dst.hi,$src.hi" %}
12102 opcode(0x0F,0x40);
12103 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12104 ins_pipe( pipe_cmov_reg_long );
12105 %}
12106
12107 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12108 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12109 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12110 ins_cost(500);
12111 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12112 "CMOV$cmp $dst.hi,$src.hi" %}
12113 opcode(0x0F,0x40);
12114 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12115 ins_pipe( pipe_cmov_reg_long );
12116 %}
12117
12118 // Compare 2 longs and CMOVE ints.
12119 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12120 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12121 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12122 ins_cost(200);
12123 format %{ "CMOV$cmp $dst,$src" %}
12124 opcode(0x0F,0x40);
12125 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12126 ins_pipe( pipe_cmov_reg );
12127 %}
12128
12129 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12130 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12131 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12132 ins_cost(250);
12133 format %{ "CMOV$cmp $dst,$src" %}
12134 opcode(0x0F,0x40);
12135 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12136 ins_pipe( pipe_cmov_mem );
12137 %}
12138
12139 // Compare 2 longs and CMOVE ints.
12140 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12141 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12142 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12143 ins_cost(200);
12144 format %{ "CMOV$cmp $dst,$src" %}
12145 opcode(0x0F,0x40);
12146 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12147 ins_pipe( pipe_cmov_reg );
12148 %}
12149
12150 // Compare 2 longs and CMOVE doubles
12151 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12152 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12153 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12154 ins_cost(200);
12155 expand %{
12156 fcmovDPR_regS(cmp,flags,dst,src);
12157 %}
12158 %}
12159
12160 // Compare 2 longs and CMOVE doubles
12161 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12162 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12163 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12164 ins_cost(200);
12165 expand %{
12166 fcmovD_regS(cmp,flags,dst,src);
12167 %}
12168 %}
12169
12170 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12171 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12172 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12173 ins_cost(200);
12174 expand %{
12175 fcmovFPR_regS(cmp,flags,dst,src);
12176 %}
12177 %}
12178
12179 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12180 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12181 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12182 ins_cost(200);
12183 expand %{
12184 fcmovF_regS(cmp,flags,dst,src);
12185 %}
12186 %}
12187
12188 //======
12189 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12190 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12191 match( Set flags (CmpL src zero ));
12192 effect(TEMP tmp);
12193 ins_cost(200);
12194 format %{ "MOV $tmp,$src.lo\n\t"
12195 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12196 ins_encode( long_cmp_flags0( src, tmp ) );
12197 ins_pipe( ialu_reg_reg_long );
12198 %}
12199
12200 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12201 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12202 match( Set flags (CmpL src1 src2 ));
12203 ins_cost(200+300);
12204 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12205 "JNE,s skip\n\t"
12206 "CMP $src1.hi,$src2.hi\n\t"
12207 "skip:\t" %}
12208 ins_encode( long_cmp_flags1( src1, src2 ) );
12209 ins_pipe( ialu_cr_reg_reg );
12210 %}
12211
12212 // Long compare reg == zero/reg OR reg != zero/reg
12213 // Just a wrapper for a normal branch, plus the predicate test.
12214 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12215 match(If cmp flags);
12216 effect(USE labl);
12217 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12218 expand %{
12219 jmpCon(cmp,flags,labl); // JEQ or JNE...
12220 %}
12221 %}
12222
12223 // Compare 2 longs and CMOVE longs.
12224 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12225 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12226 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12227 ins_cost(400);
12228 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12229 "CMOV$cmp $dst.hi,$src.hi" %}
12230 opcode(0x0F,0x40);
12231 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12232 ins_pipe( pipe_cmov_reg_long );
12233 %}
12234
12235 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12236 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12237 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12238 ins_cost(500);
12239 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12240 "CMOV$cmp $dst.hi,$src.hi" %}
12241 opcode(0x0F,0x40);
12242 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12243 ins_pipe( pipe_cmov_reg_long );
12244 %}
12245
12246 // Compare 2 longs and CMOVE ints.
12247 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12248 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12249 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12250 ins_cost(200);
12251 format %{ "CMOV$cmp $dst,$src" %}
12252 opcode(0x0F,0x40);
12253 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12254 ins_pipe( pipe_cmov_reg );
12255 %}
12256
12257 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12258 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12259 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12260 ins_cost(250);
12261 format %{ "CMOV$cmp $dst,$src" %}
12262 opcode(0x0F,0x40);
12263 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12264 ins_pipe( pipe_cmov_mem );
12265 %}
12266
12267 // Compare 2 longs and CMOVE ints.
12268 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12269 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12270 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12271 ins_cost(200);
12272 format %{ "CMOV$cmp $dst,$src" %}
12273 opcode(0x0F,0x40);
12274 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12275 ins_pipe( pipe_cmov_reg );
12276 %}
12277
12278 // Compare 2 longs and CMOVE doubles
12279 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12280 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12281 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12282 ins_cost(200);
12283 expand %{
12284 fcmovDPR_regS(cmp,flags,dst,src);
12285 %}
12286 %}
12287
12288 // Compare 2 longs and CMOVE doubles
12289 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12290 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12291 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12292 ins_cost(200);
12293 expand %{
12294 fcmovD_regS(cmp,flags,dst,src);
12295 %}
12296 %}
12297
12298 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12299 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12300 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12301 ins_cost(200);
12302 expand %{
12303 fcmovFPR_regS(cmp,flags,dst,src);
12304 %}
12305 %}
12306
12307 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12308 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12309 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12310 ins_cost(200);
12311 expand %{
12312 fcmovF_regS(cmp,flags,dst,src);
12313 %}
12314 %}
12315
12316 //======
12317 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12318 // Same as cmpL_reg_flags_LEGT except must negate src
12319 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12320 match( Set flags (CmpL src zero ));
12321 effect( TEMP tmp );
12322 ins_cost(300);
12323 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12324 "CMP $tmp,$src.lo\n\t"
12325 "SBB $tmp,$src.hi\n\t" %}
12326 ins_encode( long_cmp_flags3(src, tmp) );
12327 ins_pipe( ialu_reg_reg_long );
12328 %}
12329
12330 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12331 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12332 // requires a commuted test to get the same result.
12333 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12334 match( Set flags (CmpL src1 src2 ));
12335 effect( TEMP tmp );
12336 ins_cost(300);
12337 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12338 "MOV $tmp,$src2.hi\n\t"
12339 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12340 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12341 ins_pipe( ialu_cr_reg_reg );
12342 %}
12343
12344 // Long compares reg < zero/req OR reg >= zero/req.
12345 // Just a wrapper for a normal branch, plus the predicate test
12346 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12347 match(If cmp flags);
12348 effect(USE labl);
12349 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12350 ins_cost(300);
12351 expand %{
12352 jmpCon(cmp,flags,labl); // JGT or JLE...
12353 %}
12354 %}
12355
12356 // Compare 2 longs and CMOVE longs.
12357 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12358 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12359 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12360 ins_cost(400);
12361 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12362 "CMOV$cmp $dst.hi,$src.hi" %}
12363 opcode(0x0F,0x40);
12364 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12365 ins_pipe( pipe_cmov_reg_long );
12366 %}
12367
12368 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12369 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12370 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12371 ins_cost(500);
12372 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12373 "CMOV$cmp $dst.hi,$src.hi+4" %}
12374 opcode(0x0F,0x40);
12375 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12376 ins_pipe( pipe_cmov_reg_long );
12377 %}
12378
12379 // Compare 2 longs and CMOVE ints.
12380 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12381 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12382 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12383 ins_cost(200);
12384 format %{ "CMOV$cmp $dst,$src" %}
12385 opcode(0x0F,0x40);
12386 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12387 ins_pipe( pipe_cmov_reg );
12388 %}
12389
12390 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12391 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12392 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12393 ins_cost(250);
12394 format %{ "CMOV$cmp $dst,$src" %}
12395 opcode(0x0F,0x40);
12396 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12397 ins_pipe( pipe_cmov_mem );
12398 %}
12399
12400 // Compare 2 longs and CMOVE ptrs.
12401 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12402 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12403 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12404 ins_cost(200);
12405 format %{ "CMOV$cmp $dst,$src" %}
12406 opcode(0x0F,0x40);
12407 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12408 ins_pipe( pipe_cmov_reg );
12409 %}
12410
12411 // Compare 2 longs and CMOVE doubles
12412 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12413 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12414 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12415 ins_cost(200);
12416 expand %{
12417 fcmovDPR_regS(cmp,flags,dst,src);
12418 %}
12419 %}
12420
12421 // Compare 2 longs and CMOVE doubles
12422 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12423 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12424 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12425 ins_cost(200);
12426 expand %{
12427 fcmovD_regS(cmp,flags,dst,src);
12428 %}
12429 %}
12430
12431 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12432 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12433 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12434 ins_cost(200);
12435 expand %{
12436 fcmovFPR_regS(cmp,flags,dst,src);
12437 %}
12438 %}
12439
12440
12441 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12442 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12443 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12444 ins_cost(200);
12445 expand %{
12446 fcmovF_regS(cmp,flags,dst,src);
12447 %}
12448 %}
12449
12450
12451 // ============================================================================
12452 // Procedure Call/Return Instructions
12453 // Call Java Static Instruction
12454 // Note: If this code changes, the corresponding ret_addr_offset() and
12455 // compute_padding() functions will have to be adjusted.
12456 instruct CallStaticJavaDirect(method meth) %{
12457 match(CallStaticJava);
12458 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12459 effect(USE meth);
12460
12461 ins_cost(300);
12462 format %{ "CALL,static " %}
12463 opcode(0xE8); /* E8 cd */
12464 ins_encode( pre_call_resets,
12465 Java_Static_Call( meth ),
12466 call_epilog,
12467 post_call_FPU );
12468 ins_pipe( pipe_slow );
12469 ins_alignment(4);
12470 %}
12471
12472 // Call Java Static Instruction (method handle version)
12473 // Note: If this code changes, the corresponding ret_addr_offset() and
12474 // compute_padding() functions will have to be adjusted.
12475 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12476 match(CallStaticJava);
12477 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12478 effect(USE meth);
12479 // EBP is saved by all callees (for interpreter stack correction).
12480 // We use it here for a similar purpose, in {preserve,restore}_SP.
12481
12482 ins_cost(300);
12483 format %{ "CALL,static/MethodHandle " %}
12484 opcode(0xE8); /* E8 cd */
12485 ins_encode( pre_call_resets,
12486 preserve_SP,
12487 Java_Static_Call( meth ),
12488 restore_SP,
12489 call_epilog,
12490 post_call_FPU );
12491 ins_pipe( pipe_slow );
12492 ins_alignment(4);
12493 %}
12494
12495 // Call Java Dynamic Instruction
12496 // Note: If this code changes, the corresponding ret_addr_offset() and
12497 // compute_padding() functions will have to be adjusted.
12498 instruct CallDynamicJavaDirect(method meth) %{
12499 match(CallDynamicJava);
12500 effect(USE meth);
12501
12502 ins_cost(300);
12503 format %{ "MOV EAX,(oop)-1\n\t"
12504 "CALL,dynamic" %}
12505 opcode(0xE8); /* E8 cd */
12506 ins_encode( pre_call_resets,
12507 Java_Dynamic_Call( meth ),
12508 call_epilog,
12509 post_call_FPU );
12510 ins_pipe( pipe_slow );
12511 ins_alignment(4);
12512 %}
12513
12514 // Call Runtime Instruction
12515 instruct CallRuntimeDirect(method meth) %{
12516 match(CallRuntime );
12517 effect(USE meth);
12518
12519 ins_cost(300);
12520 format %{ "CALL,runtime " %}
12521 opcode(0xE8); /* E8 cd */
12522 // Use FFREEs to clear entries in float stack
12523 ins_encode( pre_call_resets,
12524 FFree_Float_Stack_All,
12525 Java_To_Runtime( meth ),
12526 post_call_FPU );
12527 ins_pipe( pipe_slow );
12528 %}
12529
12530 // Call runtime without safepoint
12531 instruct CallLeafDirect(method meth) %{
12532 match(CallLeaf);
12533 effect(USE meth);
12534
12535 ins_cost(300);
12536 format %{ "CALL_LEAF,runtime " %}
12537 opcode(0xE8); /* E8 cd */
12538 ins_encode( pre_call_resets,
12539 FFree_Float_Stack_All,
12540 Java_To_Runtime( meth ),
12541 Verify_FPU_For_Leaf, post_call_FPU );
12542 ins_pipe( pipe_slow );
12543 %}
12544
12545 instruct CallLeafNoFPDirect(method meth) %{
12546 match(CallLeafNoFP);
12547 effect(USE meth);
12548
12549 ins_cost(300);
12550 format %{ "CALL_LEAF_NOFP,runtime " %}
12551 opcode(0xE8); /* E8 cd */
12552 ins_encode(Java_To_Runtime(meth));
12553 ins_pipe( pipe_slow );
12554 %}
12555
12556
12557 // Return Instruction
12558 // Remove the return address & jump to it.
12559 instruct Ret() %{
12560 match(Return);
12561 format %{ "RET" %}
12562 opcode(0xC3);
12563 ins_encode(OpcP);
12564 ins_pipe( pipe_jmp );
12565 %}
12566
12567 // Tail Call; Jump from runtime stub to Java code.
12568 // Also known as an 'interprocedural jump'.
12569 // Target of jump will eventually return to caller.
12570 // TailJump below removes the return address.
12571 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12572 match(TailCall jump_target method_oop );
12573 ins_cost(300);
12574 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12575 opcode(0xFF, 0x4); /* Opcode FF /4 */
12576 ins_encode( OpcP, RegOpc(jump_target) );
12577 ins_pipe( pipe_jmp );
12578 %}
12579
12580
12581 // Tail Jump; remove the return address; jump to target.
12582 // TailCall above leaves the return address around.
12583 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12584 match( TailJump jump_target ex_oop );
12585 ins_cost(300);
12586 format %{ "POP EDX\t# pop return address into dummy\n\t"
12587 "JMP $jump_target " %}
12588 opcode(0xFF, 0x4); /* Opcode FF /4 */
12589 ins_encode( enc_pop_rdx,
12590 OpcP, RegOpc(jump_target) );
12591 ins_pipe( pipe_jmp );
12592 %}
12593
12594 // Create exception oop: created by stack-crawling runtime code.
12595 // Created exception is now available to this handler, and is setup
12596 // just prior to jumping to this handler. No code emitted.
12597 instruct CreateException( eAXRegP ex_oop )
12598 %{
12599 match(Set ex_oop (CreateEx));
12600
12601 size(0);
12602 // use the following format syntax
12603 format %{ "# exception oop is in EAX; no code emitted" %}
12604 ins_encode();
12605 ins_pipe( empty );
12606 %}
12607
12608
12609 // Rethrow exception:
12610 // The exception oop will come in the first argument position.
12611 // Then JUMP (not call) to the rethrow stub code.
12612 instruct RethrowException()
12613 %{
12614 match(Rethrow);
12615
12616 // use the following format syntax
12617 format %{ "JMP rethrow_stub" %}
12618 ins_encode(enc_rethrow);
12619 ins_pipe( pipe_jmp );
12620 %}
12621
12622 // inlined locking and unlocking
12623
12624 instruct cmpFastLock(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
12625 match(Set cr (FastLock object box));
12626 effect(TEMP tmp, TEMP scr, USE_KILL box);
12627 ins_cost(300);
12628 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
12629 ins_encode %{
12630 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, $scr$$Register, _counters);
12631 %}
12632 ins_pipe(pipe_slow);
12633 %}
12634
12635 instruct cmpFastUnlock(eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12636 match(Set cr (FastUnlock object box));
12637 effect(TEMP tmp, USE_KILL box);
12638 ins_cost(300);
12639 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
12640 ins_encode %{
12641 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register);
12642 %}
12643 ins_pipe(pipe_slow);
12644 %}
12645
12646
12647
12648 // ============================================================================
12649 // Safepoint Instruction
12650 instruct safePoint_poll(eFlagsReg cr) %{
12651 match(SafePoint);
12652 effect(KILL cr);
12653
12654 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
12655 // On SPARC that might be acceptable as we can generate the address with
12656 // just a sethi, saving an or. By polling at offset 0 we can end up
12657 // putting additional pressure on the index-0 in the D$. Because of
12658 // alignment (just like the situation at hand) the lower indices tend
12659 // to see more traffic. It'd be better to change the polling address
12660 // to offset 0 of the last $line in the polling page.
12661
12662 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
12663 ins_cost(125);
12664 size(6) ;
12665 ins_encode( Safepoint_Poll() );
12666 ins_pipe( ialu_reg_mem );
12667 %}
12668
12669
12670 // ============================================================================
12671 // This name is KNOWN by the ADLC and cannot be changed.
12672 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12673 // for this guy.
12674 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
12675 match(Set dst (ThreadLocal));
12676 effect(DEF dst, KILL cr);
12677
12678 format %{ "MOV $dst, Thread::current()" %}
12679 ins_encode %{
12680 Register dstReg = as_Register($dst$$reg);
12681 __ get_thread(dstReg);
12682 %}
12683 ins_pipe( ialu_reg_fat );
12684 %}
12685
12686
12687
12688 //----------PEEPHOLE RULES-----------------------------------------------------
12689 // These must follow all instruction definitions as they use the names
12690 // defined in the instructions definitions.
12691 //
12692 // peepmatch ( root_instr_name [preceding_instruction]* );
12693 //
12694 // peepconstraint %{
12695 // (instruction_number.operand_name relational_op instruction_number.operand_name
12696 // [, ...] );
12697 // // instruction numbers are zero-based using left to right order in peepmatch
12698 //
12699 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12700 // // provide an instruction_number.operand_name for each operand that appears
12701 // // in the replacement instruction's match rule
12702 //
12703 // ---------VM FLAGS---------------------------------------------------------
12704 //
12705 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12706 //
12707 // Each peephole rule is given an identifying number starting with zero and
12708 // increasing by one in the order seen by the parser. An individual peephole
12709 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12710 // on the command-line.
12711 //
12712 // ---------CURRENT LIMITATIONS----------------------------------------------
12713 //
12714 // Only match adjacent instructions in same basic block
12715 // Only equality constraints
12716 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12717 // Only one replacement instruction
12718 //
12719 // ---------EXAMPLE----------------------------------------------------------
12720 //
12721 // // pertinent parts of existing instructions in architecture description
12722 // instruct movI(rRegI dst, rRegI src) %{
12723 // match(Set dst (CopyI src));
12724 // %}
12725 //
12726 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
12727 // match(Set dst (AddI dst src));
12728 // effect(KILL cr);
12729 // %}
12730 //
12731 // // Change (inc mov) to lea
12732 // peephole %{
12733 // // increment preceeded by register-register move
12734 // peepmatch ( incI_eReg movI );
12735 // // require that the destination register of the increment
12736 // // match the destination register of the move
12737 // peepconstraint ( 0.dst == 1.dst );
12738 // // construct a replacement instruction that sets
12739 // // the destination to ( move's source register + one )
12740 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12741 // %}
12742 //
12743 // Implementation no longer uses movX instructions since
12744 // machine-independent system no longer uses CopyX nodes.
12745 //
12746 // peephole %{
12747 // peepmatch ( incI_eReg movI );
12748 // peepconstraint ( 0.dst == 1.dst );
12749 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12750 // %}
12751 //
12752 // peephole %{
12753 // peepmatch ( decI_eReg movI );
12754 // peepconstraint ( 0.dst == 1.dst );
12755 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12756 // %}
12757 //
12758 // peephole %{
12759 // peepmatch ( addI_eReg_imm movI );
12760 // peepconstraint ( 0.dst == 1.dst );
12761 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12762 // %}
12763 //
12764 // peephole %{
12765 // peepmatch ( addP_eReg_imm movP );
12766 // peepconstraint ( 0.dst == 1.dst );
12767 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12768 // %}
12769
12770 // // Change load of spilled value to only a spill
12771 // instruct storeI(memory mem, rRegI src) %{
12772 // match(Set mem (StoreI mem src));
12773 // %}
12774 //
12775 // instruct loadI(rRegI dst, memory mem) %{
12776 // match(Set dst (LoadI mem));
12777 // %}
12778 //
12779 peephole %{
12780 peepmatch ( loadI storeI );
12781 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12782 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12783 %}
12784
12785 //----------SMARTSPILL RULES---------------------------------------------------
12786 // These must follow all instruction definitions as they use the names
12787 // defined in the instructions definitions.