1 //
   2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
   3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4 //
   5 // This code is free software; you can redistribute it and/or modify it
   6 // under the terms of the GNU General Public License version 2 only, as
   7 // published by the Free Software Foundation.
   8 //
   9 // This code is distributed in the hope that it will be useful, but WITHOUT
  10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12 // version 2 for more details (a copy is included in the LICENSE file that
  13 // accompanied this code).
  14 //
  15 // You should have received a copy of the GNU General Public License version
  16 // 2 along with this work; if not, write to the Free Software Foundation,
  17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18 //
  19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20 // or visit www.oracle.com if you need additional information or have any
  21 // questions.
  22 //
  23 //
  24 
  25 // X86 Architecture Description File
  26 
  27 //----------REGISTER DEFINITION BLOCK------------------------------------------
  28 // This information is used by the matcher and the register allocator to
  29 // describe individual registers and classes of registers within the target
  30 // archtecture.
  31 
  32 register %{
  33 //----------Architecture Description Register Definitions----------------------
  34 // General Registers
  35 // "reg_def"  name ( register save type, C convention save type,
  36 //                   ideal register type, encoding );
  37 // Register Save Types:
  38 //
  39 // NS  = No-Save:       The register allocator assumes that these registers
  40 //                      can be used without saving upon entry to the method, &
  41 //                      that they do not need to be saved at call sites.
  42 //
  43 // SOC = Save-On-Call:  The register allocator assumes that these registers
  44 //                      can be used without saving upon entry to the method,
  45 //                      but that they must be saved at call sites.
  46 //
  47 // SOE = Save-On-Entry: The register allocator assumes that these registers
  48 //                      must be saved before using them upon entry to the
  49 //                      method, but they do not need to be saved at call
  50 //                      sites.
  51 //
  52 // AS  = Always-Save:   The register allocator assumes that these registers
  53 //                      must be saved before using them upon entry to the
  54 //                      method, & that they must be saved at call sites.
  55 //
  56 // Ideal Register Type is used to determine how to save & restore a
  57 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  58 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
  59 //
  60 // The encoding number is the actual bit-pattern placed into the opcodes.
  61 
  62 // General Registers
  63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
  64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
  65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
  66 
  67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
  68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
  69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
  70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
  71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
  72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
  73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
  74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
  75 reg_def ESP( NS,  NS, Op_RegI, 4, rsp->as_VMReg());
  76 
  77 // Float registers.  We treat TOS/FPR0 special.  It is invisible to the
  78 // allocator, and only shows up in the encodings.
  79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
  80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
  81 // Ok so here's the trick FPR1 is really st(0) except in the midst
  82 // of emission of assembly for a machnode. During the emission the fpu stack
  83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
  84 // the stack will not have this element so FPR1 == st(0) from the
  85 // oopMap viewpoint. This same weirdness with numbering causes
  86 // instruction encoding to have to play games with the register
  87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
  88 // where it does flt->flt moves to see an example
  89 //
  90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
  91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
  92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
  93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
  94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
  95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
  96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
  97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
  98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
  99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
 100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
 101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
 102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
 103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
 104 
 105 // Specify priority of register selection within phases of register
 106 // allocation.  Highest priority is first.  A useful heuristic is to
 107 // give registers a low priority when they are required by machine
 108 // instructions, like EAX and EDX.  Registers which are used as
 109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
 110 // For the Intel integer registers, the equivalent Long pairs are
 111 // EDX:EAX, EBX:ECX, and EDI:EBP.
 112 alloc_class chunk0( ECX,   EBX,   EBP,   EDI,   EAX,   EDX,   ESI, ESP,
 113                     FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
 114                     FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
 115                     FPR6L, FPR6H, FPR7L, FPR7H );
 116 
 117 
 118 //----------Architecture Description Register Classes--------------------------
 119 // Several register classes are automatically defined based upon information in
 120 // this architecture description.
 121 // 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )
 122 // 2) reg_class compiler_method_oop_reg    ( /* as def'd in frame section */ )
 123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
 124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 125 //
 126 // Class for all registers
 127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
 128 // Class for general registers
 129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
 130 // Class for general registers which may be used for implicit null checks on win95
 131 // Also safe for use by tailjump. We don't want to allocate in rbp,
 132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
 133 // Class of "X" registers
 134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
 135 // Class of registers that can appear in an address with no offset.
 136 // EBP and ESP require an extra instruction byte for zero offset.
 137 // Used in fast-unlock
 138 reg_class p_reg(EDX, EDI, ESI, EBX);
 139 // Class for general registers not including ECX
 140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
 141 // Class for general registers not including EAX
 142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
 143 // Class for general registers not including EAX or EBX.
 144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
 145 // Class of EAX (for multiply and divide operations)
 146 reg_class eax_reg(EAX);
 147 // Class of EBX (for atomic add)
 148 reg_class ebx_reg(EBX);
 149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
 150 reg_class ecx_reg(ECX);
 151 // Class of EDX (for multiply and divide operations)
 152 reg_class edx_reg(EDX);
 153 // Class of EDI (for synchronization)
 154 reg_class edi_reg(EDI);
 155 // Class of ESI (for synchronization)
 156 reg_class esi_reg(ESI);
 157 // Singleton class for interpreter's stack pointer
 158 reg_class ebp_reg(EBP);
 159 // Singleton class for stack pointer
 160 reg_class sp_reg(ESP);
 161 // Singleton class for instruction pointer
 162 // reg_class ip_reg(EIP);
 163 // Class of integer register pairs
 164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
 165 // Class of integer register pairs that aligns with calling convention
 166 reg_class eadx_reg( EAX,EDX );
 167 reg_class ebcx_reg( ECX,EBX );
 168 // Not AX or DX, used in divides
 169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
 170 
 171 // Floating point registers.  Notice FPR0 is not a choice.
 172 // FPR0 is not ever allocated; we use clever encodings to fake
 173 // a 2-address instructions out of Intels FP stack.
 174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
 175 
 176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
 177                       FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
 178                       FPR7L,FPR7H );
 179 
 180 reg_class fp_flt_reg0( FPR1L );
 181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
 182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
 183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
 184                           FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
 185 
 186 %}
 187 
 188 
 189 //----------SOURCE BLOCK-------------------------------------------------------
 190 // This is a block of C++ code which provides values, functions, and
 191 // definitions necessary in the rest of the architecture description
 192 source_hpp %{
 193 // Must be visible to the DFA in dfa_x86_32.cpp
 194 extern bool is_operand_hi32_zero(Node* n);
 195 %}
 196 
 197 source %{
 198 #define   RELOC_IMM32    Assembler::imm_operand
 199 #define   RELOC_DISP32   Assembler::disp32_operand
 200 
 201 #define __ _masm.
 202 
 203 // How to find the high register of a Long pair, given the low register
 204 #define   HIGH_FROM_LOW(x) ((x)+2)
 205 
 206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
 207 // instructions, to allow sign-masking or sign-bit flipping.  They allow
 208 // fast versions of NegF/NegD and AbsF/AbsD.
 209 
 210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
 211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
 212   // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
 213   // of 128-bits operands for SSE instructions.
 214   jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
 215   // Store the value to a 128-bits operand.
 216   operand[0] = lo;
 217   operand[1] = hi;
 218   return operand;
 219 }
 220 
 221 // Buffer for 128-bits masks used by SSE instructions.
 222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
 223 
 224 // Static initialization during VM startup.
 225 static jlong *float_signmask_pool  = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
 226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
 227 static jlong *float_signflip_pool  = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
 228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
 229 
 230 // Offset hacking within calls.
 231 static int pre_call_resets_size() {
 232   int size = 0;
 233   Compile* C = Compile::current();
 234   if (C->in_24_bit_fp_mode()) {
 235     size += 6; // fldcw
 236   }
 237   if (C->max_vector_size() > 16) {
 238     size += 3; // vzeroupper
 239   }
 240   return size;
 241 }
 242 
 243 static int preserve_SP_size() {
 244   return 2;  // op, rm(reg/reg)
 245 }
 246 
 247 // !!!!! Special hack to get all type of calls to specify the byte offset
 248 //       from the start of the call to the point where the return address
 249 //       will point.
 250 int MachCallStaticJavaNode::ret_addr_offset() {
 251   int offset = 5 + pre_call_resets_size();  // 5 bytes from start of call to where return address points
 252   if (_method_handle_invoke)
 253     offset += preserve_SP_size();
 254   return offset;
 255 }
 256 
 257 int MachCallDynamicJavaNode::ret_addr_offset() {
 258   return 10 + pre_call_resets_size();  // 10 bytes from start of call to where return address points
 259 }
 260 
 261 static int sizeof_FFree_Float_Stack_All = -1;
 262 
 263 int MachCallRuntimeNode::ret_addr_offset() {
 264   assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
 265   return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
 266 }
 267 
 268 // Indicate if the safepoint node needs the polling page as an input.
 269 // Since x86 does have absolute addressing, it doesn't.
 270 bool SafePointNode::needs_polling_address_input() {
 271   return false;
 272 }
 273 
 274 //
 275 // Compute padding required for nodes which need alignment
 276 //
 277 
 278 // The address of the call instruction needs to be 4-byte aligned to
 279 // ensure that it does not span a cache line so that it can be patched.
 280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
 281   current_offset += pre_call_resets_size();  // skip fldcw, if any
 282   current_offset += 1;      // skip call opcode byte
 283   return round_to(current_offset, alignment_required()) - current_offset;
 284 }
 285 
 286 // The address of the call instruction needs to be 4-byte aligned to
 287 // ensure that it does not span a cache line so that it can be patched.
 288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
 289   current_offset += pre_call_resets_size();  // skip fldcw, if any
 290   current_offset += preserve_SP_size();   // skip mov rbp, rsp
 291   current_offset += 1;      // skip call opcode byte
 292   return round_to(current_offset, alignment_required()) - current_offset;
 293 }
 294 
 295 // The address of the call instruction needs to be 4-byte aligned to
 296 // ensure that it does not span a cache line so that it can be patched.
 297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
 298   current_offset += pre_call_resets_size();  // skip fldcw, if any
 299   current_offset += 5;      // skip MOV instruction
 300   current_offset += 1;      // skip call opcode byte
 301   return round_to(current_offset, alignment_required()) - current_offset;
 302 }
 303 
 304 // EMIT_RM()
 305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
 306   unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
 307   cbuf.insts()->emit_int8(c);
 308 }
 309 
 310 // EMIT_CC()
 311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
 312   unsigned char c = (unsigned char)( f1 | f2 );
 313   cbuf.insts()->emit_int8(c);
 314 }
 315 
 316 // EMIT_OPCODE()
 317 void emit_opcode(CodeBuffer &cbuf, int code) {
 318   cbuf.insts()->emit_int8((unsigned char) code);
 319 }
 320 
 321 // EMIT_OPCODE() w/ relocation information
 322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
 323   cbuf.relocate(cbuf.insts_mark() + offset, reloc);
 324   emit_opcode(cbuf, code);
 325 }
 326 
 327 // EMIT_D8()
 328 void emit_d8(CodeBuffer &cbuf, int d8) {
 329   cbuf.insts()->emit_int8((unsigned char) d8);
 330 }
 331 
 332 // EMIT_D16()
 333 void emit_d16(CodeBuffer &cbuf, int d16) {
 334   cbuf.insts()->emit_int16(d16);
 335 }
 336 
 337 // EMIT_D32()
 338 void emit_d32(CodeBuffer &cbuf, int d32) {
 339   cbuf.insts()->emit_int32(d32);
 340 }
 341 
 342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
 343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
 344         int format) {
 345   cbuf.relocate(cbuf.insts_mark(), reloc, format);
 346   cbuf.insts()->emit_int32(d32);
 347 }
 348 
 349 // emit 32 bit value and construct relocation entry from RelocationHolder
 350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
 351         int format) {
 352 #ifdef ASSERT
 353   if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
 354     assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
 355   }
 356 #endif
 357   cbuf.relocate(cbuf.insts_mark(), rspec, format);
 358   cbuf.insts()->emit_int32(d32);
 359 }
 360 
 361 // Access stack slot for load or store
 362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
 363   emit_opcode( cbuf, opcode );               // (e.g., FILD   [ESP+src])
 364   if( -128 <= disp && disp <= 127 ) {
 365     emit_rm( cbuf, 0x01, rm_field, ESP_enc );  // R/M byte
 366     emit_rm( cbuf, 0x00, ESP_enc, ESP_enc);    // SIB byte
 367     emit_d8 (cbuf, disp);     // Displacement  // R/M byte
 368   } else {
 369     emit_rm( cbuf, 0x02, rm_field, ESP_enc );  // R/M byte
 370     emit_rm( cbuf, 0x00, ESP_enc, ESP_enc);    // SIB byte
 371     emit_d32(cbuf, disp);     // Displacement  // R/M byte
 372   }
 373 }
 374 
 375    // rRegI ereg, memory mem) %{    // emit_reg_mem
 376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) {
 377   // There is no index & no scale, use form without SIB byte
 378   if ((index == 0x4) &&
 379       (scale == 0) && (base != ESP_enc)) {
 380     // If no displacement, mode is 0x0; unless base is [EBP]
 381     if ( (displace == 0) && (base != EBP_enc) ) {
 382       emit_rm(cbuf, 0x0, reg_encoding, base);
 383     }
 384     else {                    // If 8-bit displacement, mode 0x1
 385       if ((displace >= -128) && (displace <= 127)
 386           && (disp_reloc == relocInfo::none) ) {
 387         emit_rm(cbuf, 0x1, reg_encoding, base);
 388         emit_d8(cbuf, displace);
 389       }
 390       else {                  // If 32-bit displacement
 391         if (base == -1) { // Special flag for absolute address
 392           emit_rm(cbuf, 0x0, reg_encoding, 0x5);
 393           // (manual lies; no SIB needed here)
 394           if ( disp_reloc != relocInfo::none ) {
 395             emit_d32_reloc(cbuf, displace, disp_reloc, 1);
 396           } else {
 397             emit_d32      (cbuf, displace);
 398           }
 399         }
 400         else {                // Normal base + offset
 401           emit_rm(cbuf, 0x2, reg_encoding, base);
 402           if ( disp_reloc != relocInfo::none ) {
 403             emit_d32_reloc(cbuf, displace, disp_reloc, 1);
 404           } else {
 405             emit_d32      (cbuf, displace);
 406           }
 407         }
 408       }
 409     }
 410   }
 411   else {                      // Else, encode with the SIB byte
 412     // If no displacement, mode is 0x0; unless base is [EBP]
 413     if (displace == 0 && (base != EBP_enc)) {  // If no displacement
 414       emit_rm(cbuf, 0x0, reg_encoding, 0x4);
 415       emit_rm(cbuf, scale, index, base);
 416     }
 417     else {                    // If 8-bit displacement, mode 0x1
 418       if ((displace >= -128) && (displace <= 127)
 419           && (disp_reloc == relocInfo::none) ) {
 420         emit_rm(cbuf, 0x1, reg_encoding, 0x4);
 421         emit_rm(cbuf, scale, index, base);
 422         emit_d8(cbuf, displace);
 423       }
 424       else {                  // If 32-bit displacement
 425         if (base == 0x04 ) {
 426           emit_rm(cbuf, 0x2, reg_encoding, 0x4);
 427           emit_rm(cbuf, scale, index, 0x04);
 428         } else {
 429           emit_rm(cbuf, 0x2, reg_encoding, 0x4);
 430           emit_rm(cbuf, scale, index, base);
 431         }
 432         if ( disp_reloc != relocInfo::none ) {
 433           emit_d32_reloc(cbuf, displace, disp_reloc, 1);
 434         } else {
 435           emit_d32      (cbuf, displace);
 436         }
 437       }
 438     }
 439   }
 440 }
 441 
 442 
 443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
 444   if( dst_encoding == src_encoding ) {
 445     // reg-reg copy, use an empty encoding
 446   } else {
 447     emit_opcode( cbuf, 0x8B );
 448     emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
 449   }
 450 }
 451 
 452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
 453   Label exit;
 454   __ jccb(Assembler::noParity, exit);
 455   __ pushf();
 456   //
 457   // comiss/ucomiss instructions set ZF,PF,CF flags and
 458   // zero OF,AF,SF for NaN values.
 459   // Fixup flags by zeroing ZF,PF so that compare of NaN
 460   // values returns 'less than' result (CF is set).
 461   // Leave the rest of flags unchanged.
 462   //
 463   //    7 6 5 4 3 2 1 0
 464   //   |S|Z|r|A|r|P|r|C|  (r - reserved bit)
 465   //    0 0 1 0 1 0 1 1   (0x2B)
 466   //
 467   __ andl(Address(rsp, 0), 0xffffff2b);
 468   __ popf();
 469   __ bind(exit);
 470 }
 471 
 472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
 473   Label done;
 474   __ movl(dst, -1);
 475   __ jcc(Assembler::parity, done);
 476   __ jcc(Assembler::below, done);
 477   __ setb(Assembler::notEqual, dst);
 478   __ movzbl(dst, dst);
 479   __ bind(done);
 480 }
 481 
 482 
 483 //=============================================================================
 484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
 485 
 486 int Compile::ConstantTable::calculate_table_base_offset() const {
 487   return 0;  // absolute addressing, no offset
 488 }
 489 
 490 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
 491 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
 492   ShouldNotReachHere();
 493 }
 494 
 495 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
 496   // Empty encoding
 497 }
 498 
 499 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
 500   return 0;
 501 }
 502 
 503 #ifndef PRODUCT
 504 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 505   st->print("# MachConstantBaseNode (empty encoding)");
 506 }
 507 #endif
 508 
 509 
 510 //=============================================================================
 511 #ifndef PRODUCT
 512 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 513   Compile* C = ra_->C;
 514 
 515   int framesize = C->frame_slots() << LogBytesPerInt;
 516   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 517   // Remove wordSize for return addr which is already pushed.
 518   framesize -= wordSize;
 519 
 520   if (C->need_stack_bang(framesize)) {
 521     framesize -= wordSize;
 522     st->print("# stack bang");
 523     st->print("\n\t");
 524     st->print("PUSH   EBP\t# Save EBP");
 525     if (framesize) {
 526       st->print("\n\t");
 527       st->print("SUB    ESP, #%d\t# Create frame",framesize);
 528     }
 529   } else {
 530     st->print("SUB    ESP, #%d\t# Create frame",framesize);
 531     st->print("\n\t");
 532     framesize -= wordSize;
 533     st->print("MOV    [ESP + #%d], EBP\t# Save EBP",framesize);
 534   }
 535 
 536   if (VerifyStackAtCalls) {
 537     st->print("\n\t");
 538     framesize -= wordSize;
 539     st->print("MOV    [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
 540   }
 541 
 542   if( C->in_24_bit_fp_mode() ) {
 543     st->print("\n\t");
 544     st->print("FLDCW  \t# load 24 bit fpu control word");
 545   }
 546   if (UseSSE >= 2 && VerifyFPU) {
 547     st->print("\n\t");
 548     st->print("# verify FPU stack (must be clean on entry)");
 549   }
 550 
 551 #ifdef ASSERT
 552   if (VerifyStackAtCalls) {
 553     st->print("\n\t");
 554     st->print("# stack alignment check");
 555   }
 556 #endif
 557   st->cr();
 558 }
 559 #endif
 560 
 561 
 562 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 563   Compile* C = ra_->C;
 564   MacroAssembler _masm(&cbuf);
 565 
 566   int framesize = C->frame_slots() << LogBytesPerInt;
 567 
 568   __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
 569 
 570   C->set_frame_complete(cbuf.insts_size());
 571 
 572   if (C->has_mach_constant_base_node()) {
 573     // NOTE: We set the table base offset here because users might be
 574     // emitted before MachConstantBaseNode.
 575     Compile::ConstantTable& constant_table = C->constant_table();
 576     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
 577   }
 578 }
 579 
 580 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
 581   return MachNode::size(ra_); // too many variables; just compute it the hard way
 582 }
 583 
 584 int MachPrologNode::reloc() const {
 585   return 0; // a large enough number
 586 }
 587 
 588 //=============================================================================
 589 #ifndef PRODUCT
 590 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
 591   Compile *C = ra_->C;
 592   int framesize = C->frame_slots() << LogBytesPerInt;
 593   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 594   // Remove two words for return addr and rbp,
 595   framesize -= 2*wordSize;
 596 
 597   if (C->max_vector_size() > 16) {
 598     st->print("VZEROUPPER");
 599     st->cr(); st->print("\t");
 600   }
 601   if (C->in_24_bit_fp_mode()) {
 602     st->print("FLDCW  standard control word");
 603     st->cr(); st->print("\t");
 604   }
 605   if (framesize) {
 606     st->print("ADD    ESP,%d\t# Destroy frame",framesize);
 607     st->cr(); st->print("\t");
 608   }
 609   st->print_cr("POPL   EBP"); st->print("\t");
 610   if (do_polling() && C->is_method_compilation()) {
 611     st->print("TEST   PollPage,EAX\t! Poll Safepoint");
 612     st->cr(); st->print("\t");
 613   }
 614 }
 615 #endif
 616 
 617 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 618   Compile *C = ra_->C;
 619 
 620   if (C->max_vector_size() > 16) {
 621     // Clear upper bits of YMM registers when current compiled code uses
 622     // wide vectors to avoid AVX <-> SSE transition penalty during call.
 623     MacroAssembler masm(&cbuf);
 624     masm.vzeroupper();
 625   }
 626   // If method set FPU control word, restore to standard control word
 627   if (C->in_24_bit_fp_mode()) {
 628     MacroAssembler masm(&cbuf);
 629     masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
 630   }
 631 
 632   int framesize = C->frame_slots() << LogBytesPerInt;
 633   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 634   // Remove two words for return addr and rbp,
 635   framesize -= 2*wordSize;
 636 
 637   // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
 638 
 639   if (framesize >= 128) {
 640     emit_opcode(cbuf, 0x81); // add  SP, #framesize
 641     emit_rm(cbuf, 0x3, 0x00, ESP_enc);
 642     emit_d32(cbuf, framesize);
 643   } else if (framesize) {
 644     emit_opcode(cbuf, 0x83); // add  SP, #framesize
 645     emit_rm(cbuf, 0x3, 0x00, ESP_enc);
 646     emit_d8(cbuf, framesize);
 647   }
 648 
 649   emit_opcode(cbuf, 0x58 | EBP_enc);
 650 
 651   if (do_polling() && C->is_method_compilation()) {
 652     cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
 653     emit_opcode(cbuf,0x85);
 654     emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
 655     emit_d32(cbuf, (intptr_t)os::get_polling_page());
 656   }
 657 }
 658 
 659 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
 660   Compile *C = ra_->C;
 661   // If method set FPU control word, restore to standard control word
 662   int size = C->in_24_bit_fp_mode() ? 6 : 0;
 663   if (C->max_vector_size() > 16) size += 3; // vzeroupper
 664   if (do_polling() && C->is_method_compilation()) size += 6;
 665 
 666   int framesize = C->frame_slots() << LogBytesPerInt;
 667   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 668   // Remove two words for return addr and rbp,
 669   framesize -= 2*wordSize;
 670 
 671   size++; // popl rbp,
 672 
 673   if (framesize >= 128) {
 674     size += 6;
 675   } else {
 676     size += framesize ? 3 : 0;
 677   }
 678   return size;
 679 }
 680 
 681 int MachEpilogNode::reloc() const {
 682   return 0; // a large enough number
 683 }
 684 
 685 const Pipeline * MachEpilogNode::pipeline() const {
 686   return MachNode::pipeline_class();
 687 }
 688 
 689 int MachEpilogNode::safepoint_offset() const { return 0; }
 690 
 691 //=============================================================================
 692 
 693 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
 694 static enum RC rc_class( OptoReg::Name reg ) {
 695 
 696   if( !OptoReg::is_valid(reg)  ) return rc_bad;
 697   if (OptoReg::is_stack(reg)) return rc_stack;
 698 
 699   VMReg r = OptoReg::as_VMReg(reg);
 700   if (r->is_Register()) return rc_int;
 701   if (r->is_FloatRegister()) {
 702     assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
 703     return rc_float;
 704   }
 705   assert(r->is_XMMRegister(), "must be");
 706   return rc_xmm;
 707 }
 708 
 709 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
 710                         int opcode, const char *op_str, int size, outputStream* st ) {
 711   if( cbuf ) {
 712     emit_opcode  (*cbuf, opcode );
 713     encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none);
 714 #ifndef PRODUCT
 715   } else if( !do_size ) {
 716     if( size != 0 ) st->print("\n\t");
 717     if( opcode == 0x8B || opcode == 0x89 ) { // MOV
 718       if( is_load ) st->print("%s   %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
 719       else          st->print("%s   [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
 720     } else { // FLD, FST, PUSH, POP
 721       st->print("%s [ESP + #%d]",op_str,offset);
 722     }
 723 #endif
 724   }
 725   int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
 726   return size+3+offset_size;
 727 }
 728 
 729 // Helper for XMM registers.  Extra opcode bits, limited syntax.
 730 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
 731                          int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
 732   if (cbuf) {
 733     MacroAssembler _masm(cbuf);
 734     if (reg_lo+1 == reg_hi) { // double move?
 735       if (is_load) {
 736         __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
 737       } else {
 738         __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
 739       }
 740     } else {
 741       if (is_load) {
 742         __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
 743       } else {
 744         __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
 745       }
 746     }
 747 #ifndef PRODUCT
 748   } else if (!do_size) {
 749     if (size != 0) st->print("\n\t");
 750     if (reg_lo+1 == reg_hi) { // double move?
 751       if (is_load) st->print("%s %s,[ESP + #%d]",
 752                               UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
 753                               Matcher::regName[reg_lo], offset);
 754       else         st->print("MOVSD  [ESP + #%d],%s",
 755                               offset, Matcher::regName[reg_lo]);
 756     } else {
 757       if (is_load) st->print("MOVSS  %s,[ESP + #%d]",
 758                               Matcher::regName[reg_lo], offset);
 759       else         st->print("MOVSS  [ESP + #%d],%s",
 760                               offset, Matcher::regName[reg_lo]);
 761     }
 762 #endif
 763   }
 764   int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
 765   // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
 766   return size+5+offset_size;
 767 }
 768 
 769 
 770 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
 771                             int src_hi, int dst_hi, int size, outputStream* st ) {
 772   if (cbuf) {
 773     MacroAssembler _masm(cbuf);
 774     if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
 775       __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
 776                 as_XMMRegister(Matcher::_regEncode[src_lo]));
 777     } else {
 778       __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
 779                 as_XMMRegister(Matcher::_regEncode[src_lo]));
 780     }
 781 #ifndef PRODUCT
 782   } else if (!do_size) {
 783     if (size != 0) st->print("\n\t");
 784     if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
 785       if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
 786         st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
 787       } else {
 788         st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
 789       }
 790     } else {
 791       if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
 792         st->print("MOVSD  %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
 793       } else {
 794         st->print("MOVSS  %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
 795       }
 796     }
 797 #endif
 798   }
 799   // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
 800   // Only MOVAPS SSE prefix uses 1 byte.
 801   int sz = 4;
 802   if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
 803       UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
 804   return size + sz;
 805 }
 806 
 807 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
 808                             int src_hi, int dst_hi, int size, outputStream* st ) {
 809   // 32-bit
 810   if (cbuf) {
 811     MacroAssembler _masm(cbuf);
 812     __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
 813              as_Register(Matcher::_regEncode[src_lo]));
 814 #ifndef PRODUCT
 815   } else if (!do_size) {
 816     st->print("movdl   %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
 817 #endif
 818   }
 819   return 4;
 820 }
 821 
 822 
 823 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
 824                                  int src_hi, int dst_hi, int size, outputStream* st ) {
 825   // 32-bit
 826   if (cbuf) {
 827     MacroAssembler _masm(cbuf);
 828     __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
 829              as_XMMRegister(Matcher::_regEncode[src_lo]));
 830 #ifndef PRODUCT
 831   } else if (!do_size) {
 832     st->print("movdl   %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
 833 #endif
 834   }
 835   return 4;
 836 }
 837 
 838 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
 839   if( cbuf ) {
 840     emit_opcode(*cbuf, 0x8B );
 841     emit_rm    (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
 842 #ifndef PRODUCT
 843   } else if( !do_size ) {
 844     if( size != 0 ) st->print("\n\t");
 845     st->print("MOV    %s,%s",Matcher::regName[dst],Matcher::regName[src]);
 846 #endif
 847   }
 848   return size+2;
 849 }
 850 
 851 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
 852                                  int offset, int size, outputStream* st ) {
 853   if( src_lo != FPR1L_num ) {      // Move value to top of FP stack, if not already there
 854     if( cbuf ) {
 855       emit_opcode( *cbuf, 0xD9 );  // FLD (i.e., push it)
 856       emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
 857 #ifndef PRODUCT
 858     } else if( !do_size ) {
 859       if( size != 0 ) st->print("\n\t");
 860       st->print("FLD    %s",Matcher::regName[src_lo]);
 861 #endif
 862     }
 863     size += 2;
 864   }
 865 
 866   int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
 867   const char *op_str;
 868   int op;
 869   if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
 870     op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
 871     op = 0xDD;
 872   } else {                   // 32-bit store
 873     op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
 874     op = 0xD9;
 875     assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
 876   }
 877 
 878   return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
 879 }
 880 
 881 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
 882 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
 883                           int src_hi, int dst_hi, uint ireg, outputStream* st);
 884 
 885 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
 886                             int stack_offset, int reg, uint ireg, outputStream* st);
 887 
 888 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
 889                                      int dst_offset, uint ireg, outputStream* st) {
 890   int calc_size = 0;
 891   int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
 892   int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
 893   switch (ireg) {
 894   case Op_VecS:
 895     calc_size = 3+src_offset_size + 3+dst_offset_size;
 896     break;
 897   case Op_VecD:
 898     calc_size = 3+src_offset_size + 3+dst_offset_size;
 899     src_offset += 4;
 900     dst_offset += 4;
 901     src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
 902     dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
 903     calc_size += 3+src_offset_size + 3+dst_offset_size;
 904     break;
 905   case Op_VecX:
 906     calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
 907     break;
 908   case Op_VecY:
 909     calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
 910     break;
 911   default:
 912     ShouldNotReachHere();
 913   }
 914   if (cbuf) {
 915     MacroAssembler _masm(cbuf);
 916     int offset = __ offset();
 917     switch (ireg) {
 918     case Op_VecS:
 919       __ pushl(Address(rsp, src_offset));
 920       __ popl (Address(rsp, dst_offset));
 921       break;
 922     case Op_VecD:
 923       __ pushl(Address(rsp, src_offset));
 924       __ popl (Address(rsp, dst_offset));
 925       __ pushl(Address(rsp, src_offset+4));
 926       __ popl (Address(rsp, dst_offset+4));
 927       break;
 928     case Op_VecX:
 929       __ movdqu(Address(rsp, -16), xmm0);
 930       __ movdqu(xmm0, Address(rsp, src_offset));
 931       __ movdqu(Address(rsp, dst_offset), xmm0);
 932       __ movdqu(xmm0, Address(rsp, -16));
 933       break;
 934     case Op_VecY:
 935       __ vmovdqu(Address(rsp, -32), xmm0);
 936       __ vmovdqu(xmm0, Address(rsp, src_offset));
 937       __ vmovdqu(Address(rsp, dst_offset), xmm0);
 938       __ vmovdqu(xmm0, Address(rsp, -32));
 939       break;
 940     default:
 941       ShouldNotReachHere();
 942     }
 943     int size = __ offset() - offset;
 944     assert(size == calc_size, "incorrect size calculattion");
 945     return size;
 946 #ifndef PRODUCT
 947   } else if (!do_size) {
 948     switch (ireg) {
 949     case Op_VecS:
 950       st->print("pushl   [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
 951                 "popl    [rsp + #%d]",
 952                 src_offset, dst_offset);
 953       break;
 954     case Op_VecD:
 955       st->print("pushl   [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
 956                 "popq    [rsp + #%d]\n\t"
 957                 "pushl   [rsp + #%d]\n\t"
 958                 "popq    [rsp + #%d]",
 959                 src_offset, dst_offset, src_offset+4, dst_offset+4);
 960       break;
 961      case Op_VecX:
 962       st->print("movdqu  [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
 963                 "movdqu  xmm0, [rsp + #%d]\n\t"
 964                 "movdqu  [rsp + #%d], xmm0\n\t"
 965                 "movdqu  xmm0, [rsp - #16]",
 966                 src_offset, dst_offset);
 967       break;
 968     case Op_VecY:
 969       st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
 970                 "vmovdqu xmm0, [rsp + #%d]\n\t"
 971                 "vmovdqu [rsp + #%d], xmm0\n\t"
 972                 "vmovdqu xmm0, [rsp - #32]",
 973                 src_offset, dst_offset);
 974       break;
 975     default:
 976       ShouldNotReachHere();
 977     }
 978 #endif
 979   }
 980   return calc_size;
 981 }
 982 
 983 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
 984   // Get registers to move
 985   OptoReg::Name src_second = ra_->get_reg_second(in(1));
 986   OptoReg::Name src_first = ra_->get_reg_first(in(1));
 987   OptoReg::Name dst_second = ra_->get_reg_second(this );
 988   OptoReg::Name dst_first = ra_->get_reg_first(this );
 989 
 990   enum RC src_second_rc = rc_class(src_second);
 991   enum RC src_first_rc = rc_class(src_first);
 992   enum RC dst_second_rc = rc_class(dst_second);
 993   enum RC dst_first_rc = rc_class(dst_first);
 994 
 995   assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
 996 
 997   // Generate spill code!
 998   int size = 0;
 999 
1000   if( src_first == dst_first && src_second == dst_second )
1001     return size;            // Self copy, no move
1002 
1003   if (bottom_type()->isa_vect() != NULL) {
1004     uint ireg = ideal_reg();
1005     assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1006     assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1007     assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1008     if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1009       // mem -> mem
1010       int src_offset = ra_->reg2offset(src_first);
1011       int dst_offset = ra_->reg2offset(dst_first);
1012       return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1013     } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1014       return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1015     } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1016       int stack_offset = ra_->reg2offset(dst_first);
1017       return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1018     } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1019       int stack_offset = ra_->reg2offset(src_first);
1020       return vec_spill_helper(cbuf, do_size, true,  stack_offset, dst_first, ireg, st);
1021     } else {
1022       ShouldNotReachHere();
1023     }
1024   }
1025 
1026   // --------------------------------------
1027   // Check for mem-mem move.  push/pop to move.
1028   if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1029     if( src_second == dst_first ) { // overlapping stack copy ranges
1030       assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1031       size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH  ",size, st);
1032       size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP   ",size, st);
1033       src_second_rc = dst_second_rc = rc_bad;  // flag as already moved the second bits
1034     }
1035     // move low bits
1036     size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH  ",size, st);
1037     size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP   ",size, st);
1038     if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1039       size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH  ",size, st);
1040       size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP   ",size, st);
1041     }
1042     return size;
1043   }
1044 
1045   // --------------------------------------
1046   // Check for integer reg-reg copy
1047   if( src_first_rc == rc_int && dst_first_rc == rc_int )
1048     size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1049 
1050   // Check for integer store
1051   if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1052     size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1053 
1054   // Check for integer load
1055   if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1056     size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1057 
1058   // Check for integer reg-xmm reg copy
1059   if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1060     assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1061             "no 64 bit integer-float reg moves" );
1062     return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1063   }
1064   // --------------------------------------
1065   // Check for float reg-reg copy
1066   if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1067     assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1068             (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1069     if( cbuf ) {
1070 
1071       // Note the mucking with the register encode to compensate for the 0/1
1072       // indexing issue mentioned in a comment in the reg_def sections
1073       // for FPR registers many lines above here.
1074 
1075       if( src_first != FPR1L_num ) {
1076         emit_opcode  (*cbuf, 0xD9 );           // FLD    ST(i)
1077         emit_d8      (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1078         emit_opcode  (*cbuf, 0xDD );           // FSTP   ST(i)
1079         emit_d8      (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1080      } else {
1081         emit_opcode  (*cbuf, 0xDD );           // FST    ST(i)
1082         emit_d8      (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1083      }
1084 #ifndef PRODUCT
1085     } else if( !do_size ) {
1086       if( size != 0 ) st->print("\n\t");
1087       if( src_first != FPR1L_num ) st->print("FLD    %s\n\tFSTP   %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1088       else                      st->print(             "FST    %s",                            Matcher::regName[dst_first]);
1089 #endif
1090     }
1091     return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1092   }
1093 
1094   // Check for float store
1095   if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1096     return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1097   }
1098 
1099   // Check for float load
1100   if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1101     int offset = ra_->reg2offset(src_first);
1102     const char *op_str;
1103     int op;
1104     if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1105       op_str = "FLD_D";
1106       op = 0xDD;
1107     } else {                   // 32-bit load
1108       op_str = "FLD_S";
1109       op = 0xD9;
1110       assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1111     }
1112     if( cbuf ) {
1113       emit_opcode  (*cbuf, op );
1114       encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none);
1115       emit_opcode  (*cbuf, 0xDD );           // FSTP   ST(i)
1116       emit_d8      (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1117 #ifndef PRODUCT
1118     } else if( !do_size ) {
1119       if( size != 0 ) st->print("\n\t");
1120       st->print("%s  ST,[ESP + #%d]\n\tFSTP   %s",op_str, offset,Matcher::regName[dst_first]);
1121 #endif
1122     }
1123     int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1124     return size + 3+offset_size+2;
1125   }
1126 
1127   // Check for xmm reg-reg copy
1128   if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1129     assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1130             (src_first+1 == src_second && dst_first+1 == dst_second),
1131             "no non-adjacent float-moves" );
1132     return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1133   }
1134 
1135   // Check for xmm reg-integer reg copy
1136   if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1137     assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1138             "no 64 bit float-integer reg moves" );
1139     return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1140   }
1141 
1142   // Check for xmm store
1143   if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1144     return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1145   }
1146 
1147   // Check for float xmm load
1148   if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1149     return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1150   }
1151 
1152   // Copy from float reg to xmm reg
1153   if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1154     // copy to the top of stack from floating point reg
1155     // and use LEA to preserve flags
1156     if( cbuf ) {
1157       emit_opcode(*cbuf,0x8D);  // LEA  ESP,[ESP-8]
1158       emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1159       emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1160       emit_d8(*cbuf,0xF8);
1161 #ifndef PRODUCT
1162     } else if( !do_size ) {
1163       if( size != 0 ) st->print("\n\t");
1164       st->print("LEA    ESP,[ESP-8]");
1165 #endif
1166     }
1167     size += 4;
1168 
1169     size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1170 
1171     // Copy from the temp memory to the xmm reg.
1172     size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1173 
1174     if( cbuf ) {
1175       emit_opcode(*cbuf,0x8D);  // LEA  ESP,[ESP+8]
1176       emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1177       emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1178       emit_d8(*cbuf,0x08);
1179 #ifndef PRODUCT
1180     } else if( !do_size ) {
1181       if( size != 0 ) st->print("\n\t");
1182       st->print("LEA    ESP,[ESP+8]");
1183 #endif
1184     }
1185     size += 4;
1186     return size;
1187   }
1188 
1189   assert( size > 0, "missed a case" );
1190 
1191   // --------------------------------------------------------------------
1192   // Check for second bits still needing moving.
1193   if( src_second == dst_second )
1194     return size;               // Self copy; no move
1195   assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1196 
1197   // Check for second word int-int move
1198   if( src_second_rc == rc_int && dst_second_rc == rc_int )
1199     return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1200 
1201   // Check for second word integer store
1202   if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1203     return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1204 
1205   // Check for second word integer load
1206   if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1207     return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1208 
1209 
1210   Unimplemented();
1211 }
1212 
1213 #ifndef PRODUCT
1214 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1215   implementation( NULL, ra_, false, st );
1216 }
1217 #endif
1218 
1219 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1220   implementation( &cbuf, ra_, false, NULL );
1221 }
1222 
1223 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1224   return implementation( NULL, ra_, true, NULL );
1225 }
1226 
1227 
1228 //=============================================================================
1229 #ifndef PRODUCT
1230 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1231   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1232   int reg = ra_->get_reg_first(this);
1233   st->print("LEA    %s,[ESP + #%d]",Matcher::regName[reg],offset);
1234 }
1235 #endif
1236 
1237 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1238   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1239   int reg = ra_->get_encode(this);
1240   if( offset >= 128 ) {
1241     emit_opcode(cbuf, 0x8D);      // LEA  reg,[SP+offset]
1242     emit_rm(cbuf, 0x2, reg, 0x04);
1243     emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1244     emit_d32(cbuf, offset);
1245   }
1246   else {
1247     emit_opcode(cbuf, 0x8D);      // LEA  reg,[SP+offset]
1248     emit_rm(cbuf, 0x1, reg, 0x04);
1249     emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1250     emit_d8(cbuf, offset);
1251   }
1252 }
1253 
1254 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1255   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1256   if( offset >= 128 ) {
1257     return 7;
1258   }
1259   else {
1260     return 4;
1261   }
1262 }
1263 
1264 //=============================================================================
1265 #ifndef PRODUCT
1266 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1267   st->print_cr(  "CMP    EAX,[ECX+4]\t# Inline cache check");
1268   st->print_cr("\tJNE    SharedRuntime::handle_ic_miss_stub");
1269   st->print_cr("\tNOP");
1270   st->print_cr("\tNOP");
1271   if( !OptoBreakpoint )
1272     st->print_cr("\tNOP");
1273 }
1274 #endif
1275 
1276 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1277   MacroAssembler masm(&cbuf);
1278 #ifdef ASSERT
1279   uint insts_size = cbuf.insts_size();
1280 #endif
1281   masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1282   masm.jump_cc(Assembler::notEqual,
1283                RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1284   /* WARNING these NOPs are critical so that verified entry point is properly
1285      aligned for patching by NativeJump::patch_verified_entry() */
1286   int nops_cnt = 2;
1287   if( !OptoBreakpoint ) // Leave space for int3
1288      nops_cnt += 1;
1289   masm.nop(nops_cnt);
1290 
1291   assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1292 }
1293 
1294 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1295   return OptoBreakpoint ? 11 : 12;
1296 }
1297 
1298 
1299 //=============================================================================
1300 uint size_exception_handler() {
1301   // NativeCall instruction size is the same as NativeJump.
1302   // exception handler starts out as jump and can be patched to
1303   // a call be deoptimization.  (4932387)
1304   // Note that this value is also credited (in output.cpp) to
1305   // the size of the code section.
1306   return NativeJump::instruction_size;
1307 }
1308 
1309 // Emit exception handler code.  Stuff framesize into a register
1310 // and call a VM stub routine.
1311 int emit_exception_handler(CodeBuffer& cbuf) {
1312 
1313   // Note that the code buffer's insts_mark is always relative to insts.
1314   // That's why we must use the macroassembler to generate a handler.
1315   MacroAssembler _masm(&cbuf);
1316   address base =
1317   __ start_a_stub(size_exception_handler());
1318   if (base == NULL)  return 0;  // CodeBuffer::expand failed
1319   int offset = __ offset();
1320   __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1321   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1322   __ end_a_stub();
1323   return offset;
1324 }
1325 
1326 uint size_deopt_handler() {
1327   // NativeCall instruction size is the same as NativeJump.
1328   // exception handler starts out as jump and can be patched to
1329   // a call be deoptimization.  (4932387)
1330   // Note that this value is also credited (in output.cpp) to
1331   // the size of the code section.
1332   return 5 + NativeJump::instruction_size; // pushl(); jmp;
1333 }
1334 
1335 // Emit deopt handler code.
1336 int emit_deopt_handler(CodeBuffer& cbuf) {
1337 
1338   // Note that the code buffer's insts_mark is always relative to insts.
1339   // That's why we must use the macroassembler to generate a handler.
1340   MacroAssembler _masm(&cbuf);
1341   address base =
1342   __ start_a_stub(size_exception_handler());
1343   if (base == NULL)  return 0;  // CodeBuffer::expand failed
1344   int offset = __ offset();
1345   InternalAddress here(__ pc());
1346   __ pushptr(here.addr());
1347 
1348   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1349   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1350   __ end_a_stub();
1351   return offset;
1352 }
1353 
1354 int Matcher::regnum_to_fpu_offset(int regnum) {
1355   return regnum - 32; // The FP registers are in the second chunk
1356 }
1357 
1358 // This is UltraSparc specific, true just means we have fast l2f conversion
1359 const bool Matcher::convL2FSupported(void) {
1360   return true;
1361 }
1362 
1363 // Is this branch offset short enough that a short branch can be used?
1364 //
1365 // NOTE: If the platform does not provide any short branch variants, then
1366 //       this method should return false for offset 0.
1367 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1368   // The passed offset is relative to address of the branch.
1369   // On 86 a branch displacement is calculated relative to address
1370   // of a next instruction.
1371   offset -= br_size;
1372 
1373   // the short version of jmpConUCF2 contains multiple branches,
1374   // making the reach slightly less
1375   if (rule == jmpConUCF2_rule)
1376     return (-126 <= offset && offset <= 125);
1377   return (-128 <= offset && offset <= 127);
1378 }
1379 
1380 const bool Matcher::isSimpleConstant64(jlong value) {
1381   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1382   return false;
1383 }
1384 
1385 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1386 const bool Matcher::init_array_count_is_in_bytes = false;
1387 
1388 // Threshold size for cleararray.
1389 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1390 
1391 // Needs 2 CMOV's for longs.
1392 const int Matcher::long_cmove_cost() { return 1; }
1393 
1394 // No CMOVF/CMOVD with SSE/SSE2
1395 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1396 
1397 // Does the CPU require late expand (see block.cpp for description of late expand)?
1398 const bool Matcher::require_postalloc_expand = false;
1399 
1400 // Should the Matcher clone shifts on addressing modes, expecting them to
1401 // be subsumed into complex addressing expressions or compute them into
1402 // registers?  True for Intel but false for most RISCs
1403 const bool Matcher::clone_shift_expressions = true;
1404 
1405 // Do we need to mask the count passed to shift instructions or does
1406 // the cpu only look at the lower 5/6 bits anyway?
1407 const bool Matcher::need_masked_shift_count = false;
1408 
1409 bool Matcher::narrow_oop_use_complex_address() {
1410   ShouldNotCallThis();
1411   return true;
1412 }
1413 
1414 bool Matcher::narrow_klass_use_complex_address() {
1415   ShouldNotCallThis();
1416   return true;
1417 }
1418 
1419 
1420 // Is it better to copy float constants, or load them directly from memory?
1421 // Intel can load a float constant from a direct address, requiring no
1422 // extra registers.  Most RISCs will have to materialize an address into a
1423 // register first, so they would do better to copy the constant from stack.
1424 const bool Matcher::rematerialize_float_constants = true;
1425 
1426 // If CPU can load and store mis-aligned doubles directly then no fixup is
1427 // needed.  Else we split the double into 2 integer pieces and move it
1428 // piece-by-piece.  Only happens when passing doubles into C code as the
1429 // Java calling convention forces doubles to be aligned.
1430 const bool Matcher::misaligned_doubles_ok = true;
1431 
1432 
1433 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1434   // Get the memory operand from the node
1435   uint numopnds = node->num_opnds();        // Virtual call for number of operands
1436   uint skipped  = node->oper_input_base();  // Sum of leaves skipped so far
1437   assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1438   uint opcnt     = 1;                 // First operand
1439   uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1440   while( idx >= skipped+num_edges ) {
1441     skipped += num_edges;
1442     opcnt++;                          // Bump operand count
1443     assert( opcnt < numopnds, "Accessing non-existent operand" );
1444     num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1445   }
1446 
1447   MachOper *memory = node->_opnds[opcnt];
1448   MachOper *new_memory = NULL;
1449   switch (memory->opcode()) {
1450   case DIRECT:
1451   case INDOFFSET32X:
1452     // No transformation necessary.
1453     return;
1454   case INDIRECT:
1455     new_memory = new (C) indirect_win95_safeOper( );
1456     break;
1457   case INDOFFSET8:
1458     new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1459     break;
1460   case INDOFFSET32:
1461     new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1462     break;
1463   case INDINDEXOFFSET:
1464     new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1465     break;
1466   case INDINDEXSCALE:
1467     new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1468     break;
1469   case INDINDEXSCALEOFFSET:
1470     new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1471     break;
1472   case LOAD_LONG_INDIRECT:
1473   case LOAD_LONG_INDOFFSET32:
1474     // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1475     return;
1476   default:
1477     assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1478     return;
1479   }
1480   node->_opnds[opcnt] = new_memory;
1481 }
1482 
1483 // Advertise here if the CPU requires explicit rounding operations
1484 // to implement the UseStrictFP mode.
1485 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1486 
1487 // Are floats conerted to double when stored to stack during deoptimization?
1488 // On x32 it is stored with convertion only when FPU is used for floats.
1489 bool Matcher::float_in_double() { return (UseSSE == 0); }
1490 
1491 // Do ints take an entire long register or just half?
1492 const bool Matcher::int_in_long = false;
1493 
1494 // Return whether or not this register is ever used as an argument.  This
1495 // function is used on startup to build the trampoline stubs in generateOptoStub.
1496 // Registers not mentioned will be killed by the VM call in the trampoline, and
1497 // arguments in those registers not be available to the callee.
1498 bool Matcher::can_be_java_arg( int reg ) {
1499   if(  reg == ECX_num   || reg == EDX_num   ) return true;
1500   if( (reg == XMM0_num  || reg == XMM1_num ) && UseSSE>=1 ) return true;
1501   if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1502   return false;
1503 }
1504 
1505 bool Matcher::is_spillable_arg( int reg ) {
1506   return can_be_java_arg(reg);
1507 }
1508 
1509 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1510   // Use hardware integer DIV instruction when
1511   // it is faster than a code which use multiply.
1512   // Only when constant divisor fits into 32 bit
1513   // (min_jint is excluded to get only correct
1514   // positive 32 bit values from negative).
1515   return VM_Version::has_fast_idiv() &&
1516          (divisor == (int)divisor && divisor != min_jint);
1517 }
1518 
1519 // Register for DIVI projection of divmodI
1520 RegMask Matcher::divI_proj_mask() {
1521   return EAX_REG_mask();
1522 }
1523 
1524 // Register for MODI projection of divmodI
1525 RegMask Matcher::modI_proj_mask() {
1526   return EDX_REG_mask();
1527 }
1528 
1529 // Register for DIVL projection of divmodL
1530 RegMask Matcher::divL_proj_mask() {
1531   ShouldNotReachHere();
1532   return RegMask();
1533 }
1534 
1535 // Register for MODL projection of divmodL
1536 RegMask Matcher::modL_proj_mask() {
1537   ShouldNotReachHere();
1538   return RegMask();
1539 }
1540 
1541 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1542   return EBP_REG_mask();
1543 }
1544 
1545 const RegMask Matcher::mathExactI_result_proj_mask() {
1546   return EAX_REG_mask();
1547 }
1548 
1549 const RegMask Matcher::mathExactL_result_proj_mask() {
1550   ShouldNotReachHere();
1551   return RegMask();
1552 }
1553 
1554 const RegMask Matcher::mathExactI_flags_proj_mask() {
1555   return INT_FLAGS_mask();
1556 }
1557 
1558 // Returns true if the high 32 bits of the value is known to be zero.
1559 bool is_operand_hi32_zero(Node* n) {
1560   int opc = n->Opcode();
1561   if (opc == Op_AndL) {
1562     Node* o2 = n->in(2);
1563     if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1564       return true;
1565     }
1566   }
1567   if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1568     return true;
1569   }
1570   return false;
1571 }
1572 
1573 %}
1574 
1575 //----------ENCODING BLOCK-----------------------------------------------------
1576 // This block specifies the encoding classes used by the compiler to output
1577 // byte streams.  Encoding classes generate functions which are called by
1578 // Machine Instruction Nodes in order to generate the bit encoding of the
1579 // instruction.  Operands specify their base encoding interface with the
1580 // interface keyword.  There are currently supported four interfaces,
1581 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an
1582 // operand to generate a function which returns its register number when
1583 // queried.   CONST_INTER causes an operand to generate a function which
1584 // returns the value of the constant when queried.  MEMORY_INTER causes an
1585 // operand to generate four functions which return the Base Register, the
1586 // Index Register, the Scale Value, and the Offset Value of the operand when
1587 // queried.  COND_INTER causes an operand to generate six functions which
1588 // return the encoding code (ie - encoding bits for the instruction)
1589 // associated with each basic boolean condition for a conditional instruction.
1590 // Instructions specify two basic values for encoding.  They use the
1591 // ins_encode keyword to specify their encoding class (which must be one of
1592 // the class names specified in the encoding block), and they use the
1593 // opcode keyword to specify, in order, their primary, secondary, and
1594 // tertiary opcode.  Only the opcode sections which a particular instruction
1595 // needs for encoding need to be specified.
1596 encode %{
1597   // Build emit functions for each basic byte or larger field in the intel
1598   // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1599   // code in the enc_class source block.  Emit functions will live in the
1600   // main source block for now.  In future, we can generalize this by
1601   // adding a syntax that specifies the sizes of fields in an order,
1602   // so that the adlc can build the emit functions automagically
1603 
1604   // Emit primary opcode
1605   enc_class OpcP %{
1606     emit_opcode(cbuf, $primary);
1607   %}
1608 
1609   // Emit secondary opcode
1610   enc_class OpcS %{
1611     emit_opcode(cbuf, $secondary);
1612   %}
1613 
1614   // Emit opcode directly
1615   enc_class Opcode(immI d8) %{
1616     emit_opcode(cbuf, $d8$$constant);
1617   %}
1618 
1619   enc_class SizePrefix %{
1620     emit_opcode(cbuf,0x66);
1621   %}
1622 
1623   enc_class RegReg (rRegI dst, rRegI src) %{    // RegReg(Many)
1624     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1625   %}
1626 
1627   enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{    // OpcRegReg(Many)
1628     emit_opcode(cbuf,$opcode$$constant);
1629     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1630   %}
1631 
1632   enc_class mov_r32_imm0( rRegI dst ) %{
1633     emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd   -- MOV r32  ,imm32
1634     emit_d32   ( cbuf, 0x0  );             //                         imm32==0x0
1635   %}
1636 
1637   enc_class cdq_enc %{
1638     // Full implementation of Java idiv and irem; checks for
1639     // special case as described in JVM spec., p.243 & p.271.
1640     //
1641     //         normal case                           special case
1642     //
1643     // input : rax,: dividend                         min_int
1644     //         reg: divisor                          -1
1645     //
1646     // output: rax,: quotient  (= rax, idiv reg)       min_int
1647     //         rdx: remainder (= rax, irem reg)       0
1648     //
1649     //  Code sequnce:
1650     //
1651     //  81 F8 00 00 00 80    cmp         rax,80000000h
1652     //  0F 85 0B 00 00 00    jne         normal_case
1653     //  33 D2                xor         rdx,edx
1654     //  83 F9 FF             cmp         rcx,0FFh
1655     //  0F 84 03 00 00 00    je          done
1656     //                  normal_case:
1657     //  99                   cdq
1658     //  F7 F9                idiv        rax,ecx
1659     //                  done:
1660     //
1661     emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1662     emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1663     emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80);                     // cmp rax,80000000h
1664     emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1665     emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1666     emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);                     // jne normal_case
1667     emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2);                     // xor rdx,edx
1668     emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1669     emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1670     emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1671     emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);                     // je done
1672     // normal_case:
1673     emit_opcode(cbuf,0x99);                                         // cdq
1674     // idiv (note: must be emitted by the user of this rule)
1675     // normal:
1676   %}
1677 
1678   // Dense encoding for older common ops
1679   enc_class Opc_plus(immI opcode, rRegI reg) %{
1680     emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1681   %}
1682 
1683 
1684   // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1685   enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1686     // Check for 8-bit immediate, and set sign extend bit in opcode
1687     if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1688       emit_opcode(cbuf, $primary | 0x02);
1689     }
1690     else {                          // If 32-bit immediate
1691       emit_opcode(cbuf, $primary);
1692     }
1693   %}
1694 
1695   enc_class OpcSErm (rRegI dst, immI imm) %{    // OpcSEr/m
1696     // Emit primary opcode and set sign-extend bit
1697     // Check for 8-bit immediate, and set sign extend bit in opcode
1698     if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1699       emit_opcode(cbuf, $primary | 0x02);    }
1700     else {                          // If 32-bit immediate
1701       emit_opcode(cbuf, $primary);
1702     }
1703     // Emit r/m byte with secondary opcode, after primary opcode.
1704     emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1705   %}
1706 
1707   enc_class Con8or32 (immI imm) %{    // Con8or32(storeImmI), 8 or 32 bits
1708     // Check for 8-bit immediate, and set sign extend bit in opcode
1709     if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1710       $$$emit8$imm$$constant;
1711     }
1712     else {                          // If 32-bit immediate
1713       // Output immediate
1714       $$$emit32$imm$$constant;
1715     }
1716   %}
1717 
1718   enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1719     // Emit primary opcode and set sign-extend bit
1720     // Check for 8-bit immediate, and set sign extend bit in opcode
1721     int con = (int)$imm$$constant; // Throw away top bits
1722     emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1723     // Emit r/m byte with secondary opcode, after primary opcode.
1724     emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1725     if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1726     else                               emit_d32(cbuf,con);
1727   %}
1728 
1729   enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1730     // Emit primary opcode and set sign-extend bit
1731     // Check for 8-bit immediate, and set sign extend bit in opcode
1732     int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1733     emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1734     // Emit r/m byte with tertiary opcode, after primary opcode.
1735     emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1736     if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1737     else                               emit_d32(cbuf,con);
1738   %}
1739 
1740   enc_class OpcSReg (rRegI dst) %{    // BSWAP
1741     emit_cc(cbuf, $secondary, $dst$$reg );
1742   %}
1743 
1744   enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1745     int destlo = $dst$$reg;
1746     int desthi = HIGH_FROM_LOW(destlo);
1747     // bswap lo
1748     emit_opcode(cbuf, 0x0F);
1749     emit_cc(cbuf, 0xC8, destlo);
1750     // bswap hi
1751     emit_opcode(cbuf, 0x0F);
1752     emit_cc(cbuf, 0xC8, desthi);
1753     // xchg lo and hi
1754     emit_opcode(cbuf, 0x87);
1755     emit_rm(cbuf, 0x3, destlo, desthi);
1756   %}
1757 
1758   enc_class RegOpc (rRegI div) %{    // IDIV, IMOD, JMP indirect, ...
1759     emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1760   %}
1761 
1762   enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1763     $$$emit8$primary;
1764     emit_cc(cbuf, $secondary, $cop$$cmpcode);
1765   %}
1766 
1767   enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1768     int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1769     emit_d8(cbuf, op >> 8 );
1770     emit_d8(cbuf, op & 255);
1771   %}
1772 
1773   // emulate a CMOV with a conditional branch around a MOV
1774   enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1775     // Invert sense of branch from sense of CMOV
1776     emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1777     emit_d8( cbuf, $brOffs$$constant );
1778   %}
1779 
1780   enc_class enc_PartialSubtypeCheck( ) %{
1781     Register Redi = as_Register(EDI_enc); // result register
1782     Register Reax = as_Register(EAX_enc); // super class
1783     Register Recx = as_Register(ECX_enc); // killed
1784     Register Resi = as_Register(ESI_enc); // sub class
1785     Label miss;
1786 
1787     MacroAssembler _masm(&cbuf);
1788     __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1789                                      NULL, &miss,
1790                                      /*set_cond_codes:*/ true);
1791     if ($primary) {
1792       __ xorptr(Redi, Redi);
1793     }
1794     __ bind(miss);
1795   %}
1796 
1797   enc_class FFree_Float_Stack_All %{    // Free_Float_Stack_All
1798     MacroAssembler masm(&cbuf);
1799     int start = masm.offset();
1800     if (UseSSE >= 2) {
1801       if (VerifyFPU) {
1802         masm.verify_FPU(0, "must be empty in SSE2+ mode");
1803       }
1804     } else {
1805       // External c_calling_convention expects the FPU stack to be 'clean'.
1806       // Compiled code leaves it dirty.  Do cleanup now.
1807       masm.empty_FPU_stack();
1808     }
1809     if (sizeof_FFree_Float_Stack_All == -1) {
1810       sizeof_FFree_Float_Stack_All = masm.offset() - start;
1811     } else {
1812       assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1813     }
1814   %}
1815 
1816   enc_class Verify_FPU_For_Leaf %{
1817     if( VerifyFPU ) {
1818       MacroAssembler masm(&cbuf);
1819       masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1820     }
1821   %}
1822 
1823   enc_class Java_To_Runtime (method meth) %{    // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1824     // This is the instruction starting address for relocation info.
1825     cbuf.set_insts_mark();
1826     $$$emit8$primary;
1827     // CALL directly to the runtime
1828     emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1829                 runtime_call_Relocation::spec(), RELOC_IMM32 );
1830 
1831     if (UseSSE >= 2) {
1832       MacroAssembler _masm(&cbuf);
1833       BasicType rt = tf()->return_type();
1834 
1835       if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1836         // A C runtime call where the return value is unused.  In SSE2+
1837         // mode the result needs to be removed from the FPU stack.  It's
1838         // likely that this function call could be removed by the
1839         // optimizer if the C function is a pure function.
1840         __ ffree(0);
1841       } else if (rt == T_FLOAT) {
1842         __ lea(rsp, Address(rsp, -4));
1843         __ fstp_s(Address(rsp, 0));
1844         __ movflt(xmm0, Address(rsp, 0));
1845         __ lea(rsp, Address(rsp,  4));
1846       } else if (rt == T_DOUBLE) {
1847         __ lea(rsp, Address(rsp, -8));
1848         __ fstp_d(Address(rsp, 0));
1849         __ movdbl(xmm0, Address(rsp, 0));
1850         __ lea(rsp, Address(rsp,  8));
1851       }
1852     }
1853   %}
1854 
1855 
1856   enc_class pre_call_resets %{
1857     // If method sets FPU control word restore it here
1858     debug_only(int off0 = cbuf.insts_size());
1859     if (ra_->C->in_24_bit_fp_mode()) {
1860       MacroAssembler _masm(&cbuf);
1861       __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1862     }
1863     if (ra_->C->max_vector_size() > 16) {
1864       // Clear upper bits of YMM registers when current compiled code uses
1865       // wide vectors to avoid AVX <-> SSE transition penalty during call.
1866       MacroAssembler _masm(&cbuf);
1867       __ vzeroupper();
1868     }
1869     debug_only(int off1 = cbuf.insts_size());
1870     assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1871   %}
1872 
1873   enc_class post_call_FPU %{
1874     // If method sets FPU control word do it here also
1875     if (Compile::current()->in_24_bit_fp_mode()) {
1876       MacroAssembler masm(&cbuf);
1877       masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1878     }
1879   %}
1880 
1881   enc_class Java_Static_Call (method meth) %{    // JAVA STATIC CALL
1882     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
1883     // who we intended to call.
1884     cbuf.set_insts_mark();
1885     $$$emit8$primary;
1886     if (!_method) {
1887       emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1888                      runtime_call_Relocation::spec(), RELOC_IMM32 );
1889     } else if (_optimized_virtual) {
1890       emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1891                      opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1892     } else {
1893       emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1894                      static_call_Relocation::spec(), RELOC_IMM32 );
1895     }
1896     if (_method) {  // Emit stub for static call.
1897       CompiledStaticCall::emit_to_interp_stub(cbuf);
1898     }
1899   %}
1900 
1901   enc_class Java_Dynamic_Call (method meth) %{    // JAVA DYNAMIC CALL
1902     MacroAssembler _masm(&cbuf);
1903     __ ic_call((address)$meth$$method);
1904   %}
1905 
1906   enc_class Java_Compiled_Call (method meth) %{    // JAVA COMPILED CALL
1907     int disp = in_bytes(Method::from_compiled_offset());
1908     assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1909 
1910     // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())]
1911     cbuf.set_insts_mark();
1912     $$$emit8$primary;
1913     emit_rm(cbuf, 0x01, $secondary, EAX_enc );  // R/M byte
1914     emit_d8(cbuf, disp);             // Displacement
1915 
1916   %}
1917 
1918 //   Following encoding is no longer used, but may be restored if calling
1919 //   convention changes significantly.
1920 //   Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1921 //
1922 //   enc_class Java_Interpreter_Call (label labl) %{    // JAVA INTERPRETER CALL
1923 //     // int ic_reg     = Matcher::inline_cache_reg();
1924 //     // int ic_encode  = Matcher::_regEncode[ic_reg];
1925 //     // int imo_reg    = Matcher::interpreter_method_oop_reg();
1926 //     // int imo_encode = Matcher::_regEncode[imo_reg];
1927 //
1928 //     // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1929 //     // // so we load it immediately before the call
1930 //     // emit_opcode(cbuf, 0x8B);                     // MOV    imo_reg,ic_reg  # method_oop
1931 //     // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1932 //
1933 //     // xor rbp,ebp
1934 //     emit_opcode(cbuf, 0x33);
1935 //     emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1936 //
1937 //     // CALL to interpreter.
1938 //     cbuf.set_insts_mark();
1939 //     $$$emit8$primary;
1940 //     emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1941 //                 runtime_call_Relocation::spec(), RELOC_IMM32 );
1942 //   %}
1943 
1944   enc_class RegOpcImm (rRegI dst, immI8 shift) %{    // SHL, SAR, SHR
1945     $$$emit8$primary;
1946     emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1947     $$$emit8$shift$$constant;
1948   %}
1949 
1950   enc_class LdImmI (rRegI dst, immI src) %{    // Load Immediate
1951     // Load immediate does not have a zero or sign extended version
1952     // for 8-bit immediates
1953     emit_opcode(cbuf, 0xB8 + $dst$$reg);
1954     $$$emit32$src$$constant;
1955   %}
1956 
1957   enc_class LdImmP (rRegI dst, immI src) %{    // Load Immediate
1958     // Load immediate does not have a zero or sign extended version
1959     // for 8-bit immediates
1960     emit_opcode(cbuf, $primary + $dst$$reg);
1961     $$$emit32$src$$constant;
1962   %}
1963 
1964   enc_class LdImmL_Lo( eRegL dst, immL src) %{    // Load Immediate
1965     // Load immediate does not have a zero or sign extended version
1966     // for 8-bit immediates
1967     int dst_enc = $dst$$reg;
1968     int src_con = $src$$constant & 0x0FFFFFFFFL;
1969     if (src_con == 0) {
1970       // xor dst, dst
1971       emit_opcode(cbuf, 0x33);
1972       emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1973     } else {
1974       emit_opcode(cbuf, $primary + dst_enc);
1975       emit_d32(cbuf, src_con);
1976     }
1977   %}
1978 
1979   enc_class LdImmL_Hi( eRegL dst, immL src) %{    // Load Immediate
1980     // Load immediate does not have a zero or sign extended version
1981     // for 8-bit immediates
1982     int dst_enc = $dst$$reg + 2;
1983     int src_con = ((julong)($src$$constant)) >> 32;
1984     if (src_con == 0) {
1985       // xor dst, dst
1986       emit_opcode(cbuf, 0x33);
1987       emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1988     } else {
1989       emit_opcode(cbuf, $primary + dst_enc);
1990       emit_d32(cbuf, src_con);
1991     }
1992   %}
1993 
1994 
1995   // Encode a reg-reg copy.  If it is useless, then empty encoding.
1996   enc_class enc_Copy( rRegI dst, rRegI src ) %{
1997     encode_Copy( cbuf, $dst$$reg, $src$$reg );
1998   %}
1999 
2000   enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
2001     encode_Copy( cbuf, $dst$$reg, $src$$reg );
2002   %}
2003 
2004   enc_class RegReg (rRegI dst, rRegI src) %{    // RegReg(Many)
2005     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2006   %}
2007 
2008   enc_class RegReg_Lo(eRegL dst, eRegL src) %{    // RegReg(Many)
2009     $$$emit8$primary;
2010     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2011   %}
2012 
2013   enc_class RegReg_Hi(eRegL dst, eRegL src) %{    // RegReg(Many)
2014     $$$emit8$secondary;
2015     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2016   %}
2017 
2018   enc_class RegReg_Lo2(eRegL dst, eRegL src) %{    // RegReg(Many)
2019     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2020   %}
2021 
2022   enc_class RegReg_Hi2(eRegL dst, eRegL src) %{    // RegReg(Many)
2023     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2024   %}
2025 
2026   enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2027     emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2028   %}
2029 
2030   enc_class Con32 (immI src) %{    // Con32(storeImmI)
2031     // Output immediate
2032     $$$emit32$src$$constant;
2033   %}
2034 
2035   enc_class Con32FPR_as_bits(immFPR src) %{        // storeF_imm
2036     // Output Float immediate bits
2037     jfloat jf = $src$$constant;
2038     int    jf_as_bits = jint_cast( jf );
2039     emit_d32(cbuf, jf_as_bits);
2040   %}
2041 
2042   enc_class Con32F_as_bits(immF src) %{      // storeX_imm
2043     // Output Float immediate bits
2044     jfloat jf = $src$$constant;
2045     int    jf_as_bits = jint_cast( jf );
2046     emit_d32(cbuf, jf_as_bits);
2047   %}
2048 
2049   enc_class Con16 (immI src) %{    // Con16(storeImmI)
2050     // Output immediate
2051     $$$emit16$src$$constant;
2052   %}
2053 
2054   enc_class Con_d32(immI src) %{
2055     emit_d32(cbuf,$src$$constant);
2056   %}
2057 
2058   enc_class conmemref (eRegP t1) %{    // Con32(storeImmI)
2059     // Output immediate memory reference
2060     emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2061     emit_d32(cbuf, 0x00);
2062   %}
2063 
2064   enc_class lock_prefix( ) %{
2065     if( os::is_MP() )
2066       emit_opcode(cbuf,0xF0);         // [Lock]
2067   %}
2068 
2069   // Cmp-xchg long value.
2070   // Note: we need to swap rbx, and rcx before and after the
2071   //       cmpxchg8 instruction because the instruction uses
2072   //       rcx as the high order word of the new value to store but
2073   //       our register encoding uses rbx,.
2074   enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2075 
2076     // XCHG  rbx,ecx
2077     emit_opcode(cbuf,0x87);
2078     emit_opcode(cbuf,0xD9);
2079     // [Lock]
2080     if( os::is_MP() )
2081       emit_opcode(cbuf,0xF0);
2082     // CMPXCHG8 [Eptr]
2083     emit_opcode(cbuf,0x0F);
2084     emit_opcode(cbuf,0xC7);
2085     emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2086     // XCHG  rbx,ecx
2087     emit_opcode(cbuf,0x87);
2088     emit_opcode(cbuf,0xD9);
2089   %}
2090 
2091   enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2092     // [Lock]
2093     if( os::is_MP() )
2094       emit_opcode(cbuf,0xF0);
2095 
2096     // CMPXCHG [Eptr]
2097     emit_opcode(cbuf,0x0F);
2098     emit_opcode(cbuf,0xB1);
2099     emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2100   %}
2101 
2102   enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2103     int res_encoding = $res$$reg;
2104 
2105     // MOV  res,0
2106     emit_opcode( cbuf, 0xB8 + res_encoding);
2107     emit_d32( cbuf, 0 );
2108     // JNE,s  fail
2109     emit_opcode(cbuf,0x75);
2110     emit_d8(cbuf, 5 );
2111     // MOV  res,1
2112     emit_opcode( cbuf, 0xB8 + res_encoding);
2113     emit_d32( cbuf, 1 );
2114     // fail:
2115   %}
2116 
2117   enc_class set_instruction_start( ) %{
2118     cbuf.set_insts_mark();            // Mark start of opcode for reloc info in mem operand
2119   %}
2120 
2121   enc_class RegMem (rRegI ereg, memory mem) %{    // emit_reg_mem
2122     int reg_encoding = $ereg$$reg;
2123     int base  = $mem$$base;
2124     int index = $mem$$index;
2125     int scale = $mem$$scale;
2126     int displace = $mem$$disp;
2127     relocInfo::relocType disp_reloc = $mem->disp_reloc();
2128     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2129   %}
2130 
2131   enc_class RegMem_Hi(eRegL ereg, memory mem) %{    // emit_reg_mem
2132     int reg_encoding = HIGH_FROM_LOW($ereg$$reg);  // Hi register of pair, computed from lo
2133     int base  = $mem$$base;
2134     int index = $mem$$index;
2135     int scale = $mem$$scale;
2136     int displace = $mem$$disp + 4;      // Offset is 4 further in memory
2137     assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" );
2138     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none);
2139   %}
2140 
2141   enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2142     int r1, r2;
2143     if( $tertiary == 0xA4 ) { r1 = $dst$$reg;  r2 = HIGH_FROM_LOW($dst$$reg); }
2144     else                    { r2 = $dst$$reg;  r1 = HIGH_FROM_LOW($dst$$reg); }
2145     emit_opcode(cbuf,0x0F);
2146     emit_opcode(cbuf,$tertiary);
2147     emit_rm(cbuf, 0x3, r1, r2);
2148     emit_d8(cbuf,$cnt$$constant);
2149     emit_d8(cbuf,$primary);
2150     emit_rm(cbuf, 0x3, $secondary, r1);
2151     emit_d8(cbuf,$cnt$$constant);
2152   %}
2153 
2154   enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2155     emit_opcode( cbuf, 0x8B ); // Move
2156     emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2157     if( $cnt$$constant > 32 ) { // Shift, if not by zero
2158       emit_d8(cbuf,$primary);
2159       emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2160       emit_d8(cbuf,$cnt$$constant-32);
2161     }
2162     emit_d8(cbuf,$primary);
2163     emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2164     emit_d8(cbuf,31);
2165   %}
2166 
2167   enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2168     int r1, r2;
2169     if( $secondary == 0x5 ) { r1 = $dst$$reg;  r2 = HIGH_FROM_LOW($dst$$reg); }
2170     else                    { r2 = $dst$$reg;  r1 = HIGH_FROM_LOW($dst$$reg); }
2171 
2172     emit_opcode( cbuf, 0x8B ); // Move r1,r2
2173     emit_rm(cbuf, 0x3, r1, r2);
2174     if( $cnt$$constant > 32 ) { // Shift, if not by zero
2175       emit_opcode(cbuf,$primary);
2176       emit_rm(cbuf, 0x3, $secondary, r1);
2177       emit_d8(cbuf,$cnt$$constant-32);
2178     }
2179     emit_opcode(cbuf,0x33);  // XOR r2,r2
2180     emit_rm(cbuf, 0x3, r2, r2);
2181   %}
2182 
2183   // Clone of RegMem but accepts an extra parameter to access each
2184   // half of a double in memory; it never needs relocation info.
2185   enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2186     emit_opcode(cbuf,$opcode$$constant);
2187     int reg_encoding = $rm_reg$$reg;
2188     int base     = $mem$$base;
2189     int index    = $mem$$index;
2190     int scale    = $mem$$scale;
2191     int displace = $mem$$disp + $disp_for_half$$constant;
2192     relocInfo::relocType disp_reloc = relocInfo::none;
2193     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2194   %}
2195 
2196   // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2197   //
2198   // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2199   // and it never needs relocation information.
2200   // Frequently used to move data between FPU's Stack Top and memory.
2201   enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2202     int rm_byte_opcode = $rm_opcode$$constant;
2203     int base     = $mem$$base;
2204     int index    = $mem$$index;
2205     int scale    = $mem$$scale;
2206     int displace = $mem$$disp;
2207     assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" );
2208     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none);
2209   %}
2210 
2211   enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2212     int rm_byte_opcode = $rm_opcode$$constant;
2213     int base     = $mem$$base;
2214     int index    = $mem$$index;
2215     int scale    = $mem$$scale;
2216     int displace = $mem$$disp;
2217     relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2218     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
2219   %}
2220 
2221   enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{    // emit_reg_lea
2222     int reg_encoding = $dst$$reg;
2223     int base         = $src0$$reg;      // 0xFFFFFFFF indicates no base
2224     int index        = 0x04;            // 0x04 indicates no index
2225     int scale        = 0x00;            // 0x00 indicates no scale
2226     int displace     = $src1$$constant; // 0x00 indicates no displacement
2227     relocInfo::relocType disp_reloc = relocInfo::none;
2228     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2229   %}
2230 
2231   enc_class min_enc (rRegI dst, rRegI src) %{    // MIN
2232     // Compare dst,src
2233     emit_opcode(cbuf,0x3B);
2234     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2235     // jmp dst < src around move
2236     emit_opcode(cbuf,0x7C);
2237     emit_d8(cbuf,2);
2238     // move dst,src
2239     emit_opcode(cbuf,0x8B);
2240     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2241   %}
2242 
2243   enc_class max_enc (rRegI dst, rRegI src) %{    // MAX
2244     // Compare dst,src
2245     emit_opcode(cbuf,0x3B);
2246     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2247     // jmp dst > src around move
2248     emit_opcode(cbuf,0x7F);
2249     emit_d8(cbuf,2);
2250     // move dst,src
2251     emit_opcode(cbuf,0x8B);
2252     emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2253   %}
2254 
2255   enc_class enc_FPR_store(memory mem, regDPR src) %{
2256     // If src is FPR1, we can just FST to store it.
2257     // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2258     int reg_encoding = 0x2; // Just store
2259     int base  = $mem$$base;
2260     int index = $mem$$index;
2261     int scale = $mem$$scale;
2262     int displace = $mem$$disp;
2263     relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
2264     if( $src$$reg != FPR1L_enc ) {
2265       reg_encoding = 0x3;  // Store & pop
2266       emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2267       emit_d8( cbuf, 0xC0-1+$src$$reg );
2268     }
2269     cbuf.set_insts_mark();       // Mark start of opcode for reloc info in mem operand
2270     emit_opcode(cbuf,$primary);
2271     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc);
2272   %}
2273 
2274   enc_class neg_reg(rRegI dst) %{
2275     // NEG $dst
2276     emit_opcode(cbuf,0xF7);
2277     emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2278   %}
2279 
2280   enc_class setLT_reg(eCXRegI dst) %{
2281     // SETLT $dst
2282     emit_opcode(cbuf,0x0F);
2283     emit_opcode(cbuf,0x9C);
2284     emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2285   %}
2286 
2287   enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{    // cadd_cmpLT
2288     int tmpReg = $tmp$$reg;
2289 
2290     // SUB $p,$q
2291     emit_opcode(cbuf,0x2B);
2292     emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2293     // SBB $tmp,$tmp
2294     emit_opcode(cbuf,0x1B);
2295     emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2296     // AND $tmp,$y
2297     emit_opcode(cbuf,0x23);
2298     emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2299     // ADD $p,$tmp
2300     emit_opcode(cbuf,0x03);
2301     emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2302   %}
2303 
2304   enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2305     // TEST shift,32
2306     emit_opcode(cbuf,0xF7);
2307     emit_rm(cbuf, 0x3, 0, ECX_enc);
2308     emit_d32(cbuf,0x20);
2309     // JEQ,s small
2310     emit_opcode(cbuf, 0x74);
2311     emit_d8(cbuf, 0x04);
2312     // MOV    $dst.hi,$dst.lo
2313     emit_opcode( cbuf, 0x8B );
2314     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2315     // CLR    $dst.lo
2316     emit_opcode(cbuf, 0x33);
2317     emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2318 // small:
2319     // SHLD   $dst.hi,$dst.lo,$shift
2320     emit_opcode(cbuf,0x0F);
2321     emit_opcode(cbuf,0xA5);
2322     emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2323     // SHL    $dst.lo,$shift"
2324     emit_opcode(cbuf,0xD3);
2325     emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2326   %}
2327 
2328   enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2329     // TEST shift,32
2330     emit_opcode(cbuf,0xF7);
2331     emit_rm(cbuf, 0x3, 0, ECX_enc);
2332     emit_d32(cbuf,0x20);
2333     // JEQ,s small
2334     emit_opcode(cbuf, 0x74);
2335     emit_d8(cbuf, 0x04);
2336     // MOV    $dst.lo,$dst.hi
2337     emit_opcode( cbuf, 0x8B );
2338     emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2339     // CLR    $dst.hi
2340     emit_opcode(cbuf, 0x33);
2341     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2342 // small:
2343     // SHRD   $dst.lo,$dst.hi,$shift
2344     emit_opcode(cbuf,0x0F);
2345     emit_opcode(cbuf,0xAD);
2346     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2347     // SHR    $dst.hi,$shift"
2348     emit_opcode(cbuf,0xD3);
2349     emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2350   %}
2351 
2352   enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2353     // TEST shift,32
2354     emit_opcode(cbuf,0xF7);
2355     emit_rm(cbuf, 0x3, 0, ECX_enc);
2356     emit_d32(cbuf,0x20);
2357     // JEQ,s small
2358     emit_opcode(cbuf, 0x74);
2359     emit_d8(cbuf, 0x05);
2360     // MOV    $dst.lo,$dst.hi
2361     emit_opcode( cbuf, 0x8B );
2362     emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2363     // SAR    $dst.hi,31
2364     emit_opcode(cbuf, 0xC1);
2365     emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2366     emit_d8(cbuf, 0x1F );
2367 // small:
2368     // SHRD   $dst.lo,$dst.hi,$shift
2369     emit_opcode(cbuf,0x0F);
2370     emit_opcode(cbuf,0xAD);
2371     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2372     // SAR    $dst.hi,$shift"
2373     emit_opcode(cbuf,0xD3);
2374     emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2375   %}
2376 
2377 
2378   // ----------------- Encodings for floating point unit -----------------
2379   // May leave result in FPU-TOS or FPU reg depending on opcodes
2380   enc_class OpcReg_FPR(regFPR src) %{    // FMUL, FDIV
2381     $$$emit8$primary;
2382     emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2383   %}
2384 
2385   // Pop argument in FPR0 with FSTP ST(0)
2386   enc_class PopFPU() %{
2387     emit_opcode( cbuf, 0xDD );
2388     emit_d8( cbuf, 0xD8 );
2389   %}
2390 
2391   // !!!!! equivalent to Pop_Reg_F
2392   enc_class Pop_Reg_DPR( regDPR dst ) %{
2393     emit_opcode( cbuf, 0xDD );           // FSTP   ST(i)
2394     emit_d8( cbuf, 0xD8+$dst$$reg );
2395   %}
2396 
2397   enc_class Push_Reg_DPR( regDPR dst ) %{
2398     emit_opcode( cbuf, 0xD9 );
2399     emit_d8( cbuf, 0xC0-1+$dst$$reg );   // FLD ST(i-1)
2400   %}
2401 
2402   enc_class strictfp_bias1( regDPR dst ) %{
2403     emit_opcode( cbuf, 0xDB );           // FLD m80real
2404     emit_opcode( cbuf, 0x2D );
2405     emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2406     emit_opcode( cbuf, 0xDE );           // FMULP ST(dst), ST0
2407     emit_opcode( cbuf, 0xC8+$dst$$reg );
2408   %}
2409 
2410   enc_class strictfp_bias2( regDPR dst ) %{
2411     emit_opcode( cbuf, 0xDB );           // FLD m80real
2412     emit_opcode( cbuf, 0x2D );
2413     emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2414     emit_opcode( cbuf, 0xDE );           // FMULP ST(dst), ST0
2415     emit_opcode( cbuf, 0xC8+$dst$$reg );
2416   %}
2417 
2418   // Special case for moving an integer register to a stack slot.
2419   enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2420     store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2421   %}
2422 
2423   // Special case for moving a register to a stack slot.
2424   enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2425     // Opcode already emitted
2426     emit_rm( cbuf, 0x02, $src$$reg, ESP_enc );   // R/M byte
2427     emit_rm( cbuf, 0x00, ESP_enc, ESP_enc);          // SIB byte
2428     emit_d32(cbuf, $dst$$disp);   // Displacement
2429   %}
2430 
2431   // Push the integer in stackSlot 'src' onto FP-stack
2432   enc_class Push_Mem_I( memory src ) %{    // FILD   [ESP+src]
2433     store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2434   %}
2435 
2436   // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2437   enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2438     store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2439   %}
2440 
2441   // Same as Pop_Mem_F except for opcode
2442   // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2443   enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2444     store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2445   %}
2446 
2447   enc_class Pop_Reg_FPR( regFPR dst ) %{
2448     emit_opcode( cbuf, 0xDD );           // FSTP   ST(i)
2449     emit_d8( cbuf, 0xD8+$dst$$reg );
2450   %}
2451 
2452   enc_class Push_Reg_FPR( regFPR dst ) %{
2453     emit_opcode( cbuf, 0xD9 );           // FLD    ST(i-1)
2454     emit_d8( cbuf, 0xC0-1+$dst$$reg );
2455   %}
2456 
2457   // Push FPU's float to a stack-slot, and pop FPU-stack
2458   enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2459     int pop = 0x02;
2460     if ($src$$reg != FPR1L_enc) {
2461       emit_opcode( cbuf, 0xD9 );         // FLD    ST(i-1)
2462       emit_d8( cbuf, 0xC0-1+$src$$reg );
2463       pop = 0x03;
2464     }
2465     store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S  [ESP+dst]
2466   %}
2467 
2468   // Push FPU's double to a stack-slot, and pop FPU-stack
2469   enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2470     int pop = 0x02;
2471     if ($src$$reg != FPR1L_enc) {
2472       emit_opcode( cbuf, 0xD9 );         // FLD    ST(i-1)
2473       emit_d8( cbuf, 0xC0-1+$src$$reg );
2474       pop = 0x03;
2475     }
2476     store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D  [ESP+dst]
2477   %}
2478 
2479   // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2480   enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2481     int pop = 0xD0 - 1; // -1 since we skip FLD
2482     if ($src$$reg != FPR1L_enc) {
2483       emit_opcode( cbuf, 0xD9 );         // FLD    ST(src-1)
2484       emit_d8( cbuf, 0xC0-1+$src$$reg );
2485       pop = 0xD8;
2486     }
2487     emit_opcode( cbuf, 0xDD );
2488     emit_d8( cbuf, pop+$dst$$reg );      // FST<P> ST(i)
2489   %}
2490 
2491 
2492   enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2493     // load dst in FPR0
2494     emit_opcode( cbuf, 0xD9 );
2495     emit_d8( cbuf, 0xC0-1+$dst$$reg );
2496     if ($src$$reg != FPR1L_enc) {
2497       // fincstp
2498       emit_opcode (cbuf, 0xD9);
2499       emit_opcode (cbuf, 0xF7);
2500       // swap src with FPR1:
2501       // FXCH FPR1 with src
2502       emit_opcode(cbuf, 0xD9);
2503       emit_d8(cbuf, 0xC8-1+$src$$reg );
2504       // fdecstp
2505       emit_opcode (cbuf, 0xD9);
2506       emit_opcode (cbuf, 0xF6);
2507     }
2508   %}
2509 
2510   enc_class Push_ModD_encoding(regD src0, regD src1) %{
2511     MacroAssembler _masm(&cbuf);
2512     __ subptr(rsp, 8);
2513     __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2514     __ fld_d(Address(rsp, 0));
2515     __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2516     __ fld_d(Address(rsp, 0));
2517   %}
2518 
2519   enc_class Push_ModF_encoding(regF src0, regF src1) %{
2520     MacroAssembler _masm(&cbuf);
2521     __ subptr(rsp, 4);
2522     __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2523     __ fld_s(Address(rsp, 0));
2524     __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2525     __ fld_s(Address(rsp, 0));
2526   %}
2527 
2528   enc_class Push_ResultD(regD dst) %{
2529     MacroAssembler _masm(&cbuf);
2530     __ fstp_d(Address(rsp, 0));
2531     __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2532     __ addptr(rsp, 8);
2533   %}
2534 
2535   enc_class Push_ResultF(regF dst, immI d8) %{
2536     MacroAssembler _masm(&cbuf);
2537     __ fstp_s(Address(rsp, 0));
2538     __ movflt($dst$$XMMRegister, Address(rsp, 0));
2539     __ addptr(rsp, $d8$$constant);
2540   %}
2541 
2542   enc_class Push_SrcD(regD src) %{
2543     MacroAssembler _masm(&cbuf);
2544     __ subptr(rsp, 8);
2545     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2546     __ fld_d(Address(rsp, 0));
2547   %}
2548 
2549   enc_class push_stack_temp_qword() %{
2550     MacroAssembler _masm(&cbuf);
2551     __ subptr(rsp, 8);
2552   %}
2553 
2554   enc_class pop_stack_temp_qword() %{
2555     MacroAssembler _masm(&cbuf);
2556     __ addptr(rsp, 8);
2557   %}
2558 
2559   enc_class push_xmm_to_fpr1(regD src) %{
2560     MacroAssembler _masm(&cbuf);
2561     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2562     __ fld_d(Address(rsp, 0));
2563   %}
2564 
2565   enc_class Push_Result_Mod_DPR( regDPR src) %{
2566     if ($src$$reg != FPR1L_enc) {
2567       // fincstp
2568       emit_opcode (cbuf, 0xD9);
2569       emit_opcode (cbuf, 0xF7);
2570       // FXCH FPR1 with src
2571       emit_opcode(cbuf, 0xD9);
2572       emit_d8(cbuf, 0xC8-1+$src$$reg );
2573       // fdecstp
2574       emit_opcode (cbuf, 0xD9);
2575       emit_opcode (cbuf, 0xF6);
2576     }
2577     // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2578     // // FSTP   FPR$dst$$reg
2579     // emit_opcode( cbuf, 0xDD );
2580     // emit_d8( cbuf, 0xD8+$dst$$reg );
2581   %}
2582 
2583   enc_class fnstsw_sahf_skip_parity() %{
2584     // fnstsw ax
2585     emit_opcode( cbuf, 0xDF );
2586     emit_opcode( cbuf, 0xE0 );
2587     // sahf
2588     emit_opcode( cbuf, 0x9E );
2589     // jnp  ::skip
2590     emit_opcode( cbuf, 0x7B );
2591     emit_opcode( cbuf, 0x05 );
2592   %}
2593 
2594   enc_class emitModDPR() %{
2595     // fprem must be iterative
2596     // :: loop
2597     // fprem
2598     emit_opcode( cbuf, 0xD9 );
2599     emit_opcode( cbuf, 0xF8 );
2600     // wait
2601     emit_opcode( cbuf, 0x9b );
2602     // fnstsw ax
2603     emit_opcode( cbuf, 0xDF );
2604     emit_opcode( cbuf, 0xE0 );
2605     // sahf
2606     emit_opcode( cbuf, 0x9E );
2607     // jp  ::loop
2608     emit_opcode( cbuf, 0x0F );
2609     emit_opcode( cbuf, 0x8A );
2610     emit_opcode( cbuf, 0xF4 );
2611     emit_opcode( cbuf, 0xFF );
2612     emit_opcode( cbuf, 0xFF );
2613     emit_opcode( cbuf, 0xFF );
2614   %}
2615 
2616   enc_class fpu_flags() %{
2617     // fnstsw_ax
2618     emit_opcode( cbuf, 0xDF);
2619     emit_opcode( cbuf, 0xE0);
2620     // test ax,0x0400
2621     emit_opcode( cbuf, 0x66 );   // operand-size prefix for 16-bit immediate
2622     emit_opcode( cbuf, 0xA9 );
2623     emit_d16   ( cbuf, 0x0400 );
2624     // // // This sequence works, but stalls for 12-16 cycles on PPro
2625     // // test rax,0x0400
2626     // emit_opcode( cbuf, 0xA9 );
2627     // emit_d32   ( cbuf, 0x00000400 );
2628     //
2629     // jz exit (no unordered comparison)
2630     emit_opcode( cbuf, 0x74 );
2631     emit_d8    ( cbuf, 0x02 );
2632     // mov ah,1 - treat as LT case (set carry flag)
2633     emit_opcode( cbuf, 0xB4 );
2634     emit_d8    ( cbuf, 0x01 );
2635     // sahf
2636     emit_opcode( cbuf, 0x9E);
2637   %}
2638 
2639   enc_class cmpF_P6_fixup() %{
2640     // Fixup the integer flags in case comparison involved a NaN
2641     //
2642     // JNP exit (no unordered comparison, P-flag is set by NaN)
2643     emit_opcode( cbuf, 0x7B );
2644     emit_d8    ( cbuf, 0x03 );
2645     // MOV AH,1 - treat as LT case (set carry flag)
2646     emit_opcode( cbuf, 0xB4 );
2647     emit_d8    ( cbuf, 0x01 );
2648     // SAHF
2649     emit_opcode( cbuf, 0x9E);
2650     // NOP     // target for branch to avoid branch to branch
2651     emit_opcode( cbuf, 0x90);
2652   %}
2653 
2654 //     fnstsw_ax();
2655 //     sahf();
2656 //     movl(dst, nan_result);
2657 //     jcc(Assembler::parity, exit);
2658 //     movl(dst, less_result);
2659 //     jcc(Assembler::below, exit);
2660 //     movl(dst, equal_result);
2661 //     jcc(Assembler::equal, exit);
2662 //     movl(dst, greater_result);
2663 
2664 // less_result     =  1;
2665 // greater_result  = -1;
2666 // equal_result    = 0;
2667 // nan_result      = -1;
2668 
2669   enc_class CmpF_Result(rRegI dst) %{
2670     // fnstsw_ax();
2671     emit_opcode( cbuf, 0xDF);
2672     emit_opcode( cbuf, 0xE0);
2673     // sahf
2674     emit_opcode( cbuf, 0x9E);
2675     // movl(dst, nan_result);
2676     emit_opcode( cbuf, 0xB8 + $dst$$reg);
2677     emit_d32( cbuf, -1 );
2678     // jcc(Assembler::parity, exit);
2679     emit_opcode( cbuf, 0x7A );
2680     emit_d8    ( cbuf, 0x13 );
2681     // movl(dst, less_result);
2682     emit_opcode( cbuf, 0xB8 + $dst$$reg);
2683     emit_d32( cbuf, -1 );
2684     // jcc(Assembler::below, exit);
2685     emit_opcode( cbuf, 0x72 );
2686     emit_d8    ( cbuf, 0x0C );
2687     // movl(dst, equal_result);
2688     emit_opcode( cbuf, 0xB8 + $dst$$reg);
2689     emit_d32( cbuf, 0 );
2690     // jcc(Assembler::equal, exit);
2691     emit_opcode( cbuf, 0x74 );
2692     emit_d8    ( cbuf, 0x05 );
2693     // movl(dst, greater_result);
2694     emit_opcode( cbuf, 0xB8 + $dst$$reg);
2695     emit_d32( cbuf, 1 );
2696   %}
2697 
2698 
2699   // Compare the longs and set flags
2700   // BROKEN!  Do Not use as-is
2701   enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2702     // CMP    $src1.hi,$src2.hi
2703     emit_opcode( cbuf, 0x3B );
2704     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2705     // JNE,s  done
2706     emit_opcode(cbuf,0x75);
2707     emit_d8(cbuf, 2 );
2708     // CMP    $src1.lo,$src2.lo
2709     emit_opcode( cbuf, 0x3B );
2710     emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2711 // done:
2712   %}
2713 
2714   enc_class convert_int_long( regL dst, rRegI src ) %{
2715     // mov $dst.lo,$src
2716     int dst_encoding = $dst$$reg;
2717     int src_encoding = $src$$reg;
2718     encode_Copy( cbuf, dst_encoding  , src_encoding );
2719     // mov $dst.hi,$src
2720     encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2721     // sar $dst.hi,31
2722     emit_opcode( cbuf, 0xC1 );
2723     emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2724     emit_d8(cbuf, 0x1F );
2725   %}
2726 
2727   enc_class convert_long_double( eRegL src ) %{
2728     // push $src.hi
2729     emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2730     // push $src.lo
2731     emit_opcode(cbuf, 0x50+$src$$reg  );
2732     // fild 64-bits at [SP]
2733     emit_opcode(cbuf,0xdf);
2734     emit_d8(cbuf, 0x6C);
2735     emit_d8(cbuf, 0x24);
2736     emit_d8(cbuf, 0x00);
2737     // pop stack
2738     emit_opcode(cbuf, 0x83); // add  SP, #8
2739     emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2740     emit_d8(cbuf, 0x8);
2741   %}
2742 
2743   enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2744     // IMUL   EDX:EAX,$src1
2745     emit_opcode( cbuf, 0xF7 );
2746     emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2747     // SAR    EDX,$cnt-32
2748     int shift_count = ((int)$cnt$$constant) - 32;
2749     if (shift_count > 0) {
2750       emit_opcode(cbuf, 0xC1);
2751       emit_rm(cbuf, 0x3, 7, $dst$$reg );
2752       emit_d8(cbuf, shift_count);
2753     }
2754   %}
2755 
2756   // this version doesn't have add sp, 8
2757   enc_class convert_long_double2( eRegL src ) %{
2758     // push $src.hi
2759     emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2760     // push $src.lo
2761     emit_opcode(cbuf, 0x50+$src$$reg  );
2762     // fild 64-bits at [SP]
2763     emit_opcode(cbuf,0xdf);
2764     emit_d8(cbuf, 0x6C);
2765     emit_d8(cbuf, 0x24);
2766     emit_d8(cbuf, 0x00);
2767   %}
2768 
2769   enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2770     // Basic idea: long = (long)int * (long)int
2771     // IMUL EDX:EAX, src
2772     emit_opcode( cbuf, 0xF7 );
2773     emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2774   %}
2775 
2776   enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2777     // Basic Idea:  long = (int & 0xffffffffL) * (int & 0xffffffffL)
2778     // MUL EDX:EAX, src
2779     emit_opcode( cbuf, 0xF7 );
2780     emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2781   %}
2782 
2783   enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2784     // Basic idea: lo(result) = lo(x_lo * y_lo)
2785     //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2786     // MOV    $tmp,$src.lo
2787     encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2788     // IMUL   $tmp,EDX
2789     emit_opcode( cbuf, 0x0F );
2790     emit_opcode( cbuf, 0xAF );
2791     emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2792     // MOV    EDX,$src.hi
2793     encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2794     // IMUL   EDX,EAX
2795     emit_opcode( cbuf, 0x0F );
2796     emit_opcode( cbuf, 0xAF );
2797     emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2798     // ADD    $tmp,EDX
2799     emit_opcode( cbuf, 0x03 );
2800     emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2801     // MUL   EDX:EAX,$src.lo
2802     emit_opcode( cbuf, 0xF7 );
2803     emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2804     // ADD    EDX,ESI
2805     emit_opcode( cbuf, 0x03 );
2806     emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2807   %}
2808 
2809   enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2810     // Basic idea: lo(result) = lo(src * y_lo)
2811     //             hi(result) = hi(src * y_lo) + lo(src * y_hi)
2812     // IMUL   $tmp,EDX,$src
2813     emit_opcode( cbuf, 0x6B );
2814     emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2815     emit_d8( cbuf, (int)$src$$constant );
2816     // MOV    EDX,$src
2817     emit_opcode(cbuf, 0xB8 + EDX_enc);
2818     emit_d32( cbuf, (int)$src$$constant );
2819     // MUL   EDX:EAX,EDX
2820     emit_opcode( cbuf, 0xF7 );
2821     emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2822     // ADD    EDX,ESI
2823     emit_opcode( cbuf, 0x03 );
2824     emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2825   %}
2826 
2827   enc_class long_div( eRegL src1, eRegL src2 ) %{
2828     // PUSH src1.hi
2829     emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2830     // PUSH src1.lo
2831     emit_opcode(cbuf,               0x50+$src1$$reg  );
2832     // PUSH src2.hi
2833     emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2834     // PUSH src2.lo
2835     emit_opcode(cbuf,               0x50+$src2$$reg  );
2836     // CALL directly to the runtime
2837     cbuf.set_insts_mark();
2838     emit_opcode(cbuf,0xE8);       // Call into runtime
2839     emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2840     // Restore stack
2841     emit_opcode(cbuf, 0x83); // add  SP, #framesize
2842     emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2843     emit_d8(cbuf, 4*4);
2844   %}
2845 
2846   enc_class long_mod( eRegL src1, eRegL src2 ) %{
2847     // PUSH src1.hi
2848     emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2849     // PUSH src1.lo
2850     emit_opcode(cbuf,               0x50+$src1$$reg  );
2851     // PUSH src2.hi
2852     emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2853     // PUSH src2.lo
2854     emit_opcode(cbuf,               0x50+$src2$$reg  );
2855     // CALL directly to the runtime
2856     cbuf.set_insts_mark();
2857     emit_opcode(cbuf,0xE8);       // Call into runtime
2858     emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2859     // Restore stack
2860     emit_opcode(cbuf, 0x83); // add  SP, #framesize
2861     emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2862     emit_d8(cbuf, 4*4);
2863   %}
2864 
2865   enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2866     // MOV   $tmp,$src.lo
2867     emit_opcode(cbuf, 0x8B);
2868     emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2869     // OR    $tmp,$src.hi
2870     emit_opcode(cbuf, 0x0B);
2871     emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2872   %}
2873 
2874   enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2875     // CMP    $src1.lo,$src2.lo
2876     emit_opcode( cbuf, 0x3B );
2877     emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2878     // JNE,s  skip
2879     emit_cc(cbuf, 0x70, 0x5);
2880     emit_d8(cbuf,2);
2881     // CMP    $src1.hi,$src2.hi
2882     emit_opcode( cbuf, 0x3B );
2883     emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2884   %}
2885 
2886   enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2887     // CMP    $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2888     emit_opcode( cbuf, 0x3B );
2889     emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2890     // MOV    $tmp,$src1.hi
2891     emit_opcode( cbuf, 0x8B );
2892     emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2893     // SBB   $tmp,$src2.hi\t! Compute flags for long compare
2894     emit_opcode( cbuf, 0x1B );
2895     emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2896   %}
2897 
2898   enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2899     // XOR    $tmp,$tmp
2900     emit_opcode(cbuf,0x33);  // XOR
2901     emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2902     // CMP    $tmp,$src.lo
2903     emit_opcode( cbuf, 0x3B );
2904     emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2905     // SBB    $tmp,$src.hi
2906     emit_opcode( cbuf, 0x1B );
2907     emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2908   %}
2909 
2910  // Sniff, sniff... smells like Gnu Superoptimizer
2911   enc_class neg_long( eRegL dst ) %{
2912     emit_opcode(cbuf,0xF7);    // NEG hi
2913     emit_rm    (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2914     emit_opcode(cbuf,0xF7);    // NEG lo
2915     emit_rm    (cbuf,0x3, 0x3,               $dst$$reg );
2916     emit_opcode(cbuf,0x83);    // SBB hi,0
2917     emit_rm    (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2918     emit_d8    (cbuf,0 );
2919   %}
2920 
2921 
2922   // Because the transitions from emitted code to the runtime
2923   // monitorenter/exit helper stubs are so slow it's critical that
2924   // we inline both the stack-locking fast-path and the inflated fast path.
2925   //
2926   // See also: cmpFastLock and cmpFastUnlock.
2927   //
2928   // What follows is a specialized inline transliteration of the code
2929   // in slow_enter() and slow_exit().  If we're concerned about I$ bloat
2930   // another option would be to emit TrySlowEnter and TrySlowExit methods
2931   // at startup-time.  These methods would accept arguments as
2932   // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2933   // indications in the icc.ZFlag.  Fast_Lock and Fast_Unlock would simply
2934   // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2935   // In practice, however, the # of lock sites is bounded and is usually small.
2936   // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2937   // if the processor uses simple bimodal branch predictors keyed by EIP
2938   // Since the helper routines would be called from multiple synchronization
2939   // sites.
2940   //
2941   // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2942   // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2943   // to those specialized methods.  That'd give us a mostly platform-independent
2944   // implementation that the JITs could optimize and inline at their pleasure.
2945   // Done correctly, the only time we'd need to cross to native could would be
2946   // to park() or unpark() threads.  We'd also need a few more unsafe operators
2947   // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2948   // (b) explicit barriers or fence operations.
2949   //
2950   // TODO:
2951   //
2952   // *  Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2953   //    This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2954   //    Given TLAB allocation, Self is usually manifested in a register, so passing it into
2955   //    the lock operators would typically be faster than reifying Self.
2956   //
2957   // *  Ideally I'd define the primitives as:
2958   //       fast_lock   (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2959   //       fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2960   //    Unfortunately ADLC bugs prevent us from expressing the ideal form.
2961   //    Instead, we're stuck with a rather awkward and brittle register assignments below.
2962   //    Furthermore the register assignments are overconstrained, possibly resulting in
2963   //    sub-optimal code near the synchronization site.
2964   //
2965   // *  Eliminate the sp-proximity tests and just use "== Self" tests instead.
2966   //    Alternately, use a better sp-proximity test.
2967   //
2968   // *  Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2969   //    Either one is sufficient to uniquely identify a thread.
2970   //    TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2971   //
2972   // *  Intrinsify notify() and notifyAll() for the common cases where the
2973   //    object is locked by the calling thread but the waitlist is empty.
2974   //    avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2975   //
2976   // *  use jccb and jmpb instead of jcc and jmp to improve code density.
2977   //    But beware of excessive branch density on AMD Opterons.
2978   //
2979   // *  Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2980   //    or failure of the fast-path.  If the fast-path fails then we pass
2981   //    control to the slow-path, typically in C.  In Fast_Lock and
2982   //    Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2983   //    will emit a conditional branch immediately after the node.
2984   //    So we have branches to branches and lots of ICC.ZF games.
2985   //    Instead, it might be better to have C2 pass a "FailureLabel"
2986   //    into Fast_Lock and Fast_Unlock.  In the case of success, control
2987   //    will drop through the node.  ICC.ZF is undefined at exit.
2988   //    In the case of failure, the node will branch directly to the
2989   //    FailureLabel
2990 
2991 
2992   // obj: object to lock
2993   // box: on-stack box address (displaced header location) - KILLED
2994   // rax,: tmp -- KILLED
2995   // scr: tmp -- KILLED
2996   enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
2997 
2998     Register objReg = as_Register($obj$$reg);
2999     Register boxReg = as_Register($box$$reg);
3000     Register tmpReg = as_Register($tmp$$reg);
3001     Register scrReg = as_Register($scr$$reg);
3002 
3003     // Ensure the register assignents are disjoint
3004     guarantee (objReg != boxReg, "") ;
3005     guarantee (objReg != tmpReg, "") ;
3006     guarantee (objReg != scrReg, "") ;
3007     guarantee (boxReg != tmpReg, "") ;
3008     guarantee (boxReg != scrReg, "") ;
3009     guarantee (tmpReg == as_Register(EAX_enc), "") ;
3010 
3011     MacroAssembler masm(&cbuf);
3012 
3013     if (_counters != NULL) {
3014       masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3015     }
3016     if (EmitSync & 1) {
3017         // set box->dhw = unused_mark (3)
3018         // Force all sync thru slow-path: slow_enter() and slow_exit() 
3019         masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;             
3020         masm.cmpptr (rsp, (int32_t)0) ;                        
3021     } else 
3022     if (EmitSync & 2) { 
3023         Label DONE_LABEL ;           
3024         if (UseBiasedLocking) {
3025            // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3026            masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3027         }
3028 
3029         masm.movptr(tmpReg, Address(objReg, 0)) ;          // fetch markword 
3030         masm.orptr (tmpReg, 0x1);
3031         masm.movptr(Address(boxReg, 0), tmpReg);           // Anticipate successful CAS 
3032         if (os::is_MP()) { masm.lock();  }
3033         masm.cmpxchgptr(boxReg, Address(objReg, 0));          // Updates tmpReg
3034         masm.jcc(Assembler::equal, DONE_LABEL);
3035         // Recursive locking
3036         masm.subptr(tmpReg, rsp);
3037         masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3038         masm.movptr(Address(boxReg, 0), tmpReg);
3039         masm.bind(DONE_LABEL) ; 
3040     } else {  
3041       // Possible cases that we'll encounter in fast_lock 
3042       // ------------------------------------------------
3043       // * Inflated
3044       //    -- unlocked
3045       //    -- Locked
3046       //       = by self
3047       //       = by other
3048       // * biased
3049       //    -- by Self
3050       //    -- by other
3051       // * neutral
3052       // * stack-locked
3053       //    -- by self
3054       //       = sp-proximity test hits
3055       //       = sp-proximity test generates false-negative
3056       //    -- by other
3057       //
3058 
3059       Label IsInflated, DONE_LABEL, PopDone ;
3060 
3061       // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3062       // order to reduce the number of conditional branches in the most common cases.
3063       // Beware -- there's a subtle invariant that fetch of the markword
3064       // at [FETCH], below, will never observe a biased encoding (*101b).
3065       // If this invariant is not held we risk exclusion (safety) failure.
3066       if (UseBiasedLocking && !UseOptoBiasInlining) {
3067         masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3068       }
3069 
3070       masm.movptr(tmpReg, Address(objReg, 0)) ;         // [FETCH]
3071       masm.testptr(tmpReg, 0x02) ;                      // Inflated v (Stack-locked or neutral)
3072       masm.jccb  (Assembler::notZero, IsInflated) ;
3073 
3074       // Attempt stack-locking ...
3075       masm.orptr (tmpReg, 0x1);
3076       masm.movptr(Address(boxReg, 0), tmpReg);          // Anticipate successful CAS
3077       if (os::is_MP()) { masm.lock();  }
3078       masm.cmpxchgptr(boxReg, Address(objReg, 0));           // Updates tmpReg
3079       if (_counters != NULL) {
3080         masm.cond_inc32(Assembler::equal,
3081                         ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3082       }
3083       masm.jccb (Assembler::equal, DONE_LABEL);
3084 
3085       // Recursive locking
3086       masm.subptr(tmpReg, rsp);
3087       masm.andptr(tmpReg, 0xFFFFF003 );
3088       masm.movptr(Address(boxReg, 0), tmpReg);
3089       if (_counters != NULL) {
3090         masm.cond_inc32(Assembler::equal,
3091                         ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3092       }
3093       masm.jmp  (DONE_LABEL) ;
3094 
3095       masm.bind (IsInflated) ;
3096 
3097       // The object is inflated.
3098       //
3099       // TODO-FIXME: eliminate the ugly use of manifest constants:
3100       //   Use markOopDesc::monitor_value instead of "2".
3101       //   use markOop::unused_mark() instead of "3".
3102       // The tmpReg value is an objectMonitor reference ORed with
3103       // markOopDesc::monitor_value (2).   We can either convert tmpReg to an
3104       // objectmonitor pointer by masking off the "2" bit or we can just
3105       // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3106       // field offsets with "-2" to compensate for and annul the low-order tag bit.
3107       //
3108       // I use the latter as it avoids AGI stalls.
3109       // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3110       // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3111       //
3112       #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3113 
3114       // boxReg refers to the on-stack BasicLock in the current frame.
3115       // We'd like to write:
3116       //   set box->_displaced_header = markOop::unused_mark().  Any non-0 value suffices.
3117       // This is convenient but results a ST-before-CAS penalty.  The following CAS suffers
3118       // additional latency as we have another ST in the store buffer that must drain.
3119 
3120       if (EmitSync & 8192) { 
3121          masm.movptr(Address(boxReg, 0), 3) ;            // results in ST-before-CAS penalty
3122          masm.get_thread (scrReg) ; 
3123          masm.movptr(boxReg, tmpReg);                    // consider: LEA box, [tmp-2] 
3124          masm.movptr(tmpReg, NULL_WORD);                 // consider: xor vs mov
3125          if (os::is_MP()) { masm.lock(); } 
3126          masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 
3127       } else 
3128       if ((EmitSync & 128) == 0) {                      // avoid ST-before-CAS
3129          masm.movptr(scrReg, boxReg) ; 
3130          masm.movptr(boxReg, tmpReg);                   // consider: LEA box, [tmp-2] 
3131 
3132          // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3133          if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3134             // prefetchw [eax + Offset(_owner)-2]
3135             masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3136          }
3137 
3138          if ((EmitSync & 64) == 0) {
3139            // Optimistic form: consider XORL tmpReg,tmpReg
3140            masm.movptr(tmpReg, NULL_WORD) ; 
3141          } else { 
3142            // Can suffer RTS->RTO upgrades on shared or cold $ lines
3143            // Test-And-CAS instead of CAS
3144            masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;   // rax, = m->_owner
3145            masm.testptr(tmpReg, tmpReg) ;                   // Locked ? 
3146            masm.jccb  (Assembler::notZero, DONE_LABEL) ;                   
3147          }
3148 
3149          // Appears unlocked - try to swing _owner from null to non-null.
3150          // Ideally, I'd manifest "Self" with get_thread and then attempt
3151          // to CAS the register containing Self into m->Owner.
3152          // But we don't have enough registers, so instead we can either try to CAS
3153          // rsp or the address of the box (in scr) into &m->owner.  If the CAS succeeds
3154          // we later store "Self" into m->Owner.  Transiently storing a stack address
3155          // (rsp or the address of the box) into  m->owner is harmless.
3156          // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
3157          if (os::is_MP()) { masm.lock();  }
3158          masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 
3159          masm.movptr(Address(scrReg, 0), 3) ;          // box->_displaced_header = 3
3160          masm.jccb  (Assembler::notZero, DONE_LABEL) ; 
3161          masm.get_thread (scrReg) ;                    // beware: clobbers ICCs
3162          masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ; 
3163          masm.xorptr(boxReg, boxReg) ;                 // set icc.ZFlag = 1 to indicate success
3164                        
3165          // If the CAS fails we can either retry or pass control to the slow-path.  
3166          // We use the latter tactic.  
3167          // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3168          // If the CAS was successful ...
3169          //   Self has acquired the lock
3170          //   Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3171          // Intentional fall-through into DONE_LABEL ...
3172       } else {
3173          masm.movptr(Address(boxReg, 0), 3) ;       // results in ST-before-CAS penalty
3174          masm.movptr(boxReg, tmpReg) ; 
3175 
3176          // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3177          if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3178             // prefetchw [eax + Offset(_owner)-2]
3179             masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3180          }
3181 
3182          if ((EmitSync & 64) == 0) {
3183            // Optimistic form
3184            masm.xorptr  (tmpReg, tmpReg) ; 
3185          } else { 
3186            // Can suffer RTS->RTO upgrades on shared or cold $ lines
3187            masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;   // rax, = m->_owner
3188            masm.testptr(tmpReg, tmpReg) ;                   // Locked ? 
3189            masm.jccb  (Assembler::notZero, DONE_LABEL) ;                   
3190          }
3191 
3192          // Appears unlocked - try to swing _owner from null to non-null.
3193          // Use either "Self" (in scr) or rsp as thread identity in _owner.
3194          // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
3195          masm.get_thread (scrReg) ;
3196          if (os::is_MP()) { masm.lock(); }
3197          masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3198 
3199          // If the CAS fails we can either retry or pass control to the slow-path.
3200          // We use the latter tactic.
3201          // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3202          // If the CAS was successful ...
3203          //   Self has acquired the lock
3204          //   Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3205          // Intentional fall-through into DONE_LABEL ...
3206       }
3207 
3208       // DONE_LABEL is a hot target - we'd really like to place it at the
3209       // start of cache line by padding with NOPs.
3210       // See the AMD and Intel software optimization manuals for the
3211       // most efficient "long" NOP encodings.
3212       // Unfortunately none of our alignment mechanisms suffice.
3213       masm.bind(DONE_LABEL);
3214 
3215       // Avoid branch-to-branch on AMD processors
3216       // This appears to be superstition.
3217       if (EmitSync & 32) masm.nop() ;
3218 
3219 
3220       // At DONE_LABEL the icc ZFlag is set as follows ...
3221       // Fast_Unlock uses the same protocol.
3222       // ZFlag == 1 -> Success
3223       // ZFlag == 0 -> Failure - force control through the slow-path
3224     }
3225   %}
3226 
3227   // obj: object to unlock
3228   // box: box address (displaced header location), killed.  Must be EAX.
3229   // rbx,: killed tmp; cannot be obj nor box.
3230   //
3231   // Some commentary on balanced locking:
3232   //
3233   // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3234   // Methods that don't have provably balanced locking are forced to run in the
3235   // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3236   // The interpreter provides two properties:
3237   // I1:  At return-time the interpreter automatically and quietly unlocks any
3238   //      objects acquired the current activation (frame).  Recall that the
3239   //      interpreter maintains an on-stack list of locks currently held by
3240   //      a frame.
3241   // I2:  If a method attempts to unlock an object that is not held by the
3242   //      the frame the interpreter throws IMSX.
3243   //
3244   // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3245   // B() doesn't have provably balanced locking so it runs in the interpreter.
3246   // Control returns to A() and A() unlocks O.  By I1 and I2, above, we know that O
3247   // is still locked by A().
3248   //
3249   // The only other source of unbalanced locking would be JNI.  The "Java Native Interface:
3250   // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3251   // should not be unlocked by "normal" java-level locking and vice-versa.  The specification
3252   // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3253 
3254   enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3255 
3256     Register objReg = as_Register($obj$$reg);
3257     Register boxReg = as_Register($box$$reg);
3258     Register tmpReg = as_Register($tmp$$reg);
3259 
3260     guarantee (objReg != boxReg, "") ;
3261     guarantee (objReg != tmpReg, "") ;
3262     guarantee (boxReg != tmpReg, "") ;
3263     guarantee (boxReg == as_Register(EAX_enc), "") ;
3264     MacroAssembler masm(&cbuf);
3265 
3266     if (EmitSync & 4) {
3267       // Disable - inhibit all inlining.  Force control through the slow-path
3268       masm.cmpptr (rsp, 0) ; 
3269     } else 
3270     if (EmitSync & 8) {
3271       Label DONE_LABEL ;
3272       if (UseBiasedLocking) {
3273          masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3274       }
3275       // classic stack-locking code ...
3276       masm.movptr(tmpReg, Address(boxReg, 0)) ;
3277       masm.testptr(tmpReg, tmpReg) ;
3278       masm.jcc   (Assembler::zero, DONE_LABEL) ;
3279       if (os::is_MP()) { masm.lock(); }
3280       masm.cmpxchgptr(tmpReg, Address(objReg, 0));          // Uses EAX which is box
3281       masm.bind(DONE_LABEL);
3282     } else {
3283       Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3284 
3285       // Critically, the biased locking test must have precedence over
3286       // and appear before the (box->dhw == 0) recursive stack-lock test.
3287       if (UseBiasedLocking && !UseOptoBiasInlining) {
3288          masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3289       }
3290       
3291       masm.cmpptr(Address(boxReg, 0), 0) ;            // Examine the displaced header
3292       masm.movptr(tmpReg, Address(objReg, 0)) ;       // Examine the object's markword
3293       masm.jccb  (Assembler::zero, DONE_LABEL) ;      // 0 indicates recursive stack-lock
3294 
3295       masm.testptr(tmpReg, 0x02) ;                     // Inflated? 
3296       masm.jccb  (Assembler::zero, Stacked) ;
3297 
3298       masm.bind  (Inflated) ;
3299       // It's inflated.
3300       // Despite our balanced locking property we still check that m->_owner == Self
3301       // as java routines or native JNI code called by this thread might
3302       // have released the lock.
3303       // Refer to the comments in synchronizer.cpp for how we might encode extra
3304       // state in _succ so we can avoid fetching EntryList|cxq.
3305       //
3306       // I'd like to add more cases in fast_lock() and fast_unlock() --
3307       // such as recursive enter and exit -- but we have to be wary of
3308       // I$ bloat, T$ effects and BP$ effects.
3309       //
3310       // If there's no contention try a 1-0 exit.  That is, exit without
3311       // a costly MEMBAR or CAS.  See synchronizer.cpp for details on how
3312       // we detect and recover from the race that the 1-0 exit admits.
3313       //
3314       // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3315       // before it STs null into _owner, releasing the lock.  Updates
3316       // to data protected by the critical section must be visible before
3317       // we drop the lock (and thus before any other thread could acquire
3318       // the lock and observe the fields protected by the lock).
3319       // IA32's memory-model is SPO, so STs are ordered with respect to
3320       // each other and there's no need for an explicit barrier (fence).
3321       // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3322 
3323       masm.get_thread (boxReg) ;
3324       if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3325         // prefetchw [ebx + Offset(_owner)-2]
3326         masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3327       }
3328 
3329       // Note that we could employ various encoding schemes to reduce
3330       // the number of loads below (currently 4) to just 2 or 3.
3331       // Refer to the comments in synchronizer.cpp.
3332       // In practice the chain of fetches doesn't seem to impact performance, however.
3333       if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3334          // Attempt to reduce branch density - AMD's branch predictor.
3335          masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;  
3336          masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3337          masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 
3338          masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 
3339          masm.jccb  (Assembler::notZero, DONE_LABEL) ; 
3340          masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; 
3341          masm.jmpb  (DONE_LABEL) ; 
3342       } else { 
3343          masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;  
3344          masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3345          masm.jccb  (Assembler::notZero, DONE_LABEL) ; 
3346          masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 
3347          masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 
3348          masm.jccb  (Assembler::notZero, CheckSucc) ; 
3349          masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; 
3350          masm.jmpb  (DONE_LABEL) ; 
3351       }
3352 
3353       // The Following code fragment (EmitSync & 65536) improves the performance of
3354       // contended applications and contended synchronization microbenchmarks.
3355       // Unfortunately the emission of the code - even though not executed - causes regressions
3356       // in scimark and jetstream, evidently because of $ effects.  Replacing the code
3357       // with an equal number of never-executed NOPs results in the same regression.
3358       // We leave it off by default.
3359 
3360       if ((EmitSync & 65536) != 0) {
3361          Label LSuccess, LGoSlowPath ;
3362 
3363          masm.bind  (CheckSucc) ;
3364 
3365          // Optional pre-test ... it's safe to elide this
3366          if ((EmitSync & 16) == 0) { 
3367             masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; 
3368             masm.jccb  (Assembler::zero, LGoSlowPath) ; 
3369          }
3370 
3371          // We have a classic Dekker-style idiom:
3372          //    ST m->_owner = 0 ; MEMBAR; LD m->_succ
3373          // There are a number of ways to implement the barrier:
3374          // (1) lock:andl &m->_owner, 0
3375          //     is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3376          //     LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3377          //     Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3378          // (2) If supported, an explicit MFENCE is appealing.
3379          //     In older IA32 processors MFENCE is slower than lock:add or xchg
3380          //     particularly if the write-buffer is full as might be the case if
3381          //     if stores closely precede the fence or fence-equivalent instruction.
3382          //     In more modern implementations MFENCE appears faster, however.
3383          // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3384          //     The $lines underlying the top-of-stack should be in M-state.
3385          //     The locked add instruction is serializing, of course.
3386          // (4) Use xchg, which is serializing
3387          //     mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3388          // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3389          //     The integer condition codes will tell us if succ was 0.
3390          //     Since _succ and _owner should reside in the same $line and
3391          //     we just stored into _owner, it's likely that the $line
3392          //     remains in M-state for the lock:orl.
3393          //
3394          // We currently use (3), although it's likely that switching to (2)
3395          // is correct for the future.
3396             
3397          masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; 
3398          if (os::is_MP()) { 
3399             if (VM_Version::supports_sse2() && 1 == FenceInstruction) { 
3400               masm.mfence();
3401             } else { 
3402               masm.lock () ; masm.addptr(Address(rsp, 0), 0) ; 
3403             }
3404          }
3405          // Ratify _succ remains non-null
3406          masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; 
3407          masm.jccb  (Assembler::notZero, LSuccess) ; 
3408 
3409          masm.xorptr(boxReg, boxReg) ;                  // box is really EAX
3410          if (os::is_MP()) { masm.lock(); }
3411          masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3412          masm.jccb  (Assembler::notEqual, LSuccess) ;
3413          // Since we're low on registers we installed rsp as a placeholding in _owner.
3414          // Now install Self over rsp.  This is safe as we're transitioning from
3415          // non-null to non=null
3416          masm.get_thread (boxReg) ;
3417          masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3418          // Intentional fall-through into LGoSlowPath ...
3419 
3420          masm.bind  (LGoSlowPath) ; 
3421          masm.orptr(boxReg, 1) ;                      // set ICC.ZF=0 to indicate failure
3422          masm.jmpb  (DONE_LABEL) ; 
3423 
3424          masm.bind  (LSuccess) ; 
3425          masm.xorptr(boxReg, boxReg) ;                 // set ICC.ZF=1 to indicate success
3426          masm.jmpb  (DONE_LABEL) ; 
3427       }
3428 
3429       masm.bind (Stacked) ;
3430       // It's not inflated and it's not recursively stack-locked and it's not biased.
3431       // It must be stack-locked.
3432       // Try to reset the header to displaced header.
3433       // The "box" value on the stack is stable, so we can reload
3434       // and be assured we observe the same value as above.
3435       masm.movptr(tmpReg, Address(boxReg, 0)) ;
3436       if (os::is_MP()) {   masm.lock();    }
3437       masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3438       // Intention fall-thru into DONE_LABEL
3439 
3440 
3441       // DONE_LABEL is a hot target - we'd really like to place it at the
3442       // start of cache line by padding with NOPs.
3443       // See the AMD and Intel software optimization manuals for the
3444       // most efficient "long" NOP encodings.
3445       // Unfortunately none of our alignment mechanisms suffice.
3446       if ((EmitSync & 65536) == 0) {
3447          masm.bind (CheckSucc) ;
3448       }
3449       masm.bind(DONE_LABEL);
3450 
3451       // Avoid branch to branch on AMD processors
3452       if (EmitSync & 32768) { masm.nop() ; }
3453     }
3454   %}
3455 
3456 
3457   enc_class enc_pop_rdx() %{
3458     emit_opcode(cbuf,0x5A);
3459   %}
3460 
3461   enc_class enc_rethrow() %{
3462     cbuf.set_insts_mark();
3463     emit_opcode(cbuf, 0xE9);        // jmp    entry
3464     emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3465                    runtime_call_Relocation::spec(), RELOC_IMM32 );
3466   %}
3467 
3468 
3469   // Convert a double to an int.  Java semantics require we do complex
3470   // manglelations in the corner cases.  So we set the rounding mode to
3471   // 'zero', store the darned double down as an int, and reset the
3472   // rounding mode to 'nearest'.  The hardware throws an exception which
3473   // patches up the correct value directly to the stack.
3474   enc_class DPR2I_encoding( regDPR src ) %{
3475     // Flip to round-to-zero mode.  We attempted to allow invalid-op
3476     // exceptions here, so that a NAN or other corner-case value will
3477     // thrown an exception (but normal values get converted at full speed).
3478     // However, I2C adapters and other float-stack manglers leave pending
3479     // invalid-op exceptions hanging.  We would have to clear them before
3480     // enabling them and that is more expensive than just testing for the
3481     // invalid value Intel stores down in the corner cases.
3482     emit_opcode(cbuf,0xD9);            // FLDCW  trunc
3483     emit_opcode(cbuf,0x2D);
3484     emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3485     // Allocate a word
3486     emit_opcode(cbuf,0x83);            // SUB ESP,4
3487     emit_opcode(cbuf,0xEC);
3488     emit_d8(cbuf,0x04);
3489     // Encoding assumes a double has been pushed into FPR0.
3490     // Store down the double as an int, popping the FPU stack
3491     emit_opcode(cbuf,0xDB);            // FISTP [ESP]
3492     emit_opcode(cbuf,0x1C);
3493     emit_d8(cbuf,0x24);
3494     // Restore the rounding mode; mask the exception
3495     emit_opcode(cbuf,0xD9);            // FLDCW   std/24-bit mode
3496     emit_opcode(cbuf,0x2D);
3497     emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3498         ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3499         : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3500 
3501     // Load the converted int; adjust CPU stack
3502     emit_opcode(cbuf,0x58);       // POP EAX
3503     emit_opcode(cbuf,0x3D);       // CMP EAX,imm
3504     emit_d32   (cbuf,0x80000000); //         0x80000000
3505     emit_opcode(cbuf,0x75);       // JNE around_slow_call
3506     emit_d8    (cbuf,0x07);       // Size of slow_call
3507     // Push src onto stack slow-path
3508     emit_opcode(cbuf,0xD9 );      // FLD     ST(i)
3509     emit_d8    (cbuf,0xC0-1+$src$$reg );
3510     // CALL directly to the runtime
3511     cbuf.set_insts_mark();
3512     emit_opcode(cbuf,0xE8);       // Call into runtime
3513     emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3514     // Carry on here...
3515   %}
3516 
3517   enc_class DPR2L_encoding( regDPR src ) %{
3518     emit_opcode(cbuf,0xD9);            // FLDCW  trunc
3519     emit_opcode(cbuf,0x2D);
3520     emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3521     // Allocate a word
3522     emit_opcode(cbuf,0x83);            // SUB ESP,8
3523     emit_opcode(cbuf,0xEC);
3524     emit_d8(cbuf,0x08);
3525     // Encoding assumes a double has been pushed into FPR0.
3526     // Store down the double as a long, popping the FPU stack
3527     emit_opcode(cbuf,0xDF);            // FISTP [ESP]
3528     emit_opcode(cbuf,0x3C);
3529     emit_d8(cbuf,0x24);
3530     // Restore the rounding mode; mask the exception
3531     emit_opcode(cbuf,0xD9);            // FLDCW   std/24-bit mode
3532     emit_opcode(cbuf,0x2D);
3533     emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3534         ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3535         : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3536 
3537     // Load the converted int; adjust CPU stack
3538     emit_opcode(cbuf,0x58);       // POP EAX
3539     emit_opcode(cbuf,0x5A);       // POP EDX
3540     emit_opcode(cbuf,0x81);       // CMP EDX,imm
3541     emit_d8    (cbuf,0xFA);       // rdx
3542     emit_d32   (cbuf,0x80000000); //         0x80000000
3543     emit_opcode(cbuf,0x75);       // JNE around_slow_call
3544     emit_d8    (cbuf,0x07+4);     // Size of slow_call
3545     emit_opcode(cbuf,0x85);       // TEST EAX,EAX
3546     emit_opcode(cbuf,0xC0);       // 2/rax,/rax,
3547     emit_opcode(cbuf,0x75);       // JNE around_slow_call
3548     emit_d8    (cbuf,0x07);       // Size of slow_call
3549     // Push src onto stack slow-path
3550     emit_opcode(cbuf,0xD9 );      // FLD     ST(i)
3551     emit_d8    (cbuf,0xC0-1+$src$$reg );
3552     // CALL directly to the runtime
3553     cbuf.set_insts_mark();
3554     emit_opcode(cbuf,0xE8);       // Call into runtime
3555     emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3556     // Carry on here...
3557   %}
3558 
3559   enc_class FMul_ST_reg( eRegFPR src1 ) %{
3560     // Operand was loaded from memory into fp ST (stack top)
3561     // FMUL   ST,$src  /* D8 C8+i */
3562     emit_opcode(cbuf, 0xD8);
3563     emit_opcode(cbuf, 0xC8 + $src1$$reg);
3564   %}
3565 
3566   enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3567     // FADDP  ST,src2  /* D8 C0+i */
3568     emit_opcode(cbuf, 0xD8);
3569     emit_opcode(cbuf, 0xC0 + $src2$$reg);
3570     //could use FADDP  src2,fpST  /* DE C0+i */
3571   %}
3572 
3573   enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3574     // FADDP  src2,ST  /* DE C0+i */
3575     emit_opcode(cbuf, 0xDE);
3576     emit_opcode(cbuf, 0xC0 + $src2$$reg);
3577   %}
3578 
3579   enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3580     // Operand has been loaded into fp ST (stack top)
3581       // FSUB   ST,$src1
3582       emit_opcode(cbuf, 0xD8);
3583       emit_opcode(cbuf, 0xE0 + $src1$$reg);
3584 
3585       // FDIV
3586       emit_opcode(cbuf, 0xD8);
3587       emit_opcode(cbuf, 0xF0 + $src2$$reg);
3588   %}
3589 
3590   enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3591     // Operand was loaded from memory into fp ST (stack top)
3592     // FADD   ST,$src  /* D8 C0+i */
3593     emit_opcode(cbuf, 0xD8);
3594     emit_opcode(cbuf, 0xC0 + $src1$$reg);
3595 
3596     // FMUL  ST,src2  /* D8 C*+i */
3597     emit_opcode(cbuf, 0xD8);
3598     emit_opcode(cbuf, 0xC8 + $src2$$reg);
3599   %}
3600 
3601 
3602   enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3603     // Operand was loaded from memory into fp ST (stack top)
3604     // FADD   ST,$src  /* D8 C0+i */
3605     emit_opcode(cbuf, 0xD8);
3606     emit_opcode(cbuf, 0xC0 + $src1$$reg);
3607 
3608     // FMULP  src2,ST  /* DE C8+i */
3609     emit_opcode(cbuf, 0xDE);
3610     emit_opcode(cbuf, 0xC8 + $src2$$reg);
3611   %}
3612 
3613   // Atomically load the volatile long
3614   enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3615     emit_opcode(cbuf,0xDF);
3616     int rm_byte_opcode = 0x05;
3617     int base     = $mem$$base;
3618     int index    = $mem$$index;
3619     int scale    = $mem$$scale;
3620     int displace = $mem$$disp;
3621     relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3622     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3623     store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3624   %}
3625 
3626   // Volatile Store Long.  Must be atomic, so move it into
3627   // the FP TOS and then do a 64-bit FIST.  Has to probe the
3628   // target address before the store (for null-ptr checks)
3629   // so the memory operand is used twice in the encoding.
3630   enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3631     store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3632     cbuf.set_insts_mark();            // Mark start of FIST in case $mem has an oop
3633     emit_opcode(cbuf,0xDF);
3634     int rm_byte_opcode = 0x07;
3635     int base     = $mem$$base;
3636     int index    = $mem$$index;
3637     int scale    = $mem$$scale;
3638     int displace = $mem$$disp;
3639     relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals
3640     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc);
3641   %}
3642 
3643   // Safepoint Poll.  This polls the safepoint page, and causes an
3644   // exception if it is not readable. Unfortunately, it kills the condition code
3645   // in the process
3646   // We current use TESTL [spp],EDI
3647   // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3648 
3649   enc_class Safepoint_Poll() %{
3650     cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3651     emit_opcode(cbuf,0x85);
3652     emit_rm (cbuf, 0x0, 0x7, 0x5);
3653     emit_d32(cbuf, (intptr_t)os::get_polling_page());
3654   %}
3655 %}
3656 
3657 
3658 //----------FRAME--------------------------------------------------------------
3659 // Definition of frame structure and management information.
3660 //
3661 //  S T A C K   L A Y O U T    Allocators stack-slot number
3662 //                             |   (to get allocators register number
3663 //  G  Owned by    |        |  v    add OptoReg::stack0())
3664 //  r   CALLER     |        |
3665 //  o     |        +--------+      pad to even-align allocators stack-slot
3666 //  w     V        |  pad0  |        numbers; owned by CALLER
3667 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
3668 //  h     ^        |   in   |  5
3669 //        |        |  args  |  4   Holes in incoming args owned by SELF
3670 //  |     |        |        |  3
3671 //  |     |        +--------+
3672 //  V     |        | old out|      Empty on Intel, window on Sparc
3673 //        |    old |preserve|      Must be even aligned.
3674 //        |     SP-+--------+----> Matcher::_old_SP, even aligned
3675 //        |        |   in   |  3   area for Intel ret address
3676 //     Owned by    |preserve|      Empty on Sparc.
3677 //       SELF      +--------+
3678 //        |        |  pad2  |  2   pad to align old SP
3679 //        |        +--------+  1
3680 //        |        | locks  |  0
3681 //        |        +--------+----> OptoReg::stack0(), even aligned
3682 //        |        |  pad1  | 11   pad to align new SP
3683 //        |        +--------+
3684 //        |        |        | 10
3685 //        |        | spills |  9   spills
3686 //        V        |        |  8   (pad0 slot for callee)
3687 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
3688 //        ^        |  out   |  7
3689 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
3690 //     Owned by    +--------+
3691 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
3692 //        |    new |preserve|      Must be even-aligned.
3693 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
3694 //        |        |        |
3695 //
3696 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
3697 //         known from SELF's arguments and the Java calling convention.
3698 //         Region 6-7 is determined per call site.
3699 // Note 2: If the calling convention leaves holes in the incoming argument
3700 //         area, those holes are owned by SELF.  Holes in the outgoing area
3701 //         are owned by the CALLEE.  Holes should not be nessecary in the
3702 //         incoming area, as the Java calling convention is completely under
3703 //         the control of the AD file.  Doubles can be sorted and packed to
3704 //         avoid holes.  Holes in the outgoing arguments may be nessecary for
3705 //         varargs C calling conventions.
3706 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
3707 //         even aligned with pad0 as needed.
3708 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
3709 //         region 6-11 is even aligned; it may be padded out more so that
3710 //         the region from SP to FP meets the minimum stack alignment.
3711 
3712 frame %{
3713   // What direction does stack grow in (assumed to be same for C & Java)
3714   stack_direction(TOWARDS_LOW);
3715 
3716   // These three registers define part of the calling convention
3717   // between compiled code and the interpreter.
3718   inline_cache_reg(EAX);                // Inline Cache Register
3719   interpreter_method_oop_reg(EBX);      // Method Oop Register when calling interpreter
3720 
3721   // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3722   cisc_spilling_operand_name(indOffset32);
3723 
3724   // Number of stack slots consumed by locking an object
3725   sync_stack_slots(1);
3726 
3727   // Compiled code's Frame Pointer
3728   frame_pointer(ESP);
3729   // Interpreter stores its frame pointer in a register which is
3730   // stored to the stack by I2CAdaptors.
3731   // I2CAdaptors convert from interpreted java to compiled java.
3732   interpreter_frame_pointer(EBP);
3733 
3734   // Stack alignment requirement
3735   // Alignment size in bytes (128-bit -> 16 bytes)
3736   stack_alignment(StackAlignmentInBytes);
3737 
3738   // Number of stack slots between incoming argument block and the start of
3739   // a new frame.  The PROLOG must add this many slots to the stack.  The
3740   // EPILOG must remove this many slots.  Intel needs one slot for
3741   // return address and one for rbp, (must save rbp)
3742   in_preserve_stack_slots(2+VerifyStackAtCalls);
3743 
3744   // Number of outgoing stack slots killed above the out_preserve_stack_slots
3745   // for calls to C.  Supports the var-args backing area for register parms.
3746   varargs_C_out_slots_killed(0);
3747 
3748   // The after-PROLOG location of the return address.  Location of
3749   // return address specifies a type (REG or STACK) and a number
3750   // representing the register number (i.e. - use a register name) or
3751   // stack slot.
3752   // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3753   // Otherwise, it is above the locks and verification slot and alignment word
3754   return_addr(STACK - 1 +
3755               round_to((Compile::current()->in_preserve_stack_slots() +
3756                         Compile::current()->fixed_slots()),
3757                        stack_alignment_in_slots()));
3758 
3759   // Body of function which returns an integer array locating
3760   // arguments either in registers or in stack slots.  Passed an array
3761   // of ideal registers called "sig" and a "length" count.  Stack-slot
3762   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3763   // arguments for a CALLEE.  Incoming stack arguments are
3764   // automatically biased by the preserve_stack_slots field above.
3765   calling_convention %{
3766     // No difference between ingoing/outgoing just pass false
3767     SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3768   %}
3769 
3770 
3771   // Body of function which returns an integer array locating
3772   // arguments either in registers or in stack slots.  Passed an array
3773   // of ideal registers called "sig" and a "length" count.  Stack-slot
3774   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3775   // arguments for a CALLEE.  Incoming stack arguments are
3776   // automatically biased by the preserve_stack_slots field above.
3777   c_calling_convention %{
3778     // This is obviously always outgoing
3779     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3780   %}
3781 
3782   // Location of C & interpreter return values
3783   c_return_value %{
3784     assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3785     static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num,      EAX_num,      FPR1L_num,    FPR1L_num, EAX_num };
3786     static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3787 
3788     // in SSE2+ mode we want to keep the FPU stack clean so pretend
3789     // that C functions return float and double results in XMM0.
3790     if( ideal_reg == Op_RegD && UseSSE>=2 )
3791       return OptoRegPair(XMM0b_num,XMM0_num);
3792     if( ideal_reg == Op_RegF && UseSSE>=2 )
3793       return OptoRegPair(OptoReg::Bad,XMM0_num);
3794 
3795     return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3796   %}
3797 
3798   // Location of return values
3799   return_value %{
3800     assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3801     static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num,      EAX_num,      FPR1L_num,    FPR1L_num, EAX_num };
3802     static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3803     if( ideal_reg == Op_RegD && UseSSE>=2 )
3804       return OptoRegPair(XMM0b_num,XMM0_num);
3805     if( ideal_reg == Op_RegF && UseSSE>=1 )
3806       return OptoRegPair(OptoReg::Bad,XMM0_num);
3807     return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3808   %}
3809 
3810 %}
3811 
3812 //----------ATTRIBUTES---------------------------------------------------------
3813 //----------Operand Attributes-------------------------------------------------
3814 op_attrib op_cost(0);        // Required cost attribute
3815 
3816 //----------Instruction Attributes---------------------------------------------
3817 ins_attrib ins_cost(100);       // Required cost attribute
3818 ins_attrib ins_size(8);         // Required size attribute (in bits)
3819 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3820                                 // non-matching short branch variant of some
3821                                                             // long branch?
3822 ins_attrib ins_alignment(1);    // Required alignment attribute (must be a power of 2)
3823                                 // specifies the alignment that some part of the instruction (not
3824                                 // necessarily the start) requires.  If > 1, a compute_padding()
3825                                 // function must be provided for the instruction
3826 
3827 //----------OPERANDS-----------------------------------------------------------
3828 // Operand definitions must precede instruction definitions for correct parsing
3829 // in the ADLC because operands constitute user defined types which are used in
3830 // instruction definitions.
3831 
3832 //----------Simple Operands----------------------------------------------------
3833 // Immediate Operands
3834 // Integer Immediate
3835 operand immI() %{
3836   match(ConI);
3837 
3838   op_cost(10);
3839   format %{ %}
3840   interface(CONST_INTER);
3841 %}
3842 
3843 // Constant for test vs zero
3844 operand immI0() %{
3845   predicate(n->get_int() == 0);
3846   match(ConI);
3847 
3848   op_cost(0);
3849   format %{ %}
3850   interface(CONST_INTER);
3851 %}
3852 
3853 // Constant for increment
3854 operand immI1() %{
3855   predicate(n->get_int() == 1);
3856   match(ConI);
3857 
3858   op_cost(0);
3859   format %{ %}
3860   interface(CONST_INTER);
3861 %}
3862 
3863 // Constant for decrement
3864 operand immI_M1() %{
3865   predicate(n->get_int() == -1);
3866   match(ConI);
3867 
3868   op_cost(0);
3869   format %{ %}
3870   interface(CONST_INTER);
3871 %}
3872 
3873 // Valid scale values for addressing modes
3874 operand immI2() %{
3875   predicate(0 <= n->get_int() && (n->get_int() <= 3));
3876   match(ConI);
3877 
3878   format %{ %}
3879   interface(CONST_INTER);
3880 %}
3881 
3882 operand immI8() %{
3883   predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3884   match(ConI);
3885 
3886   op_cost(5);
3887   format %{ %}
3888   interface(CONST_INTER);
3889 %}
3890 
3891 operand immI16() %{
3892   predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3893   match(ConI);
3894 
3895   op_cost(10);
3896   format %{ %}
3897   interface(CONST_INTER);
3898 %}
3899 
3900 // Int Immediate non-negative
3901 operand immU31()
3902 %{
3903   predicate(n->get_int() >= 0);
3904   match(ConI);
3905 
3906   op_cost(0);
3907   format %{ %}
3908   interface(CONST_INTER);
3909 %}
3910 
3911 // Constant for long shifts
3912 operand immI_32() %{
3913   predicate( n->get_int() == 32 );
3914   match(ConI);
3915 
3916   op_cost(0);
3917   format %{ %}
3918   interface(CONST_INTER);
3919 %}
3920 
3921 operand immI_1_31() %{
3922   predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3923   match(ConI);
3924 
3925   op_cost(0);
3926   format %{ %}
3927   interface(CONST_INTER);
3928 %}
3929 
3930 operand immI_32_63() %{
3931   predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3932   match(ConI);
3933   op_cost(0);
3934 
3935   format %{ %}
3936   interface(CONST_INTER);
3937 %}
3938 
3939 operand immI_1() %{
3940   predicate( n->get_int() == 1 );
3941   match(ConI);
3942 
3943   op_cost(0);
3944   format %{ %}
3945   interface(CONST_INTER);
3946 %}
3947 
3948 operand immI_2() %{
3949   predicate( n->get_int() == 2 );
3950   match(ConI);
3951 
3952   op_cost(0);
3953   format %{ %}
3954   interface(CONST_INTER);
3955 %}
3956 
3957 operand immI_3() %{
3958   predicate( n->get_int() == 3 );
3959   match(ConI);
3960 
3961   op_cost(0);
3962   format %{ %}
3963   interface(CONST_INTER);
3964 %}
3965 
3966 // Pointer Immediate
3967 operand immP() %{
3968   match(ConP);
3969 
3970   op_cost(10);
3971   format %{ %}
3972   interface(CONST_INTER);
3973 %}
3974 
3975 // NULL Pointer Immediate
3976 operand immP0() %{
3977   predicate( n->get_ptr() == 0 );
3978   match(ConP);
3979   op_cost(0);
3980 
3981   format %{ %}
3982   interface(CONST_INTER);
3983 %}
3984 
3985 // Long Immediate
3986 operand immL() %{
3987   match(ConL);
3988 
3989   op_cost(20);
3990   format %{ %}
3991   interface(CONST_INTER);
3992 %}
3993 
3994 // Long Immediate zero
3995 operand immL0() %{
3996   predicate( n->get_long() == 0L );
3997   match(ConL);
3998   op_cost(0);
3999 
4000   format %{ %}
4001   interface(CONST_INTER);
4002 %}
4003 
4004 // Long Immediate zero
4005 operand immL_M1() %{
4006   predicate( n->get_long() == -1L );
4007   match(ConL);
4008   op_cost(0);
4009 
4010   format %{ %}
4011   interface(CONST_INTER);
4012 %}
4013 
4014 // Long immediate from 0 to 127.
4015 // Used for a shorter form of long mul by 10.
4016 operand immL_127() %{
4017   predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4018   match(ConL);
4019   op_cost(0);
4020 
4021   format %{ %}
4022   interface(CONST_INTER);
4023 %}
4024 
4025 // Long Immediate: low 32-bit mask
4026 operand immL_32bits() %{
4027   predicate(n->get_long() == 0xFFFFFFFFL);
4028   match(ConL);
4029   op_cost(0);
4030 
4031   format %{ %}
4032   interface(CONST_INTER);
4033 %}
4034 
4035 // Long Immediate: low 32-bit mask
4036 operand immL32() %{
4037   predicate(n->get_long() == (int)(n->get_long()));
4038   match(ConL);
4039   op_cost(20);
4040 
4041   format %{ %}
4042   interface(CONST_INTER);
4043 %}
4044 
4045 //Double Immediate zero
4046 operand immDPR0() %{
4047   // Do additional (and counter-intuitive) test against NaN to work around VC++
4048   // bug that generates code such that NaNs compare equal to 0.0
4049   predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4050   match(ConD);
4051 
4052   op_cost(5);
4053   format %{ %}
4054   interface(CONST_INTER);
4055 %}
4056 
4057 // Double Immediate one
4058 operand immDPR1() %{
4059   predicate( UseSSE<=1 && n->getd() == 1.0 );
4060   match(ConD);
4061 
4062   op_cost(5);
4063   format %{ %}
4064   interface(CONST_INTER);
4065 %}
4066 
4067 // Double Immediate
4068 operand immDPR() %{
4069   predicate(UseSSE<=1);
4070   match(ConD);
4071 
4072   op_cost(5);
4073   format %{ %}
4074   interface(CONST_INTER);
4075 %}
4076 
4077 operand immD() %{
4078   predicate(UseSSE>=2);
4079   match(ConD);
4080 
4081   op_cost(5);
4082   format %{ %}
4083   interface(CONST_INTER);
4084 %}
4085 
4086 // Double Immediate zero
4087 operand immD0() %{
4088   // Do additional (and counter-intuitive) test against NaN to work around VC++
4089   // bug that generates code such that NaNs compare equal to 0.0 AND do not
4090   // compare equal to -0.0.
4091   predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4092   match(ConD);
4093 
4094   format %{ %}
4095   interface(CONST_INTER);
4096 %}
4097 
4098 // Float Immediate zero
4099 operand immFPR0() %{
4100   predicate(UseSSE == 0 && n->getf() == 0.0F);
4101   match(ConF);
4102 
4103   op_cost(5);
4104   format %{ %}
4105   interface(CONST_INTER);
4106 %}
4107 
4108 // Float Immediate one
4109 operand immFPR1() %{
4110   predicate(UseSSE == 0 && n->getf() == 1.0F);
4111   match(ConF);
4112 
4113   op_cost(5);
4114   format %{ %}
4115   interface(CONST_INTER);
4116 %}
4117 
4118 // Float Immediate
4119 operand immFPR() %{
4120   predicate( UseSSE == 0 );
4121   match(ConF);
4122 
4123   op_cost(5);
4124   format %{ %}
4125   interface(CONST_INTER);
4126 %}
4127 
4128 // Float Immediate
4129 operand immF() %{
4130   predicate(UseSSE >= 1);
4131   match(ConF);
4132 
4133   op_cost(5);
4134   format %{ %}
4135   interface(CONST_INTER);
4136 %}
4137 
4138 // Float Immediate zero.  Zero and not -0.0
4139 operand immF0() %{
4140   predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4141   match(ConF);
4142 
4143   op_cost(5);
4144   format %{ %}
4145   interface(CONST_INTER);
4146 %}
4147 
4148 // Immediates for special shifts (sign extend)
4149 
4150 // Constants for increment
4151 operand immI_16() %{
4152   predicate( n->get_int() == 16 );
4153   match(ConI);
4154 
4155   format %{ %}
4156   interface(CONST_INTER);
4157 %}
4158 
4159 operand immI_24() %{
4160   predicate( n->get_int() == 24 );
4161   match(ConI);
4162 
4163   format %{ %}
4164   interface(CONST_INTER);
4165 %}
4166 
4167 // Constant for byte-wide masking
4168 operand immI_255() %{
4169   predicate( n->get_int() == 255 );
4170   match(ConI);
4171 
4172   format %{ %}
4173   interface(CONST_INTER);
4174 %}
4175 
4176 // Constant for short-wide masking
4177 operand immI_65535() %{
4178   predicate(n->get_int() == 65535);
4179   match(ConI);
4180 
4181   format %{ %}
4182   interface(CONST_INTER);
4183 %}
4184 
4185 // Register Operands
4186 // Integer Register
4187 operand rRegI() %{
4188   constraint(ALLOC_IN_RC(int_reg));
4189   match(RegI);
4190   match(xRegI);
4191   match(eAXRegI);
4192   match(eBXRegI);
4193   match(eCXRegI);
4194   match(eDXRegI);
4195   match(eDIRegI);
4196   match(eSIRegI);
4197 
4198   format %{ %}
4199   interface(REG_INTER);
4200 %}
4201 
4202 // Subset of Integer Register
4203 operand xRegI(rRegI reg) %{
4204   constraint(ALLOC_IN_RC(int_x_reg));
4205   match(reg);
4206   match(eAXRegI);
4207   match(eBXRegI);
4208   match(eCXRegI);
4209   match(eDXRegI);
4210 
4211   format %{ %}
4212   interface(REG_INTER);
4213 %}
4214 
4215 // Special Registers
4216 operand eAXRegI(xRegI reg) %{
4217   constraint(ALLOC_IN_RC(eax_reg));
4218   match(reg);
4219   match(rRegI);
4220 
4221   format %{ "EAX" %}
4222   interface(REG_INTER);
4223 %}
4224 
4225 // Special Registers
4226 operand eBXRegI(xRegI reg) %{
4227   constraint(ALLOC_IN_RC(ebx_reg));
4228   match(reg);
4229   match(rRegI);
4230 
4231   format %{ "EBX" %}
4232   interface(REG_INTER);
4233 %}
4234 
4235 operand eCXRegI(xRegI reg) %{
4236   constraint(ALLOC_IN_RC(ecx_reg));
4237   match(reg);
4238   match(rRegI);
4239 
4240   format %{ "ECX" %}
4241   interface(REG_INTER);
4242 %}
4243 
4244 operand eDXRegI(xRegI reg) %{
4245   constraint(ALLOC_IN_RC(edx_reg));
4246   match(reg);
4247   match(rRegI);
4248 
4249   format %{ "EDX" %}
4250   interface(REG_INTER);
4251 %}
4252 
4253 operand eDIRegI(xRegI reg) %{
4254   constraint(ALLOC_IN_RC(edi_reg));
4255   match(reg);
4256   match(rRegI);
4257 
4258   format %{ "EDI" %}
4259   interface(REG_INTER);
4260 %}
4261 
4262 operand naxRegI() %{
4263   constraint(ALLOC_IN_RC(nax_reg));
4264   match(RegI);
4265   match(eCXRegI);
4266   match(eDXRegI);
4267   match(eSIRegI);
4268   match(eDIRegI);
4269 
4270   format %{ %}
4271   interface(REG_INTER);
4272 %}
4273 
4274 operand nadxRegI() %{
4275   constraint(ALLOC_IN_RC(nadx_reg));
4276   match(RegI);
4277   match(eBXRegI);
4278   match(eCXRegI);
4279   match(eSIRegI);
4280   match(eDIRegI);
4281 
4282   format %{ %}
4283   interface(REG_INTER);
4284 %}
4285 
4286 operand ncxRegI() %{
4287   constraint(ALLOC_IN_RC(ncx_reg));
4288   match(RegI);
4289   match(eAXRegI);
4290   match(eDXRegI);
4291   match(eSIRegI);
4292   match(eDIRegI);
4293 
4294   format %{ %}
4295   interface(REG_INTER);
4296 %}
4297 
4298 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4299 // //
4300 operand eSIRegI(xRegI reg) %{
4301    constraint(ALLOC_IN_RC(esi_reg));
4302    match(reg);
4303    match(rRegI);
4304 
4305    format %{ "ESI" %}
4306    interface(REG_INTER);
4307 %}
4308 
4309 // Pointer Register
4310 operand anyRegP() %{
4311   constraint(ALLOC_IN_RC(any_reg));
4312   match(RegP);
4313   match(eAXRegP);
4314   match(eBXRegP);
4315   match(eCXRegP);
4316   match(eDIRegP);
4317   match(eRegP);
4318 
4319   format %{ %}
4320   interface(REG_INTER);
4321 %}
4322 
4323 operand eRegP() %{
4324   constraint(ALLOC_IN_RC(int_reg));
4325   match(RegP);
4326   match(eAXRegP);
4327   match(eBXRegP);
4328   match(eCXRegP);
4329   match(eDIRegP);
4330 
4331   format %{ %}
4332   interface(REG_INTER);
4333 %}
4334 
4335 // On windows95, EBP is not safe to use for implicit null tests.
4336 operand eRegP_no_EBP() %{
4337   constraint(ALLOC_IN_RC(int_reg_no_rbp));
4338   match(RegP);
4339   match(eAXRegP);
4340   match(eBXRegP);
4341   match(eCXRegP);
4342   match(eDIRegP);
4343 
4344   op_cost(100);
4345   format %{ %}
4346   interface(REG_INTER);
4347 %}
4348 
4349 operand naxRegP() %{
4350   constraint(ALLOC_IN_RC(nax_reg));
4351   match(RegP);
4352   match(eBXRegP);
4353   match(eDXRegP);
4354   match(eCXRegP);
4355   match(eSIRegP);
4356   match(eDIRegP);
4357 
4358   format %{ %}
4359   interface(REG_INTER);
4360 %}
4361 
4362 operand nabxRegP() %{
4363   constraint(ALLOC_IN_RC(nabx_reg));
4364   match(RegP);
4365   match(eCXRegP);
4366   match(eDXRegP);
4367   match(eSIRegP);
4368   match(eDIRegP);
4369 
4370   format %{ %}
4371   interface(REG_INTER);
4372 %}
4373 
4374 operand pRegP() %{
4375   constraint(ALLOC_IN_RC(p_reg));
4376   match(RegP);
4377   match(eBXRegP);
4378   match(eDXRegP);
4379   match(eSIRegP);
4380   match(eDIRegP);
4381 
4382   format %{ %}
4383   interface(REG_INTER);
4384 %}
4385 
4386 // Special Registers
4387 // Return a pointer value
4388 operand eAXRegP(eRegP reg) %{
4389   constraint(ALLOC_IN_RC(eax_reg));
4390   match(reg);
4391   format %{ "EAX" %}
4392   interface(REG_INTER);
4393 %}
4394 
4395 // Used in AtomicAdd
4396 operand eBXRegP(eRegP reg) %{
4397   constraint(ALLOC_IN_RC(ebx_reg));
4398   match(reg);
4399   format %{ "EBX" %}
4400   interface(REG_INTER);
4401 %}
4402 
4403 // Tail-call (interprocedural jump) to interpreter
4404 operand eCXRegP(eRegP reg) %{
4405   constraint(ALLOC_IN_RC(ecx_reg));
4406   match(reg);
4407   format %{ "ECX" %}
4408   interface(REG_INTER);
4409 %}
4410 
4411 operand eSIRegP(eRegP reg) %{
4412   constraint(ALLOC_IN_RC(esi_reg));
4413   match(reg);
4414   format %{ "ESI" %}
4415   interface(REG_INTER);
4416 %}
4417 
4418 // Used in rep stosw
4419 operand eDIRegP(eRegP reg) %{
4420   constraint(ALLOC_IN_RC(edi_reg));
4421   match(reg);
4422   format %{ "EDI" %}
4423   interface(REG_INTER);
4424 %}
4425 
4426 operand eBPRegP() %{
4427   constraint(ALLOC_IN_RC(ebp_reg));
4428   match(RegP);
4429   format %{ "EBP" %}
4430   interface(REG_INTER);
4431 %}
4432 
4433 operand eRegL() %{
4434   constraint(ALLOC_IN_RC(long_reg));
4435   match(RegL);
4436   match(eADXRegL);
4437 
4438   format %{ %}
4439   interface(REG_INTER);
4440 %}
4441 
4442 operand eADXRegL( eRegL reg ) %{
4443   constraint(ALLOC_IN_RC(eadx_reg));
4444   match(reg);
4445 
4446   format %{ "EDX:EAX" %}
4447   interface(REG_INTER);
4448 %}
4449 
4450 operand eBCXRegL( eRegL reg ) %{
4451   constraint(ALLOC_IN_RC(ebcx_reg));
4452   match(reg);
4453 
4454   format %{ "EBX:ECX" %}
4455   interface(REG_INTER);
4456 %}
4457 
4458 // Special case for integer high multiply
4459 operand eADXRegL_low_only() %{
4460   constraint(ALLOC_IN_RC(eadx_reg));
4461   match(RegL);
4462 
4463   format %{ "EAX" %}
4464   interface(REG_INTER);
4465 %}
4466 
4467 // Flags register, used as output of compare instructions
4468 operand eFlagsReg() %{
4469   constraint(ALLOC_IN_RC(int_flags));
4470   match(RegFlags);
4471 
4472   format %{ "EFLAGS" %}
4473   interface(REG_INTER);
4474 %}
4475 
4476 // Flags register, used as output of FLOATING POINT compare instructions
4477 operand eFlagsRegU() %{
4478   constraint(ALLOC_IN_RC(int_flags));
4479   match(RegFlags);
4480 
4481   format %{ "EFLAGS_U" %}
4482   interface(REG_INTER);
4483 %}
4484 
4485 operand eFlagsRegUCF() %{
4486   constraint(ALLOC_IN_RC(int_flags));
4487   match(RegFlags);
4488   predicate(false);
4489 
4490   format %{ "EFLAGS_U_CF" %}
4491   interface(REG_INTER);
4492 %}
4493 
4494 // Condition Code Register used by long compare
4495 operand flagsReg_long_LTGE() %{
4496   constraint(ALLOC_IN_RC(int_flags));
4497   match(RegFlags);
4498   format %{ "FLAGS_LTGE" %}
4499   interface(REG_INTER);
4500 %}
4501 operand flagsReg_long_EQNE() %{
4502   constraint(ALLOC_IN_RC(int_flags));
4503   match(RegFlags);
4504   format %{ "FLAGS_EQNE" %}
4505   interface(REG_INTER);
4506 %}
4507 operand flagsReg_long_LEGT() %{
4508   constraint(ALLOC_IN_RC(int_flags));
4509   match(RegFlags);
4510   format %{ "FLAGS_LEGT" %}
4511   interface(REG_INTER);
4512 %}
4513 
4514 // Float register operands
4515 operand regDPR() %{
4516   predicate( UseSSE < 2 );
4517   constraint(ALLOC_IN_RC(fp_dbl_reg));
4518   match(RegD);
4519   match(regDPR1);
4520   match(regDPR2);
4521   format %{ %}
4522   interface(REG_INTER);
4523 %}
4524 
4525 operand regDPR1(regDPR reg) %{
4526   predicate( UseSSE < 2 );
4527   constraint(ALLOC_IN_RC(fp_dbl_reg0));
4528   match(reg);
4529   format %{ "FPR1" %}
4530   interface(REG_INTER);
4531 %}
4532 
4533 operand regDPR2(regDPR reg) %{
4534   predicate( UseSSE < 2 );
4535   constraint(ALLOC_IN_RC(fp_dbl_reg1));
4536   match(reg);
4537   format %{ "FPR2" %}
4538   interface(REG_INTER);
4539 %}
4540 
4541 operand regnotDPR1(regDPR reg) %{
4542   predicate( UseSSE < 2 );
4543   constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4544   match(reg);
4545   format %{ %}
4546   interface(REG_INTER);
4547 %}
4548 
4549 // Float register operands
4550 operand regFPR() %{
4551   predicate( UseSSE < 2 );
4552   constraint(ALLOC_IN_RC(fp_flt_reg));
4553   match(RegF);
4554   match(regFPR1);
4555   format %{ %}
4556   interface(REG_INTER);
4557 %}
4558 
4559 // Float register operands
4560 operand regFPR1(regFPR reg) %{
4561   predicate( UseSSE < 2 );
4562   constraint(ALLOC_IN_RC(fp_flt_reg0));
4563   match(reg);
4564   format %{ "FPR1" %}
4565   interface(REG_INTER);
4566 %}
4567 
4568 // XMM Float register operands
4569 operand regF() %{
4570   predicate( UseSSE>=1 );
4571   constraint(ALLOC_IN_RC(float_reg));
4572   match(RegF);
4573   format %{ %}
4574   interface(REG_INTER);
4575 %}
4576 
4577 // XMM Double register operands
4578 operand regD() %{
4579   predicate( UseSSE>=2 );
4580   constraint(ALLOC_IN_RC(double_reg));
4581   match(RegD);
4582   format %{ %}
4583   interface(REG_INTER);
4584 %}
4585 
4586 
4587 //----------Memory Operands----------------------------------------------------
4588 // Direct Memory Operand
4589 operand direct(immP addr) %{
4590   match(addr);
4591 
4592   format %{ "[$addr]" %}
4593   interface(MEMORY_INTER) %{
4594     base(0xFFFFFFFF);
4595     index(0x4);
4596     scale(0x0);
4597     disp($addr);
4598   %}
4599 %}
4600 
4601 // Indirect Memory Operand
4602 operand indirect(eRegP reg) %{
4603   constraint(ALLOC_IN_RC(int_reg));
4604   match(reg);
4605 
4606   format %{ "[$reg]" %}
4607   interface(MEMORY_INTER) %{
4608     base($reg);
4609     index(0x4);
4610     scale(0x0);
4611     disp(0x0);
4612   %}
4613 %}
4614 
4615 // Indirect Memory Plus Short Offset Operand
4616 operand indOffset8(eRegP reg, immI8 off) %{
4617   match(AddP reg off);
4618 
4619   format %{ "[$reg + $off]" %}
4620   interface(MEMORY_INTER) %{
4621     base($reg);
4622     index(0x4);
4623     scale(0x0);
4624     disp($off);
4625   %}
4626 %}
4627 
4628 // Indirect Memory Plus Long Offset Operand
4629 operand indOffset32(eRegP reg, immI off) %{
4630   match(AddP reg off);
4631 
4632   format %{ "[$reg + $off]" %}
4633   interface(MEMORY_INTER) %{
4634     base($reg);
4635     index(0x4);
4636     scale(0x0);
4637     disp($off);
4638   %}
4639 %}
4640 
4641 // Indirect Memory Plus Long Offset Operand
4642 operand indOffset32X(rRegI reg, immP off) %{
4643   match(AddP off reg);
4644 
4645   format %{ "[$reg + $off]" %}
4646   interface(MEMORY_INTER) %{
4647     base($reg);
4648     index(0x4);
4649     scale(0x0);
4650     disp($off);
4651   %}
4652 %}
4653 
4654 // Indirect Memory Plus Index Register Plus Offset Operand
4655 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4656   match(AddP (AddP reg ireg) off);
4657 
4658   op_cost(10);
4659   format %{"[$reg + $off + $ireg]" %}
4660   interface(MEMORY_INTER) %{
4661     base($reg);
4662     index($ireg);
4663     scale(0x0);
4664     disp($off);
4665   %}
4666 %}
4667 
4668 // Indirect Memory Plus Index Register Plus Offset Operand
4669 operand indIndex(eRegP reg, rRegI ireg) %{
4670   match(AddP reg ireg);
4671 
4672   op_cost(10);
4673   format %{"[$reg + $ireg]" %}
4674   interface(MEMORY_INTER) %{
4675     base($reg);
4676     index($ireg);
4677     scale(0x0);
4678     disp(0x0);
4679   %}
4680 %}
4681 
4682 // // -------------------------------------------------------------------------
4683 // // 486 architecture doesn't support "scale * index + offset" with out a base
4684 // // -------------------------------------------------------------------------
4685 // // Scaled Memory Operands
4686 // // Indirect Memory Times Scale Plus Offset Operand
4687 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4688 //   match(AddP off (LShiftI ireg scale));
4689 //
4690 //   op_cost(10);
4691 //   format %{"[$off + $ireg << $scale]" %}
4692 //   interface(MEMORY_INTER) %{
4693 //     base(0x4);
4694 //     index($ireg);
4695 //     scale($scale);
4696 //     disp($off);
4697 //   %}
4698 // %}
4699 
4700 // Indirect Memory Times Scale Plus Index Register
4701 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4702   match(AddP reg (LShiftI ireg scale));
4703 
4704   op_cost(10);
4705   format %{"[$reg + $ireg << $scale]" %}
4706   interface(MEMORY_INTER) %{
4707     base($reg);
4708     index($ireg);
4709     scale($scale);
4710     disp(0x0);
4711   %}
4712 %}
4713 
4714 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4715 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4716   match(AddP (AddP reg (LShiftI ireg scale)) off);
4717 
4718   op_cost(10);
4719   format %{"[$reg + $off + $ireg << $scale]" %}
4720   interface(MEMORY_INTER) %{
4721     base($reg);
4722     index($ireg);
4723     scale($scale);
4724     disp($off);
4725   %}
4726 %}
4727 
4728 //----------Load Long Memory Operands------------------------------------------
4729 // The load-long idiom will use it's address expression again after loading
4730 // the first word of the long.  If the load-long destination overlaps with
4731 // registers used in the addressing expression, the 2nd half will be loaded
4732 // from a clobbered address.  Fix this by requiring that load-long use
4733 // address registers that do not overlap with the load-long target.
4734 
4735 // load-long support
4736 operand load_long_RegP() %{
4737   constraint(ALLOC_IN_RC(esi_reg));
4738   match(RegP);
4739   match(eSIRegP);
4740   op_cost(100);
4741   format %{  %}
4742   interface(REG_INTER);
4743 %}
4744 
4745 // Indirect Memory Operand Long
4746 operand load_long_indirect(load_long_RegP reg) %{
4747   constraint(ALLOC_IN_RC(esi_reg));
4748   match(reg);
4749 
4750   format %{ "[$reg]" %}
4751   interface(MEMORY_INTER) %{
4752     base($reg);
4753     index(0x4);
4754     scale(0x0);
4755     disp(0x0);
4756   %}
4757 %}
4758 
4759 // Indirect Memory Plus Long Offset Operand
4760 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4761   match(AddP reg off);
4762 
4763   format %{ "[$reg + $off]" %}
4764   interface(MEMORY_INTER) %{
4765     base($reg);
4766     index(0x4);
4767     scale(0x0);
4768     disp($off);
4769   %}
4770 %}
4771 
4772 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4773 
4774 
4775 //----------Special Memory Operands--------------------------------------------
4776 // Stack Slot Operand - This operand is used for loading and storing temporary
4777 //                      values on the stack where a match requires a value to
4778 //                      flow through memory.
4779 operand stackSlotP(sRegP reg) %{
4780   constraint(ALLOC_IN_RC(stack_slots));
4781   // No match rule because this operand is only generated in matching
4782   format %{ "[$reg]" %}
4783   interface(MEMORY_INTER) %{
4784     base(0x4);   // ESP
4785     index(0x4);  // No Index
4786     scale(0x0);  // No Scale
4787     disp($reg);  // Stack Offset
4788   %}
4789 %}
4790 
4791 operand stackSlotI(sRegI reg) %{
4792   constraint(ALLOC_IN_RC(stack_slots));
4793   // No match rule because this operand is only generated in matching
4794   format %{ "[$reg]" %}
4795   interface(MEMORY_INTER) %{
4796     base(0x4);   // ESP
4797     index(0x4);  // No Index
4798     scale(0x0);  // No Scale
4799     disp($reg);  // Stack Offset
4800   %}
4801 %}
4802 
4803 operand stackSlotF(sRegF reg) %{
4804   constraint(ALLOC_IN_RC(stack_slots));
4805   // No match rule because this operand is only generated in matching
4806   format %{ "[$reg]" %}
4807   interface(MEMORY_INTER) %{
4808     base(0x4);   // ESP
4809     index(0x4);  // No Index
4810     scale(0x0);  // No Scale
4811     disp($reg);  // Stack Offset
4812   %}
4813 %}
4814 
4815 operand stackSlotD(sRegD reg) %{
4816   constraint(ALLOC_IN_RC(stack_slots));
4817   // No match rule because this operand is only generated in matching
4818   format %{ "[$reg]" %}
4819   interface(MEMORY_INTER) %{
4820     base(0x4);   // ESP
4821     index(0x4);  // No Index
4822     scale(0x0);  // No Scale
4823     disp($reg);  // Stack Offset
4824   %}
4825 %}
4826 
4827 operand stackSlotL(sRegL reg) %{
4828   constraint(ALLOC_IN_RC(stack_slots));
4829   // No match rule because this operand is only generated in matching
4830   format %{ "[$reg]" %}
4831   interface(MEMORY_INTER) %{
4832     base(0x4);   // ESP
4833     index(0x4);  // No Index
4834     scale(0x0);  // No Scale
4835     disp($reg);  // Stack Offset
4836   %}
4837 %}
4838 
4839 //----------Memory Operands - Win95 Implicit Null Variants----------------
4840 // Indirect Memory Operand
4841 operand indirect_win95_safe(eRegP_no_EBP reg)
4842 %{
4843   constraint(ALLOC_IN_RC(int_reg));
4844   match(reg);
4845 
4846   op_cost(100);
4847   format %{ "[$reg]" %}
4848   interface(MEMORY_INTER) %{
4849     base($reg);
4850     index(0x4);
4851     scale(0x0);
4852     disp(0x0);
4853   %}
4854 %}
4855 
4856 // Indirect Memory Plus Short Offset Operand
4857 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4858 %{
4859   match(AddP reg off);
4860 
4861   op_cost(100);
4862   format %{ "[$reg + $off]" %}
4863   interface(MEMORY_INTER) %{
4864     base($reg);
4865     index(0x4);
4866     scale(0x0);
4867     disp($off);
4868   %}
4869 %}
4870 
4871 // Indirect Memory Plus Long Offset Operand
4872 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4873 %{
4874   match(AddP reg off);
4875 
4876   op_cost(100);
4877   format %{ "[$reg + $off]" %}
4878   interface(MEMORY_INTER) %{
4879     base($reg);
4880     index(0x4);
4881     scale(0x0);
4882     disp($off);
4883   %}
4884 %}
4885 
4886 // Indirect Memory Plus Index Register Plus Offset Operand
4887 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4888 %{
4889   match(AddP (AddP reg ireg) off);
4890 
4891   op_cost(100);
4892   format %{"[$reg + $off + $ireg]" %}
4893   interface(MEMORY_INTER) %{
4894     base($reg);
4895     index($ireg);
4896     scale(0x0);
4897     disp($off);
4898   %}
4899 %}
4900 
4901 // Indirect Memory Times Scale Plus Index Register
4902 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4903 %{
4904   match(AddP reg (LShiftI ireg scale));
4905 
4906   op_cost(100);
4907   format %{"[$reg + $ireg << $scale]" %}
4908   interface(MEMORY_INTER) %{
4909     base($reg);
4910     index($ireg);
4911     scale($scale);
4912     disp(0x0);
4913   %}
4914 %}
4915 
4916 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4917 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4918 %{
4919   match(AddP (AddP reg (LShiftI ireg scale)) off);
4920 
4921   op_cost(100);
4922   format %{"[$reg + $off + $ireg << $scale]" %}
4923   interface(MEMORY_INTER) %{
4924     base($reg);
4925     index($ireg);
4926     scale($scale);
4927     disp($off);
4928   %}
4929 %}
4930 
4931 //----------Conditional Branch Operands----------------------------------------
4932 // Comparison Op  - This is the operation of the comparison, and is limited to
4933 //                  the following set of codes:
4934 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4935 //
4936 // Other attributes of the comparison, such as unsignedness, are specified
4937 // by the comparison instruction that sets a condition code flags register.
4938 // That result is represented by a flags operand whose subtype is appropriate
4939 // to the unsignedness (etc.) of the comparison.
4940 //
4941 // Later, the instruction which matches both the Comparison Op (a Bool) and
4942 // the flags (produced by the Cmp) specifies the coding of the comparison op
4943 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4944 
4945 // Comparision Code
4946 operand cmpOp() %{
4947   match(Bool);
4948 
4949   format %{ "" %}
4950   interface(COND_INTER) %{
4951     equal(0x4, "e");
4952     not_equal(0x5, "ne");
4953     less(0xC, "l");
4954     greater_equal(0xD, "ge");
4955     less_equal(0xE, "le");
4956     greater(0xF, "g");
4957     overflow(0x0, "o");
4958     no_overflow(0x1, "no");
4959   %}
4960 %}
4961 
4962 // Comparison Code, unsigned compare.  Used by FP also, with
4963 // C2 (unordered) turned into GT or LT already.  The other bits
4964 // C0 and C3 are turned into Carry & Zero flags.
4965 operand cmpOpU() %{
4966   match(Bool);
4967 
4968   format %{ "" %}
4969   interface(COND_INTER) %{
4970     equal(0x4, "e");
4971     not_equal(0x5, "ne");
4972     less(0x2, "b");
4973     greater_equal(0x3, "nb");
4974     less_equal(0x6, "be");
4975     greater(0x7, "nbe");
4976     overflow(0x0, "o");
4977     no_overflow(0x1, "no");
4978   %}
4979 %}
4980 
4981 // Floating comparisons that don't require any fixup for the unordered case
4982 operand cmpOpUCF() %{
4983   match(Bool);
4984   predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4985             n->as_Bool()->_test._test == BoolTest::ge ||
4986             n->as_Bool()->_test._test == BoolTest::le ||
4987             n->as_Bool()->_test._test == BoolTest::gt);
4988   format %{ "" %}
4989   interface(COND_INTER) %{
4990     equal(0x4, "e");
4991     not_equal(0x5, "ne");
4992     less(0x2, "b");
4993     greater_equal(0x3, "nb");
4994     less_equal(0x6, "be");
4995     greater(0x7, "nbe");
4996     overflow(0x0, "o");
4997     no_overflow(0x1, "no");
4998   %}
4999 %}
5000 
5001 
5002 // Floating comparisons that can be fixed up with extra conditional jumps
5003 operand cmpOpUCF2() %{
5004   match(Bool);
5005   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5006             n->as_Bool()->_test._test == BoolTest::eq);
5007   format %{ "" %}
5008   interface(COND_INTER) %{
5009     equal(0x4, "e");
5010     not_equal(0x5, "ne");
5011     less(0x2, "b");
5012     greater_equal(0x3, "nb");
5013     less_equal(0x6, "be");
5014     greater(0x7, "nbe");
5015     overflow(0x0, "o");
5016     no_overflow(0x1, "no");
5017   %}
5018 %}
5019 
5020 // Comparison Code for FP conditional move
5021 operand cmpOp_fcmov() %{
5022   match(Bool);
5023 
5024   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
5025             n->as_Bool()->_test._test != BoolTest::no_overflow);
5026   format %{ "" %}
5027   interface(COND_INTER) %{
5028     equal        (0x0C8);
5029     not_equal    (0x1C8);
5030     less         (0x0C0);
5031     greater_equal(0x1C0);
5032     less_equal   (0x0D0);
5033     greater      (0x1D0);
5034     overflow(0x0, "o"); // not really supported by the instruction
5035     no_overflow(0x1, "no"); // not really supported by the instruction
5036   %}
5037 %}
5038 
5039 // Comparision Code used in long compares
5040 operand cmpOp_commute() %{
5041   match(Bool);
5042 
5043   format %{ "" %}
5044   interface(COND_INTER) %{
5045     equal(0x4, "e");
5046     not_equal(0x5, "ne");
5047     less(0xF, "g");
5048     greater_equal(0xE, "le");
5049     less_equal(0xD, "ge");
5050     greater(0xC, "l");
5051     overflow(0x0, "o");
5052     no_overflow(0x1, "no");
5053   %}
5054 %}
5055 
5056 //----------OPERAND CLASSES----------------------------------------------------
5057 // Operand Classes are groups of operands that are used as to simplify
5058 // instruction definitions by not requiring the AD writer to specify separate
5059 // instructions for every form of operand when the instruction accepts
5060 // multiple operand types with the same basic encoding and format.  The classic
5061 // case of this is memory operands.
5062 
5063 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5064                indIndex, indIndexScale, indIndexScaleOffset);
5065 
5066 // Long memory operations are encoded in 2 instructions and a +4 offset.
5067 // This means some kind of offset is always required and you cannot use
5068 // an oop as the offset (done when working on static globals).
5069 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5070                     indIndex, indIndexScale, indIndexScaleOffset);
5071 
5072 
5073 //----------PIPELINE-----------------------------------------------------------
5074 // Rules which define the behavior of the target architectures pipeline.
5075 pipeline %{
5076 
5077 //----------ATTRIBUTES---------------------------------------------------------
5078 attributes %{
5079   variable_size_instructions;        // Fixed size instructions
5080   max_instructions_per_bundle = 3;   // Up to 3 instructions per bundle
5081   instruction_unit_size = 1;         // An instruction is 1 bytes long
5082   instruction_fetch_unit_size = 16;  // The processor fetches one line
5083   instruction_fetch_units = 1;       // of 16 bytes
5084 
5085   // List of nop instructions
5086   nops( MachNop );
5087 %}
5088 
5089 //----------RESOURCES----------------------------------------------------------
5090 // Resources are the functional units available to the machine
5091 
5092 // Generic P2/P3 pipeline
5093 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5094 // 3 instructions decoded per cycle.
5095 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5096 // 2 ALU op, only ALU0 handles mul/div instructions.
5097 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5098            MS0, MS1, MEM = MS0 | MS1,
5099            BR, FPU,
5100            ALU0, ALU1, ALU = ALU0 | ALU1 );
5101 
5102 //----------PIPELINE DESCRIPTION-----------------------------------------------
5103 // Pipeline Description specifies the stages in the machine's pipeline
5104 
5105 // Generic P2/P3 pipeline
5106 pipe_desc(S0, S1, S2, S3, S4, S5);
5107 
5108 //----------PIPELINE CLASSES---------------------------------------------------
5109 // Pipeline Classes describe the stages in which input and output are
5110 // referenced by the hardware pipeline.
5111 
5112 // Naming convention: ialu or fpu
5113 // Then: _reg
5114 // Then: _reg if there is a 2nd register
5115 // Then: _long if it's a pair of instructions implementing a long
5116 // Then: _fat if it requires the big decoder
5117 //   Or: _mem if it requires the big decoder and a memory unit.
5118 
5119 // Integer ALU reg operation
5120 pipe_class ialu_reg(rRegI dst) %{
5121     single_instruction;
5122     dst    : S4(write);
5123     dst    : S3(read);
5124     DECODE : S0;        // any decoder
5125     ALU    : S3;        // any alu
5126 %}
5127 
5128 // Long ALU reg operation
5129 pipe_class ialu_reg_long(eRegL dst) %{
5130     instruction_count(2);
5131     dst    : S4(write);
5132     dst    : S3(read);
5133     DECODE : S0(2);     // any 2 decoders
5134     ALU    : S3(2);     // both alus
5135 %}
5136 
5137 // Integer ALU reg operation using big decoder
5138 pipe_class ialu_reg_fat(rRegI dst) %{
5139     single_instruction;
5140     dst    : S4(write);
5141     dst    : S3(read);
5142     D0     : S0;        // big decoder only
5143     ALU    : S3;        // any alu
5144 %}
5145 
5146 // Long ALU reg operation using big decoder
5147 pipe_class ialu_reg_long_fat(eRegL dst) %{
5148     instruction_count(2);
5149     dst    : S4(write);
5150     dst    : S3(read);
5151     D0     : S0(2);     // big decoder only; twice
5152     ALU    : S3(2);     // any 2 alus
5153 %}
5154 
5155 // Integer ALU reg-reg operation
5156 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5157     single_instruction;
5158     dst    : S4(write);
5159     src    : S3(read);
5160     DECODE : S0;        // any decoder
5161     ALU    : S3;        // any alu
5162 %}
5163 
5164 // Long ALU reg-reg operation
5165 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5166     instruction_count(2);
5167     dst    : S4(write);
5168     src    : S3(read);
5169     DECODE : S0(2);     // any 2 decoders
5170     ALU    : S3(2);     // both alus
5171 %}
5172 
5173 // Integer ALU reg-reg operation
5174 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5175     single_instruction;
5176     dst    : S4(write);
5177     src    : S3(read);
5178     D0     : S0;        // big decoder only
5179     ALU    : S3;        // any alu
5180 %}
5181 
5182 // Long ALU reg-reg operation
5183 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5184     instruction_count(2);
5185     dst    : S4(write);
5186     src    : S3(read);
5187     D0     : S0(2);     // big decoder only; twice
5188     ALU    : S3(2);     // both alus
5189 %}
5190 
5191 // Integer ALU reg-mem operation
5192 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5193     single_instruction;
5194     dst    : S5(write);
5195     mem    : S3(read);
5196     D0     : S0;        // big decoder only
5197     ALU    : S4;        // any alu
5198     MEM    : S3;        // any mem
5199 %}
5200 
5201 // Long ALU reg-mem operation
5202 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5203     instruction_count(2);
5204     dst    : S5(write);
5205     mem    : S3(read);
5206     D0     : S0(2);     // big decoder only; twice
5207     ALU    : S4(2);     // any 2 alus
5208     MEM    : S3(2);     // both mems
5209 %}
5210 
5211 // Integer mem operation (prefetch)
5212 pipe_class ialu_mem(memory mem)
5213 %{
5214     single_instruction;
5215     mem    : S3(read);
5216     D0     : S0;        // big decoder only
5217     MEM    : S3;        // any mem
5218 %}
5219 
5220 // Integer Store to Memory
5221 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5222     single_instruction;
5223     mem    : S3(read);
5224     src    : S5(read);
5225     D0     : S0;        // big decoder only
5226     ALU    : S4;        // any alu
5227     MEM    : S3;
5228 %}
5229 
5230 // Long Store to Memory
5231 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5232     instruction_count(2);
5233     mem    : S3(read);
5234     src    : S5(read);
5235     D0     : S0(2);     // big decoder only; twice
5236     ALU    : S4(2);     // any 2 alus
5237     MEM    : S3(2);     // Both mems
5238 %}
5239 
5240 // Integer Store to Memory
5241 pipe_class ialu_mem_imm(memory mem) %{
5242     single_instruction;
5243     mem    : S3(read);
5244     D0     : S0;        // big decoder only
5245     ALU    : S4;        // any alu
5246     MEM    : S3;
5247 %}
5248 
5249 // Integer ALU0 reg-reg operation
5250 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5251     single_instruction;
5252     dst    : S4(write);
5253     src    : S3(read);
5254     D0     : S0;        // Big decoder only
5255     ALU0   : S3;        // only alu0
5256 %}
5257 
5258 // Integer ALU0 reg-mem operation
5259 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5260     single_instruction;
5261     dst    : S5(write);
5262     mem    : S3(read);
5263     D0     : S0;        // big decoder only
5264     ALU0   : S4;        // ALU0 only
5265     MEM    : S3;        // any mem
5266 %}
5267 
5268 // Integer ALU reg-reg operation
5269 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5270     single_instruction;
5271     cr     : S4(write);
5272     src1   : S3(read);
5273     src2   : S3(read);
5274     DECODE : S0;        // any decoder
5275     ALU    : S3;        // any alu
5276 %}
5277 
5278 // Integer ALU reg-imm operation
5279 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5280     single_instruction;
5281     cr     : S4(write);
5282     src1   : S3(read);
5283     DECODE : S0;        // any decoder
5284     ALU    : S3;        // any alu
5285 %}
5286 
5287 // Integer ALU reg-mem operation
5288 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5289     single_instruction;
5290     cr     : S4(write);
5291     src1   : S3(read);
5292     src2   : S3(read);
5293     D0     : S0;        // big decoder only
5294     ALU    : S4;        // any alu
5295     MEM    : S3;
5296 %}
5297 
5298 // Conditional move reg-reg
5299 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5300     instruction_count(4);
5301     y      : S4(read);
5302     q      : S3(read);
5303     p      : S3(read);
5304     DECODE : S0(4);     // any decoder
5305 %}
5306 
5307 // Conditional move reg-reg
5308 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5309     single_instruction;
5310     dst    : S4(write);
5311     src    : S3(read);
5312     cr     : S3(read);
5313     DECODE : S0;        // any decoder
5314 %}
5315 
5316 // Conditional move reg-mem
5317 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5318     single_instruction;
5319     dst    : S4(write);
5320     src    : S3(read);
5321     cr     : S3(read);
5322     DECODE : S0;        // any decoder
5323     MEM    : S3;
5324 %}
5325 
5326 // Conditional move reg-reg long
5327 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5328     single_instruction;
5329     dst    : S4(write);
5330     src    : S3(read);
5331     cr     : S3(read);
5332     DECODE : S0(2);     // any 2 decoders
5333 %}
5334 
5335 // Conditional move double reg-reg
5336 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5337     single_instruction;
5338     dst    : S4(write);
5339     src    : S3(read);
5340     cr     : S3(read);
5341     DECODE : S0;        // any decoder
5342 %}
5343 
5344 // Float reg-reg operation
5345 pipe_class fpu_reg(regDPR dst) %{
5346     instruction_count(2);
5347     dst    : S3(read);
5348     DECODE : S0(2);     // any 2 decoders
5349     FPU    : S3;
5350 %}
5351 
5352 // Float reg-reg operation
5353 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5354     instruction_count(2);
5355     dst    : S4(write);
5356     src    : S3(read);
5357     DECODE : S0(2);     // any 2 decoders
5358     FPU    : S3;
5359 %}
5360 
5361 // Float reg-reg operation
5362 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5363     instruction_count(3);
5364     dst    : S4(write);
5365     src1   : S3(read);
5366     src2   : S3(read);
5367     DECODE : S0(3);     // any 3 decoders
5368     FPU    : S3(2);
5369 %}
5370 
5371 // Float reg-reg operation
5372 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5373     instruction_count(4);
5374     dst    : S4(write);
5375     src1   : S3(read);
5376     src2   : S3(read);
5377     src3   : S3(read);
5378     DECODE : S0(4);     // any 3 decoders
5379     FPU    : S3(2);
5380 %}
5381 
5382 // Float reg-reg operation
5383 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5384     instruction_count(4);
5385     dst    : S4(write);
5386     src1   : S3(read);
5387     src2   : S3(read);
5388     src3   : S3(read);
5389     DECODE : S1(3);     // any 3 decoders
5390     D0     : S0;        // Big decoder only
5391     FPU    : S3(2);
5392     MEM    : S3;
5393 %}
5394 
5395 // Float reg-mem operation
5396 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5397     instruction_count(2);
5398     dst    : S5(write);
5399     mem    : S3(read);
5400     D0     : S0;        // big decoder only
5401     DECODE : S1;        // any decoder for FPU POP
5402     FPU    : S4;
5403     MEM    : S3;        // any mem
5404 %}
5405 
5406 // Float reg-mem operation
5407 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5408     instruction_count(3);
5409     dst    : S5(write);
5410     src1   : S3(read);
5411     mem    : S3(read);
5412     D0     : S0;        // big decoder only
5413     DECODE : S1(2);     // any decoder for FPU POP
5414     FPU    : S4;
5415     MEM    : S3;        // any mem
5416 %}
5417 
5418 // Float mem-reg operation
5419 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5420     instruction_count(2);
5421     src    : S5(read);
5422     mem    : S3(read);
5423     DECODE : S0;        // any decoder for FPU PUSH
5424     D0     : S1;        // big decoder only
5425     FPU    : S4;
5426     MEM    : S3;        // any mem
5427 %}
5428 
5429 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5430     instruction_count(3);
5431     src1   : S3(read);
5432     src2   : S3(read);
5433     mem    : S3(read);
5434     DECODE : S0(2);     // any decoder for FPU PUSH
5435     D0     : S1;        // big decoder only
5436     FPU    : S4;
5437     MEM    : S3;        // any mem
5438 %}
5439 
5440 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5441     instruction_count(3);
5442     src1   : S3(read);
5443     src2   : S3(read);
5444     mem    : S4(read);
5445     DECODE : S0;        // any decoder for FPU PUSH
5446     D0     : S0(2);     // big decoder only
5447     FPU    : S4;
5448     MEM    : S3(2);     // any mem
5449 %}
5450 
5451 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5452     instruction_count(2);
5453     src1   : S3(read);
5454     dst    : S4(read);
5455     D0     : S0(2);     // big decoder only
5456     MEM    : S3(2);     // any mem
5457 %}
5458 
5459 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5460     instruction_count(3);
5461     src1   : S3(read);
5462     src2   : S3(read);
5463     dst    : S4(read);
5464     D0     : S0(3);     // big decoder only
5465     FPU    : S4;
5466     MEM    : S3(3);     // any mem
5467 %}
5468 
5469 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5470     instruction_count(3);
5471     src1   : S4(read);
5472     mem    : S4(read);
5473     DECODE : S0;        // any decoder for FPU PUSH
5474     D0     : S0(2);     // big decoder only
5475     FPU    : S4;
5476     MEM    : S3(2);     // any mem
5477 %}
5478 
5479 // Float load constant
5480 pipe_class fpu_reg_con(regDPR dst) %{
5481     instruction_count(2);
5482     dst    : S5(write);
5483     D0     : S0;        // big decoder only for the load
5484     DECODE : S1;        // any decoder for FPU POP
5485     FPU    : S4;
5486     MEM    : S3;        // any mem
5487 %}
5488 
5489 // Float load constant
5490 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5491     instruction_count(3);
5492     dst    : S5(write);
5493     src    : S3(read);
5494     D0     : S0;        // big decoder only for the load
5495     DECODE : S1(2);     // any decoder for FPU POP
5496     FPU    : S4;
5497     MEM    : S3;        // any mem
5498 %}
5499 
5500 // UnConditional branch
5501 pipe_class pipe_jmp( label labl ) %{
5502     single_instruction;
5503     BR   : S3;
5504 %}
5505 
5506 // Conditional branch
5507 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5508     single_instruction;
5509     cr    : S1(read);
5510     BR    : S3;
5511 %}
5512 
5513 // Allocation idiom
5514 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5515     instruction_count(1); force_serialization;
5516     fixed_latency(6);
5517     heap_ptr : S3(read);
5518     DECODE   : S0(3);
5519     D0       : S2;
5520     MEM      : S3;
5521     ALU      : S3(2);
5522     dst      : S5(write);
5523     BR       : S5;
5524 %}
5525 
5526 // Generic big/slow expanded idiom
5527 pipe_class pipe_slow(  ) %{
5528     instruction_count(10); multiple_bundles; force_serialization;
5529     fixed_latency(100);
5530     D0  : S0(2);
5531     MEM : S3(2);
5532 %}
5533 
5534 // The real do-nothing guy
5535 pipe_class empty( ) %{
5536     instruction_count(0);
5537 %}
5538 
5539 // Define the class for the Nop node
5540 define %{
5541    MachNop = empty;
5542 %}
5543 
5544 %}
5545 
5546 //----------INSTRUCTIONS-------------------------------------------------------
5547 //
5548 // match      -- States which machine-independent subtree may be replaced
5549 //               by this instruction.
5550 // ins_cost   -- The estimated cost of this instruction is used by instruction
5551 //               selection to identify a minimum cost tree of machine
5552 //               instructions that matches a tree of machine-independent
5553 //               instructions.
5554 // format     -- A string providing the disassembly for this instruction.
5555 //               The value of an instruction's operand may be inserted
5556 //               by referring to it with a '$' prefix.
5557 // opcode     -- Three instruction opcodes may be provided.  These are referred
5558 //               to within an encode class as $primary, $secondary, and $tertiary
5559 //               respectively.  The primary opcode is commonly used to
5560 //               indicate the type of machine instruction, while secondary
5561 //               and tertiary are often used for prefix options or addressing
5562 //               modes.
5563 // ins_encode -- A list of encode classes with parameters. The encode class
5564 //               name must have been defined in an 'enc_class' specification
5565 //               in the encode section of the architecture description.
5566 
5567 //----------BSWAP-Instruction--------------------------------------------------
5568 instruct bytes_reverse_int(rRegI dst) %{
5569   match(Set dst (ReverseBytesI dst));
5570 
5571   format %{ "BSWAP  $dst" %}
5572   opcode(0x0F, 0xC8);
5573   ins_encode( OpcP, OpcSReg(dst) );
5574   ins_pipe( ialu_reg );
5575 %}
5576 
5577 instruct bytes_reverse_long(eRegL dst) %{
5578   match(Set dst (ReverseBytesL dst));
5579 
5580   format %{ "BSWAP  $dst.lo\n\t"
5581             "BSWAP  $dst.hi\n\t"
5582             "XCHG   $dst.lo $dst.hi" %}
5583 
5584   ins_cost(125);
5585   ins_encode( bswap_long_bytes(dst) );
5586   ins_pipe( ialu_reg_reg);
5587 %}
5588 
5589 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5590   match(Set dst (ReverseBytesUS dst));
5591   effect(KILL cr);
5592 
5593   format %{ "BSWAP  $dst\n\t" 
5594             "SHR    $dst,16\n\t" %}
5595   ins_encode %{
5596     __ bswapl($dst$$Register);
5597     __ shrl($dst$$Register, 16); 
5598   %}
5599   ins_pipe( ialu_reg );
5600 %}
5601 
5602 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5603   match(Set dst (ReverseBytesS dst));
5604   effect(KILL cr);
5605 
5606   format %{ "BSWAP  $dst\n\t" 
5607             "SAR    $dst,16\n\t" %}
5608   ins_encode %{
5609     __ bswapl($dst$$Register);
5610     __ sarl($dst$$Register, 16); 
5611   %}
5612   ins_pipe( ialu_reg );
5613 %}
5614 
5615 
5616 //---------- Zeros Count Instructions ------------------------------------------
5617 
5618 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5619   predicate(UseCountLeadingZerosInstruction);
5620   match(Set dst (CountLeadingZerosI src));
5621   effect(KILL cr);
5622 
5623   format %{ "LZCNT  $dst, $src\t# count leading zeros (int)" %}
5624   ins_encode %{
5625     __ lzcntl($dst$$Register, $src$$Register);
5626   %}
5627   ins_pipe(ialu_reg);
5628 %}
5629 
5630 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5631   predicate(!UseCountLeadingZerosInstruction);
5632   match(Set dst (CountLeadingZerosI src));
5633   effect(KILL cr);
5634 
5635   format %{ "BSR    $dst, $src\t# count leading zeros (int)\n\t"
5636             "JNZ    skip\n\t"
5637             "MOV    $dst, -1\n"
5638       "skip:\n\t"
5639             "NEG    $dst\n\t"
5640             "ADD    $dst, 31" %}
5641   ins_encode %{
5642     Register Rdst = $dst$$Register;
5643     Register Rsrc = $src$$Register;
5644     Label skip;
5645     __ bsrl(Rdst, Rsrc);
5646     __ jccb(Assembler::notZero, skip);
5647     __ movl(Rdst, -1);
5648     __ bind(skip);
5649     __ negl(Rdst);
5650     __ addl(Rdst, BitsPerInt - 1);
5651   %}
5652   ins_pipe(ialu_reg);
5653 %}
5654 
5655 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5656   predicate(UseCountLeadingZerosInstruction);
5657   match(Set dst (CountLeadingZerosL src));
5658   effect(TEMP dst, KILL cr);
5659 
5660   format %{ "LZCNT  $dst, $src.hi\t# count leading zeros (long)\n\t"
5661             "JNC    done\n\t"
5662             "LZCNT  $dst, $src.lo\n\t"
5663             "ADD    $dst, 32\n"
5664       "done:" %}
5665   ins_encode %{
5666     Register Rdst = $dst$$Register;
5667     Register Rsrc = $src$$Register;
5668     Label done;
5669     __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5670     __ jccb(Assembler::carryClear, done);
5671     __ lzcntl(Rdst, Rsrc);
5672     __ addl(Rdst, BitsPerInt);
5673     __ bind(done);
5674   %}
5675   ins_pipe(ialu_reg);
5676 %}
5677 
5678 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5679   predicate(!UseCountLeadingZerosInstruction);
5680   match(Set dst (CountLeadingZerosL src));
5681   effect(TEMP dst, KILL cr);
5682 
5683   format %{ "BSR    $dst, $src.hi\t# count leading zeros (long)\n\t"
5684             "JZ     msw_is_zero\n\t"
5685             "ADD    $dst, 32\n\t"
5686             "JMP    not_zero\n"
5687       "msw_is_zero:\n\t"
5688             "BSR    $dst, $src.lo\n\t"
5689             "JNZ    not_zero\n\t"
5690             "MOV    $dst, -1\n"
5691       "not_zero:\n\t"
5692             "NEG    $dst\n\t"
5693             "ADD    $dst, 63\n" %}
5694  ins_encode %{
5695     Register Rdst = $dst$$Register;
5696     Register Rsrc = $src$$Register;
5697     Label msw_is_zero;
5698     Label not_zero;
5699     __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5700     __ jccb(Assembler::zero, msw_is_zero);
5701     __ addl(Rdst, BitsPerInt);
5702     __ jmpb(not_zero);
5703     __ bind(msw_is_zero);
5704     __ bsrl(Rdst, Rsrc);
5705     __ jccb(Assembler::notZero, not_zero);
5706     __ movl(Rdst, -1);
5707     __ bind(not_zero);
5708     __ negl(Rdst);
5709     __ addl(Rdst, BitsPerLong - 1);
5710   %}
5711   ins_pipe(ialu_reg);
5712 %}
5713 
5714 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5715   match(Set dst (CountTrailingZerosI src));
5716   effect(KILL cr);
5717 
5718   format %{ "BSF    $dst, $src\t# count trailing zeros (int)\n\t"
5719             "JNZ    done\n\t"
5720             "MOV    $dst, 32\n"
5721       "done:" %}
5722   ins_encode %{
5723     Register Rdst = $dst$$Register;
5724     Label done;
5725     __ bsfl(Rdst, $src$$Register);
5726     __ jccb(Assembler::notZero, done);
5727     __ movl(Rdst, BitsPerInt);
5728     __ bind(done);
5729   %}
5730   ins_pipe(ialu_reg);
5731 %}
5732 
5733 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5734   match(Set dst (CountTrailingZerosL src));
5735   effect(TEMP dst, KILL cr);
5736 
5737   format %{ "BSF    $dst, $src.lo\t# count trailing zeros (long)\n\t"
5738             "JNZ    done\n\t"
5739             "BSF    $dst, $src.hi\n\t"
5740             "JNZ    msw_not_zero\n\t"
5741             "MOV    $dst, 32\n"
5742       "msw_not_zero:\n\t"
5743             "ADD    $dst, 32\n"
5744       "done:" %}
5745   ins_encode %{
5746     Register Rdst = $dst$$Register;
5747     Register Rsrc = $src$$Register;
5748     Label msw_not_zero;
5749     Label done;
5750     __ bsfl(Rdst, Rsrc);
5751     __ jccb(Assembler::notZero, done);
5752     __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5753     __ jccb(Assembler::notZero, msw_not_zero);
5754     __ movl(Rdst, BitsPerInt);
5755     __ bind(msw_not_zero);
5756     __ addl(Rdst, BitsPerInt);
5757     __ bind(done);
5758   %}
5759   ins_pipe(ialu_reg);
5760 %}
5761 
5762 
5763 //---------- Population Count Instructions -------------------------------------
5764 
5765 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5766   predicate(UsePopCountInstruction);
5767   match(Set dst (PopCountI src));
5768   effect(KILL cr);
5769 
5770   format %{ "POPCNT $dst, $src" %}
5771   ins_encode %{
5772     __ popcntl($dst$$Register, $src$$Register);
5773   %}
5774   ins_pipe(ialu_reg);
5775 %}
5776 
5777 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5778   predicate(UsePopCountInstruction);
5779   match(Set dst (PopCountI (LoadI mem)));
5780   effect(KILL cr);
5781 
5782   format %{ "POPCNT $dst, $mem" %}
5783   ins_encode %{
5784     __ popcntl($dst$$Register, $mem$$Address);
5785   %}
5786   ins_pipe(ialu_reg);
5787 %}
5788 
5789 // Note: Long.bitCount(long) returns an int.
5790 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5791   predicate(UsePopCountInstruction);
5792   match(Set dst (PopCountL src));
5793   effect(KILL cr, TEMP tmp, TEMP dst);
5794 
5795   format %{ "POPCNT $dst, $src.lo\n\t"
5796             "POPCNT $tmp, $src.hi\n\t"
5797             "ADD    $dst, $tmp" %}
5798   ins_encode %{
5799     __ popcntl($dst$$Register, $src$$Register);
5800     __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5801     __ addl($dst$$Register, $tmp$$Register);
5802   %}
5803   ins_pipe(ialu_reg);
5804 %}
5805 
5806 // Note: Long.bitCount(long) returns an int.
5807 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5808   predicate(UsePopCountInstruction);
5809   match(Set dst (PopCountL (LoadL mem)));
5810   effect(KILL cr, TEMP tmp, TEMP dst);
5811 
5812   format %{ "POPCNT $dst, $mem\n\t"
5813             "POPCNT $tmp, $mem+4\n\t"
5814             "ADD    $dst, $tmp" %}
5815   ins_encode %{
5816     //__ popcntl($dst$$Register, $mem$$Address$$first);
5817     //__ popcntl($tmp$$Register, $mem$$Address$$second);
5818     __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none));
5819     __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none));
5820     __ addl($dst$$Register, $tmp$$Register);
5821   %}
5822   ins_pipe(ialu_reg);
5823 %}
5824 
5825 
5826 //----------Load/Store/Move Instructions---------------------------------------
5827 //----------Load Instructions--------------------------------------------------
5828 // Load Byte (8bit signed)
5829 instruct loadB(xRegI dst, memory mem) %{
5830   match(Set dst (LoadB mem));
5831 
5832   ins_cost(125);
5833   format %{ "MOVSX8 $dst,$mem\t# byte" %}
5834 
5835   ins_encode %{
5836     __ movsbl($dst$$Register, $mem$$Address);
5837   %}
5838 
5839   ins_pipe(ialu_reg_mem);
5840 %}
5841 
5842 // Load Byte (8bit signed) into Long Register
5843 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5844   match(Set dst (ConvI2L (LoadB mem)));
5845   effect(KILL cr);
5846 
5847   ins_cost(375);
5848   format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5849             "MOV    $dst.hi,$dst.lo\n\t"
5850             "SAR    $dst.hi,7" %}
5851 
5852   ins_encode %{
5853     __ movsbl($dst$$Register, $mem$$Address);
5854     __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5855     __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5856   %}
5857 
5858   ins_pipe(ialu_reg_mem);
5859 %}
5860 
5861 // Load Unsigned Byte (8bit UNsigned)
5862 instruct loadUB(xRegI dst, memory mem) %{
5863   match(Set dst (LoadUB mem));
5864 
5865   ins_cost(125);
5866   format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5867 
5868   ins_encode %{
5869     __ movzbl($dst$$Register, $mem$$Address);
5870   %}
5871 
5872   ins_pipe(ialu_reg_mem);
5873 %}
5874 
5875 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5876 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5877   match(Set dst (ConvI2L (LoadUB mem)));
5878   effect(KILL cr);
5879 
5880   ins_cost(250);
5881   format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5882             "XOR    $dst.hi,$dst.hi" %}
5883 
5884   ins_encode %{
5885     Register Rdst = $dst$$Register;
5886     __ movzbl(Rdst, $mem$$Address);
5887     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5888   %}
5889 
5890   ins_pipe(ialu_reg_mem);
5891 %}
5892 
5893 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5894 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5895   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5896   effect(KILL cr);
5897 
5898   format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5899             "XOR    $dst.hi,$dst.hi\n\t"
5900             "AND    $dst.lo,$mask" %}
5901   ins_encode %{
5902     Register Rdst = $dst$$Register;
5903     __ movzbl(Rdst, $mem$$Address);
5904     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5905     __ andl(Rdst, $mask$$constant);
5906   %}
5907   ins_pipe(ialu_reg_mem);
5908 %}
5909 
5910 // Load Short (16bit signed)
5911 instruct loadS(rRegI dst, memory mem) %{
5912   match(Set dst (LoadS mem));
5913 
5914   ins_cost(125);
5915   format %{ "MOVSX  $dst,$mem\t# short" %}
5916 
5917   ins_encode %{
5918     __ movswl($dst$$Register, $mem$$Address);
5919   %}
5920 
5921   ins_pipe(ialu_reg_mem);
5922 %}
5923 
5924 // Load Short (16 bit signed) to Byte (8 bit signed)
5925 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5926   match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5927 
5928   ins_cost(125);
5929   format %{ "MOVSX  $dst, $mem\t# short -> byte" %}
5930   ins_encode %{
5931     __ movsbl($dst$$Register, $mem$$Address);
5932   %}
5933   ins_pipe(ialu_reg_mem);
5934 %}
5935 
5936 // Load Short (16bit signed) into Long Register
5937 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5938   match(Set dst (ConvI2L (LoadS mem)));
5939   effect(KILL cr);
5940 
5941   ins_cost(375);
5942   format %{ "MOVSX  $dst.lo,$mem\t# short -> long\n\t"
5943             "MOV    $dst.hi,$dst.lo\n\t"
5944             "SAR    $dst.hi,15" %}
5945 
5946   ins_encode %{
5947     __ movswl($dst$$Register, $mem$$Address);
5948     __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5949     __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5950   %}
5951 
5952   ins_pipe(ialu_reg_mem);
5953 %}
5954 
5955 // Load Unsigned Short/Char (16bit unsigned)
5956 instruct loadUS(rRegI dst, memory mem) %{
5957   match(Set dst (LoadUS mem));
5958 
5959   ins_cost(125);
5960   format %{ "MOVZX  $dst,$mem\t# ushort/char -> int" %}
5961 
5962   ins_encode %{
5963     __ movzwl($dst$$Register, $mem$$Address);
5964   %}
5965 
5966   ins_pipe(ialu_reg_mem);
5967 %}
5968 
5969 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5970 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5971   match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5972 
5973   ins_cost(125);
5974   format %{ "MOVSX  $dst, $mem\t# ushort -> byte" %}
5975   ins_encode %{
5976     __ movsbl($dst$$Register, $mem$$Address);
5977   %}
5978   ins_pipe(ialu_reg_mem);
5979 %}
5980 
5981 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5982 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5983   match(Set dst (ConvI2L (LoadUS mem)));
5984   effect(KILL cr);
5985 
5986   ins_cost(250);
5987   format %{ "MOVZX  $dst.lo,$mem\t# ushort/char -> long\n\t"
5988             "XOR    $dst.hi,$dst.hi" %}
5989 
5990   ins_encode %{
5991     __ movzwl($dst$$Register, $mem$$Address);
5992     __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5993   %}
5994 
5995   ins_pipe(ialu_reg_mem);
5996 %}
5997 
5998 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5999 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6000   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6001   effect(KILL cr);
6002 
6003   format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6004             "XOR    $dst.hi,$dst.hi" %}
6005   ins_encode %{
6006     Register Rdst = $dst$$Register;
6007     __ movzbl(Rdst, $mem$$Address);
6008     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6009   %}
6010   ins_pipe(ialu_reg_mem);
6011 %}
6012 
6013 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6014 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6015   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6016   effect(KILL cr);
6017 
6018   format %{ "MOVZX  $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6019             "XOR    $dst.hi,$dst.hi\n\t"
6020             "AND    $dst.lo,$mask" %}
6021   ins_encode %{
6022     Register Rdst = $dst$$Register;
6023     __ movzwl(Rdst, $mem$$Address);
6024     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6025     __ andl(Rdst, $mask$$constant);
6026   %}
6027   ins_pipe(ialu_reg_mem);
6028 %}
6029 
6030 // Load Integer
6031 instruct loadI(rRegI dst, memory mem) %{
6032   match(Set dst (LoadI mem));
6033 
6034   ins_cost(125);
6035   format %{ "MOV    $dst,$mem\t# int" %}
6036 
6037   ins_encode %{
6038     __ movl($dst$$Register, $mem$$Address);
6039   %}
6040 
6041   ins_pipe(ialu_reg_mem);
6042 %}
6043 
6044 // Load Integer (32 bit signed) to Byte (8 bit signed)
6045 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6046   match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6047 
6048   ins_cost(125);
6049   format %{ "MOVSX  $dst, $mem\t# int -> byte" %}
6050   ins_encode %{
6051     __ movsbl($dst$$Register, $mem$$Address);
6052   %}
6053   ins_pipe(ialu_reg_mem);
6054 %}
6055 
6056 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6057 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6058   match(Set dst (AndI (LoadI mem) mask));
6059 
6060   ins_cost(125);
6061   format %{ "MOVZX  $dst, $mem\t# int -> ubyte" %}
6062   ins_encode %{
6063     __ movzbl($dst$$Register, $mem$$Address);
6064   %}
6065   ins_pipe(ialu_reg_mem);
6066 %}
6067 
6068 // Load Integer (32 bit signed) to Short (16 bit signed)
6069 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6070   match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6071 
6072   ins_cost(125);
6073   format %{ "MOVSX  $dst, $mem\t# int -> short" %}
6074   ins_encode %{
6075     __ movswl($dst$$Register, $mem$$Address);
6076   %}
6077   ins_pipe(ialu_reg_mem);
6078 %}
6079 
6080 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6081 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6082   match(Set dst (AndI (LoadI mem) mask));
6083 
6084   ins_cost(125);
6085   format %{ "MOVZX  $dst, $mem\t# int -> ushort/char" %}
6086   ins_encode %{
6087     __ movzwl($dst$$Register, $mem$$Address);
6088   %}
6089   ins_pipe(ialu_reg_mem);
6090 %}
6091 
6092 // Load Integer into Long Register
6093 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6094   match(Set dst (ConvI2L (LoadI mem)));
6095   effect(KILL cr);
6096 
6097   ins_cost(375);
6098   format %{ "MOV    $dst.lo,$mem\t# int -> long\n\t"
6099             "MOV    $dst.hi,$dst.lo\n\t"
6100             "SAR    $dst.hi,31" %}
6101 
6102   ins_encode %{
6103     __ movl($dst$$Register, $mem$$Address);
6104     __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6105     __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6106   %}
6107 
6108   ins_pipe(ialu_reg_mem);
6109 %}
6110 
6111 // Load Integer with mask 0xFF into Long Register
6112 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6113   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6114   effect(KILL cr);
6115 
6116   format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6117             "XOR    $dst.hi,$dst.hi" %}
6118   ins_encode %{
6119     Register Rdst = $dst$$Register;
6120     __ movzbl(Rdst, $mem$$Address);
6121     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6122   %}
6123   ins_pipe(ialu_reg_mem);
6124 %}
6125 
6126 // Load Integer with mask 0xFFFF into Long Register
6127 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6128   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6129   effect(KILL cr);
6130 
6131   format %{ "MOVZX  $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6132             "XOR    $dst.hi,$dst.hi" %}
6133   ins_encode %{
6134     Register Rdst = $dst$$Register;
6135     __ movzwl(Rdst, $mem$$Address);
6136     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6137   %}
6138   ins_pipe(ialu_reg_mem);
6139 %}
6140 
6141 // Load Integer with 31-bit mask into Long Register
6142 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{
6143   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6144   effect(KILL cr);
6145 
6146   format %{ "MOV    $dst.lo,$mem\t# int & 31-bit mask -> long\n\t"
6147             "XOR    $dst.hi,$dst.hi\n\t"
6148             "AND    $dst.lo,$mask" %}
6149   ins_encode %{
6150     Register Rdst = $dst$$Register;
6151     __ movl(Rdst, $mem$$Address);
6152     __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6153     __ andl(Rdst, $mask$$constant);
6154   %}
6155   ins_pipe(ialu_reg_mem);
6156 %}
6157 
6158 // Load Unsigned Integer into Long Register
6159 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
6160   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
6161   effect(KILL cr);
6162 
6163   ins_cost(250);
6164   format %{ "MOV    $dst.lo,$mem\t# uint -> long\n\t"
6165             "XOR    $dst.hi,$dst.hi" %}
6166 
6167   ins_encode %{
6168     __ movl($dst$$Register, $mem$$Address);
6169     __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6170   %}
6171 
6172   ins_pipe(ialu_reg_mem);
6173 %}
6174 
6175 // Load Long.  Cannot clobber address while loading, so restrict address
6176 // register to ESI
6177 instruct loadL(eRegL dst, load_long_memory mem) %{
6178   predicate(!((LoadLNode*)n)->require_atomic_access());
6179   match(Set dst (LoadL mem));
6180 
6181   ins_cost(250);
6182   format %{ "MOV    $dst.lo,$mem\t# long\n\t"
6183             "MOV    $dst.hi,$mem+4" %}
6184 
6185   ins_encode %{
6186     Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none);
6187     Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none);
6188     __ movl($dst$$Register, Amemlo);
6189     __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6190   %}
6191 
6192   ins_pipe(ialu_reg_long_mem);
6193 %}
6194 
6195 // Volatile Load Long.  Must be atomic, so do 64-bit FILD
6196 // then store it down to the stack and reload on the int
6197 // side.
6198 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6199   predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6200   match(Set dst (LoadL mem));
6201 
6202   ins_cost(200);
6203   format %{ "FILD   $mem\t# Atomic volatile long load\n\t"
6204             "FISTp  $dst" %}
6205   ins_encode(enc_loadL_volatile(mem,dst));
6206   ins_pipe( fpu_reg_mem );
6207 %}
6208 
6209 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6210   predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6211   match(Set dst (LoadL mem));
6212   effect(TEMP tmp);
6213   ins_cost(180);
6214   format %{ "MOVSD  $tmp,$mem\t# Atomic volatile long load\n\t"
6215             "MOVSD  $dst,$tmp" %}
6216   ins_encode %{
6217     __ movdbl($tmp$$XMMRegister, $mem$$Address);
6218     __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6219   %}
6220   ins_pipe( pipe_slow );
6221 %}
6222 
6223 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6224   predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6225   match(Set dst (LoadL mem));
6226   effect(TEMP tmp);
6227   ins_cost(160);
6228   format %{ "MOVSD  $tmp,$mem\t# Atomic volatile long load\n\t"
6229             "MOVD   $dst.lo,$tmp\n\t"
6230             "PSRLQ  $tmp,32\n\t"
6231             "MOVD   $dst.hi,$tmp" %}
6232   ins_encode %{
6233     __ movdbl($tmp$$XMMRegister, $mem$$Address);
6234     __ movdl($dst$$Register, $tmp$$XMMRegister);
6235     __ psrlq($tmp$$XMMRegister, 32);
6236     __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6237   %}
6238   ins_pipe( pipe_slow );
6239 %}
6240 
6241 // Load Range
6242 instruct loadRange(rRegI dst, memory mem) %{
6243   match(Set dst (LoadRange mem));
6244 
6245   ins_cost(125);
6246   format %{ "MOV    $dst,$mem" %}
6247   opcode(0x8B);
6248   ins_encode( OpcP, RegMem(dst,mem));
6249   ins_pipe( ialu_reg_mem );
6250 %}
6251 
6252 
6253 // Load Pointer
6254 instruct loadP(eRegP dst, memory mem) %{
6255   match(Set dst (LoadP mem));
6256 
6257   ins_cost(125);
6258   format %{ "MOV    $dst,$mem" %}
6259   opcode(0x8B);
6260   ins_encode( OpcP, RegMem(dst,mem));
6261   ins_pipe( ialu_reg_mem );
6262 %}
6263 
6264 // Load Klass Pointer
6265 instruct loadKlass(eRegP dst, memory mem) %{
6266   match(Set dst (LoadKlass mem));
6267 
6268   ins_cost(125);
6269   format %{ "MOV    $dst,$mem" %}
6270   opcode(0x8B);
6271   ins_encode( OpcP, RegMem(dst,mem));
6272   ins_pipe( ialu_reg_mem );
6273 %}
6274 
6275 // Load Double
6276 instruct loadDPR(regDPR dst, memory mem) %{
6277   predicate(UseSSE<=1);
6278   match(Set dst (LoadD mem));
6279 
6280   ins_cost(150);
6281   format %{ "FLD_D  ST,$mem\n\t"
6282             "FSTP   $dst" %}
6283   opcode(0xDD);               /* DD /0 */
6284   ins_encode( OpcP, RMopc_Mem(0x00,mem),
6285               Pop_Reg_DPR(dst) );
6286   ins_pipe( fpu_reg_mem );
6287 %}
6288 
6289 // Load Double to XMM
6290 instruct loadD(regD dst, memory mem) %{
6291   predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6292   match(Set dst (LoadD mem));
6293   ins_cost(145);
6294   format %{ "MOVSD  $dst,$mem" %}
6295   ins_encode %{
6296     __ movdbl ($dst$$XMMRegister, $mem$$Address);
6297   %}
6298   ins_pipe( pipe_slow );
6299 %}
6300 
6301 instruct loadD_partial(regD dst, memory mem) %{
6302   predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6303   match(Set dst (LoadD mem));
6304   ins_cost(145);
6305   format %{ "MOVLPD $dst,$mem" %}
6306   ins_encode %{
6307     __ movdbl ($dst$$XMMRegister, $mem$$Address);
6308   %}
6309   ins_pipe( pipe_slow );
6310 %}
6311 
6312 // Load to XMM register (single-precision floating point)
6313 // MOVSS instruction
6314 instruct loadF(regF dst, memory mem) %{
6315   predicate(UseSSE>=1);
6316   match(Set dst (LoadF mem));
6317   ins_cost(145);
6318   format %{ "MOVSS  $dst,$mem" %}
6319   ins_encode %{
6320     __ movflt ($dst$$XMMRegister, $mem$$Address);
6321   %}
6322   ins_pipe( pipe_slow );
6323 %}
6324 
6325 // Load Float
6326 instruct loadFPR(regFPR dst, memory mem) %{
6327   predicate(UseSSE==0);
6328   match(Set dst (LoadF mem));
6329 
6330   ins_cost(150);
6331   format %{ "FLD_S  ST,$mem\n\t"
6332             "FSTP   $dst" %}
6333   opcode(0xD9);               /* D9 /0 */
6334   ins_encode( OpcP, RMopc_Mem(0x00,mem),
6335               Pop_Reg_FPR(dst) );
6336   ins_pipe( fpu_reg_mem );
6337 %}
6338 
6339 // Load Effective Address
6340 instruct leaP8(eRegP dst, indOffset8 mem) %{
6341   match(Set dst mem);
6342 
6343   ins_cost(110);
6344   format %{ "LEA    $dst,$mem" %}
6345   opcode(0x8D);
6346   ins_encode( OpcP, RegMem(dst,mem));
6347   ins_pipe( ialu_reg_reg_fat );
6348 %}
6349 
6350 instruct leaP32(eRegP dst, indOffset32 mem) %{
6351   match(Set dst mem);
6352 
6353   ins_cost(110);
6354   format %{ "LEA    $dst,$mem" %}
6355   opcode(0x8D);
6356   ins_encode( OpcP, RegMem(dst,mem));
6357   ins_pipe( ialu_reg_reg_fat );
6358 %}
6359 
6360 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6361   match(Set dst mem);
6362 
6363   ins_cost(110);
6364   format %{ "LEA    $dst,$mem" %}
6365   opcode(0x8D);
6366   ins_encode( OpcP, RegMem(dst,mem));
6367   ins_pipe( ialu_reg_reg_fat );
6368 %}
6369 
6370 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6371   match(Set dst mem);
6372 
6373   ins_cost(110);
6374   format %{ "LEA    $dst,$mem" %}
6375   opcode(0x8D);
6376   ins_encode( OpcP, RegMem(dst,mem));
6377   ins_pipe( ialu_reg_reg_fat );
6378 %}
6379 
6380 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6381   match(Set dst mem);
6382 
6383   ins_cost(110);
6384   format %{ "LEA    $dst,$mem" %}
6385   opcode(0x8D);
6386   ins_encode( OpcP, RegMem(dst,mem));
6387   ins_pipe( ialu_reg_reg_fat );
6388 %}
6389 
6390 // Load Constant
6391 instruct loadConI(rRegI dst, immI src) %{
6392   match(Set dst src);
6393 
6394   format %{ "MOV    $dst,$src" %}
6395   ins_encode( LdImmI(dst, src) );
6396   ins_pipe( ialu_reg_fat );
6397 %}
6398 
6399 // Load Constant zero
6400 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6401   match(Set dst src);
6402   effect(KILL cr);
6403 
6404   ins_cost(50);
6405   format %{ "XOR    $dst,$dst" %}
6406   opcode(0x33);  /* + rd */
6407   ins_encode( OpcP, RegReg( dst, dst ) );
6408   ins_pipe( ialu_reg );
6409 %}
6410 
6411 instruct loadConP(eRegP dst, immP src) %{
6412   match(Set dst src);
6413 
6414   format %{ "MOV    $dst,$src" %}
6415   opcode(0xB8);  /* + rd */
6416   ins_encode( LdImmP(dst, src) );
6417   ins_pipe( ialu_reg_fat );
6418 %}
6419 
6420 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6421   match(Set dst src);
6422   effect(KILL cr);
6423   ins_cost(200);
6424   format %{ "MOV    $dst.lo,$src.lo\n\t"
6425             "MOV    $dst.hi,$src.hi" %}
6426   opcode(0xB8);
6427   ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6428   ins_pipe( ialu_reg_long_fat );
6429 %}
6430 
6431 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6432   match(Set dst src);
6433   effect(KILL cr);
6434   ins_cost(150);
6435   format %{ "XOR    $dst.lo,$dst.lo\n\t"
6436             "XOR    $dst.hi,$dst.hi" %}
6437   opcode(0x33,0x33);
6438   ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6439   ins_pipe( ialu_reg_long );
6440 %}
6441 
6442 // The instruction usage is guarded by predicate in operand immFPR().
6443 instruct loadConFPR(regFPR dst, immFPR con) %{
6444   match(Set dst con);
6445   ins_cost(125);
6446   format %{ "FLD_S  ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6447             "FSTP   $dst" %}
6448   ins_encode %{
6449     __ fld_s($constantaddress($con));
6450     __ fstp_d($dst$$reg);
6451   %}
6452   ins_pipe(fpu_reg_con);
6453 %}
6454 
6455 // The instruction usage is guarded by predicate in operand immFPR0().
6456 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6457   match(Set dst con);
6458   ins_cost(125);
6459   format %{ "FLDZ   ST\n\t"
6460             "FSTP   $dst" %}
6461   ins_encode %{
6462     __ fldz();
6463     __ fstp_d($dst$$reg);
6464   %}
6465   ins_pipe(fpu_reg_con);
6466 %}
6467 
6468 // The instruction usage is guarded by predicate in operand immFPR1().
6469 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6470   match(Set dst con);
6471   ins_cost(125);
6472   format %{ "FLD1   ST\n\t"
6473             "FSTP   $dst" %}
6474   ins_encode %{
6475     __ fld1();
6476     __ fstp_d($dst$$reg);
6477   %}
6478   ins_pipe(fpu_reg_con);
6479 %}
6480 
6481 // The instruction usage is guarded by predicate in operand immF().
6482 instruct loadConF(regF dst, immF con) %{
6483   match(Set dst con);
6484   ins_cost(125);
6485   format %{ "MOVSS  $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6486   ins_encode %{
6487     __ movflt($dst$$XMMRegister, $constantaddress($con));
6488   %}
6489   ins_pipe(pipe_slow);
6490 %}
6491 
6492 // The instruction usage is guarded by predicate in operand immF0().
6493 instruct loadConF0(regF dst, immF0 src) %{
6494   match(Set dst src);
6495   ins_cost(100);
6496   format %{ "XORPS  $dst,$dst\t# float 0.0" %}
6497   ins_encode %{
6498     __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6499   %}
6500   ins_pipe(pipe_slow);
6501 %}
6502 
6503 // The instruction usage is guarded by predicate in operand immDPR().
6504 instruct loadConDPR(regDPR dst, immDPR con) %{
6505   match(Set dst con);
6506   ins_cost(125);
6507 
6508   format %{ "FLD_D  ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6509             "FSTP   $dst" %}
6510   ins_encode %{
6511     __ fld_d($constantaddress($con));
6512     __ fstp_d($dst$$reg);
6513   %}
6514   ins_pipe(fpu_reg_con);
6515 %}
6516 
6517 // The instruction usage is guarded by predicate in operand immDPR0().
6518 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6519   match(Set dst con);
6520   ins_cost(125);
6521 
6522   format %{ "FLDZ   ST\n\t"
6523             "FSTP   $dst" %}
6524   ins_encode %{
6525     __ fldz();
6526     __ fstp_d($dst$$reg);
6527   %}
6528   ins_pipe(fpu_reg_con);
6529 %}
6530 
6531 // The instruction usage is guarded by predicate in operand immDPR1().
6532 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6533   match(Set dst con);
6534   ins_cost(125);
6535 
6536   format %{ "FLD1   ST\n\t"
6537             "FSTP   $dst" %}
6538   ins_encode %{
6539     __ fld1();
6540     __ fstp_d($dst$$reg);
6541   %}
6542   ins_pipe(fpu_reg_con);
6543 %}
6544 
6545 // The instruction usage is guarded by predicate in operand immD().
6546 instruct loadConD(regD dst, immD con) %{
6547   match(Set dst con);
6548   ins_cost(125);
6549   format %{ "MOVSD  $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6550   ins_encode %{
6551     __ movdbl($dst$$XMMRegister, $constantaddress($con));
6552   %}
6553   ins_pipe(pipe_slow);
6554 %}
6555 
6556 // The instruction usage is guarded by predicate in operand immD0().
6557 instruct loadConD0(regD dst, immD0 src) %{
6558   match(Set dst src);
6559   ins_cost(100);
6560   format %{ "XORPD  $dst,$dst\t# double 0.0" %}
6561   ins_encode %{
6562     __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6563   %}
6564   ins_pipe( pipe_slow );
6565 %}
6566 
6567 // Load Stack Slot
6568 instruct loadSSI(rRegI dst, stackSlotI src) %{
6569   match(Set dst src);
6570   ins_cost(125);
6571 
6572   format %{ "MOV    $dst,$src" %}
6573   opcode(0x8B);
6574   ins_encode( OpcP, RegMem(dst,src));
6575   ins_pipe( ialu_reg_mem );
6576 %}
6577 
6578 instruct loadSSL(eRegL dst, stackSlotL src) %{
6579   match(Set dst src);
6580 
6581   ins_cost(200);
6582   format %{ "MOV    $dst,$src.lo\n\t"
6583             "MOV    $dst+4,$src.hi" %}
6584   opcode(0x8B, 0x8B);
6585   ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6586   ins_pipe( ialu_mem_long_reg );
6587 %}
6588 
6589 // Load Stack Slot
6590 instruct loadSSP(eRegP dst, stackSlotP src) %{
6591   match(Set dst src);
6592   ins_cost(125);
6593 
6594   format %{ "MOV    $dst,$src" %}
6595   opcode(0x8B);
6596   ins_encode( OpcP, RegMem(dst,src));
6597   ins_pipe( ialu_reg_mem );
6598 %}
6599 
6600 // Load Stack Slot
6601 instruct loadSSF(regFPR dst, stackSlotF src) %{
6602   match(Set dst src);
6603   ins_cost(125);
6604 
6605   format %{ "FLD_S  $src\n\t"
6606             "FSTP   $dst" %}
6607   opcode(0xD9);               /* D9 /0, FLD m32real */
6608   ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6609               Pop_Reg_FPR(dst) );
6610   ins_pipe( fpu_reg_mem );
6611 %}
6612 
6613 // Load Stack Slot
6614 instruct loadSSD(regDPR dst, stackSlotD src) %{
6615   match(Set dst src);
6616   ins_cost(125);
6617 
6618   format %{ "FLD_D  $src\n\t"
6619             "FSTP   $dst" %}
6620   opcode(0xDD);               /* DD /0, FLD m64real */
6621   ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6622               Pop_Reg_DPR(dst) );
6623   ins_pipe( fpu_reg_mem );
6624 %}
6625 
6626 // Prefetch instructions.
6627 // Must be safe to execute with invalid address (cannot fault).
6628 
6629 instruct prefetchr0( memory mem ) %{
6630   predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6631   match(PrefetchRead mem);
6632   ins_cost(0);
6633   size(0);
6634   format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6635   ins_encode();
6636   ins_pipe(empty);
6637 %}
6638 
6639 instruct prefetchr( memory mem ) %{
6640   predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6641   match(PrefetchRead mem);
6642   ins_cost(100);
6643 
6644   format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6645   ins_encode %{
6646     __ prefetchr($mem$$Address);
6647   %}
6648   ins_pipe(ialu_mem);
6649 %}
6650 
6651 instruct prefetchrNTA( memory mem ) %{
6652   predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6653   match(PrefetchRead mem);
6654   ins_cost(100);
6655 
6656   format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6657   ins_encode %{
6658     __ prefetchnta($mem$$Address);
6659   %}
6660   ins_pipe(ialu_mem);
6661 %}
6662 
6663 instruct prefetchrT0( memory mem ) %{
6664   predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6665   match(PrefetchRead mem);
6666   ins_cost(100);
6667 
6668   format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6669   ins_encode %{
6670     __ prefetcht0($mem$$Address);
6671   %}
6672   ins_pipe(ialu_mem);
6673 %}
6674 
6675 instruct prefetchrT2( memory mem ) %{
6676   predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6677   match(PrefetchRead mem);
6678   ins_cost(100);
6679 
6680   format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6681   ins_encode %{
6682     __ prefetcht2($mem$$Address);
6683   %}
6684   ins_pipe(ialu_mem);
6685 %}
6686 
6687 instruct prefetchw0( memory mem ) %{
6688   predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6689   match(PrefetchWrite mem);
6690   ins_cost(0);
6691   size(0);
6692   format %{ "Prefetch (non-SSE is empty encoding)" %}
6693   ins_encode();
6694   ins_pipe(empty);
6695 %}
6696 
6697 instruct prefetchw( memory mem ) %{
6698   predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6699   match( PrefetchWrite mem );
6700   ins_cost(100);
6701 
6702   format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6703   ins_encode %{
6704     __ prefetchw($mem$$Address);
6705   %}
6706   ins_pipe(ialu_mem);
6707 %}
6708 
6709 instruct prefetchwNTA( memory mem ) %{
6710   predicate(UseSSE>=1);
6711   match(PrefetchWrite mem);
6712   ins_cost(100);
6713 
6714   format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6715   ins_encode %{
6716     __ prefetchnta($mem$$Address);
6717   %}
6718   ins_pipe(ialu_mem);
6719 %}
6720 
6721 // Prefetch instructions for allocation.
6722 
6723 instruct prefetchAlloc0( memory mem ) %{
6724   predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6725   match(PrefetchAllocation mem);
6726   ins_cost(0);
6727   size(0);
6728   format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6729   ins_encode();
6730   ins_pipe(empty);
6731 %}
6732 
6733 instruct prefetchAlloc( memory mem ) %{
6734   predicate(AllocatePrefetchInstr==3);
6735   match( PrefetchAllocation mem );
6736   ins_cost(100);
6737 
6738   format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6739   ins_encode %{
6740     __ prefetchw($mem$$Address);
6741   %}
6742   ins_pipe(ialu_mem);
6743 %}
6744 
6745 instruct prefetchAllocNTA( memory mem ) %{
6746   predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6747   match(PrefetchAllocation mem);
6748   ins_cost(100);
6749 
6750   format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6751   ins_encode %{
6752     __ prefetchnta($mem$$Address);
6753   %}
6754   ins_pipe(ialu_mem);
6755 %}
6756 
6757 instruct prefetchAllocT0( memory mem ) %{
6758   predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6759   match(PrefetchAllocation mem);
6760   ins_cost(100);
6761 
6762   format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6763   ins_encode %{
6764     __ prefetcht0($mem$$Address);
6765   %}
6766   ins_pipe(ialu_mem);
6767 %}
6768 
6769 instruct prefetchAllocT2( memory mem ) %{
6770   predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6771   match(PrefetchAllocation mem);
6772   ins_cost(100);
6773 
6774   format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6775   ins_encode %{
6776     __ prefetcht2($mem$$Address);
6777   %}
6778   ins_pipe(ialu_mem);
6779 %}
6780 
6781 //----------Store Instructions-------------------------------------------------
6782 
6783 // Store Byte
6784 instruct storeB(memory mem, xRegI src) %{
6785   match(Set mem (StoreB mem src));
6786 
6787   ins_cost(125);
6788   format %{ "MOV8   $mem,$src" %}
6789   opcode(0x88);
6790   ins_encode( OpcP, RegMem( src, mem ) );
6791   ins_pipe( ialu_mem_reg );
6792 %}
6793 
6794 // Store Char/Short
6795 instruct storeC(memory mem, rRegI src) %{
6796   match(Set mem (StoreC mem src));
6797 
6798   ins_cost(125);
6799   format %{ "MOV16  $mem,$src" %}
6800   opcode(0x89, 0x66);
6801   ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6802   ins_pipe( ialu_mem_reg );
6803 %}
6804 
6805 // Store Integer
6806 instruct storeI(memory mem, rRegI src) %{
6807   match(Set mem (StoreI mem src));
6808 
6809   ins_cost(125);
6810   format %{ "MOV    $mem,$src" %}
6811   opcode(0x89);
6812   ins_encode( OpcP, RegMem( src, mem ) );
6813   ins_pipe( ialu_mem_reg );
6814 %}
6815 
6816 // Store Long
6817 instruct storeL(long_memory mem, eRegL src) %{
6818   predicate(!((StoreLNode*)n)->require_atomic_access());
6819   match(Set mem (StoreL mem src));
6820 
6821   ins_cost(200);
6822   format %{ "MOV    $mem,$src.lo\n\t"
6823             "MOV    $mem+4,$src.hi" %}
6824   opcode(0x89, 0x89);
6825   ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6826   ins_pipe( ialu_mem_long_reg );
6827 %}
6828 
6829 // Store Long to Integer
6830 instruct storeL2I(memory mem, eRegL src) %{
6831   match(Set mem (StoreI mem (ConvL2I src)));
6832 
6833   format %{ "MOV    $mem,$src.lo\t# long -> int" %}
6834   ins_encode %{
6835     __ movl($mem$$Address, $src$$Register);
6836   %}
6837   ins_pipe(ialu_mem_reg);
6838 %}
6839 
6840 // Volatile Store Long.  Must be atomic, so move it into
6841 // the FP TOS and then do a 64-bit FIST.  Has to probe the
6842 // target address before the store (for null-ptr checks)
6843 // so the memory operand is used twice in the encoding.
6844 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6845   predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6846   match(Set mem (StoreL mem src));
6847   effect( KILL cr );
6848   ins_cost(400);
6849   format %{ "CMP    $mem,EAX\t# Probe address for implicit null check\n\t"
6850             "FILD   $src\n\t"
6851             "FISTp  $mem\t # 64-bit atomic volatile long store" %}
6852   opcode(0x3B);
6853   ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6854   ins_pipe( fpu_reg_mem );
6855 %}
6856 
6857 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6858   predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6859   match(Set mem (StoreL mem src));
6860   effect( TEMP tmp, KILL cr );
6861   ins_cost(380);
6862   format %{ "CMP    $mem,EAX\t# Probe address for implicit null check\n\t"
6863             "MOVSD  $tmp,$src\n\t"
6864             "MOVSD  $mem,$tmp\t # 64-bit atomic volatile long store" %}
6865   ins_encode %{
6866     __ cmpl(rax, $mem$$Address);
6867     __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6868     __ movdbl($mem$$Address, $tmp$$XMMRegister);
6869   %}
6870   ins_pipe( pipe_slow );
6871 %}
6872 
6873 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6874   predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6875   match(Set mem (StoreL mem src));
6876   effect( TEMP tmp2 , TEMP tmp, KILL cr );
6877   ins_cost(360);
6878   format %{ "CMP    $mem,EAX\t# Probe address for implicit null check\n\t"
6879             "MOVD   $tmp,$src.lo\n\t"
6880             "MOVD   $tmp2,$src.hi\n\t"
6881             "PUNPCKLDQ $tmp,$tmp2\n\t"
6882             "MOVSD  $mem,$tmp\t # 64-bit atomic volatile long store" %}
6883   ins_encode %{
6884     __ cmpl(rax, $mem$$Address);
6885     __ movdl($tmp$$XMMRegister, $src$$Register);
6886     __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6887     __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6888     __ movdbl($mem$$Address, $tmp$$XMMRegister);
6889   %}
6890   ins_pipe( pipe_slow );
6891 %}
6892 
6893 // Store Pointer; for storing unknown oops and raw pointers
6894 instruct storeP(memory mem, anyRegP src) %{
6895   match(Set mem (StoreP mem src));
6896 
6897   ins_cost(125);
6898   format %{ "MOV    $mem,$src" %}
6899   opcode(0x89);
6900   ins_encode( OpcP, RegMem( src, mem ) );
6901   ins_pipe( ialu_mem_reg );
6902 %}
6903 
6904 // Store Integer Immediate
6905 instruct storeImmI(memory mem, immI src) %{
6906   match(Set mem (StoreI mem src));
6907 
6908   ins_cost(150);
6909   format %{ "MOV    $mem,$src" %}
6910   opcode(0xC7);               /* C7 /0 */
6911   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con32( src ));
6912   ins_pipe( ialu_mem_imm );
6913 %}
6914 
6915 // Store Short/Char Immediate
6916 instruct storeImmI16(memory mem, immI16 src) %{
6917   predicate(UseStoreImmI16);
6918   match(Set mem (StoreC mem src));
6919 
6920   ins_cost(150);
6921   format %{ "MOV16  $mem,$src" %}
6922   opcode(0xC7);     /* C7 /0 Same as 32 store immediate with prefix */
6923   ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem),  Con16( src ));
6924   ins_pipe( ialu_mem_imm );
6925 %}
6926 
6927 // Store Pointer Immediate; null pointers or constant oops that do not
6928 // need card-mark barriers.
6929 instruct storeImmP(memory mem, immP src) %{
6930   match(Set mem (StoreP mem src));
6931 
6932   ins_cost(150);
6933   format %{ "MOV    $mem,$src" %}
6934   opcode(0xC7);               /* C7 /0 */
6935   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con32( src ));
6936   ins_pipe( ialu_mem_imm );
6937 %}
6938 
6939 // Store Byte Immediate
6940 instruct storeImmB(memory mem, immI8 src) %{
6941   match(Set mem (StoreB mem src));
6942 
6943   ins_cost(150);
6944   format %{ "MOV8   $mem,$src" %}
6945   opcode(0xC6);               /* C6 /0 */
6946   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con8or32( src ));
6947   ins_pipe( ialu_mem_imm );
6948 %}
6949 
6950 // Store CMS card-mark Immediate
6951 instruct storeImmCM(memory mem, immI8 src) %{
6952   match(Set mem (StoreCM mem src));
6953 
6954   ins_cost(150);
6955   format %{ "MOV8   $mem,$src\t! CMS card-mark imm0" %}
6956   opcode(0xC6);               /* C6 /0 */
6957   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con8or32( src ));
6958   ins_pipe( ialu_mem_imm );
6959 %}
6960 
6961 // Store Double
6962 instruct storeDPR( memory mem, regDPR1 src) %{
6963   predicate(UseSSE<=1);
6964   match(Set mem (StoreD mem src));
6965 
6966   ins_cost(100);
6967   format %{ "FST_D  $mem,$src" %}
6968   opcode(0xDD);       /* DD /2 */
6969   ins_encode( enc_FPR_store(mem,src) );
6970   ins_pipe( fpu_mem_reg );
6971 %}
6972 
6973 // Store double does rounding on x86
6974 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6975   predicate(UseSSE<=1);
6976   match(Set mem (StoreD mem (RoundDouble src)));
6977 
6978   ins_cost(100);
6979   format %{ "FST_D  $mem,$src\t# round" %}
6980   opcode(0xDD);       /* DD /2 */
6981   ins_encode( enc_FPR_store(mem,src) );
6982   ins_pipe( fpu_mem_reg );
6983 %}
6984 
6985 // Store XMM register to memory (double-precision floating points)
6986 // MOVSD instruction
6987 instruct storeD(memory mem, regD src) %{
6988   predicate(UseSSE>=2);
6989   match(Set mem (StoreD mem src));
6990   ins_cost(95);
6991   format %{ "MOVSD  $mem,$src" %}
6992   ins_encode %{
6993     __ movdbl($mem$$Address, $src$$XMMRegister);
6994   %}
6995   ins_pipe( pipe_slow );
6996 %}
6997 
6998 // Store XMM register to memory (single-precision floating point)
6999 // MOVSS instruction
7000 instruct storeF(memory mem, regF src) %{
7001   predicate(UseSSE>=1);
7002   match(Set mem (StoreF mem src));
7003   ins_cost(95);
7004   format %{ "MOVSS  $mem,$src" %}
7005   ins_encode %{
7006     __ movflt($mem$$Address, $src$$XMMRegister);
7007   %}
7008   ins_pipe( pipe_slow );
7009 %}
7010 
7011 // Store Float
7012 instruct storeFPR( memory mem, regFPR1 src) %{
7013   predicate(UseSSE==0);
7014   match(Set mem (StoreF mem src));
7015 
7016   ins_cost(100);
7017   format %{ "FST_S  $mem,$src" %}
7018   opcode(0xD9);       /* D9 /2 */
7019   ins_encode( enc_FPR_store(mem,src) );
7020   ins_pipe( fpu_mem_reg );
7021 %}
7022 
7023 // Store Float does rounding on x86
7024 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7025   predicate(UseSSE==0);
7026   match(Set mem (StoreF mem (RoundFloat src)));
7027 
7028   ins_cost(100);
7029   format %{ "FST_S  $mem,$src\t# round" %}
7030   opcode(0xD9);       /* D9 /2 */
7031   ins_encode( enc_FPR_store(mem,src) );
7032   ins_pipe( fpu_mem_reg );
7033 %}
7034 
7035 // Store Float does rounding on x86
7036 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7037   predicate(UseSSE<=1);
7038   match(Set mem (StoreF mem (ConvD2F src)));
7039 
7040   ins_cost(100);
7041   format %{ "FST_S  $mem,$src\t# D-round" %}
7042   opcode(0xD9);       /* D9 /2 */
7043   ins_encode( enc_FPR_store(mem,src) );
7044   ins_pipe( fpu_mem_reg );
7045 %}
7046 
7047 // Store immediate Float value (it is faster than store from FPU register)
7048 // The instruction usage is guarded by predicate in operand immFPR().
7049 instruct storeFPR_imm( memory mem, immFPR src) %{
7050   match(Set mem (StoreF mem src));
7051 
7052   ins_cost(50);
7053   format %{ "MOV    $mem,$src\t# store float" %}
7054   opcode(0xC7);               /* C7 /0 */
7055   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con32FPR_as_bits( src ));
7056   ins_pipe( ialu_mem_imm );
7057 %}
7058 
7059 // Store immediate Float value (it is faster than store from XMM register)
7060 // The instruction usage is guarded by predicate in operand immF().
7061 instruct storeF_imm( memory mem, immF src) %{
7062   match(Set mem (StoreF mem src));
7063 
7064   ins_cost(50);
7065   format %{ "MOV    $mem,$src\t# store float" %}
7066   opcode(0xC7);               /* C7 /0 */
7067   ins_encode( OpcP, RMopc_Mem(0x00,mem),  Con32F_as_bits( src ));
7068   ins_pipe( ialu_mem_imm );
7069 %}
7070 
7071 // Store Integer to stack slot
7072 instruct storeSSI(stackSlotI dst, rRegI src) %{
7073   match(Set dst src);
7074 
7075   ins_cost(100);
7076   format %{ "MOV    $dst,$src" %}
7077   opcode(0x89);
7078   ins_encode( OpcPRegSS( dst, src ) );
7079   ins_pipe( ialu_mem_reg );
7080 %}
7081 
7082 // Store Integer to stack slot
7083 instruct storeSSP(stackSlotP dst, eRegP src) %{
7084   match(Set dst src);
7085 
7086   ins_cost(100);
7087   format %{ "MOV    $dst,$src" %}
7088   opcode(0x89);
7089   ins_encode( OpcPRegSS( dst, src ) );
7090   ins_pipe( ialu_mem_reg );
7091 %}
7092 
7093 // Store Long to stack slot
7094 instruct storeSSL(stackSlotL dst, eRegL src) %{
7095   match(Set dst src);
7096 
7097   ins_cost(200);
7098   format %{ "MOV    $dst,$src.lo\n\t"
7099             "MOV    $dst+4,$src.hi" %}
7100   opcode(0x89, 0x89);
7101   ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7102   ins_pipe( ialu_mem_long_reg );
7103 %}
7104 
7105 //----------MemBar Instructions-----------------------------------------------
7106 // Memory barrier flavors
7107 
7108 instruct membar_acquire() %{
7109   match(MemBarAcquire);
7110   match(LoadFence);
7111   ins_cost(400);
7112 
7113   size(0);
7114   format %{ "MEMBAR-acquire ! (empty encoding)" %}
7115   ins_encode();
7116   ins_pipe(empty);
7117 %}
7118 
7119 instruct membar_acquire_lock() %{
7120   match(MemBarAcquireLock);
7121   ins_cost(0);
7122 
7123   size(0);
7124   format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7125   ins_encode( );
7126   ins_pipe(empty);
7127 %}
7128 
7129 instruct membar_release() %{
7130   match(MemBarRelease);
7131   match(StoreFence);
7132   ins_cost(400);
7133 
7134   size(0);
7135   format %{ "MEMBAR-release ! (empty encoding)" %}
7136   ins_encode( );
7137   ins_pipe(empty);
7138 %}
7139 
7140 instruct membar_release_lock() %{
7141   match(MemBarReleaseLock);
7142   ins_cost(0);
7143 
7144   size(0);
7145   format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7146   ins_encode( );
7147   ins_pipe(empty);
7148 %}
7149 
7150 instruct membar_volatile(eFlagsReg cr) %{
7151   match(MemBarVolatile);
7152   effect(KILL cr);
7153   ins_cost(400);
7154 
7155   format %{ 
7156     $$template
7157     if (os::is_MP()) {
7158       $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7159     } else {
7160       $$emit$$"MEMBAR-volatile ! (empty encoding)"
7161     }
7162   %}
7163   ins_encode %{
7164     __ membar(Assembler::StoreLoad);
7165   %}
7166   ins_pipe(pipe_slow);
7167 %}
7168 
7169 instruct unnecessary_membar_volatile() %{
7170   match(MemBarVolatile);
7171   predicate(Matcher::post_store_load_barrier(n));
7172   ins_cost(0);
7173 
7174   size(0);
7175   format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7176   ins_encode( );
7177   ins_pipe(empty);
7178 %}
7179 
7180 instruct membar_storestore() %{
7181   match(MemBarStoreStore);
7182   ins_cost(0);
7183 
7184   size(0);
7185   format %{ "MEMBAR-storestore (empty encoding)" %}
7186   ins_encode( );
7187   ins_pipe(empty);
7188 %}
7189 
7190 //----------Move Instructions--------------------------------------------------
7191 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7192   match(Set dst (CastX2P src));
7193   format %{ "# X2P  $dst, $src" %}
7194   ins_encode( /*empty encoding*/ );
7195   ins_cost(0);
7196   ins_pipe(empty);
7197 %}
7198 
7199 instruct castP2X(rRegI dst, eRegP src ) %{
7200   match(Set dst (CastP2X src));
7201   ins_cost(50);
7202   format %{ "MOV    $dst, $src\t# CastP2X" %}
7203   ins_encode( enc_Copy( dst, src) );
7204   ins_pipe( ialu_reg_reg );
7205 %}
7206 
7207 //----------Conditional Move---------------------------------------------------
7208 // Conditional move
7209 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7210   predicate(!VM_Version::supports_cmov() );
7211   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7212   ins_cost(200);
7213   format %{ "J$cop,us skip\t# signed cmove\n\t"
7214             "MOV    $dst,$src\n"
7215       "skip:" %}
7216   ins_encode %{
7217     Label Lskip;
7218     // Invert sense of branch from sense of CMOV
7219     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7220     __ movl($dst$$Register, $src$$Register);
7221     __ bind(Lskip);
7222   %}
7223   ins_pipe( pipe_cmov_reg );
7224 %}
7225 
7226 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7227   predicate(!VM_Version::supports_cmov() );
7228   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7229   ins_cost(200);
7230   format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7231             "MOV    $dst,$src\n"
7232       "skip:" %}
7233   ins_encode %{
7234     Label Lskip;
7235     // Invert sense of branch from sense of CMOV
7236     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7237     __ movl($dst$$Register, $src$$Register);
7238     __ bind(Lskip);
7239   %}
7240   ins_pipe( pipe_cmov_reg );
7241 %}
7242 
7243 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7244   predicate(VM_Version::supports_cmov() );
7245   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7246   ins_cost(200);
7247   format %{ "CMOV$cop $dst,$src" %}
7248   opcode(0x0F,0x40);
7249   ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7250   ins_pipe( pipe_cmov_reg );
7251 %}
7252 
7253 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7254   predicate(VM_Version::supports_cmov() );
7255   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7256   ins_cost(200);
7257   format %{ "CMOV$cop $dst,$src" %}
7258   opcode(0x0F,0x40);
7259   ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7260   ins_pipe( pipe_cmov_reg );
7261 %}
7262 
7263 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7264   predicate(VM_Version::supports_cmov() );
7265   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7266   ins_cost(200);
7267   expand %{
7268     cmovI_regU(cop, cr, dst, src);
7269   %}
7270 %}
7271 
7272 // Conditional move
7273 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7274   predicate(VM_Version::supports_cmov() );
7275   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7276   ins_cost(250);
7277   format %{ "CMOV$cop $dst,$src" %}
7278   opcode(0x0F,0x40);
7279   ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7280   ins_pipe( pipe_cmov_mem );
7281 %}
7282 
7283 // Conditional move
7284 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7285   predicate(VM_Version::supports_cmov() );
7286   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7287   ins_cost(250);
7288   format %{ "CMOV$cop $dst,$src" %}
7289   opcode(0x0F,0x40);
7290   ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7291   ins_pipe( pipe_cmov_mem );
7292 %}
7293 
7294 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7295   predicate(VM_Version::supports_cmov() );
7296   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7297   ins_cost(250);
7298   expand %{
7299     cmovI_memU(cop, cr, dst, src);
7300   %}
7301 %}
7302 
7303 // Conditional move
7304 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7305   predicate(VM_Version::supports_cmov() );
7306   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7307   ins_cost(200);
7308   format %{ "CMOV$cop $dst,$src\t# ptr" %}
7309   opcode(0x0F,0x40);
7310   ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7311   ins_pipe( pipe_cmov_reg );
7312 %}
7313 
7314 // Conditional move (non-P6 version)
7315 // Note:  a CMoveP is generated for  stubs and native wrappers
7316 //        regardless of whether we are on a P6, so we
7317 //        emulate a cmov here
7318 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7319   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7320   ins_cost(300);
7321   format %{ "Jn$cop   skip\n\t"
7322           "MOV    $dst,$src\t# pointer\n"
7323       "skip:" %}
7324   opcode(0x8b);
7325   ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7326   ins_pipe( pipe_cmov_reg );
7327 %}
7328 
7329 // Conditional move
7330 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7331   predicate(VM_Version::supports_cmov() );
7332   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7333   ins_cost(200);
7334   format %{ "CMOV$cop $dst,$src\t# ptr" %}
7335   opcode(0x0F,0x40);
7336   ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7337   ins_pipe( pipe_cmov_reg );
7338 %}
7339 
7340 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7341   predicate(VM_Version::supports_cmov() );
7342   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7343   ins_cost(200);
7344   expand %{
7345     cmovP_regU(cop, cr, dst, src);
7346   %}
7347 %}
7348 
7349 // DISABLED: Requires the ADLC to emit a bottom_type call that
7350 // correctly meets the two pointer arguments; one is an incoming
7351 // register but the other is a memory operand.  ALSO appears to
7352 // be buggy with implicit null checks.
7353 //
7354 //// Conditional move
7355 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7356 //  predicate(VM_Version::supports_cmov() );
7357 //  match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7358 //  ins_cost(250);
7359 //  format %{ "CMOV$cop $dst,$src\t# ptr" %}
7360 //  opcode(0x0F,0x40);
7361 //  ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7362 //  ins_pipe( pipe_cmov_mem );
7363 //%}
7364 //
7365 //// Conditional move
7366 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7367 //  predicate(VM_Version::supports_cmov() );
7368 //  match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7369 //  ins_cost(250);
7370 //  format %{ "CMOV$cop $dst,$src\t# ptr" %}
7371 //  opcode(0x0F,0x40);
7372 //  ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7373 //  ins_pipe( pipe_cmov_mem );
7374 //%}
7375 
7376 // Conditional move
7377 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7378   predicate(UseSSE<=1);
7379   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7380   ins_cost(200);
7381   format %{ "FCMOV$cop $dst,$src\t# double" %}
7382   opcode(0xDA);
7383   ins_encode( enc_cmov_dpr(cop,src) );
7384   ins_pipe( pipe_cmovDPR_reg );
7385 %}
7386 
7387 // Conditional move
7388 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7389   predicate(UseSSE==0);
7390   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7391   ins_cost(200);
7392   format %{ "FCMOV$cop $dst,$src\t# float" %}
7393   opcode(0xDA);
7394   ins_encode( enc_cmov_dpr(cop,src) );
7395   ins_pipe( pipe_cmovDPR_reg );
7396 %}
7397 
7398 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7399 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7400   predicate(UseSSE<=1);
7401   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7402   ins_cost(200);
7403   format %{ "Jn$cop   skip\n\t"
7404             "MOV    $dst,$src\t# double\n"
7405       "skip:" %}
7406   opcode (0xdd, 0x3);     /* DD D8+i or DD /3 */
7407   ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7408   ins_pipe( pipe_cmovDPR_reg );
7409 %}
7410 
7411 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7412 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7413   predicate(UseSSE==0);
7414   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7415   ins_cost(200);
7416   format %{ "Jn$cop    skip\n\t"
7417             "MOV    $dst,$src\t# float\n"
7418       "skip:" %}
7419   opcode (0xdd, 0x3);     /* DD D8+i or DD /3 */
7420   ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7421   ins_pipe( pipe_cmovDPR_reg );
7422 %}
7423 
7424 // No CMOVE with SSE/SSE2
7425 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7426   predicate (UseSSE>=1);
7427   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7428   ins_cost(200);
7429   format %{ "Jn$cop   skip\n\t"
7430             "MOVSS  $dst,$src\t# float\n"
7431       "skip:" %}
7432   ins_encode %{
7433     Label skip;
7434     // Invert sense of branch from sense of CMOV
7435     __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7436     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7437     __ bind(skip);
7438   %}
7439   ins_pipe( pipe_slow );
7440 %}
7441 
7442 // No CMOVE with SSE/SSE2
7443 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7444   predicate (UseSSE>=2);
7445   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7446   ins_cost(200);
7447   format %{ "Jn$cop   skip\n\t"
7448             "MOVSD  $dst,$src\t# float\n"
7449       "skip:" %}
7450   ins_encode %{
7451     Label skip;
7452     // Invert sense of branch from sense of CMOV
7453     __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7454     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7455     __ bind(skip);
7456   %}
7457   ins_pipe( pipe_slow );
7458 %}
7459 
7460 // unsigned version
7461 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7462   predicate (UseSSE>=1);
7463   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7464   ins_cost(200);
7465   format %{ "Jn$cop   skip\n\t"
7466             "MOVSS  $dst,$src\t# float\n"
7467       "skip:" %}
7468   ins_encode %{
7469     Label skip;
7470     // Invert sense of branch from sense of CMOV
7471     __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7472     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7473     __ bind(skip);
7474   %}
7475   ins_pipe( pipe_slow );
7476 %}
7477 
7478 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7479   predicate (UseSSE>=1);
7480   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7481   ins_cost(200);
7482   expand %{
7483     fcmovF_regU(cop, cr, dst, src);
7484   %}
7485 %}
7486 
7487 // unsigned version
7488 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7489   predicate (UseSSE>=2);
7490   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7491   ins_cost(200);
7492   format %{ "Jn$cop   skip\n\t"
7493             "MOVSD  $dst,$src\t# float\n"
7494       "skip:" %}
7495   ins_encode %{
7496     Label skip;
7497     // Invert sense of branch from sense of CMOV
7498     __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7499     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7500     __ bind(skip);
7501   %}
7502   ins_pipe( pipe_slow );
7503 %}
7504 
7505 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7506   predicate (UseSSE>=2);
7507   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7508   ins_cost(200);
7509   expand %{
7510     fcmovD_regU(cop, cr, dst, src);
7511   %}
7512 %}
7513 
7514 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7515   predicate(VM_Version::supports_cmov() );
7516   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7517   ins_cost(200);
7518   format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7519             "CMOV$cop $dst.hi,$src.hi" %}
7520   opcode(0x0F,0x40);
7521   ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7522   ins_pipe( pipe_cmov_reg_long );
7523 %}
7524 
7525 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7526   predicate(VM_Version::supports_cmov() );
7527   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7528   ins_cost(200);
7529   format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7530             "CMOV$cop $dst.hi,$src.hi" %}
7531   opcode(0x0F,0x40);
7532   ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7533   ins_pipe( pipe_cmov_reg_long );
7534 %}
7535 
7536 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7537   predicate(VM_Version::supports_cmov() );
7538   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7539   ins_cost(200);
7540   expand %{
7541     cmovL_regU(cop, cr, dst, src);
7542   %}
7543 %}
7544 
7545 //----------Arithmetic Instructions--------------------------------------------
7546 //----------Addition Instructions----------------------------------------------
7547 
7548 instruct addExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7549 %{
7550   match(AddExactI dst src);
7551   effect(DEF cr);
7552 
7553   format %{ "ADD    $dst, $src\t# addExact int" %}
7554   ins_encode %{
7555     __ addl($dst$$Register, $src$$Register);
7556   %}
7557   ins_pipe(ialu_reg_reg);
7558 %}
7559 
7560 instruct addExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7561 %{
7562   match(AddExactI dst src);
7563   effect(DEF cr);
7564 
7565   format %{ "ADD    $dst, $src\t# addExact int" %}
7566   ins_encode %{
7567     __ addl($dst$$Register, $src$$constant);
7568   %}
7569   ins_pipe(ialu_reg_reg);
7570 %}
7571 
7572 instruct addExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7573 %{
7574   match(AddExactI dst (LoadI src));
7575   effect(DEF cr);
7576 
7577   ins_cost(125);
7578   format %{ "ADD    $dst,$src\t# addExact int" %}
7579   ins_encode %{
7580     __ addl($dst$$Register, $src$$Address);
7581   %}
7582   ins_pipe( ialu_reg_mem );
7583 %}
7584 
7585 
7586 // Integer Addition Instructions
7587 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7588   match(Set dst (AddI dst src));
7589   effect(KILL cr);
7590 
7591   size(2);
7592   format %{ "ADD    $dst,$src" %}
7593   opcode(0x03);
7594   ins_encode( OpcP, RegReg( dst, src) );
7595   ins_pipe( ialu_reg_reg );
7596 %}
7597 
7598 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7599   match(Set dst (AddI dst src));
7600   effect(KILL cr);
7601 
7602   format %{ "ADD    $dst,$src" %}
7603   opcode(0x81, 0x00); /* /0 id */
7604   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7605   ins_pipe( ialu_reg );
7606 %}
7607 
7608 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7609   predicate(UseIncDec);
7610   match(Set dst (AddI dst src));
7611   effect(KILL cr);
7612 
7613   size(1);
7614   format %{ "INC    $dst" %}
7615   opcode(0x40); /*  */
7616   ins_encode( Opc_plus( primary, dst ) );
7617   ins_pipe( ialu_reg );
7618 %}
7619 
7620 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7621   match(Set dst (AddI src0 src1));
7622   ins_cost(110);
7623 
7624   format %{ "LEA    $dst,[$src0 + $src1]" %}
7625   opcode(0x8D); /* 0x8D /r */
7626   ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7627   ins_pipe( ialu_reg_reg );
7628 %}
7629 
7630 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7631   match(Set dst (AddP src0 src1));
7632   ins_cost(110);
7633 
7634   format %{ "LEA    $dst,[$src0 + $src1]\t# ptr" %}
7635   opcode(0x8D); /* 0x8D /r */
7636   ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7637   ins_pipe( ialu_reg_reg );
7638 %}
7639 
7640 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7641   predicate(UseIncDec);
7642   match(Set dst (AddI dst src));
7643   effect(KILL cr);
7644 
7645   size(1);
7646   format %{ "DEC    $dst" %}
7647   opcode(0x48); /*  */
7648   ins_encode( Opc_plus( primary, dst ) );
7649   ins_pipe( ialu_reg );
7650 %}
7651 
7652 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7653   match(Set dst (AddP dst src));
7654   effect(KILL cr);
7655 
7656   size(2);
7657   format %{ "ADD    $dst,$src" %}
7658   opcode(0x03);
7659   ins_encode( OpcP, RegReg( dst, src) );
7660   ins_pipe( ialu_reg_reg );
7661 %}
7662 
7663 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7664   match(Set dst (AddP dst src));
7665   effect(KILL cr);
7666 
7667   format %{ "ADD    $dst,$src" %}
7668   opcode(0x81,0x00); /* Opcode 81 /0 id */
7669   // ins_encode( RegImm( dst, src) );
7670   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7671   ins_pipe( ialu_reg );
7672 %}
7673 
7674 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7675   match(Set dst (AddI dst (LoadI src)));
7676   effect(KILL cr);
7677 
7678   ins_cost(125);
7679   format %{ "ADD    $dst,$src" %}
7680   opcode(0x03);
7681   ins_encode( OpcP, RegMem( dst, src) );
7682   ins_pipe( ialu_reg_mem );
7683 %}
7684 
7685 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7686   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7687   effect(KILL cr);
7688 
7689   ins_cost(150);
7690   format %{ "ADD    $dst,$src" %}
7691   opcode(0x01);  /* Opcode 01 /r */
7692   ins_encode( OpcP, RegMem( src, dst ) );
7693   ins_pipe( ialu_mem_reg );
7694 %}
7695 
7696 // Add Memory with Immediate
7697 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7698   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7699   effect(KILL cr);
7700 
7701   ins_cost(125);
7702   format %{ "ADD    $dst,$src" %}
7703   opcode(0x81);               /* Opcode 81 /0 id */
7704   ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7705   ins_pipe( ialu_mem_imm );
7706 %}
7707 
7708 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7709   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7710   effect(KILL cr);
7711 
7712   ins_cost(125);
7713   format %{ "INC    $dst" %}
7714   opcode(0xFF);               /* Opcode FF /0 */
7715   ins_encode( OpcP, RMopc_Mem(0x00,dst));
7716   ins_pipe( ialu_mem_imm );
7717 %}
7718 
7719 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7720   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7721   effect(KILL cr);
7722 
7723   ins_cost(125);
7724   format %{ "DEC    $dst" %}
7725   opcode(0xFF);               /* Opcode FF /1 */
7726   ins_encode( OpcP, RMopc_Mem(0x01,dst));
7727   ins_pipe( ialu_mem_imm );
7728 %}
7729 
7730 
7731 instruct checkCastPP( eRegP dst ) %{
7732   match(Set dst (CheckCastPP dst));
7733 
7734   size(0);
7735   format %{ "#checkcastPP of $dst" %}
7736   ins_encode( /*empty encoding*/ );
7737   ins_pipe( empty );
7738 %}
7739 
7740 instruct castPP( eRegP dst ) %{
7741   match(Set dst (CastPP dst));
7742   format %{ "#castPP of $dst" %}
7743   ins_encode( /*empty encoding*/ );
7744   ins_pipe( empty );
7745 %}
7746 
7747 instruct castII( rRegI dst ) %{
7748   match(Set dst (CastII dst));
7749   format %{ "#castII of $dst" %}
7750   ins_encode( /*empty encoding*/ );
7751   ins_cost(0);
7752   ins_pipe( empty );
7753 %}
7754 
7755 
7756 // Load-locked - same as a regular pointer load when used with compare-swap
7757 instruct loadPLocked(eRegP dst, memory mem) %{
7758   match(Set dst (LoadPLocked mem));
7759 
7760   ins_cost(125);
7761   format %{ "MOV    $dst,$mem\t# Load ptr. locked" %}
7762   opcode(0x8B);
7763   ins_encode( OpcP, RegMem(dst,mem));
7764   ins_pipe( ialu_reg_mem );
7765 %}
7766 
7767 // Conditional-store of the updated heap-top.
7768 // Used during allocation of the shared heap.
7769 // Sets flags (EQ) on success.  Implemented with a CMPXCHG on Intel.
7770 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7771   match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7772   // EAX is killed if there is contention, but then it's also unused.
7773   // In the common case of no contention, EAX holds the new oop address.
7774   format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7775   ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7776   ins_pipe( pipe_cmpxchg );
7777 %}
7778 
7779 // Conditional-store of an int value.
7780 // ZF flag is set on success, reset otherwise.  Implemented with a CMPXCHG on Intel.
7781 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7782   match(Set cr (StoreIConditional mem (Binary oldval newval)));
7783   effect(KILL oldval);
7784   format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7785   ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7786   ins_pipe( pipe_cmpxchg );
7787 %}
7788 
7789 // Conditional-store of a long value.
7790 // ZF flag is set on success, reset otherwise.  Implemented with a CMPXCHG8 on Intel.
7791 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7792   match(Set cr (StoreLConditional mem (Binary oldval newval)));
7793   effect(KILL oldval);
7794   format %{ "XCHG   EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7795             "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7796             "XCHG   EBX,ECX"
7797   %}
7798   ins_encode %{
7799     // Note: we need to swap rbx, and rcx before and after the
7800     //       cmpxchg8 instruction because the instruction uses
7801     //       rcx as the high order word of the new value to store but
7802     //       our register encoding uses rbx.
7803     __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7804     if( os::is_MP() )
7805       __ lock();
7806     __ cmpxchg8($mem$$Address);
7807     __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7808   %}
7809   ins_pipe( pipe_cmpxchg );
7810 %}
7811 
7812 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7813 
7814 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7815   predicate(VM_Version::supports_cx8());
7816   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7817   effect(KILL cr, KILL oldval);
7818   format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7819             "MOV    $res,0\n\t"
7820             "JNE,s  fail\n\t"
7821             "MOV    $res,1\n"
7822           "fail:" %}
7823   ins_encode( enc_cmpxchg8(mem_ptr),
7824               enc_flags_ne_to_boolean(res) );
7825   ins_pipe( pipe_cmpxchg );
7826 %}
7827 
7828 instruct compareAndSwapP( rRegI res,  pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7829   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7830   effect(KILL cr, KILL oldval);
7831   format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7832             "MOV    $res,0\n\t"
7833             "JNE,s  fail\n\t"
7834             "MOV    $res,1\n"
7835           "fail:" %}
7836   ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7837   ins_pipe( pipe_cmpxchg );
7838 %}
7839 
7840 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7841   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7842   effect(KILL cr, KILL oldval);
7843   format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7844             "MOV    $res,0\n\t"
7845             "JNE,s  fail\n\t"
7846             "MOV    $res,1\n"
7847           "fail:" %}
7848   ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7849   ins_pipe( pipe_cmpxchg );
7850 %}
7851 
7852 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7853   predicate(n->as_LoadStore()->result_not_used());
7854   match(Set dummy (GetAndAddI mem add));
7855   effect(KILL cr);
7856   format %{ "ADDL  [$mem],$add" %}
7857   ins_encode %{
7858     if (os::is_MP()) { __ lock(); }
7859     __ addl($mem$$Address, $add$$constant);
7860   %}
7861   ins_pipe( pipe_cmpxchg );
7862 %}
7863 
7864 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7865   match(Set newval (GetAndAddI mem newval));
7866   effect(KILL cr);
7867   format %{ "XADDL  [$mem],$newval" %}
7868   ins_encode %{
7869     if (os::is_MP()) { __ lock(); }
7870     __ xaddl($mem$$Address, $newval$$Register);
7871   %}
7872   ins_pipe( pipe_cmpxchg );
7873 %}
7874 
7875 instruct xchgI( memory mem, rRegI newval) %{
7876   match(Set newval (GetAndSetI mem newval));
7877   format %{ "XCHGL  $newval,[$mem]" %}
7878   ins_encode %{
7879     __ xchgl($newval$$Register, $mem$$Address);
7880   %}
7881   ins_pipe( pipe_cmpxchg );
7882 %}
7883 
7884 instruct xchgP( memory mem, pRegP newval) %{
7885   match(Set newval (GetAndSetP mem newval));
7886   format %{ "XCHGL  $newval,[$mem]" %}
7887   ins_encode %{
7888     __ xchgl($newval$$Register, $mem$$Address);
7889   %}
7890   ins_pipe( pipe_cmpxchg );
7891 %}
7892 
7893 //----------Subtraction Instructions-------------------------------------------
7894 
7895 instruct subExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
7896 %{
7897   match(SubExactI dst src);
7898   effect(DEF cr);
7899 
7900   format %{ "SUB    $dst, $src\t# subExact int" %}
7901   ins_encode %{
7902     __ subl($dst$$Register, $src$$Register);
7903   %}
7904   ins_pipe(ialu_reg_reg);
7905 %}
7906 
7907 instruct subExactI_eReg_imm(eAXRegI dst, immI src, eFlagsReg cr)
7908 %{
7909   match(SubExactI dst src);
7910   effect(DEF cr);
7911 
7912   format %{ "SUB    $dst, $src\t# subExact int" %}
7913   ins_encode %{
7914     __ subl($dst$$Register, $src$$constant);
7915   %}
7916   ins_pipe(ialu_reg_reg);
7917 %}
7918 
7919 instruct subExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
7920 %{
7921   match(SubExactI dst (LoadI src));
7922   effect(DEF cr);
7923 
7924   ins_cost(125);
7925   format %{ "SUB    $dst,$src\t# subExact int" %}
7926   ins_encode %{
7927     __ subl($dst$$Register, $src$$Address);
7928   %}
7929   ins_pipe( ialu_reg_mem );
7930 %}
7931 
7932 // Integer Subtraction Instructions
7933 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7934   match(Set dst (SubI dst src));
7935   effect(KILL cr);
7936 
7937   size(2);
7938   format %{ "SUB    $dst,$src" %}
7939   opcode(0x2B);
7940   ins_encode( OpcP, RegReg( dst, src) );
7941   ins_pipe( ialu_reg_reg );
7942 %}
7943 
7944 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7945   match(Set dst (SubI dst src));
7946   effect(KILL cr);
7947 
7948   format %{ "SUB    $dst,$src" %}
7949   opcode(0x81,0x05);  /* Opcode 81 /5 */
7950   // ins_encode( RegImm( dst, src) );
7951   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7952   ins_pipe( ialu_reg );
7953 %}
7954 
7955 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7956   match(Set dst (SubI dst (LoadI src)));
7957   effect(KILL cr);
7958 
7959   ins_cost(125);
7960   format %{ "SUB    $dst,$src" %}
7961   opcode(0x2B);
7962   ins_encode( OpcP, RegMem( dst, src) );
7963   ins_pipe( ialu_reg_mem );
7964 %}
7965 
7966 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7967   match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7968   effect(KILL cr);
7969 
7970   ins_cost(150);
7971   format %{ "SUB    $dst,$src" %}
7972   opcode(0x29);  /* Opcode 29 /r */
7973   ins_encode( OpcP, RegMem( src, dst ) );
7974   ins_pipe( ialu_mem_reg );
7975 %}
7976 
7977 // Subtract from a pointer
7978 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7979   match(Set dst (AddP dst (SubI zero src)));
7980   effect(KILL cr);
7981 
7982   size(2);
7983   format %{ "SUB    $dst,$src" %}
7984   opcode(0x2B);
7985   ins_encode( OpcP, RegReg( dst, src) );
7986   ins_pipe( ialu_reg_reg );
7987 %}
7988 
7989 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7990   match(Set dst (SubI zero dst));
7991   effect(KILL cr);
7992 
7993   size(2);
7994   format %{ "NEG    $dst" %}
7995   opcode(0xF7,0x03);  // Opcode F7 /3
7996   ins_encode( OpcP, RegOpc( dst ) );
7997   ins_pipe( ialu_reg );
7998 %}
7999 
8000 instruct negExactI_eReg(eAXRegI dst, eFlagsReg cr) %{
8001   match(NegExactI dst);
8002   effect(DEF cr);
8003 
8004   format %{ "NEG    $dst\t# negExact int"%}
8005   ins_encode %{
8006     __ negl($dst$$Register);
8007   %}
8008   ins_pipe(ialu_reg);
8009 %}
8010 
8011 //----------Multiplication/Division Instructions-------------------------------
8012 // Integer Multiplication Instructions
8013 // Multiply Register
8014 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8015   match(Set dst (MulI dst src));
8016   effect(KILL cr);
8017 
8018   size(3);
8019   ins_cost(300);
8020   format %{ "IMUL   $dst,$src" %}
8021   opcode(0xAF, 0x0F);
8022   ins_encode( OpcS, OpcP, RegReg( dst, src) );
8023   ins_pipe( ialu_reg_reg_alu0 );
8024 %}
8025 
8026 // Multiply 32-bit Immediate
8027 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
8028   match(Set dst (MulI src imm));
8029   effect(KILL cr);
8030 
8031   ins_cost(300);
8032   format %{ "IMUL   $dst,$src,$imm" %}
8033   opcode(0x69);  /* 69 /r id */
8034   ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8035   ins_pipe( ialu_reg_reg_alu0 );
8036 %}
8037 
8038 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8039   match(Set dst src);
8040   effect(KILL cr);
8041 
8042   // Note that this is artificially increased to make it more expensive than loadConL
8043   ins_cost(250);
8044   format %{ "MOV    EAX,$src\t// low word only" %}
8045   opcode(0xB8);
8046   ins_encode( LdImmL_Lo(dst, src) );
8047   ins_pipe( ialu_reg_fat );
8048 %}
8049 
8050 // Multiply by 32-bit Immediate, taking the shifted high order results
8051 //  (special case for shift by 32)
8052 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8053   match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8054   predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8055              _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8056              _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8057   effect(USE src1, KILL cr);
8058 
8059   // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8060   ins_cost(0*100 + 1*400 - 150);
8061   format %{ "IMUL   EDX:EAX,$src1" %}
8062   ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8063   ins_pipe( pipe_slow );
8064 %}
8065 
8066 // Multiply by 32-bit Immediate, taking the shifted high order results
8067 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8068   match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8069   predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8070              _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8071              _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8072   effect(USE src1, KILL cr);
8073 
8074   // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8075   ins_cost(1*100 + 1*400 - 150);
8076   format %{ "IMUL   EDX:EAX,$src1\n\t"
8077             "SAR    EDX,$cnt-32" %}
8078   ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8079   ins_pipe( pipe_slow );
8080 %}
8081 
8082 // Multiply Memory 32-bit Immediate
8083 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
8084   match(Set dst (MulI (LoadI src) imm));
8085   effect(KILL cr);
8086 
8087   ins_cost(300);
8088   format %{ "IMUL   $dst,$src,$imm" %}
8089   opcode(0x69);  /* 69 /r id */
8090   ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8091   ins_pipe( ialu_reg_mem_alu0 );
8092 %}
8093 
8094 // Multiply Memory
8095 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
8096   match(Set dst (MulI dst (LoadI src)));
8097   effect(KILL cr);
8098 
8099   ins_cost(350);
8100   format %{ "IMUL   $dst,$src" %}
8101   opcode(0xAF, 0x0F);
8102   ins_encode( OpcS, OpcP, RegMem( dst, src) );
8103   ins_pipe( ialu_reg_mem_alu0 );
8104 %}
8105 
8106 // Multiply Register Int to Long
8107 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8108   // Basic Idea: long = (long)int * (long)int
8109   match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8110   effect(DEF dst, USE src, USE src1, KILL flags);
8111 
8112   ins_cost(300);
8113   format %{ "IMUL   $dst,$src1" %}
8114 
8115   ins_encode( long_int_multiply( dst, src1 ) );
8116   ins_pipe( ialu_reg_reg_alu0 );
8117 %}
8118 
8119 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8120   // Basic Idea:  long = (int & 0xffffffffL) * (int & 0xffffffffL)
8121   match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8122   effect(KILL flags);
8123 
8124   ins_cost(300);
8125   format %{ "MUL    $dst,$src1" %}
8126 
8127   ins_encode( long_uint_multiply(dst, src1) );
8128   ins_pipe( ialu_reg_reg_alu0 );
8129 %}
8130 
8131 // Multiply Register Long
8132 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8133   match(Set dst (MulL dst src));
8134   effect(KILL cr, TEMP tmp);
8135   ins_cost(4*100+3*400);
8136 // Basic idea: lo(result) = lo(x_lo * y_lo)
8137 //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8138   format %{ "MOV    $tmp,$src.lo\n\t"
8139             "IMUL   $tmp,EDX\n\t"
8140             "MOV    EDX,$src.hi\n\t"
8141             "IMUL   EDX,EAX\n\t"
8142             "ADD    $tmp,EDX\n\t"
8143             "MUL    EDX:EAX,$src.lo\n\t"
8144             "ADD    EDX,$tmp" %}
8145   ins_encode( long_multiply( dst, src, tmp ) );
8146   ins_pipe( pipe_slow );
8147 %}
8148 
8149 // Multiply Register Long where the left operand's high 32 bits are zero
8150 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8151   predicate(is_operand_hi32_zero(n->in(1)));
8152   match(Set dst (MulL dst src));
8153   effect(KILL cr, TEMP tmp);
8154   ins_cost(2*100+2*400);
8155 // Basic idea: lo(result) = lo(x_lo * y_lo)
8156 //             hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8157   format %{ "MOV    $tmp,$src.hi\n\t"
8158             "IMUL   $tmp,EAX\n\t"
8159             "MUL    EDX:EAX,$src.lo\n\t"
8160             "ADD    EDX,$tmp" %}
8161   ins_encode %{
8162     __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8163     __ imull($tmp$$Register, rax);
8164     __ mull($src$$Register);
8165     __ addl(rdx, $tmp$$Register);
8166   %}
8167   ins_pipe( pipe_slow );
8168 %}
8169 
8170 // Multiply Register Long where the right operand's high 32 bits are zero
8171 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8172   predicate(is_operand_hi32_zero(n->in(2)));
8173   match(Set dst (MulL dst src));
8174   effect(KILL cr, TEMP tmp);
8175   ins_cost(2*100+2*400);
8176 // Basic idea: lo(result) = lo(x_lo * y_lo)
8177 //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8178   format %{ "MOV    $tmp,$src.lo\n\t"
8179             "IMUL   $tmp,EDX\n\t"
8180             "MUL    EDX:EAX,$src.lo\n\t"
8181             "ADD    EDX,$tmp" %}
8182   ins_encode %{
8183     __ movl($tmp$$Register, $src$$Register);
8184     __ imull($tmp$$Register, rdx);
8185     __ mull($src$$Register);
8186     __ addl(rdx, $tmp$$Register);
8187   %}
8188   ins_pipe( pipe_slow );
8189 %}
8190 
8191 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8192 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8193   predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8194   match(Set dst (MulL dst src));
8195   effect(KILL cr);
8196   ins_cost(1*400);
8197 // Basic idea: lo(result) = lo(x_lo * y_lo)
8198 //             hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8199   format %{ "MUL    EDX:EAX,$src.lo\n\t" %}
8200   ins_encode %{
8201     __ mull($src$$Register);
8202   %}
8203   ins_pipe( pipe_slow );
8204 %}
8205 
8206 // Multiply Register Long by small constant
8207 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8208   match(Set dst (MulL dst src));
8209   effect(KILL cr, TEMP tmp);
8210   ins_cost(2*100+2*400);
8211   size(12);
8212 // Basic idea: lo(result) = lo(src * EAX)
8213 //             hi(result) = hi(src * EAX) + lo(src * EDX)
8214   format %{ "IMUL   $tmp,EDX,$src\n\t"
8215             "MOV    EDX,$src\n\t"
8216             "MUL    EDX\t# EDX*EAX -> EDX:EAX\n\t"
8217             "ADD    EDX,$tmp" %}
8218   ins_encode( long_multiply_con( dst, src, tmp ) );
8219   ins_pipe( pipe_slow );
8220 %}
8221 
8222 instruct mulExactI_eReg(eAXRegI dst, rRegI src, eFlagsReg cr)
8223 %{
8224   match(MulExactI dst src);
8225   effect(DEF cr);
8226 
8227   ins_cost(300);
8228   format %{ "IMUL   $dst, $src\t# mulExact int" %}
8229   ins_encode %{
8230     __ imull($dst$$Register, $src$$Register);
8231   %}
8232   ins_pipe(ialu_reg_reg_alu0);
8233 %}
8234 
8235 instruct mulExactI_eReg_imm(eAXRegI dst, rRegI src, immI imm, eFlagsReg cr)
8236 %{
8237   match(MulExactI src imm);
8238   effect(DEF cr);
8239 
8240   ins_cost(300);
8241   format %{ "IMUL   $dst, $src, $imm\t# mulExact int" %}
8242   ins_encode %{
8243     __ imull($dst$$Register, $src$$Register, $imm$$constant);
8244   %}
8245   ins_pipe(ialu_reg_reg_alu0);
8246 %}
8247 
8248 instruct mulExactI_eReg_mem(eAXRegI dst, memory src, eFlagsReg cr)
8249 %{
8250   match(MulExactI dst (LoadI src));
8251   effect(DEF cr);
8252 
8253   ins_cost(350);
8254   format %{ "IMUL   $dst, $src\t# mulExact int" %}
8255   ins_encode %{
8256     __ imull($dst$$Register, $src$$Address);
8257   %}
8258   ins_pipe(ialu_reg_mem_alu0);
8259 %}
8260 
8261 
8262 // Integer DIV with Register
8263 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8264   match(Set rax (DivI rax div));
8265   effect(KILL rdx, KILL cr);
8266   size(26);
8267   ins_cost(30*100+10*100);
8268   format %{ "CMP    EAX,0x80000000\n\t"
8269             "JNE,s  normal\n\t"
8270             "XOR    EDX,EDX\n\t"
8271             "CMP    ECX,-1\n\t"
8272             "JE,s   done\n"
8273     "normal: CDQ\n\t"
8274             "IDIV   $div\n\t"
8275     "done:"        %}
8276   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8277   ins_encode( cdq_enc, OpcP, RegOpc(div) );
8278   ins_pipe( ialu_reg_reg_alu0 );
8279 %}
8280 
8281 // Divide Register Long
8282 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8283   match(Set dst (DivL src1 src2));
8284   effect( KILL cr, KILL cx, KILL bx );
8285   ins_cost(10000);
8286   format %{ "PUSH   $src1.hi\n\t"
8287             "PUSH   $src1.lo\n\t"
8288             "PUSH   $src2.hi\n\t"
8289             "PUSH   $src2.lo\n\t"
8290             "CALL   SharedRuntime::ldiv\n\t"
8291             "ADD    ESP,16" %}
8292   ins_encode( long_div(src1,src2) );
8293   ins_pipe( pipe_slow );
8294 %}
8295 
8296 // Integer DIVMOD with Register, both quotient and mod results
8297 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8298   match(DivModI rax div);
8299   effect(KILL cr);
8300   size(26);
8301   ins_cost(30*100+10*100);
8302   format %{ "CMP    EAX,0x80000000\n\t"
8303             "JNE,s  normal\n\t"
8304             "XOR    EDX,EDX\n\t"
8305             "CMP    ECX,-1\n\t"
8306             "JE,s   done\n"
8307     "normal: CDQ\n\t"
8308             "IDIV   $div\n\t"
8309     "done:"        %}
8310   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8311   ins_encode( cdq_enc, OpcP, RegOpc(div) );
8312   ins_pipe( pipe_slow );
8313 %}
8314 
8315 // Integer MOD with Register
8316 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8317   match(Set rdx (ModI rax div));
8318   effect(KILL rax, KILL cr);
8319 
8320   size(26);
8321   ins_cost(300);
8322   format %{ "CDQ\n\t"
8323             "IDIV   $div" %}
8324   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8325   ins_encode( cdq_enc, OpcP, RegOpc(div) );
8326   ins_pipe( ialu_reg_reg_alu0 );
8327 %}
8328 
8329 // Remainder Register Long
8330 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8331   match(Set dst (ModL src1 src2));
8332   effect( KILL cr, KILL cx, KILL bx );
8333   ins_cost(10000);
8334   format %{ "PUSH   $src1.hi\n\t"
8335             "PUSH   $src1.lo\n\t"
8336             "PUSH   $src2.hi\n\t"
8337             "PUSH   $src2.lo\n\t"
8338             "CALL   SharedRuntime::lrem\n\t"
8339             "ADD    ESP,16" %}
8340   ins_encode( long_mod(src1,src2) );
8341   ins_pipe( pipe_slow );
8342 %}
8343 
8344 // Divide Register Long (no special case since divisor != -1)
8345 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8346   match(Set dst (DivL dst imm));
8347   effect( TEMP tmp, TEMP tmp2, KILL cr );
8348   ins_cost(1000);
8349   format %{ "MOV    $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8350             "XOR    $tmp2,$tmp2\n\t"
8351             "CMP    $tmp,EDX\n\t"
8352             "JA,s   fast\n\t"
8353             "MOV    $tmp2,EAX\n\t"
8354             "MOV    EAX,EDX\n\t"
8355             "MOV    EDX,0\n\t"
8356             "JLE,s  pos\n\t"
8357             "LNEG   EAX : $tmp2\n\t"
8358             "DIV    $tmp # unsigned division\n\t"
8359             "XCHG   EAX,$tmp2\n\t"
8360             "DIV    $tmp\n\t"
8361             "LNEG   $tmp2 : EAX\n\t"
8362             "JMP,s  done\n"
8363     "pos:\n\t"
8364             "DIV    $tmp\n\t"
8365             "XCHG   EAX,$tmp2\n"
8366     "fast:\n\t"
8367             "DIV    $tmp\n"
8368     "done:\n\t"
8369             "MOV    EDX,$tmp2\n\t"
8370             "NEG    EDX:EAX # if $imm < 0" %}
8371   ins_encode %{
8372     int con = (int)$imm$$constant;
8373     assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8374     int pcon = (con > 0) ? con : -con;
8375     Label Lfast, Lpos, Ldone;
8376 
8377     __ movl($tmp$$Register, pcon);
8378     __ xorl($tmp2$$Register,$tmp2$$Register);
8379     __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8380     __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8381 
8382     __ movl($tmp2$$Register, $dst$$Register); // save
8383     __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8384     __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8385     __ jccb(Assembler::lessEqual, Lpos); // result is positive
8386 
8387     // Negative dividend.
8388     // convert value to positive to use unsigned division
8389     __ lneg($dst$$Register, $tmp2$$Register);
8390     __ divl($tmp$$Register);
8391     __ xchgl($dst$$Register, $tmp2$$Register);
8392     __ divl($tmp$$Register);
8393     // revert result back to negative
8394     __ lneg($tmp2$$Register, $dst$$Register);
8395     __ jmpb(Ldone);
8396 
8397     __ bind(Lpos);
8398     __ divl($tmp$$Register); // Use unsigned division
8399     __ xchgl($dst$$Register, $tmp2$$Register);
8400     // Fallthrow for final divide, tmp2 has 32 bit hi result
8401 
8402     __ bind(Lfast);
8403     // fast path: src is positive
8404     __ divl($tmp$$Register); // Use unsigned division
8405 
8406     __ bind(Ldone);
8407     __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8408     if (con < 0) {
8409       __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8410     }
8411   %}
8412   ins_pipe( pipe_slow );
8413 %}
8414 
8415 // Remainder Register Long (remainder fit into 32 bits)
8416 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8417   match(Set dst (ModL dst imm));
8418   effect( TEMP tmp, TEMP tmp2, KILL cr );
8419   ins_cost(1000);
8420   format %{ "MOV    $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8421             "CMP    $tmp,EDX\n\t"
8422             "JA,s   fast\n\t"
8423             "MOV    $tmp2,EAX\n\t"
8424             "MOV    EAX,EDX\n\t"
8425             "MOV    EDX,0\n\t"
8426             "JLE,s  pos\n\t"
8427             "LNEG   EAX : $tmp2\n\t"
8428             "DIV    $tmp # unsigned division\n\t"
8429             "MOV    EAX,$tmp2\n\t"
8430             "DIV    $tmp\n\t"
8431             "NEG    EDX\n\t"
8432             "JMP,s  done\n"
8433     "pos:\n\t"
8434             "DIV    $tmp\n\t"
8435             "MOV    EAX,$tmp2\n"
8436     "fast:\n\t"
8437             "DIV    $tmp\n"
8438     "done:\n\t"
8439             "MOV    EAX,EDX\n\t"
8440             "SAR    EDX,31\n\t" %}
8441   ins_encode %{
8442     int con = (int)$imm$$constant;
8443     assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8444     int pcon = (con > 0) ? con : -con;
8445     Label  Lfast, Lpos, Ldone;
8446 
8447     __ movl($tmp$$Register, pcon);
8448     __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8449     __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8450 
8451     __ movl($tmp2$$Register, $dst$$Register); // save
8452     __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8453     __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8454     __ jccb(Assembler::lessEqual, Lpos); // result is positive
8455 
8456     // Negative dividend.
8457     // convert value to positive to use unsigned division
8458     __ lneg($dst$$Register, $tmp2$$Register);
8459     __ divl($tmp$$Register);
8460     __ movl($dst$$Register, $tmp2$$Register);
8461     __ divl($tmp$$Register);
8462     // revert remainder back to negative
8463     __ negl(HIGH_FROM_LOW($dst$$Register));
8464     __ jmpb(Ldone);
8465 
8466     __ bind(Lpos);
8467     __ divl($tmp$$Register);
8468     __ movl($dst$$Register, $tmp2$$Register);
8469 
8470     __ bind(Lfast);
8471     // fast path: src is positive
8472     __ divl($tmp$$Register);
8473 
8474     __ bind(Ldone);
8475     __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8476     __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8477 
8478   %}
8479   ins_pipe( pipe_slow );
8480 %}
8481 
8482 // Integer Shift Instructions
8483 // Shift Left by one
8484 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8485   match(Set dst (LShiftI dst shift));
8486   effect(KILL cr);
8487 
8488   size(2);
8489   format %{ "SHL    $dst,$shift" %}
8490   opcode(0xD1, 0x4);  /* D1 /4 */
8491   ins_encode( OpcP, RegOpc( dst ) );
8492   ins_pipe( ialu_reg );
8493 %}
8494 
8495 // Shift Left by 8-bit immediate
8496 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8497   match(Set dst (LShiftI dst shift));
8498   effect(KILL cr);
8499 
8500   size(3);
8501   format %{ "SHL    $dst,$shift" %}
8502   opcode(0xC1, 0x4);  /* C1 /4 ib */
8503   ins_encode( RegOpcImm( dst, shift) );
8504   ins_pipe( ialu_reg );
8505 %}
8506 
8507 // Shift Left by variable
8508 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8509   match(Set dst (LShiftI dst shift));
8510   effect(KILL cr);
8511 
8512   size(2);
8513   format %{ "SHL    $dst,$shift" %}
8514   opcode(0xD3, 0x4);  /* D3 /4 */
8515   ins_encode( OpcP, RegOpc( dst ) );
8516   ins_pipe( ialu_reg_reg );
8517 %}
8518 
8519 // Arithmetic shift right by one
8520 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8521   match(Set dst (RShiftI dst shift));
8522   effect(KILL cr);
8523 
8524   size(2);
8525   format %{ "SAR    $dst,$shift" %}
8526   opcode(0xD1, 0x7);  /* D1 /7 */
8527   ins_encode( OpcP, RegOpc( dst ) );
8528   ins_pipe( ialu_reg );
8529 %}
8530 
8531 // Arithmetic shift right by one
8532 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8533   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8534   effect(KILL cr);
8535   format %{ "SAR    $dst,$shift" %}
8536   opcode(0xD1, 0x7);  /* D1 /7 */
8537   ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8538   ins_pipe( ialu_mem_imm );
8539 %}
8540 
8541 // Arithmetic Shift Right by 8-bit immediate
8542 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8543   match(Set dst (RShiftI dst shift));
8544   effect(KILL cr);
8545 
8546   size(3);
8547   format %{ "SAR    $dst,$shift" %}
8548   opcode(0xC1, 0x7);  /* C1 /7 ib */
8549   ins_encode( RegOpcImm( dst, shift ) );
8550   ins_pipe( ialu_mem_imm );
8551 %}
8552 
8553 // Arithmetic Shift Right by 8-bit immediate
8554 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8555   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8556   effect(KILL cr);
8557 
8558   format %{ "SAR    $dst,$shift" %}
8559   opcode(0xC1, 0x7);  /* C1 /7 ib */
8560   ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8561   ins_pipe( ialu_mem_imm );
8562 %}
8563 
8564 // Arithmetic Shift Right by variable
8565 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8566   match(Set dst (RShiftI dst shift));
8567   effect(KILL cr);
8568 
8569   size(2);
8570   format %{ "SAR    $dst,$shift" %}
8571   opcode(0xD3, 0x7);  /* D3 /7 */
8572   ins_encode( OpcP, RegOpc( dst ) );
8573   ins_pipe( ialu_reg_reg );
8574 %}
8575 
8576 // Logical shift right by one
8577 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8578   match(Set dst (URShiftI dst shift));
8579   effect(KILL cr);
8580 
8581   size(2);
8582   format %{ "SHR    $dst,$shift" %}
8583   opcode(0xD1, 0x5);  /* D1 /5 */
8584   ins_encode( OpcP, RegOpc( dst ) );
8585   ins_pipe( ialu_reg );
8586 %}
8587 
8588 // Logical Shift Right by 8-bit immediate
8589 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8590   match(Set dst (URShiftI dst shift));
8591   effect(KILL cr);
8592 
8593   size(3);
8594   format %{ "SHR    $dst,$shift" %}
8595   opcode(0xC1, 0x5);  /* C1 /5 ib */
8596   ins_encode( RegOpcImm( dst, shift) );
8597   ins_pipe( ialu_reg );
8598 %}
8599 
8600 
8601 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8602 // This idiom is used by the compiler for the i2b bytecode.
8603 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8604   match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8605 
8606   size(3);
8607   format %{ "MOVSX  $dst,$src :8" %}
8608   ins_encode %{
8609     __ movsbl($dst$$Register, $src$$Register);
8610   %}
8611   ins_pipe(ialu_reg_reg);
8612 %}
8613 
8614 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8615 // This idiom is used by the compiler the i2s bytecode.
8616 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8617   match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8618 
8619   size(3);
8620   format %{ "MOVSX  $dst,$src :16" %}
8621   ins_encode %{
8622     __ movswl($dst$$Register, $src$$Register);
8623   %}
8624   ins_pipe(ialu_reg_reg);
8625 %}
8626 
8627 
8628 // Logical Shift Right by variable
8629 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8630   match(Set dst (URShiftI dst shift));
8631   effect(KILL cr);
8632 
8633   size(2);
8634   format %{ "SHR    $dst,$shift" %}
8635   opcode(0xD3, 0x5);  /* D3 /5 */
8636   ins_encode( OpcP, RegOpc( dst ) );
8637   ins_pipe( ialu_reg_reg );
8638 %}
8639 
8640 
8641 //----------Logical Instructions-----------------------------------------------
8642 //----------Integer Logical Instructions---------------------------------------
8643 // And Instructions
8644 // And Register with Register
8645 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8646   match(Set dst (AndI dst src));
8647   effect(KILL cr);
8648 
8649   size(2);
8650   format %{ "AND    $dst,$src" %}
8651   opcode(0x23);
8652   ins_encode( OpcP, RegReg( dst, src) );
8653   ins_pipe( ialu_reg_reg );
8654 %}
8655 
8656 // And Register with Immediate
8657 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8658   match(Set dst (AndI dst src));
8659   effect(KILL cr);
8660 
8661   format %{ "AND    $dst,$src" %}
8662   opcode(0x81,0x04);  /* Opcode 81 /4 */
8663   // ins_encode( RegImm( dst, src) );
8664   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8665   ins_pipe( ialu_reg );
8666 %}
8667 
8668 // And Register with Memory
8669 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8670   match(Set dst (AndI dst (LoadI src)));
8671   effect(KILL cr);
8672 
8673   ins_cost(125);
8674   format %{ "AND    $dst,$src" %}
8675   opcode(0x23);
8676   ins_encode( OpcP, RegMem( dst, src) );
8677   ins_pipe( ialu_reg_mem );
8678 %}
8679 
8680 // And Memory with Register
8681 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8682   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8683   effect(KILL cr);
8684 
8685   ins_cost(150);
8686   format %{ "AND    $dst,$src" %}
8687   opcode(0x21);  /* Opcode 21 /r */
8688   ins_encode( OpcP, RegMem( src, dst ) );
8689   ins_pipe( ialu_mem_reg );
8690 %}
8691 
8692 // And Memory with Immediate
8693 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8694   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8695   effect(KILL cr);
8696 
8697   ins_cost(125);
8698   format %{ "AND    $dst,$src" %}
8699   opcode(0x81, 0x4);  /* Opcode 81 /4 id */
8700   // ins_encode( MemImm( dst, src) );
8701   ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8702   ins_pipe( ialu_mem_imm );
8703 %}
8704 
8705 // Or Instructions
8706 // Or Register with Register
8707 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8708   match(Set dst (OrI dst src));
8709   effect(KILL cr);
8710 
8711   size(2);
8712   format %{ "OR     $dst,$src" %}
8713   opcode(0x0B);
8714   ins_encode( OpcP, RegReg( dst, src) );
8715   ins_pipe( ialu_reg_reg );
8716 %}
8717 
8718 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8719   match(Set dst (OrI dst (CastP2X src)));
8720   effect(KILL cr);
8721 
8722   size(2);
8723   format %{ "OR     $dst,$src" %}
8724   opcode(0x0B);
8725   ins_encode( OpcP, RegReg( dst, src) );
8726   ins_pipe( ialu_reg_reg );
8727 %}
8728 
8729 
8730 // Or Register with Immediate
8731 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8732   match(Set dst (OrI dst src));
8733   effect(KILL cr);
8734 
8735   format %{ "OR     $dst,$src" %}
8736   opcode(0x81,0x01);  /* Opcode 81 /1 id */
8737   // ins_encode( RegImm( dst, src) );
8738   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8739   ins_pipe( ialu_reg );
8740 %}
8741 
8742 // Or Register with Memory
8743 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8744   match(Set dst (OrI dst (LoadI src)));
8745   effect(KILL cr);
8746 
8747   ins_cost(125);
8748   format %{ "OR     $dst,$src" %}
8749   opcode(0x0B);
8750   ins_encode( OpcP, RegMem( dst, src) );
8751   ins_pipe( ialu_reg_mem );
8752 %}
8753 
8754 // Or Memory with Register
8755 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8756   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8757   effect(KILL cr);
8758 
8759   ins_cost(150);
8760   format %{ "OR     $dst,$src" %}
8761   opcode(0x09);  /* Opcode 09 /r */
8762   ins_encode( OpcP, RegMem( src, dst ) );
8763   ins_pipe( ialu_mem_reg );
8764 %}
8765 
8766 // Or Memory with Immediate
8767 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8768   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8769   effect(KILL cr);
8770 
8771   ins_cost(125);
8772   format %{ "OR     $dst,$src" %}
8773   opcode(0x81,0x1);  /* Opcode 81 /1 id */
8774   // ins_encode( MemImm( dst, src) );
8775   ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8776   ins_pipe( ialu_mem_imm );
8777 %}
8778 
8779 // ROL/ROR
8780 // ROL expand
8781 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8782   effect(USE_DEF dst, USE shift, KILL cr);
8783 
8784   format %{ "ROL    $dst, $shift" %}
8785   opcode(0xD1, 0x0); /* Opcode D1 /0 */
8786   ins_encode( OpcP, RegOpc( dst ));
8787   ins_pipe( ialu_reg );
8788 %}
8789 
8790 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8791   effect(USE_DEF dst, USE shift, KILL cr);
8792 
8793   format %{ "ROL    $dst, $shift" %}
8794   opcode(0xC1, 0x0); /*Opcode /C1  /0  */
8795   ins_encode( RegOpcImm(dst, shift) );
8796   ins_pipe(ialu_reg);
8797 %}
8798 
8799 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8800   effect(USE_DEF dst, USE shift, KILL cr);
8801 
8802   format %{ "ROL    $dst, $shift" %}
8803   opcode(0xD3, 0x0);    /* Opcode D3 /0 */
8804   ins_encode(OpcP, RegOpc(dst));
8805   ins_pipe( ialu_reg_reg );
8806 %}
8807 // end of ROL expand
8808 
8809 // ROL 32bit by one once
8810 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8811   match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8812 
8813   expand %{
8814     rolI_eReg_imm1(dst, lshift, cr);
8815   %}
8816 %}
8817 
8818 // ROL 32bit var by imm8 once
8819 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8820   predicate(  0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8821   match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8822 
8823   expand %{
8824     rolI_eReg_imm8(dst, lshift, cr);
8825   %}
8826 %}
8827 
8828 // ROL 32bit var by var once
8829 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8830   match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8831 
8832   expand %{
8833     rolI_eReg_CL(dst, shift, cr);
8834   %}
8835 %}
8836 
8837 // ROL 32bit var by var once
8838 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8839   match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8840 
8841   expand %{
8842     rolI_eReg_CL(dst, shift, cr);
8843   %}
8844 %}
8845 
8846 // ROR expand
8847 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8848   effect(USE_DEF dst, USE shift, KILL cr);
8849 
8850   format %{ "ROR    $dst, $shift" %}
8851   opcode(0xD1,0x1);  /* Opcode D1 /1 */
8852   ins_encode( OpcP, RegOpc( dst ) );
8853   ins_pipe( ialu_reg );
8854 %}
8855 
8856 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8857   effect (USE_DEF dst, USE shift, KILL cr);
8858 
8859   format %{ "ROR    $dst, $shift" %}
8860   opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8861   ins_encode( RegOpcImm(dst, shift) );
8862   ins_pipe( ialu_reg );
8863 %}
8864 
8865 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8866   effect(USE_DEF dst, USE shift, KILL cr);
8867 
8868   format %{ "ROR    $dst, $shift" %}
8869   opcode(0xD3, 0x1);    /* Opcode D3 /1 */
8870   ins_encode(OpcP, RegOpc(dst));
8871   ins_pipe( ialu_reg_reg );
8872 %}
8873 // end of ROR expand
8874 
8875 // ROR right once
8876 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8877   match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8878 
8879   expand %{
8880     rorI_eReg_imm1(dst, rshift, cr);
8881   %}
8882 %}
8883 
8884 // ROR 32bit by immI8 once
8885 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8886   predicate(  0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8887   match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8888 
8889   expand %{
8890     rorI_eReg_imm8(dst, rshift, cr);
8891   %}
8892 %}
8893 
8894 // ROR 32bit var by var once
8895 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8896   match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8897 
8898   expand %{
8899     rorI_eReg_CL(dst, shift, cr);
8900   %}
8901 %}
8902 
8903 // ROR 32bit var by var once
8904 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8905   match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8906 
8907   expand %{
8908     rorI_eReg_CL(dst, shift, cr);
8909   %}
8910 %}
8911 
8912 // Xor Instructions
8913 // Xor Register with Register
8914 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8915   match(Set dst (XorI dst src));
8916   effect(KILL cr);
8917 
8918   size(2);
8919   format %{ "XOR    $dst,$src" %}
8920   opcode(0x33);
8921   ins_encode( OpcP, RegReg( dst, src) );
8922   ins_pipe( ialu_reg_reg );
8923 %}
8924 
8925 // Xor Register with Immediate -1
8926 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8927   match(Set dst (XorI dst imm));  
8928 
8929   size(2);
8930   format %{ "NOT    $dst" %}  
8931   ins_encode %{
8932      __ notl($dst$$Register);
8933   %}
8934   ins_pipe( ialu_reg );
8935 %}
8936 
8937 // Xor Register with Immediate
8938 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8939   match(Set dst (XorI dst src));
8940   effect(KILL cr);
8941 
8942   format %{ "XOR    $dst,$src" %}
8943   opcode(0x81,0x06);  /* Opcode 81 /6 id */
8944   // ins_encode( RegImm( dst, src) );
8945   ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8946   ins_pipe( ialu_reg );
8947 %}
8948 
8949 // Xor Register with Memory
8950 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8951   match(Set dst (XorI dst (LoadI src)));
8952   effect(KILL cr);
8953 
8954   ins_cost(125);
8955   format %{ "XOR    $dst,$src" %}
8956   opcode(0x33);
8957   ins_encode( OpcP, RegMem(dst, src) );
8958   ins_pipe( ialu_reg_mem );
8959 %}
8960 
8961 // Xor Memory with Register
8962 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8963   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8964   effect(KILL cr);
8965 
8966   ins_cost(150);
8967   format %{ "XOR    $dst,$src" %}
8968   opcode(0x31);  /* Opcode 31 /r */
8969   ins_encode( OpcP, RegMem( src, dst ) );
8970   ins_pipe( ialu_mem_reg );
8971 %}
8972 
8973 // Xor Memory with Immediate
8974 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8975   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8976   effect(KILL cr);
8977 
8978   ins_cost(125);
8979   format %{ "XOR    $dst,$src" %}
8980   opcode(0x81,0x6);  /* Opcode 81 /6 id */
8981   ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8982   ins_pipe( ialu_mem_imm );
8983 %}
8984 
8985 //----------Convert Int to Boolean---------------------------------------------
8986 
8987 instruct movI_nocopy(rRegI dst, rRegI src) %{
8988   effect( DEF dst, USE src );
8989   format %{ "MOV    $dst,$src" %}
8990   ins_encode( enc_Copy( dst, src) );
8991   ins_pipe( ialu_reg_reg );
8992 %}
8993 
8994 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8995   effect( USE_DEF dst, USE src, KILL cr );
8996 
8997   size(4);
8998   format %{ "NEG    $dst\n\t"
8999             "ADC    $dst,$src" %}
9000   ins_encode( neg_reg(dst),
9001               OpcRegReg(0x13,dst,src) );
9002   ins_pipe( ialu_reg_reg_long );
9003 %}
9004 
9005 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
9006   match(Set dst (Conv2B src));
9007 
9008   expand %{
9009     movI_nocopy(dst,src);
9010     ci2b(dst,src,cr);
9011   %}
9012 %}
9013 
9014 instruct movP_nocopy(rRegI dst, eRegP src) %{
9015   effect( DEF dst, USE src );
9016   format %{ "MOV    $dst,$src" %}
9017   ins_encode( enc_Copy( dst, src) );
9018   ins_pipe( ialu_reg_reg );
9019 %}
9020 
9021 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
9022   effect( USE_DEF dst, USE src, KILL cr );
9023   format %{ "NEG    $dst\n\t"
9024             "ADC    $dst,$src" %}
9025   ins_encode( neg_reg(dst),
9026               OpcRegReg(0x13,dst,src) );
9027   ins_pipe( ialu_reg_reg_long );
9028 %}
9029 
9030 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
9031   match(Set dst (Conv2B src));
9032 
9033   expand %{
9034     movP_nocopy(dst,src);
9035     cp2b(dst,src,cr);
9036   %}
9037 %}
9038 
9039 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
9040   match(Set dst (CmpLTMask p q));
9041   effect(KILL cr);
9042   ins_cost(400);
9043 
9044   // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9045   format %{ "XOR    $dst,$dst\n\t"
9046             "CMP    $p,$q\n\t"
9047             "SETlt  $dst\n\t"
9048             "NEG    $dst" %}
9049   ins_encode %{
9050     Register Rp = $p$$Register;
9051     Register Rq = $q$$Register;
9052     Register Rd = $dst$$Register;
9053     Label done;
9054     __ xorl(Rd, Rd);
9055     __ cmpl(Rp, Rq);
9056     __ setb(Assembler::less, Rd);
9057     __ negl(Rd);
9058   %}
9059 
9060   ins_pipe(pipe_slow);
9061 %}
9062 
9063 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
9064   match(Set dst (CmpLTMask dst zero));
9065   effect(DEF dst, KILL cr);
9066   ins_cost(100);
9067 
9068   format %{ "SAR    $dst,31\t# cmpLTMask0" %}
9069   ins_encode %{
9070   __ sarl($dst$$Register, 31);
9071   %}
9072   ins_pipe(ialu_reg);
9073 %}
9074 
9075 /* better to save a register than avoid a branch */
9076 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
9077   match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9078   effect(KILL cr);
9079   ins_cost(400);
9080   format %{ "SUB    $p,$q\t# cadd_cmpLTMask\n\t"
9081             "JGE    done\n\t"
9082             "ADD    $p,$y\n"
9083             "done:  " %}
9084   ins_encode %{
9085     Register Rp = $p$$Register;
9086     Register Rq = $q$$Register;
9087     Register Ry = $y$$Register;
9088     Label done;
9089     __ subl(Rp, Rq);
9090     __ jccb(Assembler::greaterEqual, done);
9091     __ addl(Rp, Ry);
9092     __ bind(done);
9093   %}
9094 
9095   ins_pipe(pipe_cmplt);
9096 %}
9097 
9098 /* better to save a register than avoid a branch */
9099 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
9100   match(Set y (AndI (CmpLTMask p q) y));
9101   effect(KILL cr);
9102 
9103   ins_cost(300);
9104 
9105   format %{ "CMPL     $p, $q\t# and_cmpLTMask\n\t"
9106             "JLT      done\n\t"
9107             "XORL     $y, $y\n"
9108             "done:  " %}
9109   ins_encode %{
9110     Register Rp = $p$$Register;
9111     Register Rq = $q$$Register;
9112     Register Ry = $y$$Register;
9113     Label done;
9114     __ cmpl(Rp, Rq);
9115     __ jccb(Assembler::less, done);
9116     __ xorl(Ry, Ry);
9117     __ bind(done);
9118   %}
9119 
9120   ins_pipe(pipe_cmplt);
9121 %}
9122 
9123 /* If I enable this, I encourage spilling in the inner loop of compress.
9124 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
9125   match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9126 */
9127 
9128 //----------Long Instructions------------------------------------------------
9129 // Add Long Register with Register
9130 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9131   match(Set dst (AddL dst src));
9132   effect(KILL cr);
9133   ins_cost(200);
9134   format %{ "ADD    $dst.lo,$src.lo\n\t"
9135             "ADC    $dst.hi,$src.hi" %}
9136   opcode(0x03, 0x13);
9137   ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9138   ins_pipe( ialu_reg_reg_long );
9139 %}
9140 
9141 // Add Long Register with Immediate
9142 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9143   match(Set dst (AddL dst src));
9144   effect(KILL cr);
9145   format %{ "ADD    $dst.lo,$src.lo\n\t"
9146             "ADC    $dst.hi,$src.hi" %}
9147   opcode(0x81,0x00,0x02);  /* Opcode 81 /0, 81 /2 */
9148   ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9149   ins_pipe( ialu_reg_long );
9150 %}
9151 
9152 // Add Long Register with Memory
9153 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9154   match(Set dst (AddL dst (LoadL mem)));
9155   effect(KILL cr);
9156   ins_cost(125);
9157   format %{ "ADD    $dst.lo,$mem\n\t"
9158             "ADC    $dst.hi,$mem+4" %}
9159   opcode(0x03, 0x13);
9160   ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9161   ins_pipe( ialu_reg_long_mem );
9162 %}
9163 
9164 // Subtract Long Register with Register.
9165 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9166   match(Set dst (SubL dst src));
9167   effect(KILL cr);
9168   ins_cost(200);
9169   format %{ "SUB    $dst.lo,$src.lo\n\t"
9170             "SBB    $dst.hi,$src.hi" %}
9171   opcode(0x2B, 0x1B);
9172   ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9173   ins_pipe( ialu_reg_reg_long );
9174 %}
9175 
9176 // Subtract Long Register with Immediate
9177 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9178   match(Set dst (SubL dst src));
9179   effect(KILL cr);
9180   format %{ "SUB    $dst.lo,$src.lo\n\t"
9181             "SBB    $dst.hi,$src.hi" %}
9182   opcode(0x81,0x05,0x03);  /* Opcode 81 /5, 81 /3 */
9183   ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9184   ins_pipe( ialu_reg_long );
9185 %}
9186 
9187 // Subtract Long Register with Memory
9188 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9189   match(Set dst (SubL dst (LoadL mem)));
9190   effect(KILL cr);
9191   ins_cost(125);
9192   format %{ "SUB    $dst.lo,$mem\n\t"
9193             "SBB    $dst.hi,$mem+4" %}
9194   opcode(0x2B, 0x1B);
9195   ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9196   ins_pipe( ialu_reg_long_mem );
9197 %}
9198 
9199 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9200   match(Set dst (SubL zero dst));
9201   effect(KILL cr);
9202   ins_cost(300);
9203   format %{ "NEG    $dst.hi\n\tNEG    $dst.lo\n\tSBB    $dst.hi,0" %}
9204   ins_encode( neg_long(dst) );
9205   ins_pipe( ialu_reg_reg_long );
9206 %}
9207 
9208 // And Long Register with Register
9209 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9210   match(Set dst (AndL dst src));
9211   effect(KILL cr);
9212   format %{ "AND    $dst.lo,$src.lo\n\t"
9213             "AND    $dst.hi,$src.hi" %}
9214   opcode(0x23,0x23);
9215   ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9216   ins_pipe( ialu_reg_reg_long );
9217 %}
9218 
9219 // And Long Register with Immediate
9220 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9221   match(Set dst (AndL dst src));
9222   effect(KILL cr);
9223   format %{ "AND    $dst.lo,$src.lo\n\t"
9224             "AND    $dst.hi,$src.hi" %}
9225   opcode(0x81,0x04,0x04);  /* Opcode 81 /4, 81 /4 */
9226   ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9227   ins_pipe( ialu_reg_long );
9228 %}
9229 
9230 // And Long Register with Memory
9231 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9232   match(Set dst (AndL dst (LoadL mem)));
9233   effect(KILL cr);
9234   ins_cost(125);
9235   format %{ "AND    $dst.lo,$mem\n\t"
9236             "AND    $dst.hi,$mem+4" %}
9237   opcode(0x23, 0x23);
9238   ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9239   ins_pipe( ialu_reg_long_mem );
9240 %}
9241 
9242 // Or Long Register with Register
9243 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9244   match(Set dst (OrL dst src));
9245   effect(KILL cr);
9246   format %{ "OR     $dst.lo,$src.lo\n\t"
9247             "OR     $dst.hi,$src.hi" %}
9248   opcode(0x0B,0x0B);
9249   ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9250   ins_pipe( ialu_reg_reg_long );
9251 %}
9252 
9253 // Or Long Register with Immediate
9254 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9255   match(Set dst (OrL dst src));
9256   effect(KILL cr);
9257   format %{ "OR     $dst.lo,$src.lo\n\t"
9258             "OR     $dst.hi,$src.hi" %}
9259   opcode(0x81,0x01,0x01);  /* Opcode 81 /1, 81 /1 */
9260   ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9261   ins_pipe( ialu_reg_long );
9262 %}
9263 
9264 // Or Long Register with Memory
9265 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9266   match(Set dst (OrL dst (LoadL mem)));
9267   effect(KILL cr);
9268   ins_cost(125);
9269   format %{ "OR     $dst.lo,$mem\n\t"
9270             "OR     $dst.hi,$mem+4" %}
9271   opcode(0x0B,0x0B);
9272   ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9273   ins_pipe( ialu_reg_long_mem );
9274 %}
9275 
9276 // Xor Long Register with Register
9277 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9278   match(Set dst (XorL dst src));
9279   effect(KILL cr);
9280   format %{ "XOR    $dst.lo,$src.lo\n\t"
9281             "XOR    $dst.hi,$src.hi" %}
9282   opcode(0x33,0x33);
9283   ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9284   ins_pipe( ialu_reg_reg_long );
9285 %}
9286 
9287 // Xor Long Register with Immediate -1
9288 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9289   match(Set dst (XorL dst imm));  
9290   format %{ "NOT    $dst.lo\n\t"
9291             "NOT    $dst.hi" %}
9292   ins_encode %{
9293      __ notl($dst$$Register);
9294      __ notl(HIGH_FROM_LOW($dst$$Register));
9295   %}
9296   ins_pipe( ialu_reg_long );
9297 %}
9298 
9299 // Xor Long Register with Immediate
9300 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9301   match(Set dst (XorL dst src));
9302   effect(KILL cr);
9303   format %{ "XOR    $dst.lo,$src.lo\n\t"
9304             "XOR    $dst.hi,$src.hi" %}
9305   opcode(0x81,0x06,0x06);  /* Opcode 81 /6, 81 /6 */
9306   ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9307   ins_pipe( ialu_reg_long );
9308 %}
9309 
9310 // Xor Long Register with Memory
9311 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9312   match(Set dst (XorL dst (LoadL mem)));
9313   effect(KILL cr);
9314   ins_cost(125);
9315   format %{ "XOR    $dst.lo,$mem\n\t"
9316             "XOR    $dst.hi,$mem+4" %}
9317   opcode(0x33,0x33);
9318   ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9319   ins_pipe( ialu_reg_long_mem );
9320 %}
9321 
9322 // Shift Left Long by 1
9323 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9324   predicate(UseNewLongLShift);
9325   match(Set dst (LShiftL dst cnt));
9326   effect(KILL cr);
9327   ins_cost(100);
9328   format %{ "ADD    $dst.lo,$dst.lo\n\t"
9329             "ADC    $dst.hi,$dst.hi" %}
9330   ins_encode %{
9331     __ addl($dst$$Register,$dst$$Register);
9332     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9333   %}
9334   ins_pipe( ialu_reg_long );
9335 %}
9336 
9337 // Shift Left Long by 2
9338 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9339   predicate(UseNewLongLShift);
9340   match(Set dst (LShiftL dst cnt));
9341   effect(KILL cr);
9342   ins_cost(100);
9343   format %{ "ADD    $dst.lo,$dst.lo\n\t"
9344             "ADC    $dst.hi,$dst.hi\n\t" 
9345             "ADD    $dst.lo,$dst.lo\n\t"
9346             "ADC    $dst.hi,$dst.hi" %}
9347   ins_encode %{
9348     __ addl($dst$$Register,$dst$$Register);
9349     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9350     __ addl($dst$$Register,$dst$$Register);
9351     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9352   %}
9353   ins_pipe( ialu_reg_long );
9354 %}
9355 
9356 // Shift Left Long by 3
9357 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9358   predicate(UseNewLongLShift);
9359   match(Set dst (LShiftL dst cnt));
9360   effect(KILL cr);
9361   ins_cost(100);
9362   format %{ "ADD    $dst.lo,$dst.lo\n\t"
9363             "ADC    $dst.hi,$dst.hi\n\t" 
9364             "ADD    $dst.lo,$dst.lo\n\t"
9365             "ADC    $dst.hi,$dst.hi\n\t" 
9366             "ADD    $dst.lo,$dst.lo\n\t"
9367             "ADC    $dst.hi,$dst.hi" %}
9368   ins_encode %{
9369     __ addl($dst$$Register,$dst$$Register);
9370     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9371     __ addl($dst$$Register,$dst$$Register);
9372     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9373     __ addl($dst$$Register,$dst$$Register);
9374     __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9375   %}
9376   ins_pipe( ialu_reg_long );
9377 %}
9378 
9379 // Shift Left Long by 1-31
9380 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9381   match(Set dst (LShiftL dst cnt));
9382   effect(KILL cr);
9383   ins_cost(200);
9384   format %{ "SHLD   $dst.hi,$dst.lo,$cnt\n\t"
9385             "SHL    $dst.lo,$cnt" %}
9386   opcode(0xC1, 0x4, 0xA4);  /* 0F/A4, then C1 /4 ib */
9387   ins_encode( move_long_small_shift(dst,cnt) );
9388   ins_pipe( ialu_reg_long );
9389 %}
9390 
9391 // Shift Left Long by 32-63
9392 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9393   match(Set dst (LShiftL dst cnt));
9394   effect(KILL cr);
9395   ins_cost(300);
9396   format %{ "MOV    $dst.hi,$dst.lo\n"
9397           "\tSHL    $dst.hi,$cnt-32\n"
9398           "\tXOR    $dst.lo,$dst.lo" %}
9399   opcode(0xC1, 0x4);  /* C1 /4 ib */
9400   ins_encode( move_long_big_shift_clr(dst,cnt) );
9401   ins_pipe( ialu_reg_long );
9402 %}
9403 
9404 // Shift Left Long by variable
9405 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9406   match(Set dst (LShiftL dst shift));
9407   effect(KILL cr);
9408   ins_cost(500+200);
9409   size(17);
9410   format %{ "TEST   $shift,32\n\t"
9411             "JEQ,s  small\n\t"
9412             "MOV    $dst.hi,$dst.lo\n\t"
9413             "XOR    $dst.lo,$dst.lo\n"
9414     "small:\tSHLD   $dst.hi,$dst.lo,$shift\n\t"
9415             "SHL    $dst.lo,$shift" %}
9416   ins_encode( shift_left_long( dst, shift ) );
9417   ins_pipe( pipe_slow );
9418 %}
9419 
9420 // Shift Right Long by 1-31
9421 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9422   match(Set dst (URShiftL dst cnt));
9423   effect(KILL cr);
9424   ins_cost(200);
9425   format %{ "SHRD   $dst.lo,$dst.hi,$cnt\n\t"
9426             "SHR    $dst.hi,$cnt" %}
9427   opcode(0xC1, 0x5, 0xAC);  /* 0F/AC, then C1 /5 ib */
9428   ins_encode( move_long_small_shift(dst,cnt) );
9429   ins_pipe( ialu_reg_long );
9430 %}
9431 
9432 // Shift Right Long by 32-63
9433 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9434   match(Set dst (URShiftL dst cnt));
9435   effect(KILL cr);
9436   ins_cost(300);
9437   format %{ "MOV    $dst.lo,$dst.hi\n"
9438           "\tSHR    $dst.lo,$cnt-32\n"
9439           "\tXOR    $dst.hi,$dst.hi" %}
9440   opcode(0xC1, 0x5);  /* C1 /5 ib */
9441   ins_encode( move_long_big_shift_clr(dst,cnt) );
9442   ins_pipe( ialu_reg_long );
9443 %}
9444 
9445 // Shift Right Long by variable
9446 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9447   match(Set dst (URShiftL dst shift));
9448   effect(KILL cr);
9449   ins_cost(600);
9450   size(17);
9451   format %{ "TEST   $shift,32\n\t"
9452             "JEQ,s  small\n\t"
9453             "MOV    $dst.lo,$dst.hi\n\t"
9454             "XOR    $dst.hi,$dst.hi\n"
9455     "small:\tSHRD   $dst.lo,$dst.hi,$shift\n\t"
9456             "SHR    $dst.hi,$shift" %}
9457   ins_encode( shift_right_long( dst, shift ) );
9458   ins_pipe( pipe_slow );
9459 %}
9460 
9461 // Shift Right Long by 1-31
9462 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9463   match(Set dst (RShiftL dst cnt));
9464   effect(KILL cr);
9465   ins_cost(200);
9466   format %{ "SHRD   $dst.lo,$dst.hi,$cnt\n\t"
9467             "SAR    $dst.hi,$cnt" %}
9468   opcode(0xC1, 0x7, 0xAC);  /* 0F/AC, then C1 /7 ib */
9469   ins_encode( move_long_small_shift(dst,cnt) );
9470   ins_pipe( ialu_reg_long );
9471 %}
9472 
9473 // Shift Right Long by 32-63
9474 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9475   match(Set dst (RShiftL dst cnt));
9476   effect(KILL cr);
9477   ins_cost(300);
9478   format %{ "MOV    $dst.lo,$dst.hi\n"
9479           "\tSAR    $dst.lo,$cnt-32\n"
9480           "\tSAR    $dst.hi,31" %}
9481   opcode(0xC1, 0x7);  /* C1 /7 ib */
9482   ins_encode( move_long_big_shift_sign(dst,cnt) );
9483   ins_pipe( ialu_reg_long );
9484 %}
9485 
9486 // Shift Right arithmetic Long by variable
9487 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9488   match(Set dst (RShiftL dst shift));
9489   effect(KILL cr);
9490   ins_cost(600);
9491   size(18);
9492   format %{ "TEST   $shift,32\n\t"
9493             "JEQ,s  small\n\t"
9494             "MOV    $dst.lo,$dst.hi\n\t"
9495             "SAR    $dst.hi,31\n"
9496     "small:\tSHRD   $dst.lo,$dst.hi,$shift\n\t"
9497             "SAR    $dst.hi,$shift" %}
9498   ins_encode( shift_right_arith_long( dst, shift ) );
9499   ins_pipe( pipe_slow );
9500 %}
9501 
9502 
9503 //----------Double Instructions------------------------------------------------
9504 // Double Math
9505 
9506 // Compare & branch
9507 
9508 // P6 version of float compare, sets condition codes in EFLAGS
9509 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9510   predicate(VM_Version::supports_cmov() && UseSSE <=1);
9511   match(Set cr (CmpD src1 src2));
9512   effect(KILL rax);
9513   ins_cost(150);
9514   format %{ "FLD    $src1\n\t"
9515             "FUCOMIP ST,$src2  // P6 instruction\n\t"
9516             "JNP    exit\n\t"
9517             "MOV    ah,1       // saw a NaN, set CF\n\t"
9518             "SAHF\n"
9519      "exit:\tNOP               // avoid branch to branch" %}
9520   opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9521   ins_encode( Push_Reg_DPR(src1),
9522               OpcP, RegOpc(src2),
9523               cmpF_P6_fixup );
9524   ins_pipe( pipe_slow );
9525 %}
9526 
9527 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9528   predicate(VM_Version::supports_cmov() && UseSSE <=1);
9529   match(Set cr (CmpD src1 src2));
9530   ins_cost(150);
9531   format %{ "FLD    $src1\n\t"
9532             "FUCOMIP ST,$src2  // P6 instruction" %}
9533   opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9534   ins_encode( Push_Reg_DPR(src1),
9535               OpcP, RegOpc(src2));
9536   ins_pipe( pipe_slow );
9537 %}
9538 
9539 // Compare & branch
9540 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9541   predicate(UseSSE<=1);
9542   match(Set cr (CmpD src1 src2));
9543   effect(KILL rax);
9544   ins_cost(200);
9545   format %{ "FLD    $src1\n\t"
9546             "FCOMp  $src2\n\t"
9547             "FNSTSW AX\n\t"
9548             "TEST   AX,0x400\n\t"
9549             "JZ,s   flags\n\t"
9550             "MOV    AH,1\t# unordered treat as LT\n"
9551     "flags:\tSAHF" %}
9552   opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9553   ins_encode( Push_Reg_DPR(src1),
9554               OpcP, RegOpc(src2),
9555               fpu_flags);
9556   ins_pipe( pipe_slow );
9557 %}
9558 
9559 // Compare vs zero into -1,0,1
9560 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9561   predicate(UseSSE<=1);
9562   match(Set dst (CmpD3 src1 zero));
9563   effect(KILL cr, KILL rax);
9564   ins_cost(280);
9565   format %{ "FTSTD  $dst,$src1" %}
9566   opcode(0xE4, 0xD9);
9567   ins_encode( Push_Reg_DPR(src1),
9568               OpcS, OpcP, PopFPU,
9569               CmpF_Result(dst));
9570   ins_pipe( pipe_slow );
9571 %}
9572 
9573 // Compare into -1,0,1
9574 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9575   predicate(UseSSE<=1);
9576   match(Set dst (CmpD3 src1 src2));
9577   effect(KILL cr, KILL rax);
9578   ins_cost(300);
9579   format %{ "FCMPD  $dst,$src1,$src2" %}
9580   opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9581   ins_encode( Push_Reg_DPR(src1),
9582               OpcP, RegOpc(src2),
9583               CmpF_Result(dst));
9584   ins_pipe( pipe_slow );
9585 %}
9586 
9587 // float compare and set condition codes in EFLAGS by XMM regs
9588 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9589   predicate(UseSSE>=2);
9590   match(Set cr (CmpD src1 src2));
9591   ins_cost(145);
9592   format %{ "UCOMISD $src1,$src2\n\t"
9593             "JNP,s   exit\n\t"
9594             "PUSHF\t# saw NaN, set CF\n\t"
9595             "AND     [rsp], #0xffffff2b\n\t"
9596             "POPF\n"
9597     "exit:" %}
9598   ins_encode %{
9599     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9600     emit_cmpfp_fixup(_masm);
9601   %}
9602   ins_pipe( pipe_slow );
9603 %}
9604 
9605 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9606   predicate(UseSSE>=2);
9607   match(Set cr (CmpD src1 src2));
9608   ins_cost(100);
9609   format %{ "UCOMISD $src1,$src2" %}
9610   ins_encode %{
9611     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9612   %}
9613   ins_pipe( pipe_slow );
9614 %}
9615 
9616 // float compare and set condition codes in EFLAGS by XMM regs
9617 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9618   predicate(UseSSE>=2);
9619   match(Set cr (CmpD src1 (LoadD src2)));
9620   ins_cost(145);
9621   format %{ "UCOMISD $src1,$src2\n\t"
9622             "JNP,s   exit\n\t"
9623             "PUSHF\t# saw NaN, set CF\n\t"
9624             "AND     [rsp], #0xffffff2b\n\t"
9625             "POPF\n"
9626     "exit:" %}
9627   ins_encode %{
9628     __ ucomisd($src1$$XMMRegister, $src2$$Address);
9629     emit_cmpfp_fixup(_masm);
9630   %}
9631   ins_pipe( pipe_slow );
9632 %}
9633 
9634 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9635   predicate(UseSSE>=2);
9636   match(Set cr (CmpD src1 (LoadD src2)));
9637   ins_cost(100);
9638   format %{ "UCOMISD $src1,$src2" %}
9639   ins_encode %{
9640     __ ucomisd($src1$$XMMRegister, $src2$$Address);
9641   %}
9642   ins_pipe( pipe_slow );
9643 %}
9644 
9645 // Compare into -1,0,1 in XMM
9646 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9647   predicate(UseSSE>=2);
9648   match(Set dst (CmpD3 src1 src2));
9649   effect(KILL cr);
9650   ins_cost(255);
9651   format %{ "UCOMISD $src1, $src2\n\t"
9652             "MOV     $dst, #-1\n\t"
9653             "JP,s    done\n\t"
9654             "JB,s    done\n\t"
9655             "SETNE   $dst\n\t"
9656             "MOVZB   $dst, $dst\n"
9657     "done:" %}
9658   ins_encode %{
9659     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9660     emit_cmpfp3(_masm, $dst$$Register);
9661   %}
9662   ins_pipe( pipe_slow );
9663 %}
9664 
9665 // Compare into -1,0,1 in XMM and memory
9666 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9667   predicate(UseSSE>=2);
9668   match(Set dst (CmpD3 src1 (LoadD src2)));
9669   effect(KILL cr);
9670   ins_cost(275);
9671   format %{ "UCOMISD $src1, $src2\n\t"
9672             "MOV     $dst, #-1\n\t"
9673             "JP,s    done\n\t"
9674             "JB,s    done\n\t"
9675             "SETNE   $dst\n\t"
9676             "MOVZB   $dst, $dst\n"
9677     "done:" %}
9678   ins_encode %{
9679     __ ucomisd($src1$$XMMRegister, $src2$$Address);
9680     emit_cmpfp3(_masm, $dst$$Register);
9681   %}
9682   ins_pipe( pipe_slow );
9683 %}
9684 
9685 
9686 instruct subDPR_reg(regDPR dst, regDPR src) %{
9687   predicate (UseSSE <=1);
9688   match(Set dst (SubD dst src));
9689 
9690   format %{ "FLD    $src\n\t"
9691             "DSUBp  $dst,ST" %}
9692   opcode(0xDE, 0x5); /* DE E8+i  or DE /5 */
9693   ins_cost(150);
9694   ins_encode( Push_Reg_DPR(src),
9695               OpcP, RegOpc(dst) );
9696   ins_pipe( fpu_reg_reg );
9697 %}
9698 
9699 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9700   predicate (UseSSE <=1);
9701   match(Set dst (RoundDouble (SubD src1 src2)));
9702   ins_cost(250);
9703 
9704   format %{ "FLD    $src2\n\t"
9705             "DSUB   ST,$src1\n\t"
9706             "FSTP_D $dst\t# D-round" %}
9707   opcode(0xD8, 0x5);
9708   ins_encode( Push_Reg_DPR(src2),
9709               OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9710   ins_pipe( fpu_mem_reg_reg );
9711 %}
9712 
9713 
9714 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9715   predicate (UseSSE <=1);
9716   match(Set dst (SubD dst (LoadD src)));
9717   ins_cost(150);
9718 
9719   format %{ "FLD    $src\n\t"
9720             "DSUBp  $dst,ST" %}
9721   opcode(0xDE, 0x5, 0xDD); /* DE C0+i */  /* LoadD  DD /0 */
9722   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9723               OpcP, RegOpc(dst) );
9724   ins_pipe( fpu_reg_mem );
9725 %}
9726 
9727 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9728   predicate (UseSSE<=1);
9729   match(Set dst (AbsD src));
9730   ins_cost(100);
9731   format %{ "FABS" %}
9732   opcode(0xE1, 0xD9);
9733   ins_encode( OpcS, OpcP );
9734   ins_pipe( fpu_reg_reg );
9735 %}
9736 
9737 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9738   predicate(UseSSE<=1);
9739   match(Set dst (NegD src));
9740   ins_cost(100);
9741   format %{ "FCHS" %}
9742   opcode(0xE0, 0xD9);
9743   ins_encode( OpcS, OpcP );
9744   ins_pipe( fpu_reg_reg );
9745 %}
9746 
9747 instruct addDPR_reg(regDPR dst, regDPR src) %{
9748   predicate(UseSSE<=1);
9749   match(Set dst (AddD dst src));
9750   format %{ "FLD    $src\n\t"
9751             "DADD   $dst,ST" %}
9752   size(4);
9753   ins_cost(150);
9754   opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9755   ins_encode( Push_Reg_DPR(src),
9756               OpcP, RegOpc(dst) );
9757   ins_pipe( fpu_reg_reg );
9758 %}
9759 
9760 
9761 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9762   predicate(UseSSE<=1);
9763   match(Set dst (RoundDouble (AddD src1 src2)));
9764   ins_cost(250);
9765 
9766   format %{ "FLD    $src2\n\t"
9767             "DADD   ST,$src1\n\t"
9768             "FSTP_D $dst\t# D-round" %}
9769   opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9770   ins_encode( Push_Reg_DPR(src2),
9771               OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9772   ins_pipe( fpu_mem_reg_reg );
9773 %}
9774 
9775 
9776 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9777   predicate(UseSSE<=1);
9778   match(Set dst (AddD dst (LoadD src)));
9779   ins_cost(150);
9780 
9781   format %{ "FLD    $src\n\t"
9782             "DADDp  $dst,ST" %}
9783   opcode(0xDE, 0x0, 0xDD); /* DE C0+i */  /* LoadD  DD /0 */
9784   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9785               OpcP, RegOpc(dst) );
9786   ins_pipe( fpu_reg_mem );
9787 %}
9788 
9789 // add-to-memory
9790 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9791   predicate(UseSSE<=1);
9792   match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9793   ins_cost(150);
9794 
9795   format %{ "FLD_D  $dst\n\t"
9796             "DADD   ST,$src\n\t"
9797             "FST_D  $dst" %}
9798   opcode(0xDD, 0x0);
9799   ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9800               Opcode(0xD8), RegOpc(src),
9801               set_instruction_start,
9802               Opcode(0xDD), RMopc_Mem(0x03,dst) );
9803   ins_pipe( fpu_reg_mem );
9804 %}
9805 
9806 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9807   predicate(UseSSE<=1);
9808   match(Set dst (AddD dst con));
9809   ins_cost(125);
9810   format %{ "FLD1\n\t"
9811             "DADDp  $dst,ST" %}
9812   ins_encode %{
9813     __ fld1();
9814     __ faddp($dst$$reg);
9815   %}
9816   ins_pipe(fpu_reg);
9817 %}
9818 
9819 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9820   predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9821   match(Set dst (AddD dst con));
9822   ins_cost(200);
9823   format %{ "FLD_D  [$constantaddress]\t# load from constant table: double=$con\n\t"
9824             "DADDp  $dst,ST" %}
9825   ins_encode %{
9826     __ fld_d($constantaddress($con));
9827     __ faddp($dst$$reg);
9828   %}
9829   ins_pipe(fpu_reg_mem);
9830 %}
9831 
9832 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9833   predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9834   match(Set dst (RoundDouble (AddD src con)));
9835   ins_cost(200);
9836   format %{ "FLD_D  [$constantaddress]\t# load from constant table: double=$con\n\t"
9837             "DADD   ST,$src\n\t"
9838             "FSTP_D $dst\t# D-round" %}
9839   ins_encode %{
9840     __ fld_d($constantaddress($con));
9841     __ fadd($src$$reg);
9842     __ fstp_d(Address(rsp, $dst$$disp));
9843   %}
9844   ins_pipe(fpu_mem_reg_con);
9845 %}
9846 
9847 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9848   predicate(UseSSE<=1);
9849   match(Set dst (MulD dst src));
9850   format %{ "FLD    $src\n\t"
9851             "DMULp  $dst,ST" %}
9852   opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9853   ins_cost(150);
9854   ins_encode( Push_Reg_DPR(src),
9855               OpcP, RegOpc(dst) );
9856   ins_pipe( fpu_reg_reg );
9857 %}
9858 
9859 // Strict FP instruction biases argument before multiply then
9860 // biases result to avoid double rounding of subnormals.
9861 //
9862 // scale arg1 by multiplying arg1 by 2^(-15360)
9863 // load arg2
9864 // multiply scaled arg1 by arg2
9865 // rescale product by 2^(15360)
9866 //
9867 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9868   predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9869   match(Set dst (MulD dst src));
9870   ins_cost(1);   // Select this instruction for all strict FP double multiplies
9871 
9872   format %{ "FLD    StubRoutines::_fpu_subnormal_bias1\n\t"
9873             "DMULp  $dst,ST\n\t"
9874             "FLD    $src\n\t"
9875             "DMULp  $dst,ST\n\t"
9876             "FLD    StubRoutines::_fpu_subnormal_bias2\n\t"
9877             "DMULp  $dst,ST\n\t" %}
9878   opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9879   ins_encode( strictfp_bias1(dst),
9880               Push_Reg_DPR(src),
9881               OpcP, RegOpc(dst),
9882               strictfp_bias2(dst) );
9883   ins_pipe( fpu_reg_reg );
9884 %}
9885 
9886 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9887   predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9888   match(Set dst (MulD dst con));
9889   ins_cost(200);
9890   format %{ "FLD_D  [$constantaddress]\t# load from constant table: double=$con\n\t"
9891             "DMULp  $dst,ST" %}
9892   ins_encode %{
9893     __ fld_d($constantaddress($con));
9894     __ fmulp($dst$$reg);
9895   %}
9896   ins_pipe(fpu_reg_mem);
9897 %}
9898 
9899 
9900 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9901   predicate( UseSSE<=1 );
9902   match(Set dst (MulD dst (LoadD src)));
9903   ins_cost(200);
9904   format %{ "FLD_D  $src\n\t"
9905             "DMULp  $dst,ST" %}
9906   opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/  /* LoadD  DD /0 */
9907   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9908               OpcP, RegOpc(dst) );
9909   ins_pipe( fpu_reg_mem );
9910 %}
9911 
9912 //
9913 // Cisc-alternate to reg-reg multiply
9914 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9915   predicate( UseSSE<=1 );
9916   match(Set dst (MulD src (LoadD mem)));
9917   ins_cost(250);
9918   format %{ "FLD_D  $mem\n\t"
9919             "DMUL   ST,$src\n\t"
9920             "FSTP_D $dst" %}
9921   opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */  /* LoadD D9 /0 */
9922   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9923               OpcReg_FPR(src),
9924               Pop_Reg_DPR(dst) );
9925   ins_pipe( fpu_reg_reg_mem );
9926 %}
9927 
9928 
9929 // MACRO3 -- addDPR a mulDPR
9930 // This instruction is a '2-address' instruction in that the result goes
9931 // back to src2.  This eliminates a move from the macro; possibly the
9932 // register allocator will have to add it back (and maybe not).
9933 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9934   predicate( UseSSE<=1 );
9935   match(Set src2 (AddD (MulD src0 src1) src2));
9936   format %{ "FLD    $src0\t# ===MACRO3d===\n\t"
9937             "DMUL   ST,$src1\n\t"
9938             "DADDp  $src2,ST" %}
9939   ins_cost(250);
9940   opcode(0xDD); /* LoadD DD /0 */
9941   ins_encode( Push_Reg_FPR(src0),
9942               FMul_ST_reg(src1),
9943               FAddP_reg_ST(src2) );
9944   ins_pipe( fpu_reg_reg_reg );
9945 %}
9946 
9947 
9948 // MACRO3 -- subDPR a mulDPR
9949 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9950   predicate( UseSSE<=1 );
9951   match(Set src2 (SubD (MulD src0 src1) src2));
9952   format %{ "FLD    $src0\t# ===MACRO3d===\n\t"
9953             "DMUL   ST,$src1\n\t"
9954             "DSUBRp $src2,ST" %}
9955   ins_cost(250);
9956   ins_encode( Push_Reg_FPR(src0),
9957               FMul_ST_reg(src1),
9958               Opcode(0xDE), Opc_plus(0xE0,src2));
9959   ins_pipe( fpu_reg_reg_reg );
9960 %}
9961 
9962 
9963 instruct divDPR_reg(regDPR dst, regDPR src) %{
9964   predicate( UseSSE<=1 );
9965   match(Set dst (DivD dst src));
9966 
9967   format %{ "FLD    $src\n\t"
9968             "FDIVp  $dst,ST" %}
9969   opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9970   ins_cost(150);
9971   ins_encode( Push_Reg_DPR(src),
9972               OpcP, RegOpc(dst) );
9973   ins_pipe( fpu_reg_reg );
9974 %}
9975 
9976 // Strict FP instruction biases argument before division then
9977 // biases result, to avoid double rounding of subnormals.
9978 //
9979 // scale dividend by multiplying dividend by 2^(-15360)
9980 // load divisor
9981 // divide scaled dividend by divisor
9982 // rescale quotient by 2^(15360)
9983 //
9984 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9985   predicate (UseSSE<=1);
9986   match(Set dst (DivD dst src));
9987   predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9988   ins_cost(01);
9989 
9990   format %{ "FLD    StubRoutines::_fpu_subnormal_bias1\n\t"
9991             "DMULp  $dst,ST\n\t"
9992             "FLD    $src\n\t"
9993             "FDIVp  $dst,ST\n\t"
9994             "FLD    StubRoutines::_fpu_subnormal_bias2\n\t"
9995             "DMULp  $dst,ST\n\t" %}
9996   opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9997   ins_encode( strictfp_bias1(dst),
9998               Push_Reg_DPR(src),
9999               OpcP, RegOpc(dst),
10000               strictfp_bias2(dst) );
10001   ins_pipe( fpu_reg_reg );
10002 %}
10003 
10004 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
10005   predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10006   match(Set dst (RoundDouble (DivD src1 src2)));
10007 
10008   format %{ "FLD    $src1\n\t"
10009             "FDIV   ST,$src2\n\t"
10010             "FSTP_D $dst\t# D-round" %}
10011   opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10012   ins_encode( Push_Reg_DPR(src1),
10013               OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
10014   ins_pipe( fpu_mem_reg_reg );
10015 %}
10016 
10017 
10018 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
10019   predicate(UseSSE<=1);
10020   match(Set dst (ModD dst src));
10021   effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10022 
10023   format %{ "DMOD   $dst,$src" %}
10024   ins_cost(250);
10025   ins_encode(Push_Reg_Mod_DPR(dst, src),
10026               emitModDPR(),
10027               Push_Result_Mod_DPR(src),
10028               Pop_Reg_DPR(dst));
10029   ins_pipe( pipe_slow );
10030 %}
10031 
10032 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
10033   predicate(UseSSE>=2);
10034   match(Set dst (ModD src0 src1));
10035   effect(KILL rax, KILL cr);
10036 
10037   format %{ "SUB    ESP,8\t # DMOD\n"
10038           "\tMOVSD  [ESP+0],$src1\n"
10039           "\tFLD_D  [ESP+0]\n"
10040           "\tMOVSD  [ESP+0],$src0\n"
10041           "\tFLD_D  [ESP+0]\n"
10042      "loop:\tFPREM\n"
10043           "\tFWAIT\n"
10044           "\tFNSTSW AX\n"
10045           "\tSAHF\n"
10046           "\tJP     loop\n"
10047           "\tFSTP_D [ESP+0]\n"
10048           "\tMOVSD  $dst,[ESP+0]\n"
10049           "\tADD    ESP,8\n"
10050           "\tFSTP   ST0\t # Restore FPU Stack"
10051     %}
10052   ins_cost(250);
10053   ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
10054   ins_pipe( pipe_slow );
10055 %}
10056 
10057 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
10058   predicate (UseSSE<=1);
10059   match(Set dst (SinD src));
10060   ins_cost(1800);
10061   format %{ "DSIN   $dst" %}
10062   opcode(0xD9, 0xFE);
10063   ins_encode( OpcP, OpcS );
10064   ins_pipe( pipe_slow );
10065 %}
10066 
10067 instruct sinD_reg(regD dst, eFlagsReg cr) %{
10068   predicate (UseSSE>=2);
10069   match(Set dst (SinD dst));
10070   effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10071   ins_cost(1800);
10072   format %{ "DSIN   $dst" %}
10073   opcode(0xD9, 0xFE);
10074   ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10075   ins_pipe( pipe_slow );
10076 %}
10077 
10078 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
10079   predicate (UseSSE<=1);
10080   match(Set dst (CosD src));
10081   ins_cost(1800);
10082   format %{ "DCOS   $dst" %}
10083   opcode(0xD9, 0xFF);
10084   ins_encode( OpcP, OpcS );
10085   ins_pipe( pipe_slow );
10086 %}
10087 
10088 instruct cosD_reg(regD dst, eFlagsReg cr) %{
10089   predicate (UseSSE>=2);
10090   match(Set dst (CosD dst));
10091   effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10092   ins_cost(1800);
10093   format %{ "DCOS   $dst" %}
10094   opcode(0xD9, 0xFF);
10095   ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10096   ins_pipe( pipe_slow );
10097 %}
10098 
10099 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
10100   predicate (UseSSE<=1);
10101   match(Set dst(TanD src));
10102   format %{ "DTAN   $dst" %}
10103   ins_encode( Opcode(0xD9), Opcode(0xF2),    // fptan
10104               Opcode(0xDD), Opcode(0xD8));   // fstp st
10105   ins_pipe( pipe_slow );
10106 %}
10107 
10108 instruct tanD_reg(regD dst, eFlagsReg cr) %{
10109   predicate (UseSSE>=2);
10110   match(Set dst(TanD dst));
10111   effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10112   format %{ "DTAN   $dst" %}
10113   ins_encode( Push_SrcD(dst),
10114               Opcode(0xD9), Opcode(0xF2),    // fptan
10115               Opcode(0xDD), Opcode(0xD8),   // fstp st
10116               Push_ResultD(dst) );
10117   ins_pipe( pipe_slow );
10118 %}
10119 
10120 instruct atanDPR_reg(regDPR dst, regDPR src) %{
10121   predicate (UseSSE<=1);
10122   match(Set dst(AtanD dst src));
10123   format %{ "DATA   $dst,$src" %}
10124   opcode(0xD9, 0xF3);
10125   ins_encode( Push_Reg_DPR(src),
10126               OpcP, OpcS, RegOpc(dst) );
10127   ins_pipe( pipe_slow );
10128 %}
10129 
10130 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
10131   predicate (UseSSE>=2);
10132   match(Set dst(AtanD dst src));
10133   effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10134   format %{ "DATA   $dst,$src" %}
10135   opcode(0xD9, 0xF3);
10136   ins_encode( Push_SrcD(src),
10137               OpcP, OpcS, Push_ResultD(dst) );
10138   ins_pipe( pipe_slow );
10139 %}
10140 
10141 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
10142   predicate (UseSSE<=1);
10143   match(Set dst (SqrtD src));
10144   format %{ "DSQRT  $dst,$src" %}
10145   opcode(0xFA, 0xD9);
10146   ins_encode( Push_Reg_DPR(src),
10147               OpcS, OpcP, Pop_Reg_DPR(dst) );
10148   ins_pipe( pipe_slow );
10149 %}
10150 
10151 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10152   predicate (UseSSE<=1);
10153   match(Set Y (PowD X Y));  // Raise X to the Yth power
10154   effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10155   format %{ "fast_pow $X $Y -> $Y  // KILL $rax, $rcx, $rdx" %}
10156   ins_encode %{
10157     __ subptr(rsp, 8);
10158     __ fld_s($X$$reg - 1);
10159     __ fast_pow();
10160     __ addptr(rsp, 8);
10161   %}
10162   ins_pipe( pipe_slow );
10163 %}
10164 
10165 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10166   predicate (UseSSE>=2);
10167   match(Set dst (PowD src0 src1));  // Raise src0 to the src1'th power
10168   effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10169   format %{ "fast_pow $src0 $src1 -> $dst  // KILL $rax, $rcx, $rdx" %}
10170   ins_encode %{
10171     __ subptr(rsp, 8);
10172     __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
10173     __ fld_d(Address(rsp, 0));
10174     __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10175     __ fld_d(Address(rsp, 0));
10176     __ fast_pow();
10177     __ fstp_d(Address(rsp, 0));
10178     __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10179     __ addptr(rsp, 8);
10180   %}
10181   ins_pipe( pipe_slow );
10182 %}
10183 
10184 
10185 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10186   predicate (UseSSE<=1);
10187   match(Set dpr1 (ExpD dpr1));
10188   effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10189   format %{ "fast_exp $dpr1 -> $dpr1  // KILL $rax, $rcx, $rdx" %}
10190   ins_encode %{
10191     __ fast_exp();
10192   %}
10193   ins_pipe( pipe_slow );
10194 %}
10195 
10196 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10197   predicate (UseSSE>=2);
10198   match(Set dst (ExpD src));
10199   effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10200   format %{ "fast_exp $dst -> $src  // KILL $rax, $rcx, $rdx" %}
10201   ins_encode %{
10202     __ subptr(rsp, 8);
10203     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10204     __ fld_d(Address(rsp, 0));
10205     __ fast_exp();
10206     __ fstp_d(Address(rsp, 0));
10207     __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10208     __ addptr(rsp, 8);
10209   %}
10210   ins_pipe( pipe_slow );
10211 %}
10212 
10213 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10214   predicate (UseSSE<=1);
10215   // The source Double operand on FPU stack
10216   match(Set dst (Log10D src));
10217   // fldlg2       ; push log_10(2) on the FPU stack; full 80-bit number
10218   // fxch         ; swap ST(0) with ST(1)
10219   // fyl2x        ; compute log_10(2) * log_2(x)
10220   format %{ "FLDLG2 \t\t\t#Log10\n\t"
10221             "FXCH   \n\t"
10222             "FYL2X  \t\t\t# Q=Log10*Log_2(x)"
10223          %}
10224   ins_encode( Opcode(0xD9), Opcode(0xEC),   // fldlg2
10225               Opcode(0xD9), Opcode(0xC9),   // fxch
10226               Opcode(0xD9), Opcode(0xF1));  // fyl2x
10227 
10228   ins_pipe( pipe_slow );
10229 %}
10230 
10231 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10232   predicate (UseSSE>=2);
10233   effect(KILL cr);
10234   match(Set dst (Log10D src));
10235   // fldlg2       ; push log_10(2) on the FPU stack; full 80-bit number
10236   // fyl2x        ; compute log_10(2) * log_2(x)
10237   format %{ "FLDLG2 \t\t\t#Log10\n\t"
10238             "FYL2X  \t\t\t# Q=Log10*Log_2(x)"
10239          %}
10240   ins_encode( Opcode(0xD9), Opcode(0xEC),   // fldlg2
10241               Push_SrcD(src),
10242               Opcode(0xD9), Opcode(0xF1),   // fyl2x
10243               Push_ResultD(dst));
10244 
10245   ins_pipe( pipe_slow );
10246 %}
10247 
10248 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10249   predicate (UseSSE<=1);
10250   // The source Double operand on FPU stack
10251   match(Set dst (LogD src));
10252   // fldln2       ; push log_e(2) on the FPU stack; full 80-bit number
10253   // fxch         ; swap ST(0) with ST(1)
10254   // fyl2x        ; compute log_e(2) * log_2(x)
10255   format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10256             "FXCH   \n\t"
10257             "FYL2X  \t\t\t# Q=Log_e*Log_2(x)"
10258          %}
10259   ins_encode( Opcode(0xD9), Opcode(0xED),   // fldln2
10260               Opcode(0xD9), Opcode(0xC9),   // fxch
10261               Opcode(0xD9), Opcode(0xF1));  // fyl2x
10262 
10263   ins_pipe( pipe_slow );
10264 %}
10265 
10266 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10267   predicate (UseSSE>=2);
10268   effect(KILL cr);
10269   // The source and result Double operands in XMM registers
10270   match(Set dst (LogD src));
10271   // fldln2       ; push log_e(2) on the FPU stack; full 80-bit number
10272   // fyl2x        ; compute log_e(2) * log_2(x)
10273   format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10274             "FYL2X  \t\t\t# Q=Log_e*Log_2(x)"
10275          %}
10276   ins_encode( Opcode(0xD9), Opcode(0xED),   // fldln2
10277               Push_SrcD(src),
10278               Opcode(0xD9), Opcode(0xF1),   // fyl2x
10279               Push_ResultD(dst));
10280   ins_pipe( pipe_slow );
10281 %}
10282 
10283 //-------------Float Instructions-------------------------------
10284 // Float Math
10285 
10286 // Code for float compare:
10287 //     fcompp();
10288 //     fwait(); fnstsw_ax();
10289 //     sahf();
10290 //     movl(dst, unordered_result);
10291 //     jcc(Assembler::parity, exit);
10292 //     movl(dst, less_result);
10293 //     jcc(Assembler::below, exit);
10294 //     movl(dst, equal_result);
10295 //     jcc(Assembler::equal, exit);
10296 //     movl(dst, greater_result);
10297 //   exit:
10298 
10299 // P6 version of float compare, sets condition codes in EFLAGS
10300 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10301   predicate(VM_Version::supports_cmov() && UseSSE == 0);
10302   match(Set cr (CmpF src1 src2));
10303   effect(KILL rax);
10304   ins_cost(150);
10305   format %{ "FLD    $src1\n\t"
10306             "FUCOMIP ST,$src2  // P6 instruction\n\t"
10307             "JNP    exit\n\t"
10308             "MOV    ah,1       // saw a NaN, set CF (treat as LT)\n\t"
10309             "SAHF\n"
10310      "exit:\tNOP               // avoid branch to branch" %}
10311   opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10312   ins_encode( Push_Reg_DPR(src1),
10313               OpcP, RegOpc(src2),
10314               cmpF_P6_fixup );
10315   ins_pipe( pipe_slow );
10316 %}
10317 
10318 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10319   predicate(VM_Version::supports_cmov() && UseSSE == 0);
10320   match(Set cr (CmpF src1 src2));
10321   ins_cost(100);
10322   format %{ "FLD    $src1\n\t"
10323             "FUCOMIP ST,$src2  // P6 instruction" %}
10324   opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10325   ins_encode( Push_Reg_DPR(src1),
10326               OpcP, RegOpc(src2));
10327   ins_pipe( pipe_slow );
10328 %}
10329 
10330 
10331 // Compare & branch
10332 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10333   predicate(UseSSE == 0);
10334   match(Set cr (CmpF src1 src2));
10335   effect(KILL rax);
10336   ins_cost(200);
10337   format %{ "FLD    $src1\n\t"
10338             "FCOMp  $src2\n\t"
10339             "FNSTSW AX\n\t"
10340             "TEST   AX,0x400\n\t"
10341             "JZ,s   flags\n\t"
10342             "MOV    AH,1\t# unordered treat as LT\n"
10343     "flags:\tSAHF" %}
10344   opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10345   ins_encode( Push_Reg_DPR(src1),
10346               OpcP, RegOpc(src2),
10347               fpu_flags);
10348   ins_pipe( pipe_slow );
10349 %}
10350 
10351 // Compare vs zero into -1,0,1
10352 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10353   predicate(UseSSE == 0);
10354   match(Set dst (CmpF3 src1 zero));
10355   effect(KILL cr, KILL rax);
10356   ins_cost(280);
10357   format %{ "FTSTF  $dst,$src1" %}
10358   opcode(0xE4, 0xD9);
10359   ins_encode( Push_Reg_DPR(src1),
10360               OpcS, OpcP, PopFPU,
10361               CmpF_Result(dst));
10362   ins_pipe( pipe_slow );
10363 %}
10364 
10365 // Compare into -1,0,1
10366 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10367   predicate(UseSSE == 0);
10368   match(Set dst (CmpF3 src1 src2));
10369   effect(KILL cr, KILL rax);
10370   ins_cost(300);
10371   format %{ "FCMPF  $dst,$src1,$src2" %}
10372   opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10373   ins_encode( Push_Reg_DPR(src1),
10374               OpcP, RegOpc(src2),
10375               CmpF_Result(dst));
10376   ins_pipe( pipe_slow );
10377 %}
10378 
10379 // float compare and set condition codes in EFLAGS by XMM regs
10380 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10381   predicate(UseSSE>=1);
10382   match(Set cr (CmpF src1 src2));
10383   ins_cost(145);
10384   format %{ "UCOMISS $src1,$src2\n\t"
10385             "JNP,s   exit\n\t"
10386             "PUSHF\t# saw NaN, set CF\n\t"
10387             "AND     [rsp], #0xffffff2b\n\t"
10388             "POPF\n"
10389     "exit:" %}
10390   ins_encode %{
10391     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10392     emit_cmpfp_fixup(_masm);
10393   %}
10394   ins_pipe( pipe_slow );
10395 %}
10396 
10397 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10398   predicate(UseSSE>=1);
10399   match(Set cr (CmpF src1 src2));
10400   ins_cost(100);
10401   format %{ "UCOMISS $src1,$src2" %}
10402   ins_encode %{
10403     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10404   %}
10405   ins_pipe( pipe_slow );
10406 %}
10407 
10408 // float compare and set condition codes in EFLAGS by XMM regs
10409 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10410   predicate(UseSSE>=1);
10411   match(Set cr (CmpF src1 (LoadF src2)));
10412   ins_cost(165);
10413   format %{ "UCOMISS $src1,$src2\n\t"
10414             "JNP,s   exit\n\t"
10415             "PUSHF\t# saw NaN, set CF\n\t"
10416             "AND     [rsp], #0xffffff2b\n\t"
10417             "POPF\n"
10418     "exit:" %}
10419   ins_encode %{
10420     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10421     emit_cmpfp_fixup(_masm);
10422   %}
10423   ins_pipe( pipe_slow );
10424 %}
10425 
10426 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10427   predicate(UseSSE>=1);
10428   match(Set cr (CmpF src1 (LoadF src2)));
10429   ins_cost(100);
10430   format %{ "UCOMISS $src1,$src2" %}
10431   ins_encode %{
10432     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10433   %}
10434   ins_pipe( pipe_slow );
10435 %}
10436 
10437 // Compare into -1,0,1 in XMM
10438 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10439   predicate(UseSSE>=1);
10440   match(Set dst (CmpF3 src1 src2));
10441   effect(KILL cr);
10442   ins_cost(255);
10443   format %{ "UCOMISS $src1, $src2\n\t"
10444             "MOV     $dst, #-1\n\t"
10445             "JP,s    done\n\t"
10446             "JB,s    done\n\t"
10447             "SETNE   $dst\n\t"
10448             "MOVZB   $dst, $dst\n"
10449     "done:" %}
10450   ins_encode %{
10451     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10452     emit_cmpfp3(_masm, $dst$$Register);
10453   %}
10454   ins_pipe( pipe_slow );
10455 %}
10456 
10457 // Compare into -1,0,1 in XMM and memory
10458 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10459   predicate(UseSSE>=1);
10460   match(Set dst (CmpF3 src1 (LoadF src2)));
10461   effect(KILL cr);
10462   ins_cost(275);
10463   format %{ "UCOMISS $src1, $src2\n\t"
10464             "MOV     $dst, #-1\n\t"
10465             "JP,s    done\n\t"
10466             "JB,s    done\n\t"
10467             "SETNE   $dst\n\t"
10468             "MOVZB   $dst, $dst\n"
10469     "done:" %}
10470   ins_encode %{
10471     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10472     emit_cmpfp3(_masm, $dst$$Register);
10473   %}
10474   ins_pipe( pipe_slow );
10475 %}
10476 
10477 // Spill to obtain 24-bit precision
10478 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10479   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10480   match(Set dst (SubF src1 src2));
10481 
10482   format %{ "FSUB   $dst,$src1 - $src2" %}
10483   opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10484   ins_encode( Push_Reg_FPR(src1),
10485               OpcReg_FPR(src2),
10486               Pop_Mem_FPR(dst) );
10487   ins_pipe( fpu_mem_reg_reg );
10488 %}
10489 //
10490 // This instruction does not round to 24-bits
10491 instruct subFPR_reg(regFPR dst, regFPR src) %{
10492   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10493   match(Set dst (SubF dst src));
10494 
10495   format %{ "FSUB   $dst,$src" %}
10496   opcode(0xDE, 0x5); /* DE E8+i  or DE /5 */
10497   ins_encode( Push_Reg_FPR(src),
10498               OpcP, RegOpc(dst) );
10499   ins_pipe( fpu_reg_reg );
10500 %}
10501 
10502 // Spill to obtain 24-bit precision
10503 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10504   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10505   match(Set dst (AddF src1 src2));
10506 
10507   format %{ "FADD   $dst,$src1,$src2" %}
10508   opcode(0xD8, 0x0); /* D8 C0+i */
10509   ins_encode( Push_Reg_FPR(src2),
10510               OpcReg_FPR(src1),
10511               Pop_Mem_FPR(dst) );
10512   ins_pipe( fpu_mem_reg_reg );
10513 %}
10514 //
10515 // This instruction does not round to 24-bits
10516 instruct addFPR_reg(regFPR dst, regFPR src) %{
10517   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10518   match(Set dst (AddF dst src));
10519 
10520   format %{ "FLD    $src\n\t"
10521             "FADDp  $dst,ST" %}
10522   opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10523   ins_encode( Push_Reg_FPR(src),
10524               OpcP, RegOpc(dst) );
10525   ins_pipe( fpu_reg_reg );
10526 %}
10527 
10528 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10529   predicate(UseSSE==0);
10530   match(Set dst (AbsF src));
10531   ins_cost(100);
10532   format %{ "FABS" %}
10533   opcode(0xE1, 0xD9);
10534   ins_encode( OpcS, OpcP );
10535   ins_pipe( fpu_reg_reg );
10536 %}
10537 
10538 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10539   predicate(UseSSE==0);
10540   match(Set dst (NegF src));
10541   ins_cost(100);
10542   format %{ "FCHS" %}
10543   opcode(0xE0, 0xD9);
10544   ins_encode( OpcS, OpcP );
10545   ins_pipe( fpu_reg_reg );
10546 %}
10547 
10548 // Cisc-alternate to addFPR_reg
10549 // Spill to obtain 24-bit precision
10550 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10551   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10552   match(Set dst (AddF src1 (LoadF src2)));
10553 
10554   format %{ "FLD    $src2\n\t"
10555             "FADD   ST,$src1\n\t"
10556             "FSTP_S $dst" %}
10557   opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */  /* LoadF  D9 /0 */
10558   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10559               OpcReg_FPR(src1),
10560               Pop_Mem_FPR(dst) );
10561   ins_pipe( fpu_mem_reg_mem );
10562 %}
10563 //
10564 // Cisc-alternate to addFPR_reg
10565 // This instruction does not round to 24-bits
10566 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10567   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10568   match(Set dst (AddF dst (LoadF src)));
10569 
10570   format %{ "FADD   $dst,$src" %}
10571   opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/  /* LoadF  D9 /0 */
10572   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10573               OpcP, RegOpc(dst) );
10574   ins_pipe( fpu_reg_mem );
10575 %}
10576 
10577 // // Following two instructions for _222_mpegaudio
10578 // Spill to obtain 24-bit precision
10579 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10580   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10581   match(Set dst (AddF src1 src2));
10582 
10583   format %{ "FADD   $dst,$src1,$src2" %}
10584   opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */  /* LoadF  D9 /0 */
10585   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10586               OpcReg_FPR(src2),
10587               Pop_Mem_FPR(dst) );
10588   ins_pipe( fpu_mem_reg_mem );
10589 %}
10590 
10591 // Cisc-spill variant
10592 // Spill to obtain 24-bit precision
10593 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10594   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10595   match(Set dst (AddF src1 (LoadF src2)));
10596 
10597   format %{ "FADD   $dst,$src1,$src2 cisc" %}
10598   opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */  /* LoadF  D9 /0 */
10599   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10600               set_instruction_start,
10601               OpcP, RMopc_Mem(secondary,src1),
10602               Pop_Mem_FPR(dst) );
10603   ins_pipe( fpu_mem_mem_mem );
10604 %}
10605 
10606 // Spill to obtain 24-bit precision
10607 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10608   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10609   match(Set dst (AddF src1 src2));
10610 
10611   format %{ "FADD   $dst,$src1,$src2" %}
10612   opcode(0xD8, 0x0, 0xD9); /* D8 /0 */  /* LoadF  D9 /0 */
10613   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10614               set_instruction_start,
10615               OpcP, RMopc_Mem(secondary,src1),
10616               Pop_Mem_FPR(dst) );
10617   ins_pipe( fpu_mem_mem_mem );
10618 %}
10619 
10620 
10621 // Spill to obtain 24-bit precision
10622 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10623   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10624   match(Set dst (AddF src con));
10625   format %{ "FLD    $src\n\t"
10626             "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10627             "FSTP_S $dst"  %}
10628   ins_encode %{
10629     __ fld_s($src$$reg - 1);  // FLD ST(i-1)
10630     __ fadd_s($constantaddress($con));
10631     __ fstp_s(Address(rsp, $dst$$disp));
10632   %}
10633   ins_pipe(fpu_mem_reg_con);
10634 %}
10635 //
10636 // This instruction does not round to 24-bits
10637 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10638   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10639   match(Set dst (AddF src con));
10640   format %{ "FLD    $src\n\t"
10641             "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10642             "FSTP   $dst"  %}
10643   ins_encode %{
10644     __ fld_s($src$$reg - 1);  // FLD ST(i-1)
10645     __ fadd_s($constantaddress($con));
10646     __ fstp_d($dst$$reg);
10647   %}
10648   ins_pipe(fpu_reg_reg_con);
10649 %}
10650 
10651 // Spill to obtain 24-bit precision
10652 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10653   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10654   match(Set dst (MulF src1 src2));
10655 
10656   format %{ "FLD    $src1\n\t"
10657             "FMUL   $src2\n\t"
10658             "FSTP_S $dst"  %}
10659   opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10660   ins_encode( Push_Reg_FPR(src1),
10661               OpcReg_FPR(src2),
10662               Pop_Mem_FPR(dst) );
10663   ins_pipe( fpu_mem_reg_reg );
10664 %}
10665 //
10666 // This instruction does not round to 24-bits
10667 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10668   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10669   match(Set dst (MulF src1 src2));
10670 
10671   format %{ "FLD    $src1\n\t"
10672             "FMUL   $src2\n\t"
10673             "FSTP_S $dst"  %}
10674   opcode(0xD8, 0x1); /* D8 C8+i */
10675   ins_encode( Push_Reg_FPR(src2),
10676               OpcReg_FPR(src1),
10677               Pop_Reg_FPR(dst) );
10678   ins_pipe( fpu_reg_reg_reg );
10679 %}
10680 
10681 
10682 // Spill to obtain 24-bit precision
10683 // Cisc-alternate to reg-reg multiply
10684 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10685   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10686   match(Set dst (MulF src1 (LoadF src2)));
10687 
10688   format %{ "FLD_S  $src2\n\t"
10689             "FMUL   $src1\n\t"
10690             "FSTP_S $dst"  %}
10691   opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/  /* LoadF D9 /0 */
10692   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10693               OpcReg_FPR(src1),
10694               Pop_Mem_FPR(dst) );
10695   ins_pipe( fpu_mem_reg_mem );
10696 %}
10697 //
10698 // This instruction does not round to 24-bits
10699 // Cisc-alternate to reg-reg multiply
10700 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10701   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10702   match(Set dst (MulF src1 (LoadF src2)));
10703 
10704   format %{ "FMUL   $dst,$src1,$src2" %}
10705   opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */  /* LoadF D9 /0 */
10706   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10707               OpcReg_FPR(src1),
10708               Pop_Reg_FPR(dst) );
10709   ins_pipe( fpu_reg_reg_mem );
10710 %}
10711 
10712 // Spill to obtain 24-bit precision
10713 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10714   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10715   match(Set dst (MulF src1 src2));
10716 
10717   format %{ "FMUL   $dst,$src1,$src2" %}
10718   opcode(0xD8, 0x1, 0xD9); /* D8 /1 */  /* LoadF D9 /0 */
10719   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10720               set_instruction_start,
10721               OpcP, RMopc_Mem(secondary,src1),
10722               Pop_Mem_FPR(dst) );
10723   ins_pipe( fpu_mem_mem_mem );
10724 %}
10725 
10726 // Spill to obtain 24-bit precision
10727 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10728   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10729   match(Set dst (MulF src con));
10730 
10731   format %{ "FLD    $src\n\t"
10732             "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10733             "FSTP_S $dst"  %}
10734   ins_encode %{
10735     __ fld_s($src$$reg - 1);  // FLD ST(i-1)
10736     __ fmul_s($constantaddress($con));
10737     __ fstp_s(Address(rsp, $dst$$disp));
10738   %}
10739   ins_pipe(fpu_mem_reg_con);
10740 %}
10741 //
10742 // This instruction does not round to 24-bits
10743 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10744   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10745   match(Set dst (MulF src con));
10746 
10747   format %{ "FLD    $src\n\t"
10748             "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10749             "FSTP   $dst"  %}
10750   ins_encode %{
10751     __ fld_s($src$$reg - 1);  // FLD ST(i-1)
10752     __ fmul_s($constantaddress($con));
10753     __ fstp_d($dst$$reg);
10754   %}
10755   ins_pipe(fpu_reg_reg_con);
10756 %}
10757 
10758 
10759 //
10760 // MACRO1 -- subsume unshared load into mulFPR
10761 // This instruction does not round to 24-bits
10762 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10763   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10764   match(Set dst (MulF (LoadF mem1) src));
10765 
10766   format %{ "FLD    $mem1    ===MACRO1===\n\t"
10767             "FMUL   ST,$src\n\t"
10768             "FSTP   $dst" %}
10769   opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */  /* LoadF D9 /0 */
10770   ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10771               OpcReg_FPR(src),
10772               Pop_Reg_FPR(dst) );
10773   ins_pipe( fpu_reg_reg_mem );
10774 %}
10775 //
10776 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10777 // This instruction does not round to 24-bits
10778 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10779   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10780   match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10781   ins_cost(95);
10782 
10783   format %{ "FLD    $mem1     ===MACRO2===\n\t"
10784             "FMUL   ST,$src1  subsume mulFPR left load\n\t"
10785             "FADD   ST,$src2\n\t"
10786             "FSTP   $dst" %}
10787   opcode(0xD9); /* LoadF D9 /0 */
10788   ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10789               FMul_ST_reg(src1),
10790               FAdd_ST_reg(src2),
10791               Pop_Reg_FPR(dst) );
10792   ins_pipe( fpu_reg_mem_reg_reg );
10793 %}
10794 
10795 // MACRO3 -- addFPR a mulFPR
10796 // This instruction does not round to 24-bits.  It is a '2-address'
10797 // instruction in that the result goes back to src2.  This eliminates
10798 // a move from the macro; possibly the register allocator will have
10799 // to add it back (and maybe not).
10800 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10801   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10802   match(Set src2 (AddF (MulF src0 src1) src2));
10803 
10804   format %{ "FLD    $src0     ===MACRO3===\n\t"
10805             "FMUL   ST,$src1\n\t"
10806             "FADDP  $src2,ST" %}
10807   opcode(0xD9); /* LoadF D9 /0 */
10808   ins_encode( Push_Reg_FPR(src0),
10809               FMul_ST_reg(src1),
10810               FAddP_reg_ST(src2) );
10811   ins_pipe( fpu_reg_reg_reg );
10812 %}
10813 
10814 // MACRO4 -- divFPR subFPR
10815 // This instruction does not round to 24-bits
10816 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10817   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10818   match(Set dst (DivF (SubF src2 src1) src3));
10819 
10820   format %{ "FLD    $src2   ===MACRO4===\n\t"
10821             "FSUB   ST,$src1\n\t"
10822             "FDIV   ST,$src3\n\t"
10823             "FSTP  $dst" %}
10824   opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10825   ins_encode( Push_Reg_FPR(src2),
10826               subFPR_divFPR_encode(src1,src3),
10827               Pop_Reg_FPR(dst) );
10828   ins_pipe( fpu_reg_reg_reg_reg );
10829 %}
10830 
10831 // Spill to obtain 24-bit precision
10832 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10833   predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10834   match(Set dst (DivF src1 src2));
10835 
10836   format %{ "FDIV   $dst,$src1,$src2" %}
10837   opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10838   ins_encode( Push_Reg_FPR(src1),
10839               OpcReg_FPR(src2),
10840               Pop_Mem_FPR(dst) );
10841   ins_pipe( fpu_mem_reg_reg );
10842 %}
10843 //
10844 // This instruction does not round to 24-bits
10845 instruct divFPR_reg(regFPR dst, regFPR src) %{
10846   predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10847   match(Set dst (DivF dst src));
10848 
10849   format %{ "FDIV   $dst,$src" %}
10850   opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10851   ins_encode( Push_Reg_FPR(src),
10852               OpcP, RegOpc(dst) );
10853   ins_pipe( fpu_reg_reg );
10854 %}
10855 
10856 
10857 // Spill to obtain 24-bit precision
10858 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10859   predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10860   match(Set dst (ModF src1 src2));
10861   effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10862 
10863   format %{ "FMOD   $dst,$src1,$src2" %}
10864   ins_encode( Push_Reg_Mod_DPR(src1, src2),
10865               emitModDPR(),
10866               Push_Result_Mod_DPR(src2),
10867               Pop_Mem_FPR(dst));
10868   ins_pipe( pipe_slow );
10869 %}
10870 //
10871 // This instruction does not round to 24-bits
10872 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10873   predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10874   match(Set dst (ModF dst src));
10875   effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10876 
10877   format %{ "FMOD   $dst,$src" %}
10878   ins_encode(Push_Reg_Mod_DPR(dst, src),
10879               emitModDPR(),
10880               Push_Result_Mod_DPR(src),
10881               Pop_Reg_FPR(dst));
10882   ins_pipe( pipe_slow );
10883 %}
10884 
10885 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10886   predicate(UseSSE>=1);
10887   match(Set dst (ModF src0 src1));
10888   effect(KILL rax, KILL cr);
10889   format %{ "SUB    ESP,4\t # FMOD\n"
10890           "\tMOVSS  [ESP+0],$src1\n"
10891           "\tFLD_S  [ESP+0]\n"
10892           "\tMOVSS  [ESP+0],$src0\n"
10893           "\tFLD_S  [ESP+0]\n"
10894      "loop:\tFPREM\n"
10895           "\tFWAIT\n"
10896           "\tFNSTSW AX\n"
10897           "\tSAHF\n"
10898           "\tJP     loop\n"
10899           "\tFSTP_S [ESP+0]\n"
10900           "\tMOVSS  $dst,[ESP+0]\n"
10901           "\tADD    ESP,4\n"
10902           "\tFSTP   ST0\t # Restore FPU Stack"
10903     %}
10904   ins_cost(250);
10905   ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10906   ins_pipe( pipe_slow );
10907 %}
10908 
10909 
10910 //----------Arithmetic Conversion Instructions---------------------------------
10911 // The conversions operations are all Alpha sorted.  Please keep it that way!
10912 
10913 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10914   predicate(UseSSE==0);
10915   match(Set dst (RoundFloat src));
10916   ins_cost(125);
10917   format %{ "FST_S  $dst,$src\t# F-round" %}
10918   ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10919   ins_pipe( fpu_mem_reg );
10920 %}
10921 
10922 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10923   predicate(UseSSE<=1);
10924   match(Set dst (RoundDouble src));
10925   ins_cost(125);
10926   format %{ "FST_D  $dst,$src\t# D-round" %}
10927   ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10928   ins_pipe( fpu_mem_reg );
10929 %}
10930 
10931 // Force rounding to 24-bit precision and 6-bit exponent
10932 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10933   predicate(UseSSE==0);
10934   match(Set dst (ConvD2F src));
10935   format %{ "FST_S  $dst,$src\t# F-round" %}
10936   expand %{
10937     roundFloat_mem_reg(dst,src);
10938   %}
10939 %}
10940 
10941 // Force rounding to 24-bit precision and 6-bit exponent
10942 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10943   predicate(UseSSE==1);
10944   match(Set dst (ConvD2F src));
10945   effect( KILL cr );
10946   format %{ "SUB    ESP,4\n\t"
10947             "FST_S  [ESP],$src\t# F-round\n\t"
10948             "MOVSS  $dst,[ESP]\n\t"
10949             "ADD ESP,4" %}
10950   ins_encode %{
10951     __ subptr(rsp, 4);
10952     if ($src$$reg != FPR1L_enc) {
10953       __ fld_s($src$$reg-1);
10954       __ fstp_s(Address(rsp, 0));
10955     } else {
10956       __ fst_s(Address(rsp, 0));
10957     }
10958     __ movflt($dst$$XMMRegister, Address(rsp, 0));
10959     __ addptr(rsp, 4);
10960   %}
10961   ins_pipe( pipe_slow );
10962 %}
10963 
10964 // Force rounding double precision to single precision
10965 instruct convD2F_reg(regF dst, regD src) %{
10966   predicate(UseSSE>=2);
10967   match(Set dst (ConvD2F src));
10968   format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10969   ins_encode %{
10970     __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10971   %}
10972   ins_pipe( pipe_slow );
10973 %}
10974 
10975 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10976   predicate(UseSSE==0);
10977   match(Set dst (ConvF2D src));
10978   format %{ "FST_S  $dst,$src\t# D-round" %}
10979   ins_encode( Pop_Reg_Reg_DPR(dst, src));
10980   ins_pipe( fpu_reg_reg );
10981 %}
10982 
10983 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10984   predicate(UseSSE==1);
10985   match(Set dst (ConvF2D src));
10986   format %{ "FST_D  $dst,$src\t# D-round" %}
10987   expand %{
10988     roundDouble_mem_reg(dst,src);
10989   %}
10990 %}
10991 
10992 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10993   predicate(UseSSE==1);
10994   match(Set dst (ConvF2D src));
10995   effect( KILL cr );
10996   format %{ "SUB    ESP,4\n\t"
10997             "MOVSS  [ESP] $src\n\t"
10998             "FLD_S  [ESP]\n\t"
10999             "ADD    ESP,4\n\t"
11000             "FSTP   $dst\t# D-round" %}
11001   ins_encode %{
11002     __ subptr(rsp, 4);
11003     __ movflt(Address(rsp, 0), $src$$XMMRegister);
11004     __ fld_s(Address(rsp, 0));
11005     __ addptr(rsp, 4);
11006     __ fstp_d($dst$$reg);
11007   %}
11008   ins_pipe( pipe_slow );
11009 %}
11010 
11011 instruct convF2D_reg(regD dst, regF src) %{
11012   predicate(UseSSE>=2);
11013   match(Set dst (ConvF2D src));
11014   format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11015   ins_encode %{
11016     __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
11017   %}
11018   ins_pipe( pipe_slow );
11019 %}
11020 
11021 // Convert a double to an int.  If the double is a NAN, stuff a zero in instead.
11022 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
11023   predicate(UseSSE<=1);
11024   match(Set dst (ConvD2I src));
11025   effect( KILL tmp, KILL cr );
11026   format %{ "FLD    $src\t# Convert double to int \n\t"
11027             "FLDCW  trunc mode\n\t"
11028             "SUB    ESP,4\n\t"
11029             "FISTp  [ESP + #0]\n\t"
11030             "FLDCW  std/24-bit mode\n\t"
11031             "POP    EAX\n\t"
11032             "CMP    EAX,0x80000000\n\t"
11033             "JNE,s  fast\n\t"
11034             "FLD_D  $src\n\t"
11035             "CALL   d2i_wrapper\n"
11036       "fast:" %}
11037   ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
11038   ins_pipe( pipe_slow );
11039 %}
11040 
11041 // Convert a double to an int.  If the double is a NAN, stuff a zero in instead.
11042 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11043   predicate(UseSSE>=2);
11044   match(Set dst (ConvD2I src));
11045   effect( KILL tmp, KILL cr );
11046   format %{ "CVTTSD2SI $dst, $src\n\t"
11047             "CMP    $dst,0x80000000\n\t"
11048             "JNE,s  fast\n\t"
11049             "SUB    ESP, 8\n\t"
11050             "MOVSD  [ESP], $src\n\t"
11051             "FLD_D  [ESP]\n\t"
11052             "ADD    ESP, 8\n\t"
11053             "CALL   d2i_wrapper\n"
11054       "fast:" %}
11055   ins_encode %{
11056     Label fast;
11057     __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
11058     __ cmpl($dst$$Register, 0x80000000);
11059     __ jccb(Assembler::notEqual, fast);
11060     __ subptr(rsp, 8);
11061     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11062     __ fld_d(Address(rsp, 0));
11063     __ addptr(rsp, 8);
11064     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11065     __ bind(fast);
11066   %}
11067   ins_pipe( pipe_slow );
11068 %}
11069 
11070 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
11071   predicate(UseSSE<=1);
11072   match(Set dst (ConvD2L src));
11073   effect( KILL cr );
11074   format %{ "FLD    $src\t# Convert double to long\n\t"
11075             "FLDCW  trunc mode\n\t"
11076             "SUB    ESP,8\n\t"
11077             "FISTp  [ESP + #0]\n\t"
11078             "FLDCW  std/24-bit mode\n\t"
11079             "POP    EAX\n\t"
11080             "POP    EDX\n\t"
11081             "CMP    EDX,0x80000000\n\t"
11082             "JNE,s  fast\n\t"
11083             "TEST   EAX,EAX\n\t"
11084             "JNE,s  fast\n\t"
11085             "FLD    $src\n\t"
11086             "CALL   d2l_wrapper\n"
11087       "fast:" %}
11088   ins_encode( Push_Reg_DPR(src),  DPR2L_encoding(src) );
11089   ins_pipe( pipe_slow );
11090 %}
11091 
11092 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11093 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11094   predicate (UseSSE>=2);
11095   match(Set dst (ConvD2L src));
11096   effect( KILL cr );
11097   format %{ "SUB    ESP,8\t# Convert double to long\n\t"
11098             "MOVSD  [ESP],$src\n\t"
11099             "FLD_D  [ESP]\n\t"
11100             "FLDCW  trunc mode\n\t"
11101             "FISTp  [ESP + #0]\n\t"
11102             "FLDCW  std/24-bit mode\n\t"
11103             "POP    EAX\n\t"
11104             "POP    EDX\n\t"
11105             "CMP    EDX,0x80000000\n\t"
11106             "JNE,s  fast\n\t"
11107             "TEST   EAX,EAX\n\t"
11108             "JNE,s  fast\n\t"
11109             "SUB    ESP,8\n\t"
11110             "MOVSD  [ESP],$src\n\t"
11111             "FLD_D  [ESP]\n\t"
11112             "ADD    ESP,8\n\t"
11113             "CALL   d2l_wrapper\n"
11114       "fast:" %}
11115   ins_encode %{
11116     Label fast;
11117     __ subptr(rsp, 8);
11118     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11119     __ fld_d(Address(rsp, 0));
11120     __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11121     __ fistp_d(Address(rsp, 0));
11122     // Restore the rounding mode, mask the exception
11123     if (Compile::current()->in_24_bit_fp_mode()) {
11124       __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11125     } else {
11126       __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11127     }
11128     // Load the converted long, adjust CPU stack
11129     __ pop(rax);
11130     __ pop(rdx);
11131     __ cmpl(rdx, 0x80000000);
11132     __ jccb(Assembler::notEqual, fast);
11133     __ testl(rax, rax);
11134     __ jccb(Assembler::notEqual, fast);
11135     __ subptr(rsp, 8);
11136     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11137     __ fld_d(Address(rsp, 0));
11138     __ addptr(rsp, 8);
11139     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11140     __ bind(fast);
11141   %}
11142   ins_pipe( pipe_slow );
11143 %}
11144 
11145 // Convert a double to an int.  Java semantics require we do complex
11146 // manglations in the corner cases.  So we set the rounding mode to
11147 // 'zero', store the darned double down as an int, and reset the
11148 // rounding mode to 'nearest'.  The hardware stores a flag value down
11149 // if we would overflow or converted a NAN; we check for this and
11150 // and go the slow path if needed.
11151 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
11152   predicate(UseSSE==0);
11153   match(Set dst (ConvF2I src));
11154   effect( KILL tmp, KILL cr );
11155   format %{ "FLD    $src\t# Convert float to int \n\t"
11156             "FLDCW  trunc mode\n\t"
11157             "SUB    ESP,4\n\t"
11158             "FISTp  [ESP + #0]\n\t"
11159             "FLDCW  std/24-bit mode\n\t"
11160             "POP    EAX\n\t"
11161             "CMP    EAX,0x80000000\n\t"
11162             "JNE,s  fast\n\t"
11163             "FLD    $src\n\t"
11164             "CALL   d2i_wrapper\n"
11165       "fast:" %}
11166   // DPR2I_encoding works for FPR2I
11167   ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11168   ins_pipe( pipe_slow );
11169 %}
11170 
11171 // Convert a float in xmm to an int reg.
11172 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11173   predicate(UseSSE>=1);
11174   match(Set dst (ConvF2I src));
11175   effect( KILL tmp, KILL cr );
11176   format %{ "CVTTSS2SI $dst, $src\n\t"
11177             "CMP    $dst,0x80000000\n\t"
11178             "JNE,s  fast\n\t"
11179             "SUB    ESP, 4\n\t"
11180             "MOVSS  [ESP], $src\n\t"
11181             "FLD    [ESP]\n\t"
11182             "ADD    ESP, 4\n\t"
11183             "CALL   d2i_wrapper\n"
11184       "fast:" %}
11185   ins_encode %{
11186     Label fast;
11187     __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11188     __ cmpl($dst$$Register, 0x80000000);
11189     __ jccb(Assembler::notEqual, fast);
11190     __ subptr(rsp, 4);
11191     __ movflt(Address(rsp, 0), $src$$XMMRegister);
11192     __ fld_s(Address(rsp, 0));
11193     __ addptr(rsp, 4);
11194     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11195     __ bind(fast);
11196   %}
11197   ins_pipe( pipe_slow );
11198 %}
11199 
11200 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11201   predicate(UseSSE==0);
11202   match(Set dst (ConvF2L src));
11203   effect( KILL cr );
11204   format %{ "FLD    $src\t# Convert float to long\n\t"
11205             "FLDCW  trunc mode\n\t"
11206             "SUB    ESP,8\n\t"
11207             "FISTp  [ESP + #0]\n\t"
11208             "FLDCW  std/24-bit mode\n\t"
11209             "POP    EAX\n\t"
11210             "POP    EDX\n\t"
11211             "CMP    EDX,0x80000000\n\t"
11212             "JNE,s  fast\n\t"
11213             "TEST   EAX,EAX\n\t"
11214             "JNE,s  fast\n\t"
11215             "FLD    $src\n\t"
11216             "CALL   d2l_wrapper\n"
11217       "fast:" %}
11218   // DPR2L_encoding works for FPR2L
11219   ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11220   ins_pipe( pipe_slow );
11221 %}
11222 
11223 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11224 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11225   predicate (UseSSE>=1);
11226   match(Set dst (ConvF2L src));
11227   effect( KILL cr );
11228   format %{ "SUB    ESP,8\t# Convert float to long\n\t"
11229             "MOVSS  [ESP],$src\n\t"
11230             "FLD_S  [ESP]\n\t"
11231             "FLDCW  trunc mode\n\t"
11232             "FISTp  [ESP + #0]\n\t"
11233             "FLDCW  std/24-bit mode\n\t"
11234             "POP    EAX\n\t"
11235             "POP    EDX\n\t"
11236             "CMP    EDX,0x80000000\n\t"
11237             "JNE,s  fast\n\t"
11238             "TEST   EAX,EAX\n\t"
11239             "JNE,s  fast\n\t"
11240             "SUB    ESP,4\t# Convert float to long\n\t"
11241             "MOVSS  [ESP],$src\n\t"
11242             "FLD_S  [ESP]\n\t"
11243             "ADD    ESP,4\n\t"
11244             "CALL   d2l_wrapper\n"
11245       "fast:" %}
11246   ins_encode %{
11247     Label fast;
11248     __ subptr(rsp, 8);
11249     __ movflt(Address(rsp, 0), $src$$XMMRegister);
11250     __ fld_s(Address(rsp, 0));
11251     __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11252     __ fistp_d(Address(rsp, 0));
11253     // Restore the rounding mode, mask the exception
11254     if (Compile::current()->in_24_bit_fp_mode()) {
11255       __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11256     } else {
11257       __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11258     }
11259     // Load the converted long, adjust CPU stack
11260     __ pop(rax);
11261     __ pop(rdx);
11262     __ cmpl(rdx, 0x80000000);
11263     __ jccb(Assembler::notEqual, fast);
11264     __ testl(rax, rax);
11265     __ jccb(Assembler::notEqual, fast);
11266     __ subptr(rsp, 4);
11267     __ movflt(Address(rsp, 0), $src$$XMMRegister);
11268     __ fld_s(Address(rsp, 0));
11269     __ addptr(rsp, 4);
11270     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11271     __ bind(fast);
11272   %}
11273   ins_pipe( pipe_slow );
11274 %}
11275 
11276 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11277   predicate( UseSSE<=1 );
11278   match(Set dst (ConvI2D src));
11279   format %{ "FILD   $src\n\t"
11280             "FSTP   $dst" %}
11281   opcode(0xDB, 0x0);  /* DB /0 */
11282   ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11283   ins_pipe( fpu_reg_mem );
11284 %}
11285 
11286 instruct convI2D_reg(regD dst, rRegI src) %{
11287   predicate( UseSSE>=2 && !UseXmmI2D );
11288   match(Set dst (ConvI2D src));
11289   format %{ "CVTSI2SD $dst,$src" %}
11290   ins_encode %{
11291     __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11292   %}
11293   ins_pipe( pipe_slow );
11294 %}
11295 
11296 instruct convI2D_mem(regD dst, memory mem) %{
11297   predicate( UseSSE>=2 );
11298   match(Set dst (ConvI2D (LoadI mem)));
11299   format %{ "CVTSI2SD $dst,$mem" %}
11300   ins_encode %{
11301     __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11302   %}
11303   ins_pipe( pipe_slow );
11304 %}
11305 
11306 instruct convXI2D_reg(regD dst, rRegI src)
11307 %{
11308   predicate( UseSSE>=2 && UseXmmI2D );
11309   match(Set dst (ConvI2D src));
11310 
11311   format %{ "MOVD  $dst,$src\n\t"
11312             "CVTDQ2PD $dst,$dst\t# i2d" %}
11313   ins_encode %{
11314     __ movdl($dst$$XMMRegister, $src$$Register);
11315     __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11316   %}
11317   ins_pipe(pipe_slow); // XXX
11318 %}
11319 
11320 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11321   predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11322   match(Set dst (ConvI2D (LoadI mem)));
11323   format %{ "FILD   $mem\n\t"
11324             "FSTP   $dst" %}
11325   opcode(0xDB);      /* DB /0 */
11326   ins_encode( OpcP, RMopc_Mem(0x00,mem),
11327               Pop_Reg_DPR(dst));
11328   ins_pipe( fpu_reg_mem );
11329 %}
11330 
11331 // Convert a byte to a float; no rounding step needed.
11332 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11333   predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11334   match(Set dst (ConvI2F src));
11335   format %{ "FILD   $src\n\t"
11336             "FSTP   $dst" %}
11337 
11338   opcode(0xDB, 0x0);  /* DB /0 */
11339   ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11340   ins_pipe( fpu_reg_mem );
11341 %}
11342 
11343 // In 24-bit mode, force exponent rounding by storing back out
11344 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11345   predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11346   match(Set dst (ConvI2F src));
11347   ins_cost(200);
11348   format %{ "FILD   $src\n\t"
11349             "FSTP_S $dst" %}
11350   opcode(0xDB, 0x0);  /* DB /0 */
11351   ins_encode( Push_Mem_I(src),
11352               Pop_Mem_FPR(dst));
11353   ins_pipe( fpu_mem_mem );
11354 %}
11355 
11356 // In 24-bit mode, force exponent rounding by storing back out
11357 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11358   predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11359   match(Set dst (ConvI2F (LoadI mem)));
11360   ins_cost(200);
11361   format %{ "FILD   $mem\n\t"
11362             "FSTP_S $dst" %}
11363   opcode(0xDB);  /* DB /0 */
11364   ins_encode( OpcP, RMopc_Mem(0x00,mem),
11365               Pop_Mem_FPR(dst));
11366   ins_pipe( fpu_mem_mem );
11367 %}
11368 
11369 // This instruction does not round to 24-bits
11370 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11371   predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11372   match(Set dst (ConvI2F src));
11373   format %{ "FILD   $src\n\t"
11374             "FSTP   $dst" %}
11375   opcode(0xDB, 0x0);  /* DB /0 */
11376   ins_encode( Push_Mem_I(src),
11377               Pop_Reg_FPR(dst));
11378   ins_pipe( fpu_reg_mem );
11379 %}
11380 
11381 // This instruction does not round to 24-bits
11382 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11383   predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11384   match(Set dst (ConvI2F (LoadI mem)));
11385   format %{ "FILD   $mem\n\t"
11386             "FSTP   $dst" %}
11387   opcode(0xDB);      /* DB /0 */
11388   ins_encode( OpcP, RMopc_Mem(0x00,mem),
11389               Pop_Reg_FPR(dst));
11390   ins_pipe( fpu_reg_mem );
11391 %}
11392 
11393 // Convert an int to a float in xmm; no rounding step needed.
11394 instruct convI2F_reg(regF dst, rRegI src) %{
11395   predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11396   match(Set dst (ConvI2F src));
11397   format %{ "CVTSI2SS $dst, $src" %}
11398   ins_encode %{
11399     __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11400   %}
11401   ins_pipe( pipe_slow );
11402 %}
11403 
11404  instruct convXI2F_reg(regF dst, rRegI src)
11405 %{
11406   predicate( UseSSE>=2 && UseXmmI2F );
11407   match(Set dst (ConvI2F src));
11408 
11409   format %{ "MOVD  $dst,$src\n\t"
11410             "CVTDQ2PS $dst,$dst\t# i2f" %}
11411   ins_encode %{
11412     __ movdl($dst$$XMMRegister, $src$$Register);
11413     __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11414   %}
11415   ins_pipe(pipe_slow); // XXX
11416 %}
11417 
11418 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11419   match(Set dst (ConvI2L src));
11420   effect(KILL cr);
11421   ins_cost(375);
11422   format %{ "MOV    $dst.lo,$src\n\t"
11423             "MOV    $dst.hi,$src\n\t"
11424             "SAR    $dst.hi,31" %}
11425   ins_encode(convert_int_long(dst,src));
11426   ins_pipe( ialu_reg_reg_long );
11427 %}
11428 
11429 // Zero-extend convert int to long
11430 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11431   match(Set dst (AndL (ConvI2L src) mask) );
11432   effect( KILL flags );
11433   ins_cost(250);
11434   format %{ "MOV    $dst.lo,$src\n\t"
11435             "XOR    $dst.hi,$dst.hi" %}
11436   opcode(0x33); // XOR
11437   ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11438   ins_pipe( ialu_reg_reg_long );
11439 %}
11440 
11441 // Zero-extend long
11442 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11443   match(Set dst (AndL src mask) );
11444   effect( KILL flags );
11445   ins_cost(250);
11446   format %{ "MOV    $dst.lo,$src.lo\n\t"
11447             "XOR    $dst.hi,$dst.hi\n\t" %}
11448   opcode(0x33); // XOR
11449   ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11450   ins_pipe( ialu_reg_reg_long );
11451 %}
11452 
11453 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11454   predicate (UseSSE<=1);
11455   match(Set dst (ConvL2D src));
11456   effect( KILL cr );
11457   format %{ "PUSH   $src.hi\t# Convert long to double\n\t"
11458             "PUSH   $src.lo\n\t"
11459             "FILD   ST,[ESP + #0]\n\t"
11460             "ADD    ESP,8\n\t"
11461             "FSTP_D $dst\t# D-round" %}
11462   opcode(0xDF, 0x5);  /* DF /5 */
11463   ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11464   ins_pipe( pipe_slow );
11465 %}
11466 
11467 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11468   predicate (UseSSE>=2);
11469   match(Set dst (ConvL2D src));
11470   effect( KILL cr );
11471   format %{ "PUSH   $src.hi\t# Convert long to double\n\t"
11472             "PUSH   $src.lo\n\t"
11473             "FILD_D [ESP]\n\t"
11474             "FSTP_D [ESP]\n\t"
11475             "MOVSD  $dst,[ESP]\n\t"
11476             "ADD    ESP,8" %}
11477   opcode(0xDF, 0x5);  /* DF /5 */
11478   ins_encode(convert_long_double2(src), Push_ResultD(dst));
11479   ins_pipe( pipe_slow );
11480 %}
11481 
11482 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11483   predicate (UseSSE>=1);
11484   match(Set dst (ConvL2F src));
11485   effect( KILL cr );
11486   format %{ "PUSH   $src.hi\t# Convert long to single float\n\t"
11487             "PUSH   $src.lo\n\t"
11488             "FILD_D [ESP]\n\t"
11489             "FSTP_S [ESP]\n\t"
11490             "MOVSS  $dst,[ESP]\n\t"
11491             "ADD    ESP,8" %}
11492   opcode(0xDF, 0x5);  /* DF /5 */
11493   ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11494   ins_pipe( pipe_slow );
11495 %}
11496 
11497 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11498   match(Set dst (ConvL2F src));
11499   effect( KILL cr );
11500   format %{ "PUSH   $src.hi\t# Convert long to single float\n\t"
11501             "PUSH   $src.lo\n\t"
11502             "FILD   ST,[ESP + #0]\n\t"
11503             "ADD    ESP,8\n\t"
11504             "FSTP_S $dst\t# F-round" %}
11505   opcode(0xDF, 0x5);  /* DF /5 */
11506   ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11507   ins_pipe( pipe_slow );
11508 %}
11509 
11510 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11511   match(Set dst (ConvL2I src));
11512   effect( DEF dst, USE src );
11513   format %{ "MOV    $dst,$src.lo" %}
11514   ins_encode(enc_CopyL_Lo(dst,src));
11515   ins_pipe( ialu_reg_reg );
11516 %}
11517 
11518 
11519 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11520   match(Set dst (MoveF2I src));
11521   effect( DEF dst, USE src );
11522   ins_cost(100);
11523   format %{ "MOV    $dst,$src\t# MoveF2I_stack_reg" %}
11524   ins_encode %{
11525     __ movl($dst$$Register, Address(rsp, $src$$disp));
11526   %}
11527   ins_pipe( ialu_reg_mem );
11528 %}
11529 
11530 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11531   predicate(UseSSE==0);
11532   match(Set dst (MoveF2I src));
11533   effect( DEF dst, USE src );
11534 
11535   ins_cost(125);
11536   format %{ "FST_S  $dst,$src\t# MoveF2I_reg_stack" %}
11537   ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11538   ins_pipe( fpu_mem_reg );
11539 %}
11540 
11541 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11542   predicate(UseSSE>=1);
11543   match(Set dst (MoveF2I src));
11544   effect( DEF dst, USE src );
11545 
11546   ins_cost(95);
11547   format %{ "MOVSS  $dst,$src\t# MoveF2I_reg_stack_sse" %}
11548   ins_encode %{
11549     __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11550   %}
11551   ins_pipe( pipe_slow );
11552 %}
11553 
11554 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11555   predicate(UseSSE>=2);
11556   match(Set dst (MoveF2I src));
11557   effect( DEF dst, USE src );
11558   ins_cost(85);
11559   format %{ "MOVD   $dst,$src\t# MoveF2I_reg_reg_sse" %}
11560   ins_encode %{
11561     __ movdl($dst$$Register, $src$$XMMRegister);
11562   %}
11563   ins_pipe( pipe_slow );
11564 %}
11565 
11566 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11567   match(Set dst (MoveI2F src));
11568   effect( DEF dst, USE src );
11569 
11570   ins_cost(100);
11571   format %{ "MOV    $dst,$src\t# MoveI2F_reg_stack" %}
11572   ins_encode %{
11573     __ movl(Address(rsp, $dst$$disp), $src$$Register);
11574   %}
11575   ins_pipe( ialu_mem_reg );
11576 %}
11577 
11578 
11579 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11580   predicate(UseSSE==0);
11581   match(Set dst (MoveI2F src));
11582   effect(DEF dst, USE src);
11583 
11584   ins_cost(125);
11585   format %{ "FLD_S  $src\n\t"
11586             "FSTP   $dst\t# MoveI2F_stack_reg" %}
11587   opcode(0xD9);               /* D9 /0, FLD m32real */
11588   ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11589               Pop_Reg_FPR(dst) );
11590   ins_pipe( fpu_reg_mem );
11591 %}
11592 
11593 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11594   predicate(UseSSE>=1);
11595   match(Set dst (MoveI2F src));
11596   effect( DEF dst, USE src );
11597 
11598   ins_cost(95);
11599   format %{ "MOVSS  $dst,$src\t# MoveI2F_stack_reg_sse" %}
11600   ins_encode %{
11601     __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11602   %}
11603   ins_pipe( pipe_slow );
11604 %}
11605 
11606 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11607   predicate(UseSSE>=2);
11608   match(Set dst (MoveI2F src));
11609   effect( DEF dst, USE src );
11610 
11611   ins_cost(85);
11612   format %{ "MOVD   $dst,$src\t# MoveI2F_reg_reg_sse" %}
11613   ins_encode %{
11614     __ movdl($dst$$XMMRegister, $src$$Register);
11615   %}
11616   ins_pipe( pipe_slow );
11617 %}
11618 
11619 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11620   match(Set dst (MoveD2L src));
11621   effect(DEF dst, USE src);
11622 
11623   ins_cost(250);
11624   format %{ "MOV    $dst.lo,$src\n\t"
11625             "MOV    $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11626   opcode(0x8B, 0x8B);
11627   ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11628   ins_pipe( ialu_mem_long_reg );
11629 %}
11630 
11631 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11632   predicate(UseSSE<=1);
11633   match(Set dst (MoveD2L src));
11634   effect(DEF dst, USE src);
11635 
11636   ins_cost(125);
11637   format %{ "FST_D  $dst,$src\t# MoveD2L_reg_stack" %}
11638   ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11639   ins_pipe( fpu_mem_reg );
11640 %}
11641 
11642 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11643   predicate(UseSSE>=2);
11644   match(Set dst (MoveD2L src));
11645   effect(DEF dst, USE src);
11646   ins_cost(95);
11647   format %{ "MOVSD  $dst,$src\t# MoveD2L_reg_stack_sse" %}
11648   ins_encode %{
11649     __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11650   %}
11651   ins_pipe( pipe_slow );
11652 %}
11653 
11654 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11655   predicate(UseSSE>=2);
11656   match(Set dst (MoveD2L src));
11657   effect(DEF dst, USE src, TEMP tmp);
11658   ins_cost(85);
11659   format %{ "MOVD   $dst.lo,$src\n\t"
11660             "PSHUFLW $tmp,$src,0x4E\n\t"
11661             "MOVD   $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11662   ins_encode %{
11663     __ movdl($dst$$Register, $src$$XMMRegister);
11664     __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11665     __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11666   %}
11667   ins_pipe( pipe_slow );
11668 %}
11669 
11670 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11671   match(Set dst (MoveL2D src));
11672   effect(DEF dst, USE src);
11673 
11674   ins_cost(200);
11675   format %{ "MOV    $dst,$src.lo\n\t"
11676             "MOV    $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11677   opcode(0x89, 0x89);
11678   ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11679   ins_pipe( ialu_mem_long_reg );
11680 %}
11681 
11682 
11683 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11684   predicate(UseSSE<=1);
11685   match(Set dst (MoveL2D src));
11686   effect(DEF dst, USE src);
11687   ins_cost(125);
11688 
11689   format %{ "FLD_D  $src\n\t"
11690             "FSTP   $dst\t# MoveL2D_stack_reg" %}
11691   opcode(0xDD);               /* DD /0, FLD m64real */
11692   ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11693               Pop_Reg_DPR(dst) );
11694   ins_pipe( fpu_reg_mem );
11695 %}
11696 
11697 
11698 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11699   predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11700   match(Set dst (MoveL2D src));
11701   effect(DEF dst, USE src);
11702 
11703   ins_cost(95);
11704   format %{ "MOVSD  $dst,$src\t# MoveL2D_stack_reg_sse" %}
11705   ins_encode %{
11706     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11707   %}
11708   ins_pipe( pipe_slow );
11709 %}
11710 
11711 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11712   predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11713   match(Set dst (MoveL2D src));
11714   effect(DEF dst, USE src);
11715 
11716   ins_cost(95);
11717   format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11718   ins_encode %{
11719     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11720   %}
11721   ins_pipe( pipe_slow );
11722 %}
11723 
11724 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11725   predicate(UseSSE>=2);
11726   match(Set dst (MoveL2D src));
11727   effect(TEMP dst, USE src, TEMP tmp);
11728   ins_cost(85);
11729   format %{ "MOVD   $dst,$src.lo\n\t"
11730             "MOVD   $tmp,$src.hi\n\t"
11731             "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11732   ins_encode %{
11733     __ movdl($dst$$XMMRegister, $src$$Register);
11734     __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11735     __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11736   %}
11737   ins_pipe( pipe_slow );
11738 %}
11739 
11740 
11741 // =======================================================================
11742 // fast clearing of an array
11743 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11744   predicate(!UseFastStosb);
11745   match(Set dummy (ClearArray cnt base));
11746   effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11747   format %{ "XOR    EAX,EAX\t# ClearArray:\n\t"
11748             "SHL    ECX,1\t# Convert doublewords to words\n\t"
11749             "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11750   ins_encode %{ 
11751     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11752   %}
11753   ins_pipe( pipe_slow );
11754 %}
11755 
11756 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11757   predicate(UseFastStosb);
11758   match(Set dummy (ClearArray cnt base));
11759   effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11760   format %{ "XOR    EAX,EAX\t# ClearArray:\n\t"
11761             "SHL    ECX,3\t# Convert doublewords to bytes\n\t"
11762             "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11763   ins_encode %{ 
11764     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11765   %}
11766   ins_pipe( pipe_slow );
11767 %}
11768 
11769 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11770                         eAXRegI result, regD tmp1, eFlagsReg cr) %{
11771   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11772   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11773 
11774   format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11775   ins_encode %{
11776     __ string_compare($str1$$Register, $str2$$Register,
11777                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11778                       $tmp1$$XMMRegister);
11779   %}
11780   ins_pipe( pipe_slow );
11781 %}
11782 
11783 // fast string equals
11784 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11785                        regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11786   match(Set result (StrEquals (Binary str1 str2) cnt));
11787   effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11788 
11789   format %{ "String Equals $str1,$str2,$cnt -> $result    // KILL $tmp1, $tmp2, $tmp3" %}
11790   ins_encode %{
11791     __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11792                           $cnt$$Register, $result$$Register, $tmp3$$Register,
11793                           $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11794   %}
11795   ins_pipe( pipe_slow );
11796 %}
11797 
11798 // fast search of substring with known size.
11799 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11800                             eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11801   predicate(UseSSE42Intrinsics);
11802   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11803   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11804 
11805   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $vec, $cnt1, $cnt2, $tmp" %}
11806   ins_encode %{
11807     int icnt2 = (int)$int_cnt2$$constant;
11808     if (icnt2 >= 8) {
11809       // IndexOf for constant substrings with size >= 8 elements
11810       // which don't need to be loaded through stack.
11811       __ string_indexofC8($str1$$Register, $str2$$Register,
11812                           $cnt1$$Register, $cnt2$$Register,
11813                           icnt2, $result$$Register,
11814                           $vec$$XMMRegister, $tmp$$Register);
11815     } else {
11816       // Small strings are loaded through stack if they cross page boundary.
11817       __ string_indexof($str1$$Register, $str2$$Register,
11818                         $cnt1$$Register, $cnt2$$Register,
11819                         icnt2, $result$$Register,
11820                         $vec$$XMMRegister, $tmp$$Register);
11821     }
11822   %}
11823   ins_pipe( pipe_slow );
11824 %}
11825 
11826 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11827                         eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11828   predicate(UseSSE42Intrinsics);
11829   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11830   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11831 
11832   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11833   ins_encode %{
11834     __ string_indexof($str1$$Register, $str2$$Register,
11835                       $cnt1$$Register, $cnt2$$Register,
11836                       (-1), $result$$Register,
11837                       $vec$$XMMRegister, $tmp$$Register);
11838   %}
11839   ins_pipe( pipe_slow );
11840 %}
11841 
11842 // fast array equals
11843 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11844                       regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11845 %{
11846   match(Set result (AryEq ary1 ary2));
11847   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11848   //ins_cost(300);
11849 
11850   format %{ "Array Equals $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11851   ins_encode %{
11852     __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11853                           $tmp3$$Register, $result$$Register, $tmp4$$Register,
11854                           $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11855   %}
11856   ins_pipe( pipe_slow );
11857 %}
11858 
11859 // encode char[] to byte[] in ISO_8859_1
11860 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11861                           regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11862                           eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11863   match(Set result (EncodeISOArray src (Binary dst len)));
11864   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11865 
11866   format %{ "Encode array $src,$dst,$len -> $result    // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11867   ins_encode %{
11868     __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11869                         $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11870                         $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11871   %}
11872   ins_pipe( pipe_slow );
11873 %}
11874 
11875 
11876 //----------Control Flow Instructions------------------------------------------
11877 // Signed compare Instructions
11878 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11879   match(Set cr (CmpI op1 op2));
11880   effect( DEF cr, USE op1, USE op2 );
11881   format %{ "CMP    $op1,$op2" %}
11882   opcode(0x3B);  /* Opcode 3B /r */
11883   ins_encode( OpcP, RegReg( op1, op2) );
11884   ins_pipe( ialu_cr_reg_reg );
11885 %}
11886 
11887 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11888   match(Set cr (CmpI op1 op2));
11889   effect( DEF cr, USE op1 );
11890   format %{ "CMP    $op1,$op2" %}
11891   opcode(0x81,0x07);  /* Opcode 81 /7 */
11892   // ins_encode( RegImm( op1, op2) );  /* Was CmpImm */
11893   ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11894   ins_pipe( ialu_cr_reg_imm );
11895 %}
11896 
11897 // Cisc-spilled version of cmpI_eReg
11898 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11899   match(Set cr (CmpI op1 (LoadI op2)));
11900 
11901   format %{ "CMP    $op1,$op2" %}
11902   ins_cost(500);
11903   opcode(0x3B);  /* Opcode 3B /r */
11904   ins_encode( OpcP, RegMem( op1, op2) );
11905   ins_pipe( ialu_cr_reg_mem );
11906 %}
11907 
11908 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11909   match(Set cr (CmpI src zero));
11910   effect( DEF cr, USE src );
11911 
11912   format %{ "TEST   $src,$src" %}
11913   opcode(0x85);
11914   ins_encode( OpcP, RegReg( src, src ) );
11915   ins_pipe( ialu_cr_reg_imm );
11916 %}
11917 
11918 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11919   match(Set cr (CmpI (AndI src con) zero));
11920 
11921   format %{ "TEST   $src,$con" %}
11922   opcode(0xF7,0x00);
11923   ins_encode( OpcP, RegOpc(src), Con32(con) );
11924   ins_pipe( ialu_cr_reg_imm );
11925 %}
11926 
11927 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11928   match(Set cr (CmpI (AndI src mem) zero));
11929 
11930   format %{ "TEST   $src,$mem" %}
11931   opcode(0x85);
11932   ins_encode( OpcP, RegMem( src, mem ) );
11933   ins_pipe( ialu_cr_reg_mem );
11934 %}
11935 
11936 // Unsigned compare Instructions; really, same as signed except they
11937 // produce an eFlagsRegU instead of eFlagsReg.
11938 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11939   match(Set cr (CmpU op1 op2));
11940 
11941   format %{ "CMPu   $op1,$op2" %}
11942   opcode(0x3B);  /* Opcode 3B /r */
11943   ins_encode( OpcP, RegReg( op1, op2) );
11944   ins_pipe( ialu_cr_reg_reg );
11945 %}
11946 
11947 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11948   match(Set cr (CmpU op1 op2));
11949 
11950   format %{ "CMPu   $op1,$op2" %}
11951   opcode(0x81,0x07);  /* Opcode 81 /7 */
11952   ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11953   ins_pipe( ialu_cr_reg_imm );
11954 %}
11955 
11956 // // Cisc-spilled version of cmpU_eReg
11957 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11958   match(Set cr (CmpU op1 (LoadI op2)));
11959 
11960   format %{ "CMPu   $op1,$op2" %}
11961   ins_cost(500);
11962   opcode(0x3B);  /* Opcode 3B /r */
11963   ins_encode( OpcP, RegMem( op1, op2) );
11964   ins_pipe( ialu_cr_reg_mem );
11965 %}
11966 
11967 // // Cisc-spilled version of cmpU_eReg
11968 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11969 //  match(Set cr (CmpU (LoadI op1) op2));
11970 //
11971 //  format %{ "CMPu   $op1,$op2" %}
11972 //  ins_cost(500);
11973 //  opcode(0x39);  /* Opcode 39 /r */
11974 //  ins_encode( OpcP, RegMem( op1, op2) );
11975 //%}
11976 
11977 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11978   match(Set cr (CmpU src zero));
11979 
11980   format %{ "TESTu  $src,$src" %}
11981   opcode(0x85);
11982   ins_encode( OpcP, RegReg( src, src ) );
11983   ins_pipe( ialu_cr_reg_imm );
11984 %}
11985 
11986 // Unsigned pointer compare Instructions
11987 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11988   match(Set cr (CmpP op1 op2));
11989 
11990   format %{ "CMPu   $op1,$op2" %}
11991   opcode(0x3B);  /* Opcode 3B /r */
11992   ins_encode( OpcP, RegReg( op1, op2) );
11993   ins_pipe( ialu_cr_reg_reg );
11994 %}
11995 
11996 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11997   match(Set cr (CmpP op1 op2));
11998 
11999   format %{ "CMPu   $op1,$op2" %}
12000   opcode(0x81,0x07);  /* Opcode 81 /7 */
12001   ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12002   ins_pipe( ialu_cr_reg_imm );
12003 %}
12004 
12005 // // Cisc-spilled version of cmpP_eReg
12006 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12007   match(Set cr (CmpP op1 (LoadP op2)));
12008 
12009   format %{ "CMPu   $op1,$op2" %}
12010   ins_cost(500);
12011   opcode(0x3B);  /* Opcode 3B /r */
12012   ins_encode( OpcP, RegMem( op1, op2) );
12013   ins_pipe( ialu_cr_reg_mem );
12014 %}
12015 
12016 // // Cisc-spilled version of cmpP_eReg
12017 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12018 //  match(Set cr (CmpP (LoadP op1) op2));
12019 //
12020 //  format %{ "CMPu   $op1,$op2" %}
12021 //  ins_cost(500);
12022 //  opcode(0x39);  /* Opcode 39 /r */
12023 //  ins_encode( OpcP, RegMem( op1, op2) );
12024 //%}
12025 
12026 // Compare raw pointer (used in out-of-heap check).
12027 // Only works because non-oop pointers must be raw pointers
12028 // and raw pointers have no anti-dependencies.
12029 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12030   predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none );
12031   match(Set cr (CmpP op1 (LoadP op2)));
12032 
12033   format %{ "CMPu   $op1,$op2" %}
12034   opcode(0x3B);  /* Opcode 3B /r */
12035   ins_encode( OpcP, RegMem( op1, op2) );
12036   ins_pipe( ialu_cr_reg_mem );
12037 %}
12038 
12039 //
12040 // This will generate a signed flags result. This should be ok
12041 // since any compare to a zero should be eq/neq.
12042 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12043   match(Set cr (CmpP src zero));
12044 
12045   format %{ "TEST   $src,$src" %}
12046   opcode(0x85);
12047   ins_encode( OpcP, RegReg( src, src ) );
12048   ins_pipe( ialu_cr_reg_imm );
12049 %}
12050 
12051 // Cisc-spilled version of testP_reg
12052 // This will generate a signed flags result. This should be ok
12053 // since any compare to a zero should be eq/neq.
12054 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12055   match(Set cr (CmpP (LoadP op) zero));
12056 
12057   format %{ "TEST   $op,0xFFFFFFFF" %}
12058   ins_cost(500);
12059   opcode(0xF7);               /* Opcode F7 /0 */
12060   ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12061   ins_pipe( ialu_cr_reg_imm );
12062 %}
12063 
12064 // Yanked all unsigned pointer compare operations.
12065 // Pointer compares are done with CmpP which is already unsigned.
12066 
12067 //----------Max and Min--------------------------------------------------------
12068 // Min Instructions
12069 ////
12070 //   *** Min and Max using the conditional move are slower than the
12071 //   *** branch version on a Pentium III.
12072 // // Conditional move for min
12073 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12074 //  effect( USE_DEF op2, USE op1, USE cr );
12075 //  format %{ "CMOVlt $op2,$op1\t! min" %}
12076 //  opcode(0x4C,0x0F);
12077 //  ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12078 //  ins_pipe( pipe_cmov_reg );
12079 //%}
12080 //
12081 //// Min Register with Register (P6 version)
12082 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
12083 //  predicate(VM_Version::supports_cmov() );
12084 //  match(Set op2 (MinI op1 op2));
12085 //  ins_cost(200);
12086 //  expand %{
12087 //    eFlagsReg cr;
12088 //    compI_eReg(cr,op1,op2);
12089 //    cmovI_reg_lt(op2,op1,cr);
12090 //  %}
12091 //%}
12092 
12093 // Min Register with Register (generic version)
12094 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12095   match(Set dst (MinI dst src));
12096   effect(KILL flags);
12097   ins_cost(300);
12098 
12099   format %{ "MIN    $dst,$src" %}
12100   opcode(0xCC);
12101   ins_encode( min_enc(dst,src) );
12102   ins_pipe( pipe_slow );
12103 %}
12104 
12105 // Max Register with Register
12106 //   *** Min and Max using the conditional move are slower than the
12107 //   *** branch version on a Pentium III.
12108 // // Conditional move for max
12109 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12110 //  effect( USE_DEF op2, USE op1, USE cr );
12111 //  format %{ "CMOVgt $op2,$op1\t! max" %}
12112 //  opcode(0x4F,0x0F);
12113 //  ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12114 //  ins_pipe( pipe_cmov_reg );
12115 //%}
12116 //
12117 // // Max Register with Register (P6 version)
12118 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
12119 //  predicate(VM_Version::supports_cmov() );
12120 //  match(Set op2 (MaxI op1 op2));
12121 //  ins_cost(200);
12122 //  expand %{
12123 //    eFlagsReg cr;
12124 //    compI_eReg(cr,op1,op2);
12125 //    cmovI_reg_gt(op2,op1,cr);
12126 //  %}
12127 //%}
12128 
12129 // Max Register with Register (generic version)
12130 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12131   match(Set dst (MaxI dst src));
12132   effect(KILL flags);
12133   ins_cost(300);
12134 
12135   format %{ "MAX    $dst,$src" %}
12136   opcode(0xCC);
12137   ins_encode( max_enc(dst,src) );
12138   ins_pipe( pipe_slow );
12139 %}
12140 
12141 // ============================================================================
12142 // Counted Loop limit node which represents exact final iterator value.
12143 // Note: the resulting value should fit into integer range since
12144 // counted loops have limit check on overflow.
12145 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
12146   match(Set limit (LoopLimit (Binary init limit) stride));
12147   effect(TEMP limit_hi, TEMP tmp, KILL flags);
12148   ins_cost(300);
12149 
12150   format %{ "loopLimit $init,$limit,$stride  # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
12151   ins_encode %{
12152     int strd = (int)$stride$$constant;
12153     assert(strd != 1 && strd != -1, "sanity");
12154     int m1 = (strd > 0) ? 1 : -1;
12155     // Convert limit to long (EAX:EDX)
12156     __ cdql();
12157     // Convert init to long (init:tmp)
12158     __ movl($tmp$$Register, $init$$Register);
12159     __ sarl($tmp$$Register, 31);
12160     // $limit - $init
12161     __ subl($limit$$Register, $init$$Register);
12162     __ sbbl($limit_hi$$Register, $tmp$$Register);
12163     // + ($stride - 1)
12164     if (strd > 0) {
12165       __ addl($limit$$Register, (strd - 1));
12166       __ adcl($limit_hi$$Register, 0);
12167       __ movl($tmp$$Register, strd);
12168     } else {
12169       __ addl($limit$$Register, (strd + 1));
12170       __ adcl($limit_hi$$Register, -1);
12171       __ lneg($limit_hi$$Register, $limit$$Register);
12172       __ movl($tmp$$Register, -strd);
12173     }
12174     // signed devision: (EAX:EDX) / pos_stride
12175     __ idivl($tmp$$Register);
12176     if (strd < 0) {
12177       // restore sign
12178       __ negl($tmp$$Register);
12179     }
12180     // (EAX) * stride
12181     __ mull($tmp$$Register);
12182     // + init (ignore upper bits)
12183     __ addl($limit$$Register, $init$$Register);
12184   %}
12185   ins_pipe( pipe_slow );
12186 %}
12187 
12188 // ============================================================================
12189 // Branch Instructions
12190 // Jump Table
12191 instruct jumpXtnd(rRegI switch_val) %{
12192   match(Jump switch_val);
12193   ins_cost(350);
12194   format %{  "JMP    [$constantaddress](,$switch_val,1)\n\t" %}
12195   ins_encode %{
12196     // Jump to Address(table_base + switch_reg)
12197     Address index(noreg, $switch_val$$Register, Address::times_1);
12198     __ jump(ArrayAddress($constantaddress, index));
12199   %}
12200   ins_pipe(pipe_jmp);
12201 %}
12202 
12203 // Jump Direct - Label defines a relative address from JMP+1
12204 instruct jmpDir(label labl) %{
12205   match(Goto);
12206   effect(USE labl);
12207 
12208   ins_cost(300);
12209   format %{ "JMP    $labl" %}
12210   size(5);
12211   ins_encode %{
12212     Label* L = $labl$$label;
12213     __ jmp(*L, false); // Always long jump
12214   %}
12215   ins_pipe( pipe_jmp );
12216 %}
12217 
12218 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12219 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12220   match(If cop cr);
12221   effect(USE labl);
12222 
12223   ins_cost(300);
12224   format %{ "J$cop    $labl" %}
12225   size(6);
12226   ins_encode %{
12227     Label* L = $labl$$label;
12228     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12229   %}
12230   ins_pipe( pipe_jcc );
12231 %}
12232 
12233 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12234 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12235   match(CountedLoopEnd cop cr);
12236   effect(USE labl);
12237 
12238   ins_cost(300);
12239   format %{ "J$cop    $labl\t# Loop end" %}
12240   size(6);
12241   ins_encode %{
12242     Label* L = $labl$$label;
12243     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12244   %}
12245   ins_pipe( pipe_jcc );
12246 %}
12247 
12248 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12249 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12250   match(CountedLoopEnd cop cmp);
12251   effect(USE labl);
12252 
12253   ins_cost(300);
12254   format %{ "J$cop,u  $labl\t# Loop end" %}
12255   size(6);
12256   ins_encode %{
12257     Label* L = $labl$$label;
12258     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12259   %}
12260   ins_pipe( pipe_jcc );
12261 %}
12262 
12263 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12264   match(CountedLoopEnd cop cmp);
12265   effect(USE labl);
12266 
12267   ins_cost(200);
12268   format %{ "J$cop,u  $labl\t# Loop end" %}
12269   size(6);
12270   ins_encode %{
12271     Label* L = $labl$$label;
12272     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12273   %}
12274   ins_pipe( pipe_jcc );
12275 %}
12276 
12277 // Jump Direct Conditional - using unsigned comparison
12278 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12279   match(If cop cmp);
12280   effect(USE labl);
12281 
12282   ins_cost(300);
12283   format %{ "J$cop,u  $labl" %}
12284   size(6);
12285   ins_encode %{
12286     Label* L = $labl$$label;
12287     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12288   %}
12289   ins_pipe(pipe_jcc);
12290 %}
12291 
12292 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12293   match(If cop cmp);
12294   effect(USE labl);
12295 
12296   ins_cost(200);
12297   format %{ "J$cop,u  $labl" %}
12298   size(6);
12299   ins_encode %{
12300     Label* L = $labl$$label;
12301     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12302   %}
12303   ins_pipe(pipe_jcc);
12304 %}
12305 
12306 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12307   match(If cop cmp);
12308   effect(USE labl);
12309 
12310   ins_cost(200);
12311   format %{ $$template
12312     if ($cop$$cmpcode == Assembler::notEqual) {
12313       $$emit$$"JP,u   $labl\n\t"
12314       $$emit$$"J$cop,u   $labl"
12315     } else {
12316       $$emit$$"JP,u   done\n\t"
12317       $$emit$$"J$cop,u   $labl\n\t"
12318       $$emit$$"done:"
12319     }
12320   %}
12321   ins_encode %{
12322     Label* l = $labl$$label;
12323     if ($cop$$cmpcode == Assembler::notEqual) {
12324       __ jcc(Assembler::parity, *l, false);
12325       __ jcc(Assembler::notEqual, *l, false);
12326     } else if ($cop$$cmpcode == Assembler::equal) {
12327       Label done;
12328       __ jccb(Assembler::parity, done);
12329       __ jcc(Assembler::equal, *l, false);
12330       __ bind(done);
12331     } else {
12332        ShouldNotReachHere();
12333     }
12334   %}
12335   ins_pipe(pipe_jcc);
12336 %}
12337 
12338 // ============================================================================
12339 // The 2nd slow-half of a subtype check.  Scan the subklass's 2ndary superklass
12340 // array for an instance of the superklass.  Set a hidden internal cache on a
12341 // hit (cache is checked with exposed code in gen_subtype_check()).  Return
12342 // NZ for a miss or zero for a hit.  The encoding ALSO sets flags.
12343 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12344   match(Set result (PartialSubtypeCheck sub super));
12345   effect( KILL rcx, KILL cr );
12346 
12347   ins_cost(1100);  // slightly larger than the next version
12348   format %{ "MOV    EDI,[$sub+Klass::secondary_supers]\n\t"
12349             "MOV    ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12350             "ADD    EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12351             "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12352             "JNE,s  miss\t\t# Missed: EDI not-zero\n\t"
12353             "MOV    [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12354             "XOR    $result,$result\t\t Hit: EDI zero\n\t"
12355      "miss:\t" %}
12356 
12357   opcode(0x1); // Force a XOR of EDI
12358   ins_encode( enc_PartialSubtypeCheck() );
12359   ins_pipe( pipe_slow );
12360 %}
12361 
12362 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12363   match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12364   effect( KILL rcx, KILL result );
12365 
12366   ins_cost(1000);
12367   format %{ "MOV    EDI,[$sub+Klass::secondary_supers]\n\t"
12368             "MOV    ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t"
12369             "ADD    EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12370             "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12371             "JNE,s  miss\t\t# Missed: flags NZ\n\t"
12372             "MOV    [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12373      "miss:\t" %}
12374 
12375   opcode(0x0);  // No need to XOR EDI
12376   ins_encode( enc_PartialSubtypeCheck() );
12377   ins_pipe( pipe_slow );
12378 %}
12379 
12380 // ============================================================================
12381 // Branch Instructions -- short offset versions
12382 //
12383 // These instructions are used to replace jumps of a long offset (the default
12384 // match) with jumps of a shorter offset.  These instructions are all tagged
12385 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12386 // match rules in general matching.  Instead, the ADLC generates a conversion
12387 // method in the MachNode which can be used to do in-place replacement of the
12388 // long variant with the shorter variant.  The compiler will determine if a
12389 // branch can be taken by the is_short_branch_offset() predicate in the machine
12390 // specific code section of the file.
12391 
12392 // Jump Direct - Label defines a relative address from JMP+1
12393 instruct jmpDir_short(label labl) %{
12394   match(Goto);
12395   effect(USE labl);
12396 
12397   ins_cost(300);
12398   format %{ "JMP,s  $labl" %}
12399   size(2);
12400   ins_encode %{
12401     Label* L = $labl$$label;
12402     __ jmpb(*L);
12403   %}
12404   ins_pipe( pipe_jmp );
12405   ins_short_branch(1);
12406 %}
12407 
12408 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12409 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12410   match(If cop cr);
12411   effect(USE labl);
12412 
12413   ins_cost(300);
12414   format %{ "J$cop,s  $labl" %}
12415   size(2);
12416   ins_encode %{
12417     Label* L = $labl$$label;
12418     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12419   %}
12420   ins_pipe( pipe_jcc );
12421   ins_short_branch(1);
12422 %}
12423 
12424 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12425 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12426   match(CountedLoopEnd cop cr);
12427   effect(USE labl);
12428 
12429   ins_cost(300);
12430   format %{ "J$cop,s  $labl\t# Loop end" %}
12431   size(2);
12432   ins_encode %{
12433     Label* L = $labl$$label;
12434     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12435   %}
12436   ins_pipe( pipe_jcc );
12437   ins_short_branch(1);
12438 %}
12439 
12440 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12441 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12442   match(CountedLoopEnd cop cmp);
12443   effect(USE labl);
12444 
12445   ins_cost(300);
12446   format %{ "J$cop,us $labl\t# Loop end" %}
12447   size(2);
12448   ins_encode %{
12449     Label* L = $labl$$label;
12450     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12451   %}
12452   ins_pipe( pipe_jcc );
12453   ins_short_branch(1);
12454 %}
12455 
12456 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12457   match(CountedLoopEnd cop cmp);
12458   effect(USE labl);
12459 
12460   ins_cost(300);
12461   format %{ "J$cop,us $labl\t# Loop end" %}
12462   size(2);
12463   ins_encode %{
12464     Label* L = $labl$$label;
12465     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12466   %}
12467   ins_pipe( pipe_jcc );
12468   ins_short_branch(1);
12469 %}
12470 
12471 // Jump Direct Conditional - using unsigned comparison
12472 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12473   match(If cop cmp);
12474   effect(USE labl);
12475 
12476   ins_cost(300);
12477   format %{ "J$cop,us $labl" %}
12478   size(2);
12479   ins_encode %{
12480     Label* L = $labl$$label;
12481     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12482   %}
12483   ins_pipe( pipe_jcc );
12484   ins_short_branch(1);
12485 %}
12486 
12487 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12488   match(If cop cmp);
12489   effect(USE labl);
12490 
12491   ins_cost(300);
12492   format %{ "J$cop,us $labl" %}
12493   size(2);
12494   ins_encode %{
12495     Label* L = $labl$$label;
12496     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12497   %}
12498   ins_pipe( pipe_jcc );
12499   ins_short_branch(1);
12500 %}
12501 
12502 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12503   match(If cop cmp);
12504   effect(USE labl);
12505 
12506   ins_cost(300);
12507   format %{ $$template
12508     if ($cop$$cmpcode == Assembler::notEqual) {
12509       $$emit$$"JP,u,s   $labl\n\t"
12510       $$emit$$"J$cop,u,s   $labl"
12511     } else {
12512       $$emit$$"JP,u,s   done\n\t"
12513       $$emit$$"J$cop,u,s  $labl\n\t"
12514       $$emit$$"done:"
12515     }
12516   %}
12517   size(4);
12518   ins_encode %{
12519     Label* l = $labl$$label;
12520     if ($cop$$cmpcode == Assembler::notEqual) {
12521       __ jccb(Assembler::parity, *l);
12522       __ jccb(Assembler::notEqual, *l);
12523     } else if ($cop$$cmpcode == Assembler::equal) {
12524       Label done;
12525       __ jccb(Assembler::parity, done);
12526       __ jccb(Assembler::equal, *l);
12527       __ bind(done);
12528     } else {
12529        ShouldNotReachHere();
12530     }
12531   %}
12532   ins_pipe(pipe_jcc);
12533   ins_short_branch(1);
12534 %}
12535 
12536 // ============================================================================
12537 // Long Compare
12538 //
12539 // Currently we hold longs in 2 registers.  Comparing such values efficiently
12540 // is tricky.  The flavor of compare used depends on whether we are testing
12541 // for LT, LE, or EQ.  For a simple LT test we can check just the sign bit.
12542 // The GE test is the negated LT test.  The LE test can be had by commuting
12543 // the operands (yielding a GE test) and then negating; negate again for the
12544 // GT test.  The EQ test is done by ORcc'ing the high and low halves, and the
12545 // NE test is negated from that.
12546 
12547 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12548 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)).  Note the
12549 // difference between 'Y' and '0L'.  The tree-matches for the CmpI sections
12550 // are collapsed internally in the ADLC's dfa-gen code.  The match for
12551 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12552 // foo match ends up with the wrong leaf.  One fix is to not match both
12553 // reg-reg and reg-zero forms of long-compare.  This is unfortunate because
12554 // both forms beat the trinary form of long-compare and both are very useful
12555 // on Intel which has so few registers.
12556 
12557 // Manifest a CmpL result in an integer register.  Very painful.
12558 // This is the test to avoid.
12559 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12560   match(Set dst (CmpL3 src1 src2));
12561   effect( KILL flags );
12562   ins_cost(1000);
12563   format %{ "XOR    $dst,$dst\n\t"
12564             "CMP    $src1.hi,$src2.hi\n\t"
12565             "JLT,s  m_one\n\t"
12566             "JGT,s  p_one\n\t"
12567             "CMP    $src1.lo,$src2.lo\n\t"
12568             "JB,s   m_one\n\t"
12569             "JEQ,s  done\n"
12570     "p_one:\tINC    $dst\n\t"
12571             "JMP,s  done\n"
12572     "m_one:\tDEC    $dst\n"
12573      "done:" %}
12574   ins_encode %{
12575     Label p_one, m_one, done;
12576     __ xorptr($dst$$Register, $dst$$Register);
12577     __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12578     __ jccb(Assembler::less,    m_one);
12579     __ jccb(Assembler::greater, p_one);
12580     __ cmpl($src1$$Register, $src2$$Register);
12581     __ jccb(Assembler::below,   m_one);
12582     __ jccb(Assembler::equal,   done);
12583     __ bind(p_one);
12584     __ incrementl($dst$$Register);
12585     __ jmpb(done);
12586     __ bind(m_one);
12587     __ decrementl($dst$$Register);
12588     __ bind(done);
12589   %}
12590   ins_pipe( pipe_slow );
12591 %}
12592 
12593 //======
12594 // Manifest a CmpL result in the normal flags.  Only good for LT or GE
12595 // compares.  Can be used for LE or GT compares by reversing arguments.
12596 // NOT GOOD FOR EQ/NE tests.
12597 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12598   match( Set flags (CmpL src zero ));
12599   ins_cost(100);
12600   format %{ "TEST   $src.hi,$src.hi" %}
12601   opcode(0x85);
12602   ins_encode( OpcP, RegReg_Hi2( src, src ) );
12603   ins_pipe( ialu_cr_reg_reg );
12604 %}
12605 
12606 // Manifest a CmpL result in the normal flags.  Only good for LT or GE
12607 // compares.  Can be used for LE or GT compares by reversing arguments.
12608 // NOT GOOD FOR EQ/NE tests.
12609 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12610   match( Set flags (CmpL src1 src2 ));
12611   effect( TEMP tmp );
12612   ins_cost(300);
12613   format %{ "CMP    $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12614             "MOV    $tmp,$src1.hi\n\t"
12615             "SBB    $tmp,$src2.hi\t! Compute flags for long compare" %}
12616   ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12617   ins_pipe( ialu_cr_reg_reg );
12618 %}
12619 
12620 // Long compares reg < zero/req OR reg >= zero/req.
12621 // Just a wrapper for a normal branch, plus the predicate test.
12622 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12623   match(If cmp flags);
12624   effect(USE labl);
12625   predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12626   expand %{
12627     jmpCon(cmp,flags,labl);    // JLT or JGE...
12628   %}
12629 %}
12630 
12631 // Compare 2 longs and CMOVE longs.
12632 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12633   match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12634   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12635   ins_cost(400);
12636   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12637             "CMOV$cmp $dst.hi,$src.hi" %}
12638   opcode(0x0F,0x40);
12639   ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12640   ins_pipe( pipe_cmov_reg_long );
12641 %}
12642 
12643 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12644   match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12645   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12646   ins_cost(500);
12647   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12648             "CMOV$cmp $dst.hi,$src.hi" %}
12649   opcode(0x0F,0x40);
12650   ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12651   ins_pipe( pipe_cmov_reg_long );
12652 %}
12653 
12654 // Compare 2 longs and CMOVE ints.
12655 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12656   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12657   match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12658   ins_cost(200);
12659   format %{ "CMOV$cmp $dst,$src" %}
12660   opcode(0x0F,0x40);
12661   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12662   ins_pipe( pipe_cmov_reg );
12663 %}
12664 
12665 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12666   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12667   match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12668   ins_cost(250);
12669   format %{ "CMOV$cmp $dst,$src" %}
12670   opcode(0x0F,0x40);
12671   ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12672   ins_pipe( pipe_cmov_mem );
12673 %}
12674 
12675 // Compare 2 longs and CMOVE ints.
12676 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12677   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12678   match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12679   ins_cost(200);
12680   format %{ "CMOV$cmp $dst,$src" %}
12681   opcode(0x0F,0x40);
12682   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12683   ins_pipe( pipe_cmov_reg );
12684 %}
12685 
12686 // Compare 2 longs and CMOVE doubles
12687 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12688   predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12689   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12690   ins_cost(200);
12691   expand %{
12692     fcmovDPR_regS(cmp,flags,dst,src);
12693   %}
12694 %}
12695 
12696 // Compare 2 longs and CMOVE doubles
12697 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12698   predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12699   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12700   ins_cost(200);
12701   expand %{
12702     fcmovD_regS(cmp,flags,dst,src);
12703   %}
12704 %}
12705 
12706 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12707   predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12708   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12709   ins_cost(200);
12710   expand %{
12711     fcmovFPR_regS(cmp,flags,dst,src);
12712   %}
12713 %}
12714 
12715 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12716   predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12717   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12718   ins_cost(200);
12719   expand %{
12720     fcmovF_regS(cmp,flags,dst,src);
12721   %}
12722 %}
12723 
12724 //======
12725 // Manifest a CmpL result in the normal flags.  Only good for EQ/NE compares.
12726 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12727   match( Set flags (CmpL src zero ));
12728   effect(TEMP tmp);
12729   ins_cost(200);
12730   format %{ "MOV    $tmp,$src.lo\n\t"
12731             "OR     $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12732   ins_encode( long_cmp_flags0( src, tmp ) );
12733   ins_pipe( ialu_reg_reg_long );
12734 %}
12735 
12736 // Manifest a CmpL result in the normal flags.  Only good for EQ/NE compares.
12737 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12738   match( Set flags (CmpL src1 src2 ));
12739   ins_cost(200+300);
12740   format %{ "CMP    $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12741             "JNE,s  skip\n\t"
12742             "CMP    $src1.hi,$src2.hi\n\t"
12743      "skip:\t" %}
12744   ins_encode( long_cmp_flags1( src1, src2 ) );
12745   ins_pipe( ialu_cr_reg_reg );
12746 %}
12747 
12748 // Long compare reg == zero/reg OR reg != zero/reg
12749 // Just a wrapper for a normal branch, plus the predicate test.
12750 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12751   match(If cmp flags);
12752   effect(USE labl);
12753   predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12754   expand %{
12755     jmpCon(cmp,flags,labl);    // JEQ or JNE...
12756   %}
12757 %}
12758 
12759 // Compare 2 longs and CMOVE longs.
12760 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12761   match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12762   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12763   ins_cost(400);
12764   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12765             "CMOV$cmp $dst.hi,$src.hi" %}
12766   opcode(0x0F,0x40);
12767   ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12768   ins_pipe( pipe_cmov_reg_long );
12769 %}
12770 
12771 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12772   match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12773   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12774   ins_cost(500);
12775   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12776             "CMOV$cmp $dst.hi,$src.hi" %}
12777   opcode(0x0F,0x40);
12778   ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12779   ins_pipe( pipe_cmov_reg_long );
12780 %}
12781 
12782 // Compare 2 longs and CMOVE ints.
12783 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12784   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12785   match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12786   ins_cost(200);
12787   format %{ "CMOV$cmp $dst,$src" %}
12788   opcode(0x0F,0x40);
12789   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12790   ins_pipe( pipe_cmov_reg );
12791 %}
12792 
12793 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12794   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12795   match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12796   ins_cost(250);
12797   format %{ "CMOV$cmp $dst,$src" %}
12798   opcode(0x0F,0x40);
12799   ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12800   ins_pipe( pipe_cmov_mem );
12801 %}
12802 
12803 // Compare 2 longs and CMOVE ints.
12804 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12805   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12806   match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12807   ins_cost(200);
12808   format %{ "CMOV$cmp $dst,$src" %}
12809   opcode(0x0F,0x40);
12810   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12811   ins_pipe( pipe_cmov_reg );
12812 %}
12813 
12814 // Compare 2 longs and CMOVE doubles
12815 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12816   predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12817   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12818   ins_cost(200);
12819   expand %{
12820     fcmovDPR_regS(cmp,flags,dst,src);
12821   %}
12822 %}
12823 
12824 // Compare 2 longs and CMOVE doubles
12825 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12826   predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12827   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12828   ins_cost(200);
12829   expand %{
12830     fcmovD_regS(cmp,flags,dst,src);
12831   %}
12832 %}
12833 
12834 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12835   predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12836   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12837   ins_cost(200);
12838   expand %{
12839     fcmovFPR_regS(cmp,flags,dst,src);
12840   %}
12841 %}
12842 
12843 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12844   predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12845   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12846   ins_cost(200);
12847   expand %{
12848     fcmovF_regS(cmp,flags,dst,src);
12849   %}
12850 %}
12851 
12852 //======
12853 // Manifest a CmpL result in the normal flags.  Only good for LE or GT compares.
12854 // Same as cmpL_reg_flags_LEGT except must negate src
12855 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12856   match( Set flags (CmpL src zero ));
12857   effect( TEMP tmp );
12858   ins_cost(300);
12859   format %{ "XOR    $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12860             "CMP    $tmp,$src.lo\n\t"
12861             "SBB    $tmp,$src.hi\n\t" %}
12862   ins_encode( long_cmp_flags3(src, tmp) );
12863   ins_pipe( ialu_reg_reg_long );
12864 %}
12865 
12866 // Manifest a CmpL result in the normal flags.  Only good for LE or GT compares.
12867 // Same as cmpL_reg_flags_LTGE except operands swapped.  Swapping operands
12868 // requires a commuted test to get the same result.
12869 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12870   match( Set flags (CmpL src1 src2 ));
12871   effect( TEMP tmp );
12872   ins_cost(300);
12873   format %{ "CMP    $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12874             "MOV    $tmp,$src2.hi\n\t"
12875             "SBB    $tmp,$src1.hi\t! Compute flags for long compare" %}
12876   ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12877   ins_pipe( ialu_cr_reg_reg );
12878 %}
12879 
12880 // Long compares reg < zero/req OR reg >= zero/req.
12881 // Just a wrapper for a normal branch, plus the predicate test
12882 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12883   match(If cmp flags);
12884   effect(USE labl);
12885   predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12886   ins_cost(300);
12887   expand %{
12888     jmpCon(cmp,flags,labl);    // JGT or JLE...
12889   %}
12890 %}
12891 
12892 // Compare 2 longs and CMOVE longs.
12893 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12894   match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12895   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12896   ins_cost(400);
12897   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12898             "CMOV$cmp $dst.hi,$src.hi" %}
12899   opcode(0x0F,0x40);
12900   ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12901   ins_pipe( pipe_cmov_reg_long );
12902 %}
12903 
12904 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12905   match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12906   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12907   ins_cost(500);
12908   format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12909             "CMOV$cmp $dst.hi,$src.hi+4" %}
12910   opcode(0x0F,0x40);
12911   ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12912   ins_pipe( pipe_cmov_reg_long );
12913 %}
12914 
12915 // Compare 2 longs and CMOVE ints.
12916 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12917   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12918   match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12919   ins_cost(200);
12920   format %{ "CMOV$cmp $dst,$src" %}
12921   opcode(0x0F,0x40);
12922   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12923   ins_pipe( pipe_cmov_reg );
12924 %}
12925 
12926 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12927   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12928   match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12929   ins_cost(250);
12930   format %{ "CMOV$cmp $dst,$src" %}
12931   opcode(0x0F,0x40);
12932   ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12933   ins_pipe( pipe_cmov_mem );
12934 %}
12935 
12936 // Compare 2 longs and CMOVE ptrs.
12937 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12938   predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12939   match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12940   ins_cost(200);
12941   format %{ "CMOV$cmp $dst,$src" %}
12942   opcode(0x0F,0x40);
12943   ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12944   ins_pipe( pipe_cmov_reg );
12945 %}
12946 
12947 // Compare 2 longs and CMOVE doubles
12948 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12949   predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12950   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12951   ins_cost(200);
12952   expand %{
12953     fcmovDPR_regS(cmp,flags,dst,src);
12954   %}
12955 %}
12956 
12957 // Compare 2 longs and CMOVE doubles
12958 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12959   predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12960   match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12961   ins_cost(200);
12962   expand %{
12963     fcmovD_regS(cmp,flags,dst,src);
12964   %}
12965 %}
12966 
12967 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12968   predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12969   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12970   ins_cost(200);
12971   expand %{
12972     fcmovFPR_regS(cmp,flags,dst,src);
12973   %}
12974 %}
12975 
12976 
12977 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12978   predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12979   match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12980   ins_cost(200);
12981   expand %{
12982     fcmovF_regS(cmp,flags,dst,src);
12983   %}
12984 %}
12985 
12986 
12987 // ============================================================================
12988 // Procedure Call/Return Instructions
12989 // Call Java Static Instruction
12990 // Note: If this code changes, the corresponding ret_addr_offset() and
12991 //       compute_padding() functions will have to be adjusted.
12992 instruct CallStaticJavaDirect(method meth) %{
12993   match(CallStaticJava);
12994   predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12995   effect(USE meth);
12996 
12997   ins_cost(300);
12998   format %{ "CALL,static " %}
12999   opcode(0xE8); /* E8 cd */
13000   ins_encode( pre_call_resets,
13001               Java_Static_Call( meth ),
13002               call_epilog,
13003               post_call_FPU );
13004   ins_pipe( pipe_slow );
13005   ins_alignment(4);
13006 %}
13007 
13008 // Call Java Static Instruction (method handle version)
13009 // Note: If this code changes, the corresponding ret_addr_offset() and
13010 //       compute_padding() functions will have to be adjusted.
13011 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
13012   match(CallStaticJava);
13013   predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13014   effect(USE meth);
13015   // EBP is saved by all callees (for interpreter stack correction).
13016   // We use it here for a similar purpose, in {preserve,restore}_SP.
13017 
13018   ins_cost(300);
13019   format %{ "CALL,static/MethodHandle " %}
13020   opcode(0xE8); /* E8 cd */
13021   ins_encode( pre_call_resets,
13022               preserve_SP,
13023               Java_Static_Call( meth ),
13024               restore_SP,
13025               call_epilog,
13026               post_call_FPU );
13027   ins_pipe( pipe_slow );
13028   ins_alignment(4);
13029 %}
13030 
13031 // Call Java Dynamic Instruction
13032 // Note: If this code changes, the corresponding ret_addr_offset() and
13033 //       compute_padding() functions will have to be adjusted.
13034 instruct CallDynamicJavaDirect(method meth) %{
13035   match(CallDynamicJava);
13036   effect(USE meth);
13037 
13038   ins_cost(300);
13039   format %{ "MOV    EAX,(oop)-1\n\t"
13040             "CALL,dynamic" %}
13041   opcode(0xE8); /* E8 cd */
13042   ins_encode( pre_call_resets,
13043               Java_Dynamic_Call( meth ),
13044               call_epilog,
13045               post_call_FPU );
13046   ins_pipe( pipe_slow );
13047   ins_alignment(4);
13048 %}
13049 
13050 // Call Runtime Instruction
13051 instruct CallRuntimeDirect(method meth) %{
13052   match(CallRuntime );
13053   effect(USE meth);
13054 
13055   ins_cost(300);
13056   format %{ "CALL,runtime " %}
13057   opcode(0xE8); /* E8 cd */
13058   // Use FFREEs to clear entries in float stack
13059   ins_encode( pre_call_resets,
13060               FFree_Float_Stack_All,
13061               Java_To_Runtime( meth ),
13062               post_call_FPU );
13063   ins_pipe( pipe_slow );
13064 %}
13065 
13066 // Call runtime without safepoint
13067 instruct CallLeafDirect(method meth) %{
13068   match(CallLeaf);
13069   effect(USE meth);
13070 
13071   ins_cost(300);
13072   format %{ "CALL_LEAF,runtime " %}
13073   opcode(0xE8); /* E8 cd */
13074   ins_encode( pre_call_resets,
13075               FFree_Float_Stack_All,
13076               Java_To_Runtime( meth ),
13077               Verify_FPU_For_Leaf, post_call_FPU );
13078   ins_pipe( pipe_slow );
13079 %}
13080 
13081 instruct CallLeafNoFPDirect(method meth) %{
13082   match(CallLeafNoFP);
13083   effect(USE meth);
13084 
13085   ins_cost(300);
13086   format %{ "CALL_LEAF_NOFP,runtime " %}
13087   opcode(0xE8); /* E8 cd */
13088   ins_encode(Java_To_Runtime(meth));
13089   ins_pipe( pipe_slow );
13090 %}
13091 
13092 
13093 // Return Instruction
13094 // Remove the return address & jump to it.
13095 instruct Ret() %{
13096   match(Return);
13097   format %{ "RET" %}
13098   opcode(0xC3);
13099   ins_encode(OpcP);
13100   ins_pipe( pipe_jmp );
13101 %}
13102 
13103 // Tail Call; Jump from runtime stub to Java code.
13104 // Also known as an 'interprocedural jump'.
13105 // Target of jump will eventually return to caller.
13106 // TailJump below removes the return address.
13107 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13108   match(TailCall jump_target method_oop );
13109   ins_cost(300);
13110   format %{ "JMP    $jump_target \t# EBX holds method oop" %}
13111   opcode(0xFF, 0x4);  /* Opcode FF /4 */
13112   ins_encode( OpcP, RegOpc(jump_target) );
13113   ins_pipe( pipe_jmp );
13114 %}
13115 
13116 
13117 // Tail Jump; remove the return address; jump to target.
13118 // TailCall above leaves the return address around.
13119 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13120   match( TailJump jump_target ex_oop );
13121   ins_cost(300);
13122   format %{ "POP    EDX\t# pop return address into dummy\n\t"
13123             "JMP    $jump_target " %}
13124   opcode(0xFF, 0x4);  /* Opcode FF /4 */
13125   ins_encode( enc_pop_rdx,
13126               OpcP, RegOpc(jump_target) );
13127   ins_pipe( pipe_jmp );
13128 %}
13129 
13130 // Create exception oop: created by stack-crawling runtime code.
13131 // Created exception is now available to this handler, and is setup
13132 // just prior to jumping to this handler.  No code emitted.
13133 instruct CreateException( eAXRegP ex_oop )
13134 %{
13135   match(Set ex_oop (CreateEx));
13136 
13137   size(0);
13138   // use the following format syntax
13139   format %{ "# exception oop is in EAX; no code emitted" %}
13140   ins_encode();
13141   ins_pipe( empty );
13142 %}
13143 
13144 
13145 // Rethrow exception:
13146 // The exception oop will come in the first argument position.
13147 // Then JUMP (not call) to the rethrow stub code.
13148 instruct RethrowException()
13149 %{
13150   match(Rethrow);
13151 
13152   // use the following format syntax
13153   format %{ "JMP    rethrow_stub" %}
13154   ins_encode(enc_rethrow);
13155   ins_pipe( pipe_jmp );
13156 %}
13157 
13158 // inlined locking and unlocking
13159 
13160 
13161 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
13162   match( Set cr (FastLock object box) );
13163   effect( TEMP tmp, TEMP scr, USE_KILL box );
13164   ins_cost(300);
13165   format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
13166   ins_encode( Fast_Lock(object,box,tmp,scr) );
13167   ins_pipe( pipe_slow );


13168 %}
13169 
13170 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13171   match( Set cr (FastUnlock object box) );
13172   effect( TEMP tmp, USE_KILL box );
13173   ins_cost(300);
13174   format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
13175   ins_encode( Fast_Unlock(object,box,tmp) );
13176   ins_pipe( pipe_slow );


13177 %}
13178 
13179 
13180 
13181 // ============================================================================
13182 // Safepoint Instruction
13183 instruct safePoint_poll(eFlagsReg cr) %{
13184   match(SafePoint);
13185   effect(KILL cr);
13186 
13187   // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13188   // On SPARC that might be acceptable as we can generate the address with
13189   // just a sethi, saving an or.  By polling at offset 0 we can end up
13190   // putting additional pressure on the index-0 in the D$.  Because of
13191   // alignment (just like the situation at hand) the lower indices tend
13192   // to see more traffic.  It'd be better to change the polling address
13193   // to offset 0 of the last $line in the polling page.
13194 
13195   format %{ "TSTL   #polladdr,EAX\t! Safepoint: poll for GC" %}
13196   ins_cost(125);
13197   size(6) ;
13198   ins_encode( Safepoint_Poll() );
13199   ins_pipe( ialu_reg_mem );
13200 %}
13201 
13202 
13203 // ============================================================================
13204 // This name is KNOWN by the ADLC and cannot be changed.
13205 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13206 // for this guy.
13207 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13208   match(Set dst (ThreadLocal));
13209   effect(DEF dst, KILL cr);
13210 
13211   format %{ "MOV    $dst, Thread::current()" %}
13212   ins_encode %{
13213     Register dstReg = as_Register($dst$$reg);
13214     __ get_thread(dstReg);
13215   %}
13216   ins_pipe( ialu_reg_fat );
13217 %}
13218 
13219 
13220 
13221 //----------PEEPHOLE RULES-----------------------------------------------------
13222 // These must follow all instruction definitions as they use the names
13223 // defined in the instructions definitions.
13224 //
13225 // peepmatch ( root_instr_name [preceding_instruction]* );
13226 //
13227 // peepconstraint %{
13228 // (instruction_number.operand_name relational_op instruction_number.operand_name
13229 //  [, ...] );
13230 // // instruction numbers are zero-based using left to right order in peepmatch
13231 //
13232 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
13233 // // provide an instruction_number.operand_name for each operand that appears
13234 // // in the replacement instruction's match rule
13235 //
13236 // ---------VM FLAGS---------------------------------------------------------
13237 //
13238 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13239 //
13240 // Each peephole rule is given an identifying number starting with zero and
13241 // increasing by one in the order seen by the parser.  An individual peephole
13242 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13243 // on the command-line.
13244 //
13245 // ---------CURRENT LIMITATIONS----------------------------------------------
13246 //
13247 // Only match adjacent instructions in same basic block
13248 // Only equality constraints
13249 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13250 // Only one replacement instruction
13251 //
13252 // ---------EXAMPLE----------------------------------------------------------
13253 //
13254 // // pertinent parts of existing instructions in architecture description
13255 // instruct movI(rRegI dst, rRegI src) %{
13256 //   match(Set dst (CopyI src));
13257 // %}
13258 //
13259 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13260 //   match(Set dst (AddI dst src));
13261 //   effect(KILL cr);
13262 // %}
13263 //
13264 // // Change (inc mov) to lea
13265 // peephole %{
13266 //   // increment preceeded by register-register move
13267 //   peepmatch ( incI_eReg movI );
13268 //   // require that the destination register of the increment
13269 //   // match the destination register of the move
13270 //   peepconstraint ( 0.dst == 1.dst );
13271 //   // construct a replacement instruction that sets
13272 //   // the destination to ( move's source register + one )
13273 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13274 // %}
13275 //
13276 // Implementation no longer uses movX instructions since
13277 // machine-independent system no longer uses CopyX nodes.
13278 //
13279 // peephole %{
13280 //   peepmatch ( incI_eReg movI );
13281 //   peepconstraint ( 0.dst == 1.dst );
13282 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13283 // %}
13284 //
13285 // peephole %{
13286 //   peepmatch ( decI_eReg movI );
13287 //   peepconstraint ( 0.dst == 1.dst );
13288 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13289 // %}
13290 //
13291 // peephole %{
13292 //   peepmatch ( addI_eReg_imm movI );
13293 //   peepconstraint ( 0.dst == 1.dst );
13294 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13295 // %}
13296 //
13297 // peephole %{
13298 //   peepmatch ( addP_eReg_imm movP );
13299 //   peepconstraint ( 0.dst == 1.dst );
13300 //   peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13301 // %}
13302 
13303 // // Change load of spilled value to only a spill
13304 // instruct storeI(memory mem, rRegI src) %{
13305 //   match(Set mem (StoreI mem src));
13306 // %}
13307 //
13308 // instruct loadI(rRegI dst, memory mem) %{
13309 //   match(Set dst (LoadI mem));
13310 // %}
13311 //
13312 peephole %{
13313   peepmatch ( loadI storeI );
13314   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13315   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13316 %}
13317 
13318 //----------SMARTSPILL RULES---------------------------------------------------
13319 // These must follow all instruction definitions as they use the names
13320 // defined in the instructions definitions.
--- EOF ---