1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
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23 */
24
25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
27
28 #include "asm/register.hpp"
29
30 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
31 // level; i.e., what you write
32 // is what you get. The Assembler is generating code into a CodeBuffer.
33
34 class Assembler : public AbstractAssembler {
35 friend class AbstractAssembler;
36 friend class AddressLiteral;
37
38 // code patchers need various routines like inv_wdisp()
39 friend class NativeInstruction;
40 friend class NativeGeneralJump;
41 friend class Relocation;
42 friend class Label;
43
44 public:
45 // op carries format info; see page 62 & 267
46
47 enum ops {
48 call_op = 1, // fmt 1
49 branch_op = 0, // also sethi (fmt2)
50 arith_op = 2, // fmt 3, arith & misc
51 ldst_op = 3 // fmt 3, load/store
52 };
53
54 enum op2s {
55 bpr_op2 = 3,
56 fb_op2 = 6,
57 fbp_op2 = 5,
58 br_op2 = 2,
59 bp_op2 = 1,
60 sethi_op2 = 4
61 };
62
63 enum op3s {
64 // selected op3s
65 add_op3 = 0x00,
66 and_op3 = 0x01,
67 or_op3 = 0x02,
68 xor_op3 = 0x03,
69 sub_op3 = 0x04,
70 andn_op3 = 0x05,
71 orn_op3 = 0x06,
72 xnor_op3 = 0x07,
73 addc_op3 = 0x08,
74 mulx_op3 = 0x09,
75 umul_op3 = 0x0a,
76 smul_op3 = 0x0b,
77 subc_op3 = 0x0c,
78 udivx_op3 = 0x0d,
79 udiv_op3 = 0x0e,
80 sdiv_op3 = 0x0f,
81
82 addcc_op3 = 0x10,
83 andcc_op3 = 0x11,
84 orcc_op3 = 0x12,
85 xorcc_op3 = 0x13,
86 subcc_op3 = 0x14,
87 andncc_op3 = 0x15,
88 orncc_op3 = 0x16,
89 xnorcc_op3 = 0x17,
90 addccc_op3 = 0x18,
91 aes4_op3 = 0x19,
92 umulcc_op3 = 0x1a,
93 smulcc_op3 = 0x1b,
94 subccc_op3 = 0x1c,
95 udivcc_op3 = 0x1e,
96 sdivcc_op3 = 0x1f,
97
98 taddcc_op3 = 0x20,
99 tsubcc_op3 = 0x21,
100 taddcctv_op3 = 0x22,
101 tsubcctv_op3 = 0x23,
102 mulscc_op3 = 0x24,
103 sll_op3 = 0x25,
104 sllx_op3 = 0x25,
105 srl_op3 = 0x26,
106 srlx_op3 = 0x26,
107 sra_op3 = 0x27,
108 srax_op3 = 0x27,
109 rdreg_op3 = 0x28,
110 membar_op3 = 0x28,
111
112 flushw_op3 = 0x2b,
113 movcc_op3 = 0x2c,
114 sdivx_op3 = 0x2d,
115 popc_op3 = 0x2e,
116 movr_op3 = 0x2f,
117
118 sir_op3 = 0x30,
119 wrreg_op3 = 0x30,
120 saved_op3 = 0x31,
121
122 fpop1_op3 = 0x34,
123 fpop2_op3 = 0x35,
124 impdep1_op3 = 0x36,
125 aes3_op3 = 0x36,
126 alignaddr_op3 = 0x36,
127 faligndata_op3 = 0x36,
128 flog3_op3 = 0x36,
129 edge_op3 = 0x36,
130 fsrc_op3 = 0x36,
131 impdep2_op3 = 0x37,
132 stpartialf_op3 = 0x37,
133 jmpl_op3 = 0x38,
134 rett_op3 = 0x39,
135 trap_op3 = 0x3a,
136 flush_op3 = 0x3b,
137 save_op3 = 0x3c,
138 restore_op3 = 0x3d,
139 done_op3 = 0x3e,
140 retry_op3 = 0x3e,
141
142 lduw_op3 = 0x00,
143 ldub_op3 = 0x01,
144 lduh_op3 = 0x02,
145 ldd_op3 = 0x03,
146 stw_op3 = 0x04,
147 stb_op3 = 0x05,
148 sth_op3 = 0x06,
149 std_op3 = 0x07,
150 ldsw_op3 = 0x08,
151 ldsb_op3 = 0x09,
152 ldsh_op3 = 0x0a,
153 ldx_op3 = 0x0b,
154
155 stx_op3 = 0x0e,
156 swap_op3 = 0x0f,
157
158 stwa_op3 = 0x14,
159 stxa_op3 = 0x1e,
160
161 ldf_op3 = 0x20,
162 ldfsr_op3 = 0x21,
163 ldqf_op3 = 0x22,
164 lddf_op3 = 0x23,
165 stf_op3 = 0x24,
166 stfsr_op3 = 0x25,
167 stqf_op3 = 0x26,
168 stdf_op3 = 0x27,
169
170 prefetch_op3 = 0x2d,
171
172 casa_op3 = 0x3c,
173 casxa_op3 = 0x3e,
174
175 mftoi_op3 = 0x36,
176
177 alt_bit_op3 = 0x10,
178 cc_bit_op3 = 0x10
179 };
180
181 enum opfs {
182 // selected opfs
183 edge8n_opf = 0x01,
184
185 fmovs_opf = 0x01,
186 fmovd_opf = 0x02,
187
188 fnegs_opf = 0x05,
189 fnegd_opf = 0x06,
190
191 alignaddr_opf = 0x18,
192
193 fadds_opf = 0x41,
194 faddd_opf = 0x42,
195 fsubs_opf = 0x45,
196 fsubd_opf = 0x46,
197
198 faligndata_opf = 0x48,
199
200 fmuls_opf = 0x49,
201 fmuld_opf = 0x4a,
202 fdivs_opf = 0x4d,
203 fdivd_opf = 0x4e,
204
205 fcmps_opf = 0x51,
206 fcmpd_opf = 0x52,
207
208 fstox_opf = 0x81,
209 fdtox_opf = 0x82,
210 fxtos_opf = 0x84,
211 fxtod_opf = 0x88,
212 fitos_opf = 0xc4,
213 fdtos_opf = 0xc6,
214 fitod_opf = 0xc8,
215 fstod_opf = 0xc9,
216 fstoi_opf = 0xd1,
217 fdtoi_opf = 0xd2,
218
219 mdtox_opf = 0x110,
220 mstouw_opf = 0x111,
221 mstosw_opf = 0x113,
222 mxtod_opf = 0x118,
223 mwtos_opf = 0x119,
224
225 aes_kexpand0_opf = 0x130,
226 aes_kexpand2_opf = 0x131
227 };
228
229 enum op5s {
230 aes_eround01_op5 = 0x00,
231 aes_eround23_op5 = 0x01,
232 aes_dround01_op5 = 0x02,
233 aes_dround23_op5 = 0x03,
234 aes_eround01_l_op5 = 0x04,
235 aes_eround23_l_op5 = 0x05,
236 aes_dround01_l_op5 = 0x06,
237 aes_dround23_l_op5 = 0x07,
238 aes_kexpand1_op5 = 0x08
239 };
240
241 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
242
243 enum Condition {
244 // for FBfcc & FBPfcc instruction
245 f_never = 0,
246 f_notEqual = 1,
247 f_notZero = 1,
248 f_lessOrGreater = 2,
249 f_unorderedOrLess = 3,
250 f_less = 4,
251 f_unorderedOrGreater = 5,
252 f_greater = 6,
253 f_unordered = 7,
254 f_always = 8,
255 f_equal = 9,
256 f_zero = 9,
257 f_unorderedOrEqual = 10,
258 f_greaterOrEqual = 11,
259 f_unorderedOrGreaterOrEqual = 12,
260 f_lessOrEqual = 13,
261 f_unorderedOrLessOrEqual = 14,
262 f_ordered = 15,
263
264 // V8 coproc, pp 123 v8 manual
265
266 cp_always = 8,
267 cp_never = 0,
268 cp_3 = 7,
269 cp_2 = 6,
270 cp_2or3 = 5,
271 cp_1 = 4,
272 cp_1or3 = 3,
273 cp_1or2 = 2,
274 cp_1or2or3 = 1,
275 cp_0 = 9,
276 cp_0or3 = 10,
277 cp_0or2 = 11,
278 cp_0or2or3 = 12,
279 cp_0or1 = 13,
280 cp_0or1or3 = 14,
281 cp_0or1or2 = 15,
282
283
284 // for integers
285
286 never = 0,
287 equal = 1,
288 zero = 1,
289 lessEqual = 2,
290 less = 3,
291 lessEqualUnsigned = 4,
292 lessUnsigned = 5,
293 carrySet = 5,
294 negative = 6,
295 overflowSet = 7,
296 always = 8,
297 notEqual = 9,
298 notZero = 9,
299 greater = 10,
300 greaterEqual = 11,
301 greaterUnsigned = 12,
302 greaterEqualUnsigned = 13,
303 carryClear = 13,
304 positive = 14,
305 overflowClear = 15
306 };
307
308 enum CC {
309 icc = 0, xcc = 2,
310 // ptr_cc is the correct condition code for a pointer or intptr_t:
311 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
312 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
313 };
314
315 enum PrefetchFcn {
316 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
317 };
318
319 public:
320 // Helper functions for groups of instructions
321
322 enum Predict { pt = 1, pn = 0 }; // pt = predict taken
323
324 enum Membar_mask_bits { // page 184, v9
325 StoreStore = 1 << 3,
326 LoadStore = 1 << 2,
327 StoreLoad = 1 << 1,
328 LoadLoad = 1 << 0,
329
330 Sync = 1 << 6,
331 MemIssue = 1 << 5,
332 Lookaside = 1 << 4
333 };
334
335 static bool is_in_wdisp_range(address a, address b, int nbits) {
336 intptr_t d = intptr_t(b) - intptr_t(a);
337 return is_simm(d, nbits + 2);
338 }
339
340 address target_distance(Label& L) {
341 // Assembler::target(L) should be called only when
342 // a branch instruction is emitted since non-bound
343 // labels record current pc() as a branch address.
344 if (L.is_bound()) return target(L);
345 // Return current address for non-bound labels.
346 return pc();
347 }
348
349 // test if label is in simm16 range in words (wdisp16).
350 bool is_in_wdisp16_range(Label& L) {
351 return is_in_wdisp_range(target_distance(L), pc(), 16);
352 }
353 // test if the distance between two addresses fits in simm30 range in words
354 static bool is_in_wdisp30_range(address a, address b) {
355 return is_in_wdisp_range(a, b, 30);
356 }
357
358 enum ASIs { // page 72, v9
359 ASI_PRIMARY = 0x80,
360 ASI_PRIMARY_NOFAULT = 0x82,
361 ASI_PRIMARY_LITTLE = 0x88,
362 // 8x8-bit partial store
363 ASI_PST8_PRIMARY = 0xC0,
364 // Block initializing store
365 ASI_ST_BLKINIT_PRIMARY = 0xE2,
366 // Most-Recently-Used (MRU) BIS variant
367 ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2
368 // add more from book as needed
369 };
370
371 protected:
372 // helpers
373
374 // x is supposed to fit in a field "nbits" wide
375 // and be sign-extended. Check the range.
376
377 static void assert_signed_range(intptr_t x, int nbits) {
378 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)),
379 err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits));
380 }
381
382 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
383 assert( (x & 3) == 0, "not word aligned");
384 assert_signed_range(x, nbits + 2);
385 }
386
387 static void assert_unsigned_const(int x, int nbits) {
388 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
389 }
390
391 // fields: note bits numbered from LSB = 0,
392 // fields known by inclusive bit range
393
394 static int fmask(juint hi_bit, juint lo_bit) {
395 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
396 return (1 << ( hi_bit-lo_bit + 1 )) - 1;
397 }
398
399 // inverse of u_field
400
401 static int inv_u_field(int x, int hi_bit, int lo_bit) {
402 juint r = juint(x) >> lo_bit;
403 r &= fmask( hi_bit, lo_bit);
404 return int(r);
405 }
406
407
408 // signed version: extract from field and sign-extend
409
410 static int inv_s_field(int x, int hi_bit, int lo_bit) {
411 int sign_shift = 31 - hi_bit;
412 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
413 }
414
415 // given a field that ranges from hi_bit to lo_bit (inclusive,
416 // LSB = 0), and an unsigned value for the field,
417 // shift it into the field
418
419 #ifdef ASSERT
420 static int u_field(int x, int hi_bit, int lo_bit) {
421 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
422 "value out of range");
423 int r = x << lo_bit;
424 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
425 return r;
426 }
427 #else
428 // make sure this is inlined as it will reduce code size significantly
429 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
430 #endif
431
432 static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
433 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
434 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
435 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
436
437 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
438
439 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
440 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
441 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
442
443 static int op( int x) { return u_field(x, 31, 30); }
444 static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
445 static int fcn( int x) { return u_field(x, 29, 25); }
446 static int op3( int x) { return u_field(x, 24, 19); }
447 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
448 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
449 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
450 static int cond( int x) { return u_field(x, 28, 25); }
451 static int cond_mov( int x) { return u_field(x, 17, 14); }
452 static int rcond( RCondition x) { return u_field(x, 12, 10); }
453 static int op2( int x) { return u_field(x, 24, 22); }
454 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
455 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
456 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
457 static int imm_asi( int x) { return u_field(x, 12, 5); }
458 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
459 static int opf_low6( int w) { return u_field(w, 10, 5); }
460 static int opf_low5( int w) { return u_field(w, 9, 5); }
461 static int op5( int x) { return u_field(x, 8, 5); }
462 static int trapcc( CC cc) { return u_field(cc, 12, 11); }
463 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
464 static int opf( int x) { return u_field(x, 13, 5); }
465
466 static bool is_cbcond( int x ) {
467 return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
468 inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
469 }
470 static bool is_cxb( int x ) {
471 assert(is_cbcond(x), "wrong instruction");
472 return (x & (1<<21)) != 0;
473 }
474 static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
475 static int inv_cond_cbcond(int x) {
476 assert(is_cbcond(x), "wrong instruction");
477 return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
478 }
479
480 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
481 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
482
483 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
484 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
485 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
486 static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
487
488 // some float instructions use this encoding on the op3 field
489 static int alt_op3(int op, FloatRegisterImpl::Width w) {
490 int r;
491 switch(w) {
492 case FloatRegisterImpl::S: r = op + 0; break;
493 case FloatRegisterImpl::D: r = op + 3; break;
494 case FloatRegisterImpl::Q: r = op + 2; break;
495 default: ShouldNotReachHere(); break;
496 }
497 return op3(r);
498 }
499
500
501 // compute inverse of simm
502 static int inv_simm(int x, int nbits) {
503 return (int)(x << (32 - nbits)) >> (32 - nbits);
504 }
505
506 static int inv_simm13( int x ) { return inv_simm(x, 13); }
507
508 // signed immediate, in low bits, nbits long
509 static int simm(int x, int nbits) {
510 assert_signed_range(x, nbits);
511 return x & (( 1 << nbits ) - 1);
512 }
513
514 // compute inverse of wdisp16
515 static intptr_t inv_wdisp16(int x, intptr_t pos) {
516 int lo = x & (( 1 << 14 ) - 1);
517 int hi = (x >> 20) & 3;
518 if (hi >= 2) hi |= ~1;
519 return (((hi << 14) | lo) << 2) + pos;
520 }
521
522 // word offset, 14 bits at LSend, 2 bits at B21, B20
523 static int wdisp16(intptr_t x, intptr_t off) {
524 intptr_t xx = x - off;
525 assert_signed_word_disp_range(xx, 16);
526 int r = (xx >> 2) & ((1 << 14) - 1)
527 | ( ( (xx>>(2+14)) & 3 ) << 20 );
528 assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
529 return r;
530 }
531
532 // compute inverse of wdisp10
533 static intptr_t inv_wdisp10(int x, intptr_t pos) {
534 assert(is_cbcond(x), "wrong instruction");
535 int lo = inv_u_field(x, 12, 5);
536 int hi = (x >> 19) & 3;
537 if (hi >= 2) hi |= ~1;
538 return (((hi << 8) | lo) << 2) + pos;
539 }
540
541 // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
542 static int wdisp10(intptr_t x, intptr_t off) {
543 assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
544 intptr_t xx = x - off;
545 assert_signed_word_disp_range(xx, 10);
546 int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 )
547 | ( ( (xx >> (2+8)) & 3 ) << 19 );
548 // Have to fake cbcond instruction to pass assert in inv_wdisp10()
549 assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse");
550 return r;
551 }
552
553 // word displacement in low-order nbits bits
554
555 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
556 int pre_sign_extend = x & (( 1 << nbits ) - 1);
557 int r = pre_sign_extend >= ( 1 << (nbits-1) )
558 ? pre_sign_extend | ~(( 1 << nbits ) - 1)
559 : pre_sign_extend;
560 return (r << 2) + pos;
561 }
562
563 static int wdisp( intptr_t x, intptr_t off, int nbits ) {
564 intptr_t xx = x - off;
565 assert_signed_word_disp_range(xx, nbits);
566 int r = (xx >> 2) & (( 1 << nbits ) - 1);
567 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
568 return r;
569 }
570
571
572 // Extract the top 32 bits in a 64 bit word
573 static int32_t hi32( int64_t x ) {
574 int32_t r = int32_t( (uint64_t)x >> 32 );
575 return r;
576 }
577
578 // given a sethi instruction, extract the constant, left-justified
579 static int inv_hi22( int x ) {
580 return x << 10;
581 }
582
583 // create an imm22 field, given a 32-bit left-justified constant
584 static int hi22( int x ) {
585 int r = int( juint(x) >> 10 );
586 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
587 return r;
588 }
589
590 // create a low10 __value__ (not a field) for a given a 32-bit constant
591 static int low10( int x ) {
592 return x & ((1 << 10) - 1);
593 }
594
595 // AES crypto instructions supported only on certain processors
596 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
597
598 // instruction only in VIS1
599 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
600
601 // instruction only in VIS2
602 static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
603
604 // instruction only in VIS3
605 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
606
607 // instruction only in v9
608 static void v9_only() { } // do nothing
609
610 // instruction deprecated in v9
611 static void v9_dep() { } // do nothing for now
612
613 // v8 has no CC field
614 static void v8_no_cc(CC cc) { if (cc) v9_only(); }
615
616 protected:
617 // Simple delay-slot scheme:
618 // In order to check the programmer, the assembler keeps track of deley slots.
619 // It forbids CTIs in delay slots (conservative, but should be OK).
620 // Also, when putting an instruction into a delay slot, you must say
621 // asm->delayed()->add(...), in order to check that you don't omit
622 // delay-slot instructions.
623 // To implement this, we use a simple FSA
624
625 #ifdef ASSERT
626 #define CHECK_DELAY
627 #endif
628 #ifdef CHECK_DELAY
629 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
630 #endif
631
632 public:
633 // Tells assembler next instruction must NOT be in delay slot.
634 // Use at start of multinstruction macros.
635 void assert_not_delayed() {
636 // This is a separate overloading to avoid creation of string constants
637 // in non-asserted code--with some compilers this pollutes the object code.
638 #ifdef CHECK_DELAY
639 assert_not_delayed("next instruction should not be a delay slot");
640 #endif
641 }
642 void assert_not_delayed(const char* msg) {
643 #ifdef CHECK_DELAY
644 assert(delay_state == no_delay, msg);
645 #endif
646 }
647
648 protected:
649 // Insert a nop if the previous is cbcond
650 void insert_nop_after_cbcond() {
651 if (UseCBCond && cbcond_before()) {
652 nop();
653 }
654 }
655 // Delay slot helpers
656 // cti is called when emitting control-transfer instruction,
657 // BEFORE doing the emitting.
658 // Only effective when assertion-checking is enabled.
659 void cti() {
660 // A cbcond instruction immediately followed by a CTI
661 // instruction introduces pipeline stalls, we need to avoid that.
662 no_cbcond_before();
663 #ifdef CHECK_DELAY
664 assert_not_delayed("cti should not be in delay slot");
665 #endif
666 }
667
668 // called when emitting cti with a delay slot, AFTER emitting
669 void has_delay_slot() {
670 #ifdef CHECK_DELAY
671 assert_not_delayed("just checking");
672 delay_state = at_delay_slot;
673 #endif
674 }
675
676 // cbcond instruction should not be generated one after an other
677 bool cbcond_before() {
678 if (offset() == 0) return false; // it is first instruction
679 int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
680 return is_cbcond(x);
681 }
682
683 void no_cbcond_before() {
684 assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
685 }
686 public:
687
688 bool use_cbcond(Label& L) {
689 if (!UseCBCond || cbcond_before()) return false;
690 intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
691 assert( (x & 3) == 0, "not word aligned");
692 return is_simm12(x);
693 }
694
695 // Tells assembler you know that next instruction is delayed
696 Assembler* delayed() {
697 #ifdef CHECK_DELAY
698 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
699 delay_state = filling_delay_slot;
700 #endif
701 return this;
702 }
703
704 void flush() {
705 #ifdef CHECK_DELAY
706 assert ( delay_state == no_delay, "ending code with a delay slot");
707 #endif
708 AbstractAssembler::flush();
709 }
710
711 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
712 inline void emit_data(int x) { emit_int32(x); }
713 inline void emit_data(int, RelocationHolder const&);
714 inline void emit_data(int, relocInfo::relocType rtype);
715 // helper for above fcns
716 inline void check_delay();
717
718
719 public:
720 // instructions, refer to page numbers in the SPARC Architecture Manual, V9
721
722 // pp 135 (addc was addx in v8)
723
724 inline void add(Register s1, Register s2, Register d );
725 inline void add(Register s1, int simm13a, Register d );
726
727 void addcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
728 void addcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
729 void addc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
730 void addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
731 void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
732 void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
733
734
735 // 4-operand AES instructions
736
737 void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
738 void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
739 void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
740 void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
741 void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
742 void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
743 void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
744 void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
745 void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D) ); }
746
747
748 // 3-operand AES instructions
749
750 void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D) ); }
751 void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D) ); }
752
753 // pp 136
754
755 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
756 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
757
758 // compare and branch
759 inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
760 inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
761
762 protected: // use MacroAssembler::br instead
763
764 // pp 138
765
766 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
767 inline void fb( Condition c, bool a, Label& L );
768
769 // pp 141
770
771 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
772 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
773
774 // pp 144
775
776 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
777 inline void br( Condition c, bool a, Label& L );
778
779 // pp 146
780
781 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
782 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
783
784 // pp 149
785
786 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
787 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
788
789 public:
790
791 // pp 150
792
793 // These instructions compare the contents of s2 with the contents of
794 // memory at address in s1. If the values are equal, the contents of memory
795 // at address s1 is swapped with the data in d. If the values are not equal,
796 // the the contents of memory at s1 is loaded into d, without the swap.
797
798 void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
799 void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
800
801 // pp 152
802
803 void udiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); }
804 void udiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
805 void sdiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); }
806 void sdiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
807 void udivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
808 void udivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
809 void sdivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
810 void sdivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
811
812 // pp 155
813
814 void done() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(0) | op3(done_op3) ); }
815 void retry() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(1) | op3(retry_op3) ); }
816
817 // pp 156
818
819 void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
820 void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
821
822 // pp 157
823
824 void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
825 void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
826
827 // pp 159
828
829 void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
830 void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
831
832 // pp 160
833
834 void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
835
836 // pp 161
837
838 void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); }
839 void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); }
840
841 // pp 162
842
843 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
844
845 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
846
847 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
848
849 // pp 163
850
851 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); }
852 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
853 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
854
855 // FXORs/FXORd instructions
856
857 void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w)); }
858
859 // pp 164
860
861 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
862
863 // pp 165
864
865 inline void flush( Register s1, Register s2 );
866 inline void flush( Register s1, int simm13a);
867
868 // pp 167
869
870 void flushw() { v9_only(); emit_int32( op(arith_op) | op3(flushw_op3) ); }
871
872 // pp 168
873
874 void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_int32( op(branch_op) | u_field(const22a, 21, 0) ); }
875 // v8 unimp == illtrap(0)
876
877 // pp 169
878
879 void impdep1( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
880 void impdep2( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
881
882 // pp 170
883
884 void jmpl( Register s1, Register s2, Register d );
885 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
886
887 // 171
888
889 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
890 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
891
892
893 inline void ldfsr( Register s1, Register s2 );
894 inline void ldfsr( Register s1, int simm13a);
895 inline void ldxfsr( Register s1, Register s2 );
896 inline void ldxfsr( Register s1, int simm13a);
897
898 // 173
899
900 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
901 void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
902
903 // pp 175, lduw is ld on v8
904
905 inline void ldsb( Register s1, Register s2, Register d );
906 inline void ldsb( Register s1, int simm13a, Register d);
907 inline void ldsh( Register s1, Register s2, Register d );
908 inline void ldsh( Register s1, int simm13a, Register d);
909 inline void ldsw( Register s1, Register s2, Register d );
910 inline void ldsw( Register s1, int simm13a, Register d);
911 inline void ldub( Register s1, Register s2, Register d );
912 inline void ldub( Register s1, int simm13a, Register d);
913 inline void lduh( Register s1, Register s2, Register d );
914 inline void lduh( Register s1, int simm13a, Register d);
915 inline void lduw( Register s1, Register s2, Register d );
916 inline void lduw( Register s1, int simm13a, Register d);
917 inline void ldx( Register s1, Register s2, Register d );
918 inline void ldx( Register s1, int simm13a, Register d);
919 inline void ldd( Register s1, Register s2, Register d );
920 inline void ldd( Register s1, int simm13a, Register d);
921
922 // pp 177
923
924 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
925 void ldsba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
926 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
927 void ldsha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
928 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
929 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
930 void lduba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
931 void lduba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
932 void lduha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
933 void lduha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
934 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
935 void lduwa( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
936 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
937 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
938
939 // pp 181
940
941 void and3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
942 void and3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
943 void andcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
944 void andcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
945 void andn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
946 void andn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
947 void andncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
948 void andncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
949 void or3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
950 void or3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
951 void orcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
952 void orcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
953 void orn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
954 void orn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
955 void orncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
956 void orncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
957 void xor3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
958 void xor3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
959 void xorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
960 void xorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
961 void xnor( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
962 void xnor( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
963 void xnorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
964 void xnorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
965
966 // pp 183
967
968 void membar( Membar_mask_bits const7a ) { v9_only(); emit_int32( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }
969
970 // pp 185
971
972 void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
973
974 // pp 189
975
976 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
977
978 // pp 191
979
980 void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
981 void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
982
983 // pp 195
984
985 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
986 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
987
988 // pp 196
989
990 void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
991 void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
992 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
993 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
994 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
995 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
996
997 // pp 197
998
999 void umul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); }
1000 void umul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1001 void smul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); }
1002 void smul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1003 void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1004 void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1005 void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1006 void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1007
1008 // pp 201
1009
1010 void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); }
1011
1012
1013 // pp 202
1014
1015 void popc( Register s, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
1016 void popc( int simm13a, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
1017
1018 // pp 203
1019
1020 void prefetch( Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
1021 void prefetch( Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
1022
1023 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1024 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1025
1026 // pp 208
1027
1028 // not implementing read privileged register
1029
1030 inline void rdy( Register d) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
1031 inline void rdccr( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
1032 inline void rdasi( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
1033 inline void rdtick( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
1034 inline void rdpc( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
1035 inline void rdfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
1036
1037 // pp 213
1038
1039 inline void rett( Register s1, Register s2);
1040 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
1041
1042 // pp 214
1043
1044 void save( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
1045 void save( Register s1, int simm13a, Register d ) {
1046 // make sure frame is at least large enough for the register save area
1047 assert(-simm13a >= 16 * wordSize, "frame too small");
1048 emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) );
1049 }
1050
1051 void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
1052 void restore( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1053
1054 // pp 216
1055
1056 void saved() { v9_only(); emit_int32( op(arith_op) | fcn(0) | op3(saved_op3)); }
1057 void restored() { v9_only(); emit_int32( op(arith_op) | fcn(1) | op3(saved_op3)); }
1058
1059 // pp 217
1060
1061 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1062 // pp 218
1063
1064 void sll( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1065 void sll( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1066 void srl( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1067 void srl( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1068 void sra( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1069 void sra( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1070
1071 void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1072 void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1073 void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1074 void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1075 void srax( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1076 void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1077
1078 // pp 220
1079
1080 void sir( int simm13a ) { emit_int32( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
1081
1082 // pp 221
1083
1084 void stbar() { emit_int32( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
1085
1086 // pp 222
1087
1088 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
1089 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1090
1091 inline void stfsr( Register s1, Register s2 );
1092 inline void stfsr( Register s1, int simm13a);
1093 inline void stxfsr( Register s1, Register s2 );
1094 inline void stxfsr( Register s1, int simm13a);
1095
1096 // pp 224
1097
1098 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1099 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1100
1101 // p 226
1102
1103 inline void stb( Register d, Register s1, Register s2 );
1104 inline void stb( Register d, Register s1, int simm13a);
1105 inline void sth( Register d, Register s1, Register s2 );
1106 inline void sth( Register d, Register s1, int simm13a);
1107 inline void stw( Register d, Register s1, Register s2 );
1108 inline void stw( Register d, Register s1, int simm13a);
1109 inline void stx( Register d, Register s1, Register s2 );
1110 inline void stx( Register d, Register s1, int simm13a);
1111 inline void std( Register d, Register s1, Register s2 );
1112 inline void std( Register d, Register s1, int simm13a);
1113
1114 // pp 177
1115
1116 void stba( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1117 void stba( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1118 void stha( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1119 void stha( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1120 void stwa( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1121 void stwa( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1122 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1123 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1124 void stda( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1125 void stda( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1126
1127 // pp 230
1128
1129 void sub( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
1130 void sub( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1131
1132 void subcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1133 void subcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1134 void subc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); }
1135 void subc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1136 void subccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1137 void subccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1138
1139 // pp 231
1140
1141 inline void swap( Register s1, Register s2, Register d );
1142 inline void swap( Register s1, int simm13a, Register d);
1143
1144 // pp 232
1145
1146 void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1147 void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1148
1149 // pp 234, note op in book is wrong, see pp 268
1150
1151 void taddcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); }
1152 void taddcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1153
1154 // pp 235
1155
1156 void tsubcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); }
1157 void tsubcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1158
1159 // pp 237
1160
1161 void trap( Condition c, CC cc, Register s1, Register s2 ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
1162 void trap( Condition c, CC cc, Register s1, int trapa ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1163 // simple uncond. trap
1164 void trap( int trapa ) { trap( always, icc, G0, trapa ); }
1165
1166 // pp 239 omit write priv register for now
1167
1168 inline void wry( Register d) { v9_dep(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1169 inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1170 inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) |
1171 rs1(s) |
1172 op3(wrreg_op3) |
1173 u_field(2, 29, 25) |
1174 immed(true) |
1175 simm(simm13a, 13)); }
1176 inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1177 // wrasi(d, imm) stores (d xor imm) to asi
1178 inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) |
1179 u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
1180 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1181
1182
1183 // VIS1 instructions
1184
1185 void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
1186
1187 void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
1188
1189 void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
1190
1191 void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
1192
1193 // VIS2 instructions
1194
1195 void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
1196
1197 // VIS3 instructions
1198
1199 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1200 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1201 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1202
1203 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1204 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1205
1206 // Creation
1207 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1208 #ifdef CHECK_DELAY
1209 delay_state = no_delay;
1210 #endif
1211 }
1212 };
1213
1214 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP