106 srlx_op3 = 0x26,
107 sra_op3 = 0x27,
108 srax_op3 = 0x27,
109 rdreg_op3 = 0x28,
110 membar_op3 = 0x28,
111
112 flushw_op3 = 0x2b,
113 movcc_op3 = 0x2c,
114 sdivx_op3 = 0x2d,
115 popc_op3 = 0x2e,
116 movr_op3 = 0x2f,
117
118 sir_op3 = 0x30,
119 wrreg_op3 = 0x30,
120 saved_op3 = 0x31,
121
122 fpop1_op3 = 0x34,
123 fpop2_op3 = 0x35,
124 impdep1_op3 = 0x36,
125 aes3_op3 = 0x36,
126 alignaddr_op3 = 0x36,
127 faligndata_op3 = 0x36,
128 flog3_op3 = 0x36,
129 edge_op3 = 0x36,
130 fsrc_op3 = 0x36,
131 impdep2_op3 = 0x37,
132 stpartialf_op3 = 0x37,
133 jmpl_op3 = 0x38,
134 rett_op3 = 0x39,
135 trap_op3 = 0x3a,
136 flush_op3 = 0x3b,
137 save_op3 = 0x3c,
138 restore_op3 = 0x3d,
139 done_op3 = 0x3e,
140 retry_op3 = 0x3e,
141
142 lduw_op3 = 0x00,
143 ldub_op3 = 0x01,
144 lduh_op3 = 0x02,
145 ldd_op3 = 0x03,
206 fcmpd_opf = 0x52,
207
208 fstox_opf = 0x81,
209 fdtox_opf = 0x82,
210 fxtos_opf = 0x84,
211 fxtod_opf = 0x88,
212 fitos_opf = 0xc4,
213 fdtos_opf = 0xc6,
214 fitod_opf = 0xc8,
215 fstod_opf = 0xc9,
216 fstoi_opf = 0xd1,
217 fdtoi_opf = 0xd2,
218
219 mdtox_opf = 0x110,
220 mstouw_opf = 0x111,
221 mstosw_opf = 0x113,
222 mxtod_opf = 0x118,
223 mwtos_opf = 0x119,
224
225 aes_kexpand0_opf = 0x130,
226 aes_kexpand2_opf = 0x131
227 };
228
229 enum op5s {
230 aes_eround01_op5 = 0x00,
231 aes_eround23_op5 = 0x01,
232 aes_dround01_op5 = 0x02,
233 aes_dround23_op5 = 0x03,
234 aes_eround01_l_op5 = 0x04,
235 aes_eround23_l_op5 = 0x05,
236 aes_dround01_l_op5 = 0x06,
237 aes_dround23_l_op5 = 0x07,
238 aes_kexpand1_op5 = 0x08
239 };
240
241 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
242
243 enum Condition {
244 // for FBfcc & FBPfcc instruction
245 f_never = 0,
246 f_notEqual = 1,
578 // given a sethi instruction, extract the constant, left-justified
579 static int inv_hi22( int x ) {
580 return x << 10;
581 }
582
583 // create an imm22 field, given a 32-bit left-justified constant
584 static int hi22( int x ) {
585 int r = int( juint(x) >> 10 );
586 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
587 return r;
588 }
589
590 // create a low10 __value__ (not a field) for a given a 32-bit constant
591 static int low10( int x ) {
592 return x & ((1 << 10) - 1);
593 }
594
595 // AES crypto instructions supported only on certain processors
596 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
597
598 // instruction only in VIS1
599 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
600
601 // instruction only in VIS2
602 static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
603
604 // instruction only in VIS3
605 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
606
607 // instruction only in v9
608 static void v9_only() { } // do nothing
609
610 // instruction deprecated in v9
611 static void v9_dep() { } // do nothing for now
612
613 // v8 has no CC field
614 static void v8_no_cc(CC cc) { if (cc) v9_only(); }
615
616 protected:
617 // Simple delay-slot scheme:
1162 void trap( Condition c, CC cc, Register s1, int trapa ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1163 // simple uncond. trap
1164 void trap( int trapa ) { trap( always, icc, G0, trapa ); }
1165
1166 // pp 239 omit write priv register for now
1167
1168 inline void wry( Register d) { v9_dep(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1169 inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1170 inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) |
1171 rs1(s) |
1172 op3(wrreg_op3) |
1173 u_field(2, 29, 25) |
1174 immed(true) |
1175 simm(simm13a, 13)); }
1176 inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1177 // wrasi(d, imm) stores (d xor imm) to asi
1178 inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) |
1179 u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
1180 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1181
1182
1183 // VIS1 instructions
1184
1185 void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
1186
1187 void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
1188
1189 void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
1190
1191 void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
1192
1193 // VIS2 instructions
1194
1195 void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
1196
1197 // VIS3 instructions
1198
1199 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1200 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1201 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1202
1203 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1204 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1205
1206 // Creation
1207 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1208 #ifdef CHECK_DELAY
1209 delay_state = no_delay;
1210 #endif
1211 }
1212 };
1213
1214 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
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106 srlx_op3 = 0x26,
107 sra_op3 = 0x27,
108 srax_op3 = 0x27,
109 rdreg_op3 = 0x28,
110 membar_op3 = 0x28,
111
112 flushw_op3 = 0x2b,
113 movcc_op3 = 0x2c,
114 sdivx_op3 = 0x2d,
115 popc_op3 = 0x2e,
116 movr_op3 = 0x2f,
117
118 sir_op3 = 0x30,
119 wrreg_op3 = 0x30,
120 saved_op3 = 0x31,
121
122 fpop1_op3 = 0x34,
123 fpop2_op3 = 0x35,
124 impdep1_op3 = 0x36,
125 aes3_op3 = 0x36,
126 sha_op3 = 0x36,
127 alignaddr_op3 = 0x36,
128 faligndata_op3 = 0x36,
129 flog3_op3 = 0x36,
130 edge_op3 = 0x36,
131 fsrc_op3 = 0x36,
132 impdep2_op3 = 0x37,
133 stpartialf_op3 = 0x37,
134 jmpl_op3 = 0x38,
135 rett_op3 = 0x39,
136 trap_op3 = 0x3a,
137 flush_op3 = 0x3b,
138 save_op3 = 0x3c,
139 restore_op3 = 0x3d,
140 done_op3 = 0x3e,
141 retry_op3 = 0x3e,
142
143 lduw_op3 = 0x00,
144 ldub_op3 = 0x01,
145 lduh_op3 = 0x02,
146 ldd_op3 = 0x03,
207 fcmpd_opf = 0x52,
208
209 fstox_opf = 0x81,
210 fdtox_opf = 0x82,
211 fxtos_opf = 0x84,
212 fxtod_opf = 0x88,
213 fitos_opf = 0xc4,
214 fdtos_opf = 0xc6,
215 fitod_opf = 0xc8,
216 fstod_opf = 0xc9,
217 fstoi_opf = 0xd1,
218 fdtoi_opf = 0xd2,
219
220 mdtox_opf = 0x110,
221 mstouw_opf = 0x111,
222 mstosw_opf = 0x113,
223 mxtod_opf = 0x118,
224 mwtos_opf = 0x119,
225
226 aes_kexpand0_opf = 0x130,
227 aes_kexpand2_opf = 0x131,
228
229 sha1_opf = 0x141,
230 sha256_opf = 0x142,
231 sha512_opf = 0x143
232 };
233
234 enum op5s {
235 aes_eround01_op5 = 0x00,
236 aes_eround23_op5 = 0x01,
237 aes_dround01_op5 = 0x02,
238 aes_dround23_op5 = 0x03,
239 aes_eround01_l_op5 = 0x04,
240 aes_eround23_l_op5 = 0x05,
241 aes_dround01_l_op5 = 0x06,
242 aes_dround23_l_op5 = 0x07,
243 aes_kexpand1_op5 = 0x08
244 };
245
246 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
247
248 enum Condition {
249 // for FBfcc & FBPfcc instruction
250 f_never = 0,
251 f_notEqual = 1,
583 // given a sethi instruction, extract the constant, left-justified
584 static int inv_hi22( int x ) {
585 return x << 10;
586 }
587
588 // create an imm22 field, given a 32-bit left-justified constant
589 static int hi22( int x ) {
590 int r = int( juint(x) >> 10 );
591 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
592 return r;
593 }
594
595 // create a low10 __value__ (not a field) for a given a 32-bit constant
596 static int low10( int x ) {
597 return x & ((1 << 10) - 1);
598 }
599
600 // AES crypto instructions supported only on certain processors
601 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
602
603 // SHA crypto instructions supported only on certain processors
604 static void sha1_only() { assert( VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); }
605 static void sha256_only() { assert( VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
606 static void sha512_only() { assert( VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
607
608 // instruction only in VIS1
609 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
610
611 // instruction only in VIS2
612 static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
613
614 // instruction only in VIS3
615 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
616
617 // instruction only in v9
618 static void v9_only() { } // do nothing
619
620 // instruction deprecated in v9
621 static void v9_dep() { } // do nothing for now
622
623 // v8 has no CC field
624 static void v8_no_cc(CC cc) { if (cc) v9_only(); }
625
626 protected:
627 // Simple delay-slot scheme:
1172 void trap( Condition c, CC cc, Register s1, int trapa ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1173 // simple uncond. trap
1174 void trap( int trapa ) { trap( always, icc, G0, trapa ); }
1175
1176 // pp 239 omit write priv register for now
1177
1178 inline void wry( Register d) { v9_dep(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1179 inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1180 inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) |
1181 rs1(s) |
1182 op3(wrreg_op3) |
1183 u_field(2, 29, 25) |
1184 immed(true) |
1185 simm(simm13a, 13)); }
1186 inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1187 // wrasi(d, imm) stores (d xor imm) to asi
1188 inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) |
1189 u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); }
1190 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1191
1192 // VIS1 instructions
1193
1194 void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); }
1195
1196 void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); }
1197
1198 void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); }
1199
1200 void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); }
1201
1202 // VIS2 instructions
1203
1204 void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); }
1205
1206 // VIS3 instructions
1207
1208 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); }
1209 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); }
1210 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); }
1211
1212 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); }
1213 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); }
1214
1215 // Crypto SHA instructions
1216
1217 void sha1() { sha1_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); }
1218 void sha256() { sha256_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); }
1219 void sha512() { sha512_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); }
1220
1221 // Creation
1222 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1223 #ifdef CHECK_DELAY
1224 delay_state = no_delay;
1225 #endif
1226 }
1227 };
1228
1229 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
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