1 /*
   2  * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.inline.hpp"
  27 #include "memory/resourceArea.hpp"
  28 #include "runtime/java.hpp"
  29 #include "runtime/stubCodeGenerator.hpp"
  30 #include "vm_version_sparc.hpp"
  31 #ifdef TARGET_OS_FAMILY_linux
  32 # include "os_linux.inline.hpp"
  33 #endif
  34 #ifdef TARGET_OS_FAMILY_solaris
  35 # include "os_solaris.inline.hpp"
  36 #endif
  37 
  38 int VM_Version::_features = VM_Version::unknown_m;
  39 const char* VM_Version::_features_str = "";
  40 
  41 void VM_Version::initialize() {
  42   _features = determine_features();
  43   PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
  44   PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
  45   PrefetchFieldsAhead         = prefetch_fields_ahead();
  46 
  47   assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value");
  48   if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
  49   if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0;
  50 
  51   // Allocation prefetch settings
  52   intx cache_line_size = prefetch_data_size();
  53   if( cache_line_size > AllocatePrefetchStepSize )
  54     AllocatePrefetchStepSize = cache_line_size;
  55 
  56   assert(AllocatePrefetchLines > 0, "invalid value");
  57   if( AllocatePrefetchLines < 1 )     // set valid value in product VM
  58     AllocatePrefetchLines = 3;
  59   assert(AllocateInstancePrefetchLines > 0, "invalid value");
  60   if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
  61     AllocateInstancePrefetchLines = 1;
  62 
  63   AllocatePrefetchDistance = allocate_prefetch_distance();
  64   AllocatePrefetchStyle    = allocate_prefetch_style();
  65 
  66   assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
  67          (AllocatePrefetchDistance > 0), "invalid value");
  68   if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
  69       (AllocatePrefetchDistance <= 0)) {
  70     AllocatePrefetchDistance = AllocatePrefetchStepSize;
  71   }
  72 
  73   if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
  74     warning("BIS instructions are not available on this CPU");
  75     FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
  76   }
  77 
  78   guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
  79 
  80   assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
  81   if (ArraycopySrcPrefetchDistance >= 4096)
  82     ArraycopySrcPrefetchDistance = 4064;
  83   assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
  84   if (ArraycopyDstPrefetchDistance >= 4096)
  85     ArraycopyDstPrefetchDistance = 4064;
  86 
  87   UseSSE = 0; // Only on x86 and x64
  88 
  89   _supports_cx8 = has_v9();
  90   _supports_atomic_getset4 = true; // swap instruction
  91 
  92   // There are Fujitsu Sparc64 CPUs which support blk_init as well so
  93   // we have to take this check out of the 'is_niagara()' block below.
  94   if (has_blk_init()) {
  95     // When using CMS or G1, we cannot use memset() in BOT updates
  96     // because the sun4v/CMT version in libc_psr uses BIS which
  97     // exposes "phantom zeros" to concurrent readers. See 6948537.
  98     if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) {
  99       FLAG_SET_DEFAULT(UseMemSetInBOT, false);
 100     }
 101     // Issue a stern warning if the user has explicitly set
 102     // UseMemSetInBOT (it is known to cause issues), but allow
 103     // use for experimentation and debugging.
 104     if (UseConcMarkSweepGC || UseG1GC) {
 105       if (UseMemSetInBOT) {
 106         assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error");
 107         warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability"
 108                 " on sun4v; please understand that you are using at your own risk!");
 109       }
 110     }
 111   }
 112 
 113   if (is_niagara()) {
 114     // Indirect branch is the same cost as direct
 115     if (FLAG_IS_DEFAULT(UseInlineCaches)) {
 116       FLAG_SET_DEFAULT(UseInlineCaches, false);
 117     }
 118     // Align loops on a single instruction boundary.
 119     if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
 120       FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
 121     }
 122 #ifdef _LP64
 123     // 32-bit oops don't make sense for the 64-bit VM on sparc
 124     // since the 32-bit VM has the same registers and smaller objects.
 125     Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
 126     Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
 127 #endif // _LP64
 128 #ifdef COMPILER2
 129     // Indirect branch is the same cost as direct
 130     if (FLAG_IS_DEFAULT(UseJumpTables)) {
 131       FLAG_SET_DEFAULT(UseJumpTables, true);
 132     }
 133     // Single-issue, so entry and loop tops are
 134     // aligned on a single instruction boundary
 135     if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
 136       FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
 137     }
 138     if (is_niagara_plus()) {
 139       if (has_blk_init() && UseTLAB &&
 140           FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
 141         // Use BIS instruction for TLAB allocation prefetch.
 142         FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
 143         if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
 144           FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
 145         }
 146         if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
 147           // Use smaller prefetch distance with BIS
 148           FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
 149         }
 150       }
 151       if (is_T4()) {
 152         // Double number of prefetched cache lines on T4
 153         // since L2 cache line size is smaller (32 bytes).
 154         if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
 155           FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
 156         }
 157         if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
 158           FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
 159         }
 160       }
 161       if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
 162         // Use different prefetch distance without BIS
 163         FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
 164       }
 165       if (AllocatePrefetchInstr == 1) {
 166         // Need a space at the end of TLAB for BIS since it
 167         // will fault when accessing memory outside of heap.
 168 
 169         // +1 for rounding up to next cache line, +1 to be safe
 170         int lines = AllocatePrefetchLines + 2;
 171         int step_size = AllocatePrefetchStepSize;
 172         int distance = AllocatePrefetchDistance;
 173         _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
 174       }
 175     }
 176 #endif
 177   }
 178 
 179   // Use hardware population count instruction if available.
 180   if (has_hardware_popc()) {
 181     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
 182       FLAG_SET_DEFAULT(UsePopCountInstruction, true);
 183     }
 184   } else if (UsePopCountInstruction) {
 185     warning("POPC instruction is not available on this CPU");
 186     FLAG_SET_DEFAULT(UsePopCountInstruction, false);
 187   }
 188 
 189   // T4 and newer Sparc cpus have new compare and branch instruction.
 190   if (has_cbcond()) {
 191     if (FLAG_IS_DEFAULT(UseCBCond)) {
 192       FLAG_SET_DEFAULT(UseCBCond, true);
 193     }
 194   } else if (UseCBCond) {
 195     warning("CBCOND instruction is not available on this CPU");
 196     FLAG_SET_DEFAULT(UseCBCond, false);
 197   }
 198 
 199   assert(BlockZeroingLowLimit > 0, "invalid value");
 200   if (has_block_zeroing()) {
 201     if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
 202       FLAG_SET_DEFAULT(UseBlockZeroing, true);
 203     }
 204   } else if (UseBlockZeroing) {
 205     warning("BIS zeroing instructions are not available on this CPU");
 206     FLAG_SET_DEFAULT(UseBlockZeroing, false);
 207   }
 208 
 209   assert(BlockCopyLowLimit > 0, "invalid value");
 210   if (has_block_zeroing()) { // has_blk_init() && is_T4(): core's local L2 cache
 211     if (FLAG_IS_DEFAULT(UseBlockCopy)) {
 212       FLAG_SET_DEFAULT(UseBlockCopy, true);
 213     }
 214   } else if (UseBlockCopy) {
 215     warning("BIS instructions are not available or expensive on this CPU");
 216     FLAG_SET_DEFAULT(UseBlockCopy, false);
 217   }
 218 
 219 #ifdef COMPILER2
 220   // T4 and newer Sparc cpus have fast RDPC.
 221   if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
 222     FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
 223   }
 224 
 225   // Currently not supported anywhere.
 226   FLAG_SET_DEFAULT(UseFPUForSpilling, false);
 227 
 228   MaxVectorSize = 8;
 229 
 230   assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 231 #endif
 232 
 233   assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 234   assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 235 
 236   char buf[512];
 237   jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 238                (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
 239                (has_hardware_popc() ? ", popc" : ""),
 240                (has_vis1() ? ", vis1" : ""),
 241                (has_vis2() ? ", vis2" : ""),
 242                (has_vis3() ? ", vis3" : ""),
 243                (has_blk_init() ? ", blk_init" : ""),
 244                (has_cbcond() ? ", cbcond" : ""),
 245                (has_aes() ? ", aes" : ""),
 246                (has_sha1() ? ", sha1" : ""),
 247                (has_sha256() ? ", sha256" : ""),
 248                (has_sha512() ? ", sha512" : ""),
 249                (is_ultra3() ? ", ultra3" : ""),
 250                (is_sun4v() ? ", sun4v" : ""),
 251                (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
 252                (is_sparc64() ? ", sparc64" : ""),
 253                (!has_hardware_mul32() ? ", no-mul32" : ""),
 254                (!has_hardware_div32() ? ", no-div32" : ""),
 255                (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
 256 
 257   // buf is started with ", " or is empty
 258   _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
 259 
 260   // UseVIS is set to the smallest of what hardware supports and what
 261   // the command line requires.  I.e., you cannot set UseVIS to 3 on
 262   // older UltraSparc which do not support it.
 263   if (UseVIS > 3) UseVIS=3;
 264   if (UseVIS < 0) UseVIS=0;
 265   if (!has_vis3()) // Drop to 2 if no VIS3 support
 266     UseVIS = MIN2((intx)2,UseVIS);
 267   if (!has_vis2()) // Drop to 1 if no VIS2 support
 268     UseVIS = MIN2((intx)1,UseVIS);
 269   if (!has_vis1()) // Drop to 0 if no VIS1 support
 270     UseVIS = 0;
 271 
 272   // SPARC T4 and above should have support for AES instructions
 273   if (has_aes()) {
 274     if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3
 275       if (FLAG_IS_DEFAULT(UseAES)) {
 276         FLAG_SET_DEFAULT(UseAES, true);
 277       }
 278       if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 279         FLAG_SET_DEFAULT(UseAESIntrinsics, true);
 280       }
 281       // we disable both the AES flags if either of them is disabled on the command line
 282       if (!UseAES || !UseAESIntrinsics) {
 283         FLAG_SET_DEFAULT(UseAES, false);
 284         FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 285       }
 286     } else {
 287         if (UseAES || UseAESIntrinsics) {
 288           warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
 289           if (UseAES) {
 290             FLAG_SET_DEFAULT(UseAES, false);
 291           }
 292           if (UseAESIntrinsics) {
 293             FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 294           }
 295         }
 296     }
 297   } else if (UseAES || UseAESIntrinsics) {
 298     warning("AES instructions are not available on this CPU");
 299     if (UseAES) {
 300       FLAG_SET_DEFAULT(UseAES, false);
 301     }
 302     if (UseAESIntrinsics) {
 303       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 304     }
 305   }
 306 
 307   // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
 308   if (has_sha1() || has_sha256() || has_sha512()) {
 309     if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
 310       if (FLAG_IS_DEFAULT(UseSHA)) {
 311         FLAG_SET_DEFAULT(UseSHA, true);
 312       }
 313     } else {
 314       if (UseSHA) {
 315         warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
 316         FLAG_SET_DEFAULT(UseSHA, false);
 317       }
 318     }
 319   } else if (UseSHA) {
 320     warning("SHA instructions are not available on this CPU");
 321     FLAG_SET_DEFAULT(UseSHA, false);
 322   }
 323 
 324   if (!UseSHA) {
 325     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 326     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 327     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 328   } else {
 329     if (has_sha1()) {
 330       if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
 331         FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
 332       }
 333     } else if (UseSHA1Intrinsics) {
 334       warning("SHA1 instruction is not available on this CPU.");
 335       FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 336     }
 337     if (has_sha256()) {
 338       if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
 339         FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
 340       }
 341     } else if (UseSHA256Intrinsics) {
 342       warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU.");
 343       FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 344     }
 345 
 346     if (has_sha512()) {
 347       if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
 348         FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
 349       }
 350     } else if (UseSHA512Intrinsics) {
 351       warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
 352       FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 353     }
 354     if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
 355       FLAG_SET_DEFAULT(UseSHA, false);
 356     }
 357   }
 358 
 359   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
 360     (cache_line_size > ContendedPaddingWidth))
 361     ContendedPaddingWidth = cache_line_size;
 362 
 363 #ifndef PRODUCT
 364   if (PrintMiscellaneous && Verbose) {
 365     tty->print("Allocation");
 366     if (AllocatePrefetchStyle <= 0) {
 367       tty->print_cr(": no prefetching");
 368     } else {
 369       tty->print(" prefetching: ");
 370       if (AllocatePrefetchInstr == 0) {
 371           tty->print("PREFETCH");
 372       } else if (AllocatePrefetchInstr == 1) {
 373           tty->print("BIS");
 374       }
 375       if (AllocatePrefetchLines > 1) {
 376         tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
 377       } else {
 378         tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
 379       }
 380     }
 381     if (PrefetchCopyIntervalInBytes > 0) {
 382       tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
 383     }
 384     if (PrefetchScanIntervalInBytes > 0) {
 385       tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
 386     }
 387     if (PrefetchFieldsAhead > 0) {
 388       tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
 389     }
 390     if (ContendedPaddingWidth > 0) {
 391       tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
 392     }
 393   }
 394 #endif // PRODUCT
 395 }
 396 
 397 void VM_Version::print_features() {
 398   tty->print_cr("Version:%s", cpu_features());
 399 }
 400 
 401 int VM_Version::determine_features() {
 402   if (UseV8InstrsOnly) {
 403     NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
 404     return generic_v8_m;
 405   }
 406 
 407   int features = platform_features(unknown_m); // platform_features() is os_arch specific
 408 
 409   if (features == unknown_m) {
 410     features = generic_v9_m;
 411     warning("Cannot recognize SPARC version. Default to V9");
 412   }
 413 
 414   assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
 415   if (UseNiagaraInstrs) { // Force code generation for Niagara
 416     if (is_T_family(features)) {
 417       // Happy to accomodate...
 418     } else {
 419       NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
 420       features |= T_family_m;
 421     }
 422   } else {
 423     if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
 424       NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
 425       features &= ~(T_family_m | T1_model_m);
 426     } else {
 427       // Happy to accomodate...
 428     }
 429   }
 430 
 431   return features;
 432 }
 433 
 434 static int saved_features = 0;
 435 
 436 void VM_Version::allow_all() {
 437   saved_features = _features;
 438   _features      = all_features_m;
 439 }
 440 
 441 void VM_Version::revert() {
 442   _features = saved_features;
 443 }
 444 
 445 unsigned int VM_Version::calc_parallel_worker_threads() {
 446   unsigned int result;
 447   if (is_M_series()) {
 448     // for now, use same gc thread calculation for M-series as for niagara-plus
 449     // in future, we may want to tweak parameters for nof_parallel_worker_thread
 450     result = nof_parallel_worker_threads(5, 16, 8);
 451   } else if (is_niagara_plus()) {
 452     result = nof_parallel_worker_threads(5, 16, 8);
 453   } else {
 454     result = nof_parallel_worker_threads(5, 8, 8);
 455   }
 456   return result;
 457 }