src/cpu/sparc/vm/vm_version_sparc.cpp
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src/cpu/sparc/vm/vm_version_sparc.cpp

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 217   }
 218 
 219 #ifdef COMPILER2
 220   // T4 and newer Sparc cpus have fast RDPC.
 221   if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
 222     FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
 223   }
 224 
 225   // Currently not supported anywhere.
 226   FLAG_SET_DEFAULT(UseFPUForSpilling, false);
 227 
 228   MaxVectorSize = 8;
 229 
 230   assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 231 #endif
 232 
 233   assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 234   assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 235 
 236   char buf[512];
 237   jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 238                (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
 239                (has_hardware_popc() ? ", popc" : ""),
 240                (has_vis1() ? ", vis1" : ""),
 241                (has_vis2() ? ", vis2" : ""),
 242                (has_vis3() ? ", vis3" : ""),
 243                (has_blk_init() ? ", blk_init" : ""),
 244                (has_cbcond() ? ", cbcond" : ""),
 245                (has_aes() ? ", aes" : ""),



 246                (is_ultra3() ? ", ultra3" : ""),
 247                (is_sun4v() ? ", sun4v" : ""),
 248                (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
 249                (is_sparc64() ? ", sparc64" : ""),
 250                (!has_hardware_mul32() ? ", no-mul32" : ""),
 251                (!has_hardware_div32() ? ", no-div32" : ""),
 252                (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
 253 
 254   // buf is started with ", " or is empty
 255   _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
 256 
 257   // UseVIS is set to the smallest of what hardware supports and what
 258   // the command line requires.  I.e., you cannot set UseVIS to 3 on
 259   // older UltraSparc which do not support it.
 260   if (UseVIS > 3) UseVIS=3;
 261   if (UseVIS < 0) UseVIS=0;
 262   if (!has_vis3()) // Drop to 2 if no VIS3 support
 263     UseVIS = MIN2((intx)2,UseVIS);
 264   if (!has_vis2()) // Drop to 1 if no VIS2 support
 265     UseVIS = MIN2((intx)1,UseVIS);


 284         if (UseAES || UseAESIntrinsics) {
 285           warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
 286           if (UseAES) {
 287             FLAG_SET_DEFAULT(UseAES, false);
 288           }
 289           if (UseAESIntrinsics) {
 290             FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 291           }
 292         }
 293     }
 294   } else if (UseAES || UseAESIntrinsics) {
 295     warning("AES instructions are not available on this CPU");
 296     if (UseAES) {
 297       FLAG_SET_DEFAULT(UseAES, false);
 298     }
 299     if (UseAESIntrinsics) {
 300       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 301     }
 302   }
 303 




















































 304   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
 305     (cache_line_size > ContendedPaddingWidth))
 306     ContendedPaddingWidth = cache_line_size;
 307 
 308 #ifndef PRODUCT
 309   if (PrintMiscellaneous && Verbose) {
 310     tty->print("Allocation");
 311     if (AllocatePrefetchStyle <= 0) {
 312       tty->print_cr(": no prefetching");
 313     } else {
 314       tty->print(" prefetching: ");
 315       if (AllocatePrefetchInstr == 0) {
 316           tty->print("PREFETCH");
 317       } else if (AllocatePrefetchInstr == 1) {
 318           tty->print("BIS");
 319       }
 320       if (AllocatePrefetchLines > 1) {
 321         tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
 322       } else {
 323         tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);




 217   }
 218 
 219 #ifdef COMPILER2
 220   // T4 and newer Sparc cpus have fast RDPC.
 221   if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
 222     FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
 223   }
 224 
 225   // Currently not supported anywhere.
 226   FLAG_SET_DEFAULT(UseFPUForSpilling, false);
 227 
 228   MaxVectorSize = 8;
 229 
 230   assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 231 #endif
 232 
 233   assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 234   assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 235 
 236   char buf[512];
 237   jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 238                (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
 239                (has_hardware_popc() ? ", popc" : ""),
 240                (has_vis1() ? ", vis1" : ""),
 241                (has_vis2() ? ", vis2" : ""),
 242                (has_vis3() ? ", vis3" : ""),
 243                (has_blk_init() ? ", blk_init" : ""),
 244                (has_cbcond() ? ", cbcond" : ""),
 245                (has_aes() ? ", aes" : ""),
 246                (has_sha1() ? ", sha1" : ""),
 247                (has_sha256() ? ", sha256" : ""),
 248                (has_sha512() ? ", sha512" : ""),
 249                (is_ultra3() ? ", ultra3" : ""),
 250                (is_sun4v() ? ", sun4v" : ""),
 251                (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
 252                (is_sparc64() ? ", sparc64" : ""),
 253                (!has_hardware_mul32() ? ", no-mul32" : ""),
 254                (!has_hardware_div32() ? ", no-div32" : ""),
 255                (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
 256 
 257   // buf is started with ", " or is empty
 258   _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
 259 
 260   // UseVIS is set to the smallest of what hardware supports and what
 261   // the command line requires.  I.e., you cannot set UseVIS to 3 on
 262   // older UltraSparc which do not support it.
 263   if (UseVIS > 3) UseVIS=3;
 264   if (UseVIS < 0) UseVIS=0;
 265   if (!has_vis3()) // Drop to 2 if no VIS3 support
 266     UseVIS = MIN2((intx)2,UseVIS);
 267   if (!has_vis2()) // Drop to 1 if no VIS2 support
 268     UseVIS = MIN2((intx)1,UseVIS);


 287         if (UseAES || UseAESIntrinsics) {
 288           warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
 289           if (UseAES) {
 290             FLAG_SET_DEFAULT(UseAES, false);
 291           }
 292           if (UseAESIntrinsics) {
 293             FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 294           }
 295         }
 296     }
 297   } else if (UseAES || UseAESIntrinsics) {
 298     warning("AES instructions are not available on this CPU");
 299     if (UseAES) {
 300       FLAG_SET_DEFAULT(UseAES, false);
 301     }
 302     if (UseAESIntrinsics) {
 303       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 304     }
 305   }
 306 
 307   // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
 308   if (has_sha1() || has_sha256() || has_sha512()) {
 309     if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
 310       if (FLAG_IS_DEFAULT(UseSHA)) {
 311         FLAG_SET_DEFAULT(UseSHA, true);
 312       }
 313     } else {
 314       if (UseSHA) {
 315         warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
 316         FLAG_SET_DEFAULT(UseSHA, false);
 317       }
 318     }
 319   } else if (UseSHA) {
 320     warning("SHA instructions are not available on this CPU");
 321     FLAG_SET_DEFAULT(UseSHA, false);
 322   }
 323 
 324   if (!UseSHA) {
 325     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 326     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 327     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 328   } else {
 329     if (has_sha1()) {
 330       if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
 331         FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
 332       }
 333     } else if (UseSHA1Intrinsics) {
 334       warning("SHA1 instruction is not available on this CPU.");
 335       FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 336     }
 337     if (has_sha256()) {
 338       if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
 339         FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
 340       }
 341     } else if (UseSHA256Intrinsics) {
 342       warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU.");
 343       FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 344     }
 345 
 346     if (has_sha512()) {
 347       if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
 348         FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
 349       }
 350     } else if (UseSHA512Intrinsics) {
 351       warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
 352       FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 353     }
 354     if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
 355       FLAG_SET_DEFAULT(UseSHA, false);
 356     }
 357   }
 358 
 359   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
 360     (cache_line_size > ContendedPaddingWidth))
 361     ContendedPaddingWidth = cache_line_size;
 362 
 363 #ifndef PRODUCT
 364   if (PrintMiscellaneous && Verbose) {
 365     tty->print("Allocation");
 366     if (AllocatePrefetchStyle <= 0) {
 367       tty->print_cr(": no prefetching");
 368     } else {
 369       tty->print(" prefetching: ");
 370       if (AllocatePrefetchInstr == 0) {
 371           tty->print("PREFETCH");
 372       } else if (AllocatePrefetchInstr == 1) {
 373           tty->print("BIS");
 374       }
 375       if (AllocatePrefetchLines > 1) {
 376         tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
 377       } else {
 378         tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);


src/cpu/sparc/vm/vm_version_sparc.cpp
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