1 /* 2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "memory/resourceArea.hpp" 29 #include "runtime/java.hpp" 30 #include "runtime/stubCodeGenerator.hpp" 31 #include "vm_version_x86.hpp" 32 #ifdef TARGET_OS_FAMILY_linux 33 # include "os_linux.inline.hpp" 34 #endif 35 #ifdef TARGET_OS_FAMILY_solaris 36 # include "os_solaris.inline.hpp" 37 #endif 38 #ifdef TARGET_OS_FAMILY_windows 39 # include "os_windows.inline.hpp" 40 #endif 41 #ifdef TARGET_OS_FAMILY_bsd 42 # include "os_bsd.inline.hpp" 43 #endif 44 45 46 int VM_Version::_cpu; 47 int VM_Version::_model; 48 int VM_Version::_stepping; 49 int VM_Version::_cpuFeatures; 50 const char* VM_Version::_features_str = ""; 51 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; 52 53 // Address of instruction which causes SEGV 54 address VM_Version::_cpuinfo_segv_addr = 0; 55 // Address of instruction after the one which causes SEGV 56 address VM_Version::_cpuinfo_cont_addr = 0; 57 58 static BufferBlob* stub_blob; 59 static const int stub_size = 600; 60 61 extern "C" { 62 typedef void (*get_cpu_info_stub_t)(void*); 63 } 64 static get_cpu_info_stub_t get_cpu_info_stub = NULL; 65 66 67 class VM_Version_StubGenerator: public StubCodeGenerator { 68 public: 69 70 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} 71 72 address generate_get_cpu_info() { 73 // Flags to test CPU type. 74 const uint32_t HS_EFL_AC = 0x40000; 75 const uint32_t HS_EFL_ID = 0x200000; 76 // Values for when we don't have a CPUID instruction. 77 const int CPU_FAMILY_SHIFT = 8; 78 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); 79 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); 80 81 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; 82 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done; 83 84 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub"); 85 # define __ _masm-> 86 87 address start = __ pc(); 88 89 // 90 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info); 91 // 92 // LP64: rcx and rdx are first and second argument registers on windows 93 94 __ push(rbp); 95 #ifdef _LP64 96 __ mov(rbp, c_rarg0); // cpuid_info address 97 #else 98 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address 99 #endif 100 __ push(rbx); 101 __ push(rsi); 102 __ pushf(); // preserve rbx, and flags 103 __ pop(rax); 104 __ push(rax); 105 __ mov(rcx, rax); 106 // 107 // if we are unable to change the AC flag, we have a 386 108 // 109 __ xorl(rax, HS_EFL_AC); 110 __ push(rax); 111 __ popf(); 112 __ pushf(); 113 __ pop(rax); 114 __ cmpptr(rax, rcx); 115 __ jccb(Assembler::notEqual, detect_486); 116 117 __ movl(rax, CPU_FAMILY_386); 118 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); 119 __ jmp(done); 120 121 // 122 // If we are unable to change the ID flag, we have a 486 which does 123 // not support the "cpuid" instruction. 124 // 125 __ bind(detect_486); 126 __ mov(rax, rcx); 127 __ xorl(rax, HS_EFL_ID); 128 __ push(rax); 129 __ popf(); 130 __ pushf(); 131 __ pop(rax); 132 __ cmpptr(rcx, rax); 133 __ jccb(Assembler::notEqual, detect_586); 134 135 __ bind(cpu486); 136 __ movl(rax, CPU_FAMILY_486); 137 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); 138 __ jmp(done); 139 140 // 141 // At this point, we have a chip which supports the "cpuid" instruction 142 // 143 __ bind(detect_586); 144 __ xorl(rax, rax); 145 __ cpuid(); 146 __ orl(rax, rax); 147 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input 148 // value of at least 1, we give up and 149 // assume a 486 150 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); 151 __ movl(Address(rsi, 0), rax); 152 __ movl(Address(rsi, 4), rbx); 153 __ movl(Address(rsi, 8), rcx); 154 __ movl(Address(rsi,12), rdx); 155 156 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported? 157 __ jccb(Assembler::belowEqual, std_cpuid4); 158 159 // 160 // cpuid(0xB) Processor Topology 161 // 162 __ movl(rax, 0xb); 163 __ xorl(rcx, rcx); // Threads level 164 __ cpuid(); 165 166 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset()))); 167 __ movl(Address(rsi, 0), rax); 168 __ movl(Address(rsi, 4), rbx); 169 __ movl(Address(rsi, 8), rcx); 170 __ movl(Address(rsi,12), rdx); 171 172 __ movl(rax, 0xb); 173 __ movl(rcx, 1); // Cores level 174 __ cpuid(); 175 __ push(rax); 176 __ andl(rax, 0x1f); // Determine if valid topology level 177 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level 178 __ andl(rax, 0xffff); 179 __ pop(rax); 180 __ jccb(Assembler::equal, std_cpuid4); 181 182 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset()))); 183 __ movl(Address(rsi, 0), rax); 184 __ movl(Address(rsi, 4), rbx); 185 __ movl(Address(rsi, 8), rcx); 186 __ movl(Address(rsi,12), rdx); 187 188 __ movl(rax, 0xb); 189 __ movl(rcx, 2); // Packages level 190 __ cpuid(); 191 __ push(rax); 192 __ andl(rax, 0x1f); // Determine if valid topology level 193 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level 194 __ andl(rax, 0xffff); 195 __ pop(rax); 196 __ jccb(Assembler::equal, std_cpuid4); 197 198 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset()))); 199 __ movl(Address(rsi, 0), rax); 200 __ movl(Address(rsi, 4), rbx); 201 __ movl(Address(rsi, 8), rcx); 202 __ movl(Address(rsi,12), rdx); 203 204 // 205 // cpuid(0x4) Deterministic cache params 206 // 207 __ bind(std_cpuid4); 208 __ movl(rax, 4); 209 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported? 210 __ jccb(Assembler::greater, std_cpuid1); 211 212 __ xorl(rcx, rcx); // L1 cache 213 __ cpuid(); 214 __ push(rax); 215 __ andl(rax, 0x1f); // Determine if valid cache parameters used 216 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache 217 __ pop(rax); 218 __ jccb(Assembler::equal, std_cpuid1); 219 220 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); 221 __ movl(Address(rsi, 0), rax); 222 __ movl(Address(rsi, 4), rbx); 223 __ movl(Address(rsi, 8), rcx); 224 __ movl(Address(rsi,12), rdx); 225 226 // 227 // Standard cpuid(0x1) 228 // 229 __ bind(std_cpuid1); 230 __ movl(rax, 1); 231 __ cpuid(); 232 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); 233 __ movl(Address(rsi, 0), rax); 234 __ movl(Address(rsi, 4), rbx); 235 __ movl(Address(rsi, 8), rcx); 236 __ movl(Address(rsi,12), rdx); 237 238 // 239 // Check if OS has enabled XGETBV instruction to access XCR0 240 // (OSXSAVE feature flag) and CPU supports AVX 241 // 242 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx 243 __ cmpl(rcx, 0x18000000); 244 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported 245 246 // 247 // XCR0, XFEATURE_ENABLED_MASK register 248 // 249 __ xorl(rcx, rcx); // zero for XCR0 register 250 __ xgetbv(); 251 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); 252 __ movl(Address(rsi, 0), rax); 253 __ movl(Address(rsi, 4), rdx); 254 255 __ andl(rax, 0x6); // xcr0 bits sse | ymm 256 __ cmpl(rax, 0x6); 257 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported 258 259 // 260 // Some OSs have a bug when upper 128bits of YMM 261 // registers are not restored after a signal processing. 262 // Generate SEGV here (reference through NULL) 263 // and check upper YMM bits after it. 264 // 265 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts 266 intx saved_useavx = UseAVX; 267 intx saved_usesse = UseSSE; 268 UseAVX = 1; 269 UseSSE = 2; 270 271 // load value into all 32 bytes of ymm7 register 272 __ movl(rcx, VM_Version::ymm_test_value()); 273 274 __ movdl(xmm0, rcx); 275 __ pshufd(xmm0, xmm0, 0x00); 276 __ vinsertf128h(xmm0, xmm0, xmm0); 277 __ vmovdqu(xmm7, xmm0); 278 #ifdef _LP64 279 __ vmovdqu(xmm8, xmm0); 280 __ vmovdqu(xmm15, xmm0); 281 #endif 282 283 __ xorl(rsi, rsi); 284 VM_Version::set_cpuinfo_segv_addr( __ pc() ); 285 // Generate SEGV 286 __ movl(rax, Address(rsi, 0)); 287 288 VM_Version::set_cpuinfo_cont_addr( __ pc() ); 289 // Returns here after signal. Save xmm0 to check it later. 290 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset()))); 291 __ vmovdqu(Address(rsi, 0), xmm0); 292 __ vmovdqu(Address(rsi, 32), xmm7); 293 #ifdef _LP64 294 __ vmovdqu(Address(rsi, 64), xmm8); 295 __ vmovdqu(Address(rsi, 96), xmm15); 296 #endif 297 298 VM_Version::clean_cpuFeatures(); 299 UseAVX = saved_useavx; 300 UseSSE = saved_usesse; 301 302 // 303 // cpuid(0x7) Structured Extended Features 304 // 305 __ bind(sef_cpuid); 306 __ movl(rax, 7); 307 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported? 308 __ jccb(Assembler::greater, ext_cpuid); 309 310 __ xorl(rcx, rcx); 311 __ cpuid(); 312 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); 313 __ movl(Address(rsi, 0), rax); 314 __ movl(Address(rsi, 4), rbx); 315 316 // 317 // Extended cpuid(0x80000000) 318 // 319 __ bind(ext_cpuid); 320 __ movl(rax, 0x80000000); 321 __ cpuid(); 322 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? 323 __ jcc(Assembler::belowEqual, done); 324 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? 325 __ jccb(Assembler::belowEqual, ext_cpuid1); 326 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported? 327 __ jccb(Assembler::belowEqual, ext_cpuid5); 328 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? 329 __ jccb(Assembler::belowEqual, ext_cpuid7); 330 // 331 // Extended cpuid(0x80000008) 332 // 333 __ movl(rax, 0x80000008); 334 __ cpuid(); 335 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); 336 __ movl(Address(rsi, 0), rax); 337 __ movl(Address(rsi, 4), rbx); 338 __ movl(Address(rsi, 8), rcx); 339 __ movl(Address(rsi,12), rdx); 340 341 // 342 // Extended cpuid(0x80000007) 343 // 344 __ bind(ext_cpuid7); 345 __ movl(rax, 0x80000007); 346 __ cpuid(); 347 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset()))); 348 __ movl(Address(rsi, 0), rax); 349 __ movl(Address(rsi, 4), rbx); 350 __ movl(Address(rsi, 8), rcx); 351 __ movl(Address(rsi,12), rdx); 352 353 // 354 // Extended cpuid(0x80000005) 355 // 356 __ bind(ext_cpuid5); 357 __ movl(rax, 0x80000005); 358 __ cpuid(); 359 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); 360 __ movl(Address(rsi, 0), rax); 361 __ movl(Address(rsi, 4), rbx); 362 __ movl(Address(rsi, 8), rcx); 363 __ movl(Address(rsi,12), rdx); 364 365 // 366 // Extended cpuid(0x80000001) 367 // 368 __ bind(ext_cpuid1); 369 __ movl(rax, 0x80000001); 370 __ cpuid(); 371 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); 372 __ movl(Address(rsi, 0), rax); 373 __ movl(Address(rsi, 4), rbx); 374 __ movl(Address(rsi, 8), rcx); 375 __ movl(Address(rsi,12), rdx); 376 377 // 378 // return 379 // 380 __ bind(done); 381 __ popf(); 382 __ pop(rsi); 383 __ pop(rbx); 384 __ pop(rbp); 385 __ ret(0); 386 387 # undef __ 388 389 return start; 390 }; 391 }; 392 393 394 void VM_Version::get_cpu_info_wrapper() { 395 get_cpu_info_stub(&_cpuid_info); 396 } 397 398 #ifndef CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED 399 #define CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(f) f() 400 #endif 401 402 void VM_Version::get_processor_features() { 403 404 _cpu = 4; // 486 by default 405 _model = 0; 406 _stepping = 0; 407 _cpuFeatures = 0; 408 _logical_processors_per_package = 1; 409 410 if (!Use486InstrsOnly) { 411 // Get raw processor info 412 413 // Some platforms (like Win*) need a wrapper around here 414 // in order to properly handle SEGV for YMM registers test. 415 CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(get_cpu_info_wrapper); 416 417 assert_is_initialized(); 418 _cpu = extended_cpu_family(); 419 _model = extended_cpu_model(); 420 _stepping = cpu_stepping(); 421 422 if (cpu_family() > 4) { // it supports CPUID 423 _cpuFeatures = feature_flags(); 424 // Logical processors are only available on P4s and above, 425 // and only if hyperthreading is available. 426 _logical_processors_per_package = logical_processor_count(); 427 } 428 } 429 430 _supports_cx8 = supports_cmpxchg8(); 431 // xchg and xadd instructions 432 _supports_atomic_getset4 = true; 433 _supports_atomic_getadd4 = true; 434 LP64_ONLY(_supports_atomic_getset8 = true); 435 LP64_ONLY(_supports_atomic_getadd8 = true); 436 437 #ifdef _LP64 438 // OS should support SSE for x64 and hardware should support at least SSE2. 439 if (!VM_Version::supports_sse2()) { 440 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); 441 } 442 // in 64 bit the use of SSE2 is the minimum 443 if (UseSSE < 2) UseSSE = 2; 444 #endif 445 446 #ifdef AMD64 447 // flush_icache_stub have to be generated first. 448 // That is why Icache line size is hard coded in ICache class, 449 // see icache_x86.hpp. It is also the reason why we can't use 450 // clflush instruction in 32-bit VM since it could be running 451 // on CPU which does not support it. 452 // 453 // The only thing we can do is to verify that flushed 454 // ICache::line_size has correct value. 455 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported"); 456 // clflush_size is size in quadwords (8 bytes). 457 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported"); 458 #endif 459 460 // If the OS doesn't support SSE, we can't use this feature even if the HW does 461 if (!os::supports_sse()) 462 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); 463 464 if (UseSSE < 4) { 465 _cpuFeatures &= ~CPU_SSE4_1; 466 _cpuFeatures &= ~CPU_SSE4_2; 467 } 468 469 if (UseSSE < 3) { 470 _cpuFeatures &= ~CPU_SSE3; 471 _cpuFeatures &= ~CPU_SSSE3; 472 _cpuFeatures &= ~CPU_SSE4A; 473 } 474 475 if (UseSSE < 2) 476 _cpuFeatures &= ~CPU_SSE2; 477 478 if (UseSSE < 1) 479 _cpuFeatures &= ~CPU_SSE; 480 481 if (UseAVX < 2) 482 _cpuFeatures &= ~CPU_AVX2; 483 484 if (UseAVX < 1) 485 _cpuFeatures &= ~CPU_AVX; 486 487 if (!UseAES && !FLAG_IS_DEFAULT(UseAES)) 488 _cpuFeatures &= ~CPU_AES; 489 490 if (logical_processors_per_package() == 1) { 491 // HT processor could be installed on a system which doesn't support HT. 492 _cpuFeatures &= ~CPU_HT; 493 } 494 495 char buf[256]; 496 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 497 cores_per_cpu(), threads_per_core(), 498 cpu_family(), _model, _stepping, 499 (supports_cmov() ? ", cmov" : ""), 500 (supports_cmpxchg8() ? ", cx8" : ""), 501 (supports_fxsr() ? ", fxsr" : ""), 502 (supports_mmx() ? ", mmx" : ""), 503 (supports_sse() ? ", sse" : ""), 504 (supports_sse2() ? ", sse2" : ""), 505 (supports_sse3() ? ", sse3" : ""), 506 (supports_ssse3()? ", ssse3": ""), 507 (supports_sse4_1() ? ", sse4.1" : ""), 508 (supports_sse4_2() ? ", sse4.2" : ""), 509 (supports_popcnt() ? ", popcnt" : ""), 510 (supports_avx() ? ", avx" : ""), 511 (supports_avx2() ? ", avx2" : ""), 512 (supports_aes() ? ", aes" : ""), 513 (supports_clmul() ? ", clmul" : ""), 514 (supports_erms() ? ", erms" : ""), 515 (supports_rtm() ? ", rtm" : ""), 516 (supports_mmx_ext() ? ", mmxext" : ""), 517 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""), 518 (supports_lzcnt() ? ", lzcnt": ""), 519 (supports_sse4a() ? ", sse4a": ""), 520 (supports_ht() ? ", ht": ""), 521 (supports_tsc() ? ", tsc": ""), 522 (supports_tscinv_bit() ? ", tscinvbit": ""), 523 (supports_tscinv() ? ", tscinv": ""), 524 (supports_bmi1() ? ", bmi1" : ""), 525 (supports_bmi2() ? ", bmi2" : "")); 526 _features_str = strdup(buf); 527 528 // UseSSE is set to the smaller of what hardware supports and what 529 // the command line requires. I.e., you cannot set UseSSE to 2 on 530 // older Pentiums which do not support it. 531 if (UseSSE > 4) UseSSE=4; 532 if (UseSSE < 0) UseSSE=0; 533 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support 534 UseSSE = MIN2((intx)3,UseSSE); 535 if (!supports_sse3()) // Drop to 2 if no SSE3 support 536 UseSSE = MIN2((intx)2,UseSSE); 537 if (!supports_sse2()) // Drop to 1 if no SSE2 support 538 UseSSE = MIN2((intx)1,UseSSE); 539 if (!supports_sse ()) // Drop to 0 if no SSE support 540 UseSSE = 0; 541 542 if (UseAVX > 2) UseAVX=2; 543 if (UseAVX < 0) UseAVX=0; 544 if (!supports_avx2()) // Drop to 1 if no AVX2 support 545 UseAVX = MIN2((intx)1,UseAVX); 546 if (!supports_avx ()) // Drop to 0 if no AVX support 547 UseAVX = 0; 548 549 // Use AES instructions if available. 550 if (supports_aes()) { 551 if (FLAG_IS_DEFAULT(UseAES)) { 552 UseAES = true; 553 } 554 } else if (UseAES) { 555 if (!FLAG_IS_DEFAULT(UseAES)) 556 warning("AES instructions are not available on this CPU"); 557 FLAG_SET_DEFAULT(UseAES, false); 558 } 559 560 // Use CLMUL instructions if available. 561 if (supports_clmul()) { 562 if (FLAG_IS_DEFAULT(UseCLMUL)) { 563 UseCLMUL = true; 564 } 565 } else if (UseCLMUL) { 566 if (!FLAG_IS_DEFAULT(UseCLMUL)) 567 warning("CLMUL instructions not available on this CPU (AVX may also be required)"); 568 FLAG_SET_DEFAULT(UseCLMUL, false); 569 } 570 571 if (UseCLMUL && (UseAVX > 0) && (UseSSE > 2)) { 572 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 573 UseCRC32Intrinsics = true; 574 } 575 } else if (UseCRC32Intrinsics) { 576 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics)) 577 warning("CRC32 Intrinsics requires AVX and CLMUL instructions (not available on this CPU)"); 578 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); 579 } 580 581 // The AES intrinsic stubs require AES instruction support (of course) 582 // but also require sse3 mode for instructions it use. 583 if (UseAES && (UseSSE > 2)) { 584 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { 585 UseAESIntrinsics = true; 586 } 587 } else if (UseAESIntrinsics) { 588 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) 589 warning("AES intrinsics are not available on this CPU"); 590 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 591 } 592 593 if (UseSHA) { 594 warning("SHA instructions are not available on this CPU"); 595 FLAG_SET_DEFAULT(UseSHA, false); 596 } 597 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) { 598 warning("SHA intrinsics are not available on this CPU"); 599 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 600 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 601 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 602 } 603 604 // Adjust RTM (Restricted Transactional Memory) flags 605 if (!supports_rtm() && UseRTMLocking) { 606 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 607 // setting during arguments processing. See use_biased_locking(). 608 // VM_Version_init() is executed after UseBiasedLocking is used 609 // in Thread::allocate(). 610 vm_exit_during_initialization("RTM instructions are not available on this CPU"); 611 } 612 613 #if INCLUDE_RTM_OPT 614 if (UseRTMLocking) { 615 if (!FLAG_IS_CMDLINE(UseRTMLocking)) { 616 // RTM locking should be used only for applications with 617 // high lock contention. For now we do not use it by default. 618 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); 619 } 620 if (!is_power_of_2(RTMTotalCountIncrRate)) { 621 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64"); 622 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64); 623 } 624 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) { 625 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50"); 626 FLAG_SET_DEFAULT(RTMAbortRatio, 50); 627 } 628 } else { // !UseRTMLocking 629 if (UseRTMForStackLocks) { 630 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) { 631 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off"); 632 } 633 FLAG_SET_DEFAULT(UseRTMForStackLocks, false); 634 } 635 if (UseRTMDeopt) { 636 FLAG_SET_DEFAULT(UseRTMDeopt, false); 637 } 638 if (PrintPreciseRTMLockingStatistics) { 639 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false); 640 } 641 } 642 #else 643 if (UseRTMLocking) { 644 // Only C2 does RTM locking optimization. 645 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 646 // setting during arguments processing. See use_biased_locking(). 647 vm_exit_during_initialization("RTM locking optimization is not supported in this VM"); 648 } 649 #endif 650 651 #ifdef COMPILER2 652 if (UseFPUForSpilling) { 653 if (UseSSE < 2) { 654 // Only supported with SSE2+ 655 FLAG_SET_DEFAULT(UseFPUForSpilling, false); 656 } 657 } 658 if (MaxVectorSize > 0) { 659 if (!is_power_of_2(MaxVectorSize)) { 660 warning("MaxVectorSize must be a power of 2"); 661 FLAG_SET_DEFAULT(MaxVectorSize, 32); 662 } 663 if (MaxVectorSize > 32) { 664 FLAG_SET_DEFAULT(MaxVectorSize, 32); 665 } 666 if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) { 667 // 32 bytes vectors (in YMM) are only supported with AVX+ 668 FLAG_SET_DEFAULT(MaxVectorSize, 16); 669 } 670 if (UseSSE < 2) { 671 // Vectors (in XMM) are only supported with SSE2+ 672 FLAG_SET_DEFAULT(MaxVectorSize, 0); 673 } 674 #ifdef ASSERT 675 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) { 676 tty->print_cr("State of YMM registers after signal handle:"); 677 int nreg = 2 LP64_ONLY(+2); 678 const char* ymm_name[4] = {"0", "7", "8", "15"}; 679 for (int i = 0; i < nreg; i++) { 680 tty->print("YMM%s:", ymm_name[i]); 681 for (int j = 7; j >=0; j--) { 682 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]); 683 } 684 tty->cr(); 685 } 686 } 687 #endif 688 } 689 #endif 690 691 // On new cpus instructions which update whole XMM register should be used 692 // to prevent partial register stall due to dependencies on high half. 693 // 694 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) 695 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) 696 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). 697 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). 698 699 if( is_amd() ) { // AMD cpus specific settings 700 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { 701 // Use it on new AMD cpus starting from Opteron. 702 UseAddressNop = true; 703 } 704 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { 705 // Use it on new AMD cpus starting from Opteron. 706 UseNewLongLShift = true; 707 } 708 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { 709 if( supports_sse4a() ) { 710 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron 711 } else { 712 UseXmmLoadAndClearUpper = false; 713 } 714 } 715 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { 716 if( supports_sse4a() ) { 717 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' 718 } else { 719 UseXmmRegToRegMoveAll = false; 720 } 721 } 722 if( FLAG_IS_DEFAULT(UseXmmI2F) ) { 723 if( supports_sse4a() ) { 724 UseXmmI2F = true; 725 } else { 726 UseXmmI2F = false; 727 } 728 } 729 if( FLAG_IS_DEFAULT(UseXmmI2D) ) { 730 if( supports_sse4a() ) { 731 UseXmmI2D = true; 732 } else { 733 UseXmmI2D = false; 734 } 735 } 736 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) { 737 if( supports_sse4_2() && UseSSE >= 4 ) { 738 UseSSE42Intrinsics = true; 739 } 740 } 741 742 // some defaults for AMD family 15h 743 if ( cpu_family() == 0x15 ) { 744 // On family 15h processors default is no sw prefetch 745 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { 746 AllocatePrefetchStyle = 0; 747 } 748 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW 749 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { 750 AllocatePrefetchInstr = 3; 751 } 752 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy 753 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { 754 UseXMMForArrayCopy = true; 755 } 756 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { 757 UseUnalignedLoadStores = true; 758 } 759 } 760 761 #ifdef COMPILER2 762 if (MaxVectorSize > 16) { 763 // Limit vectors size to 16 bytes on current AMD cpus. 764 FLAG_SET_DEFAULT(MaxVectorSize, 16); 765 } 766 #endif // COMPILER2 767 } 768 769 if( is_intel() ) { // Intel cpus specific settings 770 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { 771 UseStoreImmI16 = false; // don't use it on Intel cpus 772 } 773 if( cpu_family() == 6 || cpu_family() == 15 ) { 774 if( FLAG_IS_DEFAULT(UseAddressNop) ) { 775 // Use it on all Intel cpus starting from PentiumPro 776 UseAddressNop = true; 777 } 778 } 779 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { 780 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus 781 } 782 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { 783 if( supports_sse3() ) { 784 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus 785 } else { 786 UseXmmRegToRegMoveAll = false; 787 } 788 } 789 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus 790 #ifdef COMPILER2 791 if( FLAG_IS_DEFAULT(MaxLoopPad) ) { 792 // For new Intel cpus do the next optimization: 793 // don't align the beginning of a loop if there are enough instructions 794 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) 795 // in current fetch line (OptoLoopAlignment) or the padding 796 // is big (> MaxLoopPad). 797 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of 798 // generated NOP instructions. 11 is the largest size of one 799 // address NOP instruction '0F 1F' (see Assembler::nop(i)). 800 MaxLoopPad = 11; 801 } 802 #endif // COMPILER2 803 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { 804 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus 805 } 806 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus 807 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { 808 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus 809 } 810 } 811 if (supports_sse4_2() && UseSSE >= 4) { 812 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { 813 UseSSE42Intrinsics = true; 814 } 815 } 816 } 817 } 818 819 // Use count leading zeros count instruction if available. 820 if (supports_lzcnt()) { 821 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { 822 UseCountLeadingZerosInstruction = true; 823 } 824 } else if (UseCountLeadingZerosInstruction) { 825 warning("lzcnt instruction is not available on this CPU"); 826 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false); 827 } 828 829 if (supports_bmi1()) { 830 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) { 831 UseBMI1Instructions = true; 832 } 833 } else if (UseBMI1Instructions) { 834 warning("BMI1 instructions are not available on this CPU"); 835 FLAG_SET_DEFAULT(UseBMI1Instructions, false); 836 } 837 838 // Use count trailing zeros instruction if available 839 if (supports_bmi1()) { 840 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) { 841 UseCountTrailingZerosInstruction = UseBMI1Instructions; 842 } 843 } else if (UseCountTrailingZerosInstruction) { 844 warning("tzcnt instruction is not available on this CPU"); 845 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false); 846 } 847 848 // Use population count instruction if available. 849 if (supports_popcnt()) { 850 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { 851 UsePopCountInstruction = true; 852 } 853 } else if (UsePopCountInstruction) { 854 warning("POPCNT instruction is not available on this CPU"); 855 FLAG_SET_DEFAULT(UsePopCountInstruction, false); 856 } 857 858 // Use fast-string operations if available. 859 if (supports_erms()) { 860 if (FLAG_IS_DEFAULT(UseFastStosb)) { 861 UseFastStosb = true; 862 } 863 } else if (UseFastStosb) { 864 warning("fast-string operations are not available on this CPU"); 865 FLAG_SET_DEFAULT(UseFastStosb, false); 866 } 867 868 #ifdef COMPILER2 869 if (FLAG_IS_DEFAULT(AlignVector)) { 870 // Modern processors allow misaligned memory operations for vectors. 871 AlignVector = !UseUnalignedLoadStores; 872 } 873 #endif // COMPILER2 874 875 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); 876 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); 877 878 // set valid Prefetch instruction 879 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; 880 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3; 881 if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0; 882 if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3; 883 884 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; 885 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; 886 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0; 887 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3; 888 889 // Allocation prefetch settings 890 intx cache_line_size = prefetch_data_size(); 891 if( cache_line_size > AllocatePrefetchStepSize ) 892 AllocatePrefetchStepSize = cache_line_size; 893 894 assert(AllocatePrefetchLines > 0, "invalid value"); 895 if( AllocatePrefetchLines < 1 ) // set valid value in product VM 896 AllocatePrefetchLines = 3; 897 assert(AllocateInstancePrefetchLines > 0, "invalid value"); 898 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM 899 AllocateInstancePrefetchLines = 1; 900 901 AllocatePrefetchDistance = allocate_prefetch_distance(); 902 AllocatePrefetchStyle = allocate_prefetch_style(); 903 904 if( is_intel() && cpu_family() == 6 && supports_sse3() ) { 905 if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core 906 #ifdef _LP64 907 AllocatePrefetchDistance = 384; 908 #else 909 AllocatePrefetchDistance = 320; 910 #endif 911 } 912 if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus 913 AllocatePrefetchDistance = 192; 914 AllocatePrefetchLines = 4; 915 #ifdef COMPILER2 916 if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) { 917 FLAG_SET_DEFAULT(UseFPUForSpilling, true); 918 } 919 #endif 920 } 921 } 922 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); 923 924 #ifdef _LP64 925 // Prefetch settings 926 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); 927 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); 928 PrefetchFieldsAhead = prefetch_fields_ahead(); 929 #endif 930 931 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && 932 (cache_line_size > ContendedPaddingWidth)) 933 ContendedPaddingWidth = cache_line_size; 934 935 #ifndef PRODUCT 936 if (PrintMiscellaneous && Verbose) { 937 tty->print_cr("Logical CPUs per core: %u", 938 logical_processors_per_package()); 939 tty->print("UseSSE=%d", (int) UseSSE); 940 if (UseAVX > 0) { 941 tty->print(" UseAVX=%d", (int) UseAVX); 942 } 943 if (UseAES) { 944 tty->print(" UseAES=1"); 945 } 946 #ifdef COMPILER2 947 if (MaxVectorSize > 0) { 948 tty->print(" MaxVectorSize=%d", (int) MaxVectorSize); 949 } 950 #endif 951 tty->cr(); 952 tty->print("Allocation"); 953 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) { 954 tty->print_cr(": no prefetching"); 955 } else { 956 tty->print(" prefetching: "); 957 if (UseSSE == 0 && supports_3dnow_prefetch()) { 958 tty->print("PREFETCHW"); 959 } else if (UseSSE >= 1) { 960 if (AllocatePrefetchInstr == 0) { 961 tty->print("PREFETCHNTA"); 962 } else if (AllocatePrefetchInstr == 1) { 963 tty->print("PREFETCHT0"); 964 } else if (AllocatePrefetchInstr == 2) { 965 tty->print("PREFETCHT2"); 966 } else if (AllocatePrefetchInstr == 3) { 967 tty->print("PREFETCHW"); 968 } 969 } 970 if (AllocatePrefetchLines > 1) { 971 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); 972 } else { 973 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); 974 } 975 } 976 977 if (PrefetchCopyIntervalInBytes > 0) { 978 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); 979 } 980 if (PrefetchScanIntervalInBytes > 0) { 981 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); 982 } 983 if (PrefetchFieldsAhead > 0) { 984 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); 985 } 986 if (ContendedPaddingWidth > 0) { 987 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); 988 } 989 } 990 #endif // !PRODUCT 991 } 992 993 bool VM_Version::use_biased_locking() { 994 #if INCLUDE_RTM_OPT 995 // RTM locking is most useful when there is high lock contention and 996 // low data contention. With high lock contention the lock is usually 997 // inflated and biased locking is not suitable for that case. 998 // RTM locking code requires that biased locking is off. 999 // Note: we can't switch off UseBiasedLocking in get_processor_features() 1000 // because it is used by Thread::allocate() which is called before 1001 // VM_Version::initialize(). 1002 if (UseRTMLocking && UseBiasedLocking) { 1003 if (FLAG_IS_DEFAULT(UseBiasedLocking)) { 1004 FLAG_SET_DEFAULT(UseBiasedLocking, false); 1005 } else { 1006 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." ); 1007 UseBiasedLocking = false; 1008 } 1009 } 1010 #endif 1011 return UseBiasedLocking; 1012 } 1013 1014 void VM_Version::initialize() { 1015 ResourceMark rm; 1016 // Making this stub must be FIRST use of assembler 1017 1018 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size); 1019 if (stub_blob == NULL) { 1020 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub"); 1021 } 1022 CodeBuffer c(stub_blob); 1023 VM_Version_StubGenerator g(&c); 1024 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t, 1025 g.generate_get_cpu_info()); 1026 1027 get_processor_features(); 1028 }