1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "runtime/java.hpp"
30 #include "runtime/stubCodeGenerator.hpp"
31 #include "vm_version_x86.hpp"
32 #ifdef TARGET_OS_FAMILY_linux
33 # include "os_linux.inline.hpp"
34 #endif
35 #ifdef TARGET_OS_FAMILY_solaris
36 # include "os_solaris.inline.hpp"
37 #endif
38 #ifdef TARGET_OS_FAMILY_windows
39 # include "os_windows.inline.hpp"
40 #endif
41 #ifdef TARGET_OS_FAMILY_bsd
42 # include "os_bsd.inline.hpp"
43 #endif
44
45
46 int VM_Version::_cpu;
47 int VM_Version::_model;
48 int VM_Version::_stepping;
49 int VM_Version::_cpuFeatures;
50 const char* VM_Version::_features_str = "";
51 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
52
53 // Address of instruction which causes SEGV
54 address VM_Version::_cpuinfo_segv_addr = 0;
55 // Address of instruction which causes SEGV
56 address VM_Version::_cpuinfo_cont_addr = 0;
57
58 static BufferBlob* stub_blob;
59 static const int stub_size = 600;
60
61 extern "C" {
62 typedef void (*getPsrInfo_stub_t)(void*);
63 }
64 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
65
66
67 class VM_Version_StubGenerator: public StubCodeGenerator {
68 public:
69
70 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
71
72 address generate_getPsrInfo() {
73 // Flags to test CPU type.
74 const uint32_t HS_EFL_AC = 0x40000;
75 const uint32_t HS_EFL_ID = 0x200000;
76 // Values for when we don't have a CPUID instruction.
77 const int CPU_FAMILY_SHIFT = 8;
78 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
79 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
80
81 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
82 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done;
83
84 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
85 # define __ _masm->
86
87 address start = __ pc();
88
89 //
90 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
91 //
92 // LP64: rcx and rdx are first and second argument registers on windows
93
94 __ push(rbp);
95 #ifdef _LP64
96 __ mov(rbp, c_rarg0); // cpuid_info address
97 #else
98 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
99 #endif
100 __ push(rbx);
101 __ push(rsi);
102 __ pushf(); // preserve rbx, and flags
103 __ pop(rax);
104 __ push(rax);
105 __ mov(rcx, rax);
106 //
107 // if we are unable to change the AC flag, we have a 386
108 //
109 __ xorl(rax, HS_EFL_AC);
110 __ push(rax);
111 __ popf();
112 __ pushf();
113 __ pop(rax);
114 __ cmpptr(rax, rcx);
115 __ jccb(Assembler::notEqual, detect_486);
116
117 __ movl(rax, CPU_FAMILY_386);
118 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
119 __ jmp(done);
120
121 //
122 // If we are unable to change the ID flag, we have a 486 which does
123 // not support the "cpuid" instruction.
124 //
125 __ bind(detect_486);
126 __ mov(rax, rcx);
127 __ xorl(rax, HS_EFL_ID);
128 __ push(rax);
129 __ popf();
130 __ pushf();
131 __ pop(rax);
132 __ cmpptr(rcx, rax);
133 __ jccb(Assembler::notEqual, detect_586);
134
135 __ bind(cpu486);
136 __ movl(rax, CPU_FAMILY_486);
137 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
138 __ jmp(done);
139
140 //
141 // At this point, we have a chip which supports the "cpuid" instruction
142 //
143 __ bind(detect_586);
144 __ xorl(rax, rax);
145 __ cpuid();
146 __ orl(rax, rax);
147 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
148 // value of at least 1, we give up and
149 // assume a 486
150 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
151 __ movl(Address(rsi, 0), rax);
152 __ movl(Address(rsi, 4), rbx);
153 __ movl(Address(rsi, 8), rcx);
154 __ movl(Address(rsi,12), rdx);
155
156 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
157 __ jccb(Assembler::belowEqual, std_cpuid4);
158
159 //
160 // cpuid(0xB) Processor Topology
161 //
162 __ movl(rax, 0xb);
163 __ xorl(rcx, rcx); // Threads level
164 __ cpuid();
165
166 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
167 __ movl(Address(rsi, 0), rax);
168 __ movl(Address(rsi, 4), rbx);
169 __ movl(Address(rsi, 8), rcx);
170 __ movl(Address(rsi,12), rdx);
171
172 __ movl(rax, 0xb);
173 __ movl(rcx, 1); // Cores level
174 __ cpuid();
175 __ push(rax);
176 __ andl(rax, 0x1f); // Determine if valid topology level
177 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
178 __ andl(rax, 0xffff);
179 __ pop(rax);
180 __ jccb(Assembler::equal, std_cpuid4);
181
182 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
183 __ movl(Address(rsi, 0), rax);
184 __ movl(Address(rsi, 4), rbx);
185 __ movl(Address(rsi, 8), rcx);
186 __ movl(Address(rsi,12), rdx);
187
188 __ movl(rax, 0xb);
189 __ movl(rcx, 2); // Packages level
190 __ cpuid();
191 __ push(rax);
192 __ andl(rax, 0x1f); // Determine if valid topology level
193 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
194 __ andl(rax, 0xffff);
195 __ pop(rax);
196 __ jccb(Assembler::equal, std_cpuid4);
197
198 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
199 __ movl(Address(rsi, 0), rax);
200 __ movl(Address(rsi, 4), rbx);
201 __ movl(Address(rsi, 8), rcx);
202 __ movl(Address(rsi,12), rdx);
203
204 //
205 // cpuid(0x4) Deterministic cache params
206 //
207 __ bind(std_cpuid4);
208 __ movl(rax, 4);
209 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
210 __ jccb(Assembler::greater, std_cpuid1);
211
212 __ xorl(rcx, rcx); // L1 cache
213 __ cpuid();
214 __ push(rax);
215 __ andl(rax, 0x1f); // Determine if valid cache parameters used
216 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
217 __ pop(rax);
218 __ jccb(Assembler::equal, std_cpuid1);
219
220 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
221 __ movl(Address(rsi, 0), rax);
222 __ movl(Address(rsi, 4), rbx);
223 __ movl(Address(rsi, 8), rcx);
224 __ movl(Address(rsi,12), rdx);
225
226 //
227 // Standard cpuid(0x1)
228 //
229 __ bind(std_cpuid1);
230 __ movl(rax, 1);
231 __ cpuid();
232 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
233 __ movl(Address(rsi, 0), rax);
234 __ movl(Address(rsi, 4), rbx);
235 __ movl(Address(rsi, 8), rcx);
236 __ movl(Address(rsi,12), rdx);
237
238 //
239 // Check if OS has enabled XGETBV instruction to access XCR0
240 // (OSXSAVE feature flag) and CPU supports AVX
241 //
242 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
243 __ cmpl(rcx, 0x18000000);
244 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
245
246 //
247 // XCR0, XFEATURE_ENABLED_MASK register
248 //
249 __ xorl(rcx, rcx); // zero for XCR0 register
250 __ xgetbv();
251 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
252 __ movl(Address(rsi, 0), rax);
253 __ movl(Address(rsi, 4), rdx);
254
255 __ andl(rax, 0x6); // xcr0 bits sse | ymm
256 __ cmpl(rax, 0x6);
257 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
258
259 //
260 // Some OSs have a bug when upper 128bits of YMM
261 // registers are not restored after a signal processing.
262 // Generate SEGV here (reference through NULL)
263 // and check upper YMM bits after it.
264 //
265 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
266
267 // load value into all 32 bytes of ymm7 register
268 __ movl(rcx, VM_Version::ymm_test_value());
269
270 __ movdl(xmm0, rcx);
271 __ pshufd(xmm0, xmm0, 0x00);
272 __ vinsertf128h(xmm0, xmm0, xmm0);
273 __ vmovdqu(xmm7, xmm0);
274 #ifdef _LP64
275 __ vmovdqu(xmm8, xmm0);
276 __ vmovdqu(xmm15, xmm0);
277 #endif
278
279 __ xorl(rsi, rsi);
280 VM_Version::set_cpuinfo_segv_addr( __ pc() );
281 // Generate SEGV
282 __ movl(rax, Address(rsi, 0));
283
284 VM_Version::set_cpuinfo_cont_addr( __ pc() );
285 // Returns here after signal. Save xmm0 to check it later.
286 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
287 __ vmovdqu(Address(rsi, 0), xmm0);
288 __ vmovdqu(Address(rsi, 32), xmm7);
289 #ifdef _LP64
290 __ vmovdqu(Address(rsi, 64), xmm8);
291 __ vmovdqu(Address(rsi, 96), xmm15);
292 #endif
293
294 VM_Version::clean_cpuFeatures();
295
296 //
297 // cpuid(0x7) Structured Extended Features
298 //
299 __ bind(sef_cpuid);
300 __ movl(rax, 7);
301 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
302 __ jccb(Assembler::greater, ext_cpuid);
303
304 __ xorl(rcx, rcx);
305 __ cpuid();
306 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
307 __ movl(Address(rsi, 0), rax);
308 __ movl(Address(rsi, 4), rbx);
309
310 //
311 // Extended cpuid(0x80000000)
312 //
313 __ bind(ext_cpuid);
314 __ movl(rax, 0x80000000);
315 __ cpuid();
316 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
317 __ jcc(Assembler::belowEqual, done);
318 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
319 __ jccb(Assembler::belowEqual, ext_cpuid1);
320 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported?
321 __ jccb(Assembler::belowEqual, ext_cpuid5);
322 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
323 __ jccb(Assembler::belowEqual, ext_cpuid7);
324 //
325 // Extended cpuid(0x80000008)
326 //
327 __ movl(rax, 0x80000008);
328 __ cpuid();
329 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
330 __ movl(Address(rsi, 0), rax);
331 __ movl(Address(rsi, 4), rbx);
332 __ movl(Address(rsi, 8), rcx);
333 __ movl(Address(rsi,12), rdx);
334
335 //
336 // Extended cpuid(0x80000007)
337 //
338 __ bind(ext_cpuid7);
339 __ movl(rax, 0x80000007);
340 __ cpuid();
341 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
342 __ movl(Address(rsi, 0), rax);
343 __ movl(Address(rsi, 4), rbx);
344 __ movl(Address(rsi, 8), rcx);
345 __ movl(Address(rsi,12), rdx);
346
347 //
348 // Extended cpuid(0x80000005)
349 //
350 __ bind(ext_cpuid5);
351 __ movl(rax, 0x80000005);
352 __ cpuid();
353 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
354 __ movl(Address(rsi, 0), rax);
355 __ movl(Address(rsi, 4), rbx);
356 __ movl(Address(rsi, 8), rcx);
357 __ movl(Address(rsi,12), rdx);
358
359 //
360 // Extended cpuid(0x80000001)
361 //
362 __ bind(ext_cpuid1);
363 __ movl(rax, 0x80000001);
364 __ cpuid();
365 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
366 __ movl(Address(rsi, 0), rax);
367 __ movl(Address(rsi, 4), rbx);
368 __ movl(Address(rsi, 8), rcx);
369 __ movl(Address(rsi,12), rdx);
370
371 //
372 // return
373 //
374 __ bind(done);
375 __ popf();
376 __ pop(rsi);
377 __ pop(rbx);
378 __ pop(rbp);
379 __ ret(0);
380
381 # undef __
382
383 return start;
384 };
385 };
386
387
388 void VM_Version::get_processor_features() {
389
390 _cpu = 4; // 486 by default
391 _model = 0;
392 _stepping = 0;
393 _cpuFeatures = 0;
394 _logical_processors_per_package = 1;
395
396 if (!Use486InstrsOnly) {
397 // Get raw processor info
398 getPsrInfo_stub(&_cpuid_info);
399 assert_is_initialized();
400 _cpu = extended_cpu_family();
401 _model = extended_cpu_model();
402 _stepping = cpu_stepping();
403
404 if (cpu_family() > 4) { // it supports CPUID
405 _cpuFeatures = feature_flags();
406 // Logical processors are only available on P4s and above,
407 // and only if hyperthreading is available.
408 _logical_processors_per_package = logical_processor_count();
409 }
410 }
411
412 _supports_cx8 = supports_cmpxchg8();
413 // xchg and xadd instructions
414 _supports_atomic_getset4 = true;
415 _supports_atomic_getadd4 = true;
416 LP64_ONLY(_supports_atomic_getset8 = true);
417 LP64_ONLY(_supports_atomic_getadd8 = true);
418
419 #ifdef _LP64
420 // OS should support SSE for x64 and hardware should support at least SSE2.
421 if (!VM_Version::supports_sse2()) {
422 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
423 }
424 // in 64 bit the use of SSE2 is the minimum
425 if (UseSSE < 2) UseSSE = 2;
426 #endif
427
428 #ifdef AMD64
429 // flush_icache_stub have to be generated first.
430 // That is why Icache line size is hard coded in ICache class,
431 // see icache_x86.hpp. It is also the reason why we can't use
432 // clflush instruction in 32-bit VM since it could be running
433 // on CPU which does not support it.
434 //
435 // The only thing we can do is to verify that flushed
436 // ICache::line_size has correct value.
437 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
438 // clflush_size is size in quadwords (8 bytes).
439 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
440 #endif
441
442 // If the OS doesn't support SSE, we can't use this feature even if the HW does
443 if (!os::supports_sse())
444 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
445
446 if (UseSSE < 4) {
447 _cpuFeatures &= ~CPU_SSE4_1;
448 _cpuFeatures &= ~CPU_SSE4_2;
449 }
450
451 if (UseSSE < 3) {
452 _cpuFeatures &= ~CPU_SSE3;
453 _cpuFeatures &= ~CPU_SSSE3;
454 _cpuFeatures &= ~CPU_SSE4A;
455 }
456
457 if (UseSSE < 2)
458 _cpuFeatures &= ~CPU_SSE2;
459
460 if (UseSSE < 1)
461 _cpuFeatures &= ~CPU_SSE;
462
463 if (UseAVX < 2)
464 _cpuFeatures &= ~CPU_AVX2;
465
466 if (UseAVX < 1)
467 _cpuFeatures &= ~CPU_AVX;
468
469 if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
470 _cpuFeatures &= ~CPU_AES;
471
472 if (logical_processors_per_package() == 1) {
473 // HT processor could be installed on a system which doesn't support HT.
474 _cpuFeatures &= ~CPU_HT;
475 }
476
477 char buf[256];
478 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
479 cores_per_cpu(), threads_per_core(),
480 cpu_family(), _model, _stepping,
481 (supports_cmov() ? ", cmov" : ""),
482 (supports_cmpxchg8() ? ", cx8" : ""),
483 (supports_fxsr() ? ", fxsr" : ""),
484 (supports_mmx() ? ", mmx" : ""),
485 (supports_sse() ? ", sse" : ""),
486 (supports_sse2() ? ", sse2" : ""),
487 (supports_sse3() ? ", sse3" : ""),
488 (supports_ssse3()? ", ssse3": ""),
489 (supports_sse4_1() ? ", sse4.1" : ""),
490 (supports_sse4_2() ? ", sse4.2" : ""),
491 (supports_popcnt() ? ", popcnt" : ""),
492 (supports_avx() ? ", avx" : ""),
493 (supports_avx2() ? ", avx2" : ""),
494 (supports_aes() ? ", aes" : ""),
495 (supports_clmul() ? ", clmul" : ""),
496 (supports_erms() ? ", erms" : ""),
497 (supports_mmx_ext() ? ", mmxext" : ""),
498 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
499 (supports_lzcnt() ? ", lzcnt": ""),
500 (supports_sse4a() ? ", sse4a": ""),
501 (supports_ht() ? ", ht": ""),
502 (supports_tsc() ? ", tsc": ""),
503 (supports_tscinv_bit() ? ", tscinvbit": ""),
504 (supports_tscinv() ? ", tscinv": ""),
505 (supports_bmi1() ? ", bmi1" : ""),
506 (supports_bmi2() ? ", bmi2" : ""));
507 _features_str = strdup(buf);
508
509 // UseSSE is set to the smaller of what hardware supports and what
510 // the command line requires. I.e., you cannot set UseSSE to 2 on
511 // older Pentiums which do not support it.
512 if (UseSSE > 4) UseSSE=4;
513 if (UseSSE < 0) UseSSE=0;
514 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
515 UseSSE = MIN2((intx)3,UseSSE);
516 if (!supports_sse3()) // Drop to 2 if no SSE3 support
517 UseSSE = MIN2((intx)2,UseSSE);
518 if (!supports_sse2()) // Drop to 1 if no SSE2 support
519 UseSSE = MIN2((intx)1,UseSSE);
520 if (!supports_sse ()) // Drop to 0 if no SSE support
521 UseSSE = 0;
522
523 if (UseAVX > 2) UseAVX=2;
524 if (UseAVX < 0) UseAVX=0;
525 if (!supports_avx2()) // Drop to 1 if no AVX2 support
526 UseAVX = MIN2((intx)1,UseAVX);
527 if (!supports_avx ()) // Drop to 0 if no AVX support
528 UseAVX = 0;
529
530 // Use AES instructions if available.
531 if (supports_aes()) {
532 if (FLAG_IS_DEFAULT(UseAES)) {
533 UseAES = true;
534 }
535 } else if (UseAES) {
536 if (!FLAG_IS_DEFAULT(UseAES))
537 warning("AES instructions not available on this CPU");
538 FLAG_SET_DEFAULT(UseAES, false);
539 }
540
541 // Use CLMUL instructions if available.
542 if (supports_clmul()) {
543 if (FLAG_IS_DEFAULT(UseCLMUL)) {
544 UseCLMUL = true;
545 }
546 } else if (UseCLMUL) {
547 if (!FLAG_IS_DEFAULT(UseCLMUL))
548 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
549 FLAG_SET_DEFAULT(UseCLMUL, false);
550 }
551
552 if (UseCLMUL && (UseAVX > 0) && (UseSSE > 2)) {
553 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
554 UseCRC32Intrinsics = true;
555 }
556 } else if (UseCRC32Intrinsics) {
557 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
558 warning("CRC32 Intrinsics requires AVX and CLMUL instructions (not available on this CPU)");
559 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
560 }
561
562 // The AES intrinsic stubs require AES instruction support (of course)
563 // but also require sse3 mode for instructions it use.
564 if (UseAES && (UseSSE > 2)) {
565 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
566 UseAESIntrinsics = true;
567 }
568 } else if (UseAESIntrinsics) {
569 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
570 warning("AES intrinsics not available on this CPU");
571 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
572 }
573
574 #ifdef COMPILER2
575 if (UseFPUForSpilling) {
576 if (UseSSE < 2) {
577 // Only supported with SSE2+
578 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
579 }
580 }
581 if (MaxVectorSize > 0) {
582 if (!is_power_of_2(MaxVectorSize)) {
583 warning("MaxVectorSize must be a power of 2");
584 FLAG_SET_DEFAULT(MaxVectorSize, 32);
585 }
586 if (MaxVectorSize > 32) {
587 FLAG_SET_DEFAULT(MaxVectorSize, 32);
588 }
589 if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) {
590 // 32 bytes vectors (in YMM) are only supported with AVX+
591 FLAG_SET_DEFAULT(MaxVectorSize, 16);
592 }
593 if (UseSSE < 2) {
594 // Vectors (in XMM) are only supported with SSE2+
595 FLAG_SET_DEFAULT(MaxVectorSize, 0);
596 }
597 #ifdef ASSERT
598 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
599 tty->print_cr("State of YMM registers after signal handle:");
600 int nreg = 2 LP64_ONLY(+2);
601 const char* ymm_name[4] = {"0", "7", "8", "15"};
602 for (int i = 0; i < nreg; i++) {
603 tty->print("YMM%s:", ymm_name[i]);
604 for (int j = 7; j >=0; j--) {
605 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
606 }
607 tty->cr();
608 }
609 }
610 #endif
611 }
612 #endif
613
614 // On new cpus instructions which update whole XMM register should be used
615 // to prevent partial register stall due to dependencies on high half.
616 //
617 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
618 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
619 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
620 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
621
622 if( is_amd() ) { // AMD cpus specific settings
623 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
624 // Use it on new AMD cpus starting from Opteron.
625 UseAddressNop = true;
626 }
627 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
628 // Use it on new AMD cpus starting from Opteron.
629 UseNewLongLShift = true;
630 }
631 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
632 if( supports_sse4a() ) {
633 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
634 } else {
635 UseXmmLoadAndClearUpper = false;
636 }
637 }
638 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
639 if( supports_sse4a() ) {
640 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
641 } else {
642 UseXmmRegToRegMoveAll = false;
643 }
644 }
645 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
646 if( supports_sse4a() ) {
647 UseXmmI2F = true;
648 } else {
649 UseXmmI2F = false;
650 }
651 }
652 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
653 if( supports_sse4a() ) {
654 UseXmmI2D = true;
655 } else {
656 UseXmmI2D = false;
657 }
658 }
659 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) {
660 if( supports_sse4_2() && UseSSE >= 4 ) {
661 UseSSE42Intrinsics = true;
662 }
663 }
664
665 // some defaults for AMD family 15h
666 if ( cpu_family() == 0x15 ) {
667 // On family 15h processors default is no sw prefetch
668 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
669 AllocatePrefetchStyle = 0;
670 }
671 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
672 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
673 AllocatePrefetchInstr = 3;
674 }
675 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
676 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
677 UseXMMForArrayCopy = true;
678 }
679 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
680 UseUnalignedLoadStores = true;
681 }
682 }
683
684 #ifdef COMPILER2
685 if (MaxVectorSize > 16) {
686 // Limit vectors size to 16 bytes on current AMD cpus.
687 FLAG_SET_DEFAULT(MaxVectorSize, 16);
688 }
689 #endif // COMPILER2
690 }
691
692 if( is_intel() ) { // Intel cpus specific settings
693 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
694 UseStoreImmI16 = false; // don't use it on Intel cpus
695 }
696 if( cpu_family() == 6 || cpu_family() == 15 ) {
697 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
698 // Use it on all Intel cpus starting from PentiumPro
699 UseAddressNop = true;
700 }
701 }
702 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
703 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
704 }
705 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
706 if( supports_sse3() ) {
707 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
708 } else {
709 UseXmmRegToRegMoveAll = false;
710 }
711 }
712 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
713 #ifdef COMPILER2
714 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
715 // For new Intel cpus do the next optimization:
716 // don't align the beginning of a loop if there are enough instructions
717 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
718 // in current fetch line (OptoLoopAlignment) or the padding
719 // is big (> MaxLoopPad).
720 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
721 // generated NOP instructions. 11 is the largest size of one
722 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
723 MaxLoopPad = 11;
724 }
725 #endif // COMPILER2
726 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
727 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
728 }
729 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
730 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
731 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
732 }
733 }
734 if (supports_sse4_2() && UseSSE >= 4) {
735 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
736 UseSSE42Intrinsics = true;
737 }
738 }
739 }
740 }
741
742 // Use count leading zeros count instruction if available.
743 if (supports_lzcnt()) {
744 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
745 UseCountLeadingZerosInstruction = true;
746 }
747 } else if (UseCountLeadingZerosInstruction) {
748 warning("lzcnt instruction is not available on this CPU");
749 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
750 }
751
752 if (supports_bmi1()) {
753 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
754 UseBMI1Instructions = true;
755 }
756 } else if (UseBMI1Instructions) {
757 warning("BMI1 instructions are not available on this CPU");
758 FLAG_SET_DEFAULT(UseBMI1Instructions, false);
759 }
760
761 // Use count trailing zeros instruction if available
762 if (supports_bmi1()) {
763 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
764 UseCountTrailingZerosInstruction = UseBMI1Instructions;
765 }
766 } else if (UseCountTrailingZerosInstruction) {
767 warning("tzcnt instruction is not available on this CPU");
768 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
769 }
770
771 // Use population count instruction if available.
772 if (supports_popcnt()) {
773 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
774 UsePopCountInstruction = true;
775 }
776 } else if (UsePopCountInstruction) {
777 warning("POPCNT instruction is not available on this CPU");
778 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
779 }
780
781 // Use fast-string operations if available.
782 if (supports_erms()) {
783 if (FLAG_IS_DEFAULT(UseFastStosb)) {
784 UseFastStosb = true;
785 }
786 } else if (UseFastStosb) {
787 warning("fast-string operations are not available on this CPU");
788 FLAG_SET_DEFAULT(UseFastStosb, false);
789 }
790
791 #ifdef COMPILER2
792 if (FLAG_IS_DEFAULT(AlignVector)) {
793 // Modern processors allow misaligned memory operations for vectors.
794 AlignVector = !UseUnalignedLoadStores;
795 }
796 #endif // COMPILER2
797
798 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
799 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
800
801 // set valid Prefetch instruction
802 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
803 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
804 if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0;
805 if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3;
806
807 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
808 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
809 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
810 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
811
812 // Allocation prefetch settings
813 intx cache_line_size = prefetch_data_size();
814 if( cache_line_size > AllocatePrefetchStepSize )
815 AllocatePrefetchStepSize = cache_line_size;
816
817 assert(AllocatePrefetchLines > 0, "invalid value");
818 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
819 AllocatePrefetchLines = 3;
820 assert(AllocateInstancePrefetchLines > 0, "invalid value");
821 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
822 AllocateInstancePrefetchLines = 1;
823
824 AllocatePrefetchDistance = allocate_prefetch_distance();
825 AllocatePrefetchStyle = allocate_prefetch_style();
826
827 if( is_intel() && cpu_family() == 6 && supports_sse3() ) {
828 if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core
829 #ifdef _LP64
830 AllocatePrefetchDistance = 384;
831 #else
832 AllocatePrefetchDistance = 320;
833 #endif
834 }
835 if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus
836 AllocatePrefetchDistance = 192;
837 AllocatePrefetchLines = 4;
838 #ifdef COMPILER2
839 if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
840 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
841 }
842 #endif
843 }
844 }
845 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
846
847 #ifdef _LP64
848 // Prefetch settings
849 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
850 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
851 PrefetchFieldsAhead = prefetch_fields_ahead();
852 #endif
853
854 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
855 (cache_line_size > ContendedPaddingWidth))
856 ContendedPaddingWidth = cache_line_size;
857
858 #ifndef PRODUCT
859 if (PrintMiscellaneous && Verbose) {
860 tty->print_cr("Logical CPUs per core: %u",
861 logical_processors_per_package());
862 tty->print("UseSSE=%d",UseSSE);
863 if (UseAVX > 0) {
864 tty->print(" UseAVX=%d",UseAVX);
865 }
866 if (UseAES) {
867 tty->print(" UseAES=1");
868 }
869 #ifdef COMPILER2
870 if (MaxVectorSize > 0) {
871 tty->print(" MaxVectorSize=%d", MaxVectorSize);
872 }
873 #endif
874 tty->cr();
875 tty->print("Allocation");
876 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
877 tty->print_cr(": no prefetching");
878 } else {
879 tty->print(" prefetching: ");
880 if (UseSSE == 0 && supports_3dnow_prefetch()) {
881 tty->print("PREFETCHW");
882 } else if (UseSSE >= 1) {
883 if (AllocatePrefetchInstr == 0) {
884 tty->print("PREFETCHNTA");
885 } else if (AllocatePrefetchInstr == 1) {
886 tty->print("PREFETCHT0");
887 } else if (AllocatePrefetchInstr == 2) {
888 tty->print("PREFETCHT2");
889 } else if (AllocatePrefetchInstr == 3) {
890 tty->print("PREFETCHW");
891 }
892 }
893 if (AllocatePrefetchLines > 1) {
894 tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
895 } else {
896 tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
897 }
898 }
899
900 if (PrefetchCopyIntervalInBytes > 0) {
901 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
902 }
903 if (PrefetchScanIntervalInBytes > 0) {
904 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
905 }
906 if (PrefetchFieldsAhead > 0) {
907 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
908 }
909 if (ContendedPaddingWidth > 0) {
910 tty->print_cr("ContendedPaddingWidth %d", ContendedPaddingWidth);
911 }
912 }
913 #endif // !PRODUCT
914 }
915
916 void VM_Version::initialize() {
917 ResourceMark rm;
918 // Making this stub must be FIRST use of assembler
919
920 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
921 if (stub_blob == NULL) {
922 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
923 }
924 CodeBuffer c(stub_blob);
925 VM_Version_StubGenerator g(&c);
926 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
927 g.generate_getPsrInfo());
928
929 get_processor_features();
930 }