1 /*
   2  * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "memory/resourceArea.hpp"
  29 #include "runtime/java.hpp"
  30 #include "runtime/stubCodeGenerator.hpp"
  31 #include "vm_version_x86.hpp"
  32 
  33 
  34 int VM_Version::_cpu;
  35 int VM_Version::_model;
  36 int VM_Version::_stepping;
  37 int VM_Version::_cpuFeatures;
  38 const char*           VM_Version::_features_str = "";
  39 VM_Version::CpuidInfo VM_Version::_cpuid_info   = { 0, };
  40 
  41 // Address of instruction which causes SEGV
  42 address VM_Version::_cpuinfo_segv_addr = 0;
  43 // Address of instruction after the one which causes SEGV
  44 address VM_Version::_cpuinfo_cont_addr = 0;
  45 
  46 static BufferBlob* stub_blob;
  47 static const int stub_size = 600;
  48 
  49 extern "C" {
  50   typedef void (*get_cpu_info_stub_t)(void*);
  51 }
  52 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
  53 
  54 
  55 class VM_Version_StubGenerator: public StubCodeGenerator {
  56  public:
  57 
  58   VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
  59 
  60   address generate_get_cpu_info() {
  61     // Flags to test CPU type.
  62     const uint32_t HS_EFL_AC           = 0x40000;
  63     const uint32_t HS_EFL_ID           = 0x200000;
  64     // Values for when we don't have a CPUID instruction.
  65     const int      CPU_FAMILY_SHIFT = 8;
  66     const uint32_t CPU_FAMILY_386   = (3 << CPU_FAMILY_SHIFT);
  67     const uint32_t CPU_FAMILY_486   = (4 << CPU_FAMILY_SHIFT);
  68 
  69     Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
  70     Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done;
  71 
  72     StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
  73 #   define __ _masm->
  74 
  75     address start = __ pc();
  76 
  77     //
  78     // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
  79     //
  80     // LP64: rcx and rdx are first and second argument registers on windows
  81 
  82     __ push(rbp);
  83 #ifdef _LP64
  84     __ mov(rbp, c_rarg0); // cpuid_info address
  85 #else
  86     __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
  87 #endif
  88     __ push(rbx);
  89     __ push(rsi);
  90     __ pushf();          // preserve rbx, and flags
  91     __ pop(rax);
  92     __ push(rax);
  93     __ mov(rcx, rax);
  94     //
  95     // if we are unable to change the AC flag, we have a 386
  96     //
  97     __ xorl(rax, HS_EFL_AC);
  98     __ push(rax);
  99     __ popf();
 100     __ pushf();
 101     __ pop(rax);
 102     __ cmpptr(rax, rcx);
 103     __ jccb(Assembler::notEqual, detect_486);
 104 
 105     __ movl(rax, CPU_FAMILY_386);
 106     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
 107     __ jmp(done);
 108 
 109     //
 110     // If we are unable to change the ID flag, we have a 486 which does
 111     // not support the "cpuid" instruction.
 112     //
 113     __ bind(detect_486);
 114     __ mov(rax, rcx);
 115     __ xorl(rax, HS_EFL_ID);
 116     __ push(rax);
 117     __ popf();
 118     __ pushf();
 119     __ pop(rax);
 120     __ cmpptr(rcx, rax);
 121     __ jccb(Assembler::notEqual, detect_586);
 122 
 123     __ bind(cpu486);
 124     __ movl(rax, CPU_FAMILY_486);
 125     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
 126     __ jmp(done);
 127 
 128     //
 129     // At this point, we have a chip which supports the "cpuid" instruction
 130     //
 131     __ bind(detect_586);
 132     __ xorl(rax, rax);
 133     __ cpuid();
 134     __ orl(rax, rax);
 135     __ jcc(Assembler::equal, cpu486);   // if cpuid doesn't support an input
 136                                         // value of at least 1, we give up and
 137                                         // assume a 486
 138     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
 139     __ movl(Address(rsi, 0), rax);
 140     __ movl(Address(rsi, 4), rbx);
 141     __ movl(Address(rsi, 8), rcx);
 142     __ movl(Address(rsi,12), rdx);
 143 
 144     __ cmpl(rax, 0xa);                  // Is cpuid(0xB) supported?
 145     __ jccb(Assembler::belowEqual, std_cpuid4);
 146 
 147     //
 148     // cpuid(0xB) Processor Topology
 149     //
 150     __ movl(rax, 0xb);
 151     __ xorl(rcx, rcx);   // Threads level
 152     __ cpuid();
 153 
 154     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
 155     __ movl(Address(rsi, 0), rax);
 156     __ movl(Address(rsi, 4), rbx);
 157     __ movl(Address(rsi, 8), rcx);
 158     __ movl(Address(rsi,12), rdx);
 159 
 160     __ movl(rax, 0xb);
 161     __ movl(rcx, 1);     // Cores level
 162     __ cpuid();
 163     __ push(rax);
 164     __ andl(rax, 0x1f);  // Determine if valid topology level
 165     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
 166     __ andl(rax, 0xffff);
 167     __ pop(rax);
 168     __ jccb(Assembler::equal, std_cpuid4);
 169 
 170     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
 171     __ movl(Address(rsi, 0), rax);
 172     __ movl(Address(rsi, 4), rbx);
 173     __ movl(Address(rsi, 8), rcx);
 174     __ movl(Address(rsi,12), rdx);
 175 
 176     __ movl(rax, 0xb);
 177     __ movl(rcx, 2);     // Packages level
 178     __ cpuid();
 179     __ push(rax);
 180     __ andl(rax, 0x1f);  // Determine if valid topology level
 181     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
 182     __ andl(rax, 0xffff);
 183     __ pop(rax);
 184     __ jccb(Assembler::equal, std_cpuid4);
 185 
 186     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
 187     __ movl(Address(rsi, 0), rax);
 188     __ movl(Address(rsi, 4), rbx);
 189     __ movl(Address(rsi, 8), rcx);
 190     __ movl(Address(rsi,12), rdx);
 191 
 192     //
 193     // cpuid(0x4) Deterministic cache params
 194     //
 195     __ bind(std_cpuid4);
 196     __ movl(rax, 4);
 197     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
 198     __ jccb(Assembler::greater, std_cpuid1);
 199 
 200     __ xorl(rcx, rcx);   // L1 cache
 201     __ cpuid();
 202     __ push(rax);
 203     __ andl(rax, 0x1f);  // Determine if valid cache parameters used
 204     __ orl(rax, rax);    // eax[4:0] == 0 indicates invalid cache
 205     __ pop(rax);
 206     __ jccb(Assembler::equal, std_cpuid1);
 207 
 208     __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
 209     __ movl(Address(rsi, 0), rax);
 210     __ movl(Address(rsi, 4), rbx);
 211     __ movl(Address(rsi, 8), rcx);
 212     __ movl(Address(rsi,12), rdx);
 213 
 214     //
 215     // Standard cpuid(0x1)
 216     //
 217     __ bind(std_cpuid1);
 218     __ movl(rax, 1);
 219     __ cpuid();
 220     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 221     __ movl(Address(rsi, 0), rax);
 222     __ movl(Address(rsi, 4), rbx);
 223     __ movl(Address(rsi, 8), rcx);
 224     __ movl(Address(rsi,12), rdx);
 225 
 226     //
 227     // Check if OS has enabled XGETBV instruction to access XCR0
 228     // (OSXSAVE feature flag) and CPU supports AVX
 229     //
 230     __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
 231     __ cmpl(rcx, 0x18000000);
 232     __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
 233 
 234     //
 235     // XCR0, XFEATURE_ENABLED_MASK register
 236     //
 237     __ xorl(rcx, rcx);   // zero for XCR0 register
 238     __ xgetbv();
 239     __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
 240     __ movl(Address(rsi, 0), rax);
 241     __ movl(Address(rsi, 4), rdx);
 242 
 243     __ andl(rax, 0x6); // xcr0 bits sse | ymm
 244     __ cmpl(rax, 0x6);
 245     __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
 246 
 247     //
 248     // Some OSs have a bug when upper 128bits of YMM
 249     // registers are not restored after a signal processing.
 250     // Generate SEGV here (reference through NULL)
 251     // and check upper YMM bits after it.
 252     //
 253     VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
 254     intx saved_useavx = UseAVX;
 255     intx saved_usesse = UseSSE;
 256     UseAVX = 1;
 257     UseSSE = 2;
 258 
 259     // load value into all 32 bytes of ymm7 register
 260     __ movl(rcx, VM_Version::ymm_test_value());
 261 
 262     __ movdl(xmm0, rcx);
 263     __ pshufd(xmm0, xmm0, 0x00);
 264     __ vinsertf128h(xmm0, xmm0, xmm0);
 265     __ vmovdqu(xmm7, xmm0);
 266 #ifdef _LP64
 267     __ vmovdqu(xmm8,  xmm0);
 268     __ vmovdqu(xmm15, xmm0);
 269 #endif
 270 
 271     __ xorl(rsi, rsi);
 272     VM_Version::set_cpuinfo_segv_addr( __ pc() );
 273     // Generate SEGV
 274     __ movl(rax, Address(rsi, 0));
 275 
 276     VM_Version::set_cpuinfo_cont_addr( __ pc() );
 277     // Returns here after signal. Save xmm0 to check it later.
 278     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
 279     __ vmovdqu(Address(rsi,  0), xmm0);
 280     __ vmovdqu(Address(rsi, 32), xmm7);
 281 #ifdef _LP64
 282     __ vmovdqu(Address(rsi, 64), xmm8);
 283     __ vmovdqu(Address(rsi, 96), xmm15);
 284 #endif
 285 
 286     VM_Version::clean_cpuFeatures();
 287     UseAVX = saved_useavx;
 288     UseSSE = saved_usesse;
 289 
 290     //
 291     // cpuid(0x7) Structured Extended Features
 292     //
 293     __ bind(sef_cpuid);
 294     __ movl(rax, 7);
 295     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
 296     __ jccb(Assembler::greater, ext_cpuid);
 297 
 298     __ xorl(rcx, rcx);
 299     __ cpuid();
 300     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 301     __ movl(Address(rsi, 0), rax);
 302     __ movl(Address(rsi, 4), rbx);
 303 
 304     //
 305     // Extended cpuid(0x80000000)
 306     //
 307     __ bind(ext_cpuid);
 308     __ movl(rax, 0x80000000);
 309     __ cpuid();
 310     __ cmpl(rax, 0x80000000);     // Is cpuid(0x80000001) supported?
 311     __ jcc(Assembler::belowEqual, done);
 312     __ cmpl(rax, 0x80000004);     // Is cpuid(0x80000005) supported?
 313     __ jccb(Assembler::belowEqual, ext_cpuid1);
 314     __ cmpl(rax, 0x80000006);     // Is cpuid(0x80000007) supported?
 315     __ jccb(Assembler::belowEqual, ext_cpuid5);
 316     __ cmpl(rax, 0x80000007);     // Is cpuid(0x80000008) supported?
 317     __ jccb(Assembler::belowEqual, ext_cpuid7);
 318     //
 319     // Extended cpuid(0x80000008)
 320     //
 321     __ movl(rax, 0x80000008);
 322     __ cpuid();
 323     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
 324     __ movl(Address(rsi, 0), rax);
 325     __ movl(Address(rsi, 4), rbx);
 326     __ movl(Address(rsi, 8), rcx);
 327     __ movl(Address(rsi,12), rdx);
 328 
 329     //
 330     // Extended cpuid(0x80000007)
 331     //
 332     __ bind(ext_cpuid7);
 333     __ movl(rax, 0x80000007);
 334     __ cpuid();
 335     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
 336     __ movl(Address(rsi, 0), rax);
 337     __ movl(Address(rsi, 4), rbx);
 338     __ movl(Address(rsi, 8), rcx);
 339     __ movl(Address(rsi,12), rdx);
 340 
 341     //
 342     // Extended cpuid(0x80000005)
 343     //
 344     __ bind(ext_cpuid5);
 345     __ movl(rax, 0x80000005);
 346     __ cpuid();
 347     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
 348     __ movl(Address(rsi, 0), rax);
 349     __ movl(Address(rsi, 4), rbx);
 350     __ movl(Address(rsi, 8), rcx);
 351     __ movl(Address(rsi,12), rdx);
 352 
 353     //
 354     // Extended cpuid(0x80000001)
 355     //
 356     __ bind(ext_cpuid1);
 357     __ movl(rax, 0x80000001);
 358     __ cpuid();
 359     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
 360     __ movl(Address(rsi, 0), rax);
 361     __ movl(Address(rsi, 4), rbx);
 362     __ movl(Address(rsi, 8), rcx);
 363     __ movl(Address(rsi,12), rdx);
 364 
 365     //
 366     // return
 367     //
 368     __ bind(done);
 369     __ popf();
 370     __ pop(rsi);
 371     __ pop(rbx);
 372     __ pop(rbp);
 373     __ ret(0);
 374 
 375 #   undef __
 376 
 377     return start;
 378   };
 379 };
 380 
 381 
 382 void VM_Version::get_cpu_info_wrapper() {
 383   get_cpu_info_stub(&_cpuid_info);
 384 }
 385 
 386 #ifndef CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED
 387   #define CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(f) f()
 388 #endif
 389 
 390 void VM_Version::get_processor_features() {
 391 
 392   _cpu = 4; // 486 by default
 393   _model = 0;
 394   _stepping = 0;
 395   _cpuFeatures = 0;
 396   _logical_processors_per_package = 1;
 397   // i486 internal cache is both I&D and has a 16-byte line size
 398   _L1_data_cache_line_size = 16;
 399 
 400   if (!Use486InstrsOnly) {
 401     // Get raw processor info
 402 
 403     // Some platforms (like Win*) need a wrapper around here
 404     // in order to properly handle SEGV for YMM registers test.
 405     CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(get_cpu_info_wrapper);
 406 
 407     assert_is_initialized();
 408     _cpu = extended_cpu_family();
 409     _model = extended_cpu_model();
 410     _stepping = cpu_stepping();
 411 
 412     if (cpu_family() > 4) { // it supports CPUID
 413       _cpuFeatures = feature_flags();
 414       // Logical processors are only available on P4s and above,
 415       // and only if hyperthreading is available.
 416       _logical_processors_per_package = logical_processor_count();
 417       _L1_data_cache_line_size = L1_line_size();
 418     }
 419   }
 420 
 421   _supports_cx8 = supports_cmpxchg8();
 422   // xchg and xadd instructions
 423   _supports_atomic_getset4 = true;
 424   _supports_atomic_getadd4 = true;
 425   LP64_ONLY(_supports_atomic_getset8 = true);
 426   LP64_ONLY(_supports_atomic_getadd8 = true);
 427 
 428 #ifdef _LP64
 429   // OS should support SSE for x64 and hardware should support at least SSE2.
 430   if (!VM_Version::supports_sse2()) {
 431     vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
 432   }
 433   // in 64 bit the use of SSE2 is the minimum
 434   if (UseSSE < 2) UseSSE = 2;
 435 #endif
 436 
 437 #ifdef AMD64
 438   // flush_icache_stub have to be generated first.
 439   // That is why Icache line size is hard coded in ICache class,
 440   // see icache_x86.hpp. It is also the reason why we can't use
 441   // clflush instruction in 32-bit VM since it could be running
 442   // on CPU which does not support it.
 443   //
 444   // The only thing we can do is to verify that flushed
 445   // ICache::line_size has correct value.
 446   guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
 447   // clflush_size is size in quadwords (8 bytes).
 448   guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
 449 #endif
 450 
 451   // If the OS doesn't support SSE, we can't use this feature even if the HW does
 452   if (!os::supports_sse())
 453     _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
 454 
 455   if (UseSSE < 4) {
 456     _cpuFeatures &= ~CPU_SSE4_1;
 457     _cpuFeatures &= ~CPU_SSE4_2;
 458   }
 459 
 460   if (UseSSE < 3) {
 461     _cpuFeatures &= ~CPU_SSE3;
 462     _cpuFeatures &= ~CPU_SSSE3;
 463     _cpuFeatures &= ~CPU_SSE4A;
 464   }
 465 
 466   if (UseSSE < 2)
 467     _cpuFeatures &= ~CPU_SSE2;
 468 
 469   if (UseSSE < 1)
 470     _cpuFeatures &= ~CPU_SSE;
 471 
 472   if (UseAVX < 2)
 473     _cpuFeatures &= ~CPU_AVX2;
 474 
 475   if (UseAVX < 1)
 476     _cpuFeatures &= ~CPU_AVX;
 477 
 478   if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
 479     _cpuFeatures &= ~CPU_AES;
 480 
 481   if (logical_processors_per_package() == 1) {
 482     // HT processor could be installed on a system which doesn't support HT.
 483     _cpuFeatures &= ~CPU_HT;
 484   }
 485 
 486   char buf[256];
 487   jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 488                cores_per_cpu(), threads_per_core(),
 489                cpu_family(), _model, _stepping,
 490                (supports_cmov() ? ", cmov" : ""),
 491                (supports_cmpxchg8() ? ", cx8" : ""),
 492                (supports_fxsr() ? ", fxsr" : ""),
 493                (supports_mmx()  ? ", mmx"  : ""),
 494                (supports_sse()  ? ", sse"  : ""),
 495                (supports_sse2() ? ", sse2" : ""),
 496                (supports_sse3() ? ", sse3" : ""),
 497                (supports_ssse3()? ", ssse3": ""),
 498                (supports_sse4_1() ? ", sse4.1" : ""),
 499                (supports_sse4_2() ? ", sse4.2" : ""),
 500                (supports_popcnt() ? ", popcnt" : ""),
 501                (supports_avx()    ? ", avx" : ""),
 502                (supports_avx2()   ? ", avx2" : ""),
 503                (supports_aes()    ? ", aes" : ""),
 504                (supports_clmul()  ? ", clmul" : ""),
 505                (supports_erms()   ? ", erms" : ""),
 506                (supports_rtm()    ? ", rtm" : ""),
 507                (supports_mmx_ext() ? ", mmxext" : ""),
 508                (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
 509                (supports_lzcnt()   ? ", lzcnt": ""),
 510                (supports_sse4a()   ? ", sse4a": ""),
 511                (supports_ht() ? ", ht": ""),
 512                (supports_tsc() ? ", tsc": ""),
 513                (supports_tscinv_bit() ? ", tscinvbit": ""),
 514                (supports_tscinv() ? ", tscinv": ""),
 515                (supports_bmi1() ? ", bmi1" : ""),
 516                (supports_bmi2() ? ", bmi2" : ""));
 517   _features_str = strdup(buf);
 518 
 519   // UseSSE is set to the smaller of what hardware supports and what
 520   // the command line requires.  I.e., you cannot set UseSSE to 2 on
 521   // older Pentiums which do not support it.
 522   if (UseSSE > 4) UseSSE=4;
 523   if (UseSSE < 0) UseSSE=0;
 524   if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
 525     UseSSE = MIN2((intx)3,UseSSE);
 526   if (!supports_sse3()) // Drop to 2 if no SSE3 support
 527     UseSSE = MIN2((intx)2,UseSSE);
 528   if (!supports_sse2()) // Drop to 1 if no SSE2 support
 529     UseSSE = MIN2((intx)1,UseSSE);
 530   if (!supports_sse ()) // Drop to 0 if no SSE  support
 531     UseSSE = 0;
 532 
 533   if (UseAVX > 2) UseAVX=2;
 534   if (UseAVX < 0) UseAVX=0;
 535   if (!supports_avx2()) // Drop to 1 if no AVX2 support
 536     UseAVX = MIN2((intx)1,UseAVX);
 537   if (!supports_avx ()) // Drop to 0 if no AVX  support
 538     UseAVX = 0;
 539 
 540   // Use AES instructions if available.
 541   if (supports_aes()) {
 542     if (FLAG_IS_DEFAULT(UseAES)) {
 543       UseAES = true;
 544     }
 545   } else if (UseAES) {
 546     if (!FLAG_IS_DEFAULT(UseAES))
 547       warning("AES instructions are not available on this CPU");
 548     FLAG_SET_DEFAULT(UseAES, false);
 549   }
 550 
 551   // Use CLMUL instructions if available.
 552   if (supports_clmul()) {
 553     if (FLAG_IS_DEFAULT(UseCLMUL)) {
 554       UseCLMUL = true;
 555     }
 556   } else if (UseCLMUL) {
 557     if (!FLAG_IS_DEFAULT(UseCLMUL))
 558       warning("CLMUL instructions not available on this CPU (AVX may also be required)");
 559     FLAG_SET_DEFAULT(UseCLMUL, false);
 560   }
 561 
 562   if (UseCLMUL && (UseAVX > 0) && (UseSSE > 2)) {
 563     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 564       UseCRC32Intrinsics = true;
 565     }
 566   } else if (UseCRC32Intrinsics) {
 567     if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
 568       warning("CRC32 Intrinsics requires AVX and CLMUL instructions (not available on this CPU)");
 569     FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
 570   }
 571 
 572   // The AES intrinsic stubs require AES instruction support (of course)
 573   // but also require sse3 mode for instructions it use.
 574   if (UseAES && (UseSSE > 2)) {
 575     if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 576       UseAESIntrinsics = true;
 577     }
 578   } else if (UseAESIntrinsics) {
 579     if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
 580       warning("AES intrinsics are not available on this CPU");
 581     FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 582   }
 583 
 584   if (UseSHA) {
 585     warning("SHA instructions are not available on this CPU");
 586     FLAG_SET_DEFAULT(UseSHA, false);
 587   }
 588   if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
 589     warning("SHA intrinsics are not available on this CPU");
 590     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 591     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 592     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 593   }
 594 
 595   // Adjust RTM (Restricted Transactional Memory) flags
 596   if (!supports_rtm() && UseRTMLocking) {
 597     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 598     // setting during arguments processing. See use_biased_locking().
 599     // VM_Version_init() is executed after UseBiasedLocking is used
 600     // in Thread::allocate().
 601     vm_exit_during_initialization("RTM instructions are not available on this CPU");
 602   }
 603 
 604 #if INCLUDE_RTM_OPT
 605   if (UseRTMLocking) {
 606     if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
 607       // RTM locking should be used only for applications with
 608       // high lock contention. For now we do not use it by default.
 609       vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
 610     }
 611     if (!is_power_of_2(RTMTotalCountIncrRate)) {
 612       warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
 613       FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
 614     }
 615     if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
 616       warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
 617       FLAG_SET_DEFAULT(RTMAbortRatio, 50);
 618     }
 619   } else { // !UseRTMLocking
 620     if (UseRTMForStackLocks) {
 621       if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
 622         warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
 623       }
 624       FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
 625     }
 626     if (UseRTMDeopt) {
 627       FLAG_SET_DEFAULT(UseRTMDeopt, false);
 628     }
 629     if (PrintPreciseRTMLockingStatistics) {
 630       FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
 631     }
 632   }
 633 #else
 634   if (UseRTMLocking) {
 635     // Only C2 does RTM locking optimization.
 636     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 637     // setting during arguments processing. See use_biased_locking().
 638     vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
 639   }
 640 #endif
 641 
 642 #ifdef COMPILER2
 643   if (UseFPUForSpilling) {
 644     if (UseSSE < 2) {
 645       // Only supported with SSE2+
 646       FLAG_SET_DEFAULT(UseFPUForSpilling, false);
 647     }
 648   }
 649   if (MaxVectorSize > 0) {
 650     if (!is_power_of_2(MaxVectorSize)) {
 651       warning("MaxVectorSize must be a power of 2");
 652       FLAG_SET_DEFAULT(MaxVectorSize, 32);
 653     }
 654     if (MaxVectorSize > 32) {
 655       FLAG_SET_DEFAULT(MaxVectorSize, 32);
 656     }
 657     if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) {
 658       // 32 bytes vectors (in YMM) are only supported with AVX+
 659       FLAG_SET_DEFAULT(MaxVectorSize, 16);
 660     }
 661     if (UseSSE < 2) {
 662       // Vectors (in XMM) are only supported with SSE2+
 663       FLAG_SET_DEFAULT(MaxVectorSize, 0);
 664     }
 665 #ifdef ASSERT
 666     if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
 667       tty->print_cr("State of YMM registers after signal handle:");
 668       int nreg = 2 LP64_ONLY(+2);
 669       const char* ymm_name[4] = {"0", "7", "8", "15"};
 670       for (int i = 0; i < nreg; i++) {
 671         tty->print("YMM%s:", ymm_name[i]);
 672         for (int j = 7; j >=0; j--) {
 673           tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
 674         }
 675         tty->cr();
 676       }
 677     }
 678 #endif
 679   }
 680 #endif
 681 
 682   // On new cpus instructions which update whole XMM register should be used
 683   // to prevent partial register stall due to dependencies on high half.
 684   //
 685   // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
 686   // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
 687   // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
 688   // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).
 689 
 690   if( is_amd() ) { // AMD cpus specific settings
 691     if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
 692       // Use it on new AMD cpus starting from Opteron.
 693       UseAddressNop = true;
 694     }
 695     if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
 696       // Use it on new AMD cpus starting from Opteron.
 697       UseNewLongLShift = true;
 698     }
 699     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
 700       if( supports_sse4a() ) {
 701         UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
 702       } else {
 703         UseXmmLoadAndClearUpper = false;
 704       }
 705     }
 706     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
 707       if( supports_sse4a() ) {
 708         UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
 709       } else {
 710         UseXmmRegToRegMoveAll = false;
 711       }
 712     }
 713     if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
 714       if( supports_sse4a() ) {
 715         UseXmmI2F = true;
 716       } else {
 717         UseXmmI2F = false;
 718       }
 719     }
 720     if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
 721       if( supports_sse4a() ) {
 722         UseXmmI2D = true;
 723       } else {
 724         UseXmmI2D = false;
 725       }
 726     }
 727     if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) {
 728       if( supports_sse4_2() && UseSSE >= 4 ) {
 729         UseSSE42Intrinsics = true;
 730       }
 731     }
 732 
 733     // some defaults for AMD family 15h
 734     if ( cpu_family() == 0x15 ) {
 735       // On family 15h processors default is no sw prefetch
 736       if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
 737         AllocatePrefetchStyle = 0;
 738       }
 739       // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
 740       if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
 741         AllocatePrefetchInstr = 3;
 742       }
 743       // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
 744       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
 745         UseXMMForArrayCopy = true;
 746       }
 747       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
 748         UseUnalignedLoadStores = true;
 749       }
 750     }
 751 
 752 #ifdef COMPILER2
 753     if (MaxVectorSize > 16) {
 754       // Limit vectors size to 16 bytes on current AMD cpus.
 755       FLAG_SET_DEFAULT(MaxVectorSize, 16);
 756     }
 757 #endif // COMPILER2
 758   }
 759 
 760   if( is_intel() ) { // Intel cpus specific settings
 761     if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
 762       UseStoreImmI16 = false; // don't use it on Intel cpus
 763     }
 764     if( cpu_family() == 6 || cpu_family() == 15 ) {
 765       if( FLAG_IS_DEFAULT(UseAddressNop) ) {
 766         // Use it on all Intel cpus starting from PentiumPro
 767         UseAddressNop = true;
 768       }
 769     }
 770     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
 771       UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
 772     }
 773     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
 774       if( supports_sse3() ) {
 775         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
 776       } else {
 777         UseXmmRegToRegMoveAll = false;
 778       }
 779     }
 780     if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
 781 #ifdef COMPILER2
 782       if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
 783         // For new Intel cpus do the next optimization:
 784         // don't align the beginning of a loop if there are enough instructions
 785         // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
 786         // in current fetch line (OptoLoopAlignment) or the padding
 787         // is big (> MaxLoopPad).
 788         // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
 789         // generated NOP instructions. 11 is the largest size of one
 790         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
 791         MaxLoopPad = 11;
 792       }
 793 #endif // COMPILER2
 794       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
 795         UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
 796       }
 797       if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
 798         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
 799           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
 800         }
 801       }
 802       if (supports_sse4_2() && UseSSE >= 4) {
 803         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
 804           UseSSE42Intrinsics = true;
 805         }
 806       }
 807     }
 808   }
 809 
 810   // Use count leading zeros count instruction if available.
 811   if (supports_lzcnt()) {
 812     if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
 813       UseCountLeadingZerosInstruction = true;
 814     }
 815    } else if (UseCountLeadingZerosInstruction) {
 816     warning("lzcnt instruction is not available on this CPU");
 817     FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
 818   }
 819 
 820   if (supports_bmi1()) {
 821     if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
 822       UseBMI1Instructions = true;
 823     }
 824   } else if (UseBMI1Instructions) {
 825     warning("BMI1 instructions are not available on this CPU");
 826     FLAG_SET_DEFAULT(UseBMI1Instructions, false);
 827   }
 828 
 829   // Use count trailing zeros instruction if available
 830   if (supports_bmi1()) {
 831     if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
 832       UseCountTrailingZerosInstruction = UseBMI1Instructions;
 833     }
 834   } else if (UseCountTrailingZerosInstruction) {
 835     warning("tzcnt instruction is not available on this CPU");
 836     FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
 837   }
 838 
 839   // Use population count instruction if available.
 840   if (supports_popcnt()) {
 841     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
 842       UsePopCountInstruction = true;
 843     }
 844   } else if (UsePopCountInstruction) {
 845     warning("POPCNT instruction is not available on this CPU");
 846     FLAG_SET_DEFAULT(UsePopCountInstruction, false);
 847   }
 848 
 849   // Use fast-string operations if available.
 850   if (supports_erms()) {
 851     if (FLAG_IS_DEFAULT(UseFastStosb)) {
 852       UseFastStosb = true;
 853     }
 854   } else if (UseFastStosb) {
 855     warning("fast-string operations are not available on this CPU");
 856     FLAG_SET_DEFAULT(UseFastStosb, false);
 857   }
 858 
 859 #ifdef COMPILER2
 860   if (FLAG_IS_DEFAULT(AlignVector)) {
 861     // Modern processors allow misaligned memory operations for vectors.
 862     AlignVector = !UseUnalignedLoadStores;
 863   }
 864 #endif // COMPILER2
 865 
 866   assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
 867   assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
 868 
 869   // set valid Prefetch instruction
 870   if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
 871   if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
 872   if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0;
 873   if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3;
 874 
 875   if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
 876   if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
 877   if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
 878   if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
 879 
 880   // Allocation prefetch settings
 881   intx cache_line_size = prefetch_data_size();
 882   if( cache_line_size > AllocatePrefetchStepSize )
 883     AllocatePrefetchStepSize = cache_line_size;
 884 
 885   assert(AllocatePrefetchLines > 0, "invalid value");
 886   if( AllocatePrefetchLines < 1 )     // set valid value in product VM
 887     AllocatePrefetchLines = 3;
 888   assert(AllocateInstancePrefetchLines > 0, "invalid value");
 889   if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
 890     AllocateInstancePrefetchLines = 1;
 891 
 892   AllocatePrefetchDistance = allocate_prefetch_distance();
 893   AllocatePrefetchStyle    = allocate_prefetch_style();
 894 
 895   if( is_intel() && cpu_family() == 6 && supports_sse3() ) {
 896     if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core
 897 #ifdef _LP64
 898       AllocatePrefetchDistance = 384;
 899 #else
 900       AllocatePrefetchDistance = 320;
 901 #endif
 902     }
 903     if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus
 904       AllocatePrefetchDistance = 192;
 905       AllocatePrefetchLines = 4;
 906 #ifdef COMPILER2
 907       if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
 908         FLAG_SET_DEFAULT(UseFPUForSpilling, true);
 909       }
 910 #endif
 911     }
 912   }
 913   assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
 914 
 915 #ifdef _LP64
 916   // Prefetch settings
 917   PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
 918   PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
 919   PrefetchFieldsAhead         = prefetch_fields_ahead();
 920 #endif
 921 
 922   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
 923      (cache_line_size > ContendedPaddingWidth))
 924      ContendedPaddingWidth = cache_line_size;
 925 
 926 #ifndef PRODUCT
 927   if (PrintMiscellaneous && Verbose) {
 928     tty->print_cr("Logical CPUs per core: %u",
 929                   logical_processors_per_package());
 930     tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
 931     tty->print("UseSSE=%d", (int) UseSSE);
 932     if (UseAVX > 0) {
 933       tty->print("  UseAVX=%d", (int) UseAVX);
 934     }
 935     if (UseAES) {
 936       tty->print("  UseAES=1");
 937     }
 938 #ifdef COMPILER2
 939     if (MaxVectorSize > 0) {
 940       tty->print("  MaxVectorSize=%d", (int) MaxVectorSize);
 941     }
 942 #endif
 943     tty->cr();
 944     tty->print("Allocation");
 945     if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
 946       tty->print_cr(": no prefetching");
 947     } else {
 948       tty->print(" prefetching: ");
 949       if (UseSSE == 0 && supports_3dnow_prefetch()) {
 950         tty->print("PREFETCHW");
 951       } else if (UseSSE >= 1) {
 952         if (AllocatePrefetchInstr == 0) {
 953           tty->print("PREFETCHNTA");
 954         } else if (AllocatePrefetchInstr == 1) {
 955           tty->print("PREFETCHT0");
 956         } else if (AllocatePrefetchInstr == 2) {
 957           tty->print("PREFETCHT2");
 958         } else if (AllocatePrefetchInstr == 3) {
 959           tty->print("PREFETCHW");
 960         }
 961       }
 962       if (AllocatePrefetchLines > 1) {
 963         tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
 964       } else {
 965         tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
 966       }
 967     }
 968 
 969     if (PrefetchCopyIntervalInBytes > 0) {
 970       tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
 971     }
 972     if (PrefetchScanIntervalInBytes > 0) {
 973       tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
 974     }
 975     if (PrefetchFieldsAhead > 0) {
 976       tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
 977     }
 978     if (ContendedPaddingWidth > 0) {
 979       tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
 980     }
 981   }
 982 #endif // !PRODUCT
 983 }
 984 
 985 bool VM_Version::use_biased_locking() {
 986 #if INCLUDE_RTM_OPT
 987   // RTM locking is most useful when there is high lock contention and
 988   // low data contention.  With high lock contention the lock is usually
 989   // inflated and biased locking is not suitable for that case.
 990   // RTM locking code requires that biased locking is off.
 991   // Note: we can't switch off UseBiasedLocking in get_processor_features()
 992   // because it is used by Thread::allocate() which is called before
 993   // VM_Version::initialize().
 994   if (UseRTMLocking && UseBiasedLocking) {
 995     if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
 996       FLAG_SET_DEFAULT(UseBiasedLocking, false);
 997     } else {
 998       warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
 999       UseBiasedLocking = false;
1000     }
1001   }
1002 #endif
1003   return UseBiasedLocking;
1004 }
1005 
1006 void VM_Version::initialize() {
1007   ResourceMark rm;
1008   // Making this stub must be FIRST use of assembler
1009 
1010   stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1011   if (stub_blob == NULL) {
1012     vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1013   }
1014   CodeBuffer c(stub_blob);
1015   VM_Version_StubGenerator g(&c);
1016   get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1017                                      g.generate_get_cpu_info());
1018 
1019   get_processor_features();
1020 }