src/cpu/x86/vm/vm_version_x86.cpp
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src/cpu/x86/vm/vm_version_x86.cpp

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 542     if (FLAG_IS_DEFAULT(UseAES)) {
 543       UseAES = true;
 544     }
 545   } else if (UseAES) {
 546     if (!FLAG_IS_DEFAULT(UseAES))
 547       warning("AES instructions are not available on this CPU");
 548     FLAG_SET_DEFAULT(UseAES, false);
 549   }
 550 
 551   // Use CLMUL instructions if available.
 552   if (supports_clmul()) {
 553     if (FLAG_IS_DEFAULT(UseCLMUL)) {
 554       UseCLMUL = true;
 555     }
 556   } else if (UseCLMUL) {
 557     if (!FLAG_IS_DEFAULT(UseCLMUL))
 558       warning("CLMUL instructions not available on this CPU (AVX may also be required)");
 559     FLAG_SET_DEFAULT(UseCLMUL, false);
 560   }
 561 
 562   if (UseCLMUL && (UseAVX > 0) && (UseSSE > 2)) {
 563     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 564       UseCRC32Intrinsics = true;
 565     }
 566   } else if (UseCRC32Intrinsics) {
 567     if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
 568       warning("CRC32 Intrinsics requires AVX and CLMUL instructions (not available on this CPU)");
 569     FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
 570   }
 571 
 572   // The AES intrinsic stubs require AES instruction support (of course)
 573   // but also require sse3 mode for instructions it use.
 574   if (UseAES && (UseSSE > 2)) {
 575     if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 576       UseAESIntrinsics = true;
 577     }
 578   } else if (UseAESIntrinsics) {
 579     if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
 580       warning("AES intrinsics are not available on this CPU");
 581     FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 582   }


 788         // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
 789         // generated NOP instructions. 11 is the largest size of one
 790         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
 791         MaxLoopPad = 11;
 792       }
 793 #endif // COMPILER2
 794       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
 795         UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
 796       }
 797       if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
 798         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
 799           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
 800         }
 801       }
 802       if (supports_sse4_2() && UseSSE >= 4) {
 803         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
 804           UseSSE42Intrinsics = true;
 805         }
 806       }
 807     }















 808   }
 809 
 810   // Use count leading zeros count instruction if available.
 811   if (supports_lzcnt()) {
 812     if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
 813       UseCountLeadingZerosInstruction = true;
 814     }
 815    } else if (UseCountLeadingZerosInstruction) {
 816     warning("lzcnt instruction is not available on this CPU");
 817     FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
 818   }
 819 
 820   if (supports_bmi1()) {
 821     if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
 822       UseBMI1Instructions = true;
 823     }
 824   } else if (UseBMI1Instructions) {
 825     warning("BMI1 instructions are not available on this CPU");
 826     FLAG_SET_DEFAULT(UseBMI1Instructions, false);
 827   }


 875   if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
 876   if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
 877   if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
 878   if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
 879 
 880   // Allocation prefetch settings
 881   intx cache_line_size = prefetch_data_size();
 882   if( cache_line_size > AllocatePrefetchStepSize )
 883     AllocatePrefetchStepSize = cache_line_size;
 884 
 885   assert(AllocatePrefetchLines > 0, "invalid value");
 886   if( AllocatePrefetchLines < 1 )     // set valid value in product VM
 887     AllocatePrefetchLines = 3;
 888   assert(AllocateInstancePrefetchLines > 0, "invalid value");
 889   if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
 890     AllocateInstancePrefetchLines = 1;
 891 
 892   AllocatePrefetchDistance = allocate_prefetch_distance();
 893   AllocatePrefetchStyle    = allocate_prefetch_style();
 894 
 895   if( is_intel() && cpu_family() == 6 && supports_sse3() ) {
 896     if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core
 897 #ifdef _LP64
 898       AllocatePrefetchDistance = 384;
 899 #else
 900       AllocatePrefetchDistance = 320;
 901 #endif
 902     }
 903     if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus
 904       AllocatePrefetchDistance = 192;
 905       AllocatePrefetchLines = 4;

 906 #ifdef COMPILER2
 907       if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) {

 908         FLAG_SET_DEFAULT(UseFPUForSpilling, true);
 909       }
 910 #endif
 911     }

 912   }
 913   assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
 914 
 915 #ifdef _LP64
 916   // Prefetch settings
 917   PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
 918   PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
 919   PrefetchFieldsAhead         = prefetch_fields_ahead();
 920 #endif
 921 
 922   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
 923      (cache_line_size > ContendedPaddingWidth))
 924      ContendedPaddingWidth = cache_line_size;
 925 
 926 #ifndef PRODUCT
 927   if (PrintMiscellaneous && Verbose) {
 928     tty->print_cr("Logical CPUs per core: %u",
 929                   logical_processors_per_package());
 930     tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
 931     tty->print("UseSSE=%d", (int) UseSSE);




 542     if (FLAG_IS_DEFAULT(UseAES)) {
 543       UseAES = true;
 544     }
 545   } else if (UseAES) {
 546     if (!FLAG_IS_DEFAULT(UseAES))
 547       warning("AES instructions are not available on this CPU");
 548     FLAG_SET_DEFAULT(UseAES, false);
 549   }
 550 
 551   // Use CLMUL instructions if available.
 552   if (supports_clmul()) {
 553     if (FLAG_IS_DEFAULT(UseCLMUL)) {
 554       UseCLMUL = true;
 555     }
 556   } else if (UseCLMUL) {
 557     if (!FLAG_IS_DEFAULT(UseCLMUL))
 558       warning("CLMUL instructions not available on this CPU (AVX may also be required)");
 559     FLAG_SET_DEFAULT(UseCLMUL, false);
 560   }
 561 
 562   if (UseCLMUL && (UseSSE > 2)) {
 563     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 564       UseCRC32Intrinsics = true;
 565     }
 566   } else if (UseCRC32Intrinsics) {
 567     if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
 568       warning("CRC32 Intrinsics requires AVX and CLMUL instructions (not available on this CPU)");
 569     FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
 570   }
 571 
 572   // The AES intrinsic stubs require AES instruction support (of course)
 573   // but also require sse3 mode for instructions it use.
 574   if (UseAES && (UseSSE > 2)) {
 575     if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 576       UseAESIntrinsics = true;
 577     }
 578   } else if (UseAESIntrinsics) {
 579     if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
 580       warning("AES intrinsics are not available on this CPU");
 581     FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 582   }


 788         // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
 789         // generated NOP instructions. 11 is the largest size of one
 790         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
 791         MaxLoopPad = 11;
 792       }
 793 #endif // COMPILER2
 794       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
 795         UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
 796       }
 797       if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
 798         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
 799           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
 800         }
 801       }
 802       if (supports_sse4_2() && UseSSE >= 4) {
 803         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
 804           UseSSE42Intrinsics = true;
 805         }
 806       }
 807     }
 808     if ((cpu_family() == 0x06) && 
 809         ((extended_cpu_model() == 0x36) || // Centerton
 810          (extended_cpu_model() == 0x37) || // Silvermont
 811          (extended_cpu_model() == 0x4D))) { 
 812 #ifdef COMPILER2
 813       if (FLAG_IS_DEFAULT(OptoScheduling)) {
 814         OptoScheduling = true;
 815       }
 816 #endif
 817       if (supports_sse4_2()) { // Silvermont
 818         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
 819           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
 820         }
 821       }   
 822     }
 823   }
 824 
 825   // Use count leading zeros count instruction if available.
 826   if (supports_lzcnt()) {
 827     if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
 828       UseCountLeadingZerosInstruction = true;
 829     }
 830    } else if (UseCountLeadingZerosInstruction) {
 831     warning("lzcnt instruction is not available on this CPU");
 832     FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
 833   }
 834 
 835   if (supports_bmi1()) {
 836     if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
 837       UseBMI1Instructions = true;
 838     }
 839   } else if (UseBMI1Instructions) {
 840     warning("BMI1 instructions are not available on this CPU");
 841     FLAG_SET_DEFAULT(UseBMI1Instructions, false);
 842   }


 890   if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
 891   if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
 892   if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
 893   if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
 894 
 895   // Allocation prefetch settings
 896   intx cache_line_size = prefetch_data_size();
 897   if( cache_line_size > AllocatePrefetchStepSize )
 898     AllocatePrefetchStepSize = cache_line_size;
 899 
 900   assert(AllocatePrefetchLines > 0, "invalid value");
 901   if( AllocatePrefetchLines < 1 )     // set valid value in product VM
 902     AllocatePrefetchLines = 3;
 903   assert(AllocateInstancePrefetchLines > 0, "invalid value");
 904   if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
 905     AllocateInstancePrefetchLines = 1;
 906 
 907   AllocatePrefetchDistance = allocate_prefetch_distance();
 908   AllocatePrefetchStyle    = allocate_prefetch_style();
 909 
 910   if (is_intel() && cpu_family() == 6 && supports_sse3()) {
 911     if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core
 912 #ifdef _LP64
 913       AllocatePrefetchDistance = 384;
 914 #else
 915       AllocatePrefetchDistance = 320;
 916 #endif
 917     }
 918     if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
 919       AllocatePrefetchDistance = 192;
 920       AllocatePrefetchLines = 4;
 921     }
 922 #ifdef COMPILER2
 923     if (supports_sse4_2()) { 
 924       if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
 925         FLAG_SET_DEFAULT(UseFPUForSpilling, true);
 926       }

 927     }
 928 #endif
 929   }
 930   assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
 931 
 932 #ifdef _LP64
 933   // Prefetch settings
 934   PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
 935   PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
 936   PrefetchFieldsAhead         = prefetch_fields_ahead();
 937 #endif
 938 
 939   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
 940      (cache_line_size > ContendedPaddingWidth))
 941      ContendedPaddingWidth = cache_line_size;
 942 
 943 #ifndef PRODUCT
 944   if (PrintMiscellaneous && Verbose) {
 945     tty->print_cr("Logical CPUs per core: %u",
 946                   logical_processors_per_package());
 947     tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
 948     tty->print("UseSSE=%d", (int) UseSSE);


src/cpu/x86/vm/vm_version_x86.cpp
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