src/cpu/x86/vm/assembler_x86.cpp
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src/cpu/x86/vm/assembler_x86.cpp

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4920   emit_operand(src, dst);
4921 }
4922 
4923 void Assembler::addq(Register dst, int32_t imm32) {
4924   (void) prefixq_and_encode(dst->encoding());
4925   emit_arith(0x81, 0xC0, dst, imm32);
4926 }
4927 
4928 void Assembler::addq(Register dst, Address src) {
4929   InstructionMark im(this);
4930   prefixq(src, dst);
4931   emit_int8(0x03);
4932   emit_operand(dst, src);
4933 }
4934 
4935 void Assembler::addq(Register dst, Register src) {
4936   (void) prefixq_and_encode(dst->encoding(), src->encoding());
4937   emit_arith(0x03, 0xC0, dst, src);
4938 }
4939 




















4940 void Assembler::andq(Address dst, int32_t imm32) {
4941   InstructionMark im(this);
4942   prefixq(dst);
4943   emit_int8((unsigned char)0x81);
4944   emit_operand(rsp, dst, 4);
4945   emit_int32(imm32);
4946 }
4947 
4948 void Assembler::andq(Register dst, int32_t imm32) {
4949   (void) prefixq_and_encode(dst->encoding());
4950   emit_arith(0x81, 0xE0, dst, imm32);
4951 }
4952 
4953 void Assembler::andq(Register dst, Address src) {
4954   InstructionMark im(this);
4955   prefixq(src, dst);
4956   emit_int8(0x23);
4957   emit_operand(dst, src);
4958 }
4959 


5427   emit_int8(0x0F);
5428   emit_int8((unsigned char)0xB6);
5429   emit_int8(0xC0 | encode);
5430 }
5431 
5432 void Assembler::movzwq(Register dst, Address src) {
5433   InstructionMark im(this);
5434   prefixq(src, dst);
5435   emit_int8((unsigned char)0x0F);
5436   emit_int8((unsigned char)0xB7);
5437   emit_operand(dst, src);
5438 }
5439 
5440 void Assembler::movzwq(Register dst, Register src) {
5441   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5442   emit_int8((unsigned char)0x0F);
5443   emit_int8((unsigned char)0xB7);
5444   emit_int8((unsigned char)(0xC0 | encode));
5445 }
5446 




















5447 void Assembler::negq(Register dst) {
5448   int encode = prefixq_and_encode(dst->encoding());
5449   emit_int8((unsigned char)0xF7);
5450   emit_int8((unsigned char)(0xD8 | encode));
5451 }
5452 
5453 void Assembler::notq(Register dst) {
5454   int encode = prefixq_and_encode(dst->encoding());
5455   emit_int8((unsigned char)0xF7);
5456   emit_int8((unsigned char)(0xD0 | encode));
5457 }
5458 
5459 void Assembler::orq(Address dst, int32_t imm32) {
5460   InstructionMark im(this);
5461   prefixq(dst);
5462   emit_int8((unsigned char)0x81);
5463   emit_operand(rcx, dst, 4);
5464   emit_int32(imm32);
5465 }
5466 


5555 
5556 void Assembler::pushq(Address src) {
5557   InstructionMark im(this);
5558   prefixq(src);
5559   emit_int8((unsigned char)0xFF);
5560   emit_operand(rsi, src);
5561 }
5562 
5563 void Assembler::rclq(Register dst, int imm8) {
5564   assert(isShiftCount(imm8 >> 1), "illegal shift count");
5565   int encode = prefixq_and_encode(dst->encoding());
5566   if (imm8 == 1) {
5567     emit_int8((unsigned char)0xD1);
5568     emit_int8((unsigned char)(0xD0 | encode));
5569   } else {
5570     emit_int8((unsigned char)0xC1);
5571     emit_int8((unsigned char)(0xD0 | encode));
5572     emit_int8(imm8);
5573   }
5574 }






















5575 void Assembler::sarq(Register dst, int imm8) {
5576   assert(isShiftCount(imm8 >> 1), "illegal shift count");
5577   int encode = prefixq_and_encode(dst->encoding());
5578   if (imm8 == 1) {
5579     emit_int8((unsigned char)0xD1);
5580     emit_int8((unsigned char)(0xF8 | encode));
5581   } else {
5582     emit_int8((unsigned char)0xC1);
5583     emit_int8((unsigned char)(0xF8 | encode));
5584     emit_int8(imm8);
5585   }
5586 }
5587 
5588 void Assembler::sarq(Register dst) {
5589   int encode = prefixq_and_encode(dst->encoding());
5590   emit_int8((unsigned char)0xD3);
5591   emit_int8((unsigned char)(0xF8 | encode));
5592 }
5593 
5594 void Assembler::sbbq(Address dst, int32_t imm32) {




4920   emit_operand(src, dst);
4921 }
4922 
4923 void Assembler::addq(Register dst, int32_t imm32) {
4924   (void) prefixq_and_encode(dst->encoding());
4925   emit_arith(0x81, 0xC0, dst, imm32);
4926 }
4927 
4928 void Assembler::addq(Register dst, Address src) {
4929   InstructionMark im(this);
4930   prefixq(src, dst);
4931   emit_int8(0x03);
4932   emit_operand(dst, src);
4933 }
4934 
4935 void Assembler::addq(Register dst, Register src) {
4936   (void) prefixq_and_encode(dst->encoding(), src->encoding());
4937   emit_arith(0x03, 0xC0, dst, src);
4938 }
4939 
4940 void Assembler::adcxq(Register dst, Register src) {
4941   //assert(VM_Version::supports_adx(), "adx instructions not supported");
4942   emit_int8((unsigned char)0x66);
4943   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4944   emit_int8(0x0F);
4945   emit_int8(0x38);
4946   emit_int8((unsigned char)0xF6);
4947   emit_int8((unsigned char)(0xC0 | encode));
4948 }
4949 
4950 void Assembler::adoxq(Register dst, Register src) {
4951   //assert(VM_Version::supports_adx(), "adx instructions not supported");
4952   emit_int8((unsigned char)0xF3);
4953   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4954   emit_int8(0x0F);
4955   emit_int8(0x38);
4956   emit_int8((unsigned char)0xF6);
4957   emit_int8((unsigned char)(0xC0 | encode));
4958 }
4959 
4960 void Assembler::andq(Address dst, int32_t imm32) {
4961   InstructionMark im(this);
4962   prefixq(dst);
4963   emit_int8((unsigned char)0x81);
4964   emit_operand(rsp, dst, 4);
4965   emit_int32(imm32);
4966 }
4967 
4968 void Assembler::andq(Register dst, int32_t imm32) {
4969   (void) prefixq_and_encode(dst->encoding());
4970   emit_arith(0x81, 0xE0, dst, imm32);
4971 }
4972 
4973 void Assembler::andq(Register dst, Address src) {
4974   InstructionMark im(this);
4975   prefixq(src, dst);
4976   emit_int8(0x23);
4977   emit_operand(dst, src);
4978 }
4979 


5447   emit_int8(0x0F);
5448   emit_int8((unsigned char)0xB6);
5449   emit_int8(0xC0 | encode);
5450 }
5451 
5452 void Assembler::movzwq(Register dst, Address src) {
5453   InstructionMark im(this);
5454   prefixq(src, dst);
5455   emit_int8((unsigned char)0x0F);
5456   emit_int8((unsigned char)0xB7);
5457   emit_operand(dst, src);
5458 }
5459 
5460 void Assembler::movzwq(Register dst, Register src) {
5461   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5462   emit_int8((unsigned char)0x0F);
5463   emit_int8((unsigned char)0xB7);
5464   emit_int8((unsigned char)(0xC0 | encode));
5465 }
5466 
5467 void Assembler::mulq(Address src) {
5468   InstructionMark im(this);
5469   prefixq(src);
5470   emit_int8((unsigned char)0xF7);
5471   emit_operand(rsp, src);
5472 }
5473 
5474 void Assembler::mulq(Register src) {
5475   int encode = prefixq_and_encode(src->encoding());
5476   emit_int8((unsigned char)0xF7);
5477   emit_int8((unsigned char)(0xE0 | encode));
5478 }
5479 
5480 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
5481   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
5482   int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, true, false);
5483   emit_int8((unsigned char)0xF6);
5484   emit_int8((unsigned char)(0xC0 | encode));
5485 }
5486 
5487 void Assembler::negq(Register dst) {
5488   int encode = prefixq_and_encode(dst->encoding());
5489   emit_int8((unsigned char)0xF7);
5490   emit_int8((unsigned char)(0xD8 | encode));
5491 }
5492 
5493 void Assembler::notq(Register dst) {
5494   int encode = prefixq_and_encode(dst->encoding());
5495   emit_int8((unsigned char)0xF7);
5496   emit_int8((unsigned char)(0xD0 | encode));
5497 }
5498 
5499 void Assembler::orq(Address dst, int32_t imm32) {
5500   InstructionMark im(this);
5501   prefixq(dst);
5502   emit_int8((unsigned char)0x81);
5503   emit_operand(rcx, dst, 4);
5504   emit_int32(imm32);
5505 }
5506 


5595 
5596 void Assembler::pushq(Address src) {
5597   InstructionMark im(this);
5598   prefixq(src);
5599   emit_int8((unsigned char)0xFF);
5600   emit_operand(rsi, src);
5601 }
5602 
5603 void Assembler::rclq(Register dst, int imm8) {
5604   assert(isShiftCount(imm8 >> 1), "illegal shift count");
5605   int encode = prefixq_and_encode(dst->encoding());
5606   if (imm8 == 1) {
5607     emit_int8((unsigned char)0xD1);
5608     emit_int8((unsigned char)(0xD0 | encode));
5609   } else {
5610     emit_int8((unsigned char)0xC1);
5611     emit_int8((unsigned char)(0xD0 | encode));
5612     emit_int8(imm8);
5613   }
5614 }
5615 
5616 void Assembler::rorq(Register dst, int imm8) {
5617   assert(isShiftCount(imm8 >> 1), "illegal shift count");
5618   int encode = prefixq_and_encode(dst->encoding());
5619   if (imm8 == 1) {
5620     emit_int8((unsigned char)0xD1);
5621     emit_int8((unsigned char)(0xC8 | encode));
5622   } else {
5623     emit_int8((unsigned char)0xC1);
5624     emit_int8((unsigned char)(0xc8 | encode));
5625     emit_int8(imm8);
5626   }
5627 }
5628 
5629 void Assembler::rorxq(Register dst, Register src, int imm8) {
5630   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
5631   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, true, false);
5632   emit_int8((unsigned char)0xF0);
5633   emit_int8((unsigned char)(0xC0 | encode));
5634   emit_int8(imm8);
5635 }
5636 
5637 void Assembler::sarq(Register dst, int imm8) {
5638   assert(isShiftCount(imm8 >> 1), "illegal shift count");
5639   int encode = prefixq_and_encode(dst->encoding());
5640   if (imm8 == 1) {
5641     emit_int8((unsigned char)0xD1);
5642     emit_int8((unsigned char)(0xF8 | encode));
5643   } else {
5644     emit_int8((unsigned char)0xC1);
5645     emit_int8((unsigned char)(0xF8 | encode));
5646     emit_int8(imm8);
5647   }
5648 }
5649 
5650 void Assembler::sarq(Register dst) {
5651   int encode = prefixq_and_encode(dst->encoding());
5652   emit_int8((unsigned char)0xD3);
5653   emit_int8((unsigned char)(0xF8 | encode));
5654 }
5655 
5656 void Assembler::sbbq(Address dst, int32_t imm32) {


src/cpu/x86/vm/assembler_x86.cpp
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