1 /* 2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP 26 #define CPU_X86_VM_VM_VERSION_X86_HPP 27 28 #include "runtime/globals_extension.hpp" 29 #include "runtime/vm_version.hpp" 30 31 class VM_Version : public Abstract_VM_Version { 32 public: 33 // cpuid result register layouts. These are all unions of a uint32_t 34 // (in case anyone wants access to the register as a whole) and a bitfield. 35 36 union StdCpuid1Eax { 37 uint32_t value; 38 struct { 39 uint32_t stepping : 4, 40 model : 4, 41 family : 4, 42 proc_type : 2, 43 : 2, 44 ext_model : 4, 45 ext_family : 8, 46 : 4; 47 } bits; 48 }; 49 50 union StdCpuid1Ebx { // example, unused 51 uint32_t value; 52 struct { 53 uint32_t brand_id : 8, 54 clflush_size : 8, 55 threads_per_cpu : 8, 56 apic_id : 8; 57 } bits; 58 }; 59 60 union StdCpuid1Ecx { 61 uint32_t value; 62 struct { 63 uint32_t sse3 : 1, 64 clmul : 1, 65 : 1, 66 monitor : 1, 67 : 1, 68 vmx : 1, 69 : 1, 70 est : 1, 71 : 1, 72 ssse3 : 1, 73 cid : 1, 74 : 2, 75 cmpxchg16: 1, 76 : 4, 77 dca : 1, 78 sse4_1 : 1, 79 sse4_2 : 1, 80 : 2, 81 popcnt : 1, 82 : 1, 83 aes : 1, 84 : 1, 85 osxsave : 1, 86 avx : 1, 87 : 3; 88 } bits; 89 }; 90 91 union StdCpuid1Edx { 92 uint32_t value; 93 struct { 94 uint32_t : 4, 95 tsc : 1, 96 : 3, 97 cmpxchg8 : 1, 98 : 6, 99 cmov : 1, 100 : 3, 101 clflush : 1, 102 : 3, 103 mmx : 1, 104 fxsr : 1, 105 sse : 1, 106 sse2 : 1, 107 : 1, 108 ht : 1, 109 : 3; 110 } bits; 111 }; 112 113 union DcpCpuid4Eax { 114 uint32_t value; 115 struct { 116 uint32_t cache_type : 5, 117 : 21, 118 cores_per_cpu : 6; 119 } bits; 120 }; 121 122 union DcpCpuid4Ebx { 123 uint32_t value; 124 struct { 125 uint32_t L1_line_size : 12, 126 partitions : 10, 127 associativity : 10; 128 } bits; 129 }; 130 131 union TplCpuidBEbx { 132 uint32_t value; 133 struct { 134 uint32_t logical_cpus : 16, 135 : 16; 136 } bits; 137 }; 138 139 union ExtCpuid1Ecx { 140 uint32_t value; 141 struct { 142 uint32_t LahfSahf : 1, 143 CmpLegacy : 1, 144 : 3, 145 lzcnt_intel : 1, 146 lzcnt : 1, 147 sse4a : 1, 148 misalignsse : 1, 149 prefetchw : 1, 150 : 22; 151 } bits; 152 }; 153 154 union ExtCpuid1Edx { 155 uint32_t value; 156 struct { 157 uint32_t : 22, 158 mmx_amd : 1, 159 mmx : 1, 160 fxsr : 1, 161 : 4, 162 long_mode : 1, 163 tdnow2 : 1, 164 tdnow : 1; 165 } bits; 166 }; 167 168 union ExtCpuid5Ex { 169 uint32_t value; 170 struct { 171 uint32_t L1_line_size : 8, 172 L1_tag_lines : 8, 173 L1_assoc : 8, 174 L1_size : 8; 175 } bits; 176 }; 177 178 union ExtCpuid7Edx { 179 uint32_t value; 180 struct { 181 uint32_t : 8, 182 tsc_invariance : 1, 183 : 23; 184 } bits; 185 }; 186 187 union ExtCpuid8Ecx { 188 uint32_t value; 189 struct { 190 uint32_t cores_per_cpu : 8, 191 : 24; 192 } bits; 193 }; 194 195 union SefCpuid7Eax { 196 uint32_t value; 197 }; 198 199 union SefCpuid7Ebx { 200 uint32_t value; 201 struct { 202 uint32_t fsgsbase : 1, 203 : 2, 204 bmi1 : 1, 205 : 1, 206 avx2 : 1, 207 : 2, 208 bmi2 : 1, 209 erms : 1, 210 : 1, 211 rtm : 1, 212 : 20; 213 } bits; 214 }; 215 216 union XemXcr0Eax { 217 uint32_t value; 218 struct { 219 uint32_t x87 : 1, 220 sse : 1, 221 ymm : 1, 222 : 29; 223 } bits; 224 }; 225 226 protected: 227 static int _cpu; 228 static int _model; 229 static int _stepping; 230 static int _cpuFeatures; // features returned by the "cpuid" instruction 231 // 0 if this instruction is not available 232 static const char* _features_str; 233 234 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV 235 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV 236 237 enum { 238 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) 239 CPU_CMOV = (1 << 1), 240 CPU_FXSR = (1 << 2), 241 CPU_HT = (1 << 3), 242 CPU_MMX = (1 << 4), 243 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions 244 // may not necessarily support other 3dnow instructions 245 CPU_SSE = (1 << 6), 246 CPU_SSE2 = (1 << 7), 247 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) 248 CPU_SSSE3 = (1 << 9), 249 CPU_SSE4A = (1 << 10), 250 CPU_SSE4_1 = (1 << 11), 251 CPU_SSE4_2 = (1 << 12), 252 CPU_POPCNT = (1 << 13), 253 CPU_LZCNT = (1 << 14), 254 CPU_TSC = (1 << 15), 255 CPU_TSCINV = (1 << 16), 256 CPU_AVX = (1 << 17), 257 CPU_AVX2 = (1 << 18), 258 CPU_AES = (1 << 19), 259 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions 260 CPU_CLMUL = (1 << 21), // carryless multiply for CRC 261 CPU_BMI1 = (1 << 22), 262 CPU_BMI2 = (1 << 23), 263 CPU_RTM = (1 << 24) // Restricted Transactional Memory instructions 264 } cpuFeatureFlags; 265 266 enum { 267 // AMD 268 CPU_FAMILY_AMD_11H = 0x11, 269 // Intel 270 CPU_FAMILY_INTEL_CORE = 6, 271 CPU_MODEL_NEHALEM = 0x1e, 272 CPU_MODEL_NEHALEM_EP = 0x1a, 273 CPU_MODEL_NEHALEM_EX = 0x2e, 274 CPU_MODEL_WESTMERE = 0x25, 275 CPU_MODEL_WESTMERE_EP = 0x2c, 276 CPU_MODEL_WESTMERE_EX = 0x2f, 277 CPU_MODEL_SANDYBRIDGE = 0x2a, 278 CPU_MODEL_SANDYBRIDGE_EP = 0x2d, 279 CPU_MODEL_IVYBRIDGE_EP = 0x3a, 280 CPU_MODEL_HASWELL_E3 = 0x3c, 281 CPU_MODEL_HASWELL_E7 = 0x3f, 282 CPU_MODEL_BROADWELL = 0x3d 283 } cpuExtendedFamily; 284 285 // cpuid information block. All info derived from executing cpuid with 286 // various function numbers is stored here. Intel and AMD info is 287 // merged in this block: accessor methods disentangle it. 288 // 289 // The info block is laid out in subblocks of 4 dwords corresponding to 290 // eax, ebx, ecx and edx, whether or not they contain anything useful. 291 struct CpuidInfo { 292 // cpuid function 0 293 uint32_t std_max_function; 294 uint32_t std_vendor_name_0; 295 uint32_t std_vendor_name_1; 296 uint32_t std_vendor_name_2; 297 298 // cpuid function 1 299 StdCpuid1Eax std_cpuid1_eax; 300 StdCpuid1Ebx std_cpuid1_ebx; 301 StdCpuid1Ecx std_cpuid1_ecx; 302 StdCpuid1Edx std_cpuid1_edx; 303 304 // cpuid function 4 (deterministic cache parameters) 305 DcpCpuid4Eax dcp_cpuid4_eax; 306 DcpCpuid4Ebx dcp_cpuid4_ebx; 307 uint32_t dcp_cpuid4_ecx; // unused currently 308 uint32_t dcp_cpuid4_edx; // unused currently 309 310 // cpuid function 7 (structured extended features) 311 SefCpuid7Eax sef_cpuid7_eax; 312 SefCpuid7Ebx sef_cpuid7_ebx; 313 uint32_t sef_cpuid7_ecx; // unused currently 314 uint32_t sef_cpuid7_edx; // unused currently 315 316 // cpuid function 0xB (processor topology) 317 // ecx = 0 318 uint32_t tpl_cpuidB0_eax; 319 TplCpuidBEbx tpl_cpuidB0_ebx; 320 uint32_t tpl_cpuidB0_ecx; // unused currently 321 uint32_t tpl_cpuidB0_edx; // unused currently 322 323 // ecx = 1 324 uint32_t tpl_cpuidB1_eax; 325 TplCpuidBEbx tpl_cpuidB1_ebx; 326 uint32_t tpl_cpuidB1_ecx; // unused currently 327 uint32_t tpl_cpuidB1_edx; // unused currently 328 329 // ecx = 2 330 uint32_t tpl_cpuidB2_eax; 331 TplCpuidBEbx tpl_cpuidB2_ebx; 332 uint32_t tpl_cpuidB2_ecx; // unused currently 333 uint32_t tpl_cpuidB2_edx; // unused currently 334 335 // cpuid function 0x80000000 // example, unused 336 uint32_t ext_max_function; 337 uint32_t ext_vendor_name_0; 338 uint32_t ext_vendor_name_1; 339 uint32_t ext_vendor_name_2; 340 341 // cpuid function 0x80000001 342 uint32_t ext_cpuid1_eax; // reserved 343 uint32_t ext_cpuid1_ebx; // reserved 344 ExtCpuid1Ecx ext_cpuid1_ecx; 345 ExtCpuid1Edx ext_cpuid1_edx; 346 347 // cpuid functions 0x80000002 thru 0x80000004: example, unused 348 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; 349 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; 350 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; 351 352 // cpuid function 0x80000005 // AMD L1, Intel reserved 353 uint32_t ext_cpuid5_eax; // unused currently 354 uint32_t ext_cpuid5_ebx; // reserved 355 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) 356 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) 357 358 // cpuid function 0x80000007 359 uint32_t ext_cpuid7_eax; // reserved 360 uint32_t ext_cpuid7_ebx; // reserved 361 uint32_t ext_cpuid7_ecx; // reserved 362 ExtCpuid7Edx ext_cpuid7_edx; // tscinv 363 364 // cpuid function 0x80000008 365 uint32_t ext_cpuid8_eax; // unused currently 366 uint32_t ext_cpuid8_ebx; // reserved 367 ExtCpuid8Ecx ext_cpuid8_ecx; 368 uint32_t ext_cpuid8_edx; // reserved 369 370 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) 371 XemXcr0Eax xem_xcr0_eax; 372 uint32_t xem_xcr0_edx; // reserved 373 374 // Space to save ymm registers after signal handle 375 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15 376 }; 377 378 // The actual cpuid info block 379 static CpuidInfo _cpuid_info; 380 381 // Extractors and predicates 382 static uint32_t extended_cpu_family() { 383 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; 384 result += _cpuid_info.std_cpuid1_eax.bits.ext_family; 385 return result; 386 } 387 388 static uint32_t extended_cpu_model() { 389 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; 390 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; 391 return result; 392 } 393 394 static uint32_t cpu_stepping() { 395 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; 396 return result; 397 } 398 399 static uint logical_processor_count() { 400 uint result = threads_per_core(); 401 return result; 402 } 403 404 static uint32_t feature_flags() { 405 uint32_t result = 0; 406 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) 407 result |= CPU_CX8; 408 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) 409 result |= CPU_CMOV; 410 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && 411 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) 412 result |= CPU_FXSR; 413 // HT flag is set for multi-core processors also. 414 if (threads_per_core() > 1) 415 result |= CPU_HT; 416 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && 417 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) 418 result |= CPU_MMX; 419 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) 420 result |= CPU_SSE; 421 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) 422 result |= CPU_SSE2; 423 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) 424 result |= CPU_SSE3; 425 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) 426 result |= CPU_SSSE3; 427 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) 428 result |= CPU_SSE4_1; 429 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) 430 result |= CPU_SSE4_2; 431 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) 432 result |= CPU_POPCNT; 433 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && 434 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && 435 _cpuid_info.xem_xcr0_eax.bits.sse != 0 && 436 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { 437 result |= CPU_AVX; 438 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) 439 result |= CPU_AVX2; 440 } 441 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0) 442 result |= CPU_BMI1; 443 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) 444 result |= CPU_TSC; 445 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) 446 result |= CPU_TSCINV; 447 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0) 448 result |= CPU_AES; 449 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0) 450 result |= CPU_ERMS; 451 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0) 452 result |= CPU_CLMUL; 453 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0) 454 result |= CPU_RTM; 455 456 // AMD features. 457 if (is_amd()) { 458 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || 459 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) 460 result |= CPU_3DNOW_PREFETCH; 461 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) 462 result |= CPU_LZCNT; 463 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) 464 result |= CPU_SSE4A; 465 } 466 // Intel features. 467 if(is_intel()) { 468 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) 469 result |= CPU_BMI2; 470 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) 471 result |= CPU_LZCNT; 472 } 473 474 return result; 475 } 476 477 static bool os_supports_avx_vectors() { 478 if (!supports_avx()) { 479 return false; 480 } 481 // Verify that OS save/restore all bits of AVX registers 482 // during signal processing. 483 int nreg = 2 LP64_ONLY(+2); 484 for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register 485 if (_cpuid_info.ymm_save[i] != ymm_test_value()) { 486 return false; 487 } 488 } 489 return true; 490 } 491 492 static void get_processor_features(); 493 494 public: 495 // Offsets for cpuid asm stub 496 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } 497 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } 498 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } 499 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } 500 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } 501 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } 502 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } 503 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } 504 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } 505 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } 506 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } 507 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } 508 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); } 509 510 // The value used to check ymm register after signal handle 511 static int ymm_test_value() { return 0xCAFEBABE; } 512 513 static void get_cpu_info_wrapper(); 514 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; } 515 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; } 516 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; } 517 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; } 518 519 static void clean_cpuFeatures() { _cpuFeatures = 0; } 520 static void set_avx_cpuFeatures() { _cpuFeatures = (CPU_SSE | CPU_SSE2 | CPU_AVX); } 521 522 523 // Initialization 524 static void initialize(); 525 526 // Override Abstract_VM_Version implementation 527 static bool use_biased_locking(); 528 529 // Asserts 530 static void assert_is_initialized() { 531 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); 532 } 533 534 // 535 // Processor family: 536 // 3 - 386 537 // 4 - 486 538 // 5 - Pentium 539 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, 540 // Pentium M, Core Solo, Core Duo, Core2 Duo 541 // family 6 model: 9, 13, 14, 15 542 // 0x0f - Pentium 4, Opteron 543 // 544 // Note: The cpu family should be used to select between 545 // instruction sequences which are valid on all Intel 546 // processors. Use the feature test functions below to 547 // determine whether a particular instruction is supported. 548 // 549 static int cpu_family() { return _cpu;} 550 static bool is_P6() { return cpu_family() >= 6; } 551 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' 552 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' 553 554 static bool supports_processor_topology() { 555 return (_cpuid_info.std_max_function >= 0xB) && 556 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. 557 // Some cpus have max cpuid >= 0xB but do not support processor topology. 558 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); 559 } 560 561 static uint cores_per_cpu() { 562 uint result = 1; 563 if (is_intel()) { 564 if (supports_processor_topology()) { 565 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / 566 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 567 } else { 568 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); 569 } 570 } else if (is_amd()) { 571 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); 572 } 573 return result; 574 } 575 576 static uint threads_per_core() { 577 uint result = 1; 578 if (is_intel() && supports_processor_topology()) { 579 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 580 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { 581 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / 582 cores_per_cpu(); 583 } 584 return result; 585 } 586 587 static intx L1_line_size() { 588 intx result = 0; 589 if (is_intel()) { 590 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); 591 } else if (is_amd()) { 592 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; 593 } 594 if (result < 32) // not defined ? 595 result = 32; // 32 bytes by default on x86 and other x64 596 return result; 597 } 598 599 static intx prefetch_data_size() { 600 return L1_line_size(); 601 } 602 603 // 604 // Feature identification 605 // 606 static bool supports_cpuid() { return _cpuFeatures != 0; } 607 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } 608 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } 609 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } 610 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } 611 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } 612 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } 613 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } 614 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } 615 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } 616 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } 617 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } 618 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } 619 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; } 620 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; } 621 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } 622 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; } 623 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; } 624 static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; } 625 static bool supports_rtm() { return (_cpuFeatures & CPU_RTM) != 0; } 626 static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; } 627 static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; } 628 // Intel features 629 static bool is_intel_family_core() { return is_intel() && 630 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } 631 632 static bool is_intel_tsc_synched_at_init() { 633 if (is_intel_family_core()) { 634 uint32_t ext_model = extended_cpu_model(); 635 if (ext_model == CPU_MODEL_NEHALEM_EP || 636 ext_model == CPU_MODEL_WESTMERE_EP || 637 ext_model == CPU_MODEL_SANDYBRIDGE_EP || 638 ext_model == CPU_MODEL_IVYBRIDGE_EP) { 639 // <= 2-socket invariant tsc support. EX versions are usually used 640 // in > 2-socket systems and likely don't synchronize tscs at 641 // initialization. 642 // Code that uses tsc values must be prepared for them to arbitrarily 643 // jump forward or backward. 644 return true; 645 } 646 } 647 return false; 648 } 649 650 // AMD features 651 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; } 652 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } 653 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } 654 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } 655 656 static bool is_amd_Barcelona() { return is_amd() && 657 extended_cpu_family() == CPU_FAMILY_AMD_11H; } 658 659 // Intel and AMD newer cores support fast timestamps well 660 static bool supports_tscinv_bit() { 661 return (_cpuFeatures & CPU_TSCINV) != 0; 662 } 663 static bool supports_tscinv() { 664 return supports_tscinv_bit() && 665 ( (is_amd() && !is_amd_Barcelona()) || 666 is_intel_tsc_synched_at_init() ); 667 } 668 669 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). 670 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && 671 supports_sse3() && _model != 0x1C; } 672 673 static bool supports_compare_and_exchange() { return true; } 674 675 static const char* cpu_features() { return _features_str; } 676 677 static intx allocate_prefetch_distance() { 678 // This method should be called before allocate_prefetch_style(). 679 // 680 // Hardware prefetching (distance/size in bytes): 681 // Pentium 3 - 64 / 32 682 // Pentium 4 - 256 / 128 683 // Athlon - 64 / 32 ???? 684 // Opteron - 128 / 64 only when 2 sequential cache lines accessed 685 // Core - 128 / 64 686 // 687 // Software prefetching (distance in bytes / instruction with best score): 688 // Pentium 3 - 128 / prefetchnta 689 // Pentium 4 - 512 / prefetchnta 690 // Athlon - 128 / prefetchnta 691 // Opteron - 256 / prefetchnta 692 // Core - 256 / prefetchnta 693 // It will be used only when AllocatePrefetchStyle > 0 694 695 intx count = AllocatePrefetchDistance; 696 if (count < 0) { // default ? 697 if (is_amd()) { // AMD 698 if (supports_sse2()) 699 count = 256; // Opteron 700 else 701 count = 128; // Athlon 702 } else { // Intel 703 if (supports_sse2()) 704 if (cpu_family() == 6) { 705 count = 256; // Pentium M, Core, Core2 706 } else { 707 count = 512; // Pentium 4 708 } 709 else 710 count = 128; // Pentium 3 (and all other old CPUs) 711 } 712 } 713 return count; 714 } 715 static intx allocate_prefetch_style() { 716 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); 717 // Return 0 if AllocatePrefetchDistance was not defined. 718 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; 719 } 720 721 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from 722 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. 723 // Tested intervals from 128 to 2048 in increments of 64 == one cache line. 724 // 256 bytes (4 dcache lines) was the nearest runner-up to 576. 725 726 // gc copy/scan is disabled if prefetchw isn't supported, because 727 // Prefetch::write emits an inlined prefetchw on Linux. 728 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. 729 // The used prefetcht0 instruction works for both amd64 and em64t. 730 static intx prefetch_copy_interval_in_bytes() { 731 intx interval = PrefetchCopyIntervalInBytes; 732 return interval >= 0 ? interval : 576; 733 } 734 static intx prefetch_scan_interval_in_bytes() { 735 intx interval = PrefetchScanIntervalInBytes; 736 return interval >= 0 ? interval : 576; 737 } 738 static intx prefetch_fields_ahead() { 739 intx count = PrefetchFieldsAhead; 740 return count >= 0 ? count : 1; 741 } 742 }; 743 744 #endif // CPU_X86_VM_VM_VERSION_X86_HPP