1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2015 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/os.hpp"
33 #include "runtime/stubCodeGenerator.hpp"
34 #include "utilities/defaultStream.hpp"
35 #include "utilities/globalDefinitions.hpp"
36 #include "vm_version_ppc.hpp"
37
38 # include <sys/sysinfo.h>
39
40 int VM_Version::_features = VM_Version::unknown_m;
41 int VM_Version::_measured_cache_line_size = 32; // pessimistic init value
42 const char* VM_Version::_features_str = "";
43 bool VM_Version::_is_determine_features_test_running = false;
44
45
46 #define MSG(flag) \
47 if (flag && !FLAG_IS_DEFAULT(flag)) \
48 jio_fprintf(defaultStream::error_stream(), \
49 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
50 " -XX:+" #flag " will be disabled!\n");
51
52 void VM_Version::initialize() {
53
54 // Test which instructions are supported and measure cache line size.
55 determine_features();
56
57 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
58 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
59 if (VM_Version::has_lqarx()) {
60 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
61 } else if (VM_Version::has_popcntw()) {
62 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
63 } else if (VM_Version::has_cmpb()) {
64 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
65 } else if (VM_Version::has_popcntb()) {
66 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
67 } else {
68 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
69 }
70 }
71 guarantee(PowerArchitecturePPC64 == 0 || PowerArchitecturePPC64 == 5 ||
72 PowerArchitecturePPC64 == 6 || PowerArchitecturePPC64 == 7 ||
73 PowerArchitecturePPC64 == 8,
74 "PowerArchitecturePPC64 should be 0, 5, 6, 7, or 8");
75
76 // Power 8: Configure Data Stream Control Register.
77 if (PowerArchitecturePPC64 >= 8) {
78 config_dscr();
79 }
80
81 if (!UseSIGTRAP) {
82 MSG(TrapBasedICMissChecks);
83 MSG(TrapBasedNotEntrantChecks);
84 MSG(TrapBasedNullChecks);
85 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
86 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
87 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
88 }
89
90 #ifdef COMPILER2
91 if (!UseSIGTRAP) {
92 MSG(TrapBasedRangeChecks);
93 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
94 }
95
96 // On Power6 test for section size.
97 if (PowerArchitecturePPC64 == 6) {
98 determine_section_size();
99 // TODO: PPC port } else {
100 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
101 }
102
103 MaxVectorSize = 8;
104 #endif
105
106 // Create and print feature-string.
107 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
108 jio_snprintf(buf, sizeof(buf),
109 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s",
110 (has_fsqrt() ? " fsqrt" : ""),
111 (has_isel() ? " isel" : ""),
112 (has_lxarxeh() ? " lxarxeh" : ""),
113 (has_cmpb() ? " cmpb" : ""),
114 //(has_mftgpr()? " mftgpr" : ""),
115 (has_popcntb() ? " popcntb" : ""),
116 (has_popcntw() ? " popcntw" : ""),
117 (has_fcfids() ? " fcfids" : ""),
118 (has_vand() ? " vand" : ""),
119 (has_lqarx() ? " lqarx" : ""),
120 (has_vcipher() ? " vcipher" : ""),
121 (has_vpmsumb() ? " vpmsumb" : ""),
122 (has_tcheck() ? " tcheck" : "")
123 // Make sure number of %s matches num_features!
124 );
125 _features_str = os::strdup(buf);
126 if (Verbose) {
127 print_features();
128 }
129
130 // PPC64 supports 8-byte compare-exchange operations (see
131 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
132 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
133 _supports_cx8 = true;
134
135 UseSSE = 0; // Only on x86 and x64
136
137 intx cache_line_size = _measured_cache_line_size;
138
139 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
140
141 if (AllocatePrefetchStyle == 4) {
142 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
143 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
144 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
145 } else {
146 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
147 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
148 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
149 }
150
151 assert(AllocatePrefetchLines > 0, "invalid value");
152 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
153 AllocatePrefetchLines = 1; // Conservative value.
154 }
155
156 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
157 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
158 }
159
160 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
161
162 if (UseCRC32Intrinsics) {
163 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
164 warning("CRC32 intrinsics are not available on this CPU");
165 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
166 }
167
168 // The AES intrinsic stubs require AES instruction support.
169 if (UseAES) {
170 warning("AES instructions are not available on this CPU");
171 FLAG_SET_DEFAULT(UseAES, false);
172 }
173 if (UseAESIntrinsics) {
174 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
175 warning("AES intrinsics are not available on this CPU");
176 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
177 }
178
179 if (UseGHASHIntrinsics) {
180 warning("GHASH intrinsics are not available on this CPU");
181 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
182 }
183
184 if (UseSHA) {
185 warning("SHA instructions are not available on this CPU");
186 FLAG_SET_DEFAULT(UseSHA, false);
187 }
188 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
189 warning("SHA intrinsics are not available on this CPU");
190 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
191 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
192 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
193 }
194 // Adjust RTM (Restricted Transactional Memory) flags.
195 if (!has_tcheck() && UseRTMLocking) {
196 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
197 // setting during arguments processing. See use_biased_locking().
198 // VM_Version_init() is executed after UseBiasedLocking is used
199 // in Thread::allocate().
200 vm_exit_during_initialization("RTM instructions are not available on this CPU");
201 }
202
203 if (UseRTMLocking) {
204 #if INCLUDE_RTM_OPT
205 if (!UnlockExperimentalVMOptions) {
206 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "
207 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
208 } else {
209 warning("UseRTMLocking is only available as experimental option on this platform.");
210 }
211 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
212 // RTM locking should be used only for applications with
213 // high lock contention. For now we do not use it by default.
214 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
215 }
216 if (!is_power_of_2(RTMTotalCountIncrRate)) {
217 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
218 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
219 }
220 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
221 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
222 FLAG_SET_DEFAULT(RTMAbortRatio, 50);
223 }
224 FLAG_SET_ERGO(bool, UseNewFastLockPPC64, false); // Does not implement TM.
225 guarantee(RTMSpinLoopCount > 0, "unsupported");
226 #else
227 // Only C2 does RTM locking optimization.
228 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
229 // setting during arguments processing. See use_biased_locking().
230 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
231 #endif
232 } else { // !UseRTMLocking
233 if (UseRTMForStackLocks) {
234 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
235 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
236 }
237 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
238 }
239 if (UseRTMDeopt) {
240 FLAG_SET_DEFAULT(UseRTMDeopt, false);
241 }
242 if (PrintPreciseRTMLockingStatistics) {
243 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
244 }
245 }
246
247 // This machine does not allow unaligned memory accesses
248 if (UseUnalignedAccesses) {
249 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
250 warning("Unaligned memory access is not available on this CPU");
251 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
252 }
253 }
254
255 bool VM_Version::use_biased_locking() {
256 #if INCLUDE_RTM_OPT
257 // RTM locking is most useful when there is high lock contention and
258 // low data contention. With high lock contention the lock is usually
259 // inflated and biased locking is not suitable for that case.
260 // RTM locking code requires that biased locking is off.
261 // Note: we can't switch off UseBiasedLocking in get_processor_features()
262 // because it is used by Thread::allocate() which is called before
263 // VM_Version::initialize().
264 if (UseRTMLocking && UseBiasedLocking) {
265 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
266 FLAG_SET_DEFAULT(UseBiasedLocking, false);
267 } else {
268 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
269 UseBiasedLocking = false;
270 }
271 }
272 #endif
273 return UseBiasedLocking;
274 }
275
276 void VM_Version::print_features() {
277 tty->print_cr("Version: %s cache_line_size = %d", cpu_features(), (int) get_cache_line_size());
278 }
279
280 #ifdef COMPILER2
281 // Determine section size on power6: If section size is 8 instructions,
282 // there should be a difference between the two testloops of ~15 %. If
283 // no difference is detected the section is assumed to be 32 instructions.
284 void VM_Version::determine_section_size() {
285
286 int unroll = 80;
287
288 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
289
290 // Allocate space for the code.
291 ResourceMark rm;
292 CodeBuffer cb("detect_section_size", code_size, 0);
293 MacroAssembler* a = new MacroAssembler(&cb);
294
295 uint32_t *code = (uint32_t *)a->pc();
296 // Emit code.
297 void (*test1)() = (void(*)())(void *)a->function_entry();
298
299 Label l1;
300
301 a->li(R4, 1);
302 a->sldi(R4, R4, 28);
303 a->b(l1);
304 a->align(CodeEntryAlignment);
305
306 a->bind(l1);
307
308 for (int i = 0; i < unroll; i++) {
309 // Schleife 1
310 // ------- sector 0 ------------
311 // ;; 0
312 a->nop(); // 1
313 a->fpnop0(); // 2
314 a->fpnop1(); // 3
315 a->addi(R4,R4, -1); // 4
316
317 // ;; 1
318 a->nop(); // 5
319 a->fmr(F6, F6); // 6
320 a->fmr(F7, F7); // 7
321 a->endgroup(); // 8
322 // ------- sector 8 ------------
323
324 // ;; 2
325 a->nop(); // 9
326 a->nop(); // 10
327 a->fmr(F8, F8); // 11
328 a->fmr(F9, F9); // 12
329
330 // ;; 3
331 a->nop(); // 13
332 a->fmr(F10, F10); // 14
333 a->fmr(F11, F11); // 15
334 a->endgroup(); // 16
335 // -------- sector 16 -------------
336
337 // ;; 4
338 a->nop(); // 17
339 a->nop(); // 18
340 a->fmr(F15, F15); // 19
341 a->fmr(F16, F16); // 20
342
343 // ;; 5
344 a->nop(); // 21
345 a->fmr(F17, F17); // 22
346 a->fmr(F18, F18); // 23
347 a->endgroup(); // 24
348 // ------- sector 24 ------------
349
350 // ;; 6
351 a->nop(); // 25
352 a->nop(); // 26
353 a->fmr(F19, F19); // 27
354 a->fmr(F20, F20); // 28
355
356 // ;; 7
357 a->nop(); // 29
358 a->fmr(F21, F21); // 30
359 a->fmr(F22, F22); // 31
360 a->brnop0(); // 32
361
362 // ------- sector 32 ------------
363 }
364
365 // ;; 8
366 a->cmpdi(CCR0, R4, unroll); // 33
367 a->bge(CCR0, l1); // 34
368 a->blr();
369
370 // Emit code.
371 void (*test2)() = (void(*)())(void *)a->function_entry();
372 // uint32_t *code = (uint32_t *)a->pc();
373
374 Label l2;
375
376 a->li(R4, 1);
377 a->sldi(R4, R4, 28);
378 a->b(l2);
379 a->align(CodeEntryAlignment);
380
381 a->bind(l2);
382
383 for (int i = 0; i < unroll; i++) {
384 // Schleife 2
385 // ------- sector 0 ------------
386 // ;; 0
387 a->brnop0(); // 1
388 a->nop(); // 2
389 //a->cmpdi(CCR0, R4, unroll);
390 a->fpnop0(); // 3
391 a->fpnop1(); // 4
392 a->addi(R4,R4, -1); // 5
393
394 // ;; 1
395
396 a->nop(); // 6
397 a->fmr(F6, F6); // 7
398 a->fmr(F7, F7); // 8
399 // ------- sector 8 ---------------
400
401 // ;; 2
402 a->endgroup(); // 9
403
404 // ;; 3
405 a->nop(); // 10
406 a->nop(); // 11
407 a->fmr(F8, F8); // 12
408
409 // ;; 4
410 a->fmr(F9, F9); // 13
411 a->nop(); // 14
412 a->fmr(F10, F10); // 15
413
414 // ;; 5
415 a->fmr(F11, F11); // 16
416 // -------- sector 16 -------------
417
418 // ;; 6
419 a->endgroup(); // 17
420
421 // ;; 7
422 a->nop(); // 18
423 a->nop(); // 19
424 a->fmr(F15, F15); // 20
425
426 // ;; 8
427 a->fmr(F16, F16); // 21
428 a->nop(); // 22
429 a->fmr(F17, F17); // 23
430
431 // ;; 9
432 a->fmr(F18, F18); // 24
433 // -------- sector 24 -------------
434
435 // ;; 10
436 a->endgroup(); // 25
437
438 // ;; 11
439 a->nop(); // 26
440 a->nop(); // 27
441 a->fmr(F19, F19); // 28
442
443 // ;; 12
444 a->fmr(F20, F20); // 29
445 a->nop(); // 30
446 a->fmr(F21, F21); // 31
447
448 // ;; 13
449 a->fmr(F22, F22); // 32
450 }
451
452 // -------- sector 32 -------------
453 // ;; 14
454 a->cmpdi(CCR0, R4, unroll); // 33
455 a->bge(CCR0, l2); // 34
456
457 a->blr();
458 uint32_t *code_end = (uint32_t *)a->pc();
459 a->flush();
460
461 double loop1_seconds,loop2_seconds, rel_diff;
462 uint64_t start1, stop1;
463
464 start1 = os::current_thread_cpu_time(false);
465 (*test1)();
466 stop1 = os::current_thread_cpu_time(false);
467 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
468
469
470 start1 = os::current_thread_cpu_time(false);
471 (*test2)();
472 stop1 = os::current_thread_cpu_time(false);
473
474 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
475
476 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
477
478 if (PrintAssembly) {
479 ttyLocker ttyl;
480 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
481 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
482 tty->print_cr("Time loop1 :%f", loop1_seconds);
483 tty->print_cr("Time loop2 :%f", loop2_seconds);
484 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
485
486 if (rel_diff > 12.0) {
487 tty->print_cr("Section Size 8 Instructions");
488 } else{
489 tty->print_cr("Section Size 32 Instructions or Power5");
490 }
491 }
492
493 #if 0 // TODO: PPC port
494 // Set sector size (if not set explicitly).
495 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
496 if (rel_diff > 12.0) {
497 PdScheduling::power6SectorSize = 0x20;
498 } else {
499 PdScheduling::power6SectorSize = 0x80;
500 }
501 } else if (Power6SectorSize128PPC64) {
502 PdScheduling::power6SectorSize = 0x80;
503 } else {
504 PdScheduling::power6SectorSize = 0x20;
505 }
506 #endif
507 if (UsePower6SchedulerPPC64) Unimplemented();
508 }
509 #endif // COMPILER2
510
511 void VM_Version::determine_features() {
512 #if defined(ABI_ELFv2)
513 // 1 InstWord per call for the blr instruction.
514 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
515 #else
516 // 7 InstWords for each call (function descriptor + blr instruction).
517 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
518 #endif
519 int features = 0;
520
521 // create test area
522 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
523 char test_area[BUFFER_SIZE];
524 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
525
526 // Allocate space for the code.
527 ResourceMark rm;
528 CodeBuffer cb("detect_cpu_features", code_size, 0);
529 MacroAssembler* a = new MacroAssembler(&cb);
530
531 // Must be set to true so we can generate the test code.
532 _features = VM_Version::all_features_m;
533
534 // Emit code.
535 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
536 uint32_t *code = (uint32_t *)a->pc();
537 // Don't use R0 in ldarx.
538 // Keep R3_ARG1 unmodified, it contains &field (see below).
539 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
540 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
541 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
542 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
543 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
544 a->cmpb(R7, R5, R6); // code[4] -> cmpb
545 a->popcntb(R7, R5); // code[5] -> popcntb
546 a->popcntw(R7, R5); // code[6] -> popcntw
547 a->fcfids(F3, F4); // code[7] -> fcfids
548 a->vand(VR0, VR0, VR0); // code[8] -> vand
549 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
550 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
551 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
552 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
553 a->tcheck(0); // code[12] -> tcheck
554 a->blr();
555
556 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
557 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
558 a->dcbz(R3_ARG1); // R3_ARG1 = addr
559 a->blr();
560
561 uint32_t *code_end = (uint32_t *)a->pc();
562 a->flush();
563 _features = VM_Version::unknown_m;
564
565 // Print the detection code.
566 if (PrintAssembly) {
567 ttyLocker ttyl;
568 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
569 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
570 }
571
572 // Measure cache line size.
573 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
574 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
575 int count = 0; // count zeroed bytes
576 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
577 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
578 _measured_cache_line_size = count;
579
580 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
581 VM_Version::_is_determine_features_test_running = true;
582 // We must align the first argument to 16 bytes because of the lqarx check.
583 (*test)((address)align_size_up((intptr_t)mid_of_test_area, 16), (uint64_t)0);
584 VM_Version::_is_determine_features_test_running = false;
585
586 // determine which instructions are legal.
587 int feature_cntr = 0;
588 if (code[feature_cntr++]) features |= fsqrt_m;
589 if (code[feature_cntr++]) features |= fsqrts_m;
590 if (code[feature_cntr++]) features |= isel_m;
591 if (code[feature_cntr++]) features |= lxarxeh_m;
592 if (code[feature_cntr++]) features |= cmpb_m;
593 if (code[feature_cntr++]) features |= popcntb_m;
594 if (code[feature_cntr++]) features |= popcntw_m;
595 if (code[feature_cntr++]) features |= fcfids_m;
596 if (code[feature_cntr++]) features |= vand_m;
597 if (code[feature_cntr++]) features |= lqarx_m;
598 if (code[feature_cntr++]) features |= vcipher_m;
599 if (code[feature_cntr++]) features |= vpmsumb_m;
600 if (code[feature_cntr++]) features |= tcheck_m;
601
602 // Print the detection code.
603 if (PrintAssembly) {
604 ttyLocker ttyl;
605 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
606 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
607 }
608
609 _features = features;
610 }
611
612 // Power 8: Configure Data Stream Control Register.
613 void VM_Version::config_dscr() {
614 assert(has_tcheck(), "Only execute on Power 8 or later!");
615
616 // 7 InstWords for each call (function descriptor + blr instruction).
617 const int code_size = (2+2*7)*BytesPerInstWord;
618
619 // Allocate space for the code.
620 ResourceMark rm;
621 CodeBuffer cb("config_dscr", code_size, 0);
622 MacroAssembler* a = new MacroAssembler(&cb);
623
624 // Emit code.
625 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
626 uint32_t *code = (uint32_t *)a->pc();
627 a->mfdscr(R3);
628 a->blr();
629
630 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
631 a->mtdscr(R3);
632 a->blr();
633
634 uint32_t *code_end = (uint32_t *)a->pc();
635 a->flush();
636
637 // Print the detection code.
638 if (PrintAssembly) {
639 ttyLocker ttyl;
640 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
641 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
642 }
643
644 // Apply the configuration if needed.
645 uint64_t dscr_val = (*get_dscr)();
646 if (Verbose) {
647 tty->print_cr("dscr value was 0x%lx" , dscr_val);
648 }
649 bool change_requested = false;
650 if (DSCR_PPC64 != (uintx)-1) {
651 dscr_val = DSCR_PPC64;
652 change_requested = true;
653 }
654 if (DSCR_DPFD_PPC64 <= 7) {
655 uint64_t mask = 0x7;
656 if ((dscr_val & mask) != DSCR_DPFD_PPC64) {
657 dscr_val = (dscr_val & ~mask) | (DSCR_DPFD_PPC64);
658 change_requested = true;
659 }
660 }
661 if (DSCR_URG_PPC64 <= 7) {
662 uint64_t mask = 0x7 << 6;
663 if ((dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
664 dscr_val = (dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
665 change_requested = true;
666 }
667 }
668 if (change_requested) {
669 (*set_dscr)(dscr_val);
670 if (Verbose) {
671 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
672 }
673 }
674 }
675
676 static int saved_features = 0;
677
678 void VM_Version::allow_all() {
679 saved_features = _features;
680 _features = all_features_m;
681 }
682
683 void VM_Version::revert() {
684 _features = saved_features;
685 }