939 AddressLiteral al(addr, rspec);
940 internal_set(al, d, false);
941 }
942
943 void MacroAssembler::patchable_set(const AddressLiteral& al, Register d) {
944 internal_set(al, d, true);
945 }
946
947 void MacroAssembler::patchable_set(intptr_t value, Register d) {
948 AddressLiteral al(value);
949 internal_set(al, d, true);
950 }
951
952
953 void MacroAssembler::set64(jlong value, Register d, Register tmp) {
954 assert_not_delayed();
955 v9_dep();
956
957 int hi = (int)(value >> 32);
958 int lo = (int)(value & ~0);
959 // (Matcher::isSimpleConstant64 knows about the following optimizations.)
960 if (Assembler::is_simm13(lo) && value == lo) {
961 or3(G0, lo, d);
962 } else if (hi == 0) {
963 Assembler::sethi(lo, d); // hardware version zero-extends to upper 32
964 if (low10(lo) != 0)
965 or3(d, low10(lo), d);
966 }
967 else if (hi == -1) {
968 Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32
969 xor3(d, low10(lo) ^ ~low10(~0), d);
970 }
971 else if (lo == 0) {
972 if (Assembler::is_simm13(hi)) {
973 or3(G0, hi, d);
974 } else {
975 Assembler::sethi(hi, d); // hardware version zero-extends to upper 32
976 if (low10(hi) != 0)
977 or3(d, low10(hi), d);
978 }
979 sllx(d, 32, d);
980 }
981 else {
982 Assembler::sethi(hi, tmp);
983 Assembler::sethi(lo, d); // macro assembler version sign-extends
984 if (low10(hi) != 0)
985 or3 (tmp, low10(hi), tmp);
986 if (low10(lo) != 0)
4334
4335 Label bis_loop;
4336 bind(bis_loop);
4337 stxa(G0, to, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
4338 add(to, cache_line_size, to);
4339 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, bis_loop);
4340
4341 // BIS needs membar.
4342 membar(Assembler::StoreLoad);
4343
4344 add(end, (cache_line_size*2)-8, end); // restore end
4345 cmp_and_brx_short(to, end, Assembler::greaterEqualUnsigned, Assembler::pn, Ldone);
4346
4347 // Clean the tail.
4348 bind(small_loop);
4349 stx(G0, to, 0);
4350 add(to, 8, to);
4351 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, small_loop);
4352 nop(); // Separate short branches
4353 }
|
939 AddressLiteral al(addr, rspec);
940 internal_set(al, d, false);
941 }
942
943 void MacroAssembler::patchable_set(const AddressLiteral& al, Register d) {
944 internal_set(al, d, true);
945 }
946
947 void MacroAssembler::patchable_set(intptr_t value, Register d) {
948 AddressLiteral al(value);
949 internal_set(al, d, true);
950 }
951
952
953 void MacroAssembler::set64(jlong value, Register d, Register tmp) {
954 assert_not_delayed();
955 v9_dep();
956
957 int hi = (int)(value >> 32);
958 int lo = (int)(value & ~0);
959 int bits_33to2 = (int)((value >> 2) & ~0);
960 // (Matcher::isSimpleConstant64 knows about the following optimizations.)
961 if (Assembler::is_simm13(lo) && value == lo) {
962 or3(G0, lo, d);
963 } else if (hi == 0) {
964 Assembler::sethi(lo, d); // hardware version zero-extends to upper 32
965 if (low10(lo) != 0)
966 or3(d, low10(lo), d);
967 }
968 else if ((hi >> 2) == 0) {
969 Assembler::sethi(bits_33to2, d); // hardware version zero-extends to upper 32
970 sllx(d, 2, d);
971 if (low12(lo) != 0)
972 or3(d, low12(lo), d);
973 }
974 else if (hi == -1) {
975 Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32
976 xor3(d, low10(lo) ^ ~low10(~0), d);
977 }
978 else if (lo == 0) {
979 if (Assembler::is_simm13(hi)) {
980 or3(G0, hi, d);
981 } else {
982 Assembler::sethi(hi, d); // hardware version zero-extends to upper 32
983 if (low10(hi) != 0)
984 or3(d, low10(hi), d);
985 }
986 sllx(d, 32, d);
987 }
988 else {
989 Assembler::sethi(hi, tmp);
990 Assembler::sethi(lo, d); // macro assembler version sign-extends
991 if (low10(hi) != 0)
992 or3 (tmp, low10(hi), tmp);
993 if (low10(lo) != 0)
4341
4342 Label bis_loop;
4343 bind(bis_loop);
4344 stxa(G0, to, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
4345 add(to, cache_line_size, to);
4346 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, bis_loop);
4347
4348 // BIS needs membar.
4349 membar(Assembler::StoreLoad);
4350
4351 add(end, (cache_line_size*2)-8, end); // restore end
4352 cmp_and_brx_short(to, end, Assembler::greaterEqualUnsigned, Assembler::pn, Ldone);
4353
4354 // Clean the tail.
4355 bind(small_loop);
4356 stx(G0, to, 0);
4357 add(to, 8, to);
4358 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, small_loop);
4359 nop(); // Separate short branches
4360 }
4361
4362 /**
4363 * Update CRC-32[C] with a byte value according to constants in table
4364 *
4365 * @param [in,out]crc Register containing the crc.
4366 * @param [in]val Register containing the byte to fold into the CRC.
4367 * @param [in]table Register containing the table of crc constants.
4368 *
4369 * uint32_t crc;
4370 * val = crc_table[(val ^ crc) & 0xFF];
4371 * crc = val ^ (crc >> 8);
4372 */
4373 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
4374 xor3(val, crc, val);
4375 and3(val, 0xFF, val);
4376 sllx(val, 2, val);
4377 lduw(table, val, val);
4378 srlx(crc, 8, crc);
4379 xor3(val, crc, crc);
4380 }
4381
4382 // Reverse byte order of lower 32 bits, assuming upper 32 bits all zeros
4383 void MacroAssembler::reverse_bytes_32(Register src, Register dst, Register tmp) {
4384 srlx(src, 24, dst);
4385
4386 sllx(src, 32+8, tmp);
4387 srlx(tmp, 32+24, tmp);
4388 sllx(tmp, 8, tmp);
4389 or3(dst, tmp, dst);
4390
4391 sllx(src, 32+16, tmp);
4392 srlx(tmp, 32+24, tmp);
4393 sllx(tmp, 16, tmp);
4394 or3(dst, tmp, dst);
4395
4396 sllx(src, 32+24, tmp);
4397 srlx(tmp, 32, tmp);
4398 or3(dst, tmp, dst);
4399 }
4400
4401 void MacroAssembler::movitof_revbytes(Register src, FloatRegister dst, Register tmp1, Register tmp2) {
4402 reverse_bytes_32(src, tmp1, tmp2);
4403 movxtod(tmp1, dst);
4404 }
4405
4406 void MacroAssembler::movftoi_revbytes(FloatRegister src, Register dst, Register tmp1, Register tmp2) {
4407 movdtox(src, tmp1);
4408 reverse_bytes_32(tmp1, dst, tmp2);
4409 }
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