682 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
683 UseGHASHIntrinsics = true;
684 }
685 } else if (UseGHASHIntrinsics) {
686 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
687 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
688 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
689 }
690
691 if (UseSHA) {
692 warning("SHA instructions are not available on this CPU");
693 FLAG_SET_DEFAULT(UseSHA, false);
694 }
695 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
696 warning("SHA intrinsics are not available on this CPU");
697 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
698 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
699 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
700 }
701
702 // Adjust RTM (Restricted Transactional Memory) flags
703 if (!supports_rtm() && UseRTMLocking) {
704 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
705 // setting during arguments processing. See use_biased_locking().
706 // VM_Version_init() is executed after UseBiasedLocking is used
707 // in Thread::allocate().
708 vm_exit_during_initialization("RTM instructions are not available on this CPU");
709 }
710
711 #if INCLUDE_RTM_OPT
712 if (UseRTMLocking) {
713 if (is_intel_family_core()) {
714 if ((_model == CPU_MODEL_HASWELL_E3) ||
715 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
716 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) {
717 // currently a collision between SKL and HSW_E3
718 if (!UnlockExperimentalVMOptions && UseAVX < 3) {
719 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
720 } else {
721 warning("UseRTMLocking is only available as experimental option on this platform.");
|
682 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
683 UseGHASHIntrinsics = true;
684 }
685 } else if (UseGHASHIntrinsics) {
686 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
687 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
688 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
689 }
690
691 if (UseSHA) {
692 warning("SHA instructions are not available on this CPU");
693 FLAG_SET_DEFAULT(UseSHA, false);
694 }
695 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
696 warning("SHA intrinsics are not available on this CPU");
697 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
698 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
699 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
700 }
701
702 if (UseCRC32CIntrinsics) {
703 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
704 warning("CRC32C intrinsics are not available on this CPU");
705 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
706 }
707
708 // Adjust RTM (Restricted Transactional Memory) flags
709 if (!supports_rtm() && UseRTMLocking) {
710 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
711 // setting during arguments processing. See use_biased_locking().
712 // VM_Version_init() is executed after UseBiasedLocking is used
713 // in Thread::allocate().
714 vm_exit_during_initialization("RTM instructions are not available on this CPU");
715 }
716
717 #if INCLUDE_RTM_OPT
718 if (UseRTMLocking) {
719 if (is_intel_family_core()) {
720 if ((_model == CPU_MODEL_HASWELL_E3) ||
721 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
722 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) {
723 // currently a collision between SKL and HSW_E3
724 if (!UnlockExperimentalVMOptions && UseAVX < 3) {
725 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
726 } else {
727 warning("UseRTMLocking is only available as experimental option on this platform.");
|