3342 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3343 }
3344
3345 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3346 assert(VM_Version::supports_avx(), "");
3347 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3348 }
3349
3350 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3351 assert(VM_Version::supports_avx(), "");
3352 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3353 }
3354
3355 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3356 assert(VM_Version::supports_avx(), "");
3357 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3358 }
3359
3360
3361 // Integer vector arithmetic
3362 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
3363 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3364 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
3365 }
3366
3367 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
3368 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3369 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
3370 }
3371
3372 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
3373 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3374 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
3375 }
3376
3377 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
3378 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3379 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
3380 }
3381
3382 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3383 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3384 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3385 }
3386
3387 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3388 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3389 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3390 }
3391
3392 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3393 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3394 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3395 }
3396
3397 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3398 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3399 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3400 }
3401
3783 assert(VM_Version::supports_avx(), "");
3784 bool vector256 = true;
3785 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3786 emit_int8(0x18);
3787 emit_int8((unsigned char)(0xC0 | encode));
3788 // 0x00 - insert into lower 128 bits
3789 // 0x01 - insert into upper 128 bits
3790 emit_int8(0x01);
3791 }
3792
3793 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
3794 assert(VM_Version::supports_avx(), "");
3795 InstructionMark im(this);
3796 bool vector256 = true;
3797 assert(dst != xnoreg, "sanity");
3798 int dst_enc = dst->encoding();
3799 // swap src<->dst for encoding
3800 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3801 emit_int8(0x18);
3802 emit_operand(dst, src);
3803 // 0x01 - insert into upper 128 bits
3804 emit_int8(0x01);
3805 }
3806
3807 void Assembler::vextractf128h(Address dst, XMMRegister src) {
3808 assert(VM_Version::supports_avx(), "");
3809 InstructionMark im(this);
3810 bool vector256 = true;
3811 assert(src != xnoreg, "sanity");
3812 int src_enc = src->encoding();
3813 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3814 emit_int8(0x19);
3815 emit_operand(src, dst);
3816 // 0x01 - extract from upper 128 bits
3817 emit_int8(0x01);
3818 }
3819
3820 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3821 assert(VM_Version::supports_avx2(), "");
3822 bool vector256 = true;
|
3342 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3343 }
3344
3345 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3346 assert(VM_Version::supports_avx(), "");
3347 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3348 }
3349
3350 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3351 assert(VM_Version::supports_avx(), "");
3352 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3353 }
3354
3355 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3356 assert(VM_Version::supports_avx(), "");
3357 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3358 }
3359
3360
3361 // Integer vector arithmetic
3362 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3363 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3364 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3365 emit_int8(0x01);
3366 emit_int8((unsigned char)(0xC0 | encode));
3367 }
3368
3369 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3370 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3371 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3372 emit_int8(0x02);
3373 emit_int8((unsigned char)(0xC0 | encode));
3374 }
3375
3376 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
3377 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3378 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
3379 }
3380
3381 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
3382 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3383 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
3384 }
3385
3386 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
3387 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3388 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
3389 }
3390
3391 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
3392 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3393 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
3394 }
3395
3396 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
3397 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
3398 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
3399 emit_int8(0x01);
3400 emit_int8((unsigned char)(0xC0 | encode));
3401 }
3402
3403 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
3404 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
3405 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
3406 emit_int8(0x02);
3407 emit_int8((unsigned char)(0xC0 | encode));
3408 }
3409
3410 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3411 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3412 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3413 }
3414
3415 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3416 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3417 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3418 }
3419
3420 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3421 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3422 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3423 }
3424
3425 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3426 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3427 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3428 }
3429
3811 assert(VM_Version::supports_avx(), "");
3812 bool vector256 = true;
3813 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3814 emit_int8(0x18);
3815 emit_int8((unsigned char)(0xC0 | encode));
3816 // 0x00 - insert into lower 128 bits
3817 // 0x01 - insert into upper 128 bits
3818 emit_int8(0x01);
3819 }
3820
3821 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
3822 assert(VM_Version::supports_avx(), "");
3823 InstructionMark im(this);
3824 bool vector256 = true;
3825 assert(dst != xnoreg, "sanity");
3826 int dst_enc = dst->encoding();
3827 // swap src<->dst for encoding
3828 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3829 emit_int8(0x18);
3830 emit_operand(dst, src);
3831 // 0x01 - insert into upper 128 bits
3832 emit_int8(0x01);
3833 }
3834
3835 void Assembler::vextractf128h(XMMRegister dst, XMMRegister src) {
3836 assert(VM_Version::supports_avx(), "");
3837 bool vector256 = true;
3838 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3839 emit_int8(0x19);
3840 emit_int8((unsigned char)(0xC0 | encode));
3841 // 0x00 - insert into lower 128 bits
3842 // 0x01 - insert into upper 128 bits
3843 emit_int8(0x01);
3844 }
3845
3846 void Assembler::vextractf128h(Address dst, XMMRegister src) {
3847 assert(VM_Version::supports_avx(), "");
3848 InstructionMark im(this);
3849 bool vector256 = true;
3850 assert(src != xnoreg, "sanity");
3851 int src_enc = src->encoding();
3852 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3853 emit_int8(0x19);
3854 emit_operand(src, dst);
3855 // 0x01 - extract from upper 128 bits
3856 emit_int8(0x01);
3857 }
3858
3859 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3860 assert(VM_Version::supports_avx2(), "");
3861 bool vector256 = true;
|