1 //
2 // Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Class for all pointer registers (including RSP)
170 reg_class any_reg(RAX, RAX_H,
171 RDX, RDX_H,
172 RBP, RBP_H,
173 RDI, RDI_H,
174 RSI, RSI_H,
175 RCX, RCX_H,
176 RBX, RBX_H,
177 RSP, RSP_H,
178 R8, R8_H,
179 R9, R9_H,
180 R10, R10_H,
181 R11, R11_H,
182 R12, R12_H,
183 R13, R13_H,
184 R14, R14_H,
185 R15, R15_H);
186
187 // Class for all pointer registers except RSP
188 reg_class ptr_reg(RAX, RAX_H,
189 RDX, RDX_H,
190 RBP, RBP_H,
191 RDI, RDI_H,
192 RSI, RSI_H,
193 RCX, RCX_H,
194 RBX, RBX_H,
195 R8, R8_H,
196 R9, R9_H,
197 R10, R10_H,
198 R11, R11_H,
199 R13, R13_H,
200 R14, R14_H);
201
202 // Class for all pointer registers except RAX and RSP
203 reg_class ptr_no_rax_reg(RDX, RDX_H,
204 RBP, RBP_H,
205 RDI, RDI_H,
206 RSI, RSI_H,
207 RCX, RCX_H,
208 RBX, RBX_H,
209 R8, R8_H,
210 R9, R9_H,
211 R10, R10_H,
212 R11, R11_H,
213 R13, R13_H,
214 R14, R14_H);
215
216 reg_class ptr_no_rbp_reg(RDX, RDX_H,
217 RAX, RAX_H,
218 RDI, RDI_H,
219 RSI, RSI_H,
220 RCX, RCX_H,
221 RBX, RBX_H,
222 R8, R8_H,
223 R9, R9_H,
224 R10, R10_H,
225 R11, R11_H,
226 R13, R13_H,
227 R14, R14_H);
228
229 // Class for all pointer registers except RAX, RBX and RSP
230 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
231 RBP, RBP_H,
232 RDI, RDI_H,
233 RSI, RSI_H,
234 RCX, RCX_H,
235 R8, R8_H,
236 R9, R9_H,
237 R10, R10_H,
238 R11, R11_H,
239 R13, R13_H,
240 R14, R14_H);
241
242 // Singleton class for RAX pointer register
243 reg_class ptr_rax_reg(RAX, RAX_H);
244
245 // Singleton class for RBX pointer register
246 reg_class ptr_rbx_reg(RBX, RBX_H);
247
248 // Singleton class for RSI pointer register
249 reg_class ptr_rsi_reg(RSI, RSI_H);
250
251 // Singleton class for RDI pointer register
252 reg_class ptr_rdi_reg(RDI, RDI_H);
253
254 // Singleton class for RBP pointer register
255 reg_class ptr_rbp_reg(RBP, RBP_H);
256
257 // Singleton class for stack pointer
258 reg_class ptr_rsp_reg(RSP, RSP_H);
259
260 // Singleton class for TLS pointer
261 reg_class ptr_r15_reg(R15, R15_H);
262
263 // Class for all long registers (except RSP)
264 reg_class long_reg(RAX, RAX_H,
265 RDX, RDX_H,
266 RBP, RBP_H,
267 RDI, RDI_H,
268 RSI, RSI_H,
269 RCX, RCX_H,
270 RBX, RBX_H,
271 R8, R8_H,
272 R9, R9_H,
273 R10, R10_H,
274 R11, R11_H,
275 R13, R13_H,
276 R14, R14_H);
277
278 // Class for all long registers except RAX, RDX (and RSP)
279 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
280 RDI, RDI_H,
281 RSI, RSI_H,
282 RCX, RCX_H,
283 RBX, RBX_H,
284 R8, R8_H,
285 R9, R9_H,
286 R10, R10_H,
287 R11, R11_H,
288 R13, R13_H,
289 R14, R14_H);
290
291 // Class for all long registers except RCX (and RSP)
292 reg_class long_no_rcx_reg(RBP, RBP_H,
293 RDI, RDI_H,
294 RSI, RSI_H,
295 RAX, RAX_H,
296 RDX, RDX_H,
297 RBX, RBX_H,
298 R8, R8_H,
299 R9, R9_H,
300 R10, R10_H,
301 R11, R11_H,
302 R13, R13_H,
303 R14, R14_H);
304
305 // Class for all long registers except RAX (and RSP)
306 reg_class long_no_rax_reg(RBP, RBP_H,
307 RDX, RDX_H,
308 RDI, RDI_H,
309 RSI, RSI_H,
310 RCX, RCX_H,
311 RBX, RBX_H,
312 R8, R8_H,
313 R9, R9_H,
314 R10, R10_H,
315 R11, R11_H,
316 R13, R13_H,
317 R14, R14_H);
318
319 // Singleton class for RAX long register
320 reg_class long_rax_reg(RAX, RAX_H);
321
322 // Singleton class for RCX long register
323 reg_class long_rcx_reg(RCX, RCX_H);
324
325 // Singleton class for RDX long register
326 reg_class long_rdx_reg(RDX, RDX_H);
327
328 // Class for all int registers (except RSP)
329 reg_class int_reg(RAX,
330 RDX,
331 RBP,
332 RDI,
333 RSI,
334 RCX,
335 RBX,
336 R8,
337 R9,
338 R10,
339 R11,
340 R13,
341 R14);
342
343 // Class for all int registers except RCX (and RSP)
344 reg_class int_no_rcx_reg(RAX,
345 RDX,
346 RBP,
347 RDI,
348 RSI,
349 RBX,
350 R8,
351 R9,
352 R10,
353 R11,
354 R13,
355 R14);
356
357 // Class for all int registers except RAX, RDX (and RSP)
358 reg_class int_no_rax_rdx_reg(RBP,
359 RDI,
360 RSI,
361 RCX,
362 RBX,
363 R8,
364 R9,
365 R10,
366 R11,
367 R13,
368 R14);
369
370 // Singleton class for RAX int register
371 reg_class int_rax_reg(RAX);
372
373 // Singleton class for RBX int register
374 reg_class int_rbx_reg(RBX);
375
376 // Singleton class for RCX int register
377 reg_class int_rcx_reg(RCX);
378
379 // Singleton class for RCX int register
380 reg_class int_rdx_reg(RDX);
381
382 // Singleton class for RCX int register
383 reg_class int_rdi_reg(RDI);
384
385 // Singleton class for instruction pointer
386 // reg_class ip_reg(RIP);
387
388 %}
389
390 //----------SOURCE BLOCK-------------------------------------------------------
391 // This is a block of C++ code which provides values, functions, and
392 // definitions necessary in the rest of the architecture description
393 source %{
394 #define RELOC_IMM64 Assembler::imm_operand
395 #define RELOC_DISP32 Assembler::disp32_operand
396
397 #define __ _masm.
398
399 static int preserve_SP_size() {
400 return 3; // rex.w, op, rm(reg/reg)
401 }
402 static int clear_avx_size() {
403 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
404 }
405
406 // !!!!! Special hack to get all types of calls to specify the byte offset
407 // from the start of the call to the point where the return address
408 // will point.
409 int MachCallStaticJavaNode::ret_addr_offset()
410 {
411 int offset = 5; // 5 bytes from start of call to where return address points
412 offset += clear_avx_size();
413 if (_method_handle_invoke)
414 offset += preserve_SP_size();
415 return offset;
416 }
417
418 int MachCallDynamicJavaNode::ret_addr_offset()
419 {
420 int offset = 15; // 15 bytes from start of call to where return address points
421 offset += clear_avx_size();
422 return offset;
423 }
424
425 int MachCallRuntimeNode::ret_addr_offset() {
426 int offset = 13; // movq r10,#addr; callq (r10)
427 offset += clear_avx_size();
428 return offset;
429 }
430
431 // Indicate if the safepoint node needs the polling page as an input,
432 // it does if the polling page is more than disp32 away.
433 bool SafePointNode::needs_polling_address_input()
434 {
435 return Assembler::is_polling_page_far();
436 }
437
438 //
439 // Compute padding required for nodes which need alignment
440 //
441
442 // The address of the call instruction needs to be 4-byte aligned to
443 // ensure that it does not span a cache line so that it can be patched.
444 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
445 {
446 current_offset += clear_avx_size(); // skip vzeroupper
447 current_offset += 1; // skip call opcode byte
448 return round_to(current_offset, alignment_required()) - current_offset;
449 }
450
451 // The address of the call instruction needs to be 4-byte aligned to
452 // ensure that it does not span a cache line so that it can be patched.
453 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
454 {
455 current_offset += preserve_SP_size(); // skip mov rbp, rsp
456 current_offset += clear_avx_size(); // skip vzeroupper
457 current_offset += 1; // skip call opcode byte
458 return round_to(current_offset, alignment_required()) - current_offset;
459 }
460
461 // The address of the call instruction needs to be 4-byte aligned to
462 // ensure that it does not span a cache line so that it can be patched.
463 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
464 {
465 current_offset += clear_avx_size(); // skip vzeroupper
466 current_offset += 11; // skip movq instruction + call opcode byte
467 return round_to(current_offset, alignment_required()) - current_offset;
468 }
469
470 // EMIT_RM()
471 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
472 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
473 cbuf.insts()->emit_int8(c);
474 }
475
476 // EMIT_CC()
477 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
478 unsigned char c = (unsigned char) (f1 | f2);
479 cbuf.insts()->emit_int8(c);
480 }
481
482 // EMIT_OPCODE()
483 void emit_opcode(CodeBuffer &cbuf, int code) {
484 cbuf.insts()->emit_int8((unsigned char) code);
485 }
486
487 // EMIT_OPCODE() w/ relocation information
488 void emit_opcode(CodeBuffer &cbuf,
489 int code, relocInfo::relocType reloc, int offset, int format)
490 {
491 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
492 emit_opcode(cbuf, code);
493 }
494
495 // EMIT_D8()
496 void emit_d8(CodeBuffer &cbuf, int d8) {
497 cbuf.insts()->emit_int8((unsigned char) d8);
498 }
499
500 // EMIT_D16()
501 void emit_d16(CodeBuffer &cbuf, int d16) {
502 cbuf.insts()->emit_int16(d16);
503 }
504
505 // EMIT_D32()
506 void emit_d32(CodeBuffer &cbuf, int d32) {
507 cbuf.insts()->emit_int32(d32);
508 }
509
510 // EMIT_D64()
511 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
512 cbuf.insts()->emit_int64(d64);
513 }
514
515 // emit 32 bit value and construct relocation entry from relocInfo::relocType
516 void emit_d32_reloc(CodeBuffer& cbuf,
517 int d32,
518 relocInfo::relocType reloc,
519 int format)
520 {
521 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
522 cbuf.relocate(cbuf.insts_mark(), reloc, format);
523 cbuf.insts()->emit_int32(d32);
524 }
525
526 // emit 32 bit value and construct relocation entry from RelocationHolder
527 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
528 #ifdef ASSERT
529 if (rspec.reloc()->type() == relocInfo::oop_type &&
530 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
531 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
532 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
533 }
534 #endif
535 cbuf.relocate(cbuf.insts_mark(), rspec, format);
536 cbuf.insts()->emit_int32(d32);
537 }
538
539 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
540 address next_ip = cbuf.insts_end() + 4;
541 emit_d32_reloc(cbuf, (int) (addr - next_ip),
542 external_word_Relocation::spec(addr),
543 RELOC_DISP32);
544 }
545
546
547 // emit 64 bit value and construct relocation entry from relocInfo::relocType
548 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
549 cbuf.relocate(cbuf.insts_mark(), reloc, format);
550 cbuf.insts()->emit_int64(d64);
551 }
552
553 // emit 64 bit value and construct relocation entry from RelocationHolder
554 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
555 #ifdef ASSERT
556 if (rspec.reloc()->type() == relocInfo::oop_type &&
557 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
558 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
559 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
560 "cannot embed scavengable oops in code");
561 }
562 #endif
563 cbuf.relocate(cbuf.insts_mark(), rspec, format);
564 cbuf.insts()->emit_int64(d64);
565 }
566
567 // Access stack slot for load or store
568 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
569 {
570 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
571 if (-0x80 <= disp && disp < 0x80) {
572 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
573 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
574 emit_d8(cbuf, disp); // Displacement // R/M byte
575 } else {
576 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
577 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
578 emit_d32(cbuf, disp); // Displacement // R/M byte
579 }
580 }
581
582 // rRegI ereg, memory mem) %{ // emit_reg_mem
583 void encode_RegMem(CodeBuffer &cbuf,
584 int reg,
585 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
586 {
587 assert(disp_reloc == relocInfo::none, "cannot have disp");
588 int regenc = reg & 7;
589 int baseenc = base & 7;
590 int indexenc = index & 7;
591
592 // There is no index & no scale, use form without SIB byte
593 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
594 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
595 if (disp == 0 && base != RBP_enc && base != R13_enc) {
596 emit_rm(cbuf, 0x0, regenc, baseenc); // *
597 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
598 // If 8-bit displacement, mode 0x1
599 emit_rm(cbuf, 0x1, regenc, baseenc); // *
600 emit_d8(cbuf, disp);
601 } else {
602 // If 32-bit displacement
603 if (base == -1) { // Special flag for absolute address
604 emit_rm(cbuf, 0x0, regenc, 0x5); // *
605 if (disp_reloc != relocInfo::none) {
606 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
607 } else {
608 emit_d32(cbuf, disp);
609 }
610 } else {
611 // Normal base + offset
612 emit_rm(cbuf, 0x2, regenc, baseenc); // *
613 if (disp_reloc != relocInfo::none) {
614 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
615 } else {
616 emit_d32(cbuf, disp);
617 }
618 }
619 }
620 } else {
621 // Else, encode with the SIB byte
622 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
623 if (disp == 0 && base != RBP_enc && base != R13_enc) {
624 // If no displacement
625 emit_rm(cbuf, 0x0, regenc, 0x4); // *
626 emit_rm(cbuf, scale, indexenc, baseenc);
627 } else {
628 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
629 // If 8-bit displacement, mode 0x1
630 emit_rm(cbuf, 0x1, regenc, 0x4); // *
631 emit_rm(cbuf, scale, indexenc, baseenc);
632 emit_d8(cbuf, disp);
633 } else {
634 // If 32-bit displacement
635 if (base == 0x04 ) {
636 emit_rm(cbuf, 0x2, regenc, 0x4);
637 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
638 } else {
639 emit_rm(cbuf, 0x2, regenc, 0x4);
640 emit_rm(cbuf, scale, indexenc, baseenc); // *
641 }
642 if (disp_reloc != relocInfo::none) {
643 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
644 } else {
645 emit_d32(cbuf, disp);
646 }
647 }
648 }
649 }
650 }
651
652 // This could be in MacroAssembler but it's fairly C2 specific
653 void emit_cmpfp_fixup(MacroAssembler& _masm) {
654 Label exit;
655 __ jccb(Assembler::noParity, exit);
656 __ pushf();
657 //
658 // comiss/ucomiss instructions set ZF,PF,CF flags and
659 // zero OF,AF,SF for NaN values.
660 // Fixup flags by zeroing ZF,PF so that compare of NaN
661 // values returns 'less than' result (CF is set).
662 // Leave the rest of flags unchanged.
663 //
664 // 7 6 5 4 3 2 1 0
665 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
666 // 0 0 1 0 1 0 1 1 (0x2B)
667 //
668 __ andq(Address(rsp, 0), 0xffffff2b);
669 __ popf();
670 __ bind(exit);
671 }
672
673 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
674 Label done;
675 __ movl(dst, -1);
676 __ jcc(Assembler::parity, done);
677 __ jcc(Assembler::below, done);
678 __ setb(Assembler::notEqual, dst);
679 __ movzbl(dst, dst);
680 __ bind(done);
681 }
682
683
684 //=============================================================================
685 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
686
687 int Compile::ConstantTable::calculate_table_base_offset() const {
688 return 0; // absolute addressing, no offset
689 }
690
691 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
692 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
693 ShouldNotReachHere();
694 }
695
696 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
697 // Empty encoding
698 }
699
700 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
701 return 0;
702 }
703
704 #ifndef PRODUCT
705 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
706 st->print("# MachConstantBaseNode (empty encoding)");
707 }
708 #endif
709
710
711 //=============================================================================
712 #ifndef PRODUCT
713 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
714 Compile* C = ra_->C;
715
716 int framesize = C->frame_size_in_bytes();
717 int bangsize = C->bang_size_in_bytes();
718 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
719 // Remove wordSize for return addr which is already pushed.
720 framesize -= wordSize;
721
722 if (C->need_stack_bang(bangsize)) {
723 framesize -= wordSize;
724 st->print("# stack bang (%d bytes)", bangsize);
725 st->print("\n\t");
726 st->print("pushq rbp\t# Save rbp");
727 if (framesize) {
728 st->print("\n\t");
729 st->print("subq rsp, #%d\t# Create frame",framesize);
730 }
731 } else {
732 st->print("subq rsp, #%d\t# Create frame",framesize);
733 st->print("\n\t");
734 framesize -= wordSize;
735 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
736 }
737
738 if (VerifyStackAtCalls) {
739 st->print("\n\t");
740 framesize -= wordSize;
741 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
742 #ifdef ASSERT
743 st->print("\n\t");
744 st->print("# stack alignment check");
745 #endif
746 }
747 st->cr();
748 }
749 #endif
750
751 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
752 Compile* C = ra_->C;
753 MacroAssembler _masm(&cbuf);
754
755 int framesize = C->frame_size_in_bytes();
756 int bangsize = C->bang_size_in_bytes();
757
758 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
759
760 C->set_frame_complete(cbuf.insts_size());
761
762 if (C->has_mach_constant_base_node()) {
763 // NOTE: We set the table base offset here because users might be
764 // emitted before MachConstantBaseNode.
765 Compile::ConstantTable& constant_table = C->constant_table();
766 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
767 }
768 }
769
770 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
771 {
772 return MachNode::size(ra_); // too many variables; just compute it
773 // the hard way
774 }
775
776 int MachPrologNode::reloc() const
777 {
778 return 0; // a large enough number
779 }
780
781 //=============================================================================
782 #ifndef PRODUCT
783 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
784 {
785 Compile* C = ra_->C;
786 if (C->max_vector_size() > 16) {
787 st->print("vzeroupper");
788 st->cr(); st->print("\t");
789 }
790
791 int framesize = C->frame_size_in_bytes();
792 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
793 // Remove word for return adr already pushed
794 // and RBP
795 framesize -= 2*wordSize;
796
797 if (framesize) {
798 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
799 st->print("\t");
800 }
801
802 st->print_cr("popq rbp");
803 if (do_polling() && C->is_method_compilation()) {
804 st->print("\t");
805 if (Assembler::is_polling_page_far()) {
806 st->print_cr("movq rscratch1, #polling_page_address\n\t"
807 "testl rax, [rscratch1]\t"
808 "# Safepoint: poll for GC");
809 } else {
810 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
811 "# Safepoint: poll for GC");
812 }
813 }
814 }
815 #endif
816
817 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
818 {
819 Compile* C = ra_->C;
820 if (C->max_vector_size() > 16) {
821 // Clear upper bits of YMM registers when current compiled code uses
822 // wide vectors to avoid AVX <-> SSE transition penalty during call.
823 MacroAssembler _masm(&cbuf);
824 __ vzeroupper();
825 }
826
827 int framesize = C->frame_size_in_bytes();
828 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
829 // Remove word for return adr already pushed
830 // and RBP
831 framesize -= 2*wordSize;
832
833 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
834
835 if (framesize) {
836 emit_opcode(cbuf, Assembler::REX_W);
837 if (framesize < 0x80) {
838 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
839 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
840 emit_d8(cbuf, framesize);
841 } else {
842 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
843 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
844 emit_d32(cbuf, framesize);
845 }
846 }
847
848 // popq rbp
849 emit_opcode(cbuf, 0x58 | RBP_enc);
850
851 if (do_polling() && C->is_method_compilation()) {
852 MacroAssembler _masm(&cbuf);
853 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
854 if (Assembler::is_polling_page_far()) {
855 __ lea(rscratch1, polling_page);
856 __ relocate(relocInfo::poll_return_type);
857 __ testl(rax, Address(rscratch1, 0));
858 } else {
859 __ testl(rax, polling_page);
860 }
861 }
862 }
863
864 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
865 {
866 return MachNode::size(ra_); // too many variables; just compute it
867 // the hard way
868 }
869
870 int MachEpilogNode::reloc() const
871 {
872 return 2; // a large enough number
873 }
874
875 const Pipeline* MachEpilogNode::pipeline() const
876 {
877 return MachNode::pipeline_class();
878 }
879
880 int MachEpilogNode::safepoint_offset() const
881 {
882 return 0;
883 }
884
885 //=============================================================================
886
887 enum RC {
888 rc_bad,
889 rc_int,
890 rc_float,
891 rc_stack
892 };
893
894 static enum RC rc_class(OptoReg::Name reg)
895 {
896 if( !OptoReg::is_valid(reg) ) return rc_bad;
897
898 if (OptoReg::is_stack(reg)) return rc_stack;
899
900 VMReg r = OptoReg::as_VMReg(reg);
901
902 if (r->is_Register()) return rc_int;
903
904 assert(r->is_XMMRegister(), "must be");
905 return rc_float;
906 }
907
908 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
909 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
910 int src_hi, int dst_hi, uint ireg, outputStream* st);
911
912 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
913 int stack_offset, int reg, uint ireg, outputStream* st);
914
915 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
916 int dst_offset, uint ireg, outputStream* st) {
917 if (cbuf) {
918 MacroAssembler _masm(cbuf);
919 switch (ireg) {
920 case Op_VecS:
921 __ movq(Address(rsp, -8), rax);
922 __ movl(rax, Address(rsp, src_offset));
923 __ movl(Address(rsp, dst_offset), rax);
924 __ movq(rax, Address(rsp, -8));
925 break;
926 case Op_VecD:
927 __ pushq(Address(rsp, src_offset));
928 __ popq (Address(rsp, dst_offset));
929 break;
930 case Op_VecX:
931 __ pushq(Address(rsp, src_offset));
932 __ popq (Address(rsp, dst_offset));
933 __ pushq(Address(rsp, src_offset+8));
934 __ popq (Address(rsp, dst_offset+8));
935 break;
936 case Op_VecY:
937 __ vmovdqu(Address(rsp, -32), xmm0);
938 __ vmovdqu(xmm0, Address(rsp, src_offset));
939 __ vmovdqu(Address(rsp, dst_offset), xmm0);
940 __ vmovdqu(xmm0, Address(rsp, -32));
941 break;
942 default:
943 ShouldNotReachHere();
944 }
945 #ifndef PRODUCT
946 } else {
947 switch (ireg) {
948 case Op_VecS:
949 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
950 "movl rax, [rsp + #%d]\n\t"
951 "movl [rsp + #%d], rax\n\t"
952 "movq rax, [rsp - #8]",
953 src_offset, dst_offset);
954 break;
955 case Op_VecD:
956 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
957 "popq [rsp + #%d]",
958 src_offset, dst_offset);
959 break;
960 case Op_VecX:
961 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
962 "popq [rsp + #%d]\n\t"
963 "pushq [rsp + #%d]\n\t"
964 "popq [rsp + #%d]",
965 src_offset, dst_offset, src_offset+8, dst_offset+8);
966 break;
967 case Op_VecY:
968 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
969 "vmovdqu xmm0, [rsp + #%d]\n\t"
970 "vmovdqu [rsp + #%d], xmm0\n\t"
971 "vmovdqu xmm0, [rsp - #32]",
972 src_offset, dst_offset);
973 break;
974 default:
975 ShouldNotReachHere();
976 }
977 #endif
978 }
979 }
980
981 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
982 PhaseRegAlloc* ra_,
983 bool do_size,
984 outputStream* st) const {
985 assert(cbuf != NULL || st != NULL, "sanity");
986 // Get registers to move
987 OptoReg::Name src_second = ra_->get_reg_second(in(1));
988 OptoReg::Name src_first = ra_->get_reg_first(in(1));
989 OptoReg::Name dst_second = ra_->get_reg_second(this);
990 OptoReg::Name dst_first = ra_->get_reg_first(this);
991
992 enum RC src_second_rc = rc_class(src_second);
993 enum RC src_first_rc = rc_class(src_first);
994 enum RC dst_second_rc = rc_class(dst_second);
995 enum RC dst_first_rc = rc_class(dst_first);
996
997 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
998 "must move at least 1 register" );
999
1000 if (src_first == dst_first && src_second == dst_second) {
1001 // Self copy, no move
1002 return 0;
1003 }
1004 if (bottom_type()->isa_vect() != NULL) {
1005 uint ireg = ideal_reg();
1006 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1007 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1008 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1009 // mem -> mem
1010 int src_offset = ra_->reg2offset(src_first);
1011 int dst_offset = ra_->reg2offset(dst_first);
1012 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1013 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1014 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1015 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1016 int stack_offset = ra_->reg2offset(dst_first);
1017 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1018 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1019 int stack_offset = ra_->reg2offset(src_first);
1020 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1021 } else {
1022 ShouldNotReachHere();
1023 }
1024 return 0;
1025 }
1026 if (src_first_rc == rc_stack) {
1027 // mem ->
1028 if (dst_first_rc == rc_stack) {
1029 // mem -> mem
1030 assert(src_second != dst_first, "overlap");
1031 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1032 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1033 // 64-bit
1034 int src_offset = ra_->reg2offset(src_first);
1035 int dst_offset = ra_->reg2offset(dst_first);
1036 if (cbuf) {
1037 MacroAssembler _masm(cbuf);
1038 __ pushq(Address(rsp, src_offset));
1039 __ popq (Address(rsp, dst_offset));
1040 #ifndef PRODUCT
1041 } else {
1042 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1043 "popq [rsp + #%d]",
1044 src_offset, dst_offset);
1045 #endif
1046 }
1047 } else {
1048 // 32-bit
1049 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1050 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1051 // No pushl/popl, so:
1052 int src_offset = ra_->reg2offset(src_first);
1053 int dst_offset = ra_->reg2offset(dst_first);
1054 if (cbuf) {
1055 MacroAssembler _masm(cbuf);
1056 __ movq(Address(rsp, -8), rax);
1057 __ movl(rax, Address(rsp, src_offset));
1058 __ movl(Address(rsp, dst_offset), rax);
1059 __ movq(rax, Address(rsp, -8));
1060 #ifndef PRODUCT
1061 } else {
1062 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1063 "movl rax, [rsp + #%d]\n\t"
1064 "movl [rsp + #%d], rax\n\t"
1065 "movq rax, [rsp - #8]",
1066 src_offset, dst_offset);
1067 #endif
1068 }
1069 }
1070 return 0;
1071 } else if (dst_first_rc == rc_int) {
1072 // mem -> gpr
1073 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1074 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1075 // 64-bit
1076 int offset = ra_->reg2offset(src_first);
1077 if (cbuf) {
1078 MacroAssembler _masm(cbuf);
1079 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1080 #ifndef PRODUCT
1081 } else {
1082 st->print("movq %s, [rsp + #%d]\t# spill",
1083 Matcher::regName[dst_first],
1084 offset);
1085 #endif
1086 }
1087 } else {
1088 // 32-bit
1089 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1090 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1091 int offset = ra_->reg2offset(src_first);
1092 if (cbuf) {
1093 MacroAssembler _masm(cbuf);
1094 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1095 #ifndef PRODUCT
1096 } else {
1097 st->print("movl %s, [rsp + #%d]\t# spill",
1098 Matcher::regName[dst_first],
1099 offset);
1100 #endif
1101 }
1102 }
1103 return 0;
1104 } else if (dst_first_rc == rc_float) {
1105 // mem-> xmm
1106 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1107 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1108 // 64-bit
1109 int offset = ra_->reg2offset(src_first);
1110 if (cbuf) {
1111 MacroAssembler _masm(cbuf);
1112 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1113 #ifndef PRODUCT
1114 } else {
1115 st->print("%s %s, [rsp + #%d]\t# spill",
1116 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1117 Matcher::regName[dst_first],
1118 offset);
1119 #endif
1120 }
1121 } else {
1122 // 32-bit
1123 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1124 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1125 int offset = ra_->reg2offset(src_first);
1126 if (cbuf) {
1127 MacroAssembler _masm(cbuf);
1128 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1129 #ifndef PRODUCT
1130 } else {
1131 st->print("movss %s, [rsp + #%d]\t# spill",
1132 Matcher::regName[dst_first],
1133 offset);
1134 #endif
1135 }
1136 }
1137 return 0;
1138 }
1139 } else if (src_first_rc == rc_int) {
1140 // gpr ->
1141 if (dst_first_rc == rc_stack) {
1142 // gpr -> mem
1143 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1144 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1145 // 64-bit
1146 int offset = ra_->reg2offset(dst_first);
1147 if (cbuf) {
1148 MacroAssembler _masm(cbuf);
1149 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1150 #ifndef PRODUCT
1151 } else {
1152 st->print("movq [rsp + #%d], %s\t# spill",
1153 offset,
1154 Matcher::regName[src_first]);
1155 #endif
1156 }
1157 } else {
1158 // 32-bit
1159 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1160 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1161 int offset = ra_->reg2offset(dst_first);
1162 if (cbuf) {
1163 MacroAssembler _masm(cbuf);
1164 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1165 #ifndef PRODUCT
1166 } else {
1167 st->print("movl [rsp + #%d], %s\t# spill",
1168 offset,
1169 Matcher::regName[src_first]);
1170 #endif
1171 }
1172 }
1173 return 0;
1174 } else if (dst_first_rc == rc_int) {
1175 // gpr -> gpr
1176 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1177 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1178 // 64-bit
1179 if (cbuf) {
1180 MacroAssembler _masm(cbuf);
1181 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1182 as_Register(Matcher::_regEncode[src_first]));
1183 #ifndef PRODUCT
1184 } else {
1185 st->print("movq %s, %s\t# spill",
1186 Matcher::regName[dst_first],
1187 Matcher::regName[src_first]);
1188 #endif
1189 }
1190 return 0;
1191 } else {
1192 // 32-bit
1193 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1194 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1195 if (cbuf) {
1196 MacroAssembler _masm(cbuf);
1197 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1198 as_Register(Matcher::_regEncode[src_first]));
1199 #ifndef PRODUCT
1200 } else {
1201 st->print("movl %s, %s\t# spill",
1202 Matcher::regName[dst_first],
1203 Matcher::regName[src_first]);
1204 #endif
1205 }
1206 return 0;
1207 }
1208 } else if (dst_first_rc == rc_float) {
1209 // gpr -> xmm
1210 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1211 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1212 // 64-bit
1213 if (cbuf) {
1214 MacroAssembler _masm(cbuf);
1215 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1216 #ifndef PRODUCT
1217 } else {
1218 st->print("movdq %s, %s\t# spill",
1219 Matcher::regName[dst_first],
1220 Matcher::regName[src_first]);
1221 #endif
1222 }
1223 } else {
1224 // 32-bit
1225 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1226 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1227 if (cbuf) {
1228 MacroAssembler _masm(cbuf);
1229 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1230 #ifndef PRODUCT
1231 } else {
1232 st->print("movdl %s, %s\t# spill",
1233 Matcher::regName[dst_first],
1234 Matcher::regName[src_first]);
1235 #endif
1236 }
1237 }
1238 return 0;
1239 }
1240 } else if (src_first_rc == rc_float) {
1241 // xmm ->
1242 if (dst_first_rc == rc_stack) {
1243 // xmm -> mem
1244 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1245 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1246 // 64-bit
1247 int offset = ra_->reg2offset(dst_first);
1248 if (cbuf) {
1249 MacroAssembler _masm(cbuf);
1250 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1251 #ifndef PRODUCT
1252 } else {
1253 st->print("movsd [rsp + #%d], %s\t# spill",
1254 offset,
1255 Matcher::regName[src_first]);
1256 #endif
1257 }
1258 } else {
1259 // 32-bit
1260 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1261 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1262 int offset = ra_->reg2offset(dst_first);
1263 if (cbuf) {
1264 MacroAssembler _masm(cbuf);
1265 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1266 #ifndef PRODUCT
1267 } else {
1268 st->print("movss [rsp + #%d], %s\t# spill",
1269 offset,
1270 Matcher::regName[src_first]);
1271 #endif
1272 }
1273 }
1274 return 0;
1275 } else if (dst_first_rc == rc_int) {
1276 // xmm -> gpr
1277 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1278 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1279 // 64-bit
1280 if (cbuf) {
1281 MacroAssembler _masm(cbuf);
1282 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1283 #ifndef PRODUCT
1284 } else {
1285 st->print("movdq %s, %s\t# spill",
1286 Matcher::regName[dst_first],
1287 Matcher::regName[src_first]);
1288 #endif
1289 }
1290 } else {
1291 // 32-bit
1292 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1293 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1294 if (cbuf) {
1295 MacroAssembler _masm(cbuf);
1296 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1297 #ifndef PRODUCT
1298 } else {
1299 st->print("movdl %s, %s\t# spill",
1300 Matcher::regName[dst_first],
1301 Matcher::regName[src_first]);
1302 #endif
1303 }
1304 }
1305 return 0;
1306 } else if (dst_first_rc == rc_float) {
1307 // xmm -> xmm
1308 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1309 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1310 // 64-bit
1311 if (cbuf) {
1312 MacroAssembler _masm(cbuf);
1313 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1314 #ifndef PRODUCT
1315 } else {
1316 st->print("%s %s, %s\t# spill",
1317 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1318 Matcher::regName[dst_first],
1319 Matcher::regName[src_first]);
1320 #endif
1321 }
1322 } else {
1323 // 32-bit
1324 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1325 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1326 if (cbuf) {
1327 MacroAssembler _masm(cbuf);
1328 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1329 #ifndef PRODUCT
1330 } else {
1331 st->print("%s %s, %s\t# spill",
1332 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1333 Matcher::regName[dst_first],
1334 Matcher::regName[src_first]);
1335 #endif
1336 }
1337 }
1338 return 0;
1339 }
1340 }
1341
1342 assert(0," foo ");
1343 Unimplemented();
1344 return 0;
1345 }
1346
1347 #ifndef PRODUCT
1348 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1349 implementation(NULL, ra_, false, st);
1350 }
1351 #endif
1352
1353 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1354 implementation(&cbuf, ra_, false, NULL);
1355 }
1356
1357 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1358 return MachNode::size(ra_);
1359 }
1360
1361 //=============================================================================
1362 #ifndef PRODUCT
1363 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1364 {
1365 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1366 int reg = ra_->get_reg_first(this);
1367 st->print("leaq %s, [rsp + #%d]\t# box lock",
1368 Matcher::regName[reg], offset);
1369 }
1370 #endif
1371
1372 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1373 {
1374 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1375 int reg = ra_->get_encode(this);
1376 if (offset >= 0x80) {
1377 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1378 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1379 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1380 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1381 emit_d32(cbuf, offset);
1382 } else {
1383 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1384 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1385 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1386 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1387 emit_d8(cbuf, offset);
1388 }
1389 }
1390
1391 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1392 {
1393 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1394 return (offset < 0x80) ? 5 : 8; // REX
1395 }
1396
1397 //=============================================================================
1398 #ifndef PRODUCT
1399 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1400 {
1401 if (UseCompressedClassPointers) {
1402 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1403 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1404 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1405 } else {
1406 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1407 "# Inline cache check");
1408 }
1409 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1410 st->print_cr("\tnop\t# nops to align entry point");
1411 }
1412 #endif
1413
1414 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1415 {
1416 MacroAssembler masm(&cbuf);
1417 uint insts_size = cbuf.insts_size();
1418 if (UseCompressedClassPointers) {
1419 masm.load_klass(rscratch1, j_rarg0);
1420 masm.cmpptr(rax, rscratch1);
1421 } else {
1422 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1423 }
1424
1425 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1426
1427 /* WARNING these NOPs are critical so that verified entry point is properly
1428 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1429 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1430 if (OptoBreakpoint) {
1431 // Leave space for int3
1432 nops_cnt -= 1;
1433 }
1434 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1435 if (nops_cnt > 0)
1436 masm.nop(nops_cnt);
1437 }
1438
1439 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1440 {
1441 return MachNode::size(ra_); // too many variables; just compute it
1442 // the hard way
1443 }
1444
1445
1446 //=============================================================================
1447
1448 int Matcher::regnum_to_fpu_offset(int regnum)
1449 {
1450 return regnum - 32; // The FP registers are in the second chunk
1451 }
1452
1453 // This is UltraSparc specific, true just means we have fast l2f conversion
1454 const bool Matcher::convL2FSupported(void) {
1455 return true;
1456 }
1457
1458 // Is this branch offset short enough that a short branch can be used?
1459 //
1460 // NOTE: If the platform does not provide any short branch variants, then
1461 // this method should return false for offset 0.
1462 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1463 // The passed offset is relative to address of the branch.
1464 // On 86 a branch displacement is calculated relative to address
1465 // of a next instruction.
1466 offset -= br_size;
1467
1468 // the short version of jmpConUCF2 contains multiple branches,
1469 // making the reach slightly less
1470 if (rule == jmpConUCF2_rule)
1471 return (-126 <= offset && offset <= 125);
1472 return (-128 <= offset && offset <= 127);
1473 }
1474
1475 const bool Matcher::isSimpleConstant64(jlong value) {
1476 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1477 //return value == (int) value; // Cf. storeImmL and immL32.
1478
1479 // Probably always true, even if a temp register is required.
1480 return true;
1481 }
1482
1483 // The ecx parameter to rep stosq for the ClearArray node is in words.
1484 const bool Matcher::init_array_count_is_in_bytes = false;
1485
1486 // Threshold size for cleararray.
1487 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1488
1489 // No additional cost for CMOVL.
1490 const int Matcher::long_cmove_cost() { return 0; }
1491
1492 // No CMOVF/CMOVD with SSE2
1493 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1494
1495 // Does the CPU require late expand (see block.cpp for description of late expand)?
1496 const bool Matcher::require_postalloc_expand = false;
1497
1498 // Should the Matcher clone shifts on addressing modes, expecting them
1499 // to be subsumed into complex addressing expressions or compute them
1500 // into registers? True for Intel but false for most RISCs
1501 const bool Matcher::clone_shift_expressions = true;
1502
1503 // Do we need to mask the count passed to shift instructions or does
1504 // the cpu only look at the lower 5/6 bits anyway?
1505 const bool Matcher::need_masked_shift_count = false;
1506
1507 bool Matcher::narrow_oop_use_complex_address() {
1508 assert(UseCompressedOops, "only for compressed oops code");
1509 return (LogMinObjAlignmentInBytes <= 3);
1510 }
1511
1512 bool Matcher::narrow_klass_use_complex_address() {
1513 assert(UseCompressedClassPointers, "only for compressed klass code");
1514 return (LogKlassAlignmentInBytes <= 3);
1515 }
1516
1517 // Is it better to copy float constants, or load them directly from
1518 // memory? Intel can load a float constant from a direct address,
1519 // requiring no extra registers. Most RISCs will have to materialize
1520 // an address into a register first, so they would do better to copy
1521 // the constant from stack.
1522 const bool Matcher::rematerialize_float_constants = true; // XXX
1523
1524 // If CPU can load and store mis-aligned doubles directly then no
1525 // fixup is needed. Else we split the double into 2 integer pieces
1526 // and move it piece-by-piece. Only happens when passing doubles into
1527 // C code as the Java calling convention forces doubles to be aligned.
1528 const bool Matcher::misaligned_doubles_ok = true;
1529
1530 // No-op on amd64
1531 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1532
1533 // Advertise here if the CPU requires explicit rounding operations to
1534 // implement the UseStrictFP mode.
1535 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1536
1537 // Are floats conerted to double when stored to stack during deoptimization?
1538 // On x64 it is stored without convertion so we can use normal access.
1539 bool Matcher::float_in_double() { return false; }
1540
1541 // Do ints take an entire long register or just half?
1542 const bool Matcher::int_in_long = true;
1543
1544 // Return whether or not this register is ever used as an argument.
1545 // This function is used on startup to build the trampoline stubs in
1546 // generateOptoStub. Registers not mentioned will be killed by the VM
1547 // call in the trampoline, and arguments in those registers not be
1548 // available to the callee.
1549 bool Matcher::can_be_java_arg(int reg)
1550 {
1551 return
1552 reg == RDI_num || reg == RDI_H_num ||
1553 reg == RSI_num || reg == RSI_H_num ||
1554 reg == RDX_num || reg == RDX_H_num ||
1555 reg == RCX_num || reg == RCX_H_num ||
1556 reg == R8_num || reg == R8_H_num ||
1557 reg == R9_num || reg == R9_H_num ||
1558 reg == R12_num || reg == R12_H_num ||
1559 reg == XMM0_num || reg == XMM0b_num ||
1560 reg == XMM1_num || reg == XMM1b_num ||
1561 reg == XMM2_num || reg == XMM2b_num ||
1562 reg == XMM3_num || reg == XMM3b_num ||
1563 reg == XMM4_num || reg == XMM4b_num ||
1564 reg == XMM5_num || reg == XMM5b_num ||
1565 reg == XMM6_num || reg == XMM6b_num ||
1566 reg == XMM7_num || reg == XMM7b_num;
1567 }
1568
1569 bool Matcher::is_spillable_arg(int reg)
1570 {
1571 return can_be_java_arg(reg);
1572 }
1573
1574 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1575 // In 64 bit mode a code which use multiply when
1576 // devisor is constant is faster than hardware
1577 // DIV instruction (it uses MulHiL).
1578 return false;
1579 }
1580
1581 // Register for DIVI projection of divmodI
1582 RegMask Matcher::divI_proj_mask() {
1583 return INT_RAX_REG_mask();
1584 }
1585
1586 // Register for MODI projection of divmodI
1587 RegMask Matcher::modI_proj_mask() {
1588 return INT_RDX_REG_mask();
1589 }
1590
1591 // Register for DIVL projection of divmodL
1592 RegMask Matcher::divL_proj_mask() {
1593 return LONG_RAX_REG_mask();
1594 }
1595
1596 // Register for MODL projection of divmodL
1597 RegMask Matcher::modL_proj_mask() {
1598 return LONG_RDX_REG_mask();
1599 }
1600
1601 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1602 return PTR_RBP_REG_mask();
1603 }
1604
1605 %}
1606
1607 //----------ENCODING BLOCK-----------------------------------------------------
1608 // This block specifies the encoding classes used by the compiler to
1609 // output byte streams. Encoding classes are parameterized macros
1610 // used by Machine Instruction Nodes in order to generate the bit
1611 // encoding of the instruction. Operands specify their base encoding
1612 // interface with the interface keyword. There are currently
1613 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1614 // COND_INTER. REG_INTER causes an operand to generate a function
1615 // which returns its register number when queried. CONST_INTER causes
1616 // an operand to generate a function which returns the value of the
1617 // constant when queried. MEMORY_INTER causes an operand to generate
1618 // four functions which return the Base Register, the Index Register,
1619 // the Scale Value, and the Offset Value of the operand when queried.
1620 // COND_INTER causes an operand to generate six functions which return
1621 // the encoding code (ie - encoding bits for the instruction)
1622 // associated with each basic boolean condition for a conditional
1623 // instruction.
1624 //
1625 // Instructions specify two basic values for encoding. Again, a
1626 // function is available to check if the constant displacement is an
1627 // oop. They use the ins_encode keyword to specify their encoding
1628 // classes (which must be a sequence of enc_class names, and their
1629 // parameters, specified in the encoding block), and they use the
1630 // opcode keyword to specify, in order, their primary, secondary, and
1631 // tertiary opcode. Only the opcode sections which a particular
1632 // instruction needs for encoding need to be specified.
1633 encode %{
1634 // Build emit functions for each basic byte or larger field in the
1635 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1636 // from C++ code in the enc_class source block. Emit functions will
1637 // live in the main source block for now. In future, we can
1638 // generalize this by adding a syntax that specifies the sizes of
1639 // fields in an order, so that the adlc can build the emit functions
1640 // automagically
1641
1642 // Emit primary opcode
1643 enc_class OpcP
1644 %{
1645 emit_opcode(cbuf, $primary);
1646 %}
1647
1648 // Emit secondary opcode
1649 enc_class OpcS
1650 %{
1651 emit_opcode(cbuf, $secondary);
1652 %}
1653
1654 // Emit tertiary opcode
1655 enc_class OpcT
1656 %{
1657 emit_opcode(cbuf, $tertiary);
1658 %}
1659
1660 // Emit opcode directly
1661 enc_class Opcode(immI d8)
1662 %{
1663 emit_opcode(cbuf, $d8$$constant);
1664 %}
1665
1666 // Emit size prefix
1667 enc_class SizePrefix
1668 %{
1669 emit_opcode(cbuf, 0x66);
1670 %}
1671
1672 enc_class reg(rRegI reg)
1673 %{
1674 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1675 %}
1676
1677 enc_class reg_reg(rRegI dst, rRegI src)
1678 %{
1679 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1680 %}
1681
1682 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1683 %{
1684 emit_opcode(cbuf, $opcode$$constant);
1685 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1686 %}
1687
1688 enc_class cdql_enc(no_rax_rdx_RegI div)
1689 %{
1690 // Full implementation of Java idiv and irem; checks for
1691 // special case as described in JVM spec., p.243 & p.271.
1692 //
1693 // normal case special case
1694 //
1695 // input : rax: dividend min_int
1696 // reg: divisor -1
1697 //
1698 // output: rax: quotient (= rax idiv reg) min_int
1699 // rdx: remainder (= rax irem reg) 0
1700 //
1701 // Code sequnce:
1702 //
1703 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1704 // 5: 75 07/08 jne e <normal>
1705 // 7: 33 d2 xor %edx,%edx
1706 // [div >= 8 -> offset + 1]
1707 // [REX_B]
1708 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1709 // c: 74 03/04 je 11 <done>
1710 // 000000000000000e <normal>:
1711 // e: 99 cltd
1712 // [div >= 8 -> offset + 1]
1713 // [REX_B]
1714 // f: f7 f9 idiv $div
1715 // 0000000000000011 <done>:
1716
1717 // cmp $0x80000000,%eax
1718 emit_opcode(cbuf, 0x3d);
1719 emit_d8(cbuf, 0x00);
1720 emit_d8(cbuf, 0x00);
1721 emit_d8(cbuf, 0x00);
1722 emit_d8(cbuf, 0x80);
1723
1724 // jne e <normal>
1725 emit_opcode(cbuf, 0x75);
1726 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1727
1728 // xor %edx,%edx
1729 emit_opcode(cbuf, 0x33);
1730 emit_d8(cbuf, 0xD2);
1731
1732 // cmp $0xffffffffffffffff,%ecx
1733 if ($div$$reg >= 8) {
1734 emit_opcode(cbuf, Assembler::REX_B);
1735 }
1736 emit_opcode(cbuf, 0x83);
1737 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1738 emit_d8(cbuf, 0xFF);
1739
1740 // je 11 <done>
1741 emit_opcode(cbuf, 0x74);
1742 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1743
1744 // <normal>
1745 // cltd
1746 emit_opcode(cbuf, 0x99);
1747
1748 // idivl (note: must be emitted by the user of this rule)
1749 // <done>
1750 %}
1751
1752 enc_class cdqq_enc(no_rax_rdx_RegL div)
1753 %{
1754 // Full implementation of Java ldiv and lrem; checks for
1755 // special case as described in JVM spec., p.243 & p.271.
1756 //
1757 // normal case special case
1758 //
1759 // input : rax: dividend min_long
1760 // reg: divisor -1
1761 //
1762 // output: rax: quotient (= rax idiv reg) min_long
1763 // rdx: remainder (= rax irem reg) 0
1764 //
1765 // Code sequnce:
1766 //
1767 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1768 // 7: 00 00 80
1769 // a: 48 39 d0 cmp %rdx,%rax
1770 // d: 75 08 jne 17 <normal>
1771 // f: 33 d2 xor %edx,%edx
1772 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1773 // 15: 74 05 je 1c <done>
1774 // 0000000000000017 <normal>:
1775 // 17: 48 99 cqto
1776 // 19: 48 f7 f9 idiv $div
1777 // 000000000000001c <done>:
1778
1779 // mov $0x8000000000000000,%rdx
1780 emit_opcode(cbuf, Assembler::REX_W);
1781 emit_opcode(cbuf, 0xBA);
1782 emit_d8(cbuf, 0x00);
1783 emit_d8(cbuf, 0x00);
1784 emit_d8(cbuf, 0x00);
1785 emit_d8(cbuf, 0x00);
1786 emit_d8(cbuf, 0x00);
1787 emit_d8(cbuf, 0x00);
1788 emit_d8(cbuf, 0x00);
1789 emit_d8(cbuf, 0x80);
1790
1791 // cmp %rdx,%rax
1792 emit_opcode(cbuf, Assembler::REX_W);
1793 emit_opcode(cbuf, 0x39);
1794 emit_d8(cbuf, 0xD0);
1795
1796 // jne 17 <normal>
1797 emit_opcode(cbuf, 0x75);
1798 emit_d8(cbuf, 0x08);
1799
1800 // xor %edx,%edx
1801 emit_opcode(cbuf, 0x33);
1802 emit_d8(cbuf, 0xD2);
1803
1804 // cmp $0xffffffffffffffff,$div
1805 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1806 emit_opcode(cbuf, 0x83);
1807 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1808 emit_d8(cbuf, 0xFF);
1809
1810 // je 1e <done>
1811 emit_opcode(cbuf, 0x74);
1812 emit_d8(cbuf, 0x05);
1813
1814 // <normal>
1815 // cqto
1816 emit_opcode(cbuf, Assembler::REX_W);
1817 emit_opcode(cbuf, 0x99);
1818
1819 // idivq (note: must be emitted by the user of this rule)
1820 // <done>
1821 %}
1822
1823 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1824 enc_class OpcSE(immI imm)
1825 %{
1826 // Emit primary opcode and set sign-extend bit
1827 // Check for 8-bit immediate, and set sign extend bit in opcode
1828 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1829 emit_opcode(cbuf, $primary | 0x02);
1830 } else {
1831 // 32-bit immediate
1832 emit_opcode(cbuf, $primary);
1833 }
1834 %}
1835
1836 enc_class OpcSErm(rRegI dst, immI imm)
1837 %{
1838 // OpcSEr/m
1839 int dstenc = $dst$$reg;
1840 if (dstenc >= 8) {
1841 emit_opcode(cbuf, Assembler::REX_B);
1842 dstenc -= 8;
1843 }
1844 // Emit primary opcode and set sign-extend bit
1845 // Check for 8-bit immediate, and set sign extend bit in opcode
1846 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1847 emit_opcode(cbuf, $primary | 0x02);
1848 } else {
1849 // 32-bit immediate
1850 emit_opcode(cbuf, $primary);
1851 }
1852 // Emit r/m byte with secondary opcode, after primary opcode.
1853 emit_rm(cbuf, 0x3, $secondary, dstenc);
1854 %}
1855
1856 enc_class OpcSErm_wide(rRegL dst, immI imm)
1857 %{
1858 // OpcSEr/m
1859 int dstenc = $dst$$reg;
1860 if (dstenc < 8) {
1861 emit_opcode(cbuf, Assembler::REX_W);
1862 } else {
1863 emit_opcode(cbuf, Assembler::REX_WB);
1864 dstenc -= 8;
1865 }
1866 // Emit primary opcode and set sign-extend bit
1867 // Check for 8-bit immediate, and set sign extend bit in opcode
1868 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1869 emit_opcode(cbuf, $primary | 0x02);
1870 } else {
1871 // 32-bit immediate
1872 emit_opcode(cbuf, $primary);
1873 }
1874 // Emit r/m byte with secondary opcode, after primary opcode.
1875 emit_rm(cbuf, 0x3, $secondary, dstenc);
1876 %}
1877
1878 enc_class Con8or32(immI imm)
1879 %{
1880 // Check for 8-bit immediate, and set sign extend bit in opcode
1881 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1882 $$$emit8$imm$$constant;
1883 } else {
1884 // 32-bit immediate
1885 $$$emit32$imm$$constant;
1886 }
1887 %}
1888
1889 enc_class opc2_reg(rRegI dst)
1890 %{
1891 // BSWAP
1892 emit_cc(cbuf, $secondary, $dst$$reg);
1893 %}
1894
1895 enc_class opc3_reg(rRegI dst)
1896 %{
1897 // BSWAP
1898 emit_cc(cbuf, $tertiary, $dst$$reg);
1899 %}
1900
1901 enc_class reg_opc(rRegI div)
1902 %{
1903 // INC, DEC, IDIV, IMOD, JMP indirect, ...
1904 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
1905 %}
1906
1907 enc_class enc_cmov(cmpOp cop)
1908 %{
1909 // CMOV
1910 $$$emit8$primary;
1911 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1912 %}
1913
1914 enc_class enc_PartialSubtypeCheck()
1915 %{
1916 Register Rrdi = as_Register(RDI_enc); // result register
1917 Register Rrax = as_Register(RAX_enc); // super class
1918 Register Rrcx = as_Register(RCX_enc); // killed
1919 Register Rrsi = as_Register(RSI_enc); // sub class
1920 Label miss;
1921 const bool set_cond_codes = true;
1922
1923 MacroAssembler _masm(&cbuf);
1924 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
1925 NULL, &miss,
1926 /*set_cond_codes:*/ true);
1927 if ($primary) {
1928 __ xorptr(Rrdi, Rrdi);
1929 }
1930 __ bind(miss);
1931 %}
1932
1933 enc_class clear_avx %{
1934 debug_only(int off0 = cbuf.insts_size());
1935 if (ra_->C->max_vector_size() > 16) {
1936 // Clear upper bits of YMM registers when current compiled code uses
1937 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1938 MacroAssembler _masm(&cbuf);
1939 __ vzeroupper();
1940 }
1941 debug_only(int off1 = cbuf.insts_size());
1942 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
1943 %}
1944
1945 enc_class Java_To_Runtime(method meth) %{
1946 // No relocation needed
1947 MacroAssembler _masm(&cbuf);
1948 __ mov64(r10, (int64_t) $meth$$method);
1949 __ call(r10);
1950 %}
1951
1952 enc_class Java_To_Interpreter(method meth)
1953 %{
1954 // CALL Java_To_Interpreter
1955 // This is the instruction starting address for relocation info.
1956 cbuf.set_insts_mark();
1957 $$$emit8$primary;
1958 // CALL directly to the runtime
1959 emit_d32_reloc(cbuf,
1960 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
1961 runtime_call_Relocation::spec(),
1962 RELOC_DISP32);
1963 %}
1964
1965 enc_class Java_Static_Call(method meth)
1966 %{
1967 // JAVA STATIC CALL
1968 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
1969 // determine who we intended to call.
1970 cbuf.set_insts_mark();
1971 $$$emit8$primary;
1972
1973 if (!_method) {
1974 emit_d32_reloc(cbuf,
1975 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
1976 runtime_call_Relocation::spec(),
1977 RELOC_DISP32);
1978 } else if (_optimized_virtual) {
1979 emit_d32_reloc(cbuf,
1980 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
1981 opt_virtual_call_Relocation::spec(),
1982 RELOC_DISP32);
1983 } else {
1984 emit_d32_reloc(cbuf,
1985 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
1986 static_call_Relocation::spec(),
1987 RELOC_DISP32);
1988 }
1989 if (_method) {
1990 // Emit stub for static call.
1991 CompiledStaticCall::emit_to_interp_stub(cbuf);
1992 }
1993 %}
1994
1995 enc_class Java_Dynamic_Call(method meth) %{
1996 MacroAssembler _masm(&cbuf);
1997 __ ic_call((address)$meth$$method);
1998 %}
1999
2000 enc_class Java_Compiled_Call(method meth)
2001 %{
2002 // JAVA COMPILED CALL
2003 int disp = in_bytes(Method:: from_compiled_offset());
2004
2005 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2006 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2007
2008 // callq *disp(%rax)
2009 cbuf.set_insts_mark();
2010 $$$emit8$primary;
2011 if (disp < 0x80) {
2012 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2013 emit_d8(cbuf, disp); // Displacement
2014 } else {
2015 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2016 emit_d32(cbuf, disp); // Displacement
2017 }
2018 %}
2019
2020 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2021 %{
2022 // SAL, SAR, SHR
2023 int dstenc = $dst$$reg;
2024 if (dstenc >= 8) {
2025 emit_opcode(cbuf, Assembler::REX_B);
2026 dstenc -= 8;
2027 }
2028 $$$emit8$primary;
2029 emit_rm(cbuf, 0x3, $secondary, dstenc);
2030 $$$emit8$shift$$constant;
2031 %}
2032
2033 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2034 %{
2035 // SAL, SAR, SHR
2036 int dstenc = $dst$$reg;
2037 if (dstenc < 8) {
2038 emit_opcode(cbuf, Assembler::REX_W);
2039 } else {
2040 emit_opcode(cbuf, Assembler::REX_WB);
2041 dstenc -= 8;
2042 }
2043 $$$emit8$primary;
2044 emit_rm(cbuf, 0x3, $secondary, dstenc);
2045 $$$emit8$shift$$constant;
2046 %}
2047
2048 enc_class load_immI(rRegI dst, immI src)
2049 %{
2050 int dstenc = $dst$$reg;
2051 if (dstenc >= 8) {
2052 emit_opcode(cbuf, Assembler::REX_B);
2053 dstenc -= 8;
2054 }
2055 emit_opcode(cbuf, 0xB8 | dstenc);
2056 $$$emit32$src$$constant;
2057 %}
2058
2059 enc_class load_immL(rRegL dst, immL src)
2060 %{
2061 int dstenc = $dst$$reg;
2062 if (dstenc < 8) {
2063 emit_opcode(cbuf, Assembler::REX_W);
2064 } else {
2065 emit_opcode(cbuf, Assembler::REX_WB);
2066 dstenc -= 8;
2067 }
2068 emit_opcode(cbuf, 0xB8 | dstenc);
2069 emit_d64(cbuf, $src$$constant);
2070 %}
2071
2072 enc_class load_immUL32(rRegL dst, immUL32 src)
2073 %{
2074 // same as load_immI, but this time we care about zeroes in the high word
2075 int dstenc = $dst$$reg;
2076 if (dstenc >= 8) {
2077 emit_opcode(cbuf, Assembler::REX_B);
2078 dstenc -= 8;
2079 }
2080 emit_opcode(cbuf, 0xB8 | dstenc);
2081 $$$emit32$src$$constant;
2082 %}
2083
2084 enc_class load_immL32(rRegL dst, immL32 src)
2085 %{
2086 int dstenc = $dst$$reg;
2087 if (dstenc < 8) {
2088 emit_opcode(cbuf, Assembler::REX_W);
2089 } else {
2090 emit_opcode(cbuf, Assembler::REX_WB);
2091 dstenc -= 8;
2092 }
2093 emit_opcode(cbuf, 0xC7);
2094 emit_rm(cbuf, 0x03, 0x00, dstenc);
2095 $$$emit32$src$$constant;
2096 %}
2097
2098 enc_class load_immP31(rRegP dst, immP32 src)
2099 %{
2100 // same as load_immI, but this time we care about zeroes in the high word
2101 int dstenc = $dst$$reg;
2102 if (dstenc >= 8) {
2103 emit_opcode(cbuf, Assembler::REX_B);
2104 dstenc -= 8;
2105 }
2106 emit_opcode(cbuf, 0xB8 | dstenc);
2107 $$$emit32$src$$constant;
2108 %}
2109
2110 enc_class load_immP(rRegP dst, immP src)
2111 %{
2112 int dstenc = $dst$$reg;
2113 if (dstenc < 8) {
2114 emit_opcode(cbuf, Assembler::REX_W);
2115 } else {
2116 emit_opcode(cbuf, Assembler::REX_WB);
2117 dstenc -= 8;
2118 }
2119 emit_opcode(cbuf, 0xB8 | dstenc);
2120 // This next line should be generated from ADLC
2121 if ($src->constant_reloc() != relocInfo::none) {
2122 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2123 } else {
2124 emit_d64(cbuf, $src$$constant);
2125 }
2126 %}
2127
2128 enc_class Con32(immI src)
2129 %{
2130 // Output immediate
2131 $$$emit32$src$$constant;
2132 %}
2133
2134 enc_class Con32F_as_bits(immF src)
2135 %{
2136 // Output Float immediate bits
2137 jfloat jf = $src$$constant;
2138 jint jf_as_bits = jint_cast(jf);
2139 emit_d32(cbuf, jf_as_bits);
2140 %}
2141
2142 enc_class Con16(immI src)
2143 %{
2144 // Output immediate
2145 $$$emit16$src$$constant;
2146 %}
2147
2148 // How is this different from Con32??? XXX
2149 enc_class Con_d32(immI src)
2150 %{
2151 emit_d32(cbuf,$src$$constant);
2152 %}
2153
2154 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2155 // Output immediate memory reference
2156 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2157 emit_d32(cbuf, 0x00);
2158 %}
2159
2160 enc_class lock_prefix()
2161 %{
2162 if (os::is_MP()) {
2163 emit_opcode(cbuf, 0xF0); // lock
2164 }
2165 %}
2166
2167 enc_class REX_mem(memory mem)
2168 %{
2169 if ($mem$$base >= 8) {
2170 if ($mem$$index < 8) {
2171 emit_opcode(cbuf, Assembler::REX_B);
2172 } else {
2173 emit_opcode(cbuf, Assembler::REX_XB);
2174 }
2175 } else {
2176 if ($mem$$index >= 8) {
2177 emit_opcode(cbuf, Assembler::REX_X);
2178 }
2179 }
2180 %}
2181
2182 enc_class REX_mem_wide(memory mem)
2183 %{
2184 if ($mem$$base >= 8) {
2185 if ($mem$$index < 8) {
2186 emit_opcode(cbuf, Assembler::REX_WB);
2187 } else {
2188 emit_opcode(cbuf, Assembler::REX_WXB);
2189 }
2190 } else {
2191 if ($mem$$index < 8) {
2192 emit_opcode(cbuf, Assembler::REX_W);
2193 } else {
2194 emit_opcode(cbuf, Assembler::REX_WX);
2195 }
2196 }
2197 %}
2198
2199 // for byte regs
2200 enc_class REX_breg(rRegI reg)
2201 %{
2202 if ($reg$$reg >= 4) {
2203 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2204 }
2205 %}
2206
2207 // for byte regs
2208 enc_class REX_reg_breg(rRegI dst, rRegI src)
2209 %{
2210 if ($dst$$reg < 8) {
2211 if ($src$$reg >= 4) {
2212 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2213 }
2214 } else {
2215 if ($src$$reg < 8) {
2216 emit_opcode(cbuf, Assembler::REX_R);
2217 } else {
2218 emit_opcode(cbuf, Assembler::REX_RB);
2219 }
2220 }
2221 %}
2222
2223 // for byte regs
2224 enc_class REX_breg_mem(rRegI reg, memory mem)
2225 %{
2226 if ($reg$$reg < 8) {
2227 if ($mem$$base < 8) {
2228 if ($mem$$index >= 8) {
2229 emit_opcode(cbuf, Assembler::REX_X);
2230 } else if ($reg$$reg >= 4) {
2231 emit_opcode(cbuf, Assembler::REX);
2232 }
2233 } else {
2234 if ($mem$$index < 8) {
2235 emit_opcode(cbuf, Assembler::REX_B);
2236 } else {
2237 emit_opcode(cbuf, Assembler::REX_XB);
2238 }
2239 }
2240 } else {
2241 if ($mem$$base < 8) {
2242 if ($mem$$index < 8) {
2243 emit_opcode(cbuf, Assembler::REX_R);
2244 } else {
2245 emit_opcode(cbuf, Assembler::REX_RX);
2246 }
2247 } else {
2248 if ($mem$$index < 8) {
2249 emit_opcode(cbuf, Assembler::REX_RB);
2250 } else {
2251 emit_opcode(cbuf, Assembler::REX_RXB);
2252 }
2253 }
2254 }
2255 %}
2256
2257 enc_class REX_reg(rRegI reg)
2258 %{
2259 if ($reg$$reg >= 8) {
2260 emit_opcode(cbuf, Assembler::REX_B);
2261 }
2262 %}
2263
2264 enc_class REX_reg_wide(rRegI reg)
2265 %{
2266 if ($reg$$reg < 8) {
2267 emit_opcode(cbuf, Assembler::REX_W);
2268 } else {
2269 emit_opcode(cbuf, Assembler::REX_WB);
2270 }
2271 %}
2272
2273 enc_class REX_reg_reg(rRegI dst, rRegI src)
2274 %{
2275 if ($dst$$reg < 8) {
2276 if ($src$$reg >= 8) {
2277 emit_opcode(cbuf, Assembler::REX_B);
2278 }
2279 } else {
2280 if ($src$$reg < 8) {
2281 emit_opcode(cbuf, Assembler::REX_R);
2282 } else {
2283 emit_opcode(cbuf, Assembler::REX_RB);
2284 }
2285 }
2286 %}
2287
2288 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2289 %{
2290 if ($dst$$reg < 8) {
2291 if ($src$$reg < 8) {
2292 emit_opcode(cbuf, Assembler::REX_W);
2293 } else {
2294 emit_opcode(cbuf, Assembler::REX_WB);
2295 }
2296 } else {
2297 if ($src$$reg < 8) {
2298 emit_opcode(cbuf, Assembler::REX_WR);
2299 } else {
2300 emit_opcode(cbuf, Assembler::REX_WRB);
2301 }
2302 }
2303 %}
2304
2305 enc_class REX_reg_mem(rRegI reg, memory mem)
2306 %{
2307 if ($reg$$reg < 8) {
2308 if ($mem$$base < 8) {
2309 if ($mem$$index >= 8) {
2310 emit_opcode(cbuf, Assembler::REX_X);
2311 }
2312 } else {
2313 if ($mem$$index < 8) {
2314 emit_opcode(cbuf, Assembler::REX_B);
2315 } else {
2316 emit_opcode(cbuf, Assembler::REX_XB);
2317 }
2318 }
2319 } else {
2320 if ($mem$$base < 8) {
2321 if ($mem$$index < 8) {
2322 emit_opcode(cbuf, Assembler::REX_R);
2323 } else {
2324 emit_opcode(cbuf, Assembler::REX_RX);
2325 }
2326 } else {
2327 if ($mem$$index < 8) {
2328 emit_opcode(cbuf, Assembler::REX_RB);
2329 } else {
2330 emit_opcode(cbuf, Assembler::REX_RXB);
2331 }
2332 }
2333 }
2334 %}
2335
2336 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2337 %{
2338 if ($reg$$reg < 8) {
2339 if ($mem$$base < 8) {
2340 if ($mem$$index < 8) {
2341 emit_opcode(cbuf, Assembler::REX_W);
2342 } else {
2343 emit_opcode(cbuf, Assembler::REX_WX);
2344 }
2345 } else {
2346 if ($mem$$index < 8) {
2347 emit_opcode(cbuf, Assembler::REX_WB);
2348 } else {
2349 emit_opcode(cbuf, Assembler::REX_WXB);
2350 }
2351 }
2352 } else {
2353 if ($mem$$base < 8) {
2354 if ($mem$$index < 8) {
2355 emit_opcode(cbuf, Assembler::REX_WR);
2356 } else {
2357 emit_opcode(cbuf, Assembler::REX_WRX);
2358 }
2359 } else {
2360 if ($mem$$index < 8) {
2361 emit_opcode(cbuf, Assembler::REX_WRB);
2362 } else {
2363 emit_opcode(cbuf, Assembler::REX_WRXB);
2364 }
2365 }
2366 }
2367 %}
2368
2369 enc_class reg_mem(rRegI ereg, memory mem)
2370 %{
2371 // High registers handle in encode_RegMem
2372 int reg = $ereg$$reg;
2373 int base = $mem$$base;
2374 int index = $mem$$index;
2375 int scale = $mem$$scale;
2376 int disp = $mem$$disp;
2377 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2378
2379 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2380 %}
2381
2382 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2383 %{
2384 int rm_byte_opcode = $rm_opcode$$constant;
2385
2386 // High registers handle in encode_RegMem
2387 int base = $mem$$base;
2388 int index = $mem$$index;
2389 int scale = $mem$$scale;
2390 int displace = $mem$$disp;
2391
2392 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2393 // working with static
2394 // globals
2395 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2396 disp_reloc);
2397 %}
2398
2399 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2400 %{
2401 int reg_encoding = $dst$$reg;
2402 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2403 int index = 0x04; // 0x04 indicates no index
2404 int scale = 0x00; // 0x00 indicates no scale
2405 int displace = $src1$$constant; // 0x00 indicates no displacement
2406 relocInfo::relocType disp_reloc = relocInfo::none;
2407 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2408 disp_reloc);
2409 %}
2410
2411 enc_class neg_reg(rRegI dst)
2412 %{
2413 int dstenc = $dst$$reg;
2414 if (dstenc >= 8) {
2415 emit_opcode(cbuf, Assembler::REX_B);
2416 dstenc -= 8;
2417 }
2418 // NEG $dst
2419 emit_opcode(cbuf, 0xF7);
2420 emit_rm(cbuf, 0x3, 0x03, dstenc);
2421 %}
2422
2423 enc_class neg_reg_wide(rRegI dst)
2424 %{
2425 int dstenc = $dst$$reg;
2426 if (dstenc < 8) {
2427 emit_opcode(cbuf, Assembler::REX_W);
2428 } else {
2429 emit_opcode(cbuf, Assembler::REX_WB);
2430 dstenc -= 8;
2431 }
2432 // NEG $dst
2433 emit_opcode(cbuf, 0xF7);
2434 emit_rm(cbuf, 0x3, 0x03, dstenc);
2435 %}
2436
2437 enc_class setLT_reg(rRegI dst)
2438 %{
2439 int dstenc = $dst$$reg;
2440 if (dstenc >= 8) {
2441 emit_opcode(cbuf, Assembler::REX_B);
2442 dstenc -= 8;
2443 } else if (dstenc >= 4) {
2444 emit_opcode(cbuf, Assembler::REX);
2445 }
2446 // SETLT $dst
2447 emit_opcode(cbuf, 0x0F);
2448 emit_opcode(cbuf, 0x9C);
2449 emit_rm(cbuf, 0x3, 0x0, dstenc);
2450 %}
2451
2452 enc_class setNZ_reg(rRegI dst)
2453 %{
2454 int dstenc = $dst$$reg;
2455 if (dstenc >= 8) {
2456 emit_opcode(cbuf, Assembler::REX_B);
2457 dstenc -= 8;
2458 } else if (dstenc >= 4) {
2459 emit_opcode(cbuf, Assembler::REX);
2460 }
2461 // SETNZ $dst
2462 emit_opcode(cbuf, 0x0F);
2463 emit_opcode(cbuf, 0x95);
2464 emit_rm(cbuf, 0x3, 0x0, dstenc);
2465 %}
2466
2467
2468 // Compare the lonogs and set -1, 0, or 1 into dst
2469 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2470 %{
2471 int src1enc = $src1$$reg;
2472 int src2enc = $src2$$reg;
2473 int dstenc = $dst$$reg;
2474
2475 // cmpq $src1, $src2
2476 if (src1enc < 8) {
2477 if (src2enc < 8) {
2478 emit_opcode(cbuf, Assembler::REX_W);
2479 } else {
2480 emit_opcode(cbuf, Assembler::REX_WB);
2481 }
2482 } else {
2483 if (src2enc < 8) {
2484 emit_opcode(cbuf, Assembler::REX_WR);
2485 } else {
2486 emit_opcode(cbuf, Assembler::REX_WRB);
2487 }
2488 }
2489 emit_opcode(cbuf, 0x3B);
2490 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2491
2492 // movl $dst, -1
2493 if (dstenc >= 8) {
2494 emit_opcode(cbuf, Assembler::REX_B);
2495 }
2496 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2497 emit_d32(cbuf, -1);
2498
2499 // jl,s done
2500 emit_opcode(cbuf, 0x7C);
2501 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2502
2503 // setne $dst
2504 if (dstenc >= 4) {
2505 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2506 }
2507 emit_opcode(cbuf, 0x0F);
2508 emit_opcode(cbuf, 0x95);
2509 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2510
2511 // movzbl $dst, $dst
2512 if (dstenc >= 4) {
2513 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2514 }
2515 emit_opcode(cbuf, 0x0F);
2516 emit_opcode(cbuf, 0xB6);
2517 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2518 %}
2519
2520 enc_class Push_ResultXD(regD dst) %{
2521 MacroAssembler _masm(&cbuf);
2522 __ fstp_d(Address(rsp, 0));
2523 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2524 __ addptr(rsp, 8);
2525 %}
2526
2527 enc_class Push_SrcXD(regD src) %{
2528 MacroAssembler _masm(&cbuf);
2529 __ subptr(rsp, 8);
2530 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2531 __ fld_d(Address(rsp, 0));
2532 %}
2533
2534
2535 enc_class enc_rethrow()
2536 %{
2537 cbuf.set_insts_mark();
2538 emit_opcode(cbuf, 0xE9); // jmp entry
2539 emit_d32_reloc(cbuf,
2540 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2541 runtime_call_Relocation::spec(),
2542 RELOC_DISP32);
2543 %}
2544
2545 %}
2546
2547
2548
2549 //----------FRAME--------------------------------------------------------------
2550 // Definition of frame structure and management information.
2551 //
2552 // S T A C K L A Y O U T Allocators stack-slot number
2553 // | (to get allocators register number
2554 // G Owned by | | v add OptoReg::stack0())
2555 // r CALLER | |
2556 // o | +--------+ pad to even-align allocators stack-slot
2557 // w V | pad0 | numbers; owned by CALLER
2558 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2559 // h ^ | in | 5
2560 // | | args | 4 Holes in incoming args owned by SELF
2561 // | | | | 3
2562 // | | +--------+
2563 // V | | old out| Empty on Intel, window on Sparc
2564 // | old |preserve| Must be even aligned.
2565 // | SP-+--------+----> Matcher::_old_SP, even aligned
2566 // | | in | 3 area for Intel ret address
2567 // Owned by |preserve| Empty on Sparc.
2568 // SELF +--------+
2569 // | | pad2 | 2 pad to align old SP
2570 // | +--------+ 1
2571 // | | locks | 0
2572 // | +--------+----> OptoReg::stack0(), even aligned
2573 // | | pad1 | 11 pad to align new SP
2574 // | +--------+
2575 // | | | 10
2576 // | | spills | 9 spills
2577 // V | | 8 (pad0 slot for callee)
2578 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2579 // ^ | out | 7
2580 // | | args | 6 Holes in outgoing args owned by CALLEE
2581 // Owned by +--------+
2582 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2583 // | new |preserve| Must be even-aligned.
2584 // | SP-+--------+----> Matcher::_new_SP, even aligned
2585 // | | |
2586 //
2587 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2588 // known from SELF's arguments and the Java calling convention.
2589 // Region 6-7 is determined per call site.
2590 // Note 2: If the calling convention leaves holes in the incoming argument
2591 // area, those holes are owned by SELF. Holes in the outgoing area
2592 // are owned by the CALLEE. Holes should not be nessecary in the
2593 // incoming area, as the Java calling convention is completely under
2594 // the control of the AD file. Doubles can be sorted and packed to
2595 // avoid holes. Holes in the outgoing arguments may be nessecary for
2596 // varargs C calling conventions.
2597 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2598 // even aligned with pad0 as needed.
2599 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2600 // region 6-11 is even aligned; it may be padded out more so that
2601 // the region from SP to FP meets the minimum stack alignment.
2602 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2603 // alignment. Region 11, pad1, may be dynamically extended so that
2604 // SP meets the minimum alignment.
2605
2606 frame
2607 %{
2608 // What direction does stack grow in (assumed to be same for C & Java)
2609 stack_direction(TOWARDS_LOW);
2610
2611 // These three registers define part of the calling convention
2612 // between compiled code and the interpreter.
2613 inline_cache_reg(RAX); // Inline Cache Register
2614 interpreter_method_oop_reg(RBX); // Method Oop Register when
2615 // calling interpreter
2616
2617 // Optional: name the operand used by cisc-spilling to access
2618 // [stack_pointer + offset]
2619 cisc_spilling_operand_name(indOffset32);
2620
2621 // Number of stack slots consumed by locking an object
2622 sync_stack_slots(2);
2623
2624 // Compiled code's Frame Pointer
2625 frame_pointer(RSP);
2626
2627 // Interpreter stores its frame pointer in a register which is
2628 // stored to the stack by I2CAdaptors.
2629 // I2CAdaptors convert from interpreted java to compiled java.
2630 interpreter_frame_pointer(RBP);
2631
2632 // Stack alignment requirement
2633 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2634
2635 // Number of stack slots between incoming argument block and the start of
2636 // a new frame. The PROLOG must add this many slots to the stack. The
2637 // EPILOG must remove this many slots. amd64 needs two slots for
2638 // return address.
2639 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2640
2641 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2642 // for calls to C. Supports the var-args backing area for register parms.
2643 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2644
2645 // The after-PROLOG location of the return address. Location of
2646 // return address specifies a type (REG or STACK) and a number
2647 // representing the register number (i.e. - use a register name) or
2648 // stack slot.
2649 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2650 // Otherwise, it is above the locks and verification slot and alignment word
2651 return_addr(STACK - 2 +
2652 round_to((Compile::current()->in_preserve_stack_slots() +
2653 Compile::current()->fixed_slots()),
2654 stack_alignment_in_slots()));
2655
2656 // Body of function which returns an integer array locating
2657 // arguments either in registers or in stack slots. Passed an array
2658 // of ideal registers called "sig" and a "length" count. Stack-slot
2659 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2660 // arguments for a CALLEE. Incoming stack arguments are
2661 // automatically biased by the preserve_stack_slots field above.
2662
2663 calling_convention
2664 %{
2665 // No difference between ingoing/outgoing just pass false
2666 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2667 %}
2668
2669 c_calling_convention
2670 %{
2671 // This is obviously always outgoing
2672 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2673 %}
2674
2675 // Location of compiled Java return values. Same as C for now.
2676 return_value
2677 %{
2678 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2679 "only return normal values");
2680
2681 static const int lo[Op_RegL + 1] = {
2682 0,
2683 0,
2684 RAX_num, // Op_RegN
2685 RAX_num, // Op_RegI
2686 RAX_num, // Op_RegP
2687 XMM0_num, // Op_RegF
2688 XMM0_num, // Op_RegD
2689 RAX_num // Op_RegL
2690 };
2691 static const int hi[Op_RegL + 1] = {
2692 0,
2693 0,
2694 OptoReg::Bad, // Op_RegN
2695 OptoReg::Bad, // Op_RegI
2696 RAX_H_num, // Op_RegP
2697 OptoReg::Bad, // Op_RegF
2698 XMM0b_num, // Op_RegD
2699 RAX_H_num // Op_RegL
2700 };
2701 // Excluded flags and vector registers.
2702 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type");
2703 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2704 %}
2705 %}
2706
2707 //----------ATTRIBUTES---------------------------------------------------------
2708 //----------Operand Attributes-------------------------------------------------
2709 op_attrib op_cost(0); // Required cost attribute
2710
2711 //----------Instruction Attributes---------------------------------------------
2712 ins_attrib ins_cost(100); // Required cost attribute
2713 ins_attrib ins_size(8); // Required size attribute (in bits)
2714 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2715 // a non-matching short branch variant
2716 // of some long branch?
2717 ins_attrib ins_alignment(1); // Required alignment attribute (must
2718 // be a power of 2) specifies the
2719 // alignment that some part of the
2720 // instruction (not necessarily the
2721 // start) requires. If > 1, a
2722 // compute_padding() function must be
2723 // provided for the instruction
2724
2725 //----------OPERANDS-----------------------------------------------------------
2726 // Operand definitions must precede instruction definitions for correct parsing
2727 // in the ADLC because operands constitute user defined types which are used in
2728 // instruction definitions.
2729
2730 //----------Simple Operands----------------------------------------------------
2731 // Immediate Operands
2732 // Integer Immediate
2733 operand immI()
2734 %{
2735 match(ConI);
2736
2737 op_cost(10);
2738 format %{ %}
2739 interface(CONST_INTER);
2740 %}
2741
2742 // Constant for test vs zero
2743 operand immI0()
2744 %{
2745 predicate(n->get_int() == 0);
2746 match(ConI);
2747
2748 op_cost(0);
2749 format %{ %}
2750 interface(CONST_INTER);
2751 %}
2752
2753 // Constant for increment
2754 operand immI1()
2755 %{
2756 predicate(n->get_int() == 1);
2757 match(ConI);
2758
2759 op_cost(0);
2760 format %{ %}
2761 interface(CONST_INTER);
2762 %}
2763
2764 // Constant for decrement
2765 operand immI_M1()
2766 %{
2767 predicate(n->get_int() == -1);
2768 match(ConI);
2769
2770 op_cost(0);
2771 format %{ %}
2772 interface(CONST_INTER);
2773 %}
2774
2775 // Valid scale values for addressing modes
2776 operand immI2()
2777 %{
2778 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2779 match(ConI);
2780
2781 format %{ %}
2782 interface(CONST_INTER);
2783 %}
2784
2785 operand immI8()
2786 %{
2787 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2788 match(ConI);
2789
2790 op_cost(5);
2791 format %{ %}
2792 interface(CONST_INTER);
2793 %}
2794
2795 operand immI16()
2796 %{
2797 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2798 match(ConI);
2799
2800 op_cost(10);
2801 format %{ %}
2802 interface(CONST_INTER);
2803 %}
2804
2805 // Int Immediate non-negative
2806 operand immU31()
2807 %{
2808 predicate(n->get_int() >= 0);
2809 match(ConI);
2810
2811 op_cost(0);
2812 format %{ %}
2813 interface(CONST_INTER);
2814 %}
2815
2816 // Constant for long shifts
2817 operand immI_32()
2818 %{
2819 predicate( n->get_int() == 32 );
2820 match(ConI);
2821
2822 op_cost(0);
2823 format %{ %}
2824 interface(CONST_INTER);
2825 %}
2826
2827 // Constant for long shifts
2828 operand immI_64()
2829 %{
2830 predicate( n->get_int() == 64 );
2831 match(ConI);
2832
2833 op_cost(0);
2834 format %{ %}
2835 interface(CONST_INTER);
2836 %}
2837
2838 // Pointer Immediate
2839 operand immP()
2840 %{
2841 match(ConP);
2842
2843 op_cost(10);
2844 format %{ %}
2845 interface(CONST_INTER);
2846 %}
2847
2848 // NULL Pointer Immediate
2849 operand immP0()
2850 %{
2851 predicate(n->get_ptr() == 0);
2852 match(ConP);
2853
2854 op_cost(5);
2855 format %{ %}
2856 interface(CONST_INTER);
2857 %}
2858
2859 // Pointer Immediate
2860 operand immN() %{
2861 match(ConN);
2862
2863 op_cost(10);
2864 format %{ %}
2865 interface(CONST_INTER);
2866 %}
2867
2868 operand immNKlass() %{
2869 match(ConNKlass);
2870
2871 op_cost(10);
2872 format %{ %}
2873 interface(CONST_INTER);
2874 %}
2875
2876 // NULL Pointer Immediate
2877 operand immN0() %{
2878 predicate(n->get_narrowcon() == 0);
2879 match(ConN);
2880
2881 op_cost(5);
2882 format %{ %}
2883 interface(CONST_INTER);
2884 %}
2885
2886 operand immP31()
2887 %{
2888 predicate(n->as_Type()->type()->reloc() == relocInfo::none
2889 && (n->get_ptr() >> 31) == 0);
2890 match(ConP);
2891
2892 op_cost(5);
2893 format %{ %}
2894 interface(CONST_INTER);
2895 %}
2896
2897
2898 // Long Immediate
2899 operand immL()
2900 %{
2901 match(ConL);
2902
2903 op_cost(20);
2904 format %{ %}
2905 interface(CONST_INTER);
2906 %}
2907
2908 // Long Immediate 8-bit
2909 operand immL8()
2910 %{
2911 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
2912 match(ConL);
2913
2914 op_cost(5);
2915 format %{ %}
2916 interface(CONST_INTER);
2917 %}
2918
2919 // Long Immediate 32-bit unsigned
2920 operand immUL32()
2921 %{
2922 predicate(n->get_long() == (unsigned int) (n->get_long()));
2923 match(ConL);
2924
2925 op_cost(10);
2926 format %{ %}
2927 interface(CONST_INTER);
2928 %}
2929
2930 // Long Immediate 32-bit signed
2931 operand immL32()
2932 %{
2933 predicate(n->get_long() == (int) (n->get_long()));
2934 match(ConL);
2935
2936 op_cost(15);
2937 format %{ %}
2938 interface(CONST_INTER);
2939 %}
2940
2941 // Long Immediate zero
2942 operand immL0()
2943 %{
2944 predicate(n->get_long() == 0L);
2945 match(ConL);
2946
2947 op_cost(10);
2948 format %{ %}
2949 interface(CONST_INTER);
2950 %}
2951
2952 // Constant for increment
2953 operand immL1()
2954 %{
2955 predicate(n->get_long() == 1);
2956 match(ConL);
2957
2958 format %{ %}
2959 interface(CONST_INTER);
2960 %}
2961
2962 // Constant for decrement
2963 operand immL_M1()
2964 %{
2965 predicate(n->get_long() == -1);
2966 match(ConL);
2967
2968 format %{ %}
2969 interface(CONST_INTER);
2970 %}
2971
2972 // Long Immediate: the value 10
2973 operand immL10()
2974 %{
2975 predicate(n->get_long() == 10);
2976 match(ConL);
2977
2978 format %{ %}
2979 interface(CONST_INTER);
2980 %}
2981
2982 // Long immediate from 0 to 127.
2983 // Used for a shorter form of long mul by 10.
2984 operand immL_127()
2985 %{
2986 predicate(0 <= n->get_long() && n->get_long() < 0x80);
2987 match(ConL);
2988
2989 op_cost(10);
2990 format %{ %}
2991 interface(CONST_INTER);
2992 %}
2993
2994 // Long Immediate: low 32-bit mask
2995 operand immL_32bits()
2996 %{
2997 predicate(n->get_long() == 0xFFFFFFFFL);
2998 match(ConL);
2999 op_cost(20);
3000
3001 format %{ %}
3002 interface(CONST_INTER);
3003 %}
3004
3005 // Float Immediate zero
3006 operand immF0()
3007 %{
3008 predicate(jint_cast(n->getf()) == 0);
3009 match(ConF);
3010
3011 op_cost(5);
3012 format %{ %}
3013 interface(CONST_INTER);
3014 %}
3015
3016 // Float Immediate
3017 operand immF()
3018 %{
3019 match(ConF);
3020
3021 op_cost(15);
3022 format %{ %}
3023 interface(CONST_INTER);
3024 %}
3025
3026 // Double Immediate zero
3027 operand immD0()
3028 %{
3029 predicate(jlong_cast(n->getd()) == 0);
3030 match(ConD);
3031
3032 op_cost(5);
3033 format %{ %}
3034 interface(CONST_INTER);
3035 %}
3036
3037 // Double Immediate
3038 operand immD()
3039 %{
3040 match(ConD);
3041
3042 op_cost(15);
3043 format %{ %}
3044 interface(CONST_INTER);
3045 %}
3046
3047 // Immediates for special shifts (sign extend)
3048
3049 // Constants for increment
3050 operand immI_16()
3051 %{
3052 predicate(n->get_int() == 16);
3053 match(ConI);
3054
3055 format %{ %}
3056 interface(CONST_INTER);
3057 %}
3058
3059 operand immI_24()
3060 %{
3061 predicate(n->get_int() == 24);
3062 match(ConI);
3063
3064 format %{ %}
3065 interface(CONST_INTER);
3066 %}
3067
3068 // Constant for byte-wide masking
3069 operand immI_255()
3070 %{
3071 predicate(n->get_int() == 255);
3072 match(ConI);
3073
3074 format %{ %}
3075 interface(CONST_INTER);
3076 %}
3077
3078 // Constant for short-wide masking
3079 operand immI_65535()
3080 %{
3081 predicate(n->get_int() == 65535);
3082 match(ConI);
3083
3084 format %{ %}
3085 interface(CONST_INTER);
3086 %}
3087
3088 // Constant for byte-wide masking
3089 operand immL_255()
3090 %{
3091 predicate(n->get_long() == 255);
3092 match(ConL);
3093
3094 format %{ %}
3095 interface(CONST_INTER);
3096 %}
3097
3098 // Constant for short-wide masking
3099 operand immL_65535()
3100 %{
3101 predicate(n->get_long() == 65535);
3102 match(ConL);
3103
3104 format %{ %}
3105 interface(CONST_INTER);
3106 %}
3107
3108 // Register Operands
3109 // Integer Register
3110 operand rRegI()
3111 %{
3112 constraint(ALLOC_IN_RC(int_reg));
3113 match(RegI);
3114
3115 match(rax_RegI);
3116 match(rbx_RegI);
3117 match(rcx_RegI);
3118 match(rdx_RegI);
3119 match(rdi_RegI);
3120
3121 format %{ %}
3122 interface(REG_INTER);
3123 %}
3124
3125 // Special Registers
3126 operand rax_RegI()
3127 %{
3128 constraint(ALLOC_IN_RC(int_rax_reg));
3129 match(RegI);
3130 match(rRegI);
3131
3132 format %{ "RAX" %}
3133 interface(REG_INTER);
3134 %}
3135
3136 // Special Registers
3137 operand rbx_RegI()
3138 %{
3139 constraint(ALLOC_IN_RC(int_rbx_reg));
3140 match(RegI);
3141 match(rRegI);
3142
3143 format %{ "RBX" %}
3144 interface(REG_INTER);
3145 %}
3146
3147 operand rcx_RegI()
3148 %{
3149 constraint(ALLOC_IN_RC(int_rcx_reg));
3150 match(RegI);
3151 match(rRegI);
3152
3153 format %{ "RCX" %}
3154 interface(REG_INTER);
3155 %}
3156
3157 operand rdx_RegI()
3158 %{
3159 constraint(ALLOC_IN_RC(int_rdx_reg));
3160 match(RegI);
3161 match(rRegI);
3162
3163 format %{ "RDX" %}
3164 interface(REG_INTER);
3165 %}
3166
3167 operand rdi_RegI()
3168 %{
3169 constraint(ALLOC_IN_RC(int_rdi_reg));
3170 match(RegI);
3171 match(rRegI);
3172
3173 format %{ "RDI" %}
3174 interface(REG_INTER);
3175 %}
3176
3177 operand no_rcx_RegI()
3178 %{
3179 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3180 match(RegI);
3181 match(rax_RegI);
3182 match(rbx_RegI);
3183 match(rdx_RegI);
3184 match(rdi_RegI);
3185
3186 format %{ %}
3187 interface(REG_INTER);
3188 %}
3189
3190 operand no_rax_rdx_RegI()
3191 %{
3192 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3193 match(RegI);
3194 match(rbx_RegI);
3195 match(rcx_RegI);
3196 match(rdi_RegI);
3197
3198 format %{ %}
3199 interface(REG_INTER);
3200 %}
3201
3202 // Pointer Register
3203 operand any_RegP()
3204 %{
3205 constraint(ALLOC_IN_RC(any_reg));
3206 match(RegP);
3207 match(rax_RegP);
3208 match(rbx_RegP);
3209 match(rdi_RegP);
3210 match(rsi_RegP);
3211 match(rbp_RegP);
3212 match(r15_RegP);
3213 match(rRegP);
3214
3215 format %{ %}
3216 interface(REG_INTER);
3217 %}
3218
3219 operand rRegP()
3220 %{
3221 constraint(ALLOC_IN_RC(ptr_reg));
3222 match(RegP);
3223 match(rax_RegP);
3224 match(rbx_RegP);
3225 match(rdi_RegP);
3226 match(rsi_RegP);
3227 match(rbp_RegP);
3228 match(r15_RegP); // See Q&A below about r15_RegP.
3229
3230 format %{ %}
3231 interface(REG_INTER);
3232 %}
3233
3234 operand rRegN() %{
3235 constraint(ALLOC_IN_RC(int_reg));
3236 match(RegN);
3237
3238 format %{ %}
3239 interface(REG_INTER);
3240 %}
3241
3242 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3243 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3244 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
3245 // The output of an instruction is controlled by the allocator, which respects
3246 // register class masks, not match rules. Unless an instruction mentions
3247 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3248 // by the allocator as an input.
3249
3250 operand no_rax_RegP()
3251 %{
3252 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3253 match(RegP);
3254 match(rbx_RegP);
3255 match(rsi_RegP);
3256 match(rdi_RegP);
3257
3258 format %{ %}
3259 interface(REG_INTER);
3260 %}
3261
3262 operand no_rbp_RegP()
3263 %{
3264 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
3265 match(RegP);
3266 match(rbx_RegP);
3267 match(rsi_RegP);
3268 match(rdi_RegP);
3269
3270 format %{ %}
3271 interface(REG_INTER);
3272 %}
3273
3274 operand no_rax_rbx_RegP()
3275 %{
3276 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3277 match(RegP);
3278 match(rsi_RegP);
3279 match(rdi_RegP);
3280
3281 format %{ %}
3282 interface(REG_INTER);
3283 %}
3284
3285 // Special Registers
3286 // Return a pointer value
3287 operand rax_RegP()
3288 %{
3289 constraint(ALLOC_IN_RC(ptr_rax_reg));
3290 match(RegP);
3291 match(rRegP);
3292
3293 format %{ %}
3294 interface(REG_INTER);
3295 %}
3296
3297 // Special Registers
3298 // Return a compressed pointer value
3299 operand rax_RegN()
3300 %{
3301 constraint(ALLOC_IN_RC(int_rax_reg));
3302 match(RegN);
3303 match(rRegN);
3304
3305 format %{ %}
3306 interface(REG_INTER);
3307 %}
3308
3309 // Used in AtomicAdd
3310 operand rbx_RegP()
3311 %{
3312 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3313 match(RegP);
3314 match(rRegP);
3315
3316 format %{ %}
3317 interface(REG_INTER);
3318 %}
3319
3320 operand rsi_RegP()
3321 %{
3322 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3323 match(RegP);
3324 match(rRegP);
3325
3326 format %{ %}
3327 interface(REG_INTER);
3328 %}
3329
3330 // Used in rep stosq
3331 operand rdi_RegP()
3332 %{
3333 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3334 match(RegP);
3335 match(rRegP);
3336
3337 format %{ %}
3338 interface(REG_INTER);
3339 %}
3340
3341 operand rbp_RegP()
3342 %{
3343 constraint(ALLOC_IN_RC(ptr_rbp_reg));
3344 match(RegP);
3345 match(rRegP);
3346
3347 format %{ %}
3348 interface(REG_INTER);
3349 %}
3350
3351 operand r15_RegP()
3352 %{
3353 constraint(ALLOC_IN_RC(ptr_r15_reg));
3354 match(RegP);
3355 match(rRegP);
3356
3357 format %{ %}
3358 interface(REG_INTER);
3359 %}
3360
3361 operand rRegL()
3362 %{
3363 constraint(ALLOC_IN_RC(long_reg));
3364 match(RegL);
3365 match(rax_RegL);
3366 match(rdx_RegL);
3367
3368 format %{ %}
3369 interface(REG_INTER);
3370 %}
3371
3372 // Special Registers
3373 operand no_rax_rdx_RegL()
3374 %{
3375 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3376 match(RegL);
3377 match(rRegL);
3378
3379 format %{ %}
3380 interface(REG_INTER);
3381 %}
3382
3383 operand no_rax_RegL()
3384 %{
3385 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3386 match(RegL);
3387 match(rRegL);
3388 match(rdx_RegL);
3389
3390 format %{ %}
3391 interface(REG_INTER);
3392 %}
3393
3394 operand no_rcx_RegL()
3395 %{
3396 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3397 match(RegL);
3398 match(rRegL);
3399
3400 format %{ %}
3401 interface(REG_INTER);
3402 %}
3403
3404 operand rax_RegL()
3405 %{
3406 constraint(ALLOC_IN_RC(long_rax_reg));
3407 match(RegL);
3408 match(rRegL);
3409
3410 format %{ "RAX" %}
3411 interface(REG_INTER);
3412 %}
3413
3414 operand rcx_RegL()
3415 %{
3416 constraint(ALLOC_IN_RC(long_rcx_reg));
3417 match(RegL);
3418 match(rRegL);
3419
3420 format %{ %}
3421 interface(REG_INTER);
3422 %}
3423
3424 operand rdx_RegL()
3425 %{
3426 constraint(ALLOC_IN_RC(long_rdx_reg));
3427 match(RegL);
3428 match(rRegL);
3429
3430 format %{ %}
3431 interface(REG_INTER);
3432 %}
3433
3434 // Flags register, used as output of compare instructions
3435 operand rFlagsReg()
3436 %{
3437 constraint(ALLOC_IN_RC(int_flags));
3438 match(RegFlags);
3439
3440 format %{ "RFLAGS" %}
3441 interface(REG_INTER);
3442 %}
3443
3444 // Flags register, used as output of FLOATING POINT compare instructions
3445 operand rFlagsRegU()
3446 %{
3447 constraint(ALLOC_IN_RC(int_flags));
3448 match(RegFlags);
3449
3450 format %{ "RFLAGS_U" %}
3451 interface(REG_INTER);
3452 %}
3453
3454 operand rFlagsRegUCF() %{
3455 constraint(ALLOC_IN_RC(int_flags));
3456 match(RegFlags);
3457 predicate(false);
3458
3459 format %{ "RFLAGS_U_CF" %}
3460 interface(REG_INTER);
3461 %}
3462
3463 // Float register operands
3464 operand regF()
3465 %{
3466 constraint(ALLOC_IN_RC(float_reg));
3467 match(RegF);
3468
3469 format %{ %}
3470 interface(REG_INTER);
3471 %}
3472
3473 // Double register operands
3474 operand regD()
3475 %{
3476 constraint(ALLOC_IN_RC(double_reg));
3477 match(RegD);
3478
3479 format %{ %}
3480 interface(REG_INTER);
3481 %}
3482
3483 //----------Memory Operands----------------------------------------------------
3484 // Direct Memory Operand
3485 // operand direct(immP addr)
3486 // %{
3487 // match(addr);
3488
3489 // format %{ "[$addr]" %}
3490 // interface(MEMORY_INTER) %{
3491 // base(0xFFFFFFFF);
3492 // index(0x4);
3493 // scale(0x0);
3494 // disp($addr);
3495 // %}
3496 // %}
3497
3498 // Indirect Memory Operand
3499 operand indirect(any_RegP reg)
3500 %{
3501 constraint(ALLOC_IN_RC(ptr_reg));
3502 match(reg);
3503
3504 format %{ "[$reg]" %}
3505 interface(MEMORY_INTER) %{
3506 base($reg);
3507 index(0x4);
3508 scale(0x0);
3509 disp(0x0);
3510 %}
3511 %}
3512
3513 // Indirect Memory Plus Short Offset Operand
3514 operand indOffset8(any_RegP reg, immL8 off)
3515 %{
3516 constraint(ALLOC_IN_RC(ptr_reg));
3517 match(AddP reg off);
3518
3519 format %{ "[$reg + $off (8-bit)]" %}
3520 interface(MEMORY_INTER) %{
3521 base($reg);
3522 index(0x4);
3523 scale(0x0);
3524 disp($off);
3525 %}
3526 %}
3527
3528 // Indirect Memory Plus Long Offset Operand
3529 operand indOffset32(any_RegP reg, immL32 off)
3530 %{
3531 constraint(ALLOC_IN_RC(ptr_reg));
3532 match(AddP reg off);
3533
3534 format %{ "[$reg + $off (32-bit)]" %}
3535 interface(MEMORY_INTER) %{
3536 base($reg);
3537 index(0x4);
3538 scale(0x0);
3539 disp($off);
3540 %}
3541 %}
3542
3543 // Indirect Memory Plus Index Register Plus Offset Operand
3544 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3545 %{
3546 constraint(ALLOC_IN_RC(ptr_reg));
3547 match(AddP (AddP reg lreg) off);
3548
3549 op_cost(10);
3550 format %{"[$reg + $off + $lreg]" %}
3551 interface(MEMORY_INTER) %{
3552 base($reg);
3553 index($lreg);
3554 scale(0x0);
3555 disp($off);
3556 %}
3557 %}
3558
3559 // Indirect Memory Plus Index Register Plus Offset Operand
3560 operand indIndex(any_RegP reg, rRegL lreg)
3561 %{
3562 constraint(ALLOC_IN_RC(ptr_reg));
3563 match(AddP reg lreg);
3564
3565 op_cost(10);
3566 format %{"[$reg + $lreg]" %}
3567 interface(MEMORY_INTER) %{
3568 base($reg);
3569 index($lreg);
3570 scale(0x0);
3571 disp(0x0);
3572 %}
3573 %}
3574
3575 // Indirect Memory Times Scale Plus Index Register
3576 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3577 %{
3578 constraint(ALLOC_IN_RC(ptr_reg));
3579 match(AddP reg (LShiftL lreg scale));
3580
3581 op_cost(10);
3582 format %{"[$reg + $lreg << $scale]" %}
3583 interface(MEMORY_INTER) %{
3584 base($reg);
3585 index($lreg);
3586 scale($scale);
3587 disp(0x0);
3588 %}
3589 %}
3590
3591 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3592 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3593 %{
3594 constraint(ALLOC_IN_RC(ptr_reg));
3595 match(AddP (AddP reg (LShiftL lreg scale)) off);
3596
3597 op_cost(10);
3598 format %{"[$reg + $off + $lreg << $scale]" %}
3599 interface(MEMORY_INTER) %{
3600 base($reg);
3601 index($lreg);
3602 scale($scale);
3603 disp($off);
3604 %}
3605 %}
3606
3607 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3608 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3609 %{
3610 constraint(ALLOC_IN_RC(ptr_reg));
3611 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3612 match(AddP (AddP reg (ConvI2L idx)) off);
3613
3614 op_cost(10);
3615 format %{"[$reg + $off + $idx]" %}
3616 interface(MEMORY_INTER) %{
3617 base($reg);
3618 index($idx);
3619 scale(0x0);
3620 disp($off);
3621 %}
3622 %}
3623
3624 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3625 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3626 %{
3627 constraint(ALLOC_IN_RC(ptr_reg));
3628 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3629 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3630
3631 op_cost(10);
3632 format %{"[$reg + $off + $idx << $scale]" %}
3633 interface(MEMORY_INTER) %{
3634 base($reg);
3635 index($idx);
3636 scale($scale);
3637 disp($off);
3638 %}
3639 %}
3640
3641 // Indirect Narrow Oop Plus Offset Operand
3642 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3643 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3644 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3645 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3646 constraint(ALLOC_IN_RC(ptr_reg));
3647 match(AddP (DecodeN reg) off);
3648
3649 op_cost(10);
3650 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3651 interface(MEMORY_INTER) %{
3652 base(0xc); // R12
3653 index($reg);
3654 scale(0x3);
3655 disp($off);
3656 %}
3657 %}
3658
3659 // Indirect Memory Operand
3660 operand indirectNarrow(rRegN reg)
3661 %{
3662 predicate(Universe::narrow_oop_shift() == 0);
3663 constraint(ALLOC_IN_RC(ptr_reg));
3664 match(DecodeN reg);
3665
3666 format %{ "[$reg]" %}
3667 interface(MEMORY_INTER) %{
3668 base($reg);
3669 index(0x4);
3670 scale(0x0);
3671 disp(0x0);
3672 %}
3673 %}
3674
3675 // Indirect Memory Plus Short Offset Operand
3676 operand indOffset8Narrow(rRegN reg, immL8 off)
3677 %{
3678 predicate(Universe::narrow_oop_shift() == 0);
3679 constraint(ALLOC_IN_RC(ptr_reg));
3680 match(AddP (DecodeN reg) off);
3681
3682 format %{ "[$reg + $off (8-bit)]" %}
3683 interface(MEMORY_INTER) %{
3684 base($reg);
3685 index(0x4);
3686 scale(0x0);
3687 disp($off);
3688 %}
3689 %}
3690
3691 // Indirect Memory Plus Long Offset Operand
3692 operand indOffset32Narrow(rRegN reg, immL32 off)
3693 %{
3694 predicate(Universe::narrow_oop_shift() == 0);
3695 constraint(ALLOC_IN_RC(ptr_reg));
3696 match(AddP (DecodeN reg) off);
3697
3698 format %{ "[$reg + $off (32-bit)]" %}
3699 interface(MEMORY_INTER) %{
3700 base($reg);
3701 index(0x4);
3702 scale(0x0);
3703 disp($off);
3704 %}
3705 %}
3706
3707 // Indirect Memory Plus Index Register Plus Offset Operand
3708 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3709 %{
3710 predicate(Universe::narrow_oop_shift() == 0);
3711 constraint(ALLOC_IN_RC(ptr_reg));
3712 match(AddP (AddP (DecodeN reg) lreg) off);
3713
3714 op_cost(10);
3715 format %{"[$reg + $off + $lreg]" %}
3716 interface(MEMORY_INTER) %{
3717 base($reg);
3718 index($lreg);
3719 scale(0x0);
3720 disp($off);
3721 %}
3722 %}
3723
3724 // Indirect Memory Plus Index Register Plus Offset Operand
3725 operand indIndexNarrow(rRegN reg, rRegL lreg)
3726 %{
3727 predicate(Universe::narrow_oop_shift() == 0);
3728 constraint(ALLOC_IN_RC(ptr_reg));
3729 match(AddP (DecodeN reg) lreg);
3730
3731 op_cost(10);
3732 format %{"[$reg + $lreg]" %}
3733 interface(MEMORY_INTER) %{
3734 base($reg);
3735 index($lreg);
3736 scale(0x0);
3737 disp(0x0);
3738 %}
3739 %}
3740
3741 // Indirect Memory Times Scale Plus Index Register
3742 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3743 %{
3744 predicate(Universe::narrow_oop_shift() == 0);
3745 constraint(ALLOC_IN_RC(ptr_reg));
3746 match(AddP (DecodeN reg) (LShiftL lreg scale));
3747
3748 op_cost(10);
3749 format %{"[$reg + $lreg << $scale]" %}
3750 interface(MEMORY_INTER) %{
3751 base($reg);
3752 index($lreg);
3753 scale($scale);
3754 disp(0x0);
3755 %}
3756 %}
3757
3758 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3759 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3760 %{
3761 predicate(Universe::narrow_oop_shift() == 0);
3762 constraint(ALLOC_IN_RC(ptr_reg));
3763 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3764
3765 op_cost(10);
3766 format %{"[$reg + $off + $lreg << $scale]" %}
3767 interface(MEMORY_INTER) %{
3768 base($reg);
3769 index($lreg);
3770 scale($scale);
3771 disp($off);
3772 %}
3773 %}
3774
3775 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
3776 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
3777 %{
3778 constraint(ALLOC_IN_RC(ptr_reg));
3779 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3780 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
3781
3782 op_cost(10);
3783 format %{"[$reg + $off + $idx]" %}
3784 interface(MEMORY_INTER) %{
3785 base($reg);
3786 index($idx);
3787 scale(0x0);
3788 disp($off);
3789 %}
3790 %}
3791
3792 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3793 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3794 %{
3795 constraint(ALLOC_IN_RC(ptr_reg));
3796 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3797 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
3798
3799 op_cost(10);
3800 format %{"[$reg + $off + $idx << $scale]" %}
3801 interface(MEMORY_INTER) %{
3802 base($reg);
3803 index($idx);
3804 scale($scale);
3805 disp($off);
3806 %}
3807 %}
3808
3809 //----------Special Memory Operands--------------------------------------------
3810 // Stack Slot Operand - This operand is used for loading and storing temporary
3811 // values on the stack where a match requires a value to
3812 // flow through memory.
3813 operand stackSlotP(sRegP reg)
3814 %{
3815 constraint(ALLOC_IN_RC(stack_slots));
3816 // No match rule because this operand is only generated in matching
3817
3818 format %{ "[$reg]" %}
3819 interface(MEMORY_INTER) %{
3820 base(0x4); // RSP
3821 index(0x4); // No Index
3822 scale(0x0); // No Scale
3823 disp($reg); // Stack Offset
3824 %}
3825 %}
3826
3827 operand stackSlotI(sRegI reg)
3828 %{
3829 constraint(ALLOC_IN_RC(stack_slots));
3830 // No match rule because this operand is only generated in matching
3831
3832 format %{ "[$reg]" %}
3833 interface(MEMORY_INTER) %{
3834 base(0x4); // RSP
3835 index(0x4); // No Index
3836 scale(0x0); // No Scale
3837 disp($reg); // Stack Offset
3838 %}
3839 %}
3840
3841 operand stackSlotF(sRegF reg)
3842 %{
3843 constraint(ALLOC_IN_RC(stack_slots));
3844 // No match rule because this operand is only generated in matching
3845
3846 format %{ "[$reg]" %}
3847 interface(MEMORY_INTER) %{
3848 base(0x4); // RSP
3849 index(0x4); // No Index
3850 scale(0x0); // No Scale
3851 disp($reg); // Stack Offset
3852 %}
3853 %}
3854
3855 operand stackSlotD(sRegD reg)
3856 %{
3857 constraint(ALLOC_IN_RC(stack_slots));
3858 // No match rule because this operand is only generated in matching
3859
3860 format %{ "[$reg]" %}
3861 interface(MEMORY_INTER) %{
3862 base(0x4); // RSP
3863 index(0x4); // No Index
3864 scale(0x0); // No Scale
3865 disp($reg); // Stack Offset
3866 %}
3867 %}
3868 operand stackSlotL(sRegL reg)
3869 %{
3870 constraint(ALLOC_IN_RC(stack_slots));
3871 // No match rule because this operand is only generated in matching
3872
3873 format %{ "[$reg]" %}
3874 interface(MEMORY_INTER) %{
3875 base(0x4); // RSP
3876 index(0x4); // No Index
3877 scale(0x0); // No Scale
3878 disp($reg); // Stack Offset
3879 %}
3880 %}
3881
3882 //----------Conditional Branch Operands----------------------------------------
3883 // Comparison Op - This is the operation of the comparison, and is limited to
3884 // the following set of codes:
3885 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3886 //
3887 // Other attributes of the comparison, such as unsignedness, are specified
3888 // by the comparison instruction that sets a condition code flags register.
3889 // That result is represented by a flags operand whose subtype is appropriate
3890 // to the unsignedness (etc.) of the comparison.
3891 //
3892 // Later, the instruction which matches both the Comparison Op (a Bool) and
3893 // the flags (produced by the Cmp) specifies the coding of the comparison op
3894 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3895
3896 // Comparision Code
3897 operand cmpOp()
3898 %{
3899 match(Bool);
3900
3901 format %{ "" %}
3902 interface(COND_INTER) %{
3903 equal(0x4, "e");
3904 not_equal(0x5, "ne");
3905 less(0xC, "l");
3906 greater_equal(0xD, "ge");
3907 less_equal(0xE, "le");
3908 greater(0xF, "g");
3909 overflow(0x0, "o");
3910 no_overflow(0x1, "no");
3911 %}
3912 %}
3913
3914 // Comparison Code, unsigned compare. Used by FP also, with
3915 // C2 (unordered) turned into GT or LT already. The other bits
3916 // C0 and C3 are turned into Carry & Zero flags.
3917 operand cmpOpU()
3918 %{
3919 match(Bool);
3920
3921 format %{ "" %}
3922 interface(COND_INTER) %{
3923 equal(0x4, "e");
3924 not_equal(0x5, "ne");
3925 less(0x2, "b");
3926 greater_equal(0x3, "nb");
3927 less_equal(0x6, "be");
3928 greater(0x7, "nbe");
3929 overflow(0x0, "o");
3930 no_overflow(0x1, "no");
3931 %}
3932 %}
3933
3934
3935 // Floating comparisons that don't require any fixup for the unordered case
3936 operand cmpOpUCF() %{
3937 match(Bool);
3938 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3939 n->as_Bool()->_test._test == BoolTest::ge ||
3940 n->as_Bool()->_test._test == BoolTest::le ||
3941 n->as_Bool()->_test._test == BoolTest::gt);
3942 format %{ "" %}
3943 interface(COND_INTER) %{
3944 equal(0x4, "e");
3945 not_equal(0x5, "ne");
3946 less(0x2, "b");
3947 greater_equal(0x3, "nb");
3948 less_equal(0x6, "be");
3949 greater(0x7, "nbe");
3950 overflow(0x0, "o");
3951 no_overflow(0x1, "no");
3952 %}
3953 %}
3954
3955
3956 // Floating comparisons that can be fixed up with extra conditional jumps
3957 operand cmpOpUCF2() %{
3958 match(Bool);
3959 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3960 n->as_Bool()->_test._test == BoolTest::eq);
3961 format %{ "" %}
3962 interface(COND_INTER) %{
3963 equal(0x4, "e");
3964 not_equal(0x5, "ne");
3965 less(0x2, "b");
3966 greater_equal(0x3, "nb");
3967 less_equal(0x6, "be");
3968 greater(0x7, "nbe");
3969 overflow(0x0, "o");
3970 no_overflow(0x1, "no");
3971 %}
3972 %}
3973
3974
3975 //----------OPERAND CLASSES----------------------------------------------------
3976 // Operand Classes are groups of operands that are used as to simplify
3977 // instruction definitions by not requiring the AD writer to specify separate
3978 // instructions for every form of operand when the instruction accepts
3979 // multiple operand types with the same basic encoding and format. The classic
3980 // case of this is memory operands.
3981
3982 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
3983 indIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
3984 indCompressedOopOffset,
3985 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
3986 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
3987 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
3988
3989 //----------PIPELINE-----------------------------------------------------------
3990 // Rules which define the behavior of the target architectures pipeline.
3991 pipeline %{
3992
3993 //----------ATTRIBUTES---------------------------------------------------------
3994 attributes %{
3995 variable_size_instructions; // Fixed size instructions
3996 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
3997 instruction_unit_size = 1; // An instruction is 1 bytes long
3998 instruction_fetch_unit_size = 16; // The processor fetches one line
3999 instruction_fetch_units = 1; // of 16 bytes
4000
4001 // List of nop instructions
4002 nops( MachNop );
4003 %}
4004
4005 //----------RESOURCES----------------------------------------------------------
4006 // Resources are the functional units available to the machine
4007
4008 // Generic P2/P3 pipeline
4009 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4010 // 3 instructions decoded per cycle.
4011 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4012 // 3 ALU op, only ALU0 handles mul instructions.
4013 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4014 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4015 BR, FPU,
4016 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4017
4018 //----------PIPELINE DESCRIPTION-----------------------------------------------
4019 // Pipeline Description specifies the stages in the machine's pipeline
4020
4021 // Generic P2/P3 pipeline
4022 pipe_desc(S0, S1, S2, S3, S4, S5);
4023
4024 //----------PIPELINE CLASSES---------------------------------------------------
4025 // Pipeline Classes describe the stages in which input and output are
4026 // referenced by the hardware pipeline.
4027
4028 // Naming convention: ialu or fpu
4029 // Then: _reg
4030 // Then: _reg if there is a 2nd register
4031 // Then: _long if it's a pair of instructions implementing a long
4032 // Then: _fat if it requires the big decoder
4033 // Or: _mem if it requires the big decoder and a memory unit.
4034
4035 // Integer ALU reg operation
4036 pipe_class ialu_reg(rRegI dst)
4037 %{
4038 single_instruction;
4039 dst : S4(write);
4040 dst : S3(read);
4041 DECODE : S0; // any decoder
4042 ALU : S3; // any alu
4043 %}
4044
4045 // Long ALU reg operation
4046 pipe_class ialu_reg_long(rRegL dst)
4047 %{
4048 instruction_count(2);
4049 dst : S4(write);
4050 dst : S3(read);
4051 DECODE : S0(2); // any 2 decoders
4052 ALU : S3(2); // both alus
4053 %}
4054
4055 // Integer ALU reg operation using big decoder
4056 pipe_class ialu_reg_fat(rRegI dst)
4057 %{
4058 single_instruction;
4059 dst : S4(write);
4060 dst : S3(read);
4061 D0 : S0; // big decoder only
4062 ALU : S3; // any alu
4063 %}
4064
4065 // Long ALU reg operation using big decoder
4066 pipe_class ialu_reg_long_fat(rRegL dst)
4067 %{
4068 instruction_count(2);
4069 dst : S4(write);
4070 dst : S3(read);
4071 D0 : S0(2); // big decoder only; twice
4072 ALU : S3(2); // any 2 alus
4073 %}
4074
4075 // Integer ALU reg-reg operation
4076 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4077 %{
4078 single_instruction;
4079 dst : S4(write);
4080 src : S3(read);
4081 DECODE : S0; // any decoder
4082 ALU : S3; // any alu
4083 %}
4084
4085 // Long ALU reg-reg operation
4086 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4087 %{
4088 instruction_count(2);
4089 dst : S4(write);
4090 src : S3(read);
4091 DECODE : S0(2); // any 2 decoders
4092 ALU : S3(2); // both alus
4093 %}
4094
4095 // Integer ALU reg-reg operation
4096 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4097 %{
4098 single_instruction;
4099 dst : S4(write);
4100 src : S3(read);
4101 D0 : S0; // big decoder only
4102 ALU : S3; // any alu
4103 %}
4104
4105 // Long ALU reg-reg operation
4106 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4107 %{
4108 instruction_count(2);
4109 dst : S4(write);
4110 src : S3(read);
4111 D0 : S0(2); // big decoder only; twice
4112 ALU : S3(2); // both alus
4113 %}
4114
4115 // Integer ALU reg-mem operation
4116 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4117 %{
4118 single_instruction;
4119 dst : S5(write);
4120 mem : S3(read);
4121 D0 : S0; // big decoder only
4122 ALU : S4; // any alu
4123 MEM : S3; // any mem
4124 %}
4125
4126 // Integer mem operation (prefetch)
4127 pipe_class ialu_mem(memory mem)
4128 %{
4129 single_instruction;
4130 mem : S3(read);
4131 D0 : S0; // big decoder only
4132 MEM : S3; // any mem
4133 %}
4134
4135 // Integer Store to Memory
4136 pipe_class ialu_mem_reg(memory mem, rRegI src)
4137 %{
4138 single_instruction;
4139 mem : S3(read);
4140 src : S5(read);
4141 D0 : S0; // big decoder only
4142 ALU : S4; // any alu
4143 MEM : S3;
4144 %}
4145
4146 // // Long Store to Memory
4147 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4148 // %{
4149 // instruction_count(2);
4150 // mem : S3(read);
4151 // src : S5(read);
4152 // D0 : S0(2); // big decoder only; twice
4153 // ALU : S4(2); // any 2 alus
4154 // MEM : S3(2); // Both mems
4155 // %}
4156
4157 // Integer Store to Memory
4158 pipe_class ialu_mem_imm(memory mem)
4159 %{
4160 single_instruction;
4161 mem : S3(read);
4162 D0 : S0; // big decoder only
4163 ALU : S4; // any alu
4164 MEM : S3;
4165 %}
4166
4167 // Integer ALU0 reg-reg operation
4168 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4169 %{
4170 single_instruction;
4171 dst : S4(write);
4172 src : S3(read);
4173 D0 : S0; // Big decoder only
4174 ALU0 : S3; // only alu0
4175 %}
4176
4177 // Integer ALU0 reg-mem operation
4178 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4179 %{
4180 single_instruction;
4181 dst : S5(write);
4182 mem : S3(read);
4183 D0 : S0; // big decoder only
4184 ALU0 : S4; // ALU0 only
4185 MEM : S3; // any mem
4186 %}
4187
4188 // Integer ALU reg-reg operation
4189 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4190 %{
4191 single_instruction;
4192 cr : S4(write);
4193 src1 : S3(read);
4194 src2 : S3(read);
4195 DECODE : S0; // any decoder
4196 ALU : S3; // any alu
4197 %}
4198
4199 // Integer ALU reg-imm operation
4200 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4201 %{
4202 single_instruction;
4203 cr : S4(write);
4204 src1 : S3(read);
4205 DECODE : S0; // any decoder
4206 ALU : S3; // any alu
4207 %}
4208
4209 // Integer ALU reg-mem operation
4210 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4211 %{
4212 single_instruction;
4213 cr : S4(write);
4214 src1 : S3(read);
4215 src2 : S3(read);
4216 D0 : S0; // big decoder only
4217 ALU : S4; // any alu
4218 MEM : S3;
4219 %}
4220
4221 // Conditional move reg-reg
4222 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4223 %{
4224 instruction_count(4);
4225 y : S4(read);
4226 q : S3(read);
4227 p : S3(read);
4228 DECODE : S0(4); // any decoder
4229 %}
4230
4231 // Conditional move reg-reg
4232 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4233 %{
4234 single_instruction;
4235 dst : S4(write);
4236 src : S3(read);
4237 cr : S3(read);
4238 DECODE : S0; // any decoder
4239 %}
4240
4241 // Conditional move reg-mem
4242 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4243 %{
4244 single_instruction;
4245 dst : S4(write);
4246 src : S3(read);
4247 cr : S3(read);
4248 DECODE : S0; // any decoder
4249 MEM : S3;
4250 %}
4251
4252 // Conditional move reg-reg long
4253 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4254 %{
4255 single_instruction;
4256 dst : S4(write);
4257 src : S3(read);
4258 cr : S3(read);
4259 DECODE : S0(2); // any 2 decoders
4260 %}
4261
4262 // XXX
4263 // // Conditional move double reg-reg
4264 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4265 // %{
4266 // single_instruction;
4267 // dst : S4(write);
4268 // src : S3(read);
4269 // cr : S3(read);
4270 // DECODE : S0; // any decoder
4271 // %}
4272
4273 // Float reg-reg operation
4274 pipe_class fpu_reg(regD dst)
4275 %{
4276 instruction_count(2);
4277 dst : S3(read);
4278 DECODE : S0(2); // any 2 decoders
4279 FPU : S3;
4280 %}
4281
4282 // Float reg-reg operation
4283 pipe_class fpu_reg_reg(regD dst, regD src)
4284 %{
4285 instruction_count(2);
4286 dst : S4(write);
4287 src : S3(read);
4288 DECODE : S0(2); // any 2 decoders
4289 FPU : S3;
4290 %}
4291
4292 // Float reg-reg operation
4293 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4294 %{
4295 instruction_count(3);
4296 dst : S4(write);
4297 src1 : S3(read);
4298 src2 : S3(read);
4299 DECODE : S0(3); // any 3 decoders
4300 FPU : S3(2);
4301 %}
4302
4303 // Float reg-reg operation
4304 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4305 %{
4306 instruction_count(4);
4307 dst : S4(write);
4308 src1 : S3(read);
4309 src2 : S3(read);
4310 src3 : S3(read);
4311 DECODE : S0(4); // any 3 decoders
4312 FPU : S3(2);
4313 %}
4314
4315 // Float reg-reg operation
4316 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4317 %{
4318 instruction_count(4);
4319 dst : S4(write);
4320 src1 : S3(read);
4321 src2 : S3(read);
4322 src3 : S3(read);
4323 DECODE : S1(3); // any 3 decoders
4324 D0 : S0; // Big decoder only
4325 FPU : S3(2);
4326 MEM : S3;
4327 %}
4328
4329 // Float reg-mem operation
4330 pipe_class fpu_reg_mem(regD dst, memory mem)
4331 %{
4332 instruction_count(2);
4333 dst : S5(write);
4334 mem : S3(read);
4335 D0 : S0; // big decoder only
4336 DECODE : S1; // any decoder for FPU POP
4337 FPU : S4;
4338 MEM : S3; // any mem
4339 %}
4340
4341 // Float reg-mem operation
4342 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4343 %{
4344 instruction_count(3);
4345 dst : S5(write);
4346 src1 : S3(read);
4347 mem : S3(read);
4348 D0 : S0; // big decoder only
4349 DECODE : S1(2); // any decoder for FPU POP
4350 FPU : S4;
4351 MEM : S3; // any mem
4352 %}
4353
4354 // Float mem-reg operation
4355 pipe_class fpu_mem_reg(memory mem, regD src)
4356 %{
4357 instruction_count(2);
4358 src : S5(read);
4359 mem : S3(read);
4360 DECODE : S0; // any decoder for FPU PUSH
4361 D0 : S1; // big decoder only
4362 FPU : S4;
4363 MEM : S3; // any mem
4364 %}
4365
4366 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4367 %{
4368 instruction_count(3);
4369 src1 : S3(read);
4370 src2 : S3(read);
4371 mem : S3(read);
4372 DECODE : S0(2); // any decoder for FPU PUSH
4373 D0 : S1; // big decoder only
4374 FPU : S4;
4375 MEM : S3; // any mem
4376 %}
4377
4378 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4379 %{
4380 instruction_count(3);
4381 src1 : S3(read);
4382 src2 : S3(read);
4383 mem : S4(read);
4384 DECODE : S0; // any decoder for FPU PUSH
4385 D0 : S0(2); // big decoder only
4386 FPU : S4;
4387 MEM : S3(2); // any mem
4388 %}
4389
4390 pipe_class fpu_mem_mem(memory dst, memory src1)
4391 %{
4392 instruction_count(2);
4393 src1 : S3(read);
4394 dst : S4(read);
4395 D0 : S0(2); // big decoder only
4396 MEM : S3(2); // any mem
4397 %}
4398
4399 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4400 %{
4401 instruction_count(3);
4402 src1 : S3(read);
4403 src2 : S3(read);
4404 dst : S4(read);
4405 D0 : S0(3); // big decoder only
4406 FPU : S4;
4407 MEM : S3(3); // any mem
4408 %}
4409
4410 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4411 %{
4412 instruction_count(3);
4413 src1 : S4(read);
4414 mem : S4(read);
4415 DECODE : S0; // any decoder for FPU PUSH
4416 D0 : S0(2); // big decoder only
4417 FPU : S4;
4418 MEM : S3(2); // any mem
4419 %}
4420
4421 // Float load constant
4422 pipe_class fpu_reg_con(regD dst)
4423 %{
4424 instruction_count(2);
4425 dst : S5(write);
4426 D0 : S0; // big decoder only for the load
4427 DECODE : S1; // any decoder for FPU POP
4428 FPU : S4;
4429 MEM : S3; // any mem
4430 %}
4431
4432 // Float load constant
4433 pipe_class fpu_reg_reg_con(regD dst, regD src)
4434 %{
4435 instruction_count(3);
4436 dst : S5(write);
4437 src : S3(read);
4438 D0 : S0; // big decoder only for the load
4439 DECODE : S1(2); // any decoder for FPU POP
4440 FPU : S4;
4441 MEM : S3; // any mem
4442 %}
4443
4444 // UnConditional branch
4445 pipe_class pipe_jmp(label labl)
4446 %{
4447 single_instruction;
4448 BR : S3;
4449 %}
4450
4451 // Conditional branch
4452 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4453 %{
4454 single_instruction;
4455 cr : S1(read);
4456 BR : S3;
4457 %}
4458
4459 // Allocation idiom
4460 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4461 %{
4462 instruction_count(1); force_serialization;
4463 fixed_latency(6);
4464 heap_ptr : S3(read);
4465 DECODE : S0(3);
4466 D0 : S2;
4467 MEM : S3;
4468 ALU : S3(2);
4469 dst : S5(write);
4470 BR : S5;
4471 %}
4472
4473 // Generic big/slow expanded idiom
4474 pipe_class pipe_slow()
4475 %{
4476 instruction_count(10); multiple_bundles; force_serialization;
4477 fixed_latency(100);
4478 D0 : S0(2);
4479 MEM : S3(2);
4480 %}
4481
4482 // The real do-nothing guy
4483 pipe_class empty()
4484 %{
4485 instruction_count(0);
4486 %}
4487
4488 // Define the class for the Nop node
4489 define
4490 %{
4491 MachNop = empty;
4492 %}
4493
4494 %}
4495
4496 //----------INSTRUCTIONS-------------------------------------------------------
4497 //
4498 // match -- States which machine-independent subtree may be replaced
4499 // by this instruction.
4500 // ins_cost -- The estimated cost of this instruction is used by instruction
4501 // selection to identify a minimum cost tree of machine
4502 // instructions that matches a tree of machine-independent
4503 // instructions.
4504 // format -- A string providing the disassembly for this instruction.
4505 // The value of an instruction's operand may be inserted
4506 // by referring to it with a '$' prefix.
4507 // opcode -- Three instruction opcodes may be provided. These are referred
4508 // to within an encode class as $primary, $secondary, and $tertiary
4509 // rrspectively. The primary opcode is commonly used to
4510 // indicate the type of machine instruction, while secondary
4511 // and tertiary are often used for prefix options or addressing
4512 // modes.
4513 // ins_encode -- A list of encode classes with parameters. The encode class
4514 // name must have been defined in an 'enc_class' specification
4515 // in the encode section of the architecture description.
4516
4517
4518 //----------Load/Store/Move Instructions---------------------------------------
4519 //----------Load Instructions--------------------------------------------------
4520
4521 // Load Byte (8 bit signed)
4522 instruct loadB(rRegI dst, memory mem)
4523 %{
4524 match(Set dst (LoadB mem));
4525
4526 ins_cost(125);
4527 format %{ "movsbl $dst, $mem\t# byte" %}
4528
4529 ins_encode %{
4530 __ movsbl($dst$$Register, $mem$$Address);
4531 %}
4532
4533 ins_pipe(ialu_reg_mem);
4534 %}
4535
4536 // Load Byte (8 bit signed) into Long Register
4537 instruct loadB2L(rRegL dst, memory mem)
4538 %{
4539 match(Set dst (ConvI2L (LoadB mem)));
4540
4541 ins_cost(125);
4542 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4543
4544 ins_encode %{
4545 __ movsbq($dst$$Register, $mem$$Address);
4546 %}
4547
4548 ins_pipe(ialu_reg_mem);
4549 %}
4550
4551 // Load Unsigned Byte (8 bit UNsigned)
4552 instruct loadUB(rRegI dst, memory mem)
4553 %{
4554 match(Set dst (LoadUB mem));
4555
4556 ins_cost(125);
4557 format %{ "movzbl $dst, $mem\t# ubyte" %}
4558
4559 ins_encode %{
4560 __ movzbl($dst$$Register, $mem$$Address);
4561 %}
4562
4563 ins_pipe(ialu_reg_mem);
4564 %}
4565
4566 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4567 instruct loadUB2L(rRegL dst, memory mem)
4568 %{
4569 match(Set dst (ConvI2L (LoadUB mem)));
4570
4571 ins_cost(125);
4572 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4573
4574 ins_encode %{
4575 __ movzbq($dst$$Register, $mem$$Address);
4576 %}
4577
4578 ins_pipe(ialu_reg_mem);
4579 %}
4580
4581 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register
4582 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{
4583 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4584 effect(KILL cr);
4585
4586 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t"
4587 "andl $dst, $mask" %}
4588 ins_encode %{
4589 Register Rdst = $dst$$Register;
4590 __ movzbq(Rdst, $mem$$Address);
4591 __ andl(Rdst, $mask$$constant);
4592 %}
4593 ins_pipe(ialu_reg_mem);
4594 %}
4595
4596 // Load Short (16 bit signed)
4597 instruct loadS(rRegI dst, memory mem)
4598 %{
4599 match(Set dst (LoadS mem));
4600
4601 ins_cost(125);
4602 format %{ "movswl $dst, $mem\t# short" %}
4603
4604 ins_encode %{
4605 __ movswl($dst$$Register, $mem$$Address);
4606 %}
4607
4608 ins_pipe(ialu_reg_mem);
4609 %}
4610
4611 // Load Short (16 bit signed) to Byte (8 bit signed)
4612 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4613 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4614
4615 ins_cost(125);
4616 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4617 ins_encode %{
4618 __ movsbl($dst$$Register, $mem$$Address);
4619 %}
4620 ins_pipe(ialu_reg_mem);
4621 %}
4622
4623 // Load Short (16 bit signed) into Long Register
4624 instruct loadS2L(rRegL dst, memory mem)
4625 %{
4626 match(Set dst (ConvI2L (LoadS mem)));
4627
4628 ins_cost(125);
4629 format %{ "movswq $dst, $mem\t# short -> long" %}
4630
4631 ins_encode %{
4632 __ movswq($dst$$Register, $mem$$Address);
4633 %}
4634
4635 ins_pipe(ialu_reg_mem);
4636 %}
4637
4638 // Load Unsigned Short/Char (16 bit UNsigned)
4639 instruct loadUS(rRegI dst, memory mem)
4640 %{
4641 match(Set dst (LoadUS mem));
4642
4643 ins_cost(125);
4644 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4645
4646 ins_encode %{
4647 __ movzwl($dst$$Register, $mem$$Address);
4648 %}
4649
4650 ins_pipe(ialu_reg_mem);
4651 %}
4652
4653 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4654 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4655 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4656
4657 ins_cost(125);
4658 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4659 ins_encode %{
4660 __ movsbl($dst$$Register, $mem$$Address);
4661 %}
4662 ins_pipe(ialu_reg_mem);
4663 %}
4664
4665 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4666 instruct loadUS2L(rRegL dst, memory mem)
4667 %{
4668 match(Set dst (ConvI2L (LoadUS mem)));
4669
4670 ins_cost(125);
4671 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4672
4673 ins_encode %{
4674 __ movzwq($dst$$Register, $mem$$Address);
4675 %}
4676
4677 ins_pipe(ialu_reg_mem);
4678 %}
4679
4680 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4681 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4682 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4683
4684 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4685 ins_encode %{
4686 __ movzbq($dst$$Register, $mem$$Address);
4687 %}
4688 ins_pipe(ialu_reg_mem);
4689 %}
4690
4691 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register
4692 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{
4693 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4694 effect(KILL cr);
4695
4696 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t"
4697 "andl $dst, $mask" %}
4698 ins_encode %{
4699 Register Rdst = $dst$$Register;
4700 __ movzwq(Rdst, $mem$$Address);
4701 __ andl(Rdst, $mask$$constant);
4702 %}
4703 ins_pipe(ialu_reg_mem);
4704 %}
4705
4706 // Load Integer
4707 instruct loadI(rRegI dst, memory mem)
4708 %{
4709 match(Set dst (LoadI mem));
4710
4711 ins_cost(125);
4712 format %{ "movl $dst, $mem\t# int" %}
4713
4714 ins_encode %{
4715 __ movl($dst$$Register, $mem$$Address);
4716 %}
4717
4718 ins_pipe(ialu_reg_mem);
4719 %}
4720
4721 // Load Integer (32 bit signed) to Byte (8 bit signed)
4722 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4723 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4724
4725 ins_cost(125);
4726 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4727 ins_encode %{
4728 __ movsbl($dst$$Register, $mem$$Address);
4729 %}
4730 ins_pipe(ialu_reg_mem);
4731 %}
4732
4733 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4734 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4735 match(Set dst (AndI (LoadI mem) mask));
4736
4737 ins_cost(125);
4738 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4739 ins_encode %{
4740 __ movzbl($dst$$Register, $mem$$Address);
4741 %}
4742 ins_pipe(ialu_reg_mem);
4743 %}
4744
4745 // Load Integer (32 bit signed) to Short (16 bit signed)
4746 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4747 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4748
4749 ins_cost(125);
4750 format %{ "movswl $dst, $mem\t# int -> short" %}
4751 ins_encode %{
4752 __ movswl($dst$$Register, $mem$$Address);
4753 %}
4754 ins_pipe(ialu_reg_mem);
4755 %}
4756
4757 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4758 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4759 match(Set dst (AndI (LoadI mem) mask));
4760
4761 ins_cost(125);
4762 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4763 ins_encode %{
4764 __ movzwl($dst$$Register, $mem$$Address);
4765 %}
4766 ins_pipe(ialu_reg_mem);
4767 %}
4768
4769 // Load Integer into Long Register
4770 instruct loadI2L(rRegL dst, memory mem)
4771 %{
4772 match(Set dst (ConvI2L (LoadI mem)));
4773
4774 ins_cost(125);
4775 format %{ "movslq $dst, $mem\t# int -> long" %}
4776
4777 ins_encode %{
4778 __ movslq($dst$$Register, $mem$$Address);
4779 %}
4780
4781 ins_pipe(ialu_reg_mem);
4782 %}
4783
4784 // Load Integer with mask 0xFF into Long Register
4785 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4786 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4787
4788 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
4789 ins_encode %{
4790 __ movzbq($dst$$Register, $mem$$Address);
4791 %}
4792 ins_pipe(ialu_reg_mem);
4793 %}
4794
4795 // Load Integer with mask 0xFFFF into Long Register
4796 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
4797 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4798
4799 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
4800 ins_encode %{
4801 __ movzwq($dst$$Register, $mem$$Address);
4802 %}
4803 ins_pipe(ialu_reg_mem);
4804 %}
4805
4806 // Load Integer with a 31-bit mask into Long Register
4807 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
4808 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4809 effect(KILL cr);
4810
4811 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
4812 "andl $dst, $mask" %}
4813 ins_encode %{
4814 Register Rdst = $dst$$Register;
4815 __ movl(Rdst, $mem$$Address);
4816 __ andl(Rdst, $mask$$constant);
4817 %}
4818 ins_pipe(ialu_reg_mem);
4819 %}
4820
4821 // Load Unsigned Integer into Long Register
4822 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
4823 %{
4824 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4825
4826 ins_cost(125);
4827 format %{ "movl $dst, $mem\t# uint -> long" %}
4828
4829 ins_encode %{
4830 __ movl($dst$$Register, $mem$$Address);
4831 %}
4832
4833 ins_pipe(ialu_reg_mem);
4834 %}
4835
4836 // Load Long
4837 instruct loadL(rRegL dst, memory mem)
4838 %{
4839 match(Set dst (LoadL mem));
4840
4841 ins_cost(125);
4842 format %{ "movq $dst, $mem\t# long" %}
4843
4844 ins_encode %{
4845 __ movq($dst$$Register, $mem$$Address);
4846 %}
4847
4848 ins_pipe(ialu_reg_mem); // XXX
4849 %}
4850
4851 // Load Range
4852 instruct loadRange(rRegI dst, memory mem)
4853 %{
4854 match(Set dst (LoadRange mem));
4855
4856 ins_cost(125); // XXX
4857 format %{ "movl $dst, $mem\t# range" %}
4858 opcode(0x8B);
4859 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
4860 ins_pipe(ialu_reg_mem);
4861 %}
4862
4863 // Load Pointer
4864 instruct loadP(rRegP dst, memory mem)
4865 %{
4866 match(Set dst (LoadP mem));
4867
4868 ins_cost(125); // XXX
4869 format %{ "movq $dst, $mem\t# ptr" %}
4870 opcode(0x8B);
4871 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
4872 ins_pipe(ialu_reg_mem); // XXX
4873 %}
4874
4875 // Load Compressed Pointer
4876 instruct loadN(rRegN dst, memory mem)
4877 %{
4878 match(Set dst (LoadN mem));
4879
4880 ins_cost(125); // XXX
4881 format %{ "movl $dst, $mem\t# compressed ptr" %}
4882 ins_encode %{
4883 __ movl($dst$$Register, $mem$$Address);
4884 %}
4885 ins_pipe(ialu_reg_mem); // XXX
4886 %}
4887
4888
4889 // Load Klass Pointer
4890 instruct loadKlass(rRegP dst, memory mem)
4891 %{
4892 match(Set dst (LoadKlass mem));
4893
4894 ins_cost(125); // XXX
4895 format %{ "movq $dst, $mem\t# class" %}
4896 opcode(0x8B);
4897 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
4898 ins_pipe(ialu_reg_mem); // XXX
4899 %}
4900
4901 // Load narrow Klass Pointer
4902 instruct loadNKlass(rRegN dst, memory mem)
4903 %{
4904 match(Set dst (LoadNKlass mem));
4905
4906 ins_cost(125); // XXX
4907 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
4908 ins_encode %{
4909 __ movl($dst$$Register, $mem$$Address);
4910 %}
4911 ins_pipe(ialu_reg_mem); // XXX
4912 %}
4913
4914 // Load Float
4915 instruct loadF(regF dst, memory mem)
4916 %{
4917 match(Set dst (LoadF mem));
4918
4919 ins_cost(145); // XXX
4920 format %{ "movss $dst, $mem\t# float" %}
4921 ins_encode %{
4922 __ movflt($dst$$XMMRegister, $mem$$Address);
4923 %}
4924 ins_pipe(pipe_slow); // XXX
4925 %}
4926
4927 // Load Double
4928 instruct loadD_partial(regD dst, memory mem)
4929 %{
4930 predicate(!UseXmmLoadAndClearUpper);
4931 match(Set dst (LoadD mem));
4932
4933 ins_cost(145); // XXX
4934 format %{ "movlpd $dst, $mem\t# double" %}
4935 ins_encode %{
4936 __ movdbl($dst$$XMMRegister, $mem$$Address);
4937 %}
4938 ins_pipe(pipe_slow); // XXX
4939 %}
4940
4941 instruct loadD(regD dst, memory mem)
4942 %{
4943 predicate(UseXmmLoadAndClearUpper);
4944 match(Set dst (LoadD mem));
4945
4946 ins_cost(145); // XXX
4947 format %{ "movsd $dst, $mem\t# double" %}
4948 ins_encode %{
4949 __ movdbl($dst$$XMMRegister, $mem$$Address);
4950 %}
4951 ins_pipe(pipe_slow); // XXX
4952 %}
4953
4954 // Load Effective Address
4955 instruct leaP8(rRegP dst, indOffset8 mem)
4956 %{
4957 match(Set dst mem);
4958
4959 ins_cost(110); // XXX
4960 format %{ "leaq $dst, $mem\t# ptr 8" %}
4961 opcode(0x8D);
4962 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
4963 ins_pipe(ialu_reg_reg_fat);
4964 %}
4965
4966 instruct leaP32(rRegP dst, indOffset32 mem)
4967 %{
4968 match(Set dst mem);
4969
4970 ins_cost(110);
4971 format %{ "leaq $dst, $mem\t# ptr 32" %}
4972 opcode(0x8D);
4973 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
4974 ins_pipe(ialu_reg_reg_fat);
4975 %}
4976
4977 // instruct leaPIdx(rRegP dst, indIndex mem)
4978 // %{
4979 // match(Set dst mem);
4980
4981 // ins_cost(110);
4982 // format %{ "leaq $dst, $mem\t# ptr idx" %}
4983 // opcode(0x8D);
4984 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
4985 // ins_pipe(ialu_reg_reg_fat);
4986 // %}
4987
4988 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
4989 %{
4990 match(Set dst mem);
4991
4992 ins_cost(110);
4993 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
4994 opcode(0x8D);
4995 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
4996 ins_pipe(ialu_reg_reg_fat);
4997 %}
4998
4999 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5000 %{
5001 match(Set dst mem);
5002
5003 ins_cost(110);
5004 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5005 opcode(0x8D);
5006 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5007 ins_pipe(ialu_reg_reg_fat);
5008 %}
5009
5010 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5011 %{
5012 match(Set dst mem);
5013
5014 ins_cost(110);
5015 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5016 opcode(0x8D);
5017 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5018 ins_pipe(ialu_reg_reg_fat);
5019 %}
5020
5021 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5022 %{
5023 match(Set dst mem);
5024
5025 ins_cost(110);
5026 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5027 opcode(0x8D);
5028 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5029 ins_pipe(ialu_reg_reg_fat);
5030 %}
5031
5032 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5033 %{
5034 match(Set dst mem);
5035
5036 ins_cost(110);
5037 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5038 opcode(0x8D);
5039 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5040 ins_pipe(ialu_reg_reg_fat);
5041 %}
5042
5043 // Load Effective Address which uses Narrow (32-bits) oop
5044 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5045 %{
5046 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5047 match(Set dst mem);
5048
5049 ins_cost(110);
5050 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5051 opcode(0x8D);
5052 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5053 ins_pipe(ialu_reg_reg_fat);
5054 %}
5055
5056 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5057 %{
5058 predicate(Universe::narrow_oop_shift() == 0);
5059 match(Set dst mem);
5060
5061 ins_cost(110); // XXX
5062 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5063 opcode(0x8D);
5064 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5065 ins_pipe(ialu_reg_reg_fat);
5066 %}
5067
5068 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5069 %{
5070 predicate(Universe::narrow_oop_shift() == 0);
5071 match(Set dst mem);
5072
5073 ins_cost(110);
5074 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5075 opcode(0x8D);
5076 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5077 ins_pipe(ialu_reg_reg_fat);
5078 %}
5079
5080 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5081 %{
5082 predicate(Universe::narrow_oop_shift() == 0);
5083 match(Set dst mem);
5084
5085 ins_cost(110);
5086 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5087 opcode(0x8D);
5088 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5089 ins_pipe(ialu_reg_reg_fat);
5090 %}
5091
5092 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5093 %{
5094 predicate(Universe::narrow_oop_shift() == 0);
5095 match(Set dst mem);
5096
5097 ins_cost(110);
5098 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5099 opcode(0x8D);
5100 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5101 ins_pipe(ialu_reg_reg_fat);
5102 %}
5103
5104 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5105 %{
5106 predicate(Universe::narrow_oop_shift() == 0);
5107 match(Set dst mem);
5108
5109 ins_cost(110);
5110 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5111 opcode(0x8D);
5112 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5113 ins_pipe(ialu_reg_reg_fat);
5114 %}
5115
5116 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5117 %{
5118 predicate(Universe::narrow_oop_shift() == 0);
5119 match(Set dst mem);
5120
5121 ins_cost(110);
5122 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5123 opcode(0x8D);
5124 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5125 ins_pipe(ialu_reg_reg_fat);
5126 %}
5127
5128 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5129 %{
5130 predicate(Universe::narrow_oop_shift() == 0);
5131 match(Set dst mem);
5132
5133 ins_cost(110);
5134 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5135 opcode(0x8D);
5136 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5137 ins_pipe(ialu_reg_reg_fat);
5138 %}
5139
5140 instruct loadConI(rRegI dst, immI src)
5141 %{
5142 match(Set dst src);
5143
5144 format %{ "movl $dst, $src\t# int" %}
5145 ins_encode(load_immI(dst, src));
5146 ins_pipe(ialu_reg_fat); // XXX
5147 %}
5148
5149 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5150 %{
5151 match(Set dst src);
5152 effect(KILL cr);
5153
5154 ins_cost(50);
5155 format %{ "xorl $dst, $dst\t# int" %}
5156 opcode(0x33); /* + rd */
5157 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5158 ins_pipe(ialu_reg);
5159 %}
5160
5161 instruct loadConL(rRegL dst, immL src)
5162 %{
5163 match(Set dst src);
5164
5165 ins_cost(150);
5166 format %{ "movq $dst, $src\t# long" %}
5167 ins_encode(load_immL(dst, src));
5168 ins_pipe(ialu_reg);
5169 %}
5170
5171 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5172 %{
5173 match(Set dst src);
5174 effect(KILL cr);
5175
5176 ins_cost(50);
5177 format %{ "xorl $dst, $dst\t# long" %}
5178 opcode(0x33); /* + rd */
5179 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5180 ins_pipe(ialu_reg); // XXX
5181 %}
5182
5183 instruct loadConUL32(rRegL dst, immUL32 src)
5184 %{
5185 match(Set dst src);
5186
5187 ins_cost(60);
5188 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5189 ins_encode(load_immUL32(dst, src));
5190 ins_pipe(ialu_reg);
5191 %}
5192
5193 instruct loadConL32(rRegL dst, immL32 src)
5194 %{
5195 match(Set dst src);
5196
5197 ins_cost(70);
5198 format %{ "movq $dst, $src\t# long (32-bit)" %}
5199 ins_encode(load_immL32(dst, src));
5200 ins_pipe(ialu_reg);
5201 %}
5202
5203 instruct loadConP(rRegP dst, immP con) %{
5204 match(Set dst con);
5205
5206 format %{ "movq $dst, $con\t# ptr" %}
5207 ins_encode(load_immP(dst, con));
5208 ins_pipe(ialu_reg_fat); // XXX
5209 %}
5210
5211 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5212 %{
5213 match(Set dst src);
5214 effect(KILL cr);
5215
5216 ins_cost(50);
5217 format %{ "xorl $dst, $dst\t# ptr" %}
5218 opcode(0x33); /* + rd */
5219 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5220 ins_pipe(ialu_reg);
5221 %}
5222
5223 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5224 %{
5225 match(Set dst src);
5226 effect(KILL cr);
5227
5228 ins_cost(60);
5229 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5230 ins_encode(load_immP31(dst, src));
5231 ins_pipe(ialu_reg);
5232 %}
5233
5234 instruct loadConF(regF dst, immF con) %{
5235 match(Set dst con);
5236 ins_cost(125);
5237 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5238 ins_encode %{
5239 __ movflt($dst$$XMMRegister, $constantaddress($con));
5240 %}
5241 ins_pipe(pipe_slow);
5242 %}
5243
5244 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5245 match(Set dst src);
5246 effect(KILL cr);
5247 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5248 ins_encode %{
5249 __ xorq($dst$$Register, $dst$$Register);
5250 %}
5251 ins_pipe(ialu_reg);
5252 %}
5253
5254 instruct loadConN(rRegN dst, immN src) %{
5255 match(Set dst src);
5256
5257 ins_cost(125);
5258 format %{ "movl $dst, $src\t# compressed ptr" %}
5259 ins_encode %{
5260 address con = (address)$src$$constant;
5261 if (con == NULL) {
5262 ShouldNotReachHere();
5263 } else {
5264 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5265 }
5266 %}
5267 ins_pipe(ialu_reg_fat); // XXX
5268 %}
5269
5270 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5271 match(Set dst src);
5272
5273 ins_cost(125);
5274 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5275 ins_encode %{
5276 address con = (address)$src$$constant;
5277 if (con == NULL) {
5278 ShouldNotReachHere();
5279 } else {
5280 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5281 }
5282 %}
5283 ins_pipe(ialu_reg_fat); // XXX
5284 %}
5285
5286 instruct loadConF0(regF dst, immF0 src)
5287 %{
5288 match(Set dst src);
5289 ins_cost(100);
5290
5291 format %{ "xorps $dst, $dst\t# float 0.0" %}
5292 ins_encode %{
5293 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5294 %}
5295 ins_pipe(pipe_slow);
5296 %}
5297
5298 // Use the same format since predicate() can not be used here.
5299 instruct loadConD(regD dst, immD con) %{
5300 match(Set dst con);
5301 ins_cost(125);
5302 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5303 ins_encode %{
5304 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5305 %}
5306 ins_pipe(pipe_slow);
5307 %}
5308
5309 instruct loadConD0(regD dst, immD0 src)
5310 %{
5311 match(Set dst src);
5312 ins_cost(100);
5313
5314 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5315 ins_encode %{
5316 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5317 %}
5318 ins_pipe(pipe_slow);
5319 %}
5320
5321 instruct loadSSI(rRegI dst, stackSlotI src)
5322 %{
5323 match(Set dst src);
5324
5325 ins_cost(125);
5326 format %{ "movl $dst, $src\t# int stk" %}
5327 opcode(0x8B);
5328 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5329 ins_pipe(ialu_reg_mem);
5330 %}
5331
5332 instruct loadSSL(rRegL dst, stackSlotL src)
5333 %{
5334 match(Set dst src);
5335
5336 ins_cost(125);
5337 format %{ "movq $dst, $src\t# long stk" %}
5338 opcode(0x8B);
5339 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5340 ins_pipe(ialu_reg_mem);
5341 %}
5342
5343 instruct loadSSP(rRegP dst, stackSlotP src)
5344 %{
5345 match(Set dst src);
5346
5347 ins_cost(125);
5348 format %{ "movq $dst, $src\t# ptr stk" %}
5349 opcode(0x8B);
5350 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5351 ins_pipe(ialu_reg_mem);
5352 %}
5353
5354 instruct loadSSF(regF dst, stackSlotF src)
5355 %{
5356 match(Set dst src);
5357
5358 ins_cost(125);
5359 format %{ "movss $dst, $src\t# float stk" %}
5360 ins_encode %{
5361 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5362 %}
5363 ins_pipe(pipe_slow); // XXX
5364 %}
5365
5366 // Use the same format since predicate() can not be used here.
5367 instruct loadSSD(regD dst, stackSlotD src)
5368 %{
5369 match(Set dst src);
5370
5371 ins_cost(125);
5372 format %{ "movsd $dst, $src\t# double stk" %}
5373 ins_encode %{
5374 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5375 %}
5376 ins_pipe(pipe_slow); // XXX
5377 %}
5378
5379 // Prefetch instructions for allocation.
5380 // Must be safe to execute with invalid address (cannot fault).
5381
5382 instruct prefetchAlloc( memory mem ) %{
5383 predicate(AllocatePrefetchInstr==3);
5384 match(PrefetchAllocation mem);
5385 ins_cost(125);
5386
5387 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5388 ins_encode %{
5389 __ prefetchw($mem$$Address);
5390 %}
5391 ins_pipe(ialu_mem);
5392 %}
5393
5394 instruct prefetchAllocNTA( memory mem ) %{
5395 predicate(AllocatePrefetchInstr==0);
5396 match(PrefetchAllocation mem);
5397 ins_cost(125);
5398
5399 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5400 ins_encode %{
5401 __ prefetchnta($mem$$Address);
5402 %}
5403 ins_pipe(ialu_mem);
5404 %}
5405
5406 instruct prefetchAllocT0( memory mem ) %{
5407 predicate(AllocatePrefetchInstr==1);
5408 match(PrefetchAllocation mem);
5409 ins_cost(125);
5410
5411 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5412 ins_encode %{
5413 __ prefetcht0($mem$$Address);
5414 %}
5415 ins_pipe(ialu_mem);
5416 %}
5417
5418 instruct prefetchAllocT2( memory mem ) %{
5419 predicate(AllocatePrefetchInstr==2);
5420 match(PrefetchAllocation mem);
5421 ins_cost(125);
5422
5423 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5424 ins_encode %{
5425 __ prefetcht2($mem$$Address);
5426 %}
5427 ins_pipe(ialu_mem);
5428 %}
5429
5430 //----------Store Instructions-------------------------------------------------
5431
5432 // Store Byte
5433 instruct storeB(memory mem, rRegI src)
5434 %{
5435 match(Set mem (StoreB mem src));
5436
5437 ins_cost(125); // XXX
5438 format %{ "movb $mem, $src\t# byte" %}
5439 opcode(0x88);
5440 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5441 ins_pipe(ialu_mem_reg);
5442 %}
5443
5444 // Store Char/Short
5445 instruct storeC(memory mem, rRegI src)
5446 %{
5447 match(Set mem (StoreC mem src));
5448
5449 ins_cost(125); // XXX
5450 format %{ "movw $mem, $src\t# char/short" %}
5451 opcode(0x89);
5452 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5453 ins_pipe(ialu_mem_reg);
5454 %}
5455
5456 // Store Integer
5457 instruct storeI(memory mem, rRegI src)
5458 %{
5459 match(Set mem (StoreI mem src));
5460
5461 ins_cost(125); // XXX
5462 format %{ "movl $mem, $src\t# int" %}
5463 opcode(0x89);
5464 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5465 ins_pipe(ialu_mem_reg);
5466 %}
5467
5468 // Store Long
5469 instruct storeL(memory mem, rRegL src)
5470 %{
5471 match(Set mem (StoreL mem src));
5472
5473 ins_cost(125); // XXX
5474 format %{ "movq $mem, $src\t# long" %}
5475 opcode(0x89);
5476 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5477 ins_pipe(ialu_mem_reg); // XXX
5478 %}
5479
5480 // Store Pointer
5481 instruct storeP(memory mem, any_RegP src)
5482 %{
5483 match(Set mem (StoreP mem src));
5484
5485 ins_cost(125); // XXX
5486 format %{ "movq $mem, $src\t# ptr" %}
5487 opcode(0x89);
5488 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5489 ins_pipe(ialu_mem_reg);
5490 %}
5491
5492 instruct storeImmP0(memory mem, immP0 zero)
5493 %{
5494 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5495 match(Set mem (StoreP mem zero));
5496
5497 ins_cost(125); // XXX
5498 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5499 ins_encode %{
5500 __ movq($mem$$Address, r12);
5501 %}
5502 ins_pipe(ialu_mem_reg);
5503 %}
5504
5505 // Store NULL Pointer, mark word, or other simple pointer constant.
5506 instruct storeImmP(memory mem, immP31 src)
5507 %{
5508 match(Set mem (StoreP mem src));
5509
5510 ins_cost(150); // XXX
5511 format %{ "movq $mem, $src\t# ptr" %}
5512 opcode(0xC7); /* C7 /0 */
5513 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5514 ins_pipe(ialu_mem_imm);
5515 %}
5516
5517 // Store Compressed Pointer
5518 instruct storeN(memory mem, rRegN src)
5519 %{
5520 match(Set mem (StoreN mem src));
5521
5522 ins_cost(125); // XXX
5523 format %{ "movl $mem, $src\t# compressed ptr" %}
5524 ins_encode %{
5525 __ movl($mem$$Address, $src$$Register);
5526 %}
5527 ins_pipe(ialu_mem_reg);
5528 %}
5529
5530 instruct storeNKlass(memory mem, rRegN src)
5531 %{
5532 match(Set mem (StoreNKlass mem src));
5533
5534 ins_cost(125); // XXX
5535 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5536 ins_encode %{
5537 __ movl($mem$$Address, $src$$Register);
5538 %}
5539 ins_pipe(ialu_mem_reg);
5540 %}
5541
5542 instruct storeImmN0(memory mem, immN0 zero)
5543 %{
5544 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
5545 match(Set mem (StoreN mem zero));
5546
5547 ins_cost(125); // XXX
5548 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5549 ins_encode %{
5550 __ movl($mem$$Address, r12);
5551 %}
5552 ins_pipe(ialu_mem_reg);
5553 %}
5554
5555 instruct storeImmN(memory mem, immN src)
5556 %{
5557 match(Set mem (StoreN mem src));
5558
5559 ins_cost(150); // XXX
5560 format %{ "movl $mem, $src\t# compressed ptr" %}
5561 ins_encode %{
5562 address con = (address)$src$$constant;
5563 if (con == NULL) {
5564 __ movl($mem$$Address, (int32_t)0);
5565 } else {
5566 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5567 }
5568 %}
5569 ins_pipe(ialu_mem_imm);
5570 %}
5571
5572 instruct storeImmNKlass(memory mem, immNKlass src)
5573 %{
5574 match(Set mem (StoreNKlass mem src));
5575
5576 ins_cost(150); // XXX
5577 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5578 ins_encode %{
5579 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5580 %}
5581 ins_pipe(ialu_mem_imm);
5582 %}
5583
5584 // Store Integer Immediate
5585 instruct storeImmI0(memory mem, immI0 zero)
5586 %{
5587 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5588 match(Set mem (StoreI mem zero));
5589
5590 ins_cost(125); // XXX
5591 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5592 ins_encode %{
5593 __ movl($mem$$Address, r12);
5594 %}
5595 ins_pipe(ialu_mem_reg);
5596 %}
5597
5598 instruct storeImmI(memory mem, immI src)
5599 %{
5600 match(Set mem (StoreI mem src));
5601
5602 ins_cost(150);
5603 format %{ "movl $mem, $src\t# int" %}
5604 opcode(0xC7); /* C7 /0 */
5605 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5606 ins_pipe(ialu_mem_imm);
5607 %}
5608
5609 // Store Long Immediate
5610 instruct storeImmL0(memory mem, immL0 zero)
5611 %{
5612 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5613 match(Set mem (StoreL mem zero));
5614
5615 ins_cost(125); // XXX
5616 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5617 ins_encode %{
5618 __ movq($mem$$Address, r12);
5619 %}
5620 ins_pipe(ialu_mem_reg);
5621 %}
5622
5623 instruct storeImmL(memory mem, immL32 src)
5624 %{
5625 match(Set mem (StoreL mem src));
5626
5627 ins_cost(150);
5628 format %{ "movq $mem, $src\t# long" %}
5629 opcode(0xC7); /* C7 /0 */
5630 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5631 ins_pipe(ialu_mem_imm);
5632 %}
5633
5634 // Store Short/Char Immediate
5635 instruct storeImmC0(memory mem, immI0 zero)
5636 %{
5637 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5638 match(Set mem (StoreC mem zero));
5639
5640 ins_cost(125); // XXX
5641 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5642 ins_encode %{
5643 __ movw($mem$$Address, r12);
5644 %}
5645 ins_pipe(ialu_mem_reg);
5646 %}
5647
5648 instruct storeImmI16(memory mem, immI16 src)
5649 %{
5650 predicate(UseStoreImmI16);
5651 match(Set mem (StoreC mem src));
5652
5653 ins_cost(150);
5654 format %{ "movw $mem, $src\t# short/char" %}
5655 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
5656 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
5657 ins_pipe(ialu_mem_imm);
5658 %}
5659
5660 // Store Byte Immediate
5661 instruct storeImmB0(memory mem, immI0 zero)
5662 %{
5663 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5664 match(Set mem (StoreB mem zero));
5665
5666 ins_cost(125); // XXX
5667 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5668 ins_encode %{
5669 __ movb($mem$$Address, r12);
5670 %}
5671 ins_pipe(ialu_mem_reg);
5672 %}
5673
5674 instruct storeImmB(memory mem, immI8 src)
5675 %{
5676 match(Set mem (StoreB mem src));
5677
5678 ins_cost(150); // XXX
5679 format %{ "movb $mem, $src\t# byte" %}
5680 opcode(0xC6); /* C6 /0 */
5681 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5682 ins_pipe(ialu_mem_imm);
5683 %}
5684
5685 // Store CMS card-mark Immediate
5686 instruct storeImmCM0_reg(memory mem, immI0 zero)
5687 %{
5688 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5689 match(Set mem (StoreCM mem zero));
5690
5691 ins_cost(125); // XXX
5692 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5693 ins_encode %{
5694 __ movb($mem$$Address, r12);
5695 %}
5696 ins_pipe(ialu_mem_reg);
5697 %}
5698
5699 instruct storeImmCM0(memory mem, immI0 src)
5700 %{
5701 match(Set mem (StoreCM mem src));
5702
5703 ins_cost(150); // XXX
5704 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5705 opcode(0xC6); /* C6 /0 */
5706 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5707 ins_pipe(ialu_mem_imm);
5708 %}
5709
5710 // Store Float
5711 instruct storeF(memory mem, regF src)
5712 %{
5713 match(Set mem (StoreF mem src));
5714
5715 ins_cost(95); // XXX
5716 format %{ "movss $mem, $src\t# float" %}
5717 ins_encode %{
5718 __ movflt($mem$$Address, $src$$XMMRegister);
5719 %}
5720 ins_pipe(pipe_slow); // XXX
5721 %}
5722
5723 // Store immediate Float value (it is faster than store from XMM register)
5724 instruct storeF0(memory mem, immF0 zero)
5725 %{
5726 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5727 match(Set mem (StoreF mem zero));
5728
5729 ins_cost(25); // XXX
5730 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5731 ins_encode %{
5732 __ movl($mem$$Address, r12);
5733 %}
5734 ins_pipe(ialu_mem_reg);
5735 %}
5736
5737 instruct storeF_imm(memory mem, immF src)
5738 %{
5739 match(Set mem (StoreF mem src));
5740
5741 ins_cost(50);
5742 format %{ "movl $mem, $src\t# float" %}
5743 opcode(0xC7); /* C7 /0 */
5744 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5745 ins_pipe(ialu_mem_imm);
5746 %}
5747
5748 // Store Double
5749 instruct storeD(memory mem, regD src)
5750 %{
5751 match(Set mem (StoreD mem src));
5752
5753 ins_cost(95); // XXX
5754 format %{ "movsd $mem, $src\t# double" %}
5755 ins_encode %{
5756 __ movdbl($mem$$Address, $src$$XMMRegister);
5757 %}
5758 ins_pipe(pipe_slow); // XXX
5759 %}
5760
5761 // Store immediate double 0.0 (it is faster than store from XMM register)
5762 instruct storeD0_imm(memory mem, immD0 src)
5763 %{
5764 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
5765 match(Set mem (StoreD mem src));
5766
5767 ins_cost(50);
5768 format %{ "movq $mem, $src\t# double 0." %}
5769 opcode(0xC7); /* C7 /0 */
5770 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5771 ins_pipe(ialu_mem_imm);
5772 %}
5773
5774 instruct storeD0(memory mem, immD0 zero)
5775 %{
5776 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5777 match(Set mem (StoreD mem zero));
5778
5779 ins_cost(25); // XXX
5780 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
5781 ins_encode %{
5782 __ movq($mem$$Address, r12);
5783 %}
5784 ins_pipe(ialu_mem_reg);
5785 %}
5786
5787 instruct storeSSI(stackSlotI dst, rRegI src)
5788 %{
5789 match(Set dst src);
5790
5791 ins_cost(100);
5792 format %{ "movl $dst, $src\t# int stk" %}
5793 opcode(0x89);
5794 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
5795 ins_pipe( ialu_mem_reg );
5796 %}
5797
5798 instruct storeSSL(stackSlotL dst, rRegL src)
5799 %{
5800 match(Set dst src);
5801
5802 ins_cost(100);
5803 format %{ "movq $dst, $src\t# long stk" %}
5804 opcode(0x89);
5805 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
5806 ins_pipe(ialu_mem_reg);
5807 %}
5808
5809 instruct storeSSP(stackSlotP dst, rRegP src)
5810 %{
5811 match(Set dst src);
5812
5813 ins_cost(100);
5814 format %{ "movq $dst, $src\t# ptr stk" %}
5815 opcode(0x89);
5816 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
5817 ins_pipe(ialu_mem_reg);
5818 %}
5819
5820 instruct storeSSF(stackSlotF dst, regF src)
5821 %{
5822 match(Set dst src);
5823
5824 ins_cost(95); // XXX
5825 format %{ "movss $dst, $src\t# float stk" %}
5826 ins_encode %{
5827 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
5828 %}
5829 ins_pipe(pipe_slow); // XXX
5830 %}
5831
5832 instruct storeSSD(stackSlotD dst, regD src)
5833 %{
5834 match(Set dst src);
5835
5836 ins_cost(95); // XXX
5837 format %{ "movsd $dst, $src\t# double stk" %}
5838 ins_encode %{
5839 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
5840 %}
5841 ins_pipe(pipe_slow); // XXX
5842 %}
5843
5844 //----------BSWAP Instructions-------------------------------------------------
5845 instruct bytes_reverse_int(rRegI dst) %{
5846 match(Set dst (ReverseBytesI dst));
5847
5848 format %{ "bswapl $dst" %}
5849 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
5850 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
5851 ins_pipe( ialu_reg );
5852 %}
5853
5854 instruct bytes_reverse_long(rRegL dst) %{
5855 match(Set dst (ReverseBytesL dst));
5856
5857 format %{ "bswapq $dst" %}
5858 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
5859 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
5860 ins_pipe( ialu_reg);
5861 %}
5862
5863 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
5864 match(Set dst (ReverseBytesUS dst));
5865 effect(KILL cr);
5866
5867 format %{ "bswapl $dst\n\t"
5868 "shrl $dst,16\n\t" %}
5869 ins_encode %{
5870 __ bswapl($dst$$Register);
5871 __ shrl($dst$$Register, 16);
5872 %}
5873 ins_pipe( ialu_reg );
5874 %}
5875
5876 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
5877 match(Set dst (ReverseBytesS dst));
5878 effect(KILL cr);
5879
5880 format %{ "bswapl $dst\n\t"
5881 "sar $dst,16\n\t" %}
5882 ins_encode %{
5883 __ bswapl($dst$$Register);
5884 __ sarl($dst$$Register, 16);
5885 %}
5886 ins_pipe( ialu_reg );
5887 %}
5888
5889 //---------- Zeros Count Instructions ------------------------------------------
5890
5891 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
5892 predicate(UseCountLeadingZerosInstruction);
5893 match(Set dst (CountLeadingZerosI src));
5894 effect(KILL cr);
5895
5896 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
5897 ins_encode %{
5898 __ lzcntl($dst$$Register, $src$$Register);
5899 %}
5900 ins_pipe(ialu_reg);
5901 %}
5902
5903 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
5904 predicate(!UseCountLeadingZerosInstruction);
5905 match(Set dst (CountLeadingZerosI src));
5906 effect(KILL cr);
5907
5908 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
5909 "jnz skip\n\t"
5910 "movl $dst, -1\n"
5911 "skip:\n\t"
5912 "negl $dst\n\t"
5913 "addl $dst, 31" %}
5914 ins_encode %{
5915 Register Rdst = $dst$$Register;
5916 Register Rsrc = $src$$Register;
5917 Label skip;
5918 __ bsrl(Rdst, Rsrc);
5919 __ jccb(Assembler::notZero, skip);
5920 __ movl(Rdst, -1);
5921 __ bind(skip);
5922 __ negl(Rdst);
5923 __ addl(Rdst, BitsPerInt - 1);
5924 %}
5925 ins_pipe(ialu_reg);
5926 %}
5927
5928 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
5929 predicate(UseCountLeadingZerosInstruction);
5930 match(Set dst (CountLeadingZerosL src));
5931 effect(KILL cr);
5932
5933 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
5934 ins_encode %{
5935 __ lzcntq($dst$$Register, $src$$Register);
5936 %}
5937 ins_pipe(ialu_reg);
5938 %}
5939
5940 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
5941 predicate(!UseCountLeadingZerosInstruction);
5942 match(Set dst (CountLeadingZerosL src));
5943 effect(KILL cr);
5944
5945 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
5946 "jnz skip\n\t"
5947 "movl $dst, -1\n"
5948 "skip:\n\t"
5949 "negl $dst\n\t"
5950 "addl $dst, 63" %}
5951 ins_encode %{
5952 Register Rdst = $dst$$Register;
5953 Register Rsrc = $src$$Register;
5954 Label skip;
5955 __ bsrq(Rdst, Rsrc);
5956 __ jccb(Assembler::notZero, skip);
5957 __ movl(Rdst, -1);
5958 __ bind(skip);
5959 __ negl(Rdst);
5960 __ addl(Rdst, BitsPerLong - 1);
5961 %}
5962 ins_pipe(ialu_reg);
5963 %}
5964
5965 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
5966 predicate(UseCountTrailingZerosInstruction);
5967 match(Set dst (CountTrailingZerosI src));
5968 effect(KILL cr);
5969
5970 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
5971 ins_encode %{
5972 __ tzcntl($dst$$Register, $src$$Register);
5973 %}
5974 ins_pipe(ialu_reg);
5975 %}
5976
5977 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
5978 predicate(!UseCountTrailingZerosInstruction);
5979 match(Set dst (CountTrailingZerosI src));
5980 effect(KILL cr);
5981
5982 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
5983 "jnz done\n\t"
5984 "movl $dst, 32\n"
5985 "done:" %}
5986 ins_encode %{
5987 Register Rdst = $dst$$Register;
5988 Label done;
5989 __ bsfl(Rdst, $src$$Register);
5990 __ jccb(Assembler::notZero, done);
5991 __ movl(Rdst, BitsPerInt);
5992 __ bind(done);
5993 %}
5994 ins_pipe(ialu_reg);
5995 %}
5996
5997 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
5998 predicate(UseCountTrailingZerosInstruction);
5999 match(Set dst (CountTrailingZerosL src));
6000 effect(KILL cr);
6001
6002 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6003 ins_encode %{
6004 __ tzcntq($dst$$Register, $src$$Register);
6005 %}
6006 ins_pipe(ialu_reg);
6007 %}
6008
6009 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6010 predicate(!UseCountTrailingZerosInstruction);
6011 match(Set dst (CountTrailingZerosL src));
6012 effect(KILL cr);
6013
6014 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6015 "jnz done\n\t"
6016 "movl $dst, 64\n"
6017 "done:" %}
6018 ins_encode %{
6019 Register Rdst = $dst$$Register;
6020 Label done;
6021 __ bsfq(Rdst, $src$$Register);
6022 __ jccb(Assembler::notZero, done);
6023 __ movl(Rdst, BitsPerLong);
6024 __ bind(done);
6025 %}
6026 ins_pipe(ialu_reg);
6027 %}
6028
6029
6030 //---------- Population Count Instructions -------------------------------------
6031
6032 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6033 predicate(UsePopCountInstruction);
6034 match(Set dst (PopCountI src));
6035 effect(KILL cr);
6036
6037 format %{ "popcnt $dst, $src" %}
6038 ins_encode %{
6039 __ popcntl($dst$$Register, $src$$Register);
6040 %}
6041 ins_pipe(ialu_reg);
6042 %}
6043
6044 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6045 predicate(UsePopCountInstruction);
6046 match(Set dst (PopCountI (LoadI mem)));
6047 effect(KILL cr);
6048
6049 format %{ "popcnt $dst, $mem" %}
6050 ins_encode %{
6051 __ popcntl($dst$$Register, $mem$$Address);
6052 %}
6053 ins_pipe(ialu_reg);
6054 %}
6055
6056 // Note: Long.bitCount(long) returns an int.
6057 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6058 predicate(UsePopCountInstruction);
6059 match(Set dst (PopCountL src));
6060 effect(KILL cr);
6061
6062 format %{ "popcnt $dst, $src" %}
6063 ins_encode %{
6064 __ popcntq($dst$$Register, $src$$Register);
6065 %}
6066 ins_pipe(ialu_reg);
6067 %}
6068
6069 // Note: Long.bitCount(long) returns an int.
6070 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6071 predicate(UsePopCountInstruction);
6072 match(Set dst (PopCountL (LoadL mem)));
6073 effect(KILL cr);
6074
6075 format %{ "popcnt $dst, $mem" %}
6076 ins_encode %{
6077 __ popcntq($dst$$Register, $mem$$Address);
6078 %}
6079 ins_pipe(ialu_reg);
6080 %}
6081
6082
6083 //----------MemBar Instructions-----------------------------------------------
6084 // Memory barrier flavors
6085
6086 instruct membar_acquire()
6087 %{
6088 match(MemBarAcquire);
6089 match(LoadFence);
6090 ins_cost(0);
6091
6092 size(0);
6093 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6094 ins_encode();
6095 ins_pipe(empty);
6096 %}
6097
6098 instruct membar_acquire_lock()
6099 %{
6100 match(MemBarAcquireLock);
6101 ins_cost(0);
6102
6103 size(0);
6104 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6105 ins_encode();
6106 ins_pipe(empty);
6107 %}
6108
6109 instruct membar_release()
6110 %{
6111 match(MemBarRelease);
6112 match(StoreFence);
6113 ins_cost(0);
6114
6115 size(0);
6116 format %{ "MEMBAR-release ! (empty encoding)" %}
6117 ins_encode();
6118 ins_pipe(empty);
6119 %}
6120
6121 instruct membar_release_lock()
6122 %{
6123 match(MemBarReleaseLock);
6124 ins_cost(0);
6125
6126 size(0);
6127 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6128 ins_encode();
6129 ins_pipe(empty);
6130 %}
6131
6132 instruct membar_volatile(rFlagsReg cr) %{
6133 match(MemBarVolatile);
6134 effect(KILL cr);
6135 ins_cost(400);
6136
6137 format %{
6138 $$template
6139 if (os::is_MP()) {
6140 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6141 } else {
6142 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6143 }
6144 %}
6145 ins_encode %{
6146 __ membar(Assembler::StoreLoad);
6147 %}
6148 ins_pipe(pipe_slow);
6149 %}
6150
6151 instruct unnecessary_membar_volatile()
6152 %{
6153 match(MemBarVolatile);
6154 predicate(Matcher::post_store_load_barrier(n));
6155 ins_cost(0);
6156
6157 size(0);
6158 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6159 ins_encode();
6160 ins_pipe(empty);
6161 %}
6162
6163 instruct membar_storestore() %{
6164 match(MemBarStoreStore);
6165 ins_cost(0);
6166
6167 size(0);
6168 format %{ "MEMBAR-storestore (empty encoding)" %}
6169 ins_encode( );
6170 ins_pipe(empty);
6171 %}
6172
6173 //----------Move Instructions--------------------------------------------------
6174
6175 instruct castX2P(rRegP dst, rRegL src)
6176 %{
6177 match(Set dst (CastX2P src));
6178
6179 format %{ "movq $dst, $src\t# long->ptr" %}
6180 ins_encode %{
6181 if ($dst$$reg != $src$$reg) {
6182 __ movptr($dst$$Register, $src$$Register);
6183 }
6184 %}
6185 ins_pipe(ialu_reg_reg); // XXX
6186 %}
6187
6188 instruct castP2X(rRegL dst, rRegP src)
6189 %{
6190 match(Set dst (CastP2X src));
6191
6192 format %{ "movq $dst, $src\t# ptr -> long" %}
6193 ins_encode %{
6194 if ($dst$$reg != $src$$reg) {
6195 __ movptr($dst$$Register, $src$$Register);
6196 }
6197 %}
6198 ins_pipe(ialu_reg_reg); // XXX
6199 %}
6200
6201 // Convert oop into int for vectors alignment masking
6202 instruct convP2I(rRegI dst, rRegP src)
6203 %{
6204 match(Set dst (ConvL2I (CastP2X src)));
6205
6206 format %{ "movl $dst, $src\t# ptr -> int" %}
6207 ins_encode %{
6208 __ movl($dst$$Register, $src$$Register);
6209 %}
6210 ins_pipe(ialu_reg_reg); // XXX
6211 %}
6212
6213 // Convert compressed oop into int for vectors alignment masking
6214 // in case of 32bit oops (heap < 4Gb).
6215 instruct convN2I(rRegI dst, rRegN src)
6216 %{
6217 predicate(Universe::narrow_oop_shift() == 0);
6218 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6219
6220 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6221 ins_encode %{
6222 __ movl($dst$$Register, $src$$Register);
6223 %}
6224 ins_pipe(ialu_reg_reg); // XXX
6225 %}
6226
6227 // Convert oop pointer into compressed form
6228 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6229 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6230 match(Set dst (EncodeP src));
6231 effect(KILL cr);
6232 format %{ "encode_heap_oop $dst,$src" %}
6233 ins_encode %{
6234 Register s = $src$$Register;
6235 Register d = $dst$$Register;
6236 if (s != d) {
6237 __ movq(d, s);
6238 }
6239 __ encode_heap_oop(d);
6240 %}
6241 ins_pipe(ialu_reg_long);
6242 %}
6243
6244 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6245 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6246 match(Set dst (EncodeP src));
6247 effect(KILL cr);
6248 format %{ "encode_heap_oop_not_null $dst,$src" %}
6249 ins_encode %{
6250 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6251 %}
6252 ins_pipe(ialu_reg_long);
6253 %}
6254
6255 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6256 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6257 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6258 match(Set dst (DecodeN src));
6259 effect(KILL cr);
6260 format %{ "decode_heap_oop $dst,$src" %}
6261 ins_encode %{
6262 Register s = $src$$Register;
6263 Register d = $dst$$Register;
6264 if (s != d) {
6265 __ movq(d, s);
6266 }
6267 __ decode_heap_oop(d);
6268 %}
6269 ins_pipe(ialu_reg_long);
6270 %}
6271
6272 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6273 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6274 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6275 match(Set dst (DecodeN src));
6276 effect(KILL cr);
6277 format %{ "decode_heap_oop_not_null $dst,$src" %}
6278 ins_encode %{
6279 Register s = $src$$Register;
6280 Register d = $dst$$Register;
6281 if (s != d) {
6282 __ decode_heap_oop_not_null(d, s);
6283 } else {
6284 __ decode_heap_oop_not_null(d);
6285 }
6286 %}
6287 ins_pipe(ialu_reg_long);
6288 %}
6289
6290 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6291 match(Set dst (EncodePKlass src));
6292 effect(KILL cr);
6293 format %{ "encode_klass_not_null $dst,$src" %}
6294 ins_encode %{
6295 __ encode_klass_not_null($dst$$Register, $src$$Register);
6296 %}
6297 ins_pipe(ialu_reg_long);
6298 %}
6299
6300 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6301 match(Set dst (DecodeNKlass src));
6302 effect(KILL cr);
6303 format %{ "decode_klass_not_null $dst,$src" %}
6304 ins_encode %{
6305 Register s = $src$$Register;
6306 Register d = $dst$$Register;
6307 if (s != d) {
6308 __ decode_klass_not_null(d, s);
6309 } else {
6310 __ decode_klass_not_null(d);
6311 }
6312 %}
6313 ins_pipe(ialu_reg_long);
6314 %}
6315
6316
6317 //----------Conditional Move---------------------------------------------------
6318 // Jump
6319 // dummy instruction for generating temp registers
6320 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6321 match(Jump (LShiftL switch_val shift));
6322 ins_cost(350);
6323 predicate(false);
6324 effect(TEMP dest);
6325
6326 format %{ "leaq $dest, [$constantaddress]\n\t"
6327 "jmp [$dest + $switch_val << $shift]\n\t" %}
6328 ins_encode %{
6329 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6330 // to do that and the compiler is using that register as one it can allocate.
6331 // So we build it all by hand.
6332 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6333 // ArrayAddress dispatch(table, index);
6334 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6335 __ lea($dest$$Register, $constantaddress);
6336 __ jmp(dispatch);
6337 %}
6338 ins_pipe(pipe_jmp);
6339 %}
6340
6341 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6342 match(Jump (AddL (LShiftL switch_val shift) offset));
6343 ins_cost(350);
6344 effect(TEMP dest);
6345
6346 format %{ "leaq $dest, [$constantaddress]\n\t"
6347 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6348 ins_encode %{
6349 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6350 // to do that and the compiler is using that register as one it can allocate.
6351 // So we build it all by hand.
6352 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6353 // ArrayAddress dispatch(table, index);
6354 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6355 __ lea($dest$$Register, $constantaddress);
6356 __ jmp(dispatch);
6357 %}
6358 ins_pipe(pipe_jmp);
6359 %}
6360
6361 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6362 match(Jump switch_val);
6363 ins_cost(350);
6364 effect(TEMP dest);
6365
6366 format %{ "leaq $dest, [$constantaddress]\n\t"
6367 "jmp [$dest + $switch_val]\n\t" %}
6368 ins_encode %{
6369 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6370 // to do that and the compiler is using that register as one it can allocate.
6371 // So we build it all by hand.
6372 // Address index(noreg, switch_reg, Address::times_1);
6373 // ArrayAddress dispatch(table, index);
6374 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6375 __ lea($dest$$Register, $constantaddress);
6376 __ jmp(dispatch);
6377 %}
6378 ins_pipe(pipe_jmp);
6379 %}
6380
6381 // Conditional move
6382 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6383 %{
6384 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6385
6386 ins_cost(200); // XXX
6387 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6388 opcode(0x0F, 0x40);
6389 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6390 ins_pipe(pipe_cmov_reg);
6391 %}
6392
6393 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6394 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6395
6396 ins_cost(200); // XXX
6397 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6398 opcode(0x0F, 0x40);
6399 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6400 ins_pipe(pipe_cmov_reg);
6401 %}
6402
6403 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6404 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6405 ins_cost(200);
6406 expand %{
6407 cmovI_regU(cop, cr, dst, src);
6408 %}
6409 %}
6410
6411 // Conditional move
6412 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6413 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6414
6415 ins_cost(250); // XXX
6416 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6417 opcode(0x0F, 0x40);
6418 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6419 ins_pipe(pipe_cmov_mem);
6420 %}
6421
6422 // Conditional move
6423 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6424 %{
6425 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6426
6427 ins_cost(250); // XXX
6428 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6429 opcode(0x0F, 0x40);
6430 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6431 ins_pipe(pipe_cmov_mem);
6432 %}
6433
6434 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6435 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6436 ins_cost(250);
6437 expand %{
6438 cmovI_memU(cop, cr, dst, src);
6439 %}
6440 %}
6441
6442 // Conditional move
6443 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6444 %{
6445 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6446
6447 ins_cost(200); // XXX
6448 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6449 opcode(0x0F, 0x40);
6450 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6451 ins_pipe(pipe_cmov_reg);
6452 %}
6453
6454 // Conditional move
6455 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6456 %{
6457 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6458
6459 ins_cost(200); // XXX
6460 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6461 opcode(0x0F, 0x40);
6462 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6463 ins_pipe(pipe_cmov_reg);
6464 %}
6465
6466 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6467 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6468 ins_cost(200);
6469 expand %{
6470 cmovN_regU(cop, cr, dst, src);
6471 %}
6472 %}
6473
6474 // Conditional move
6475 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6476 %{
6477 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6478
6479 ins_cost(200); // XXX
6480 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6481 opcode(0x0F, 0x40);
6482 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6483 ins_pipe(pipe_cmov_reg); // XXX
6484 %}
6485
6486 // Conditional move
6487 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6488 %{
6489 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6490
6491 ins_cost(200); // XXX
6492 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6493 opcode(0x0F, 0x40);
6494 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6495 ins_pipe(pipe_cmov_reg); // XXX
6496 %}
6497
6498 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6499 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6500 ins_cost(200);
6501 expand %{
6502 cmovP_regU(cop, cr, dst, src);
6503 %}
6504 %}
6505
6506 // DISABLED: Requires the ADLC to emit a bottom_type call that
6507 // correctly meets the two pointer arguments; one is an incoming
6508 // register but the other is a memory operand. ALSO appears to
6509 // be buggy with implicit null checks.
6510 //
6511 //// Conditional move
6512 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6513 //%{
6514 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6515 // ins_cost(250);
6516 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6517 // opcode(0x0F,0x40);
6518 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6519 // ins_pipe( pipe_cmov_mem );
6520 //%}
6521 //
6522 //// Conditional move
6523 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6524 //%{
6525 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6526 // ins_cost(250);
6527 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6528 // opcode(0x0F,0x40);
6529 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6530 // ins_pipe( pipe_cmov_mem );
6531 //%}
6532
6533 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6534 %{
6535 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6536
6537 ins_cost(200); // XXX
6538 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6539 opcode(0x0F, 0x40);
6540 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6541 ins_pipe(pipe_cmov_reg); // XXX
6542 %}
6543
6544 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6545 %{
6546 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6547
6548 ins_cost(200); // XXX
6549 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6550 opcode(0x0F, 0x40);
6551 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6552 ins_pipe(pipe_cmov_mem); // XXX
6553 %}
6554
6555 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6556 %{
6557 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6558
6559 ins_cost(200); // XXX
6560 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6561 opcode(0x0F, 0x40);
6562 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6563 ins_pipe(pipe_cmov_reg); // XXX
6564 %}
6565
6566 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6567 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6568 ins_cost(200);
6569 expand %{
6570 cmovL_regU(cop, cr, dst, src);
6571 %}
6572 %}
6573
6574 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6575 %{
6576 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6577
6578 ins_cost(200); // XXX
6579 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6580 opcode(0x0F, 0x40);
6581 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6582 ins_pipe(pipe_cmov_mem); // XXX
6583 %}
6584
6585 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6586 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6587 ins_cost(200);
6588 expand %{
6589 cmovL_memU(cop, cr, dst, src);
6590 %}
6591 %}
6592
6593 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6594 %{
6595 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6596
6597 ins_cost(200); // XXX
6598 format %{ "jn$cop skip\t# signed cmove float\n\t"
6599 "movss $dst, $src\n"
6600 "skip:" %}
6601 ins_encode %{
6602 Label Lskip;
6603 // Invert sense of branch from sense of CMOV
6604 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6605 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6606 __ bind(Lskip);
6607 %}
6608 ins_pipe(pipe_slow);
6609 %}
6610
6611 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
6612 // %{
6613 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
6614
6615 // ins_cost(200); // XXX
6616 // format %{ "jn$cop skip\t# signed cmove float\n\t"
6617 // "movss $dst, $src\n"
6618 // "skip:" %}
6619 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
6620 // ins_pipe(pipe_slow);
6621 // %}
6622
6623 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6624 %{
6625 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6626
6627 ins_cost(200); // XXX
6628 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6629 "movss $dst, $src\n"
6630 "skip:" %}
6631 ins_encode %{
6632 Label Lskip;
6633 // Invert sense of branch from sense of CMOV
6634 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6635 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6636 __ bind(Lskip);
6637 %}
6638 ins_pipe(pipe_slow);
6639 %}
6640
6641 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6642 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6643 ins_cost(200);
6644 expand %{
6645 cmovF_regU(cop, cr, dst, src);
6646 %}
6647 %}
6648
6649 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6650 %{
6651 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6652
6653 ins_cost(200); // XXX
6654 format %{ "jn$cop skip\t# signed cmove double\n\t"
6655 "movsd $dst, $src\n"
6656 "skip:" %}
6657 ins_encode %{
6658 Label Lskip;
6659 // Invert sense of branch from sense of CMOV
6660 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6661 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6662 __ bind(Lskip);
6663 %}
6664 ins_pipe(pipe_slow);
6665 %}
6666
6667 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6668 %{
6669 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6670
6671 ins_cost(200); // XXX
6672 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6673 "movsd $dst, $src\n"
6674 "skip:" %}
6675 ins_encode %{
6676 Label Lskip;
6677 // Invert sense of branch from sense of CMOV
6678 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6679 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6680 __ bind(Lskip);
6681 %}
6682 ins_pipe(pipe_slow);
6683 %}
6684
6685 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6686 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6687 ins_cost(200);
6688 expand %{
6689 cmovD_regU(cop, cr, dst, src);
6690 %}
6691 %}
6692
6693 //----------Arithmetic Instructions--------------------------------------------
6694 //----------Addition Instructions----------------------------------------------
6695
6696 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6697 %{
6698 match(Set dst (AddI dst src));
6699 effect(KILL cr);
6700
6701 format %{ "addl $dst, $src\t# int" %}
6702 opcode(0x03);
6703 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6704 ins_pipe(ialu_reg_reg);
6705 %}
6706
6707 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6708 %{
6709 match(Set dst (AddI dst src));
6710 effect(KILL cr);
6711
6712 format %{ "addl $dst, $src\t# int" %}
6713 opcode(0x81, 0x00); /* /0 id */
6714 ins_encode(OpcSErm(dst, src), Con8or32(src));
6715 ins_pipe( ialu_reg );
6716 %}
6717
6718 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6719 %{
6720 match(Set dst (AddI dst (LoadI src)));
6721 effect(KILL cr);
6722
6723 ins_cost(125); // XXX
6724 format %{ "addl $dst, $src\t# int" %}
6725 opcode(0x03);
6726 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6727 ins_pipe(ialu_reg_mem);
6728 %}
6729
6730 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6731 %{
6732 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6733 effect(KILL cr);
6734
6735 ins_cost(150); // XXX
6736 format %{ "addl $dst, $src\t# int" %}
6737 opcode(0x01); /* Opcode 01 /r */
6738 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6739 ins_pipe(ialu_mem_reg);
6740 %}
6741
6742 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
6743 %{
6744 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6745 effect(KILL cr);
6746
6747 ins_cost(125); // XXX
6748 format %{ "addl $dst, $src\t# int" %}
6749 opcode(0x81); /* Opcode 81 /0 id */
6750 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
6751 ins_pipe(ialu_mem_imm);
6752 %}
6753
6754 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
6755 %{
6756 predicate(UseIncDec);
6757 match(Set dst (AddI dst src));
6758 effect(KILL cr);
6759
6760 format %{ "incl $dst\t# int" %}
6761 opcode(0xFF, 0x00); // FF /0
6762 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6763 ins_pipe(ialu_reg);
6764 %}
6765
6766 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
6767 %{
6768 predicate(UseIncDec);
6769 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6770 effect(KILL cr);
6771
6772 ins_cost(125); // XXX
6773 format %{ "incl $dst\t# int" %}
6774 opcode(0xFF); /* Opcode FF /0 */
6775 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
6776 ins_pipe(ialu_mem_imm);
6777 %}
6778
6779 // XXX why does that use AddI
6780 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
6781 %{
6782 predicate(UseIncDec);
6783 match(Set dst (AddI dst src));
6784 effect(KILL cr);
6785
6786 format %{ "decl $dst\t# int" %}
6787 opcode(0xFF, 0x01); // FF /1
6788 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6789 ins_pipe(ialu_reg);
6790 %}
6791
6792 // XXX why does that use AddI
6793 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
6794 %{
6795 predicate(UseIncDec);
6796 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6797 effect(KILL cr);
6798
6799 ins_cost(125); // XXX
6800 format %{ "decl $dst\t# int" %}
6801 opcode(0xFF); /* Opcode FF /1 */
6802 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
6803 ins_pipe(ialu_mem_imm);
6804 %}
6805
6806 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
6807 %{
6808 match(Set dst (AddI src0 src1));
6809
6810 ins_cost(110);
6811 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
6812 opcode(0x8D); /* 0x8D /r */
6813 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
6814 ins_pipe(ialu_reg_reg);
6815 %}
6816
6817 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
6818 %{
6819 match(Set dst (AddL dst src));
6820 effect(KILL cr);
6821
6822 format %{ "addq $dst, $src\t# long" %}
6823 opcode(0x03);
6824 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
6825 ins_pipe(ialu_reg_reg);
6826 %}
6827
6828 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
6829 %{
6830 match(Set dst (AddL dst src));
6831 effect(KILL cr);
6832
6833 format %{ "addq $dst, $src\t# long" %}
6834 opcode(0x81, 0x00); /* /0 id */
6835 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
6836 ins_pipe( ialu_reg );
6837 %}
6838
6839 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
6840 %{
6841 match(Set dst (AddL dst (LoadL src)));
6842 effect(KILL cr);
6843
6844 ins_cost(125); // XXX
6845 format %{ "addq $dst, $src\t# long" %}
6846 opcode(0x03);
6847 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6848 ins_pipe(ialu_reg_mem);
6849 %}
6850
6851 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
6852 %{
6853 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6854 effect(KILL cr);
6855
6856 ins_cost(150); // XXX
6857 format %{ "addq $dst, $src\t# long" %}
6858 opcode(0x01); /* Opcode 01 /r */
6859 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6860 ins_pipe(ialu_mem_reg);
6861 %}
6862
6863 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
6864 %{
6865 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6866 effect(KILL cr);
6867
6868 ins_cost(125); // XXX
6869 format %{ "addq $dst, $src\t# long" %}
6870 opcode(0x81); /* Opcode 81 /0 id */
6871 ins_encode(REX_mem_wide(dst),
6872 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
6873 ins_pipe(ialu_mem_imm);
6874 %}
6875
6876 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
6877 %{
6878 predicate(UseIncDec);
6879 match(Set dst (AddL dst src));
6880 effect(KILL cr);
6881
6882 format %{ "incq $dst\t# long" %}
6883 opcode(0xFF, 0x00); // FF /0
6884 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
6885 ins_pipe(ialu_reg);
6886 %}
6887
6888 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
6889 %{
6890 predicate(UseIncDec);
6891 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6892 effect(KILL cr);
6893
6894 ins_cost(125); // XXX
6895 format %{ "incq $dst\t# long" %}
6896 opcode(0xFF); /* Opcode FF /0 */
6897 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
6898 ins_pipe(ialu_mem_imm);
6899 %}
6900
6901 // XXX why does that use AddL
6902 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
6903 %{
6904 predicate(UseIncDec);
6905 match(Set dst (AddL dst src));
6906 effect(KILL cr);
6907
6908 format %{ "decq $dst\t# long" %}
6909 opcode(0xFF, 0x01); // FF /1
6910 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
6911 ins_pipe(ialu_reg);
6912 %}
6913
6914 // XXX why does that use AddL
6915 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
6916 %{
6917 predicate(UseIncDec);
6918 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6919 effect(KILL cr);
6920
6921 ins_cost(125); // XXX
6922 format %{ "decq $dst\t# long" %}
6923 opcode(0xFF); /* Opcode FF /1 */
6924 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
6925 ins_pipe(ialu_mem_imm);
6926 %}
6927
6928 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
6929 %{
6930 match(Set dst (AddL src0 src1));
6931
6932 ins_cost(110);
6933 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
6934 opcode(0x8D); /* 0x8D /r */
6935 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
6936 ins_pipe(ialu_reg_reg);
6937 %}
6938
6939 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
6940 %{
6941 match(Set dst (AddP dst src));
6942 effect(KILL cr);
6943
6944 format %{ "addq $dst, $src\t# ptr" %}
6945 opcode(0x03);
6946 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
6947 ins_pipe(ialu_reg_reg);
6948 %}
6949
6950 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
6951 %{
6952 match(Set dst (AddP dst src));
6953 effect(KILL cr);
6954
6955 format %{ "addq $dst, $src\t# ptr" %}
6956 opcode(0x81, 0x00); /* /0 id */
6957 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
6958 ins_pipe( ialu_reg );
6959 %}
6960
6961 // XXX addP mem ops ????
6962
6963 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
6964 %{
6965 match(Set dst (AddP src0 src1));
6966
6967 ins_cost(110);
6968 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
6969 opcode(0x8D); /* 0x8D /r */
6970 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
6971 ins_pipe(ialu_reg_reg);
6972 %}
6973
6974 instruct checkCastPP(rRegP dst)
6975 %{
6976 match(Set dst (CheckCastPP dst));
6977
6978 size(0);
6979 format %{ "# checkcastPP of $dst" %}
6980 ins_encode(/* empty encoding */);
6981 ins_pipe(empty);
6982 %}
6983
6984 instruct castPP(rRegP dst)
6985 %{
6986 match(Set dst (CastPP dst));
6987
6988 size(0);
6989 format %{ "# castPP of $dst" %}
6990 ins_encode(/* empty encoding */);
6991 ins_pipe(empty);
6992 %}
6993
6994 instruct castII(rRegI dst)
6995 %{
6996 match(Set dst (CastII dst));
6997
6998 size(0);
6999 format %{ "# castII of $dst" %}
7000 ins_encode(/* empty encoding */);
7001 ins_cost(0);
7002 ins_pipe(empty);
7003 %}
7004
7005 // LoadP-locked same as a regular LoadP when used with compare-swap
7006 instruct loadPLocked(rRegP dst, memory mem)
7007 %{
7008 match(Set dst (LoadPLocked mem));
7009
7010 ins_cost(125); // XXX
7011 format %{ "movq $dst, $mem\t# ptr locked" %}
7012 opcode(0x8B);
7013 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7014 ins_pipe(ialu_reg_mem); // XXX
7015 %}
7016
7017 // Conditional-store of the updated heap-top.
7018 // Used during allocation of the shared heap.
7019 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7020
7021 instruct storePConditional(memory heap_top_ptr,
7022 rax_RegP oldval, rRegP newval,
7023 rFlagsReg cr)
7024 %{
7025 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7026
7027 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7028 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7029 opcode(0x0F, 0xB1);
7030 ins_encode(lock_prefix,
7031 REX_reg_mem_wide(newval, heap_top_ptr),
7032 OpcP, OpcS,
7033 reg_mem(newval, heap_top_ptr));
7034 ins_pipe(pipe_cmpxchg);
7035 %}
7036
7037 // Conditional-store of an int value.
7038 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7039 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7040 %{
7041 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7042 effect(KILL oldval);
7043
7044 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7045 opcode(0x0F, 0xB1);
7046 ins_encode(lock_prefix,
7047 REX_reg_mem(newval, mem),
7048 OpcP, OpcS,
7049 reg_mem(newval, mem));
7050 ins_pipe(pipe_cmpxchg);
7051 %}
7052
7053 // Conditional-store of a long value.
7054 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7055 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7056 %{
7057 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7058 effect(KILL oldval);
7059
7060 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7061 opcode(0x0F, 0xB1);
7062 ins_encode(lock_prefix,
7063 REX_reg_mem_wide(newval, mem),
7064 OpcP, OpcS,
7065 reg_mem(newval, mem));
7066 ins_pipe(pipe_cmpxchg);
7067 %}
7068
7069
7070 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7071 instruct compareAndSwapP(rRegI res,
7072 memory mem_ptr,
7073 rax_RegP oldval, rRegP newval,
7074 rFlagsReg cr)
7075 %{
7076 predicate(VM_Version::supports_cx8());
7077 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7078 effect(KILL cr, KILL oldval);
7079
7080 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7081 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7082 "sete $res\n\t"
7083 "movzbl $res, $res" %}
7084 opcode(0x0F, 0xB1);
7085 ins_encode(lock_prefix,
7086 REX_reg_mem_wide(newval, mem_ptr),
7087 OpcP, OpcS,
7088 reg_mem(newval, mem_ptr),
7089 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7090 REX_reg_breg(res, res), // movzbl
7091 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7092 ins_pipe( pipe_cmpxchg );
7093 %}
7094
7095 instruct compareAndSwapL(rRegI res,
7096 memory mem_ptr,
7097 rax_RegL oldval, rRegL newval,
7098 rFlagsReg cr)
7099 %{
7100 predicate(VM_Version::supports_cx8());
7101 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7102 effect(KILL cr, KILL oldval);
7103
7104 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7105 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7106 "sete $res\n\t"
7107 "movzbl $res, $res" %}
7108 opcode(0x0F, 0xB1);
7109 ins_encode(lock_prefix,
7110 REX_reg_mem_wide(newval, mem_ptr),
7111 OpcP, OpcS,
7112 reg_mem(newval, mem_ptr),
7113 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7114 REX_reg_breg(res, res), // movzbl
7115 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7116 ins_pipe( pipe_cmpxchg );
7117 %}
7118
7119 instruct compareAndSwapI(rRegI res,
7120 memory mem_ptr,
7121 rax_RegI oldval, rRegI newval,
7122 rFlagsReg cr)
7123 %{
7124 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7125 effect(KILL cr, KILL oldval);
7126
7127 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7128 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7129 "sete $res\n\t"
7130 "movzbl $res, $res" %}
7131 opcode(0x0F, 0xB1);
7132 ins_encode(lock_prefix,
7133 REX_reg_mem(newval, mem_ptr),
7134 OpcP, OpcS,
7135 reg_mem(newval, mem_ptr),
7136 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7137 REX_reg_breg(res, res), // movzbl
7138 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7139 ins_pipe( pipe_cmpxchg );
7140 %}
7141
7142
7143 instruct compareAndSwapN(rRegI res,
7144 memory mem_ptr,
7145 rax_RegN oldval, rRegN newval,
7146 rFlagsReg cr) %{
7147 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7148 effect(KILL cr, KILL oldval);
7149
7150 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7151 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7152 "sete $res\n\t"
7153 "movzbl $res, $res" %}
7154 opcode(0x0F, 0xB1);
7155 ins_encode(lock_prefix,
7156 REX_reg_mem(newval, mem_ptr),
7157 OpcP, OpcS,
7158 reg_mem(newval, mem_ptr),
7159 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7160 REX_reg_breg(res, res), // movzbl
7161 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7162 ins_pipe( pipe_cmpxchg );
7163 %}
7164
7165 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7166 predicate(n->as_LoadStore()->result_not_used());
7167 match(Set dummy (GetAndAddI mem add));
7168 effect(KILL cr);
7169 format %{ "ADDL [$mem],$add" %}
7170 ins_encode %{
7171 if (os::is_MP()) { __ lock(); }
7172 __ addl($mem$$Address, $add$$constant);
7173 %}
7174 ins_pipe( pipe_cmpxchg );
7175 %}
7176
7177 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7178 match(Set newval (GetAndAddI mem newval));
7179 effect(KILL cr);
7180 format %{ "XADDL [$mem],$newval" %}
7181 ins_encode %{
7182 if (os::is_MP()) { __ lock(); }
7183 __ xaddl($mem$$Address, $newval$$Register);
7184 %}
7185 ins_pipe( pipe_cmpxchg );
7186 %}
7187
7188 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7189 predicate(n->as_LoadStore()->result_not_used());
7190 match(Set dummy (GetAndAddL mem add));
7191 effect(KILL cr);
7192 format %{ "ADDQ [$mem],$add" %}
7193 ins_encode %{
7194 if (os::is_MP()) { __ lock(); }
7195 __ addq($mem$$Address, $add$$constant);
7196 %}
7197 ins_pipe( pipe_cmpxchg );
7198 %}
7199
7200 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7201 match(Set newval (GetAndAddL mem newval));
7202 effect(KILL cr);
7203 format %{ "XADDQ [$mem],$newval" %}
7204 ins_encode %{
7205 if (os::is_MP()) { __ lock(); }
7206 __ xaddq($mem$$Address, $newval$$Register);
7207 %}
7208 ins_pipe( pipe_cmpxchg );
7209 %}
7210
7211 instruct xchgI( memory mem, rRegI newval) %{
7212 match(Set newval (GetAndSetI mem newval));
7213 format %{ "XCHGL $newval,[$mem]" %}
7214 ins_encode %{
7215 __ xchgl($newval$$Register, $mem$$Address);
7216 %}
7217 ins_pipe( pipe_cmpxchg );
7218 %}
7219
7220 instruct xchgL( memory mem, rRegL newval) %{
7221 match(Set newval (GetAndSetL mem newval));
7222 format %{ "XCHGL $newval,[$mem]" %}
7223 ins_encode %{
7224 __ xchgq($newval$$Register, $mem$$Address);
7225 %}
7226 ins_pipe( pipe_cmpxchg );
7227 %}
7228
7229 instruct xchgP( memory mem, rRegP newval) %{
7230 match(Set newval (GetAndSetP mem newval));
7231 format %{ "XCHGQ $newval,[$mem]" %}
7232 ins_encode %{
7233 __ xchgq($newval$$Register, $mem$$Address);
7234 %}
7235 ins_pipe( pipe_cmpxchg );
7236 %}
7237
7238 instruct xchgN( memory mem, rRegN newval) %{
7239 match(Set newval (GetAndSetN mem newval));
7240 format %{ "XCHGL $newval,$mem]" %}
7241 ins_encode %{
7242 __ xchgl($newval$$Register, $mem$$Address);
7243 %}
7244 ins_pipe( pipe_cmpxchg );
7245 %}
7246
7247 //----------Subtraction Instructions-------------------------------------------
7248
7249 // Integer Subtraction Instructions
7250 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7251 %{
7252 match(Set dst (SubI dst src));
7253 effect(KILL cr);
7254
7255 format %{ "subl $dst, $src\t# int" %}
7256 opcode(0x2B);
7257 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7258 ins_pipe(ialu_reg_reg);
7259 %}
7260
7261 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7262 %{
7263 match(Set dst (SubI dst src));
7264 effect(KILL cr);
7265
7266 format %{ "subl $dst, $src\t# int" %}
7267 opcode(0x81, 0x05); /* Opcode 81 /5 */
7268 ins_encode(OpcSErm(dst, src), Con8or32(src));
7269 ins_pipe(ialu_reg);
7270 %}
7271
7272 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7273 %{
7274 match(Set dst (SubI dst (LoadI src)));
7275 effect(KILL cr);
7276
7277 ins_cost(125);
7278 format %{ "subl $dst, $src\t# int" %}
7279 opcode(0x2B);
7280 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7281 ins_pipe(ialu_reg_mem);
7282 %}
7283
7284 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7285 %{
7286 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7287 effect(KILL cr);
7288
7289 ins_cost(150);
7290 format %{ "subl $dst, $src\t# int" %}
7291 opcode(0x29); /* Opcode 29 /r */
7292 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7293 ins_pipe(ialu_mem_reg);
7294 %}
7295
7296 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7297 %{
7298 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7299 effect(KILL cr);
7300
7301 ins_cost(125); // XXX
7302 format %{ "subl $dst, $src\t# int" %}
7303 opcode(0x81); /* Opcode 81 /5 id */
7304 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7305 ins_pipe(ialu_mem_imm);
7306 %}
7307
7308 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7309 %{
7310 match(Set dst (SubL dst src));
7311 effect(KILL cr);
7312
7313 format %{ "subq $dst, $src\t# long" %}
7314 opcode(0x2B);
7315 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7316 ins_pipe(ialu_reg_reg);
7317 %}
7318
7319 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7320 %{
7321 match(Set dst (SubL dst src));
7322 effect(KILL cr);
7323
7324 format %{ "subq $dst, $src\t# long" %}
7325 opcode(0x81, 0x05); /* Opcode 81 /5 */
7326 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7327 ins_pipe(ialu_reg);
7328 %}
7329
7330 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7331 %{
7332 match(Set dst (SubL dst (LoadL src)));
7333 effect(KILL cr);
7334
7335 ins_cost(125);
7336 format %{ "subq $dst, $src\t# long" %}
7337 opcode(0x2B);
7338 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7339 ins_pipe(ialu_reg_mem);
7340 %}
7341
7342 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7343 %{
7344 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7345 effect(KILL cr);
7346
7347 ins_cost(150);
7348 format %{ "subq $dst, $src\t# long" %}
7349 opcode(0x29); /* Opcode 29 /r */
7350 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7351 ins_pipe(ialu_mem_reg);
7352 %}
7353
7354 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7355 %{
7356 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7357 effect(KILL cr);
7358
7359 ins_cost(125); // XXX
7360 format %{ "subq $dst, $src\t# long" %}
7361 opcode(0x81); /* Opcode 81 /5 id */
7362 ins_encode(REX_mem_wide(dst),
7363 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7364 ins_pipe(ialu_mem_imm);
7365 %}
7366
7367 // Subtract from a pointer
7368 // XXX hmpf???
7369 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7370 %{
7371 match(Set dst (AddP dst (SubI zero src)));
7372 effect(KILL cr);
7373
7374 format %{ "subq $dst, $src\t# ptr - int" %}
7375 opcode(0x2B);
7376 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7377 ins_pipe(ialu_reg_reg);
7378 %}
7379
7380 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7381 %{
7382 match(Set dst (SubI zero dst));
7383 effect(KILL cr);
7384
7385 format %{ "negl $dst\t# int" %}
7386 opcode(0xF7, 0x03); // Opcode F7 /3
7387 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7388 ins_pipe(ialu_reg);
7389 %}
7390
7391 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7392 %{
7393 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7394 effect(KILL cr);
7395
7396 format %{ "negl $dst\t# int" %}
7397 opcode(0xF7, 0x03); // Opcode F7 /3
7398 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7399 ins_pipe(ialu_reg);
7400 %}
7401
7402 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7403 %{
7404 match(Set dst (SubL zero dst));
7405 effect(KILL cr);
7406
7407 format %{ "negq $dst\t# long" %}
7408 opcode(0xF7, 0x03); // Opcode F7 /3
7409 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7410 ins_pipe(ialu_reg);
7411 %}
7412
7413 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7414 %{
7415 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7416 effect(KILL cr);
7417
7418 format %{ "negq $dst\t# long" %}
7419 opcode(0xF7, 0x03); // Opcode F7 /3
7420 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7421 ins_pipe(ialu_reg);
7422 %}
7423
7424 //----------Multiplication/Division Instructions-------------------------------
7425 // Integer Multiplication Instructions
7426 // Multiply Register
7427
7428 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7429 %{
7430 match(Set dst (MulI dst src));
7431 effect(KILL cr);
7432
7433 ins_cost(300);
7434 format %{ "imull $dst, $src\t# int" %}
7435 opcode(0x0F, 0xAF);
7436 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7437 ins_pipe(ialu_reg_reg_alu0);
7438 %}
7439
7440 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7441 %{
7442 match(Set dst (MulI src imm));
7443 effect(KILL cr);
7444
7445 ins_cost(300);
7446 format %{ "imull $dst, $src, $imm\t# int" %}
7447 opcode(0x69); /* 69 /r id */
7448 ins_encode(REX_reg_reg(dst, src),
7449 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7450 ins_pipe(ialu_reg_reg_alu0);
7451 %}
7452
7453 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7454 %{
7455 match(Set dst (MulI dst (LoadI src)));
7456 effect(KILL cr);
7457
7458 ins_cost(350);
7459 format %{ "imull $dst, $src\t# int" %}
7460 opcode(0x0F, 0xAF);
7461 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7462 ins_pipe(ialu_reg_mem_alu0);
7463 %}
7464
7465 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7466 %{
7467 match(Set dst (MulI (LoadI src) imm));
7468 effect(KILL cr);
7469
7470 ins_cost(300);
7471 format %{ "imull $dst, $src, $imm\t# int" %}
7472 opcode(0x69); /* 69 /r id */
7473 ins_encode(REX_reg_mem(dst, src),
7474 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7475 ins_pipe(ialu_reg_mem_alu0);
7476 %}
7477
7478 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7479 %{
7480 match(Set dst (MulL dst src));
7481 effect(KILL cr);
7482
7483 ins_cost(300);
7484 format %{ "imulq $dst, $src\t# long" %}
7485 opcode(0x0F, 0xAF);
7486 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7487 ins_pipe(ialu_reg_reg_alu0);
7488 %}
7489
7490 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7491 %{
7492 match(Set dst (MulL src imm));
7493 effect(KILL cr);
7494
7495 ins_cost(300);
7496 format %{ "imulq $dst, $src, $imm\t# long" %}
7497 opcode(0x69); /* 69 /r id */
7498 ins_encode(REX_reg_reg_wide(dst, src),
7499 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7500 ins_pipe(ialu_reg_reg_alu0);
7501 %}
7502
7503 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7504 %{
7505 match(Set dst (MulL dst (LoadL src)));
7506 effect(KILL cr);
7507
7508 ins_cost(350);
7509 format %{ "imulq $dst, $src\t# long" %}
7510 opcode(0x0F, 0xAF);
7511 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
7512 ins_pipe(ialu_reg_mem_alu0);
7513 %}
7514
7515 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7516 %{
7517 match(Set dst (MulL (LoadL src) imm));
7518 effect(KILL cr);
7519
7520 ins_cost(300);
7521 format %{ "imulq $dst, $src, $imm\t# long" %}
7522 opcode(0x69); /* 69 /r id */
7523 ins_encode(REX_reg_mem_wide(dst, src),
7524 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7525 ins_pipe(ialu_reg_mem_alu0);
7526 %}
7527
7528 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7529 %{
7530 match(Set dst (MulHiL src rax));
7531 effect(USE_KILL rax, KILL cr);
7532
7533 ins_cost(300);
7534 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7535 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7536 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7537 ins_pipe(ialu_reg_reg_alu0);
7538 %}
7539
7540 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7541 rFlagsReg cr)
7542 %{
7543 match(Set rax (DivI rax div));
7544 effect(KILL rdx, KILL cr);
7545
7546 ins_cost(30*100+10*100); // XXX
7547 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7548 "jne,s normal\n\t"
7549 "xorl rdx, rdx\n\t"
7550 "cmpl $div, -1\n\t"
7551 "je,s done\n"
7552 "normal: cdql\n\t"
7553 "idivl $div\n"
7554 "done:" %}
7555 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7556 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7557 ins_pipe(ialu_reg_reg_alu0);
7558 %}
7559
7560 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7561 rFlagsReg cr)
7562 %{
7563 match(Set rax (DivL rax div));
7564 effect(KILL rdx, KILL cr);
7565
7566 ins_cost(30*100+10*100); // XXX
7567 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7568 "cmpq rax, rdx\n\t"
7569 "jne,s normal\n\t"
7570 "xorl rdx, rdx\n\t"
7571 "cmpq $div, -1\n\t"
7572 "je,s done\n"
7573 "normal: cdqq\n\t"
7574 "idivq $div\n"
7575 "done:" %}
7576 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7577 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7578 ins_pipe(ialu_reg_reg_alu0);
7579 %}
7580
7581 // Integer DIVMOD with Register, both quotient and mod results
7582 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7583 rFlagsReg cr)
7584 %{
7585 match(DivModI rax div);
7586 effect(KILL cr);
7587
7588 ins_cost(30*100+10*100); // XXX
7589 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7590 "jne,s normal\n\t"
7591 "xorl rdx, rdx\n\t"
7592 "cmpl $div, -1\n\t"
7593 "je,s done\n"
7594 "normal: cdql\n\t"
7595 "idivl $div\n"
7596 "done:" %}
7597 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7598 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7599 ins_pipe(pipe_slow);
7600 %}
7601
7602 // Long DIVMOD with Register, both quotient and mod results
7603 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7604 rFlagsReg cr)
7605 %{
7606 match(DivModL rax div);
7607 effect(KILL cr);
7608
7609 ins_cost(30*100+10*100); // XXX
7610 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7611 "cmpq rax, rdx\n\t"
7612 "jne,s normal\n\t"
7613 "xorl rdx, rdx\n\t"
7614 "cmpq $div, -1\n\t"
7615 "je,s done\n"
7616 "normal: cdqq\n\t"
7617 "idivq $div\n"
7618 "done:" %}
7619 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7620 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7621 ins_pipe(pipe_slow);
7622 %}
7623
7624 //----------- DivL-By-Constant-Expansions--------------------------------------
7625 // DivI cases are handled by the compiler
7626
7627 // Magic constant, reciprocal of 10
7628 instruct loadConL_0x6666666666666667(rRegL dst)
7629 %{
7630 effect(DEF dst);
7631
7632 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
7633 ins_encode(load_immL(dst, 0x6666666666666667));
7634 ins_pipe(ialu_reg);
7635 %}
7636
7637 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7638 %{
7639 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
7640
7641 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
7642 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7643 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7644 ins_pipe(ialu_reg_reg_alu0);
7645 %}
7646
7647 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
7648 %{
7649 effect(USE_DEF dst, KILL cr);
7650
7651 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
7652 opcode(0xC1, 0x7); /* C1 /7 ib */
7653 ins_encode(reg_opc_imm_wide(dst, 0x3F));
7654 ins_pipe(ialu_reg);
7655 %}
7656
7657 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
7658 %{
7659 effect(USE_DEF dst, KILL cr);
7660
7661 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
7662 opcode(0xC1, 0x7); /* C1 /7 ib */
7663 ins_encode(reg_opc_imm_wide(dst, 0x2));
7664 ins_pipe(ialu_reg);
7665 %}
7666
7667 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
7668 %{
7669 match(Set dst (DivL src div));
7670
7671 ins_cost((5+8)*100);
7672 expand %{
7673 rax_RegL rax; // Killed temp
7674 rFlagsReg cr; // Killed
7675 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
7676 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
7677 sarL_rReg_63(src, cr); // sarq src, 63
7678 sarL_rReg_2(dst, cr); // sarq rdx, 2
7679 subL_rReg(dst, src, cr); // subl rdx, src
7680 %}
7681 %}
7682
7683 //-----------------------------------------------------------------------------
7684
7685 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
7686 rFlagsReg cr)
7687 %{
7688 match(Set rdx (ModI rax div));
7689 effect(KILL rax, KILL cr);
7690
7691 ins_cost(300); // XXX
7692 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
7693 "jne,s normal\n\t"
7694 "xorl rdx, rdx\n\t"
7695 "cmpl $div, -1\n\t"
7696 "je,s done\n"
7697 "normal: cdql\n\t"
7698 "idivl $div\n"
7699 "done:" %}
7700 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7701 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7702 ins_pipe(ialu_reg_reg_alu0);
7703 %}
7704
7705 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
7706 rFlagsReg cr)
7707 %{
7708 match(Set rdx (ModL rax div));
7709 effect(KILL rax, KILL cr);
7710
7711 ins_cost(300); // XXX
7712 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
7713 "cmpq rax, rdx\n\t"
7714 "jne,s normal\n\t"
7715 "xorl rdx, rdx\n\t"
7716 "cmpq $div, -1\n\t"
7717 "je,s done\n"
7718 "normal: cdqq\n\t"
7719 "idivq $div\n"
7720 "done:" %}
7721 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7722 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7723 ins_pipe(ialu_reg_reg_alu0);
7724 %}
7725
7726 // Integer Shift Instructions
7727 // Shift Left by one
7728 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7729 %{
7730 match(Set dst (LShiftI dst shift));
7731 effect(KILL cr);
7732
7733 format %{ "sall $dst, $shift" %}
7734 opcode(0xD1, 0x4); /* D1 /4 */
7735 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7736 ins_pipe(ialu_reg);
7737 %}
7738
7739 // Shift Left by one
7740 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7741 %{
7742 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7743 effect(KILL cr);
7744
7745 format %{ "sall $dst, $shift\t" %}
7746 opcode(0xD1, 0x4); /* D1 /4 */
7747 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7748 ins_pipe(ialu_mem_imm);
7749 %}
7750
7751 // Shift Left by 8-bit immediate
7752 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7753 %{
7754 match(Set dst (LShiftI dst shift));
7755 effect(KILL cr);
7756
7757 format %{ "sall $dst, $shift" %}
7758 opcode(0xC1, 0x4); /* C1 /4 ib */
7759 ins_encode(reg_opc_imm(dst, shift));
7760 ins_pipe(ialu_reg);
7761 %}
7762
7763 // Shift Left by 8-bit immediate
7764 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7765 %{
7766 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7767 effect(KILL cr);
7768
7769 format %{ "sall $dst, $shift" %}
7770 opcode(0xC1, 0x4); /* C1 /4 ib */
7771 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
7772 ins_pipe(ialu_mem_imm);
7773 %}
7774
7775 // Shift Left by variable
7776 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
7777 %{
7778 match(Set dst (LShiftI dst shift));
7779 effect(KILL cr);
7780
7781 format %{ "sall $dst, $shift" %}
7782 opcode(0xD3, 0x4); /* D3 /4 */
7783 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7784 ins_pipe(ialu_reg_reg);
7785 %}
7786
7787 // Shift Left by variable
7788 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
7789 %{
7790 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7791 effect(KILL cr);
7792
7793 format %{ "sall $dst, $shift" %}
7794 opcode(0xD3, 0x4); /* D3 /4 */
7795 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7796 ins_pipe(ialu_mem_reg);
7797 %}
7798
7799 // Arithmetic shift right by one
7800 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7801 %{
7802 match(Set dst (RShiftI dst shift));
7803 effect(KILL cr);
7804
7805 format %{ "sarl $dst, $shift" %}
7806 opcode(0xD1, 0x7); /* D1 /7 */
7807 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7808 ins_pipe(ialu_reg);
7809 %}
7810
7811 // Arithmetic shift right by one
7812 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7813 %{
7814 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7815 effect(KILL cr);
7816
7817 format %{ "sarl $dst, $shift" %}
7818 opcode(0xD1, 0x7); /* D1 /7 */
7819 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7820 ins_pipe(ialu_mem_imm);
7821 %}
7822
7823 // Arithmetic Shift Right by 8-bit immediate
7824 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7825 %{
7826 match(Set dst (RShiftI dst shift));
7827 effect(KILL cr);
7828
7829 format %{ "sarl $dst, $shift" %}
7830 opcode(0xC1, 0x7); /* C1 /7 ib */
7831 ins_encode(reg_opc_imm(dst, shift));
7832 ins_pipe(ialu_mem_imm);
7833 %}
7834
7835 // Arithmetic Shift Right by 8-bit immediate
7836 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7837 %{
7838 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7839 effect(KILL cr);
7840
7841 format %{ "sarl $dst, $shift" %}
7842 opcode(0xC1, 0x7); /* C1 /7 ib */
7843 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
7844 ins_pipe(ialu_mem_imm);
7845 %}
7846
7847 // Arithmetic Shift Right by variable
7848 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
7849 %{
7850 match(Set dst (RShiftI dst shift));
7851 effect(KILL cr);
7852
7853 format %{ "sarl $dst, $shift" %}
7854 opcode(0xD3, 0x7); /* D3 /7 */
7855 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7856 ins_pipe(ialu_reg_reg);
7857 %}
7858
7859 // Arithmetic Shift Right by variable
7860 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
7861 %{
7862 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7863 effect(KILL cr);
7864
7865 format %{ "sarl $dst, $shift" %}
7866 opcode(0xD3, 0x7); /* D3 /7 */
7867 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7868 ins_pipe(ialu_mem_reg);
7869 %}
7870
7871 // Logical shift right by one
7872 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7873 %{
7874 match(Set dst (URShiftI dst shift));
7875 effect(KILL cr);
7876
7877 format %{ "shrl $dst, $shift" %}
7878 opcode(0xD1, 0x5); /* D1 /5 */
7879 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7880 ins_pipe(ialu_reg);
7881 %}
7882
7883 // Logical shift right by one
7884 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7885 %{
7886 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
7887 effect(KILL cr);
7888
7889 format %{ "shrl $dst, $shift" %}
7890 opcode(0xD1, 0x5); /* D1 /5 */
7891 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7892 ins_pipe(ialu_mem_imm);
7893 %}
7894
7895 // Logical Shift Right by 8-bit immediate
7896 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7897 %{
7898 match(Set dst (URShiftI dst shift));
7899 effect(KILL cr);
7900
7901 format %{ "shrl $dst, $shift" %}
7902 opcode(0xC1, 0x5); /* C1 /5 ib */
7903 ins_encode(reg_opc_imm(dst, shift));
7904 ins_pipe(ialu_reg);
7905 %}
7906
7907 // Logical Shift Right by 8-bit immediate
7908 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7909 %{
7910 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
7911 effect(KILL cr);
7912
7913 format %{ "shrl $dst, $shift" %}
7914 opcode(0xC1, 0x5); /* C1 /5 ib */
7915 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
7916 ins_pipe(ialu_mem_imm);
7917 %}
7918
7919 // Logical Shift Right by variable
7920 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
7921 %{
7922 match(Set dst (URShiftI dst shift));
7923 effect(KILL cr);
7924
7925 format %{ "shrl $dst, $shift" %}
7926 opcode(0xD3, 0x5); /* D3 /5 */
7927 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7928 ins_pipe(ialu_reg_reg);
7929 %}
7930
7931 // Logical Shift Right by variable
7932 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
7933 %{
7934 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
7935 effect(KILL cr);
7936
7937 format %{ "shrl $dst, $shift" %}
7938 opcode(0xD3, 0x5); /* D3 /5 */
7939 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7940 ins_pipe(ialu_mem_reg);
7941 %}
7942
7943 // Long Shift Instructions
7944 // Shift Left by one
7945 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
7946 %{
7947 match(Set dst (LShiftL dst shift));
7948 effect(KILL cr);
7949
7950 format %{ "salq $dst, $shift" %}
7951 opcode(0xD1, 0x4); /* D1 /4 */
7952 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7953 ins_pipe(ialu_reg);
7954 %}
7955
7956 // Shift Left by one
7957 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7958 %{
7959 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
7960 effect(KILL cr);
7961
7962 format %{ "salq $dst, $shift" %}
7963 opcode(0xD1, 0x4); /* D1 /4 */
7964 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7965 ins_pipe(ialu_mem_imm);
7966 %}
7967
7968 // Shift Left by 8-bit immediate
7969 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
7970 %{
7971 match(Set dst (LShiftL dst shift));
7972 effect(KILL cr);
7973
7974 format %{ "salq $dst, $shift" %}
7975 opcode(0xC1, 0x4); /* C1 /4 ib */
7976 ins_encode(reg_opc_imm_wide(dst, shift));
7977 ins_pipe(ialu_reg);
7978 %}
7979
7980 // Shift Left by 8-bit immediate
7981 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7982 %{
7983 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
7984 effect(KILL cr);
7985
7986 format %{ "salq $dst, $shift" %}
7987 opcode(0xC1, 0x4); /* C1 /4 ib */
7988 ins_encode(REX_mem_wide(dst), OpcP,
7989 RM_opc_mem(secondary, dst), Con8or32(shift));
7990 ins_pipe(ialu_mem_imm);
7991 %}
7992
7993 // Shift Left by variable
7994 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
7995 %{
7996 match(Set dst (LShiftL dst shift));
7997 effect(KILL cr);
7998
7999 format %{ "salq $dst, $shift" %}
8000 opcode(0xD3, 0x4); /* D3 /4 */
8001 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8002 ins_pipe(ialu_reg_reg);
8003 %}
8004
8005 // Shift Left by variable
8006 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8007 %{
8008 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8009 effect(KILL cr);
8010
8011 format %{ "salq $dst, $shift" %}
8012 opcode(0xD3, 0x4); /* D3 /4 */
8013 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8014 ins_pipe(ialu_mem_reg);
8015 %}
8016
8017 // Arithmetic shift right by one
8018 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8019 %{
8020 match(Set dst (RShiftL dst shift));
8021 effect(KILL cr);
8022
8023 format %{ "sarq $dst, $shift" %}
8024 opcode(0xD1, 0x7); /* D1 /7 */
8025 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8026 ins_pipe(ialu_reg);
8027 %}
8028
8029 // Arithmetic shift right by one
8030 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8031 %{
8032 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8033 effect(KILL cr);
8034
8035 format %{ "sarq $dst, $shift" %}
8036 opcode(0xD1, 0x7); /* D1 /7 */
8037 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8038 ins_pipe(ialu_mem_imm);
8039 %}
8040
8041 // Arithmetic Shift Right by 8-bit immediate
8042 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8043 %{
8044 match(Set dst (RShiftL dst shift));
8045 effect(KILL cr);
8046
8047 format %{ "sarq $dst, $shift" %}
8048 opcode(0xC1, 0x7); /* C1 /7 ib */
8049 ins_encode(reg_opc_imm_wide(dst, shift));
8050 ins_pipe(ialu_mem_imm);
8051 %}
8052
8053 // Arithmetic Shift Right by 8-bit immediate
8054 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8055 %{
8056 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8057 effect(KILL cr);
8058
8059 format %{ "sarq $dst, $shift" %}
8060 opcode(0xC1, 0x7); /* C1 /7 ib */
8061 ins_encode(REX_mem_wide(dst), OpcP,
8062 RM_opc_mem(secondary, dst), Con8or32(shift));
8063 ins_pipe(ialu_mem_imm);
8064 %}
8065
8066 // Arithmetic Shift Right by variable
8067 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8068 %{
8069 match(Set dst (RShiftL dst shift));
8070 effect(KILL cr);
8071
8072 format %{ "sarq $dst, $shift" %}
8073 opcode(0xD3, 0x7); /* D3 /7 */
8074 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8075 ins_pipe(ialu_reg_reg);
8076 %}
8077
8078 // Arithmetic Shift Right by variable
8079 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8080 %{
8081 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8082 effect(KILL cr);
8083
8084 format %{ "sarq $dst, $shift" %}
8085 opcode(0xD3, 0x7); /* D3 /7 */
8086 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8087 ins_pipe(ialu_mem_reg);
8088 %}
8089
8090 // Logical shift right by one
8091 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8092 %{
8093 match(Set dst (URShiftL dst shift));
8094 effect(KILL cr);
8095
8096 format %{ "shrq $dst, $shift" %}
8097 opcode(0xD1, 0x5); /* D1 /5 */
8098 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8099 ins_pipe(ialu_reg);
8100 %}
8101
8102 // Logical shift right by one
8103 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8104 %{
8105 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8106 effect(KILL cr);
8107
8108 format %{ "shrq $dst, $shift" %}
8109 opcode(0xD1, 0x5); /* D1 /5 */
8110 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8111 ins_pipe(ialu_mem_imm);
8112 %}
8113
8114 // Logical Shift Right by 8-bit immediate
8115 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8116 %{
8117 match(Set dst (URShiftL dst shift));
8118 effect(KILL cr);
8119
8120 format %{ "shrq $dst, $shift" %}
8121 opcode(0xC1, 0x5); /* C1 /5 ib */
8122 ins_encode(reg_opc_imm_wide(dst, shift));
8123 ins_pipe(ialu_reg);
8124 %}
8125
8126
8127 // Logical Shift Right by 8-bit immediate
8128 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8129 %{
8130 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8131 effect(KILL cr);
8132
8133 format %{ "shrq $dst, $shift" %}
8134 opcode(0xC1, 0x5); /* C1 /5 ib */
8135 ins_encode(REX_mem_wide(dst), OpcP,
8136 RM_opc_mem(secondary, dst), Con8or32(shift));
8137 ins_pipe(ialu_mem_imm);
8138 %}
8139
8140 // Logical Shift Right by variable
8141 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8142 %{
8143 match(Set dst (URShiftL dst shift));
8144 effect(KILL cr);
8145
8146 format %{ "shrq $dst, $shift" %}
8147 opcode(0xD3, 0x5); /* D3 /5 */
8148 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8149 ins_pipe(ialu_reg_reg);
8150 %}
8151
8152 // Logical Shift Right by variable
8153 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8154 %{
8155 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8156 effect(KILL cr);
8157
8158 format %{ "shrq $dst, $shift" %}
8159 opcode(0xD3, 0x5); /* D3 /5 */
8160 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8161 ins_pipe(ialu_mem_reg);
8162 %}
8163
8164 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8165 // This idiom is used by the compiler for the i2b bytecode.
8166 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8167 %{
8168 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8169
8170 format %{ "movsbl $dst, $src\t# i2b" %}
8171 opcode(0x0F, 0xBE);
8172 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8173 ins_pipe(ialu_reg_reg);
8174 %}
8175
8176 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8177 // This idiom is used by the compiler the i2s bytecode.
8178 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8179 %{
8180 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8181
8182 format %{ "movswl $dst, $src\t# i2s" %}
8183 opcode(0x0F, 0xBF);
8184 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8185 ins_pipe(ialu_reg_reg);
8186 %}
8187
8188 // ROL/ROR instructions
8189
8190 // ROL expand
8191 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8192 effect(KILL cr, USE_DEF dst);
8193
8194 format %{ "roll $dst" %}
8195 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8196 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8197 ins_pipe(ialu_reg);
8198 %}
8199
8200 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8201 effect(USE_DEF dst, USE shift, KILL cr);
8202
8203 format %{ "roll $dst, $shift" %}
8204 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8205 ins_encode( reg_opc_imm(dst, shift) );
8206 ins_pipe(ialu_reg);
8207 %}
8208
8209 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8210 %{
8211 effect(USE_DEF dst, USE shift, KILL cr);
8212
8213 format %{ "roll $dst, $shift" %}
8214 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8215 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8216 ins_pipe(ialu_reg_reg);
8217 %}
8218 // end of ROL expand
8219
8220 // Rotate Left by one
8221 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8222 %{
8223 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8224
8225 expand %{
8226 rolI_rReg_imm1(dst, cr);
8227 %}
8228 %}
8229
8230 // Rotate Left by 8-bit immediate
8231 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8232 %{
8233 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8234 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8235
8236 expand %{
8237 rolI_rReg_imm8(dst, lshift, cr);
8238 %}
8239 %}
8240
8241 // Rotate Left by variable
8242 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8243 %{
8244 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8245
8246 expand %{
8247 rolI_rReg_CL(dst, shift, cr);
8248 %}
8249 %}
8250
8251 // Rotate Left by variable
8252 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8253 %{
8254 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8255
8256 expand %{
8257 rolI_rReg_CL(dst, shift, cr);
8258 %}
8259 %}
8260
8261 // ROR expand
8262 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8263 %{
8264 effect(USE_DEF dst, KILL cr);
8265
8266 format %{ "rorl $dst" %}
8267 opcode(0xD1, 0x1); /* D1 /1 */
8268 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8269 ins_pipe(ialu_reg);
8270 %}
8271
8272 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8273 %{
8274 effect(USE_DEF dst, USE shift, KILL cr);
8275
8276 format %{ "rorl $dst, $shift" %}
8277 opcode(0xC1, 0x1); /* C1 /1 ib */
8278 ins_encode(reg_opc_imm(dst, shift));
8279 ins_pipe(ialu_reg);
8280 %}
8281
8282 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8283 %{
8284 effect(USE_DEF dst, USE shift, KILL cr);
8285
8286 format %{ "rorl $dst, $shift" %}
8287 opcode(0xD3, 0x1); /* D3 /1 */
8288 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8289 ins_pipe(ialu_reg_reg);
8290 %}
8291 // end of ROR expand
8292
8293 // Rotate Right by one
8294 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8295 %{
8296 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8297
8298 expand %{
8299 rorI_rReg_imm1(dst, cr);
8300 %}
8301 %}
8302
8303 // Rotate Right by 8-bit immediate
8304 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8305 %{
8306 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8307 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8308
8309 expand %{
8310 rorI_rReg_imm8(dst, rshift, cr);
8311 %}
8312 %}
8313
8314 // Rotate Right by variable
8315 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8316 %{
8317 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8318
8319 expand %{
8320 rorI_rReg_CL(dst, shift, cr);
8321 %}
8322 %}
8323
8324 // Rotate Right by variable
8325 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8326 %{
8327 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8328
8329 expand %{
8330 rorI_rReg_CL(dst, shift, cr);
8331 %}
8332 %}
8333
8334 // for long rotate
8335 // ROL expand
8336 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8337 effect(USE_DEF dst, KILL cr);
8338
8339 format %{ "rolq $dst" %}
8340 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8341 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8342 ins_pipe(ialu_reg);
8343 %}
8344
8345 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8346 effect(USE_DEF dst, USE shift, KILL cr);
8347
8348 format %{ "rolq $dst, $shift" %}
8349 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8350 ins_encode( reg_opc_imm_wide(dst, shift) );
8351 ins_pipe(ialu_reg);
8352 %}
8353
8354 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8355 %{
8356 effect(USE_DEF dst, USE shift, KILL cr);
8357
8358 format %{ "rolq $dst, $shift" %}
8359 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8360 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8361 ins_pipe(ialu_reg_reg);
8362 %}
8363 // end of ROL expand
8364
8365 // Rotate Left by one
8366 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8367 %{
8368 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8369
8370 expand %{
8371 rolL_rReg_imm1(dst, cr);
8372 %}
8373 %}
8374
8375 // Rotate Left by 8-bit immediate
8376 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8377 %{
8378 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8379 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8380
8381 expand %{
8382 rolL_rReg_imm8(dst, lshift, cr);
8383 %}
8384 %}
8385
8386 // Rotate Left by variable
8387 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8388 %{
8389 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8390
8391 expand %{
8392 rolL_rReg_CL(dst, shift, cr);
8393 %}
8394 %}
8395
8396 // Rotate Left by variable
8397 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8398 %{
8399 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8400
8401 expand %{
8402 rolL_rReg_CL(dst, shift, cr);
8403 %}
8404 %}
8405
8406 // ROR expand
8407 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8408 %{
8409 effect(USE_DEF dst, KILL cr);
8410
8411 format %{ "rorq $dst" %}
8412 opcode(0xD1, 0x1); /* D1 /1 */
8413 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8414 ins_pipe(ialu_reg);
8415 %}
8416
8417 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8418 %{
8419 effect(USE_DEF dst, USE shift, KILL cr);
8420
8421 format %{ "rorq $dst, $shift" %}
8422 opcode(0xC1, 0x1); /* C1 /1 ib */
8423 ins_encode(reg_opc_imm_wide(dst, shift));
8424 ins_pipe(ialu_reg);
8425 %}
8426
8427 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8428 %{
8429 effect(USE_DEF dst, USE shift, KILL cr);
8430
8431 format %{ "rorq $dst, $shift" %}
8432 opcode(0xD3, 0x1); /* D3 /1 */
8433 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8434 ins_pipe(ialu_reg_reg);
8435 %}
8436 // end of ROR expand
8437
8438 // Rotate Right by one
8439 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8440 %{
8441 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8442
8443 expand %{
8444 rorL_rReg_imm1(dst, cr);
8445 %}
8446 %}
8447
8448 // Rotate Right by 8-bit immediate
8449 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8450 %{
8451 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8452 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8453
8454 expand %{
8455 rorL_rReg_imm8(dst, rshift, cr);
8456 %}
8457 %}
8458
8459 // Rotate Right by variable
8460 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8461 %{
8462 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8463
8464 expand %{
8465 rorL_rReg_CL(dst, shift, cr);
8466 %}
8467 %}
8468
8469 // Rotate Right by variable
8470 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8471 %{
8472 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8473
8474 expand %{
8475 rorL_rReg_CL(dst, shift, cr);
8476 %}
8477 %}
8478
8479 // Logical Instructions
8480
8481 // Integer Logical Instructions
8482
8483 // And Instructions
8484 // And Register with Register
8485 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8486 %{
8487 match(Set dst (AndI dst src));
8488 effect(KILL cr);
8489
8490 format %{ "andl $dst, $src\t# int" %}
8491 opcode(0x23);
8492 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8493 ins_pipe(ialu_reg_reg);
8494 %}
8495
8496 // And Register with Immediate 255
8497 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
8498 %{
8499 match(Set dst (AndI dst src));
8500
8501 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
8502 opcode(0x0F, 0xB6);
8503 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8504 ins_pipe(ialu_reg);
8505 %}
8506
8507 // And Register with Immediate 255 and promote to long
8508 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8509 %{
8510 match(Set dst (ConvI2L (AndI src mask)));
8511
8512 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8513 opcode(0x0F, 0xB6);
8514 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8515 ins_pipe(ialu_reg);
8516 %}
8517
8518 // And Register with Immediate 65535
8519 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
8520 %{
8521 match(Set dst (AndI dst src));
8522
8523 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
8524 opcode(0x0F, 0xB7);
8525 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8526 ins_pipe(ialu_reg);
8527 %}
8528
8529 // And Register with Immediate 65535 and promote to long
8530 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
8531 %{
8532 match(Set dst (ConvI2L (AndI src mask)));
8533
8534 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
8535 opcode(0x0F, 0xB7);
8536 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8537 ins_pipe(ialu_reg);
8538 %}
8539
8540 // And Register with Immediate
8541 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8542 %{
8543 match(Set dst (AndI dst src));
8544 effect(KILL cr);
8545
8546 format %{ "andl $dst, $src\t# int" %}
8547 opcode(0x81, 0x04); /* Opcode 81 /4 */
8548 ins_encode(OpcSErm(dst, src), Con8or32(src));
8549 ins_pipe(ialu_reg);
8550 %}
8551
8552 // And Register with Memory
8553 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8554 %{
8555 match(Set dst (AndI dst (LoadI src)));
8556 effect(KILL cr);
8557
8558 ins_cost(125);
8559 format %{ "andl $dst, $src\t# int" %}
8560 opcode(0x23);
8561 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8562 ins_pipe(ialu_reg_mem);
8563 %}
8564
8565 // And Memory with Register
8566 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8567 %{
8568 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8569 effect(KILL cr);
8570
8571 ins_cost(150);
8572 format %{ "andl $dst, $src\t# int" %}
8573 opcode(0x21); /* Opcode 21 /r */
8574 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8575 ins_pipe(ialu_mem_reg);
8576 %}
8577
8578 // And Memory with Immediate
8579 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
8580 %{
8581 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8582 effect(KILL cr);
8583
8584 ins_cost(125);
8585 format %{ "andl $dst, $src\t# int" %}
8586 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8587 ins_encode(REX_mem(dst), OpcSE(src),
8588 RM_opc_mem(secondary, dst), Con8or32(src));
8589 ins_pipe(ialu_mem_imm);
8590 %}
8591
8592 // BMI1 instructions
8593 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
8594 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
8595 predicate(UseBMI1Instructions);
8596 effect(KILL cr);
8597
8598 ins_cost(125);
8599 format %{ "andnl $dst, $src1, $src2" %}
8600
8601 ins_encode %{
8602 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
8603 %}
8604 ins_pipe(ialu_reg_mem);
8605 %}
8606
8607 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
8608 match(Set dst (AndI (XorI src1 minus_1) src2));
8609 predicate(UseBMI1Instructions);
8610 effect(KILL cr);
8611
8612 format %{ "andnl $dst, $src1, $src2" %}
8613
8614 ins_encode %{
8615 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
8616 %}
8617 ins_pipe(ialu_reg);
8618 %}
8619
8620 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
8621 match(Set dst (AndI (SubI imm_zero src) src));
8622 predicate(UseBMI1Instructions);
8623 effect(KILL cr);
8624
8625 format %{ "blsil $dst, $src" %}
8626
8627 ins_encode %{
8628 __ blsil($dst$$Register, $src$$Register);
8629 %}
8630 ins_pipe(ialu_reg);
8631 %}
8632
8633 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
8634 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
8635 predicate(UseBMI1Instructions);
8636 effect(KILL cr);
8637
8638 ins_cost(125);
8639 format %{ "blsil $dst, $src" %}
8640
8641 ins_encode %{
8642 __ blsil($dst$$Register, $src$$Address);
8643 %}
8644 ins_pipe(ialu_reg_mem);
8645 %}
8646
8647 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
8648 %{
8649 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
8650 predicate(UseBMI1Instructions);
8651 effect(KILL cr);
8652
8653 ins_cost(125);
8654 format %{ "blsmskl $dst, $src" %}
8655
8656 ins_encode %{
8657 __ blsmskl($dst$$Register, $src$$Address);
8658 %}
8659 ins_pipe(ialu_reg_mem);
8660 %}
8661
8662 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
8663 %{
8664 match(Set dst (XorI (AddI src minus_1) src));
8665 predicate(UseBMI1Instructions);
8666 effect(KILL cr);
8667
8668 format %{ "blsmskl $dst, $src" %}
8669
8670 ins_encode %{
8671 __ blsmskl($dst$$Register, $src$$Register);
8672 %}
8673
8674 ins_pipe(ialu_reg);
8675 %}
8676
8677 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
8678 %{
8679 match(Set dst (AndI (AddI src minus_1) src) );
8680 predicate(UseBMI1Instructions);
8681 effect(KILL cr);
8682
8683 format %{ "blsrl $dst, $src" %}
8684
8685 ins_encode %{
8686 __ blsrl($dst$$Register, $src$$Register);
8687 %}
8688
8689 ins_pipe(ialu_reg_mem);
8690 %}
8691
8692 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
8693 %{
8694 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
8695 predicate(UseBMI1Instructions);
8696 effect(KILL cr);
8697
8698 ins_cost(125);
8699 format %{ "blsrl $dst, $src" %}
8700
8701 ins_encode %{
8702 __ blsrl($dst$$Register, $src$$Address);
8703 %}
8704
8705 ins_pipe(ialu_reg);
8706 %}
8707
8708 // Or Instructions
8709 // Or Register with Register
8710 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8711 %{
8712 match(Set dst (OrI dst src));
8713 effect(KILL cr);
8714
8715 format %{ "orl $dst, $src\t# int" %}
8716 opcode(0x0B);
8717 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8718 ins_pipe(ialu_reg_reg);
8719 %}
8720
8721 // Or Register with Immediate
8722 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8723 %{
8724 match(Set dst (OrI dst src));
8725 effect(KILL cr);
8726
8727 format %{ "orl $dst, $src\t# int" %}
8728 opcode(0x81, 0x01); /* Opcode 81 /1 id */
8729 ins_encode(OpcSErm(dst, src), Con8or32(src));
8730 ins_pipe(ialu_reg);
8731 %}
8732
8733 // Or Register with Memory
8734 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8735 %{
8736 match(Set dst (OrI dst (LoadI src)));
8737 effect(KILL cr);
8738
8739 ins_cost(125);
8740 format %{ "orl $dst, $src\t# int" %}
8741 opcode(0x0B);
8742 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8743 ins_pipe(ialu_reg_mem);
8744 %}
8745
8746 // Or Memory with Register
8747 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8748 %{
8749 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8750 effect(KILL cr);
8751
8752 ins_cost(150);
8753 format %{ "orl $dst, $src\t# int" %}
8754 opcode(0x09); /* Opcode 09 /r */
8755 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8756 ins_pipe(ialu_mem_reg);
8757 %}
8758
8759 // Or Memory with Immediate
8760 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
8761 %{
8762 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8763 effect(KILL cr);
8764
8765 ins_cost(125);
8766 format %{ "orl $dst, $src\t# int" %}
8767 opcode(0x81, 0x1); /* Opcode 81 /1 id */
8768 ins_encode(REX_mem(dst), OpcSE(src),
8769 RM_opc_mem(secondary, dst), Con8or32(src));
8770 ins_pipe(ialu_mem_imm);
8771 %}
8772
8773 // Xor Instructions
8774 // Xor Register with Register
8775 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8776 %{
8777 match(Set dst (XorI dst src));
8778 effect(KILL cr);
8779
8780 format %{ "xorl $dst, $src\t# int" %}
8781 opcode(0x33);
8782 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8783 ins_pipe(ialu_reg_reg);
8784 %}
8785
8786 // Xor Register with Immediate -1
8787 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
8788 match(Set dst (XorI dst imm));
8789
8790 format %{ "not $dst" %}
8791 ins_encode %{
8792 __ notl($dst$$Register);
8793 %}
8794 ins_pipe(ialu_reg);
8795 %}
8796
8797 // Xor Register with Immediate
8798 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8799 %{
8800 match(Set dst (XorI dst src));
8801 effect(KILL cr);
8802
8803 format %{ "xorl $dst, $src\t# int" %}
8804 opcode(0x81, 0x06); /* Opcode 81 /6 id */
8805 ins_encode(OpcSErm(dst, src), Con8or32(src));
8806 ins_pipe(ialu_reg);
8807 %}
8808
8809 // Xor Register with Memory
8810 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8811 %{
8812 match(Set dst (XorI dst (LoadI src)));
8813 effect(KILL cr);
8814
8815 ins_cost(125);
8816 format %{ "xorl $dst, $src\t# int" %}
8817 opcode(0x33);
8818 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8819 ins_pipe(ialu_reg_mem);
8820 %}
8821
8822 // Xor Memory with Register
8823 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8824 %{
8825 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8826 effect(KILL cr);
8827
8828 ins_cost(150);
8829 format %{ "xorl $dst, $src\t# int" %}
8830 opcode(0x31); /* Opcode 31 /r */
8831 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8832 ins_pipe(ialu_mem_reg);
8833 %}
8834
8835 // Xor Memory with Immediate
8836 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
8837 %{
8838 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8839 effect(KILL cr);
8840
8841 ins_cost(125);
8842 format %{ "xorl $dst, $src\t# int" %}
8843 opcode(0x81, 0x6); /* Opcode 81 /6 id */
8844 ins_encode(REX_mem(dst), OpcSE(src),
8845 RM_opc_mem(secondary, dst), Con8or32(src));
8846 ins_pipe(ialu_mem_imm);
8847 %}
8848
8849
8850 // Long Logical Instructions
8851
8852 // And Instructions
8853 // And Register with Register
8854 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8855 %{
8856 match(Set dst (AndL dst src));
8857 effect(KILL cr);
8858
8859 format %{ "andq $dst, $src\t# long" %}
8860 opcode(0x23);
8861 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8862 ins_pipe(ialu_reg_reg);
8863 %}
8864
8865 // And Register with Immediate 255
8866 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
8867 %{
8868 match(Set dst (AndL dst src));
8869
8870 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
8871 opcode(0x0F, 0xB6);
8872 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8873 ins_pipe(ialu_reg);
8874 %}
8875
8876 // And Register with Immediate 65535
8877 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
8878 %{
8879 match(Set dst (AndL dst src));
8880
8881 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
8882 opcode(0x0F, 0xB7);
8883 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8884 ins_pipe(ialu_reg);
8885 %}
8886
8887 // And Register with Immediate
8888 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
8889 %{
8890 match(Set dst (AndL dst src));
8891 effect(KILL cr);
8892
8893 format %{ "andq $dst, $src\t# long" %}
8894 opcode(0x81, 0x04); /* Opcode 81 /4 */
8895 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8896 ins_pipe(ialu_reg);
8897 %}
8898
8899 // And Register with Memory
8900 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8901 %{
8902 match(Set dst (AndL dst (LoadL src)));
8903 effect(KILL cr);
8904
8905 ins_cost(125);
8906 format %{ "andq $dst, $src\t# long" %}
8907 opcode(0x23);
8908 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8909 ins_pipe(ialu_reg_mem);
8910 %}
8911
8912 // And Memory with Register
8913 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8914 %{
8915 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
8916 effect(KILL cr);
8917
8918 ins_cost(150);
8919 format %{ "andq $dst, $src\t# long" %}
8920 opcode(0x21); /* Opcode 21 /r */
8921 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8922 ins_pipe(ialu_mem_reg);
8923 %}
8924
8925 // And Memory with Immediate
8926 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8927 %{
8928 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
8929 effect(KILL cr);
8930
8931 ins_cost(125);
8932 format %{ "andq $dst, $src\t# long" %}
8933 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8934 ins_encode(REX_mem_wide(dst), OpcSE(src),
8935 RM_opc_mem(secondary, dst), Con8or32(src));
8936 ins_pipe(ialu_mem_imm);
8937 %}
8938
8939 // BMI1 instructions
8940 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
8941 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
8942 predicate(UseBMI1Instructions);
8943 effect(KILL cr);
8944
8945 ins_cost(125);
8946 format %{ "andnq $dst, $src1, $src2" %}
8947
8948 ins_encode %{
8949 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
8950 %}
8951 ins_pipe(ialu_reg_mem);
8952 %}
8953
8954 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
8955 match(Set dst (AndL (XorL src1 minus_1) src2));
8956 predicate(UseBMI1Instructions);
8957 effect(KILL cr);
8958
8959 format %{ "andnq $dst, $src1, $src2" %}
8960
8961 ins_encode %{
8962 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
8963 %}
8964 ins_pipe(ialu_reg_mem);
8965 %}
8966
8967 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
8968 match(Set dst (AndL (SubL imm_zero src) src));
8969 predicate(UseBMI1Instructions);
8970 effect(KILL cr);
8971
8972 format %{ "blsiq $dst, $src" %}
8973
8974 ins_encode %{
8975 __ blsiq($dst$$Register, $src$$Register);
8976 %}
8977 ins_pipe(ialu_reg);
8978 %}
8979
8980 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
8981 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
8982 predicate(UseBMI1Instructions);
8983 effect(KILL cr);
8984
8985 ins_cost(125);
8986 format %{ "blsiq $dst, $src" %}
8987
8988 ins_encode %{
8989 __ blsiq($dst$$Register, $src$$Address);
8990 %}
8991 ins_pipe(ialu_reg_mem);
8992 %}
8993
8994 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
8995 %{
8996 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
8997 predicate(UseBMI1Instructions);
8998 effect(KILL cr);
8999
9000 ins_cost(125);
9001 format %{ "blsmskq $dst, $src" %}
9002
9003 ins_encode %{
9004 __ blsmskq($dst$$Register, $src$$Address);
9005 %}
9006 ins_pipe(ialu_reg_mem);
9007 %}
9008
9009 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9010 %{
9011 match(Set dst (XorL (AddL src minus_1) src));
9012 predicate(UseBMI1Instructions);
9013 effect(KILL cr);
9014
9015 format %{ "blsmskq $dst, $src" %}
9016
9017 ins_encode %{
9018 __ blsmskq($dst$$Register, $src$$Register);
9019 %}
9020
9021 ins_pipe(ialu_reg);
9022 %}
9023
9024 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9025 %{
9026 match(Set dst (AndL (AddL src minus_1) src) );
9027 predicate(UseBMI1Instructions);
9028 effect(KILL cr);
9029
9030 format %{ "blsrq $dst, $src" %}
9031
9032 ins_encode %{
9033 __ blsrq($dst$$Register, $src$$Register);
9034 %}
9035
9036 ins_pipe(ialu_reg);
9037 %}
9038
9039 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9040 %{
9041 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9042 predicate(UseBMI1Instructions);
9043 effect(KILL cr);
9044
9045 ins_cost(125);
9046 format %{ "blsrq $dst, $src" %}
9047
9048 ins_encode %{
9049 __ blsrq($dst$$Register, $src$$Address);
9050 %}
9051
9052 ins_pipe(ialu_reg);
9053 %}
9054
9055 // Or Instructions
9056 // Or Register with Register
9057 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9058 %{
9059 match(Set dst (OrL dst src));
9060 effect(KILL cr);
9061
9062 format %{ "orq $dst, $src\t# long" %}
9063 opcode(0x0B);
9064 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9065 ins_pipe(ialu_reg_reg);
9066 %}
9067
9068 // Use any_RegP to match R15 (TLS register) without spilling.
9069 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9070 match(Set dst (OrL dst (CastP2X src)));
9071 effect(KILL cr);
9072
9073 format %{ "orq $dst, $src\t# long" %}
9074 opcode(0x0B);
9075 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9076 ins_pipe(ialu_reg_reg);
9077 %}
9078
9079
9080 // Or Register with Immediate
9081 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9082 %{
9083 match(Set dst (OrL dst src));
9084 effect(KILL cr);
9085
9086 format %{ "orq $dst, $src\t# long" %}
9087 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9088 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9089 ins_pipe(ialu_reg);
9090 %}
9091
9092 // Or Register with Memory
9093 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9094 %{
9095 match(Set dst (OrL dst (LoadL src)));
9096 effect(KILL cr);
9097
9098 ins_cost(125);
9099 format %{ "orq $dst, $src\t# long" %}
9100 opcode(0x0B);
9101 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9102 ins_pipe(ialu_reg_mem);
9103 %}
9104
9105 // Or Memory with Register
9106 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9107 %{
9108 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9109 effect(KILL cr);
9110
9111 ins_cost(150);
9112 format %{ "orq $dst, $src\t# long" %}
9113 opcode(0x09); /* Opcode 09 /r */
9114 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9115 ins_pipe(ialu_mem_reg);
9116 %}
9117
9118 // Or Memory with Immediate
9119 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9120 %{
9121 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9122 effect(KILL cr);
9123
9124 ins_cost(125);
9125 format %{ "orq $dst, $src\t# long" %}
9126 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9127 ins_encode(REX_mem_wide(dst), OpcSE(src),
9128 RM_opc_mem(secondary, dst), Con8or32(src));
9129 ins_pipe(ialu_mem_imm);
9130 %}
9131
9132 // Xor Instructions
9133 // Xor Register with Register
9134 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9135 %{
9136 match(Set dst (XorL dst src));
9137 effect(KILL cr);
9138
9139 format %{ "xorq $dst, $src\t# long" %}
9140 opcode(0x33);
9141 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9142 ins_pipe(ialu_reg_reg);
9143 %}
9144
9145 // Xor Register with Immediate -1
9146 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9147 match(Set dst (XorL dst imm));
9148
9149 format %{ "notq $dst" %}
9150 ins_encode %{
9151 __ notq($dst$$Register);
9152 %}
9153 ins_pipe(ialu_reg);
9154 %}
9155
9156 // Xor Register with Immediate
9157 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9158 %{
9159 match(Set dst (XorL dst src));
9160 effect(KILL cr);
9161
9162 format %{ "xorq $dst, $src\t# long" %}
9163 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9164 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9165 ins_pipe(ialu_reg);
9166 %}
9167
9168 // Xor Register with Memory
9169 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9170 %{
9171 match(Set dst (XorL dst (LoadL src)));
9172 effect(KILL cr);
9173
9174 ins_cost(125);
9175 format %{ "xorq $dst, $src\t# long" %}
9176 opcode(0x33);
9177 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9178 ins_pipe(ialu_reg_mem);
9179 %}
9180
9181 // Xor Memory with Register
9182 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9183 %{
9184 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9185 effect(KILL cr);
9186
9187 ins_cost(150);
9188 format %{ "xorq $dst, $src\t# long" %}
9189 opcode(0x31); /* Opcode 31 /r */
9190 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9191 ins_pipe(ialu_mem_reg);
9192 %}
9193
9194 // Xor Memory with Immediate
9195 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9196 %{
9197 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9198 effect(KILL cr);
9199
9200 ins_cost(125);
9201 format %{ "xorq $dst, $src\t# long" %}
9202 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9203 ins_encode(REX_mem_wide(dst), OpcSE(src),
9204 RM_opc_mem(secondary, dst), Con8or32(src));
9205 ins_pipe(ialu_mem_imm);
9206 %}
9207
9208 // Convert Int to Boolean
9209 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9210 %{
9211 match(Set dst (Conv2B src));
9212 effect(KILL cr);
9213
9214 format %{ "testl $src, $src\t# ci2b\n\t"
9215 "setnz $dst\n\t"
9216 "movzbl $dst, $dst" %}
9217 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9218 setNZ_reg(dst),
9219 REX_reg_breg(dst, dst), // movzbl
9220 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9221 ins_pipe(pipe_slow); // XXX
9222 %}
9223
9224 // Convert Pointer to Boolean
9225 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9226 %{
9227 match(Set dst (Conv2B src));
9228 effect(KILL cr);
9229
9230 format %{ "testq $src, $src\t# cp2b\n\t"
9231 "setnz $dst\n\t"
9232 "movzbl $dst, $dst" %}
9233 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9234 setNZ_reg(dst),
9235 REX_reg_breg(dst, dst), // movzbl
9236 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9237 ins_pipe(pipe_slow); // XXX
9238 %}
9239
9240 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9241 %{
9242 match(Set dst (CmpLTMask p q));
9243 effect(KILL cr);
9244
9245 ins_cost(400);
9246 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9247 "setlt $dst\n\t"
9248 "movzbl $dst, $dst\n\t"
9249 "negl $dst" %}
9250 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9251 setLT_reg(dst),
9252 REX_reg_breg(dst, dst), // movzbl
9253 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9254 neg_reg(dst));
9255 ins_pipe(pipe_slow);
9256 %}
9257
9258 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9259 %{
9260 match(Set dst (CmpLTMask dst zero));
9261 effect(KILL cr);
9262
9263 ins_cost(100);
9264 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9265 ins_encode %{
9266 __ sarl($dst$$Register, 31);
9267 %}
9268 ins_pipe(ialu_reg);
9269 %}
9270
9271 /* Better to save a register than avoid a branch */
9272 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9273 %{
9274 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9275 effect(KILL cr);
9276 ins_cost(300);
9277 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
9278 "jge done\n\t"
9279 "addl $p,$y\n"
9280 "done: " %}
9281 ins_encode %{
9282 Register Rp = $p$$Register;
9283 Register Rq = $q$$Register;
9284 Register Ry = $y$$Register;
9285 Label done;
9286 __ subl(Rp, Rq);
9287 __ jccb(Assembler::greaterEqual, done);
9288 __ addl(Rp, Ry);
9289 __ bind(done);
9290 %}
9291 ins_pipe(pipe_cmplt);
9292 %}
9293
9294 /* Better to save a register than avoid a branch */
9295 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9296 %{
9297 match(Set y (AndI (CmpLTMask p q) y));
9298 effect(KILL cr);
9299
9300 ins_cost(300);
9301
9302 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
9303 "jlt done\n\t"
9304 "xorl $y, $y\n"
9305 "done: " %}
9306 ins_encode %{
9307 Register Rp = $p$$Register;
9308 Register Rq = $q$$Register;
9309 Register Ry = $y$$Register;
9310 Label done;
9311 __ cmpl(Rp, Rq);
9312 __ jccb(Assembler::less, done);
9313 __ xorl(Ry, Ry);
9314 __ bind(done);
9315 %}
9316 ins_pipe(pipe_cmplt);
9317 %}
9318
9319
9320 //---------- FP Instructions------------------------------------------------
9321
9322 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9323 %{
9324 match(Set cr (CmpF src1 src2));
9325
9326 ins_cost(145);
9327 format %{ "ucomiss $src1, $src2\n\t"
9328 "jnp,s exit\n\t"
9329 "pushfq\t# saw NaN, set CF\n\t"
9330 "andq [rsp], #0xffffff2b\n\t"
9331 "popfq\n"
9332 "exit:" %}
9333 ins_encode %{
9334 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9335 emit_cmpfp_fixup(_masm);
9336 %}
9337 ins_pipe(pipe_slow);
9338 %}
9339
9340 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9341 match(Set cr (CmpF src1 src2));
9342
9343 ins_cost(100);
9344 format %{ "ucomiss $src1, $src2" %}
9345 ins_encode %{
9346 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9347 %}
9348 ins_pipe(pipe_slow);
9349 %}
9350
9351 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9352 %{
9353 match(Set cr (CmpF src1 (LoadF src2)));
9354
9355 ins_cost(145);
9356 format %{ "ucomiss $src1, $src2\n\t"
9357 "jnp,s exit\n\t"
9358 "pushfq\t# saw NaN, set CF\n\t"
9359 "andq [rsp], #0xffffff2b\n\t"
9360 "popfq\n"
9361 "exit:" %}
9362 ins_encode %{
9363 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9364 emit_cmpfp_fixup(_masm);
9365 %}
9366 ins_pipe(pipe_slow);
9367 %}
9368
9369 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9370 match(Set cr (CmpF src1 (LoadF src2)));
9371
9372 ins_cost(100);
9373 format %{ "ucomiss $src1, $src2" %}
9374 ins_encode %{
9375 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9376 %}
9377 ins_pipe(pipe_slow);
9378 %}
9379
9380 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9381 match(Set cr (CmpF src con));
9382
9383 ins_cost(145);
9384 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9385 "jnp,s exit\n\t"
9386 "pushfq\t# saw NaN, set CF\n\t"
9387 "andq [rsp], #0xffffff2b\n\t"
9388 "popfq\n"
9389 "exit:" %}
9390 ins_encode %{
9391 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9392 emit_cmpfp_fixup(_masm);
9393 %}
9394 ins_pipe(pipe_slow);
9395 %}
9396
9397 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9398 match(Set cr (CmpF src con));
9399 ins_cost(100);
9400 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9401 ins_encode %{
9402 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9403 %}
9404 ins_pipe(pipe_slow);
9405 %}
9406
9407 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9408 %{
9409 match(Set cr (CmpD src1 src2));
9410
9411 ins_cost(145);
9412 format %{ "ucomisd $src1, $src2\n\t"
9413 "jnp,s exit\n\t"
9414 "pushfq\t# saw NaN, set CF\n\t"
9415 "andq [rsp], #0xffffff2b\n\t"
9416 "popfq\n"
9417 "exit:" %}
9418 ins_encode %{
9419 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9420 emit_cmpfp_fixup(_masm);
9421 %}
9422 ins_pipe(pipe_slow);
9423 %}
9424
9425 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9426 match(Set cr (CmpD src1 src2));
9427
9428 ins_cost(100);
9429 format %{ "ucomisd $src1, $src2 test" %}
9430 ins_encode %{
9431 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9432 %}
9433 ins_pipe(pipe_slow);
9434 %}
9435
9436 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9437 %{
9438 match(Set cr (CmpD src1 (LoadD src2)));
9439
9440 ins_cost(145);
9441 format %{ "ucomisd $src1, $src2\n\t"
9442 "jnp,s exit\n\t"
9443 "pushfq\t# saw NaN, set CF\n\t"
9444 "andq [rsp], #0xffffff2b\n\t"
9445 "popfq\n"
9446 "exit:" %}
9447 ins_encode %{
9448 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9449 emit_cmpfp_fixup(_masm);
9450 %}
9451 ins_pipe(pipe_slow);
9452 %}
9453
9454 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9455 match(Set cr (CmpD src1 (LoadD src2)));
9456
9457 ins_cost(100);
9458 format %{ "ucomisd $src1, $src2" %}
9459 ins_encode %{
9460 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9461 %}
9462 ins_pipe(pipe_slow);
9463 %}
9464
9465 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9466 match(Set cr (CmpD src con));
9467
9468 ins_cost(145);
9469 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9470 "jnp,s exit\n\t"
9471 "pushfq\t# saw NaN, set CF\n\t"
9472 "andq [rsp], #0xffffff2b\n\t"
9473 "popfq\n"
9474 "exit:" %}
9475 ins_encode %{
9476 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9477 emit_cmpfp_fixup(_masm);
9478 %}
9479 ins_pipe(pipe_slow);
9480 %}
9481
9482 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9483 match(Set cr (CmpD src con));
9484 ins_cost(100);
9485 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9486 ins_encode %{
9487 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9488 %}
9489 ins_pipe(pipe_slow);
9490 %}
9491
9492 // Compare into -1,0,1
9493 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9494 %{
9495 match(Set dst (CmpF3 src1 src2));
9496 effect(KILL cr);
9497
9498 ins_cost(275);
9499 format %{ "ucomiss $src1, $src2\n\t"
9500 "movl $dst, #-1\n\t"
9501 "jp,s done\n\t"
9502 "jb,s done\n\t"
9503 "setne $dst\n\t"
9504 "movzbl $dst, $dst\n"
9505 "done:" %}
9506 ins_encode %{
9507 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9508 emit_cmpfp3(_masm, $dst$$Register);
9509 %}
9510 ins_pipe(pipe_slow);
9511 %}
9512
9513 // Compare into -1,0,1
9514 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9515 %{
9516 match(Set dst (CmpF3 src1 (LoadF src2)));
9517 effect(KILL cr);
9518
9519 ins_cost(275);
9520 format %{ "ucomiss $src1, $src2\n\t"
9521 "movl $dst, #-1\n\t"
9522 "jp,s done\n\t"
9523 "jb,s done\n\t"
9524 "setne $dst\n\t"
9525 "movzbl $dst, $dst\n"
9526 "done:" %}
9527 ins_encode %{
9528 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9529 emit_cmpfp3(_masm, $dst$$Register);
9530 %}
9531 ins_pipe(pipe_slow);
9532 %}
9533
9534 // Compare into -1,0,1
9535 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9536 match(Set dst (CmpF3 src con));
9537 effect(KILL cr);
9538
9539 ins_cost(275);
9540 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9541 "movl $dst, #-1\n\t"
9542 "jp,s done\n\t"
9543 "jb,s done\n\t"
9544 "setne $dst\n\t"
9545 "movzbl $dst, $dst\n"
9546 "done:" %}
9547 ins_encode %{
9548 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9549 emit_cmpfp3(_masm, $dst$$Register);
9550 %}
9551 ins_pipe(pipe_slow);
9552 %}
9553
9554 // Compare into -1,0,1
9555 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9556 %{
9557 match(Set dst (CmpD3 src1 src2));
9558 effect(KILL cr);
9559
9560 ins_cost(275);
9561 format %{ "ucomisd $src1, $src2\n\t"
9562 "movl $dst, #-1\n\t"
9563 "jp,s done\n\t"
9564 "jb,s done\n\t"
9565 "setne $dst\n\t"
9566 "movzbl $dst, $dst\n"
9567 "done:" %}
9568 ins_encode %{
9569 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9570 emit_cmpfp3(_masm, $dst$$Register);
9571 %}
9572 ins_pipe(pipe_slow);
9573 %}
9574
9575 // Compare into -1,0,1
9576 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
9577 %{
9578 match(Set dst (CmpD3 src1 (LoadD src2)));
9579 effect(KILL cr);
9580
9581 ins_cost(275);
9582 format %{ "ucomisd $src1, $src2\n\t"
9583 "movl $dst, #-1\n\t"
9584 "jp,s done\n\t"
9585 "jb,s done\n\t"
9586 "setne $dst\n\t"
9587 "movzbl $dst, $dst\n"
9588 "done:" %}
9589 ins_encode %{
9590 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9591 emit_cmpfp3(_masm, $dst$$Register);
9592 %}
9593 ins_pipe(pipe_slow);
9594 %}
9595
9596 // Compare into -1,0,1
9597 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
9598 match(Set dst (CmpD3 src con));
9599 effect(KILL cr);
9600
9601 ins_cost(275);
9602 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9603 "movl $dst, #-1\n\t"
9604 "jp,s done\n\t"
9605 "jb,s done\n\t"
9606 "setne $dst\n\t"
9607 "movzbl $dst, $dst\n"
9608 "done:" %}
9609 ins_encode %{
9610 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9611 emit_cmpfp3(_masm, $dst$$Register);
9612 %}
9613 ins_pipe(pipe_slow);
9614 %}
9615
9616 // -----------Trig and Trancendental Instructions------------------------------
9617 instruct cosD_reg(regD dst) %{
9618 match(Set dst (CosD dst));
9619
9620 format %{ "dcos $dst\n\t" %}
9621 opcode(0xD9, 0xFF);
9622 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9623 ins_pipe( pipe_slow );
9624 %}
9625
9626 instruct sinD_reg(regD dst) %{
9627 match(Set dst (SinD dst));
9628
9629 format %{ "dsin $dst\n\t" %}
9630 opcode(0xD9, 0xFE);
9631 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9632 ins_pipe( pipe_slow );
9633 %}
9634
9635 instruct tanD_reg(regD dst) %{
9636 match(Set dst (TanD dst));
9637
9638 format %{ "dtan $dst\n\t" %}
9639 ins_encode( Push_SrcXD(dst),
9640 Opcode(0xD9), Opcode(0xF2), //fptan
9641 Opcode(0xDD), Opcode(0xD8), //fstp st
9642 Push_ResultXD(dst) );
9643 ins_pipe( pipe_slow );
9644 %}
9645
9646 instruct log10D_reg(regD dst) %{
9647 // The source and result Double operands in XMM registers
9648 match(Set dst (Log10D dst));
9649 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9650 // fyl2x ; compute log_10(2) * log_2(x)
9651 format %{ "fldlg2\t\t\t#Log10\n\t"
9652 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
9653 %}
9654 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
9655 Push_SrcXD(dst),
9656 Opcode(0xD9), Opcode(0xF1), // fyl2x
9657 Push_ResultXD(dst));
9658
9659 ins_pipe( pipe_slow );
9660 %}
9661
9662 instruct logD_reg(regD dst) %{
9663 // The source and result Double operands in XMM registers
9664 match(Set dst (LogD dst));
9665 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9666 // fyl2x ; compute log_e(2) * log_2(x)
9667 format %{ "fldln2\t\t\t#Log_e\n\t"
9668 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
9669 %}
9670 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9671 Push_SrcXD(dst),
9672 Opcode(0xD9), Opcode(0xF1), // fyl2x
9673 Push_ResultXD(dst));
9674 ins_pipe( pipe_slow );
9675 %}
9676
9677 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9678 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9679 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9680 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9681 ins_encode %{
9682 __ subptr(rsp, 8);
9683 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9684 __ fld_d(Address(rsp, 0));
9685 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9686 __ fld_d(Address(rsp, 0));
9687 __ fast_pow();
9688 __ fstp_d(Address(rsp, 0));
9689 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9690 __ addptr(rsp, 8);
9691 %}
9692 ins_pipe( pipe_slow );
9693 %}
9694
9695 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9696 match(Set dst (ExpD src));
9697 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9698 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9699 ins_encode %{
9700 __ subptr(rsp, 8);
9701 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9702 __ fld_d(Address(rsp, 0));
9703 __ fast_exp();
9704 __ fstp_d(Address(rsp, 0));
9705 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9706 __ addptr(rsp, 8);
9707 %}
9708 ins_pipe( pipe_slow );
9709 %}
9710
9711 //----------Arithmetic Conversion Instructions---------------------------------
9712
9713 instruct roundFloat_nop(regF dst)
9714 %{
9715 match(Set dst (RoundFloat dst));
9716
9717 ins_cost(0);
9718 ins_encode();
9719 ins_pipe(empty);
9720 %}
9721
9722 instruct roundDouble_nop(regD dst)
9723 %{
9724 match(Set dst (RoundDouble dst));
9725
9726 ins_cost(0);
9727 ins_encode();
9728 ins_pipe(empty);
9729 %}
9730
9731 instruct convF2D_reg_reg(regD dst, regF src)
9732 %{
9733 match(Set dst (ConvF2D src));
9734
9735 format %{ "cvtss2sd $dst, $src" %}
9736 ins_encode %{
9737 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
9738 %}
9739 ins_pipe(pipe_slow); // XXX
9740 %}
9741
9742 instruct convF2D_reg_mem(regD dst, memory src)
9743 %{
9744 match(Set dst (ConvF2D (LoadF src)));
9745
9746 format %{ "cvtss2sd $dst, $src" %}
9747 ins_encode %{
9748 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
9749 %}
9750 ins_pipe(pipe_slow); // XXX
9751 %}
9752
9753 instruct convD2F_reg_reg(regF dst, regD src)
9754 %{
9755 match(Set dst (ConvD2F src));
9756
9757 format %{ "cvtsd2ss $dst, $src" %}
9758 ins_encode %{
9759 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
9760 %}
9761 ins_pipe(pipe_slow); // XXX
9762 %}
9763
9764 instruct convD2F_reg_mem(regF dst, memory src)
9765 %{
9766 match(Set dst (ConvD2F (LoadD src)));
9767
9768 format %{ "cvtsd2ss $dst, $src" %}
9769 ins_encode %{
9770 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
9771 %}
9772 ins_pipe(pipe_slow); // XXX
9773 %}
9774
9775 // XXX do mem variants
9776 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
9777 %{
9778 match(Set dst (ConvF2I src));
9779 effect(KILL cr);
9780
9781 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
9782 "cmpl $dst, #0x80000000\n\t"
9783 "jne,s done\n\t"
9784 "subq rsp, #8\n\t"
9785 "movss [rsp], $src\n\t"
9786 "call f2i_fixup\n\t"
9787 "popq $dst\n"
9788 "done: "%}
9789 ins_encode %{
9790 Label done;
9791 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
9792 __ cmpl($dst$$Register, 0x80000000);
9793 __ jccb(Assembler::notEqual, done);
9794 __ subptr(rsp, 8);
9795 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9796 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9797 __ pop($dst$$Register);
9798 __ bind(done);
9799 %}
9800 ins_pipe(pipe_slow);
9801 %}
9802
9803 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
9804 %{
9805 match(Set dst (ConvF2L src));
9806 effect(KILL cr);
9807
9808 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
9809 "cmpq $dst, [0x8000000000000000]\n\t"
9810 "jne,s done\n\t"
9811 "subq rsp, #8\n\t"
9812 "movss [rsp], $src\n\t"
9813 "call f2l_fixup\n\t"
9814 "popq $dst\n"
9815 "done: "%}
9816 ins_encode %{
9817 Label done;
9818 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
9819 __ cmp64($dst$$Register,
9820 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9821 __ jccb(Assembler::notEqual, done);
9822 __ subptr(rsp, 8);
9823 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9824 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
9825 __ pop($dst$$Register);
9826 __ bind(done);
9827 %}
9828 ins_pipe(pipe_slow);
9829 %}
9830
9831 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
9832 %{
9833 match(Set dst (ConvD2I src));
9834 effect(KILL cr);
9835
9836 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
9837 "cmpl $dst, #0x80000000\n\t"
9838 "jne,s done\n\t"
9839 "subq rsp, #8\n\t"
9840 "movsd [rsp], $src\n\t"
9841 "call d2i_fixup\n\t"
9842 "popq $dst\n"
9843 "done: "%}
9844 ins_encode %{
9845 Label done;
9846 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
9847 __ cmpl($dst$$Register, 0x80000000);
9848 __ jccb(Assembler::notEqual, done);
9849 __ subptr(rsp, 8);
9850 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9851 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
9852 __ pop($dst$$Register);
9853 __ bind(done);
9854 %}
9855 ins_pipe(pipe_slow);
9856 %}
9857
9858 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
9859 %{
9860 match(Set dst (ConvD2L src));
9861 effect(KILL cr);
9862
9863 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
9864 "cmpq $dst, [0x8000000000000000]\n\t"
9865 "jne,s done\n\t"
9866 "subq rsp, #8\n\t"
9867 "movsd [rsp], $src\n\t"
9868 "call d2l_fixup\n\t"
9869 "popq $dst\n"
9870 "done: "%}
9871 ins_encode %{
9872 Label done;
9873 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
9874 __ cmp64($dst$$Register,
9875 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9876 __ jccb(Assembler::notEqual, done);
9877 __ subptr(rsp, 8);
9878 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9879 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
9880 __ pop($dst$$Register);
9881 __ bind(done);
9882 %}
9883 ins_pipe(pipe_slow);
9884 %}
9885
9886 instruct convI2F_reg_reg(regF dst, rRegI src)
9887 %{
9888 predicate(!UseXmmI2F);
9889 match(Set dst (ConvI2F src));
9890
9891 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
9892 ins_encode %{
9893 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
9894 %}
9895 ins_pipe(pipe_slow); // XXX
9896 %}
9897
9898 instruct convI2F_reg_mem(regF dst, memory src)
9899 %{
9900 match(Set dst (ConvI2F (LoadI src)));
9901
9902 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
9903 ins_encode %{
9904 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
9905 %}
9906 ins_pipe(pipe_slow); // XXX
9907 %}
9908
9909 instruct convI2D_reg_reg(regD dst, rRegI src)
9910 %{
9911 predicate(!UseXmmI2D);
9912 match(Set dst (ConvI2D src));
9913
9914 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
9915 ins_encode %{
9916 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
9917 %}
9918 ins_pipe(pipe_slow); // XXX
9919 %}
9920
9921 instruct convI2D_reg_mem(regD dst, memory src)
9922 %{
9923 match(Set dst (ConvI2D (LoadI src)));
9924
9925 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
9926 ins_encode %{
9927 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
9928 %}
9929 ins_pipe(pipe_slow); // XXX
9930 %}
9931
9932 instruct convXI2F_reg(regF dst, rRegI src)
9933 %{
9934 predicate(UseXmmI2F);
9935 match(Set dst (ConvI2F src));
9936
9937 format %{ "movdl $dst, $src\n\t"
9938 "cvtdq2psl $dst, $dst\t# i2f" %}
9939 ins_encode %{
9940 __ movdl($dst$$XMMRegister, $src$$Register);
9941 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
9942 %}
9943 ins_pipe(pipe_slow); // XXX
9944 %}
9945
9946 instruct convXI2D_reg(regD dst, rRegI src)
9947 %{
9948 predicate(UseXmmI2D);
9949 match(Set dst (ConvI2D src));
9950
9951 format %{ "movdl $dst, $src\n\t"
9952 "cvtdq2pdl $dst, $dst\t# i2d" %}
9953 ins_encode %{
9954 __ movdl($dst$$XMMRegister, $src$$Register);
9955 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
9956 %}
9957 ins_pipe(pipe_slow); // XXX
9958 %}
9959
9960 instruct convL2F_reg_reg(regF dst, rRegL src)
9961 %{
9962 match(Set dst (ConvL2F src));
9963
9964 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
9965 ins_encode %{
9966 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
9967 %}
9968 ins_pipe(pipe_slow); // XXX
9969 %}
9970
9971 instruct convL2F_reg_mem(regF dst, memory src)
9972 %{
9973 match(Set dst (ConvL2F (LoadL src)));
9974
9975 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
9976 ins_encode %{
9977 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
9978 %}
9979 ins_pipe(pipe_slow); // XXX
9980 %}
9981
9982 instruct convL2D_reg_reg(regD dst, rRegL src)
9983 %{
9984 match(Set dst (ConvL2D src));
9985
9986 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
9987 ins_encode %{
9988 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
9989 %}
9990 ins_pipe(pipe_slow); // XXX
9991 %}
9992
9993 instruct convL2D_reg_mem(regD dst, memory src)
9994 %{
9995 match(Set dst (ConvL2D (LoadL src)));
9996
9997 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
9998 ins_encode %{
9999 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10000 %}
10001 ins_pipe(pipe_slow); // XXX
10002 %}
10003
10004 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10005 %{
10006 match(Set dst (ConvI2L src));
10007
10008 ins_cost(125);
10009 format %{ "movslq $dst, $src\t# i2l" %}
10010 ins_encode %{
10011 __ movslq($dst$$Register, $src$$Register);
10012 %}
10013 ins_pipe(ialu_reg_reg);
10014 %}
10015
10016 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10017 // %{
10018 // match(Set dst (ConvI2L src));
10019 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10020 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10021 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10022 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10023 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10024 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10025
10026 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10027 // ins_encode(enc_copy(dst, src));
10028 // // opcode(0x63); // needs REX.W
10029 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10030 // ins_pipe(ialu_reg_reg);
10031 // %}
10032
10033 // Zero-extend convert int to long
10034 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10035 %{
10036 match(Set dst (AndL (ConvI2L src) mask));
10037
10038 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10039 ins_encode %{
10040 if ($dst$$reg != $src$$reg) {
10041 __ movl($dst$$Register, $src$$Register);
10042 }
10043 %}
10044 ins_pipe(ialu_reg_reg);
10045 %}
10046
10047 // Zero-extend convert int to long
10048 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10049 %{
10050 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10051
10052 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10053 ins_encode %{
10054 __ movl($dst$$Register, $src$$Address);
10055 %}
10056 ins_pipe(ialu_reg_mem);
10057 %}
10058
10059 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10060 %{
10061 match(Set dst (AndL src mask));
10062
10063 format %{ "movl $dst, $src\t# zero-extend long" %}
10064 ins_encode %{
10065 __ movl($dst$$Register, $src$$Register);
10066 %}
10067 ins_pipe(ialu_reg_reg);
10068 %}
10069
10070 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10071 %{
10072 match(Set dst (ConvL2I src));
10073
10074 format %{ "movl $dst, $src\t# l2i" %}
10075 ins_encode %{
10076 __ movl($dst$$Register, $src$$Register);
10077 %}
10078 ins_pipe(ialu_reg_reg);
10079 %}
10080
10081
10082 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10083 match(Set dst (MoveF2I src));
10084 effect(DEF dst, USE src);
10085
10086 ins_cost(125);
10087 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10088 ins_encode %{
10089 __ movl($dst$$Register, Address(rsp, $src$$disp));
10090 %}
10091 ins_pipe(ialu_reg_mem);
10092 %}
10093
10094 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10095 match(Set dst (MoveI2F src));
10096 effect(DEF dst, USE src);
10097
10098 ins_cost(125);
10099 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10100 ins_encode %{
10101 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10102 %}
10103 ins_pipe(pipe_slow);
10104 %}
10105
10106 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10107 match(Set dst (MoveD2L src));
10108 effect(DEF dst, USE src);
10109
10110 ins_cost(125);
10111 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10112 ins_encode %{
10113 __ movq($dst$$Register, Address(rsp, $src$$disp));
10114 %}
10115 ins_pipe(ialu_reg_mem);
10116 %}
10117
10118 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10119 predicate(!UseXmmLoadAndClearUpper);
10120 match(Set dst (MoveL2D src));
10121 effect(DEF dst, USE src);
10122
10123 ins_cost(125);
10124 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10125 ins_encode %{
10126 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10127 %}
10128 ins_pipe(pipe_slow);
10129 %}
10130
10131 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10132 predicate(UseXmmLoadAndClearUpper);
10133 match(Set dst (MoveL2D src));
10134 effect(DEF dst, USE src);
10135
10136 ins_cost(125);
10137 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10138 ins_encode %{
10139 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10140 %}
10141 ins_pipe(pipe_slow);
10142 %}
10143
10144
10145 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10146 match(Set dst (MoveF2I src));
10147 effect(DEF dst, USE src);
10148
10149 ins_cost(95); // XXX
10150 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10151 ins_encode %{
10152 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10153 %}
10154 ins_pipe(pipe_slow);
10155 %}
10156
10157 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10158 match(Set dst (MoveI2F src));
10159 effect(DEF dst, USE src);
10160
10161 ins_cost(100);
10162 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10163 ins_encode %{
10164 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10165 %}
10166 ins_pipe( ialu_mem_reg );
10167 %}
10168
10169 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10170 match(Set dst (MoveD2L src));
10171 effect(DEF dst, USE src);
10172
10173 ins_cost(95); // XXX
10174 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10175 ins_encode %{
10176 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10177 %}
10178 ins_pipe(pipe_slow);
10179 %}
10180
10181 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10182 match(Set dst (MoveL2D src));
10183 effect(DEF dst, USE src);
10184
10185 ins_cost(100);
10186 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10187 ins_encode %{
10188 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10189 %}
10190 ins_pipe(ialu_mem_reg);
10191 %}
10192
10193 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10194 match(Set dst (MoveF2I src));
10195 effect(DEF dst, USE src);
10196 ins_cost(85);
10197 format %{ "movd $dst,$src\t# MoveF2I" %}
10198 ins_encode %{
10199 __ movdl($dst$$Register, $src$$XMMRegister);
10200 %}
10201 ins_pipe( pipe_slow );
10202 %}
10203
10204 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10205 match(Set dst (MoveD2L src));
10206 effect(DEF dst, USE src);
10207 ins_cost(85);
10208 format %{ "movd $dst,$src\t# MoveD2L" %}
10209 ins_encode %{
10210 __ movdq($dst$$Register, $src$$XMMRegister);
10211 %}
10212 ins_pipe( pipe_slow );
10213 %}
10214
10215 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10216 match(Set dst (MoveI2F src));
10217 effect(DEF dst, USE src);
10218 ins_cost(100);
10219 format %{ "movd $dst,$src\t# MoveI2F" %}
10220 ins_encode %{
10221 __ movdl($dst$$XMMRegister, $src$$Register);
10222 %}
10223 ins_pipe( pipe_slow );
10224 %}
10225
10226 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10227 match(Set dst (MoveL2D src));
10228 effect(DEF dst, USE src);
10229 ins_cost(100);
10230 format %{ "movd $dst,$src\t# MoveL2D" %}
10231 ins_encode %{
10232 __ movdq($dst$$XMMRegister, $src$$Register);
10233 %}
10234 ins_pipe( pipe_slow );
10235 %}
10236
10237
10238 // =======================================================================
10239 // fast clearing of an array
10240 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10241 rFlagsReg cr)
10242 %{
10243 predicate(!UseFastStosb);
10244 match(Set dummy (ClearArray cnt base));
10245 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10246
10247 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10248 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
10249 ins_encode %{
10250 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10251 %}
10252 ins_pipe(pipe_slow);
10253 %}
10254
10255 instruct rep_fast_stosb(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10256 rFlagsReg cr)
10257 %{
10258 predicate(UseFastStosb);
10259 match(Set dummy (ClearArray cnt base));
10260 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10261 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10262 "shlq rcx,3\t# Convert doublewords to bytes\n\t"
10263 "rep stosb\t# Store rax to *rdi++ while rcx--" %}
10264 ins_encode %{
10265 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10266 %}
10267 ins_pipe( pipe_slow );
10268 %}
10269
10270 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10271 rax_RegI result, regD tmp1, rFlagsReg cr)
10272 %{
10273 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10274 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10275
10276 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10277 ins_encode %{
10278 __ string_compare($str1$$Register, $str2$$Register,
10279 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10280 $tmp1$$XMMRegister);
10281 %}
10282 ins_pipe( pipe_slow );
10283 %}
10284
10285 // fast search of substring with known size.
10286 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10287 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10288 %{
10289 predicate(UseSSE42Intrinsics);
10290 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10291 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10292
10293 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10294 ins_encode %{
10295 int icnt2 = (int)$int_cnt2$$constant;
10296 if (icnt2 >= 8) {
10297 // IndexOf for constant substrings with size >= 8 elements
10298 // which don't need to be loaded through stack.
10299 __ string_indexofC8($str1$$Register, $str2$$Register,
10300 $cnt1$$Register, $cnt2$$Register,
10301 icnt2, $result$$Register,
10302 $vec$$XMMRegister, $tmp$$Register);
10303 } else {
10304 // Small strings are loaded through stack if they cross page boundary.
10305 __ string_indexof($str1$$Register, $str2$$Register,
10306 $cnt1$$Register, $cnt2$$Register,
10307 icnt2, $result$$Register,
10308 $vec$$XMMRegister, $tmp$$Register);
10309 }
10310 %}
10311 ins_pipe( pipe_slow );
10312 %}
10313
10314 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10315 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10316 %{
10317 predicate(UseSSE42Intrinsics);
10318 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10319 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10320
10321 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10322 ins_encode %{
10323 __ string_indexof($str1$$Register, $str2$$Register,
10324 $cnt1$$Register, $cnt2$$Register,
10325 (-1), $result$$Register,
10326 $vec$$XMMRegister, $tmp$$Register);
10327 %}
10328 ins_pipe( pipe_slow );
10329 %}
10330
10331 // fast string equals
10332 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10333 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10334 %{
10335 match(Set result (StrEquals (Binary str1 str2) cnt));
10336 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10337
10338 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10339 ins_encode %{
10340 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
10341 $cnt$$Register, $result$$Register, $tmp3$$Register,
10342 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10343 %}
10344 ins_pipe( pipe_slow );
10345 %}
10346
10347 // fast array equals
10348 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10349 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10350 %{
10351 match(Set result (AryEq ary1 ary2));
10352 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10353 //ins_cost(300);
10354
10355 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10356 ins_encode %{
10357 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
10358 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10359 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10360 %}
10361 ins_pipe( pipe_slow );
10362 %}
10363
10364 // encode char[] to byte[] in ISO_8859_1
10365 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10366 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10367 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10368 match(Set result (EncodeISOArray src (Binary dst len)));
10369 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10370
10371 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10372 ins_encode %{
10373 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10374 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10375 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10376 %}
10377 ins_pipe( pipe_slow );
10378 %}
10379
10380 //----------Overflow Math Instructions-----------------------------------------
10381
10382 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10383 %{
10384 match(Set cr (OverflowAddI op1 op2));
10385 effect(DEF cr, USE_KILL op1, USE op2);
10386
10387 format %{ "addl $op1, $op2\t# overflow check int" %}
10388
10389 ins_encode %{
10390 __ addl($op1$$Register, $op2$$Register);
10391 %}
10392 ins_pipe(ialu_reg_reg);
10393 %}
10394
10395 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10396 %{
10397 match(Set cr (OverflowAddI op1 op2));
10398 effect(DEF cr, USE_KILL op1, USE op2);
10399
10400 format %{ "addl $op1, $op2\t# overflow check int" %}
10401
10402 ins_encode %{
10403 __ addl($op1$$Register, $op2$$constant);
10404 %}
10405 ins_pipe(ialu_reg_reg);
10406 %}
10407
10408 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10409 %{
10410 match(Set cr (OverflowAddL op1 op2));
10411 effect(DEF cr, USE_KILL op1, USE op2);
10412
10413 format %{ "addq $op1, $op2\t# overflow check long" %}
10414 ins_encode %{
10415 __ addq($op1$$Register, $op2$$Register);
10416 %}
10417 ins_pipe(ialu_reg_reg);
10418 %}
10419
10420 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
10421 %{
10422 match(Set cr (OverflowAddL op1 op2));
10423 effect(DEF cr, USE_KILL op1, USE op2);
10424
10425 format %{ "addq $op1, $op2\t# overflow check long" %}
10426 ins_encode %{
10427 __ addq($op1$$Register, $op2$$constant);
10428 %}
10429 ins_pipe(ialu_reg_reg);
10430 %}
10431
10432 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10433 %{
10434 match(Set cr (OverflowSubI op1 op2));
10435
10436 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10437 ins_encode %{
10438 __ cmpl($op1$$Register, $op2$$Register);
10439 %}
10440 ins_pipe(ialu_reg_reg);
10441 %}
10442
10443 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10444 %{
10445 match(Set cr (OverflowSubI op1 op2));
10446
10447 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10448 ins_encode %{
10449 __ cmpl($op1$$Register, $op2$$constant);
10450 %}
10451 ins_pipe(ialu_reg_reg);
10452 %}
10453
10454 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10455 %{
10456 match(Set cr (OverflowSubL op1 op2));
10457
10458 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10459 ins_encode %{
10460 __ cmpq($op1$$Register, $op2$$Register);
10461 %}
10462 ins_pipe(ialu_reg_reg);
10463 %}
10464
10465 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10466 %{
10467 match(Set cr (OverflowSubL op1 op2));
10468
10469 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10470 ins_encode %{
10471 __ cmpq($op1$$Register, $op2$$constant);
10472 %}
10473 ins_pipe(ialu_reg_reg);
10474 %}
10475
10476 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
10477 %{
10478 match(Set cr (OverflowSubI zero op2));
10479 effect(DEF cr, USE_KILL op2);
10480
10481 format %{ "negl $op2\t# overflow check int" %}
10482 ins_encode %{
10483 __ negl($op2$$Register);
10484 %}
10485 ins_pipe(ialu_reg_reg);
10486 %}
10487
10488 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
10489 %{
10490 match(Set cr (OverflowSubL zero op2));
10491 effect(DEF cr, USE_KILL op2);
10492
10493 format %{ "negq $op2\t# overflow check long" %}
10494 ins_encode %{
10495 __ negq($op2$$Register);
10496 %}
10497 ins_pipe(ialu_reg_reg);
10498 %}
10499
10500 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10501 %{
10502 match(Set cr (OverflowMulI op1 op2));
10503 effect(DEF cr, USE_KILL op1, USE op2);
10504
10505 format %{ "imull $op1, $op2\t# overflow check int" %}
10506 ins_encode %{
10507 __ imull($op1$$Register, $op2$$Register);
10508 %}
10509 ins_pipe(ialu_reg_reg_alu0);
10510 %}
10511
10512 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
10513 %{
10514 match(Set cr (OverflowMulI op1 op2));
10515 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10516
10517 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
10518 ins_encode %{
10519 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
10520 %}
10521 ins_pipe(ialu_reg_reg_alu0);
10522 %}
10523
10524 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10525 %{
10526 match(Set cr (OverflowMulL op1 op2));
10527 effect(DEF cr, USE_KILL op1, USE op2);
10528
10529 format %{ "imulq $op1, $op2\t# overflow check long" %}
10530 ins_encode %{
10531 __ imulq($op1$$Register, $op2$$Register);
10532 %}
10533 ins_pipe(ialu_reg_reg_alu0);
10534 %}
10535
10536 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
10537 %{
10538 match(Set cr (OverflowMulL op1 op2));
10539 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10540
10541 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
10542 ins_encode %{
10543 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
10544 %}
10545 ins_pipe(ialu_reg_reg_alu0);
10546 %}
10547
10548
10549 //----------Control Flow Instructions------------------------------------------
10550 // Signed compare Instructions
10551
10552 // XXX more variants!!
10553 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10554 %{
10555 match(Set cr (CmpI op1 op2));
10556 effect(DEF cr, USE op1, USE op2);
10557
10558 format %{ "cmpl $op1, $op2" %}
10559 opcode(0x3B); /* Opcode 3B /r */
10560 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10561 ins_pipe(ialu_cr_reg_reg);
10562 %}
10563
10564 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10565 %{
10566 match(Set cr (CmpI op1 op2));
10567
10568 format %{ "cmpl $op1, $op2" %}
10569 opcode(0x81, 0x07); /* Opcode 81 /7 */
10570 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10571 ins_pipe(ialu_cr_reg_imm);
10572 %}
10573
10574 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
10575 %{
10576 match(Set cr (CmpI op1 (LoadI op2)));
10577
10578 ins_cost(500); // XXX
10579 format %{ "cmpl $op1, $op2" %}
10580 opcode(0x3B); /* Opcode 3B /r */
10581 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10582 ins_pipe(ialu_cr_reg_mem);
10583 %}
10584
10585 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
10586 %{
10587 match(Set cr (CmpI src zero));
10588
10589 format %{ "testl $src, $src" %}
10590 opcode(0x85);
10591 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10592 ins_pipe(ialu_cr_reg_imm);
10593 %}
10594
10595 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
10596 %{
10597 match(Set cr (CmpI (AndI src con) zero));
10598
10599 format %{ "testl $src, $con" %}
10600 opcode(0xF7, 0x00);
10601 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
10602 ins_pipe(ialu_cr_reg_imm);
10603 %}
10604
10605 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
10606 %{
10607 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
10608
10609 format %{ "testl $src, $mem" %}
10610 opcode(0x85);
10611 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
10612 ins_pipe(ialu_cr_reg_mem);
10613 %}
10614
10615 // Unsigned compare Instructions; really, same as signed except they
10616 // produce an rFlagsRegU instead of rFlagsReg.
10617 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
10618 %{
10619 match(Set cr (CmpU op1 op2));
10620
10621 format %{ "cmpl $op1, $op2\t# unsigned" %}
10622 opcode(0x3B); /* Opcode 3B /r */
10623 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10624 ins_pipe(ialu_cr_reg_reg);
10625 %}
10626
10627 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
10628 %{
10629 match(Set cr (CmpU op1 op2));
10630
10631 format %{ "cmpl $op1, $op2\t# unsigned" %}
10632 opcode(0x81,0x07); /* Opcode 81 /7 */
10633 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10634 ins_pipe(ialu_cr_reg_imm);
10635 %}
10636
10637 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
10638 %{
10639 match(Set cr (CmpU op1 (LoadI op2)));
10640
10641 ins_cost(500); // XXX
10642 format %{ "cmpl $op1, $op2\t# unsigned" %}
10643 opcode(0x3B); /* Opcode 3B /r */
10644 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10645 ins_pipe(ialu_cr_reg_mem);
10646 %}
10647
10648 // // // Cisc-spilled version of cmpU_rReg
10649 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
10650 // //%{
10651 // // match(Set cr (CmpU (LoadI op1) op2));
10652 // //
10653 // // format %{ "CMPu $op1,$op2" %}
10654 // // ins_cost(500);
10655 // // opcode(0x39); /* Opcode 39 /r */
10656 // // ins_encode( OpcP, reg_mem( op1, op2) );
10657 // //%}
10658
10659 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
10660 %{
10661 match(Set cr (CmpU src zero));
10662
10663 format %{ "testl $src, $src\t# unsigned" %}
10664 opcode(0x85);
10665 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10666 ins_pipe(ialu_cr_reg_imm);
10667 %}
10668
10669 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
10670 %{
10671 match(Set cr (CmpP op1 op2));
10672
10673 format %{ "cmpq $op1, $op2\t# ptr" %}
10674 opcode(0x3B); /* Opcode 3B /r */
10675 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10676 ins_pipe(ialu_cr_reg_reg);
10677 %}
10678
10679 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
10680 %{
10681 match(Set cr (CmpP op1 (LoadP op2)));
10682
10683 ins_cost(500); // XXX
10684 format %{ "cmpq $op1, $op2\t# ptr" %}
10685 opcode(0x3B); /* Opcode 3B /r */
10686 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10687 ins_pipe(ialu_cr_reg_mem);
10688 %}
10689
10690 // // // Cisc-spilled version of cmpP_rReg
10691 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
10692 // //%{
10693 // // match(Set cr (CmpP (LoadP op1) op2));
10694 // //
10695 // // format %{ "CMPu $op1,$op2" %}
10696 // // ins_cost(500);
10697 // // opcode(0x39); /* Opcode 39 /r */
10698 // // ins_encode( OpcP, reg_mem( op1, op2) );
10699 // //%}
10700
10701 // XXX this is generalized by compP_rReg_mem???
10702 // Compare raw pointer (used in out-of-heap check).
10703 // Only works because non-oop pointers must be raw pointers
10704 // and raw pointers have no anti-dependencies.
10705 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
10706 %{
10707 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
10708 match(Set cr (CmpP op1 (LoadP op2)));
10709
10710 format %{ "cmpq $op1, $op2\t# raw ptr" %}
10711 opcode(0x3B); /* Opcode 3B /r */
10712 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10713 ins_pipe(ialu_cr_reg_mem);
10714 %}
10715
10716 // This will generate a signed flags result. This should be OK since
10717 // any compare to a zero should be eq/neq.
10718 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
10719 %{
10720 match(Set cr (CmpP src zero));
10721
10722 format %{ "testq $src, $src\t# ptr" %}
10723 opcode(0x85);
10724 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10725 ins_pipe(ialu_cr_reg_imm);
10726 %}
10727
10728 // This will generate a signed flags result. This should be OK since
10729 // any compare to a zero should be eq/neq.
10730 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
10731 %{
10732 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
10733 match(Set cr (CmpP (LoadP op) zero));
10734
10735 ins_cost(500); // XXX
10736 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
10737 opcode(0xF7); /* Opcode F7 /0 */
10738 ins_encode(REX_mem_wide(op),
10739 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
10740 ins_pipe(ialu_cr_reg_imm);
10741 %}
10742
10743 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
10744 %{
10745 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
10746 match(Set cr (CmpP (LoadP mem) zero));
10747
10748 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
10749 ins_encode %{
10750 __ cmpq(r12, $mem$$Address);
10751 %}
10752 ins_pipe(ialu_cr_reg_mem);
10753 %}
10754
10755 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
10756 %{
10757 match(Set cr (CmpN op1 op2));
10758
10759 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10760 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
10761 ins_pipe(ialu_cr_reg_reg);
10762 %}
10763
10764 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
10765 %{
10766 match(Set cr (CmpN src (LoadN mem)));
10767
10768 format %{ "cmpl $src, $mem\t# compressed ptr" %}
10769 ins_encode %{
10770 __ cmpl($src$$Register, $mem$$Address);
10771 %}
10772 ins_pipe(ialu_cr_reg_mem);
10773 %}
10774
10775 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
10776 match(Set cr (CmpN op1 op2));
10777
10778 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10779 ins_encode %{
10780 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
10781 %}
10782 ins_pipe(ialu_cr_reg_imm);
10783 %}
10784
10785 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
10786 %{
10787 match(Set cr (CmpN src (LoadN mem)));
10788
10789 format %{ "cmpl $mem, $src\t# compressed ptr" %}
10790 ins_encode %{
10791 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
10792 %}
10793 ins_pipe(ialu_cr_reg_mem);
10794 %}
10795
10796 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
10797 match(Set cr (CmpN op1 op2));
10798
10799 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
10800 ins_encode %{
10801 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
10802 %}
10803 ins_pipe(ialu_cr_reg_imm);
10804 %}
10805
10806 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
10807 %{
10808 match(Set cr (CmpN src (LoadNKlass mem)));
10809
10810 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
10811 ins_encode %{
10812 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
10813 %}
10814 ins_pipe(ialu_cr_reg_mem);
10815 %}
10816
10817 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
10818 match(Set cr (CmpN src zero));
10819
10820 format %{ "testl $src, $src\t# compressed ptr" %}
10821 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
10822 ins_pipe(ialu_cr_reg_imm);
10823 %}
10824
10825 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
10826 %{
10827 predicate(Universe::narrow_oop_base() != NULL);
10828 match(Set cr (CmpN (LoadN mem) zero));
10829
10830 ins_cost(500); // XXX
10831 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
10832 ins_encode %{
10833 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
10834 %}
10835 ins_pipe(ialu_cr_reg_mem);
10836 %}
10837
10838 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
10839 %{
10840 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
10841 match(Set cr (CmpN (LoadN mem) zero));
10842
10843 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
10844 ins_encode %{
10845 __ cmpl(r12, $mem$$Address);
10846 %}
10847 ins_pipe(ialu_cr_reg_mem);
10848 %}
10849
10850 // Yanked all unsigned pointer compare operations.
10851 // Pointer compares are done with CmpP which is already unsigned.
10852
10853 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10854 %{
10855 match(Set cr (CmpL op1 op2));
10856
10857 format %{ "cmpq $op1, $op2" %}
10858 opcode(0x3B); /* Opcode 3B /r */
10859 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10860 ins_pipe(ialu_cr_reg_reg);
10861 %}
10862
10863 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10864 %{
10865 match(Set cr (CmpL op1 op2));
10866
10867 format %{ "cmpq $op1, $op2" %}
10868 opcode(0x81, 0x07); /* Opcode 81 /7 */
10869 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
10870 ins_pipe(ialu_cr_reg_imm);
10871 %}
10872
10873 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
10874 %{
10875 match(Set cr (CmpL op1 (LoadL op2)));
10876
10877 format %{ "cmpq $op1, $op2" %}
10878 opcode(0x3B); /* Opcode 3B /r */
10879 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10880 ins_pipe(ialu_cr_reg_mem);
10881 %}
10882
10883 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
10884 %{
10885 match(Set cr (CmpL src zero));
10886
10887 format %{ "testq $src, $src" %}
10888 opcode(0x85);
10889 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10890 ins_pipe(ialu_cr_reg_imm);
10891 %}
10892
10893 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
10894 %{
10895 match(Set cr (CmpL (AndL src con) zero));
10896
10897 format %{ "testq $src, $con\t# long" %}
10898 opcode(0xF7, 0x00);
10899 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
10900 ins_pipe(ialu_cr_reg_imm);
10901 %}
10902
10903 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
10904 %{
10905 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
10906
10907 format %{ "testq $src, $mem" %}
10908 opcode(0x85);
10909 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
10910 ins_pipe(ialu_cr_reg_mem);
10911 %}
10912
10913 // Manifest a CmpL result in an integer register. Very painful.
10914 // This is the test to avoid.
10915 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
10916 %{
10917 match(Set dst (CmpL3 src1 src2));
10918 effect(KILL flags);
10919
10920 ins_cost(275); // XXX
10921 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
10922 "movl $dst, -1\n\t"
10923 "jl,s done\n\t"
10924 "setne $dst\n\t"
10925 "movzbl $dst, $dst\n\t"
10926 "done:" %}
10927 ins_encode(cmpl3_flag(src1, src2, dst));
10928 ins_pipe(pipe_slow);
10929 %}
10930
10931 //----------Max and Min--------------------------------------------------------
10932 // Min Instructions
10933
10934 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
10935 %{
10936 effect(USE_DEF dst, USE src, USE cr);
10937
10938 format %{ "cmovlgt $dst, $src\t# min" %}
10939 opcode(0x0F, 0x4F);
10940 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
10941 ins_pipe(pipe_cmov_reg);
10942 %}
10943
10944
10945 instruct minI_rReg(rRegI dst, rRegI src)
10946 %{
10947 match(Set dst (MinI dst src));
10948
10949 ins_cost(200);
10950 expand %{
10951 rFlagsReg cr;
10952 compI_rReg(cr, dst, src);
10953 cmovI_reg_g(dst, src, cr);
10954 %}
10955 %}
10956
10957 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
10958 %{
10959 effect(USE_DEF dst, USE src, USE cr);
10960
10961 format %{ "cmovllt $dst, $src\t# max" %}
10962 opcode(0x0F, 0x4C);
10963 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
10964 ins_pipe(pipe_cmov_reg);
10965 %}
10966
10967
10968 instruct maxI_rReg(rRegI dst, rRegI src)
10969 %{
10970 match(Set dst (MaxI dst src));
10971
10972 ins_cost(200);
10973 expand %{
10974 rFlagsReg cr;
10975 compI_rReg(cr, dst, src);
10976 cmovI_reg_l(dst, src, cr);
10977 %}
10978 %}
10979
10980 // ============================================================================
10981 // Branch Instructions
10982
10983 // Jump Direct - Label defines a relative address from JMP+1
10984 instruct jmpDir(label labl)
10985 %{
10986 match(Goto);
10987 effect(USE labl);
10988
10989 ins_cost(300);
10990 format %{ "jmp $labl" %}
10991 size(5);
10992 ins_encode %{
10993 Label* L = $labl$$label;
10994 __ jmp(*L, false); // Always long jump
10995 %}
10996 ins_pipe(pipe_jmp);
10997 %}
10998
10999 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11000 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11001 %{
11002 match(If cop cr);
11003 effect(USE labl);
11004
11005 ins_cost(300);
11006 format %{ "j$cop $labl" %}
11007 size(6);
11008 ins_encode %{
11009 Label* L = $labl$$label;
11010 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11011 %}
11012 ins_pipe(pipe_jcc);
11013 %}
11014
11015 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11016 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11017 %{
11018 match(CountedLoopEnd cop cr);
11019 effect(USE labl);
11020
11021 ins_cost(300);
11022 format %{ "j$cop $labl\t# loop end" %}
11023 size(6);
11024 ins_encode %{
11025 Label* L = $labl$$label;
11026 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11027 %}
11028 ins_pipe(pipe_jcc);
11029 %}
11030
11031 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11032 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11033 match(CountedLoopEnd cop cmp);
11034 effect(USE labl);
11035
11036 ins_cost(300);
11037 format %{ "j$cop,u $labl\t# loop end" %}
11038 size(6);
11039 ins_encode %{
11040 Label* L = $labl$$label;
11041 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11042 %}
11043 ins_pipe(pipe_jcc);
11044 %}
11045
11046 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11047 match(CountedLoopEnd cop cmp);
11048 effect(USE labl);
11049
11050 ins_cost(200);
11051 format %{ "j$cop,u $labl\t# loop end" %}
11052 size(6);
11053 ins_encode %{
11054 Label* L = $labl$$label;
11055 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11056 %}
11057 ins_pipe(pipe_jcc);
11058 %}
11059
11060 // Jump Direct Conditional - using unsigned comparison
11061 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11062 match(If cop cmp);
11063 effect(USE labl);
11064
11065 ins_cost(300);
11066 format %{ "j$cop,u $labl" %}
11067 size(6);
11068 ins_encode %{
11069 Label* L = $labl$$label;
11070 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11071 %}
11072 ins_pipe(pipe_jcc);
11073 %}
11074
11075 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11076 match(If cop cmp);
11077 effect(USE labl);
11078
11079 ins_cost(200);
11080 format %{ "j$cop,u $labl" %}
11081 size(6);
11082 ins_encode %{
11083 Label* L = $labl$$label;
11084 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11085 %}
11086 ins_pipe(pipe_jcc);
11087 %}
11088
11089 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11090 match(If cop cmp);
11091 effect(USE labl);
11092
11093 ins_cost(200);
11094 format %{ $$template
11095 if ($cop$$cmpcode == Assembler::notEqual) {
11096 $$emit$$"jp,u $labl\n\t"
11097 $$emit$$"j$cop,u $labl"
11098 } else {
11099 $$emit$$"jp,u done\n\t"
11100 $$emit$$"j$cop,u $labl\n\t"
11101 $$emit$$"done:"
11102 }
11103 %}
11104 ins_encode %{
11105 Label* l = $labl$$label;
11106 if ($cop$$cmpcode == Assembler::notEqual) {
11107 __ jcc(Assembler::parity, *l, false);
11108 __ jcc(Assembler::notEqual, *l, false);
11109 } else if ($cop$$cmpcode == Assembler::equal) {
11110 Label done;
11111 __ jccb(Assembler::parity, done);
11112 __ jcc(Assembler::equal, *l, false);
11113 __ bind(done);
11114 } else {
11115 ShouldNotReachHere();
11116 }
11117 %}
11118 ins_pipe(pipe_jcc);
11119 %}
11120
11121 // ============================================================================
11122 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11123 // superklass array for an instance of the superklass. Set a hidden
11124 // internal cache on a hit (cache is checked with exposed code in
11125 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11126 // encoding ALSO sets flags.
11127
11128 instruct partialSubtypeCheck(rdi_RegP result,
11129 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11130 rFlagsReg cr)
11131 %{
11132 match(Set result (PartialSubtypeCheck sub super));
11133 effect(KILL rcx, KILL cr);
11134
11135 ins_cost(1100); // slightly larger than the next version
11136 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11137 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11138 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11139 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
11140 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
11141 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11142 "xorq $result, $result\t\t Hit: rdi zero\n\t"
11143 "miss:\t" %}
11144
11145 opcode(0x1); // Force a XOR of RDI
11146 ins_encode(enc_PartialSubtypeCheck());
11147 ins_pipe(pipe_slow);
11148 %}
11149
11150 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
11151 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11152 immP0 zero,
11153 rdi_RegP result)
11154 %{
11155 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11156 effect(KILL rcx, KILL result);
11157
11158 ins_cost(1000);
11159 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11160 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11161 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11162 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
11163 "jne,s miss\t\t# Missed: flags nz\n\t"
11164 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11165 "miss:\t" %}
11166
11167 opcode(0x0); // No need to XOR RDI
11168 ins_encode(enc_PartialSubtypeCheck());
11169 ins_pipe(pipe_slow);
11170 %}
11171
11172 // ============================================================================
11173 // Branch Instructions -- short offset versions
11174 //
11175 // These instructions are used to replace jumps of a long offset (the default
11176 // match) with jumps of a shorter offset. These instructions are all tagged
11177 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11178 // match rules in general matching. Instead, the ADLC generates a conversion
11179 // method in the MachNode which can be used to do in-place replacement of the
11180 // long variant with the shorter variant. The compiler will determine if a
11181 // branch can be taken by the is_short_branch_offset() predicate in the machine
11182 // specific code section of the file.
11183
11184 // Jump Direct - Label defines a relative address from JMP+1
11185 instruct jmpDir_short(label labl) %{
11186 match(Goto);
11187 effect(USE labl);
11188
11189 ins_cost(300);
11190 format %{ "jmp,s $labl" %}
11191 size(2);
11192 ins_encode %{
11193 Label* L = $labl$$label;
11194 __ jmpb(*L);
11195 %}
11196 ins_pipe(pipe_jmp);
11197 ins_short_branch(1);
11198 %}
11199
11200 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11201 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
11202 match(If cop cr);
11203 effect(USE labl);
11204
11205 ins_cost(300);
11206 format %{ "j$cop,s $labl" %}
11207 size(2);
11208 ins_encode %{
11209 Label* L = $labl$$label;
11210 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11211 %}
11212 ins_pipe(pipe_jcc);
11213 ins_short_branch(1);
11214 %}
11215
11216 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11217 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
11218 match(CountedLoopEnd cop cr);
11219 effect(USE labl);
11220
11221 ins_cost(300);
11222 format %{ "j$cop,s $labl\t# loop end" %}
11223 size(2);
11224 ins_encode %{
11225 Label* L = $labl$$label;
11226 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11227 %}
11228 ins_pipe(pipe_jcc);
11229 ins_short_branch(1);
11230 %}
11231
11232 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11233 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11234 match(CountedLoopEnd cop cmp);
11235 effect(USE labl);
11236
11237 ins_cost(300);
11238 format %{ "j$cop,us $labl\t# loop end" %}
11239 size(2);
11240 ins_encode %{
11241 Label* L = $labl$$label;
11242 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11243 %}
11244 ins_pipe(pipe_jcc);
11245 ins_short_branch(1);
11246 %}
11247
11248 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11249 match(CountedLoopEnd cop cmp);
11250 effect(USE labl);
11251
11252 ins_cost(300);
11253 format %{ "j$cop,us $labl\t# loop end" %}
11254 size(2);
11255 ins_encode %{
11256 Label* L = $labl$$label;
11257 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11258 %}
11259 ins_pipe(pipe_jcc);
11260 ins_short_branch(1);
11261 %}
11262
11263 // Jump Direct Conditional - using unsigned comparison
11264 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11265 match(If cop cmp);
11266 effect(USE labl);
11267
11268 ins_cost(300);
11269 format %{ "j$cop,us $labl" %}
11270 size(2);
11271 ins_encode %{
11272 Label* L = $labl$$label;
11273 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11274 %}
11275 ins_pipe(pipe_jcc);
11276 ins_short_branch(1);
11277 %}
11278
11279 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11280 match(If cop cmp);
11281 effect(USE labl);
11282
11283 ins_cost(300);
11284 format %{ "j$cop,us $labl" %}
11285 size(2);
11286 ins_encode %{
11287 Label* L = $labl$$label;
11288 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11289 %}
11290 ins_pipe(pipe_jcc);
11291 ins_short_branch(1);
11292 %}
11293
11294 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11295 match(If cop cmp);
11296 effect(USE labl);
11297
11298 ins_cost(300);
11299 format %{ $$template
11300 if ($cop$$cmpcode == Assembler::notEqual) {
11301 $$emit$$"jp,u,s $labl\n\t"
11302 $$emit$$"j$cop,u,s $labl"
11303 } else {
11304 $$emit$$"jp,u,s done\n\t"
11305 $$emit$$"j$cop,u,s $labl\n\t"
11306 $$emit$$"done:"
11307 }
11308 %}
11309 size(4);
11310 ins_encode %{
11311 Label* l = $labl$$label;
11312 if ($cop$$cmpcode == Assembler::notEqual) {
11313 __ jccb(Assembler::parity, *l);
11314 __ jccb(Assembler::notEqual, *l);
11315 } else if ($cop$$cmpcode == Assembler::equal) {
11316 Label done;
11317 __ jccb(Assembler::parity, done);
11318 __ jccb(Assembler::equal, *l);
11319 __ bind(done);
11320 } else {
11321 ShouldNotReachHere();
11322 }
11323 %}
11324 ins_pipe(pipe_jcc);
11325 ins_short_branch(1);
11326 %}
11327
11328 // ============================================================================
11329 // inlined locking and unlocking
11330
11331 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
11332 predicate(Compile::current()->use_rtm());
11333 match(Set cr (FastLock object box));
11334 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
11335 ins_cost(300);
11336 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
11337 ins_encode %{
11338 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
11339 $scr$$Register, $cx1$$Register, $cx2$$Register,
11340 _counters, _rtm_counters, _stack_rtm_counters,
11341 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
11342 true, ra_->C->profile_rtm());
11343 %}
11344 ins_pipe(pipe_slow);
11345 %}
11346
11347 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
11348 predicate(!Compile::current()->use_rtm());
11349 match(Set cr (FastLock object box));
11350 effect(TEMP tmp, TEMP scr, USE_KILL box);
11351 ins_cost(300);
11352 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
11353 ins_encode %{
11354 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
11355 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
11356 %}
11357 ins_pipe(pipe_slow);
11358 %}
11359
11360 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
11361 match(Set cr (FastUnlock object box));
11362 effect(TEMP tmp, USE_KILL box);
11363 ins_cost(300);
11364 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
11365 ins_encode %{
11366 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
11367 %}
11368 ins_pipe(pipe_slow);
11369 %}
11370
11371
11372 // ============================================================================
11373 // Safepoint Instructions
11374 instruct safePoint_poll(rFlagsReg cr)
11375 %{
11376 predicate(!Assembler::is_polling_page_far());
11377 match(SafePoint);
11378 effect(KILL cr);
11379
11380 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
11381 "# Safepoint: poll for GC" %}
11382 ins_cost(125);
11383 ins_encode %{
11384 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
11385 __ testl(rax, addr);
11386 %}
11387 ins_pipe(ialu_reg_mem);
11388 %}
11389
11390 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
11391 %{
11392 predicate(Assembler::is_polling_page_far());
11393 match(SafePoint poll);
11394 effect(KILL cr, USE poll);
11395
11396 format %{ "testl rax, [$poll]\t"
11397 "# Safepoint: poll for GC" %}
11398 ins_cost(125);
11399 ins_encode %{
11400 __ relocate(relocInfo::poll_type);
11401 __ testl(rax, Address($poll$$Register, 0));
11402 %}
11403 ins_pipe(ialu_reg_mem);
11404 %}
11405
11406 // ============================================================================
11407 // Procedure Call/Return Instructions
11408 // Call Java Static Instruction
11409 // Note: If this code changes, the corresponding ret_addr_offset() and
11410 // compute_padding() functions will have to be adjusted.
11411 instruct CallStaticJavaDirect(method meth) %{
11412 match(CallStaticJava);
11413 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke());
11414 effect(USE meth);
11415
11416 ins_cost(300);
11417 format %{ "call,static " %}
11418 opcode(0xE8); /* E8 cd */
11419 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
11420 ins_pipe(pipe_slow);
11421 ins_alignment(4);
11422 %}
11423
11424 // Call Java Static Instruction (method handle version)
11425 // Note: If this code changes, the corresponding ret_addr_offset() and
11426 // compute_padding() functions will have to be adjusted.
11427 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{
11428 match(CallStaticJava);
11429 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke());
11430 effect(USE meth);
11431 // RBP is saved by all callees (for interpreter stack correction).
11432 // We use it here for a similar purpose, in {preserve,restore}_SP.
11433
11434 ins_cost(300);
11435 format %{ "call,static/MethodHandle " %}
11436 opcode(0xE8); /* E8 cd */
11437 ins_encode(clear_avx, preserve_SP,
11438 Java_Static_Call(meth),
11439 restore_SP,
11440 call_epilog);
11441 ins_pipe(pipe_slow);
11442 ins_alignment(4);
11443 %}
11444
11445 // Call Java Dynamic Instruction
11446 // Note: If this code changes, the corresponding ret_addr_offset() and
11447 // compute_padding() functions will have to be adjusted.
11448 instruct CallDynamicJavaDirect(method meth)
11449 %{
11450 match(CallDynamicJava);
11451 effect(USE meth);
11452
11453 ins_cost(300);
11454 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11455 "call,dynamic " %}
11456 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
11457 ins_pipe(pipe_slow);
11458 ins_alignment(4);
11459 %}
11460
11461 // Call Runtime Instruction
11462 instruct CallRuntimeDirect(method meth)
11463 %{
11464 match(CallRuntime);
11465 effect(USE meth);
11466
11467 ins_cost(300);
11468 format %{ "call,runtime " %}
11469 ins_encode(clear_avx, Java_To_Runtime(meth));
11470 ins_pipe(pipe_slow);
11471 %}
11472
11473 // Call runtime without safepoint
11474 instruct CallLeafDirect(method meth)
11475 %{
11476 match(CallLeaf);
11477 effect(USE meth);
11478
11479 ins_cost(300);
11480 format %{ "call_leaf,runtime " %}
11481 ins_encode(clear_avx, Java_To_Runtime(meth));
11482 ins_pipe(pipe_slow);
11483 %}
11484
11485 // Call runtime without safepoint
11486 instruct CallLeafNoFPDirect(method meth)
11487 %{
11488 match(CallLeafNoFP);
11489 effect(USE meth);
11490
11491 ins_cost(300);
11492 format %{ "call_leaf_nofp,runtime " %}
11493 ins_encode(Java_To_Runtime(meth));
11494 ins_pipe(pipe_slow);
11495 %}
11496
11497 // Return Instruction
11498 // Remove the return address & jump to it.
11499 // Notice: We always emit a nop after a ret to make sure there is room
11500 // for safepoint patching
11501 instruct Ret()
11502 %{
11503 match(Return);
11504
11505 format %{ "ret" %}
11506 opcode(0xC3);
11507 ins_encode(OpcP);
11508 ins_pipe(pipe_jmp);
11509 %}
11510
11511 // Tail Call; Jump from runtime stub to Java code.
11512 // Also known as an 'interprocedural jump'.
11513 // Target of jump will eventually return to caller.
11514 // TailJump below removes the return address.
11515 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
11516 %{
11517 match(TailCall jump_target method_oop);
11518
11519 ins_cost(300);
11520 format %{ "jmp $jump_target\t# rbx holds method oop" %}
11521 opcode(0xFF, 0x4); /* Opcode FF /4 */
11522 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
11523 ins_pipe(pipe_jmp);
11524 %}
11525
11526 // Tail Jump; remove the return address; jump to target.
11527 // TailCall above leaves the return address around.
11528 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
11529 %{
11530 match(TailJump jump_target ex_oop);
11531
11532 ins_cost(300);
11533 format %{ "popq rdx\t# pop return address\n\t"
11534 "jmp $jump_target" %}
11535 opcode(0xFF, 0x4); /* Opcode FF /4 */
11536 ins_encode(Opcode(0x5a), // popq rdx
11537 REX_reg(jump_target), OpcP, reg_opc(jump_target));
11538 ins_pipe(pipe_jmp);
11539 %}
11540
11541 // Create exception oop: created by stack-crawling runtime code.
11542 // Created exception is now available to this handler, and is setup
11543 // just prior to jumping to this handler. No code emitted.
11544 instruct CreateException(rax_RegP ex_oop)
11545 %{
11546 match(Set ex_oop (CreateEx));
11547
11548 size(0);
11549 // use the following format syntax
11550 format %{ "# exception oop is in rax; no code emitted" %}
11551 ins_encode();
11552 ins_pipe(empty);
11553 %}
11554
11555 // Rethrow exception:
11556 // The exception oop will come in the first argument position.
11557 // Then JUMP (not call) to the rethrow stub code.
11558 instruct RethrowException()
11559 %{
11560 match(Rethrow);
11561
11562 // use the following format syntax
11563 format %{ "jmp rethrow_stub" %}
11564 ins_encode(enc_rethrow);
11565 ins_pipe(pipe_jmp);
11566 %}
11567
11568
11569 // ============================================================================
11570 // This name is KNOWN by the ADLC and cannot be changed.
11571 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11572 // for this guy.
11573 instruct tlsLoadP(r15_RegP dst) %{
11574 match(Set dst (ThreadLocal));
11575 effect(DEF dst);
11576
11577 size(0);
11578 format %{ "# TLS is in R15" %}
11579 ins_encode( /*empty encoding*/ );
11580 ins_pipe(ialu_reg_reg);
11581 %}
11582
11583
11584 //----------PEEPHOLE RULES-----------------------------------------------------
11585 // These must follow all instruction definitions as they use the names
11586 // defined in the instructions definitions.
11587 //
11588 // peepmatch ( root_instr_name [preceding_instruction]* );
11589 //
11590 // peepconstraint %{
11591 // (instruction_number.operand_name relational_op instruction_number.operand_name
11592 // [, ...] );
11593 // // instruction numbers are zero-based using left to right order in peepmatch
11594 //
11595 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11596 // // provide an instruction_number.operand_name for each operand that appears
11597 // // in the replacement instruction's match rule
11598 //
11599 // ---------VM FLAGS---------------------------------------------------------
11600 //
11601 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11602 //
11603 // Each peephole rule is given an identifying number starting with zero and
11604 // increasing by one in the order seen by the parser. An individual peephole
11605 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11606 // on the command-line.
11607 //
11608 // ---------CURRENT LIMITATIONS----------------------------------------------
11609 //
11610 // Only match adjacent instructions in same basic block
11611 // Only equality constraints
11612 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11613 // Only one replacement instruction
11614 //
11615 // ---------EXAMPLE----------------------------------------------------------
11616 //
11617 // // pertinent parts of existing instructions in architecture description
11618 // instruct movI(rRegI dst, rRegI src)
11619 // %{
11620 // match(Set dst (CopyI src));
11621 // %}
11622 //
11623 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
11624 // %{
11625 // match(Set dst (AddI dst src));
11626 // effect(KILL cr);
11627 // %}
11628 //
11629 // // Change (inc mov) to lea
11630 // peephole %{
11631 // // increment preceeded by register-register move
11632 // peepmatch ( incI_rReg movI );
11633 // // require that the destination register of the increment
11634 // // match the destination register of the move
11635 // peepconstraint ( 0.dst == 1.dst );
11636 // // construct a replacement instruction that sets
11637 // // the destination to ( move's source register + one )
11638 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
11639 // %}
11640 //
11641
11642 // Implementation no longer uses movX instructions since
11643 // machine-independent system no longer uses CopyX nodes.
11644 //
11645 // peephole
11646 // %{
11647 // peepmatch (incI_rReg movI);
11648 // peepconstraint (0.dst == 1.dst);
11649 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11650 // %}
11651
11652 // peephole
11653 // %{
11654 // peepmatch (decI_rReg movI);
11655 // peepconstraint (0.dst == 1.dst);
11656 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11657 // %}
11658
11659 // peephole
11660 // %{
11661 // peepmatch (addI_rReg_imm movI);
11662 // peepconstraint (0.dst == 1.dst);
11663 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11664 // %}
11665
11666 // peephole
11667 // %{
11668 // peepmatch (incL_rReg movL);
11669 // peepconstraint (0.dst == 1.dst);
11670 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11671 // %}
11672
11673 // peephole
11674 // %{
11675 // peepmatch (decL_rReg movL);
11676 // peepconstraint (0.dst == 1.dst);
11677 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11678 // %}
11679
11680 // peephole
11681 // %{
11682 // peepmatch (addL_rReg_imm movL);
11683 // peepconstraint (0.dst == 1.dst);
11684 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11685 // %}
11686
11687 // peephole
11688 // %{
11689 // peepmatch (addP_rReg_imm movP);
11690 // peepconstraint (0.dst == 1.dst);
11691 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
11692 // %}
11693
11694 // // Change load of spilled value to only a spill
11695 // instruct storeI(memory mem, rRegI src)
11696 // %{
11697 // match(Set mem (StoreI mem src));
11698 // %}
11699 //
11700 // instruct loadI(rRegI dst, memory mem)
11701 // %{
11702 // match(Set dst (LoadI mem));
11703 // %}
11704 //
11705
11706 peephole
11707 %{
11708 peepmatch (loadI storeI);
11709 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11710 peepreplace (storeI(1.mem 1.mem 1.src));
11711 %}
11712
11713 peephole
11714 %{
11715 peepmatch (loadL storeL);
11716 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11717 peepreplace (storeL(1.mem 1.mem 1.src));
11718 %}
11719
11720 //----------SMARTSPILL RULES---------------------------------------------------
11721 // These must follow all instruction definitions as they use the names
11722 // defined in the instructions definitions.