1 /*
   2  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "memory/allocation.inline.hpp"
  27 #include "opto/ad.hpp"
  28 #include "opto/addnode.hpp"
  29 #include "opto/callnode.hpp"
  30 #include "opto/idealGraphPrinter.hpp"
  31 #include "opto/matcher.hpp"
  32 #include "opto/memnode.hpp"
  33 #include "opto/movenode.hpp"
  34 #include "opto/opcodes.hpp"
  35 #include "opto/regmask.hpp"
  36 #include "opto/rootnode.hpp"
  37 #include "opto/runtime.hpp"
  38 #include "opto/type.hpp"
  39 #include "opto/vectornode.hpp"
  40 #include "runtime/os.hpp"
  41 #include "runtime/sharedRuntime.hpp"
  42 
  43 OptoReg::Name OptoReg::c_frame_pointer;
  44 
  45 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
  46 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
  47 RegMask Matcher::STACK_ONLY_mask;
  48 RegMask Matcher::c_frame_ptr_mask;
  49 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
  50 const uint Matcher::_end_rematerialize   = _END_REMATERIALIZE;
  51 
  52 //---------------------------Matcher-------------------------------------------
  53 Matcher::Matcher()
  54 : PhaseTransform( Phase::Ins_Select ),
  55 #ifdef ASSERT
  56   _old2new_map(C->comp_arena()),
  57   _new2old_map(C->comp_arena()),
  58 #endif
  59   _shared_nodes(C->comp_arena()),
  60   _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
  61   _swallowed(swallowed),
  62   _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
  63   _end_inst_chain_rule(_END_INST_CHAIN_RULE),
  64   _must_clone(must_clone),
  65   _register_save_policy(register_save_policy),
  66   _c_reg_save_policy(c_reg_save_policy),
  67   _register_save_type(register_save_type),
  68   _ruleName(ruleName),
  69   _allocation_started(false),
  70   _states_arena(Chunk::medium_size),
  71   _visited(&_states_arena),
  72   _shared(&_states_arena),
  73   _dontcare(&_states_arena) {
  74   C->set_matcher(this);
  75 
  76   idealreg2spillmask  [Op_RegI] = NULL;
  77   idealreg2spillmask  [Op_RegN] = NULL;
  78   idealreg2spillmask  [Op_RegL] = NULL;
  79   idealreg2spillmask  [Op_RegF] = NULL;
  80   idealreg2spillmask  [Op_RegD] = NULL;
  81   idealreg2spillmask  [Op_RegP] = NULL;
  82   idealreg2spillmask  [Op_VecS] = NULL;
  83   idealreg2spillmask  [Op_VecD] = NULL;
  84   idealreg2spillmask  [Op_VecX] = NULL;
  85   idealreg2spillmask  [Op_VecY] = NULL;
  86 
  87   idealreg2debugmask  [Op_RegI] = NULL;
  88   idealreg2debugmask  [Op_RegN] = NULL;
  89   idealreg2debugmask  [Op_RegL] = NULL;
  90   idealreg2debugmask  [Op_RegF] = NULL;
  91   idealreg2debugmask  [Op_RegD] = NULL;
  92   idealreg2debugmask  [Op_RegP] = NULL;
  93   idealreg2debugmask  [Op_VecS] = NULL;
  94   idealreg2debugmask  [Op_VecD] = NULL;
  95   idealreg2debugmask  [Op_VecX] = NULL;
  96   idealreg2debugmask  [Op_VecY] = NULL;
  97 
  98   idealreg2mhdebugmask[Op_RegI] = NULL;
  99   idealreg2mhdebugmask[Op_RegN] = NULL;
 100   idealreg2mhdebugmask[Op_RegL] = NULL;
 101   idealreg2mhdebugmask[Op_RegF] = NULL;
 102   idealreg2mhdebugmask[Op_RegD] = NULL;
 103   idealreg2mhdebugmask[Op_RegP] = NULL;
 104   idealreg2mhdebugmask[Op_VecS] = NULL;
 105   idealreg2mhdebugmask[Op_VecD] = NULL;
 106   idealreg2mhdebugmask[Op_VecX] = NULL;
 107   idealreg2mhdebugmask[Op_VecY] = NULL;
 108 
 109   debug_only(_mem_node = NULL;)   // Ideal memory node consumed by mach node
 110 }
 111 
 112 //------------------------------warp_incoming_stk_arg------------------------
 113 // This warps a VMReg into an OptoReg::Name
 114 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
 115   OptoReg::Name warped;
 116   if( reg->is_stack() ) {  // Stack slot argument?
 117     warped = OptoReg::add(_old_SP, reg->reg2stack() );
 118     warped = OptoReg::add(warped, C->out_preserve_stack_slots());
 119     if( warped >= _in_arg_limit )
 120       _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
 121     if (!RegMask::can_represent_arg(warped)) {
 122       // the compiler cannot represent this method's calling sequence
 123       C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
 124       return OptoReg::Bad;
 125     }
 126     return warped;
 127   }
 128   return OptoReg::as_OptoReg(reg);
 129 }
 130 
 131 //---------------------------compute_old_SP------------------------------------
 132 OptoReg::Name Compile::compute_old_SP() {
 133   int fixed    = fixed_slots();
 134   int preserve = in_preserve_stack_slots();
 135   return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
 136 }
 137 
 138 
 139 
 140 #ifdef ASSERT
 141 void Matcher::verify_new_nodes_only(Node* xroot) {
 142   // Make sure that the new graph only references new nodes
 143   ResourceMark rm;
 144   Unique_Node_List worklist;
 145   VectorSet visited(Thread::current()->resource_area());
 146   worklist.push(xroot);
 147   while (worklist.size() > 0) {
 148     Node* n = worklist.pop();
 149     visited <<= n->_idx;
 150     assert(C->node_arena()->contains(n), "dead node");
 151     for (uint j = 0; j < n->req(); j++) {
 152       Node* in = n->in(j);
 153       if (in != NULL) {
 154         assert(C->node_arena()->contains(in), "dead node");
 155         if (!visited.test(in->_idx)) {
 156           worklist.push(in);
 157         }
 158       }
 159     }
 160   }
 161 }
 162 #endif
 163 
 164 
 165 //---------------------------match---------------------------------------------
 166 void Matcher::match( ) {
 167   if( MaxLabelRootDepth < 100 ) { // Too small?
 168     assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
 169     MaxLabelRootDepth = 100;
 170   }
 171   // One-time initialization of some register masks.
 172   init_spill_mask( C->root()->in(1) );
 173   _return_addr_mask = return_addr();
 174 #ifdef _LP64
 175   // Pointers take 2 slots in 64-bit land
 176   _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
 177 #endif
 178 
 179   // Map a Java-signature return type into return register-value
 180   // machine registers for 0, 1 and 2 returned values.
 181   const TypeTuple *range = C->tf()->range();
 182   if( range->cnt() > TypeFunc::Parms ) { // If not a void function
 183     // Get ideal-register return type
 184     int ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
 185     // Get machine return register
 186     uint sop = C->start()->Opcode();
 187     OptoRegPair regs = return_value(ireg, false);
 188 
 189     // And mask for same
 190     _return_value_mask = RegMask(regs.first());
 191     if( OptoReg::is_valid(regs.second()) )
 192       _return_value_mask.Insert(regs.second());
 193   }
 194 
 195   // ---------------
 196   // Frame Layout
 197 
 198   // Need the method signature to determine the incoming argument types,
 199   // because the types determine which registers the incoming arguments are
 200   // in, and this affects the matched code.
 201   const TypeTuple *domain = C->tf()->domain();
 202   uint             argcnt = domain->cnt() - TypeFunc::Parms;
 203   BasicType *sig_bt        = NEW_RESOURCE_ARRAY( BasicType, argcnt );
 204   VMRegPair *vm_parm_regs  = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
 205   _parm_regs               = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
 206   _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
 207   uint i;
 208   for( i = 0; i<argcnt; i++ ) {
 209     sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
 210   }
 211 
 212   // Pass array of ideal registers and length to USER code (from the AD file)
 213   // that will convert this to an array of register numbers.
 214   const StartNode *start = C->start();
 215   start->calling_convention( sig_bt, vm_parm_regs, argcnt );
 216 #ifdef ASSERT
 217   // Sanity check users' calling convention.  Real handy while trying to
 218   // get the initial port correct.
 219   { for (uint i = 0; i<argcnt; i++) {
 220       if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
 221         assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
 222         _parm_regs[i].set_bad();
 223         continue;
 224       }
 225       VMReg parm_reg = vm_parm_regs[i].first();
 226       assert(parm_reg->is_valid(), "invalid arg?");
 227       if (parm_reg->is_reg()) {
 228         OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
 229         assert(can_be_java_arg(opto_parm_reg) ||
 230                C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
 231                opto_parm_reg == inline_cache_reg(),
 232                "parameters in register must be preserved by runtime stubs");
 233       }
 234       for (uint j = 0; j < i; j++) {
 235         assert(parm_reg != vm_parm_regs[j].first(),
 236                "calling conv. must produce distinct regs");
 237       }
 238     }
 239   }
 240 #endif
 241 
 242   // Do some initial frame layout.
 243 
 244   // Compute the old incoming SP (may be called FP) as
 245   //   OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
 246   _old_SP = C->compute_old_SP();
 247   assert( is_even(_old_SP), "must be even" );
 248 
 249   // Compute highest incoming stack argument as
 250   //   _old_SP + out_preserve_stack_slots + incoming argument size.
 251   _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
 252   assert( is_even(_in_arg_limit), "out_preserve must be even" );
 253   for( i = 0; i < argcnt; i++ ) {
 254     // Permit args to have no register
 255     _calling_convention_mask[i].Clear();
 256     if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
 257       continue;
 258     }
 259     // calling_convention returns stack arguments as a count of
 260     // slots beyond OptoReg::stack0()/VMRegImpl::stack0.  We need to convert this to
 261     // the allocators point of view, taking into account all the
 262     // preserve area, locks & pad2.
 263 
 264     OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
 265     if( OptoReg::is_valid(reg1))
 266       _calling_convention_mask[i].Insert(reg1);
 267 
 268     OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
 269     if( OptoReg::is_valid(reg2))
 270       _calling_convention_mask[i].Insert(reg2);
 271 
 272     // Saved biased stack-slot register number
 273     _parm_regs[i].set_pair(reg2, reg1);
 274   }
 275 
 276   // Finally, make sure the incoming arguments take up an even number of
 277   // words, in case the arguments or locals need to contain doubleword stack
 278   // slots.  The rest of the system assumes that stack slot pairs (in
 279   // particular, in the spill area) which look aligned will in fact be
 280   // aligned relative to the stack pointer in the target machine.  Double
 281   // stack slots will always be allocated aligned.
 282   _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
 283 
 284   // Compute highest outgoing stack argument as
 285   //   _new_SP + out_preserve_stack_slots + max(outgoing argument size).
 286   _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
 287   assert( is_even(_out_arg_limit), "out_preserve must be even" );
 288 
 289   if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
 290     // the compiler cannot represent this method's calling sequence
 291     C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
 292   }
 293 
 294   if (C->failing())  return;  // bailed out on incoming arg failure
 295 
 296   // ---------------
 297   // Collect roots of matcher trees.  Every node for which
 298   // _shared[_idx] is cleared is guaranteed to not be shared, and thus
 299   // can be a valid interior of some tree.
 300   find_shared( C->root() );
 301   find_shared( C->top() );
 302 
 303   C->print_method(PHASE_BEFORE_MATCHING);
 304 
 305   // Create new ideal node ConP #NULL even if it does exist in old space
 306   // to avoid false sharing if the corresponding mach node is not used.
 307   // The corresponding mach node is only used in rare cases for derived
 308   // pointers.
 309   Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
 310 
 311   // Swap out to old-space; emptying new-space
 312   Arena *old = C->node_arena()->move_contents(C->old_arena());
 313 
 314   // Save debug and profile information for nodes in old space:
 315   _old_node_note_array = C->node_note_array();
 316   if (_old_node_note_array != NULL) {
 317     C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
 318                            (C->comp_arena(), _old_node_note_array->length(),
 319                             0, NULL));
 320   }
 321 
 322   // Pre-size the new_node table to avoid the need for range checks.
 323   grow_new_node_array(C->unique());
 324 
 325   // Reset node counter so MachNodes start with _idx at 0
 326   int nodes = C->unique(); // save value
 327   C->set_unique(0);
 328   C->reset_dead_node_list();
 329 
 330   // Recursively match trees from old space into new space.
 331   // Correct leaves of new-space Nodes; they point to old-space.
 332   _visited.Clear();             // Clear visit bits for xform call
 333   C->set_cached_top_node(xform( C->top(), nodes ));
 334   if (!C->failing()) {
 335     Node* xroot =        xform( C->root(), 1 );
 336     if (xroot == NULL) {
 337       Matcher::soft_match_failure();  // recursive matching process failed
 338       C->record_method_not_compilable("instruction match failed");
 339     } else {
 340       // During matching shared constants were attached to C->root()
 341       // because xroot wasn't available yet, so transfer the uses to
 342       // the xroot.
 343       for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
 344         Node* n = C->root()->fast_out(j);
 345         if (C->node_arena()->contains(n)) {
 346           assert(n->in(0) == C->root(), "should be control user");
 347           n->set_req(0, xroot);
 348           --j;
 349           --jmax;
 350         }
 351       }
 352 
 353       // Generate new mach node for ConP #NULL
 354       assert(new_ideal_null != NULL, "sanity");
 355       _mach_null = match_tree(new_ideal_null);
 356       // Don't set control, it will confuse GCM since there are no uses.
 357       // The control will be set when this node is used first time
 358       // in find_base_for_derived().
 359       assert(_mach_null != NULL, "");
 360 
 361       C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
 362 
 363 #ifdef ASSERT
 364       verify_new_nodes_only(xroot);
 365 #endif
 366     }
 367   }
 368   if (C->top() == NULL || C->root() == NULL) {
 369     C->record_method_not_compilable("graph lost"); // %%% cannot happen?
 370   }
 371   if (C->failing()) {
 372     // delete old;
 373     old->destruct_contents();
 374     return;
 375   }
 376   assert( C->top(), "" );
 377   assert( C->root(), "" );
 378   validate_null_checks();
 379 
 380   // Now smoke old-space
 381   NOT_DEBUG( old->destruct_contents() );
 382 
 383   // ------------------------
 384   // Set up save-on-entry registers
 385   Fixup_Save_On_Entry( );
 386 }
 387 
 388 
 389 //------------------------------Fixup_Save_On_Entry----------------------------
 390 // The stated purpose of this routine is to take care of save-on-entry
 391 // registers.  However, the overall goal of the Match phase is to convert into
 392 // machine-specific instructions which have RegMasks to guide allocation.
 393 // So what this procedure really does is put a valid RegMask on each input
 394 // to the machine-specific variations of all Return, TailCall and Halt
 395 // instructions.  It also adds edgs to define the save-on-entry values (and of
 396 // course gives them a mask).
 397 
 398 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
 399   RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
 400   // Do all the pre-defined register masks
 401   rms[TypeFunc::Control  ] = RegMask::Empty;
 402   rms[TypeFunc::I_O      ] = RegMask::Empty;
 403   rms[TypeFunc::Memory   ] = RegMask::Empty;
 404   rms[TypeFunc::ReturnAdr] = ret_adr;
 405   rms[TypeFunc::FramePtr ] = fp;
 406   return rms;
 407 }
 408 
 409 //---------------------------init_first_stack_mask-----------------------------
 410 // Create the initial stack mask used by values spilling to the stack.
 411 // Disallow any debug info in outgoing argument areas by setting the
 412 // initial mask accordingly.
 413 void Matcher::init_first_stack_mask() {
 414 
 415   // Allocate storage for spill masks as masks for the appropriate load type.
 416   RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+4));
 417 
 418   idealreg2spillmask  [Op_RegN] = &rms[0];
 419   idealreg2spillmask  [Op_RegI] = &rms[1];
 420   idealreg2spillmask  [Op_RegL] = &rms[2];
 421   idealreg2spillmask  [Op_RegF] = &rms[3];
 422   idealreg2spillmask  [Op_RegD] = &rms[4];
 423   idealreg2spillmask  [Op_RegP] = &rms[5];
 424 
 425   idealreg2debugmask  [Op_RegN] = &rms[6];
 426   idealreg2debugmask  [Op_RegI] = &rms[7];
 427   idealreg2debugmask  [Op_RegL] = &rms[8];
 428   idealreg2debugmask  [Op_RegF] = &rms[9];
 429   idealreg2debugmask  [Op_RegD] = &rms[10];
 430   idealreg2debugmask  [Op_RegP] = &rms[11];
 431 
 432   idealreg2mhdebugmask[Op_RegN] = &rms[12];
 433   idealreg2mhdebugmask[Op_RegI] = &rms[13];
 434   idealreg2mhdebugmask[Op_RegL] = &rms[14];
 435   idealreg2mhdebugmask[Op_RegF] = &rms[15];
 436   idealreg2mhdebugmask[Op_RegD] = &rms[16];
 437   idealreg2mhdebugmask[Op_RegP] = &rms[17];
 438 
 439   idealreg2spillmask  [Op_VecS] = &rms[18];
 440   idealreg2spillmask  [Op_VecD] = &rms[19];
 441   idealreg2spillmask  [Op_VecX] = &rms[20];
 442   idealreg2spillmask  [Op_VecY] = &rms[21];
 443 
 444   OptoReg::Name i;
 445 
 446   // At first, start with the empty mask
 447   C->FIRST_STACK_mask().Clear();
 448 
 449   // Add in the incoming argument area
 450   OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
 451   for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
 452     C->FIRST_STACK_mask().Insert(i);
 453   }
 454   // Add in all bits past the outgoing argument area
 455   guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
 456             "must be able to represent all call arguments in reg mask");
 457   OptoReg::Name init = _out_arg_limit;
 458   for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
 459     C->FIRST_STACK_mask().Insert(i);
 460   }
 461   // Finally, set the "infinite stack" bit.
 462   C->FIRST_STACK_mask().set_AllStack();
 463 
 464   // Make spill masks.  Registers for their class, plus FIRST_STACK_mask.
 465   RegMask aligned_stack_mask = C->FIRST_STACK_mask();
 466   // Keep spill masks aligned.
 467   aligned_stack_mask.clear_to_pairs();
 468   assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 469 
 470   *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
 471 #ifdef _LP64
 472   *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
 473    idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
 474    idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
 475 #else
 476    idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
 477 #endif
 478   *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
 479    idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
 480   *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
 481    idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
 482   *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
 483    idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
 484   *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
 485    idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
 486 
 487   if (Matcher::vector_size_supported(T_BYTE,4)) {
 488     *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
 489      idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
 490   }
 491   if (Matcher::vector_size_supported(T_FLOAT,2)) {
 492     // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
 493     // RA guarantees such alignment since it is needed for Double and Long values.
 494     *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
 495      idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
 496   }
 497   if (Matcher::vector_size_supported(T_FLOAT,4)) {
 498     // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
 499     //
 500     // RA can use input arguments stack slots for spills but until RA
 501     // we don't know frame size and offset of input arg stack slots.
 502     //
 503     // Exclude last input arg stack slots to avoid spilling vectors there
 504     // otherwise vector spills could stomp over stack slots in caller frame.
 505     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 506     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
 507       aligned_stack_mask.Remove(in);
 508       in = OptoReg::add(in, -1);
 509     }
 510      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
 511      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 512     *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
 513      idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
 514   }
 515   if (Matcher::vector_size_supported(T_FLOAT,8)) {
 516     // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
 517     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 518     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
 519       aligned_stack_mask.Remove(in);
 520       in = OptoReg::add(in, -1);
 521     }
 522      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
 523      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 524     *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
 525      idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
 526   }
 527    if (UseFPUForSpilling) {
 528      // This mask logic assumes that the spill operations are
 529      // symmetric and that the registers involved are the same size.
 530      // On sparc for instance we may have to use 64 bit moves will
 531      // kill 2 registers when used with F0-F31.
 532      idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
 533      idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
 534 #ifdef _LP64
 535      idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
 536      idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
 537      idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
 538      idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
 539 #else
 540      idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
 541 #ifdef ARM
 542      // ARM has support for moving 64bit values between a pair of
 543      // integer registers and a double register
 544      idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
 545      idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
 546 #endif
 547 #endif
 548    }
 549 
 550   // Make up debug masks.  Any spill slot plus callee-save registers.
 551   // Caller-save registers are assumed to be trashable by the various
 552   // inline-cache fixup routines.
 553   *idealreg2debugmask  [Op_RegN]= *idealreg2spillmask[Op_RegN];
 554   *idealreg2debugmask  [Op_RegI]= *idealreg2spillmask[Op_RegI];
 555   *idealreg2debugmask  [Op_RegL]= *idealreg2spillmask[Op_RegL];
 556   *idealreg2debugmask  [Op_RegF]= *idealreg2spillmask[Op_RegF];
 557   *idealreg2debugmask  [Op_RegD]= *idealreg2spillmask[Op_RegD];
 558   *idealreg2debugmask  [Op_RegP]= *idealreg2spillmask[Op_RegP];
 559 
 560   *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
 561   *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
 562   *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
 563   *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
 564   *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
 565   *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
 566 
 567   // Prevent stub compilations from attempting to reference
 568   // callee-saved registers from debug info
 569   bool exclude_soe = !Compile::current()->is_method_compilation();
 570 
 571   for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
 572     // registers the caller has to save do not work
 573     if( _register_save_policy[i] == 'C' ||
 574         _register_save_policy[i] == 'A' ||
 575         (_register_save_policy[i] == 'E' && exclude_soe) ) {
 576       idealreg2debugmask  [Op_RegN]->Remove(i);
 577       idealreg2debugmask  [Op_RegI]->Remove(i); // Exclude save-on-call
 578       idealreg2debugmask  [Op_RegL]->Remove(i); // registers from debug
 579       idealreg2debugmask  [Op_RegF]->Remove(i); // masks
 580       idealreg2debugmask  [Op_RegD]->Remove(i);
 581       idealreg2debugmask  [Op_RegP]->Remove(i);
 582 
 583       idealreg2mhdebugmask[Op_RegN]->Remove(i);
 584       idealreg2mhdebugmask[Op_RegI]->Remove(i);
 585       idealreg2mhdebugmask[Op_RegL]->Remove(i);
 586       idealreg2mhdebugmask[Op_RegF]->Remove(i);
 587       idealreg2mhdebugmask[Op_RegD]->Remove(i);
 588       idealreg2mhdebugmask[Op_RegP]->Remove(i);
 589     }
 590   }
 591 
 592   // Subtract the register we use to save the SP for MethodHandle
 593   // invokes to from the debug mask.
 594   const RegMask save_mask = method_handle_invoke_SP_save_mask();
 595   idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
 596   idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
 597   idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
 598   idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
 599   idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
 600   idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
 601 }
 602 
 603 //---------------------------is_save_on_entry----------------------------------
 604 bool Matcher::is_save_on_entry( int reg ) {
 605   return
 606     _register_save_policy[reg] == 'E' ||
 607     _register_save_policy[reg] == 'A' || // Save-on-entry register?
 608     // Also save argument registers in the trampolining stubs
 609     (C->save_argument_registers() && is_spillable_arg(reg));
 610 }
 611 
 612 //---------------------------Fixup_Save_On_Entry-------------------------------
 613 void Matcher::Fixup_Save_On_Entry( ) {
 614   init_first_stack_mask();
 615 
 616   Node *root = C->root();       // Short name for root
 617   // Count number of save-on-entry registers.
 618   uint soe_cnt = number_of_saved_registers();
 619   uint i;
 620 
 621   // Find the procedure Start Node
 622   StartNode *start = C->start();
 623   assert( start, "Expect a start node" );
 624 
 625   // Save argument registers in the trampolining stubs
 626   if( C->save_argument_registers() )
 627     for( i = 0; i < _last_Mach_Reg; i++ )
 628       if( is_spillable_arg(i) )
 629         soe_cnt++;
 630 
 631   // Input RegMask array shared by all Returns.
 632   // The type for doubles and longs has a count of 2, but
 633   // there is only 1 returned value
 634   uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
 635   RegMask *ret_rms  = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 636   // Returns have 0 or 1 returned values depending on call signature.
 637   // Return register is specified by return_value in the AD file.
 638   if (ret_edge_cnt > TypeFunc::Parms)
 639     ret_rms[TypeFunc::Parms+0] = _return_value_mask;
 640 
 641   // Input RegMask array shared by all Rethrows.
 642   uint reth_edge_cnt = TypeFunc::Parms+1;
 643   RegMask *reth_rms  = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 644   // Rethrow takes exception oop only, but in the argument 0 slot.
 645   reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
 646 #ifdef _LP64
 647   // Need two slots for ptrs in 64-bit land
 648   reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
 649 #endif
 650 
 651   // Input RegMask array shared by all TailCalls
 652   uint tail_call_edge_cnt = TypeFunc::Parms+2;
 653   RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 654 
 655   // Input RegMask array shared by all TailJumps
 656   uint tail_jump_edge_cnt = TypeFunc::Parms+2;
 657   RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 658 
 659   // TailCalls have 2 returned values (target & moop), whose masks come
 660   // from the usual MachNode/MachOper mechanism.  Find a sample
 661   // TailCall to extract these masks and put the correct masks into
 662   // the tail_call_rms array.
 663   for( i=1; i < root->req(); i++ ) {
 664     MachReturnNode *m = root->in(i)->as_MachReturn();
 665     if( m->ideal_Opcode() == Op_TailCall ) {
 666       tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
 667       tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
 668       break;
 669     }
 670   }
 671 
 672   // TailJumps have 2 returned values (target & ex_oop), whose masks come
 673   // from the usual MachNode/MachOper mechanism.  Find a sample
 674   // TailJump to extract these masks and put the correct masks into
 675   // the tail_jump_rms array.
 676   for( i=1; i < root->req(); i++ ) {
 677     MachReturnNode *m = root->in(i)->as_MachReturn();
 678     if( m->ideal_Opcode() == Op_TailJump ) {
 679       tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
 680       tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
 681       break;
 682     }
 683   }
 684 
 685   // Input RegMask array shared by all Halts
 686   uint halt_edge_cnt = TypeFunc::Parms;
 687   RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 688 
 689   // Capture the return input masks into each exit flavor
 690   for( i=1; i < root->req(); i++ ) {
 691     MachReturnNode *exit = root->in(i)->as_MachReturn();
 692     switch( exit->ideal_Opcode() ) {
 693       case Op_Return   : exit->_in_rms = ret_rms;  break;
 694       case Op_Rethrow  : exit->_in_rms = reth_rms; break;
 695       case Op_TailCall : exit->_in_rms = tail_call_rms; break;
 696       case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
 697       case Op_Halt     : exit->_in_rms = halt_rms; break;
 698       default          : ShouldNotReachHere();
 699     }
 700   }
 701 
 702   // Next unused projection number from Start.
 703   int proj_cnt = C->tf()->domain()->cnt();
 704 
 705   // Do all the save-on-entry registers.  Make projections from Start for
 706   // them, and give them a use at the exit points.  To the allocator, they
 707   // look like incoming register arguments.
 708   for( i = 0; i < _last_Mach_Reg; i++ ) {
 709     if( is_save_on_entry(i) ) {
 710 
 711       // Add the save-on-entry to the mask array
 712       ret_rms      [      ret_edge_cnt] = mreg2regmask[i];
 713       reth_rms     [     reth_edge_cnt] = mreg2regmask[i];
 714       tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
 715       tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
 716       // Halts need the SOE registers, but only in the stack as debug info.
 717       // A just-prior uncommon-trap or deoptimization will use the SOE regs.
 718       halt_rms     [     halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
 719 
 720       Node *mproj;
 721 
 722       // Is this a RegF low half of a RegD?  Double up 2 adjacent RegF's
 723       // into a single RegD.
 724       if( (i&1) == 0 &&
 725           _register_save_type[i  ] == Op_RegF &&
 726           _register_save_type[i+1] == Op_RegF &&
 727           is_save_on_entry(i+1) ) {
 728         // Add other bit for double
 729         ret_rms      [      ret_edge_cnt].Insert(OptoReg::Name(i+1));
 730         reth_rms     [     reth_edge_cnt].Insert(OptoReg::Name(i+1));
 731         tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
 732         tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
 733         halt_rms     [     halt_edge_cnt].Insert(OptoReg::Name(i+1));
 734         mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
 735         proj_cnt += 2;          // Skip 2 for doubles
 736       }
 737       else if( (i&1) == 1 &&    // Else check for high half of double
 738                _register_save_type[i-1] == Op_RegF &&
 739                _register_save_type[i  ] == Op_RegF &&
 740                is_save_on_entry(i-1) ) {
 741         ret_rms      [      ret_edge_cnt] = RegMask::Empty;
 742         reth_rms     [     reth_edge_cnt] = RegMask::Empty;
 743         tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
 744         tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
 745         halt_rms     [     halt_edge_cnt] = RegMask::Empty;
 746         mproj = C->top();
 747       }
 748       // Is this a RegI low half of a RegL?  Double up 2 adjacent RegI's
 749       // into a single RegL.
 750       else if( (i&1) == 0 &&
 751           _register_save_type[i  ] == Op_RegI &&
 752           _register_save_type[i+1] == Op_RegI &&
 753         is_save_on_entry(i+1) ) {
 754         // Add other bit for long
 755         ret_rms      [      ret_edge_cnt].Insert(OptoReg::Name(i+1));
 756         reth_rms     [     reth_edge_cnt].Insert(OptoReg::Name(i+1));
 757         tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
 758         tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
 759         halt_rms     [     halt_edge_cnt].Insert(OptoReg::Name(i+1));
 760         mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
 761         proj_cnt += 2;          // Skip 2 for longs
 762       }
 763       else if( (i&1) == 1 &&    // Else check for high half of long
 764                _register_save_type[i-1] == Op_RegI &&
 765                _register_save_type[i  ] == Op_RegI &&
 766                is_save_on_entry(i-1) ) {
 767         ret_rms      [      ret_edge_cnt] = RegMask::Empty;
 768         reth_rms     [     reth_edge_cnt] = RegMask::Empty;
 769         tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
 770         tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
 771         halt_rms     [     halt_edge_cnt] = RegMask::Empty;
 772         mproj = C->top();
 773       } else {
 774         // Make a projection for it off the Start
 775         mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
 776       }
 777 
 778       ret_edge_cnt ++;
 779       reth_edge_cnt ++;
 780       tail_call_edge_cnt ++;
 781       tail_jump_edge_cnt ++;
 782       halt_edge_cnt ++;
 783 
 784       // Add a use of the SOE register to all exit paths
 785       for( uint j=1; j < root->req(); j++ )
 786         root->in(j)->add_req(mproj);
 787     } // End of if a save-on-entry register
 788   } // End of for all machine registers
 789 }
 790 
 791 //------------------------------init_spill_mask--------------------------------
 792 void Matcher::init_spill_mask( Node *ret ) {
 793   if( idealreg2regmask[Op_RegI] ) return; // One time only init
 794 
 795   OptoReg::c_frame_pointer = c_frame_pointer();
 796   c_frame_ptr_mask = c_frame_pointer();
 797 #ifdef _LP64
 798   // pointers are twice as big
 799   c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
 800 #endif
 801 
 802   // Start at OptoReg::stack0()
 803   STACK_ONLY_mask.Clear();
 804   OptoReg::Name init = OptoReg::stack2reg(0);
 805   // STACK_ONLY_mask is all stack bits
 806   OptoReg::Name i;
 807   for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
 808     STACK_ONLY_mask.Insert(i);
 809   // Also set the "infinite stack" bit.
 810   STACK_ONLY_mask.set_AllStack();
 811 
 812   // Copy the register names over into the shared world
 813   for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
 814     // SharedInfo::regName[i] = regName[i];
 815     // Handy RegMasks per machine register
 816     mreg2regmask[i].Insert(i);
 817   }
 818 
 819   // Grab the Frame Pointer
 820   Node *fp  = ret->in(TypeFunc::FramePtr);
 821   Node *mem = ret->in(TypeFunc::Memory);
 822   const TypePtr* atp = TypePtr::BOTTOM;
 823   // Share frame pointer while making spill ops
 824   set_shared(fp);
 825 
 826   // Compute generic short-offset Loads
 827 #ifdef _LP64
 828   MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
 829 #endif
 830   MachNode *spillI  = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
 831   MachNode *spillL  = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered,false));
 832   MachNode *spillF  = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
 833   MachNode *spillD  = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
 834   MachNode *spillP  = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
 835   assert(spillI != NULL && spillL != NULL && spillF != NULL &&
 836          spillD != NULL && spillP != NULL, "");
 837   // Get the ADLC notion of the right regmask, for each basic type.
 838 #ifdef _LP64
 839   idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
 840 #endif
 841   idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
 842   idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
 843   idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
 844   idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
 845   idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
 846 
 847   // Vector regmasks.
 848   if (Matcher::vector_size_supported(T_BYTE,4)) {
 849     TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
 850     MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
 851     idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
 852   }
 853   if (Matcher::vector_size_supported(T_FLOAT,2)) {
 854     MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
 855     idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
 856   }
 857   if (Matcher::vector_size_supported(T_FLOAT,4)) {
 858     MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
 859     idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
 860   }
 861   if (Matcher::vector_size_supported(T_FLOAT,8)) {
 862     MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
 863     idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
 864   }
 865 }
 866 
 867 #ifdef ASSERT
 868 static void match_alias_type(Compile* C, Node* n, Node* m) {
 869   if (!VerifyAliases)  return;  // do not go looking for trouble by default
 870   const TypePtr* nat = n->adr_type();
 871   const TypePtr* mat = m->adr_type();
 872   int nidx = C->get_alias_index(nat);
 873   int midx = C->get_alias_index(mat);
 874   // Detune the assert for cases like (AndI 0xFF (LoadB p)).
 875   if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
 876     for (uint i = 1; i < n->req(); i++) {
 877       Node* n1 = n->in(i);
 878       const TypePtr* n1at = n1->adr_type();
 879       if (n1at != NULL) {
 880         nat = n1at;
 881         nidx = C->get_alias_index(n1at);
 882       }
 883     }
 884   }
 885   // %%% Kludgery.  Instead, fix ideal adr_type methods for all these cases:
 886   if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
 887     switch (n->Opcode()) {
 888     case Op_PrefetchAllocation:
 889       nidx = Compile::AliasIdxRaw;
 890       nat = TypeRawPtr::BOTTOM;
 891       break;
 892     }
 893   }
 894   if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
 895     switch (n->Opcode()) {
 896     case Op_ClearArray:
 897       midx = Compile::AliasIdxRaw;
 898       mat = TypeRawPtr::BOTTOM;
 899       break;
 900     }
 901   }
 902   if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
 903     switch (n->Opcode()) {
 904     case Op_Return:
 905     case Op_Rethrow:
 906     case Op_Halt:
 907     case Op_TailCall:
 908     case Op_TailJump:
 909       nidx = Compile::AliasIdxBot;
 910       nat = TypePtr::BOTTOM;
 911       break;
 912     }
 913   }
 914   if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
 915     switch (n->Opcode()) {
 916     case Op_StrComp:
 917     case Op_StrEquals:
 918     case Op_StrIndexOf:
 919     case Op_AryEq:
 920     case Op_MemBarVolatile:
 921     case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
 922     case Op_EncodeISOArray:
 923       nidx = Compile::AliasIdxTop;
 924       nat = NULL;
 925       break;
 926     }
 927   }
 928   if (nidx != midx) {
 929     if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
 930       tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
 931       n->dump();
 932       m->dump();
 933     }
 934     assert(C->subsume_loads() && C->must_alias(nat, midx),
 935            "must not lose alias info when matching");
 936   }
 937 }
 938 #endif
 939 
 940 
 941 //------------------------------MStack-----------------------------------------
 942 // State and MStack class used in xform() and find_shared() iterative methods.
 943 enum Node_State { Pre_Visit,  // node has to be pre-visited
 944                       Visit,  // visit node
 945                  Post_Visit,  // post-visit node
 946              Alt_Post_Visit   // alternative post-visit path
 947                 };
 948 
 949 class MStack: public Node_Stack {
 950   public:
 951     MStack(int size) : Node_Stack(size) { }
 952 
 953     void push(Node *n, Node_State ns) {
 954       Node_Stack::push(n, (uint)ns);
 955     }
 956     void push(Node *n, Node_State ns, Node *parent, int indx) {
 957       ++_inode_top;
 958       if ((_inode_top + 1) >= _inode_max) grow();
 959       _inode_top->node = parent;
 960       _inode_top->indx = (uint)indx;
 961       ++_inode_top;
 962       _inode_top->node = n;
 963       _inode_top->indx = (uint)ns;
 964     }
 965     Node *parent() {
 966       pop();
 967       return node();
 968     }
 969     Node_State state() const {
 970       return (Node_State)index();
 971     }
 972     void set_state(Node_State ns) {
 973       set_index((uint)ns);
 974     }
 975 };
 976 
 977 
 978 //------------------------------xform------------------------------------------
 979 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
 980 // Node in new-space.  Given a new-space Node, recursively walk his children.
 981 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
 982 Node *Matcher::xform( Node *n, int max_stack ) {
 983   // Use one stack to keep both: child's node/state and parent's node/index
 984   MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2
 985   mstack.push(n, Visit, NULL, -1);  // set NULL as parent to indicate root
 986 
 987   while (mstack.is_nonempty()) {
 988     C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
 989     if (C->failing()) return NULL;
 990     n = mstack.node();          // Leave node on stack
 991     Node_State nstate = mstack.state();
 992     if (nstate == Visit) {
 993       mstack.set_state(Post_Visit);
 994       Node *oldn = n;
 995       // Old-space or new-space check
 996       if (!C->node_arena()->contains(n)) {
 997         // Old space!
 998         Node* m;
 999         if (has_new_node(n)) {  // Not yet Label/Reduced
1000           m = new_node(n);
1001         } else {
1002           if (!is_dontcare(n)) { // Matcher can match this guy
1003             // Calls match special.  They match alone with no children.
1004             // Their children, the incoming arguments, match normally.
1005             m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1006             if (C->failing())  return NULL;
1007             if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1008           } else {                  // Nothing the matcher cares about
1009             if( n->is_Proj() && n->in(0)->is_Multi()) {       // Projections?
1010               // Convert to machine-dependent projection
1011               m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1012 #ifdef ASSERT
1013               _new2old_map.map(m->_idx, n);
1014 #endif
1015               if (m->in(0) != NULL) // m might be top
1016                 collect_null_checks(m, n);
1017             } else {                // Else just a regular 'ol guy
1018               m = n->clone();       // So just clone into new-space
1019 #ifdef ASSERT
1020               _new2old_map.map(m->_idx, n);
1021 #endif
1022               // Def-Use edges will be added incrementally as Uses
1023               // of this node are matched.
1024               assert(m->outcnt() == 0, "no Uses of this clone yet");
1025             }
1026           }
1027 
1028           set_new_node(n, m);       // Map old to new
1029           if (_old_node_note_array != NULL) {
1030             Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1031                                                   n->_idx);
1032             C->set_node_notes_at(m->_idx, nn);
1033           }
1034           debug_only(match_alias_type(C, n, m));
1035         }
1036         n = m;    // n is now a new-space node
1037         mstack.set_node(n);
1038       }
1039 
1040       // New space!
1041       if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1042 
1043       int i;
1044       // Put precedence edges on stack first (match them last).
1045       for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1046         Node *m = oldn->in(i);
1047         if (m == NULL) break;
1048         // set -1 to call add_prec() instead of set_req() during Step1
1049         mstack.push(m, Visit, n, -1);
1050       }
1051 
1052       // For constant debug info, I'd rather have unmatched constants.
1053       int cnt = n->req();
1054       JVMState* jvms = n->jvms();
1055       int debug_cnt = jvms ? jvms->debug_start() : cnt;
1056 
1057       // Now do only debug info.  Clone constants rather than matching.
1058       // Constants are represented directly in the debug info without
1059       // the need for executable machine instructions.
1060       // Monitor boxes are also represented directly.
1061       for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1062         Node *m = n->in(i);          // Get input
1063         int op = m->Opcode();
1064         assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1065         if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1066             op == Op_ConF || op == Op_ConD || op == Op_ConL
1067             // || op == Op_BoxLock  // %%%% enable this and remove (+++) in chaitin.cpp
1068             ) {
1069           m = m->clone();
1070 #ifdef ASSERT
1071           _new2old_map.map(m->_idx, n);
1072 #endif
1073           mstack.push(m, Post_Visit, n, i); // Don't need to visit
1074           mstack.push(m->in(0), Visit, m, 0);
1075         } else {
1076           mstack.push(m, Visit, n, i);
1077         }
1078       }
1079 
1080       // And now walk his children, and convert his inputs to new-space.
1081       for( ; i >= 0; --i ) { // For all normal inputs do
1082         Node *m = n->in(i);  // Get input
1083         if(m != NULL)
1084           mstack.push(m, Visit, n, i);
1085       }
1086 
1087     }
1088     else if (nstate == Post_Visit) {
1089       // Set xformed input
1090       Node *p = mstack.parent();
1091       if (p != NULL) { // root doesn't have parent
1092         int i = (int)mstack.index();
1093         if (i >= 0)
1094           p->set_req(i, n); // required input
1095         else if (i == -1)
1096           p->add_prec(n);   // precedence input
1097         else
1098           ShouldNotReachHere();
1099       }
1100       mstack.pop(); // remove processed node from stack
1101     }
1102     else {
1103       ShouldNotReachHere();
1104     }
1105   } // while (mstack.is_nonempty())
1106   return n; // Return new-space Node
1107 }
1108 
1109 //------------------------------warp_outgoing_stk_arg------------------------
1110 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1111   // Convert outgoing argument location to a pre-biased stack offset
1112   if (reg->is_stack()) {
1113     OptoReg::Name warped = reg->reg2stack();
1114     // Adjust the stack slot offset to be the register number used
1115     // by the allocator.
1116     warped = OptoReg::add(begin_out_arg_area, warped);
1117     // Keep track of the largest numbered stack slot used for an arg.
1118     // Largest used slot per call-site indicates the amount of stack
1119     // that is killed by the call.
1120     if( warped >= out_arg_limit_per_call )
1121       out_arg_limit_per_call = OptoReg::add(warped,1);
1122     if (!RegMask::can_represent_arg(warped)) {
1123       C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1124       return OptoReg::Bad;
1125     }
1126     return warped;
1127   }
1128   return OptoReg::as_OptoReg(reg);
1129 }
1130 
1131 
1132 //------------------------------match_sfpt-------------------------------------
1133 // Helper function to match call instructions.  Calls match special.
1134 // They match alone with no children.  Their children, the incoming
1135 // arguments, match normally.
1136 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1137   MachSafePointNode *msfpt = NULL;
1138   MachCallNode      *mcall = NULL;
1139   uint               cnt;
1140   // Split out case for SafePoint vs Call
1141   CallNode *call;
1142   const TypeTuple *domain;
1143   ciMethod*        method = NULL;
1144   bool             is_method_handle_invoke = false;  // for special kill effects
1145   if( sfpt->is_Call() ) {
1146     call = sfpt->as_Call();
1147     domain = call->tf()->domain();
1148     cnt = domain->cnt();
1149 
1150     // Match just the call, nothing else
1151     MachNode *m = match_tree(call);
1152     if (C->failing())  return NULL;
1153     if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1154 
1155     // Copy data from the Ideal SafePoint to the machine version
1156     mcall = m->as_MachCall();
1157 
1158     mcall->set_tf(         call->tf());
1159     mcall->set_entry_point(call->entry_point());
1160     mcall->set_cnt(        call->cnt());
1161 
1162     if( mcall->is_MachCallJava() ) {
1163       MachCallJavaNode *mcall_java  = mcall->as_MachCallJava();
1164       const CallJavaNode *call_java =  call->as_CallJava();
1165       method = call_java->method();
1166       mcall_java->_method = method;
1167       mcall_java->_bci = call_java->_bci;
1168       mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1169       is_method_handle_invoke = call_java->is_method_handle_invoke();
1170       mcall_java->_method_handle_invoke = is_method_handle_invoke;
1171       if (is_method_handle_invoke) {
1172         C->set_has_method_handle_invokes(true);
1173       }
1174       if( mcall_java->is_MachCallStaticJava() )
1175         mcall_java->as_MachCallStaticJava()->_name =
1176          call_java->as_CallStaticJava()->_name;
1177       if( mcall_java->is_MachCallDynamicJava() )
1178         mcall_java->as_MachCallDynamicJava()->_vtable_index =
1179          call_java->as_CallDynamicJava()->_vtable_index;
1180     }
1181     else if( mcall->is_MachCallRuntime() ) {
1182       mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1183     }
1184     msfpt = mcall;
1185   }
1186   // This is a non-call safepoint
1187   else {
1188     call = NULL;
1189     domain = NULL;
1190     MachNode *mn = match_tree(sfpt);
1191     if (C->failing())  return NULL;
1192     msfpt = mn->as_MachSafePoint();
1193     cnt = TypeFunc::Parms;
1194   }
1195 
1196   // Advertise the correct memory effects (for anti-dependence computation).
1197   msfpt->set_adr_type(sfpt->adr_type());
1198 
1199   // Allocate a private array of RegMasks.  These RegMasks are not shared.
1200   msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1201   // Empty them all.
1202   memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1203 
1204   // Do all the pre-defined non-Empty register masks
1205   msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1206   msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1207 
1208   // Place first outgoing argument can possibly be put.
1209   OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1210   assert( is_even(begin_out_arg_area), "" );
1211   // Compute max outgoing register number per call site.
1212   OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1213   // Calls to C may hammer extra stack slots above and beyond any arguments.
1214   // These are usually backing store for register arguments for varargs.
1215   if( call != NULL && call->is_CallRuntime() )
1216     out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1217 
1218 
1219   // Do the normal argument list (parameters) register masks
1220   int argcnt = cnt - TypeFunc::Parms;
1221   if( argcnt > 0 ) {          // Skip it all if we have no args
1222     BasicType *sig_bt  = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1223     VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1224     int i;
1225     for( i = 0; i < argcnt; i++ ) {
1226       sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1227     }
1228     // V-call to pick proper calling convention
1229     call->calling_convention( sig_bt, parm_regs, argcnt );
1230 
1231 #ifdef ASSERT
1232     // Sanity check users' calling convention.  Really handy during
1233     // the initial porting effort.  Fairly expensive otherwise.
1234     { for (int i = 0; i<argcnt; i++) {
1235       if( !parm_regs[i].first()->is_valid() &&
1236           !parm_regs[i].second()->is_valid() ) continue;
1237       VMReg reg1 = parm_regs[i].first();
1238       VMReg reg2 = parm_regs[i].second();
1239       for (int j = 0; j < i; j++) {
1240         if( !parm_regs[j].first()->is_valid() &&
1241             !parm_regs[j].second()->is_valid() ) continue;
1242         VMReg reg3 = parm_regs[j].first();
1243         VMReg reg4 = parm_regs[j].second();
1244         if( !reg1->is_valid() ) {
1245           assert( !reg2->is_valid(), "valid halvsies" );
1246         } else if( !reg3->is_valid() ) {
1247           assert( !reg4->is_valid(), "valid halvsies" );
1248         } else {
1249           assert( reg1 != reg2, "calling conv. must produce distinct regs");
1250           assert( reg1 != reg3, "calling conv. must produce distinct regs");
1251           assert( reg1 != reg4, "calling conv. must produce distinct regs");
1252           assert( reg2 != reg3, "calling conv. must produce distinct regs");
1253           assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1254           assert( reg3 != reg4, "calling conv. must produce distinct regs");
1255         }
1256       }
1257     }
1258     }
1259 #endif
1260 
1261     // Visit each argument.  Compute its outgoing register mask.
1262     // Return results now can have 2 bits returned.
1263     // Compute max over all outgoing arguments both per call-site
1264     // and over the entire method.
1265     for( i = 0; i < argcnt; i++ ) {
1266       // Address of incoming argument mask to fill in
1267       RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1268       if( !parm_regs[i].first()->is_valid() &&
1269           !parm_regs[i].second()->is_valid() ) {
1270         continue;               // Avoid Halves
1271       }
1272       // Grab first register, adjust stack slots and insert in mask.
1273       OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1274       if (OptoReg::is_valid(reg1))
1275         rm->Insert( reg1 );
1276       // Grab second register (if any), adjust stack slots and insert in mask.
1277       OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1278       if (OptoReg::is_valid(reg2))
1279         rm->Insert( reg2 );
1280     } // End of for all arguments
1281 
1282     // Compute number of stack slots needed to restore stack in case of
1283     // Pascal-style argument popping.
1284     mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1285   }
1286 
1287   // Compute the max stack slot killed by any call.  These will not be
1288   // available for debug info, and will be used to adjust FIRST_STACK_mask
1289   // after all call sites have been visited.
1290   if( _out_arg_limit < out_arg_limit_per_call)
1291     _out_arg_limit = out_arg_limit_per_call;
1292 
1293   if (mcall) {
1294     // Kill the outgoing argument area, including any non-argument holes and
1295     // any legacy C-killed slots.  Use Fat-Projections to do the killing.
1296     // Since the max-per-method covers the max-per-call-site and debug info
1297     // is excluded on the max-per-method basis, debug info cannot land in
1298     // this killed area.
1299     uint r_cnt = mcall->tf()->range()->cnt();
1300     MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1301     if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1302       C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1303     } else {
1304       for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1305         proj->_rout.Insert(OptoReg::Name(i));
1306     }
1307     if (proj->_rout.is_NotEmpty()) {
1308       push_projection(proj);
1309     }
1310   }
1311   // Transfer the safepoint information from the call to the mcall
1312   // Move the JVMState list
1313   msfpt->set_jvms(sfpt->jvms());
1314   for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1315     jvms->set_map(sfpt);
1316   }
1317 
1318   // Debug inputs begin just after the last incoming parameter
1319   assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1320          (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1321 
1322   // Move the OopMap
1323   msfpt->_oop_map = sfpt->_oop_map;
1324 
1325   // Add additional edges.
1326   if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1327     // For these calls we can not add MachConstantBase in expand(), as the
1328     // ins are not complete then.
1329     msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1330     if (msfpt->jvms() &&
1331         msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1332       // We added an edge before jvms, so we must adapt the position of the ins.
1333       msfpt->jvms()->adapt_position(+1);
1334     }
1335   }
1336 
1337   // Registers killed by the call are set in the local scheduling pass
1338   // of Global Code Motion.
1339   return msfpt;
1340 }
1341 
1342 //---------------------------match_tree----------------------------------------
1343 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce.  Used as part
1344 // of the whole-sale conversion from Ideal to Mach Nodes.  Also used for
1345 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1346 // a Load's result RegMask for memoization in idealreg2regmask[]
1347 MachNode *Matcher::match_tree( const Node *n ) {
1348   assert( n->Opcode() != Op_Phi, "cannot match" );
1349   assert( !n->is_block_start(), "cannot match" );
1350   // Set the mark for all locally allocated State objects.
1351   // When this call returns, the _states_arena arena will be reset
1352   // freeing all State objects.
1353   ResourceMark rm( &_states_arena );
1354 
1355   LabelRootDepth = 0;
1356 
1357   // StoreNodes require their Memory input to match any LoadNodes
1358   Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1359 #ifdef ASSERT
1360   Node* save_mem_node = _mem_node;
1361   _mem_node = n->is_Store() ? (Node*)n : NULL;
1362 #endif
1363   // State object for root node of match tree
1364   // Allocate it on _states_arena - stack allocation can cause stack overflow.
1365   State *s = new (&_states_arena) State;
1366   s->_kids[0] = NULL;
1367   s->_kids[1] = NULL;
1368   s->_leaf = (Node*)n;
1369   // Label the input tree, allocating labels from top-level arena
1370   Label_Root( n, s, n->in(0), mem );
1371   if (C->failing())  return NULL;
1372 
1373   // The minimum cost match for the whole tree is found at the root State
1374   uint mincost = max_juint;
1375   uint cost = max_juint;
1376   uint i;
1377   for( i = 0; i < NUM_OPERANDS; i++ ) {
1378     if( s->valid(i) &&                // valid entry and
1379         s->_cost[i] < cost &&         // low cost and
1380         s->_rule[i] >= NUM_OPERANDS ) // not an operand
1381       cost = s->_cost[mincost=i];
1382   }
1383   if (mincost == max_juint) {
1384 #ifndef PRODUCT
1385     tty->print("No matching rule for:");
1386     s->dump();
1387 #endif
1388     Matcher::soft_match_failure();
1389     return NULL;
1390   }
1391   // Reduce input tree based upon the state labels to machine Nodes
1392   MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1393 #ifdef ASSERT
1394   _old2new_map.map(n->_idx, m);
1395   _new2old_map.map(m->_idx, (Node*)n);
1396 #endif
1397 
1398   // Add any Matcher-ignored edges
1399   uint cnt = n->req();
1400   uint start = 1;
1401   if( mem != (Node*)1 ) start = MemNode::Memory+1;
1402   if( n->is_AddP() ) {
1403     assert( mem == (Node*)1, "" );
1404     start = AddPNode::Base+1;
1405   }
1406   for( i = start; i < cnt; i++ ) {
1407     if( !n->match_edge(i) ) {
1408       if( i < m->req() )
1409         m->ins_req( i, n->in(i) );
1410       else
1411         m->add_req( n->in(i) );
1412     }
1413   }
1414 
1415   debug_only( _mem_node = save_mem_node; )
1416   return m;
1417 }
1418 
1419 
1420 //------------------------------match_into_reg---------------------------------
1421 // Choose to either match this Node in a register or part of the current
1422 // match tree.  Return true for requiring a register and false for matching
1423 // as part of the current match tree.
1424 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1425 
1426   const Type *t = m->bottom_type();
1427 
1428   if (t->singleton()) {
1429     // Never force constants into registers.  Allow them to match as
1430     // constants or registers.  Copies of the same value will share
1431     // the same register.  See find_shared_node.
1432     return false;
1433   } else {                      // Not a constant
1434     // Stop recursion if they have different Controls.
1435     Node* m_control = m->in(0);
1436     // Control of load's memory can post-dominates load's control.
1437     // So use it since load can't float above its memory.
1438     Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1439     if (control && m_control && control != m_control && control != mem_control) {
1440 
1441       // Actually, we can live with the most conservative control we
1442       // find, if it post-dominates the others.  This allows us to
1443       // pick up load/op/store trees where the load can float a little
1444       // above the store.
1445       Node *x = control;
1446       const uint max_scan = 6;  // Arbitrary scan cutoff
1447       uint j;
1448       for (j=0; j<max_scan; j++) {
1449         if (x->is_Region())     // Bail out at merge points
1450           return true;
1451         x = x->in(0);
1452         if (x == m_control)     // Does 'control' post-dominate
1453           break;                // m->in(0)?  If so, we can use it
1454         if (x == mem_control)   // Does 'control' post-dominate
1455           break;                // mem_control?  If so, we can use it
1456       }
1457       if (j == max_scan)        // No post-domination before scan end?
1458         return true;            // Then break the match tree up
1459     }
1460     if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1461         (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1462       // These are commonly used in address expressions and can
1463       // efficiently fold into them on X64 in some cases.
1464       return false;
1465     }
1466   }
1467 
1468   // Not forceable cloning.  If shared, put it into a register.
1469   return shared;
1470 }
1471 
1472 
1473 //------------------------------Instruction Selection--------------------------
1474 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1475 // ideal nodes to machine instructions.  Trees are delimited by shared Nodes,
1476 // things the Matcher does not match (e.g., Memory), and things with different
1477 // Controls (hence forced into different blocks).  We pass in the Control
1478 // selected for this entire State tree.
1479 
1480 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1481 // Store and the Load must have identical Memories (as well as identical
1482 // pointers).  Since the Matcher does not have anything for Memory (and
1483 // does not handle DAGs), I have to match the Memory input myself.  If the
1484 // Tree root is a Store, I require all Loads to have the identical memory.
1485 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1486   // Since Label_Root is a recursive function, its possible that we might run
1487   // out of stack space.  See bugs 6272980 & 6227033 for more info.
1488   LabelRootDepth++;
1489   if (LabelRootDepth > MaxLabelRootDepth) {
1490     C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1491     return NULL;
1492   }
1493   uint care = 0;                // Edges matcher cares about
1494   uint cnt = n->req();
1495   uint i = 0;
1496 
1497   // Examine children for memory state
1498   // Can only subsume a child into your match-tree if that child's memory state
1499   // is not modified along the path to another input.
1500   // It is unsafe even if the other inputs are separate roots.
1501   Node *input_mem = NULL;
1502   for( i = 1; i < cnt; i++ ) {
1503     if( !n->match_edge(i) ) continue;
1504     Node *m = n->in(i);         // Get ith input
1505     assert( m, "expect non-null children" );
1506     if( m->is_Load() ) {
1507       if( input_mem == NULL ) {
1508         input_mem = m->in(MemNode::Memory);
1509       } else if( input_mem != m->in(MemNode::Memory) ) {
1510         input_mem = NodeSentinel;
1511       }
1512     }
1513   }
1514 
1515   for( i = 1; i < cnt; i++ ){// For my children
1516     if( !n->match_edge(i) ) continue;
1517     Node *m = n->in(i);         // Get ith input
1518     // Allocate states out of a private arena
1519     State *s = new (&_states_arena) State;
1520     svec->_kids[care++] = s;
1521     assert( care <= 2, "binary only for now" );
1522 
1523     // Recursively label the State tree.
1524     s->_kids[0] = NULL;
1525     s->_kids[1] = NULL;
1526     s->_leaf = m;
1527 
1528     // Check for leaves of the State Tree; things that cannot be a part of
1529     // the current tree.  If it finds any, that value is matched as a
1530     // register operand.  If not, then the normal matching is used.
1531     if( match_into_reg(n, m, control, i, is_shared(m)) ||
1532         //
1533         // Stop recursion if this is LoadNode and the root of this tree is a
1534         // StoreNode and the load & store have different memories.
1535         ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1536         // Can NOT include the match of a subtree when its memory state
1537         // is used by any of the other subtrees
1538         (input_mem == NodeSentinel) ) {
1539 #ifndef PRODUCT
1540       // Print when we exclude matching due to different memory states at input-loads
1541       if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1542         && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1543         tty->print_cr("invalid input_mem");
1544       }
1545 #endif
1546       // Switch to a register-only opcode; this value must be in a register
1547       // and cannot be subsumed as part of a larger instruction.
1548       s->DFA( m->ideal_reg(), m );
1549 
1550     } else {
1551       // If match tree has no control and we do, adopt it for entire tree
1552       if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1553         control = m->in(0);         // Pick up control
1554       // Else match as a normal part of the match tree.
1555       control = Label_Root(m,s,control,mem);
1556       if (C->failing()) return NULL;
1557     }
1558   }
1559 
1560 
1561   // Call DFA to match this node, and return
1562   svec->DFA( n->Opcode(), n );
1563 
1564 #ifdef ASSERT
1565   uint x;
1566   for( x = 0; x < _LAST_MACH_OPER; x++ )
1567     if( svec->valid(x) )
1568       break;
1569 
1570   if (x >= _LAST_MACH_OPER) {
1571     n->dump();
1572     svec->dump();
1573     assert( false, "bad AD file" );
1574   }
1575 #endif
1576   return control;
1577 }
1578 
1579 
1580 // Con nodes reduced using the same rule can share their MachNode
1581 // which reduces the number of copies of a constant in the final
1582 // program.  The register allocator is free to split uses later to
1583 // split live ranges.
1584 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1585   if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1586 
1587   // See if this Con has already been reduced using this rule.
1588   if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1589   MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1590   if (last != NULL && rule == last->rule()) {
1591     // Don't expect control change for DecodeN
1592     if (leaf->is_DecodeNarrowPtr())
1593       return last;
1594     // Get the new space root.
1595     Node* xroot = new_node(C->root());
1596     if (xroot == NULL) {
1597       // This shouldn't happen give the order of matching.
1598       return NULL;
1599     }
1600 
1601     // Shared constants need to have their control be root so they
1602     // can be scheduled properly.
1603     Node* control = last->in(0);
1604     if (control != xroot) {
1605       if (control == NULL || control == C->root()) {
1606         last->set_req(0, xroot);
1607       } else {
1608         assert(false, "unexpected control");
1609         return NULL;
1610       }
1611     }
1612     return last;
1613   }
1614   return NULL;
1615 }
1616 
1617 
1618 //------------------------------ReduceInst-------------------------------------
1619 // Reduce a State tree (with given Control) into a tree of MachNodes.
1620 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1621 // complicated machine Nodes.  Each MachNode covers some tree of Ideal Nodes.
1622 // Each MachNode has a number of complicated MachOper operands; each
1623 // MachOper also covers a further tree of Ideal Nodes.
1624 
1625 // The root of the Ideal match tree is always an instruction, so we enter
1626 // the recursion here.  After building the MachNode, we need to recurse
1627 // the tree checking for these cases:
1628 // (1) Child is an instruction -
1629 //     Build the instruction (recursively), add it as an edge.
1630 //     Build a simple operand (register) to hold the result of the instruction.
1631 // (2) Child is an interior part of an instruction -
1632 //     Skip over it (do nothing)
1633 // (3) Child is the start of a operand -
1634 //     Build the operand, place it inside the instruction
1635 //     Call ReduceOper.
1636 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1637   assert( rule >= NUM_OPERANDS, "called with operand rule" );
1638 
1639   MachNode* shared_node = find_shared_node(s->_leaf, rule);
1640   if (shared_node != NULL) {
1641     return shared_node;
1642   }
1643 
1644   // Build the object to represent this state & prepare for recursive calls
1645   MachNode *mach = s->MachNodeGenerator(rule);
1646   mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1647   assert( mach->_opnds[0] != NULL, "Missing result operand" );
1648   Node *leaf = s->_leaf;
1649   // Check for instruction or instruction chain rule
1650   if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1651     assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1652            "duplicating node that's already been matched");
1653     // Instruction
1654     mach->add_req( leaf->in(0) ); // Set initial control
1655     // Reduce interior of complex instruction
1656     ReduceInst_Interior( s, rule, mem, mach, 1 );
1657   } else {
1658     // Instruction chain rules are data-dependent on their inputs
1659     mach->add_req(0);             // Set initial control to none
1660     ReduceInst_Chain_Rule( s, rule, mem, mach );
1661   }
1662 
1663   // If a Memory was used, insert a Memory edge
1664   if( mem != (Node*)1 ) {
1665     mach->ins_req(MemNode::Memory,mem);
1666 #ifdef ASSERT
1667     // Verify adr type after matching memory operation
1668     const MachOper* oper = mach->memory_operand();
1669     if (oper != NULL && oper != (MachOper*)-1) {
1670       // It has a unique memory operand.  Find corresponding ideal mem node.
1671       Node* m = NULL;
1672       if (leaf->is_Mem()) {
1673         m = leaf;
1674       } else {
1675         m = _mem_node;
1676         assert(m != NULL && m->is_Mem(), "expecting memory node");
1677       }
1678       const Type* mach_at = mach->adr_type();
1679       // DecodeN node consumed by an address may have different type
1680       // then its input. Don't compare types for such case.
1681       if (m->adr_type() != mach_at &&
1682           (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1683            m->in(MemNode::Address)->is_AddP() &&
1684            m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
1685            m->in(MemNode::Address)->is_AddP() &&
1686            m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1687            m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1688         mach_at = m->adr_type();
1689       }
1690       if (m->adr_type() != mach_at) {
1691         m->dump();
1692         tty->print_cr("mach:");
1693         mach->dump(1);
1694       }
1695       assert(m->adr_type() == mach_at, "matcher should not change adr type");
1696     }
1697 #endif
1698   }
1699 
1700   // If the _leaf is an AddP, insert the base edge
1701   if (leaf->is_AddP()) {
1702     mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1703   }
1704 
1705   uint number_of_projections_prior = number_of_projections();
1706 
1707   // Perform any 1-to-many expansions required
1708   MachNode *ex = mach->Expand(s, _projection_list, mem);
1709   if (ex != mach) {
1710     assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1711     if( ex->in(1)->is_Con() )
1712       ex->in(1)->set_req(0, C->root());
1713     // Remove old node from the graph
1714     for( uint i=0; i<mach->req(); i++ ) {
1715       mach->set_req(i,NULL);
1716     }
1717 #ifdef ASSERT
1718     _new2old_map.map(ex->_idx, s->_leaf);
1719 #endif
1720   }
1721 
1722   // PhaseChaitin::fixup_spills will sometimes generate spill code
1723   // via the matcher.  By the time, nodes have been wired into the CFG,
1724   // and any further nodes generated by expand rules will be left hanging
1725   // in space, and will not get emitted as output code.  Catch this.
1726   // Also, catch any new register allocation constraints ("projections")
1727   // generated belatedly during spill code generation.
1728   if (_allocation_started) {
1729     guarantee(ex == mach, "no expand rules during spill generation");
1730     guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1731   }
1732 
1733   if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1734     // Record the con for sharing
1735     _shared_nodes.map(leaf->_idx, ex);
1736   }
1737 
1738   return ex;
1739 }
1740 
1741 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1742   // 'op' is what I am expecting to receive
1743   int op = _leftOp[rule];
1744   // Operand type to catch childs result
1745   // This is what my child will give me.
1746   int opnd_class_instance = s->_rule[op];
1747   // Choose between operand class or not.
1748   // This is what I will receive.
1749   int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1750   // New rule for child.  Chase operand classes to get the actual rule.
1751   int newrule = s->_rule[catch_op];
1752 
1753   if( newrule < NUM_OPERANDS ) {
1754     // Chain from operand or operand class, may be output of shared node
1755     assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1756             "Bad AD file: Instruction chain rule must chain from operand");
1757     // Insert operand into array of operands for this instruction
1758     mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1759 
1760     ReduceOper( s, newrule, mem, mach );
1761   } else {
1762     // Chain from the result of an instruction
1763     assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1764     mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1765     Node *mem1 = (Node*)1;
1766     debug_only(Node *save_mem_node = _mem_node;)
1767     mach->add_req( ReduceInst(s, newrule, mem1) );
1768     debug_only(_mem_node = save_mem_node;)
1769   }
1770   return;
1771 }
1772 
1773 
1774 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1775   if( s->_leaf->is_Load() ) {
1776     Node *mem2 = s->_leaf->in(MemNode::Memory);
1777     assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1778     debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1779     mem = mem2;
1780   }
1781   if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1782     if( mach->in(0) == NULL )
1783       mach->set_req(0, s->_leaf->in(0));
1784   }
1785 
1786   // Now recursively walk the state tree & add operand list.
1787   for( uint i=0; i<2; i++ ) {   // binary tree
1788     State *newstate = s->_kids[i];
1789     if( newstate == NULL ) break;      // Might only have 1 child
1790     // 'op' is what I am expecting to receive
1791     int op;
1792     if( i == 0 ) {
1793       op = _leftOp[rule];
1794     } else {
1795       op = _rightOp[rule];
1796     }
1797     // Operand type to catch childs result
1798     // This is what my child will give me.
1799     int opnd_class_instance = newstate->_rule[op];
1800     // Choose between operand class or not.
1801     // This is what I will receive.
1802     int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1803     // New rule for child.  Chase operand classes to get the actual rule.
1804     int newrule = newstate->_rule[catch_op];
1805 
1806     if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1807       // Operand/operandClass
1808       // Insert operand into array of operands for this instruction
1809       mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
1810       ReduceOper( newstate, newrule, mem, mach );
1811 
1812     } else {                    // Child is internal operand or new instruction
1813       if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1814         // internal operand --> call ReduceInst_Interior
1815         // Interior of complex instruction.  Do nothing but recurse.
1816         num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1817       } else {
1818         // instruction --> call build operand(  ) to catch result
1819         //             --> ReduceInst( newrule )
1820         mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
1821         Node *mem1 = (Node*)1;
1822         debug_only(Node *save_mem_node = _mem_node;)
1823         mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1824         debug_only(_mem_node = save_mem_node;)
1825       }
1826     }
1827     assert( mach->_opnds[num_opnds-1], "" );
1828   }
1829   return num_opnds;
1830 }
1831 
1832 // This routine walks the interior of possible complex operands.
1833 // At each point we check our children in the match tree:
1834 // (1) No children -
1835 //     We are a leaf; add _leaf field as an input to the MachNode
1836 // (2) Child is an internal operand -
1837 //     Skip over it ( do nothing )
1838 // (3) Child is an instruction -
1839 //     Call ReduceInst recursively and
1840 //     and instruction as an input to the MachNode
1841 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1842   assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1843   State *kid = s->_kids[0];
1844   assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1845 
1846   // Leaf?  And not subsumed?
1847   if( kid == NULL && !_swallowed[rule] ) {
1848     mach->add_req( s->_leaf );  // Add leaf pointer
1849     return;                     // Bail out
1850   }
1851 
1852   if( s->_leaf->is_Load() ) {
1853     assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1854     mem = s->_leaf->in(MemNode::Memory);
1855     debug_only(_mem_node = s->_leaf;)
1856   }
1857   if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1858     if( !mach->in(0) )
1859       mach->set_req(0,s->_leaf->in(0));
1860     else {
1861       assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1862     }
1863   }
1864 
1865   for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) {   // binary tree
1866     int newrule;
1867     if( i == 0)
1868       newrule = kid->_rule[_leftOp[rule]];
1869     else
1870       newrule = kid->_rule[_rightOp[rule]];
1871 
1872     if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1873       // Internal operand; recurse but do nothing else
1874       ReduceOper( kid, newrule, mem, mach );
1875 
1876     } else {                    // Child is a new instruction
1877       // Reduce the instruction, and add a direct pointer from this
1878       // machine instruction to the newly reduced one.
1879       Node *mem1 = (Node*)1;
1880       debug_only(Node *save_mem_node = _mem_node;)
1881       mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1882       debug_only(_mem_node = save_mem_node;)
1883     }
1884   }
1885 }
1886 
1887 
1888 // -------------------------------------------------------------------------
1889 // Java-Java calling convention
1890 // (what you use when Java calls Java)
1891 
1892 //------------------------------find_receiver----------------------------------
1893 // For a given signature, return the OptoReg for parameter 0.
1894 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1895   VMRegPair regs;
1896   BasicType sig_bt = T_OBJECT;
1897   calling_convention(&sig_bt, &regs, 1, is_outgoing);
1898   // Return argument 0 register.  In the LP64 build pointers
1899   // take 2 registers, but the VM wants only the 'main' name.
1900   return OptoReg::as_OptoReg(regs.first());
1901 }
1902 
1903 // This function identifies sub-graphs in which a 'load' node is
1904 // input to two different nodes, and such that it can be matched
1905 // with BMI instructions like blsi, blsr, etc.
1906 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1907 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1908 // refers to the same node.
1909 #ifdef X86
1910 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1911 // This is a temporary solution until we make DAGs expressible in ADL.
1912 template<typename ConType>
1913 class FusedPatternMatcher {
1914   Node* _op1_node;
1915   Node* _mop_node;
1916   int _con_op;
1917 
1918   static int match_next(Node* n, int next_op, int next_op_idx) {
1919     if (n->in(1) == NULL || n->in(2) == NULL) {
1920       return -1;
1921     }
1922 
1923     if (next_op_idx == -1) { // n is commutative, try rotations
1924       if (n->in(1)->Opcode() == next_op) {
1925         return 1;
1926       } else if (n->in(2)->Opcode() == next_op) {
1927         return 2;
1928       }
1929     } else {
1930       assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1931       if (n->in(next_op_idx)->Opcode() == next_op) {
1932         return next_op_idx;
1933       }
1934     }
1935     return -1;
1936   }
1937 public:
1938   FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1939     _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1940 
1941   bool match(int op1, int op1_op2_idx,  // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1942              int op2, int op2_con_idx,  // op2 and the index of the op2->con edge, -1 if op2 is commutative
1943              typename ConType::NativeType con_value) {
1944     if (_op1_node->Opcode() != op1) {
1945       return false;
1946     }
1947     if (_mop_node->outcnt() > 2) {
1948       return false;
1949     }
1950     op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
1951     if (op1_op2_idx == -1) {
1952       return false;
1953     }
1954     // Memory operation must be the other edge
1955     int op1_mop_idx = (op1_op2_idx & 1) + 1;
1956 
1957     // Check that the mop node is really what we want
1958     if (_op1_node->in(op1_mop_idx) == _mop_node) {
1959       Node *op2_node = _op1_node->in(op1_op2_idx);
1960       if (op2_node->outcnt() > 1) {
1961         return false;
1962       }
1963       assert(op2_node->Opcode() == op2, "Should be");
1964       op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
1965       if (op2_con_idx == -1) {
1966         return false;
1967       }
1968       // Memory operation must be the other edge
1969       int op2_mop_idx = (op2_con_idx & 1) + 1;
1970       // Check that the memory operation is the same node
1971       if (op2_node->in(op2_mop_idx) == _mop_node) {
1972         // Now check the constant
1973         const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
1974         if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
1975           return true;
1976         }
1977       }
1978     }
1979     return false;
1980   }
1981 };
1982 
1983 
1984 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
1985   if (n != NULL && m != NULL) {
1986     if (m->Opcode() == Op_LoadI) {
1987       FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
1988       return bmii.match(Op_AndI, -1, Op_SubI,  1,  0)  ||
1989              bmii.match(Op_AndI, -1, Op_AddI, -1, -1)  ||
1990              bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
1991     } else if (m->Opcode() == Op_LoadL) {
1992       FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
1993       return bmil.match(Op_AndL, -1, Op_SubL,  1,  0) ||
1994              bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
1995              bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
1996     }
1997   }
1998   return false;
1999 }
2000 #endif // X86
2001 
2002 // A method-klass-holder may be passed in the inline_cache_reg
2003 // and then expanded into the inline_cache_reg and a method_oop register
2004 //   defined in ad_<arch>.cpp
2005 
2006 
2007 //------------------------------find_shared------------------------------------
2008 // Set bits if Node is shared or otherwise a root
2009 void Matcher::find_shared( Node *n ) {
2010   // Allocate stack of size C->unique() * 2 to avoid frequent realloc
2011   MStack mstack(C->unique() * 2);
2012   // Mark nodes as address_visited if they are inputs to an address expression
2013   VectorSet address_visited(Thread::current()->resource_area());
2014   mstack.push(n, Visit);     // Don't need to pre-visit root node
2015   while (mstack.is_nonempty()) {
2016     n = mstack.node();       // Leave node on stack
2017     Node_State nstate = mstack.state();
2018     uint nop = n->Opcode();
2019     if (nstate == Pre_Visit) {
2020       if (address_visited.test(n->_idx)) { // Visited in address already?
2021         // Flag as visited and shared now.
2022         set_visited(n);
2023       }
2024       if (is_visited(n)) {   // Visited already?
2025         // Node is shared and has no reason to clone.  Flag it as shared.
2026         // This causes it to match into a register for the sharing.
2027         set_shared(n);       // Flag as shared and
2028         mstack.pop();        // remove node from stack
2029         continue;
2030       }
2031       nstate = Visit; // Not already visited; so visit now
2032     }
2033     if (nstate == Visit) {
2034       mstack.set_state(Post_Visit);
2035       set_visited(n);   // Flag as visited now
2036       bool mem_op = false;
2037 
2038       switch( nop ) {  // Handle some opcodes special
2039       case Op_Phi:             // Treat Phis as shared roots
2040       case Op_Parm:
2041       case Op_Proj:            // All handled specially during matching
2042       case Op_SafePointScalarObject:
2043         set_shared(n);
2044         set_dontcare(n);
2045         break;
2046       case Op_If:
2047       case Op_CountedLoopEnd:
2048         mstack.set_state(Alt_Post_Visit); // Alternative way
2049         // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)).  Helps
2050         // with matching cmp/branch in 1 instruction.  The Matcher needs the
2051         // Bool and CmpX side-by-side, because it can only get at constants
2052         // that are at the leaves of Match trees, and the Bool's condition acts
2053         // as a constant here.
2054         mstack.push(n->in(1), Visit);         // Clone the Bool
2055         mstack.push(n->in(0), Pre_Visit);     // Visit control input
2056         continue; // while (mstack.is_nonempty())
2057       case Op_ConvI2D:         // These forms efficiently match with a prior
2058       case Op_ConvI2F:         //   Load but not a following Store
2059         if( n->in(1)->is_Load() &&        // Prior load
2060             n->outcnt() == 1 &&           // Not already shared
2061             n->unique_out()->is_Store() ) // Following store
2062           set_shared(n);       // Force it to be a root
2063         break;
2064       case Op_ReverseBytesI:
2065       case Op_ReverseBytesL:
2066         if( n->in(1)->is_Load() &&        // Prior load
2067             n->outcnt() == 1 )            // Not already shared
2068           set_shared(n);                  // Force it to be a root
2069         break;
2070       case Op_BoxLock:         // Cant match until we get stack-regs in ADLC
2071       case Op_IfFalse:
2072       case Op_IfTrue:
2073       case Op_MachProj:
2074       case Op_MergeMem:
2075       case Op_Catch:
2076       case Op_CatchProj:
2077       case Op_CProj:
2078       case Op_JumpProj:
2079       case Op_JProj:
2080       case Op_NeverBranch:
2081         set_dontcare(n);
2082         break;
2083       case Op_Jump:
2084         mstack.push(n->in(1), Pre_Visit);     // Switch Value (could be shared)
2085         mstack.push(n->in(0), Pre_Visit);     // Visit Control input
2086         continue;                             // while (mstack.is_nonempty())
2087       case Op_StrComp:
2088       case Op_StrEquals:
2089       case Op_StrIndexOf:
2090       case Op_AryEq:
2091       case Op_EncodeISOArray:
2092         set_shared(n); // Force result into register (it will be anyways)
2093         break;
2094       case Op_ConP: {  // Convert pointers above the centerline to NUL
2095         TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2096         const TypePtr* tp = tn->type()->is_ptr();
2097         if (tp->_ptr == TypePtr::AnyNull) {
2098           tn->set_type(TypePtr::NULL_PTR);
2099         }
2100         break;
2101       }
2102       case Op_ConN: {  // Convert narrow pointers above the centerline to NUL
2103         TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2104         const TypePtr* tp = tn->type()->make_ptr();
2105         if (tp && tp->_ptr == TypePtr::AnyNull) {
2106           tn->set_type(TypeNarrowOop::NULL_PTR);
2107         }
2108         break;
2109       }
2110       case Op_Binary:         // These are introduced in the Post_Visit state.
2111         ShouldNotReachHere();
2112         break;
2113       case Op_ClearArray:
2114       case Op_SafePoint:
2115         mem_op = true;
2116         break;
2117       default:
2118         if( n->is_Store() ) {
2119           // Do match stores, despite no ideal reg
2120           mem_op = true;
2121           break;
2122         }
2123         if( n->is_Mem() ) { // Loads and LoadStores
2124           mem_op = true;
2125           // Loads must be root of match tree due to prior load conflict
2126           if( C->subsume_loads() == false )
2127             set_shared(n);
2128         }
2129         // Fall into default case
2130         if( !n->ideal_reg() )
2131           set_dontcare(n);  // Unmatchable Nodes
2132       } // end_switch
2133 
2134       for(int i = n->req() - 1; i >= 0; --i) { // For my children
2135         Node *m = n->in(i); // Get ith input
2136         if (m == NULL) continue;  // Ignore NULLs
2137         uint mop = m->Opcode();
2138 
2139         // Must clone all producers of flags, or we will not match correctly.
2140         // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2141         // then it will match into an ideal Op_RegFlags.  Alas, the fp-flags
2142         // are also there, so we may match a float-branch to int-flags and
2143         // expect the allocator to haul the flags from the int-side to the
2144         // fp-side.  No can do.
2145         if( _must_clone[mop] ) {
2146           mstack.push(m, Visit);
2147           continue; // for(int i = ...)
2148         }
2149 
2150         if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2151           // Bases used in addresses must be shared but since
2152           // they are shared through a DecodeN they may appear
2153           // to have a single use so force sharing here.
2154           set_shared(m->in(AddPNode::Base)->in(1));
2155         }
2156 
2157         // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2158 #ifdef X86
2159         if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2160           mstack.push(m, Visit);
2161           continue;
2162         }
2163 #endif
2164 
2165         // Clone addressing expressions as they are "free" in memory access instructions
2166         if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
2167           // Some inputs for address expression are not put on stack
2168           // to avoid marking them as shared and forcing them into register
2169           // if they are used only in address expressions.
2170           // But they should be marked as shared if there are other uses
2171           // besides address expressions.
2172 
2173           Node *off = m->in(AddPNode::Offset);
2174           if( off->is_Con() &&
2175               // When there are other uses besides address expressions
2176               // put it on stack and mark as shared.
2177               !is_visited(m) ) {
2178             address_visited.test_set(m->_idx); // Flag as address_visited
2179             Node *adr = m->in(AddPNode::Address);
2180 
2181             // Intel, ARM and friends can handle 2 adds in addressing mode
2182             if( clone_shift_expressions && adr->is_AddP() &&
2183                 // AtomicAdd is not an addressing expression.
2184                 // Cheap to find it by looking for screwy base.
2185                 !adr->in(AddPNode::Base)->is_top() &&
2186                 // Are there other uses besides address expressions?
2187                 !is_visited(adr) ) {
2188               address_visited.set(adr->_idx); // Flag as address_visited
2189               Node *shift = adr->in(AddPNode::Offset);
2190               // Check for shift by small constant as well
2191               if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2192                   shift->in(2)->get_int() <= 3 &&
2193                   // Are there other uses besides address expressions?
2194                   !is_visited(shift) ) {
2195                 address_visited.set(shift->_idx); // Flag as address_visited
2196                 mstack.push(shift->in(2), Visit);
2197                 Node *conv = shift->in(1);
2198 #ifdef _LP64
2199                 // Allow Matcher to match the rule which bypass
2200                 // ConvI2L operation for an array index on LP64
2201                 // if the index value is positive.
2202                 if( conv->Opcode() == Op_ConvI2L &&
2203                     conv->as_Type()->type()->is_long()->_lo >= 0 &&
2204                     // Are there other uses besides address expressions?
2205                     !is_visited(conv) ) {
2206                   address_visited.set(conv->_idx); // Flag as address_visited
2207                   mstack.push(conv->in(1), Pre_Visit);
2208                 } else
2209 #endif
2210                 mstack.push(conv, Pre_Visit);
2211               } else {
2212                 mstack.push(shift, Pre_Visit);
2213               }
2214               mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2215               mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2216             } else {  // Sparc, Alpha, PPC and friends
2217               mstack.push(adr, Pre_Visit);
2218             }
2219 
2220             // Clone X+offset as it also folds into most addressing expressions
2221             mstack.push(off, Visit);
2222             mstack.push(m->in(AddPNode::Base), Pre_Visit);
2223             continue; // for(int i = ...)
2224           } // if( off->is_Con() )
2225         }   // if( mem_op &&
2226         mstack.push(m, Pre_Visit);
2227       }     // for(int i = ...)
2228     }
2229     else if (nstate == Alt_Post_Visit) {
2230       mstack.pop(); // Remove node from stack
2231       // We cannot remove the Cmp input from the Bool here, as the Bool may be
2232       // shared and all users of the Bool need to move the Cmp in parallel.
2233       // This leaves both the Bool and the If pointing at the Cmp.  To
2234       // prevent the Matcher from trying to Match the Cmp along both paths
2235       // BoolNode::match_edge always returns a zero.
2236 
2237       // We reorder the Op_If in a pre-order manner, so we can visit without
2238       // accidentally sharing the Cmp (the Bool and the If make 2 users).
2239       n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2240     }
2241     else if (nstate == Post_Visit) {
2242       mstack.pop(); // Remove node from stack
2243 
2244       // Now hack a few special opcodes
2245       switch( n->Opcode() ) {       // Handle some opcodes special
2246       case Op_StorePConditional:
2247       case Op_StoreIConditional:
2248       case Op_StoreLConditional:
2249       case Op_CompareAndSwapI:
2250       case Op_CompareAndSwapL:
2251       case Op_CompareAndSwapP:
2252       case Op_CompareAndSwapN: {   // Convert trinary to binary-tree
2253         Node *newval = n->in(MemNode::ValueIn );
2254         Node *oldval  = n->in(LoadStoreConditionalNode::ExpectedIn);
2255         Node *pair = new BinaryNode( oldval, newval );
2256         n->set_req(MemNode::ValueIn,pair);
2257         n->del_req(LoadStoreConditionalNode::ExpectedIn);
2258         break;
2259       }
2260       case Op_CMoveD:              // Convert trinary to binary-tree
2261       case Op_CMoveF:
2262       case Op_CMoveI:
2263       case Op_CMoveL:
2264       case Op_CMoveN:
2265       case Op_CMoveP: {
2266         // Restructure into a binary tree for Matching.  It's possible that
2267         // we could move this code up next to the graph reshaping for IfNodes
2268         // or vice-versa, but I do not want to debug this for Ladybird.
2269         // 10/2/2000 CNC.
2270         Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1));
2271         n->set_req(1,pair1);
2272         Node *pair2 = new BinaryNode(n->in(2),n->in(3));
2273         n->set_req(2,pair2);
2274         n->del_req(3);
2275         break;
2276       }
2277       case Op_LoopLimit: {
2278         Node *pair1 = new BinaryNode(n->in(1),n->in(2));
2279         n->set_req(1,pair1);
2280         n->set_req(2,n->in(3));
2281         n->del_req(3);
2282         break;
2283       }
2284       case Op_StrEquals: {
2285         Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2286         n->set_req(2,pair1);
2287         n->set_req(3,n->in(4));
2288         n->del_req(4);
2289         break;
2290       }
2291       case Op_StrComp:
2292       case Op_StrIndexOf: {
2293         Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2294         n->set_req(2,pair1);
2295         Node *pair2 = new BinaryNode(n->in(4),n->in(5));
2296         n->set_req(3,pair2);
2297         n->del_req(5);
2298         n->del_req(4);
2299         break;
2300       }
2301       case Op_EncodeISOArray: {
2302         // Restructure into a binary tree for Matching.
2303         Node* pair = new BinaryNode(n->in(3), n->in(4));
2304         n->set_req(3, pair);
2305         n->del_req(4);
2306         break;
2307       }
2308       default:
2309         break;
2310       }
2311     }
2312     else {
2313       ShouldNotReachHere();
2314     }
2315   } // end of while (mstack.is_nonempty())
2316 }
2317 
2318 #ifdef ASSERT
2319 // machine-independent root to machine-dependent root
2320 void Matcher::dump_old2new_map() {
2321   _old2new_map.dump();
2322 }
2323 #endif
2324 
2325 //---------------------------collect_null_checks-------------------------------
2326 // Find null checks in the ideal graph; write a machine-specific node for
2327 // it.  Used by later implicit-null-check handling.  Actually collects
2328 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2329 // value being tested.
2330 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2331   Node *iff = proj->in(0);
2332   if( iff->Opcode() == Op_If ) {
2333     // During matching If's have Bool & Cmp side-by-side
2334     BoolNode *b = iff->in(1)->as_Bool();
2335     Node *cmp = iff->in(2);
2336     int opc = cmp->Opcode();
2337     if (opc != Op_CmpP && opc != Op_CmpN) return;
2338 
2339     const Type* ct = cmp->in(2)->bottom_type();
2340     if (ct == TypePtr::NULL_PTR ||
2341         (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2342 
2343       bool push_it = false;
2344       if( proj->Opcode() == Op_IfTrue ) {
2345         extern int all_null_checks_found;
2346         all_null_checks_found++;
2347         if( b->_test._test == BoolTest::ne ) {
2348           push_it = true;
2349         }
2350       } else {
2351         assert( proj->Opcode() == Op_IfFalse, "" );
2352         if( b->_test._test == BoolTest::eq ) {
2353           push_it = true;
2354         }
2355       }
2356       if( push_it ) {
2357         _null_check_tests.push(proj);
2358         Node* val = cmp->in(1);
2359 #ifdef _LP64
2360         if (val->bottom_type()->isa_narrowoop() &&
2361             !Matcher::narrow_oop_use_complex_address()) {
2362           //
2363           // Look for DecodeN node which should be pinned to orig_proj.
2364           // On platforms (Sparc) which can not handle 2 adds
2365           // in addressing mode we have to keep a DecodeN node and
2366           // use it to do implicit NULL check in address.
2367           //
2368           // DecodeN node was pinned to non-null path (orig_proj) during
2369           // CastPP transformation in final_graph_reshaping_impl().
2370           //
2371           uint cnt = orig_proj->outcnt();
2372           for (uint i = 0; i < orig_proj->outcnt(); i++) {
2373             Node* d = orig_proj->raw_out(i);
2374             if (d->is_DecodeN() && d->in(1) == val) {
2375               val = d;
2376               val->set_req(0, NULL); // Unpin now.
2377               // Mark this as special case to distinguish from
2378               // a regular case: CmpP(DecodeN, NULL).
2379               val = (Node*)(((intptr_t)val) | 1);
2380               break;
2381             }
2382           }
2383         }
2384 #endif
2385         _null_check_tests.push(val);
2386       }
2387     }
2388   }
2389 }
2390 
2391 //---------------------------validate_null_checks------------------------------
2392 // Its possible that the value being NULL checked is not the root of a match
2393 // tree.  If so, I cannot use the value in an implicit null check.
2394 void Matcher::validate_null_checks( ) {
2395   uint cnt = _null_check_tests.size();
2396   for( uint i=0; i < cnt; i+=2 ) {
2397     Node *test = _null_check_tests[i];
2398     Node *val = _null_check_tests[i+1];
2399     bool is_decoden = ((intptr_t)val) & 1;
2400     val = (Node*)(((intptr_t)val) & ~1);
2401     if (has_new_node(val)) {
2402       Node* new_val = new_node(val);
2403       if (is_decoden) {
2404         assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2405         // Note: new_val may have a control edge if
2406         // the original ideal node DecodeN was matched before
2407         // it was unpinned in Matcher::collect_null_checks().
2408         // Unpin the mach node and mark it.
2409         new_val->set_req(0, NULL);
2410         new_val = (Node*)(((intptr_t)new_val) | 1);
2411       }
2412       // Is a match-tree root, so replace with the matched value
2413       _null_check_tests.map(i+1, new_val);
2414     } else {
2415       // Yank from candidate list
2416       _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2417       _null_check_tests.map(i,_null_check_tests[--cnt]);
2418       _null_check_tests.pop();
2419       _null_check_tests.pop();
2420       i-=2;
2421     }
2422   }
2423 }
2424 
2425 // Used by the DFA in dfa_xxx.cpp.  Check for a following barrier or
2426 // atomic instruction acting as a store_load barrier without any
2427 // intervening volatile load, and thus we don't need a barrier here.
2428 // We retain the Node to act as a compiler ordering barrier.
2429 bool Matcher::post_store_load_barrier(const Node* vmb) {
2430   Compile* C = Compile::current();
2431   assert(vmb->is_MemBar(), "");
2432   assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2433   const MemBarNode* membar = vmb->as_MemBar();
2434 
2435   // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2436   Node* ctrl = NULL;
2437   for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2438     Node* p = membar->fast_out(i);
2439     assert(p->is_Proj(), "only projections here");
2440     if ((p->as_Proj()->_con == TypeFunc::Control) &&
2441         !C->node_arena()->contains(p)) { // Unmatched old-space only
2442       ctrl = p;
2443       break;
2444     }
2445   }
2446   assert((ctrl != NULL), "missing control projection");
2447 
2448   for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2449     Node *x = ctrl->fast_out(j);
2450     int xop = x->Opcode();
2451 
2452     // We don't need current barrier if we see another or a lock
2453     // before seeing volatile load.
2454     //
2455     // Op_Fastunlock previously appeared in the Op_* list below.
2456     // With the advent of 1-0 lock operations we're no longer guaranteed
2457     // that a monitor exit operation contains a serializing instruction.
2458 
2459     if (xop == Op_MemBarVolatile ||
2460         xop == Op_CompareAndSwapL ||
2461         xop == Op_CompareAndSwapP ||
2462         xop == Op_CompareAndSwapN ||
2463         xop == Op_CompareAndSwapI) {
2464       return true;
2465     }
2466 
2467     // Op_FastLock previously appeared in the Op_* list above.
2468     // With biased locking we're no longer guaranteed that a monitor
2469     // enter operation contains a serializing instruction.
2470     if ((xop == Op_FastLock) && !UseBiasedLocking) {
2471       return true;
2472     }
2473 
2474     if (x->is_MemBar()) {
2475       // We must retain this membar if there is an upcoming volatile
2476       // load, which will be followed by acquire membar.
2477       if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2478         return false;
2479       } else {
2480         // For other kinds of barriers, check by pretending we
2481         // are them, and seeing if we can be removed.
2482         return post_store_load_barrier(x->as_MemBar());
2483       }
2484     }
2485 
2486     // probably not necessary to check for these
2487     if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2488       return false;
2489     }
2490   }
2491   return false;
2492 }
2493 
2494 // Check whether node n is a branch to an uncommon trap that we could
2495 // optimize as test with very high branch costs in case of going to
2496 // the uncommon trap. The code must be able to be recompiled to use
2497 // a cheaper test.
2498 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2499   // Don't do it for natives, adapters, or runtime stubs
2500   Compile *C = Compile::current();
2501   if (!C->is_method_compilation()) return false;
2502 
2503   assert(n->is_If(), "You should only call this on if nodes.");
2504   IfNode *ifn = n->as_If();
2505 
2506   Node *ifFalse = NULL;
2507   for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2508     if (ifn->fast_out(i)->is_IfFalse()) {
2509       ifFalse = ifn->fast_out(i);
2510       break;
2511     }
2512   }
2513   assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2514 
2515   Node *reg = ifFalse;
2516   int cnt = 4; // We must protect against cycles.  Limit to 4 iterations.
2517                // Alternatively use visited set?  Seems too expensive.
2518   while (reg != NULL && cnt > 0) {
2519     CallNode *call = NULL;
2520     RegionNode *nxt_reg = NULL;
2521     for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2522       Node *o = reg->fast_out(i);
2523       if (o->is_Call()) {
2524         call = o->as_Call();
2525       }
2526       if (o->is_Region()) {
2527         nxt_reg = o->as_Region();
2528       }
2529     }
2530 
2531     if (call &&
2532         call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2533       const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2534       if (trtype->isa_int() && trtype->is_int()->is_con()) {
2535         jint tr_con = trtype->is_int()->get_con();
2536         Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2537         Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2538         assert((int)reason < (int)BitsPerInt, "recode bit map");
2539 
2540         if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2541             && action != Deoptimization::Action_none) {
2542           // This uncommon trap is sure to recompile, eventually.
2543           // When that happens, C->too_many_traps will prevent
2544           // this transformation from happening again.
2545           return true;
2546         }
2547       }
2548     }
2549 
2550     reg = nxt_reg;
2551     cnt--;
2552   }
2553 
2554   return false;
2555 }
2556 
2557 //=============================================================================
2558 //---------------------------State---------------------------------------------
2559 State::State(void) {
2560 #ifdef ASSERT
2561   _id = 0;
2562   _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2563   _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2564   //memset(_cost, -1, sizeof(_cost));
2565   //memset(_rule, -1, sizeof(_rule));
2566 #endif
2567   memset(_valid, 0, sizeof(_valid));
2568 }
2569 
2570 #ifdef ASSERT
2571 State::~State() {
2572   _id = 99;
2573   _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2574   _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2575   memset(_cost, -3, sizeof(_cost));
2576   memset(_rule, -3, sizeof(_rule));
2577 }
2578 #endif
2579 
2580 #ifndef PRODUCT
2581 //---------------------------dump----------------------------------------------
2582 void State::dump() {
2583   tty->print("\n");
2584   dump(0);
2585 }
2586 
2587 void State::dump(int depth) {
2588   for( int j = 0; j < depth; j++ )
2589     tty->print("   ");
2590   tty->print("--N: ");
2591   _leaf->dump();
2592   uint i;
2593   for( i = 0; i < _LAST_MACH_OPER; i++ )
2594     // Check for valid entry
2595     if( valid(i) ) {
2596       for( int j = 0; j < depth; j++ )
2597         tty->print("   ");
2598         assert(_cost[i] != max_juint, "cost must be a valid value");
2599         assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2600         tty->print_cr("%s  %d  %s",
2601                       ruleName[i], _cost[i], ruleName[_rule[i]] );
2602       }
2603   tty->cr();
2604 
2605   for( i=0; i<2; i++ )
2606     if( _kids[i] )
2607       _kids[i]->dump(depth+1);
2608 }
2609 #endif