1 /*
   2  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "memory/allocation.inline.hpp"
  27 #include "opto/ad.hpp"
  28 #include "opto/addnode.hpp"
  29 #include "opto/callnode.hpp"
  30 #include "opto/idealGraphPrinter.hpp"
  31 #include "opto/matcher.hpp"
  32 #include "opto/memnode.hpp"
  33 #include "opto/movenode.hpp"
  34 #include "opto/opcodes.hpp"
  35 #include "opto/regmask.hpp"
  36 #include "opto/rootnode.hpp"
  37 #include "opto/runtime.hpp"
  38 #include "opto/type.hpp"
  39 #include "opto/vectornode.hpp"
  40 #include "runtime/os.hpp"
  41 #include "runtime/sharedRuntime.hpp"
  42 
  43 OptoReg::Name OptoReg::c_frame_pointer;
  44 
  45 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
  46 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
  47 RegMask Matcher::STACK_ONLY_mask;
  48 RegMask Matcher::c_frame_ptr_mask;
  49 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
  50 const uint Matcher::_end_rematerialize   = _END_REMATERIALIZE;
  51 
  52 //---------------------------Matcher-------------------------------------------
  53 Matcher::Matcher()
  54 : PhaseTransform( Phase::Ins_Select ),
  55 #ifdef ASSERT
  56   _old2new_map(C->comp_arena()),
  57   _new2old_map(C->comp_arena()),
  58 #endif
  59   _shared_nodes(C->comp_arena()),
  60   _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
  61   _swallowed(swallowed),
  62   _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
  63   _end_inst_chain_rule(_END_INST_CHAIN_RULE),
  64   _must_clone(must_clone),
  65   _register_save_policy(register_save_policy),
  66   _c_reg_save_policy(c_reg_save_policy),
  67   _register_save_type(register_save_type),
  68   _ruleName(ruleName),
  69   _allocation_started(false),
  70   _states_arena(Chunk::medium_size),
  71   _visited(&_states_arena),
  72   _shared(&_states_arena),
  73   _dontcare(&_states_arena) {
  74   C->set_matcher(this);
  75 
  76   idealreg2spillmask  [Op_RegI] = NULL;
  77   idealreg2spillmask  [Op_RegN] = NULL;
  78   idealreg2spillmask  [Op_RegL] = NULL;
  79   idealreg2spillmask  [Op_RegF] = NULL;
  80   idealreg2spillmask  [Op_RegD] = NULL;
  81   idealreg2spillmask  [Op_RegP] = NULL;
  82   idealreg2spillmask  [Op_VecS] = NULL;
  83   idealreg2spillmask  [Op_VecD] = NULL;
  84   idealreg2spillmask  [Op_VecX] = NULL;
  85   idealreg2spillmask  [Op_VecY] = NULL;
  86   idealreg2spillmask  [Op_VecZ] = NULL;
  87 
  88   idealreg2debugmask  [Op_RegI] = NULL;
  89   idealreg2debugmask  [Op_RegN] = NULL;
  90   idealreg2debugmask  [Op_RegL] = NULL;
  91   idealreg2debugmask  [Op_RegF] = NULL;
  92   idealreg2debugmask  [Op_RegD] = NULL;
  93   idealreg2debugmask  [Op_RegP] = NULL;
  94   idealreg2debugmask  [Op_VecS] = NULL;
  95   idealreg2debugmask  [Op_VecD] = NULL;
  96   idealreg2debugmask  [Op_VecX] = NULL;
  97   idealreg2debugmask  [Op_VecY] = NULL;
  98   idealreg2debugmask  [Op_VecZ] = NULL;
  99 
 100   idealreg2mhdebugmask[Op_RegI] = NULL;
 101   idealreg2mhdebugmask[Op_RegN] = NULL;
 102   idealreg2mhdebugmask[Op_RegL] = NULL;
 103   idealreg2mhdebugmask[Op_RegF] = NULL;
 104   idealreg2mhdebugmask[Op_RegD] = NULL;
 105   idealreg2mhdebugmask[Op_RegP] = NULL;
 106   idealreg2mhdebugmask[Op_VecS] = NULL;
 107   idealreg2mhdebugmask[Op_VecD] = NULL;
 108   idealreg2mhdebugmask[Op_VecX] = NULL;
 109   idealreg2mhdebugmask[Op_VecY] = NULL;
 110   idealreg2mhdebugmask[Op_VecZ] = NULL;
 111 
 112   debug_only(_mem_node = NULL;)   // Ideal memory node consumed by mach node
 113 }
 114 
 115 //------------------------------warp_incoming_stk_arg------------------------
 116 // This warps a VMReg into an OptoReg::Name
 117 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
 118   OptoReg::Name warped;
 119   if( reg->is_stack() ) {  // Stack slot argument?
 120     warped = OptoReg::add(_old_SP, reg->reg2stack() );
 121     warped = OptoReg::add(warped, C->out_preserve_stack_slots());
 122     if( warped >= _in_arg_limit )
 123       _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
 124     if (!RegMask::can_represent_arg(warped)) {
 125       // the compiler cannot represent this method's calling sequence
 126       C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
 127       return OptoReg::Bad;
 128     }
 129     return warped;
 130   }
 131   return OptoReg::as_OptoReg(reg);
 132 }
 133 
 134 //---------------------------compute_old_SP------------------------------------
 135 OptoReg::Name Compile::compute_old_SP() {
 136   int fixed    = fixed_slots();
 137   int preserve = in_preserve_stack_slots();
 138   return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
 139 }
 140 
 141 
 142 
 143 #ifdef ASSERT
 144 void Matcher::verify_new_nodes_only(Node* xroot) {
 145   // Make sure that the new graph only references new nodes
 146   ResourceMark rm;
 147   Unique_Node_List worklist;
 148   VectorSet visited(Thread::current()->resource_area());
 149   worklist.push(xroot);
 150   while (worklist.size() > 0) {
 151     Node* n = worklist.pop();
 152     visited <<= n->_idx;
 153     assert(C->node_arena()->contains(n), "dead node");
 154     for (uint j = 0; j < n->req(); j++) {
 155       Node* in = n->in(j);
 156       if (in != NULL) {
 157         assert(C->node_arena()->contains(in), "dead node");
 158         if (!visited.test(in->_idx)) {
 159           worklist.push(in);
 160         }
 161       }
 162     }
 163   }
 164 }
 165 #endif
 166 
 167 
 168 //---------------------------match---------------------------------------------
 169 void Matcher::match( ) {
 170   if( MaxLabelRootDepth < 100 ) { // Too small?
 171     assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
 172     MaxLabelRootDepth = 100;
 173   }
 174   // One-time initialization of some register masks.
 175   init_spill_mask( C->root()->in(1) );
 176   _return_addr_mask = return_addr();
 177 #ifdef _LP64
 178   // Pointers take 2 slots in 64-bit land
 179   _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
 180 #endif
 181 
 182   // Map a Java-signature return type into return register-value
 183   // machine registers for 0, 1 and 2 returned values.
 184   const TypeTuple *range = C->tf()->range();
 185   if( range->cnt() > TypeFunc::Parms ) { // If not a void function
 186     // Get ideal-register return type
 187     int ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
 188     // Get machine return register
 189     uint sop = C->start()->Opcode();
 190     OptoRegPair regs = return_value(ireg, false);
 191 
 192     // And mask for same
 193     _return_value_mask = RegMask(regs.first());
 194     if( OptoReg::is_valid(regs.second()) )
 195       _return_value_mask.Insert(regs.second());
 196   }
 197 
 198   // ---------------
 199   // Frame Layout
 200 
 201   // Need the method signature to determine the incoming argument types,
 202   // because the types determine which registers the incoming arguments are
 203   // in, and this affects the matched code.
 204   const TypeTuple *domain = C->tf()->domain();
 205   uint             argcnt = domain->cnt() - TypeFunc::Parms;
 206   BasicType *sig_bt        = NEW_RESOURCE_ARRAY( BasicType, argcnt );
 207   VMRegPair *vm_parm_regs  = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
 208   _parm_regs               = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
 209   _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
 210   uint i;
 211   for( i = 0; i<argcnt; i++ ) {
 212     sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
 213   }
 214 
 215   // Pass array of ideal registers and length to USER code (from the AD file)
 216   // that will convert this to an array of register numbers.
 217   const StartNode *start = C->start();
 218   start->calling_convention( sig_bt, vm_parm_regs, argcnt );
 219 #ifdef ASSERT
 220   // Sanity check users' calling convention.  Real handy while trying to
 221   // get the initial port correct.
 222   { for (uint i = 0; i<argcnt; i++) {
 223       if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
 224         assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
 225         _parm_regs[i].set_bad();
 226         continue;
 227       }
 228       VMReg parm_reg = vm_parm_regs[i].first();
 229       assert(parm_reg->is_valid(), "invalid arg?");
 230       if (parm_reg->is_reg()) {
 231         OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
 232         assert(can_be_java_arg(opto_parm_reg) ||
 233                C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
 234                opto_parm_reg == inline_cache_reg(),
 235                "parameters in register must be preserved by runtime stubs");
 236       }
 237       for (uint j = 0; j < i; j++) {
 238         assert(parm_reg != vm_parm_regs[j].first(),
 239                "calling conv. must produce distinct regs");
 240       }
 241     }
 242   }
 243 #endif
 244 
 245   // Do some initial frame layout.
 246 
 247   // Compute the old incoming SP (may be called FP) as
 248   //   OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
 249   _old_SP = C->compute_old_SP();
 250   assert( is_even(_old_SP), "must be even" );
 251 
 252   // Compute highest incoming stack argument as
 253   //   _old_SP + out_preserve_stack_slots + incoming argument size.
 254   _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
 255   assert( is_even(_in_arg_limit), "out_preserve must be even" );
 256   for( i = 0; i < argcnt; i++ ) {
 257     // Permit args to have no register
 258     _calling_convention_mask[i].Clear();
 259     if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
 260       continue;
 261     }
 262     // calling_convention returns stack arguments as a count of
 263     // slots beyond OptoReg::stack0()/VMRegImpl::stack0.  We need to convert this to
 264     // the allocators point of view, taking into account all the
 265     // preserve area, locks & pad2.
 266 
 267     OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
 268     if( OptoReg::is_valid(reg1))
 269       _calling_convention_mask[i].Insert(reg1);
 270 
 271     OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
 272     if( OptoReg::is_valid(reg2))
 273       _calling_convention_mask[i].Insert(reg2);
 274 
 275     // Saved biased stack-slot register number
 276     _parm_regs[i].set_pair(reg2, reg1);
 277   }
 278 
 279   // Finally, make sure the incoming arguments take up an even number of
 280   // words, in case the arguments or locals need to contain doubleword stack
 281   // slots.  The rest of the system assumes that stack slot pairs (in
 282   // particular, in the spill area) which look aligned will in fact be
 283   // aligned relative to the stack pointer in the target machine.  Double
 284   // stack slots will always be allocated aligned.
 285   _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
 286 
 287   // Compute highest outgoing stack argument as
 288   //   _new_SP + out_preserve_stack_slots + max(outgoing argument size).
 289   _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
 290   assert( is_even(_out_arg_limit), "out_preserve must be even" );
 291 
 292   if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
 293     // the compiler cannot represent this method's calling sequence
 294     C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
 295   }
 296 
 297   if (C->failing())  return;  // bailed out on incoming arg failure
 298 
 299   // ---------------
 300   // Collect roots of matcher trees.  Every node for which
 301   // _shared[_idx] is cleared is guaranteed to not be shared, and thus
 302   // can be a valid interior of some tree.
 303   find_shared( C->root() );
 304   find_shared( C->top() );
 305 
 306   C->print_method(PHASE_BEFORE_MATCHING);
 307 
 308   // Create new ideal node ConP #NULL even if it does exist in old space
 309   // to avoid false sharing if the corresponding mach node is not used.
 310   // The corresponding mach node is only used in rare cases for derived
 311   // pointers.
 312   Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
 313 
 314   // Swap out to old-space; emptying new-space
 315   Arena *old = C->node_arena()->move_contents(C->old_arena());
 316 
 317   // Save debug and profile information for nodes in old space:
 318   _old_node_note_array = C->node_note_array();
 319   if (_old_node_note_array != NULL) {
 320     C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
 321                            (C->comp_arena(), _old_node_note_array->length(),
 322                             0, NULL));
 323   }
 324 
 325   // Pre-size the new_node table to avoid the need for range checks.
 326   grow_new_node_array(C->unique());
 327 
 328   // Reset node counter so MachNodes start with _idx at 0
 329   int nodes = C->unique(); // save value
 330   C->set_unique(0);
 331   C->reset_dead_node_list();
 332 
 333   // Recursively match trees from old space into new space.
 334   // Correct leaves of new-space Nodes; they point to old-space.
 335   _visited.Clear();             // Clear visit bits for xform call
 336   C->set_cached_top_node(xform( C->top(), nodes ));
 337   if (!C->failing()) {
 338     Node* xroot =        xform( C->root(), 1 );
 339     if (xroot == NULL) {
 340       Matcher::soft_match_failure();  // recursive matching process failed
 341       C->record_method_not_compilable("instruction match failed");
 342     } else {
 343       // During matching shared constants were attached to C->root()
 344       // because xroot wasn't available yet, so transfer the uses to
 345       // the xroot.
 346       for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
 347         Node* n = C->root()->fast_out(j);
 348         if (C->node_arena()->contains(n)) {
 349           assert(n->in(0) == C->root(), "should be control user");
 350           n->set_req(0, xroot);
 351           --j;
 352           --jmax;
 353         }
 354       }
 355 
 356       // Generate new mach node for ConP #NULL
 357       assert(new_ideal_null != NULL, "sanity");
 358       _mach_null = match_tree(new_ideal_null);
 359       // Don't set control, it will confuse GCM since there are no uses.
 360       // The control will be set when this node is used first time
 361       // in find_base_for_derived().
 362       assert(_mach_null != NULL, "");
 363 
 364       C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
 365 
 366 #ifdef ASSERT
 367       verify_new_nodes_only(xroot);
 368 #endif
 369     }
 370   }
 371   if (C->top() == NULL || C->root() == NULL) {
 372     C->record_method_not_compilable("graph lost"); // %%% cannot happen?
 373   }
 374   if (C->failing()) {
 375     // delete old;
 376     old->destruct_contents();
 377     return;
 378   }
 379   assert( C->top(), "" );
 380   assert( C->root(), "" );
 381   validate_null_checks();
 382 
 383   // Now smoke old-space
 384   NOT_DEBUG( old->destruct_contents() );
 385 
 386   // ------------------------
 387   // Set up save-on-entry registers
 388   Fixup_Save_On_Entry( );
 389 }
 390 
 391 
 392 //------------------------------Fixup_Save_On_Entry----------------------------
 393 // The stated purpose of this routine is to take care of save-on-entry
 394 // registers.  However, the overall goal of the Match phase is to convert into
 395 // machine-specific instructions which have RegMasks to guide allocation.
 396 // So what this procedure really does is put a valid RegMask on each input
 397 // to the machine-specific variations of all Return, TailCall and Halt
 398 // instructions.  It also adds edgs to define the save-on-entry values (and of
 399 // course gives them a mask).
 400 
 401 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
 402   RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
 403   // Do all the pre-defined register masks
 404   rms[TypeFunc::Control  ] = RegMask::Empty;
 405   rms[TypeFunc::I_O      ] = RegMask::Empty;
 406   rms[TypeFunc::Memory   ] = RegMask::Empty;
 407   rms[TypeFunc::ReturnAdr] = ret_adr;
 408   rms[TypeFunc::FramePtr ] = fp;
 409   return rms;
 410 }
 411 
 412 //---------------------------init_first_stack_mask-----------------------------
 413 // Create the initial stack mask used by values spilling to the stack.
 414 // Disallow any debug info in outgoing argument areas by setting the
 415 // initial mask accordingly.
 416 void Matcher::init_first_stack_mask() {
 417 
 418   // Allocate storage for spill masks as masks for the appropriate load type.
 419   RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5));
 420 
 421   idealreg2spillmask  [Op_RegN] = &rms[0];
 422   idealreg2spillmask  [Op_RegI] = &rms[1];
 423   idealreg2spillmask  [Op_RegL] = &rms[2];
 424   idealreg2spillmask  [Op_RegF] = &rms[3];
 425   idealreg2spillmask  [Op_RegD] = &rms[4];
 426   idealreg2spillmask  [Op_RegP] = &rms[5];
 427 
 428   idealreg2debugmask  [Op_RegN] = &rms[6];
 429   idealreg2debugmask  [Op_RegI] = &rms[7];
 430   idealreg2debugmask  [Op_RegL] = &rms[8];
 431   idealreg2debugmask  [Op_RegF] = &rms[9];
 432   idealreg2debugmask  [Op_RegD] = &rms[10];
 433   idealreg2debugmask  [Op_RegP] = &rms[11];
 434 
 435   idealreg2mhdebugmask[Op_RegN] = &rms[12];
 436   idealreg2mhdebugmask[Op_RegI] = &rms[13];
 437   idealreg2mhdebugmask[Op_RegL] = &rms[14];
 438   idealreg2mhdebugmask[Op_RegF] = &rms[15];
 439   idealreg2mhdebugmask[Op_RegD] = &rms[16];
 440   idealreg2mhdebugmask[Op_RegP] = &rms[17];
 441 
 442   idealreg2spillmask  [Op_VecS] = &rms[18];
 443   idealreg2spillmask  [Op_VecD] = &rms[19];
 444   idealreg2spillmask  [Op_VecX] = &rms[20];
 445   idealreg2spillmask  [Op_VecY] = &rms[21];
 446   idealreg2spillmask  [Op_VecZ] = &rms[22];
 447 
 448   OptoReg::Name i;
 449 
 450   // At first, start with the empty mask
 451   C->FIRST_STACK_mask().Clear();
 452 
 453   // Add in the incoming argument area
 454   OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
 455   for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
 456     C->FIRST_STACK_mask().Insert(i);
 457   }
 458   // Add in all bits past the outgoing argument area
 459   guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
 460             "must be able to represent all call arguments in reg mask");
 461   OptoReg::Name init = _out_arg_limit;
 462   for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
 463     C->FIRST_STACK_mask().Insert(i);
 464   }
 465   // Finally, set the "infinite stack" bit.
 466   C->FIRST_STACK_mask().set_AllStack();
 467 
 468   // Make spill masks.  Registers for their class, plus FIRST_STACK_mask.
 469   RegMask aligned_stack_mask = C->FIRST_STACK_mask();
 470   // Keep spill masks aligned.
 471   aligned_stack_mask.clear_to_pairs();
 472   assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 473 
 474   *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
 475 #ifdef _LP64
 476   *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
 477    idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
 478    idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
 479 #else
 480    idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
 481 #endif
 482   *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
 483    idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
 484   *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
 485    idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
 486   *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
 487    idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
 488   *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
 489    idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
 490 
 491   if (Matcher::vector_size_supported(T_BYTE,4)) {
 492     *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
 493      idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
 494   }
 495   if (Matcher::vector_size_supported(T_FLOAT,2)) {
 496     // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
 497     // RA guarantees such alignment since it is needed for Double and Long values.
 498     *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
 499      idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
 500   }
 501   if (Matcher::vector_size_supported(T_FLOAT,4)) {
 502     // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
 503     //
 504     // RA can use input arguments stack slots for spills but until RA
 505     // we don't know frame size and offset of input arg stack slots.
 506     //
 507     // Exclude last input arg stack slots to avoid spilling vectors there
 508     // otherwise vector spills could stomp over stack slots in caller frame.
 509     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 510     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
 511       aligned_stack_mask.Remove(in);
 512       in = OptoReg::add(in, -1);
 513     }
 514      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
 515      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 516     *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
 517      idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
 518   }
 519   if (Matcher::vector_size_supported(T_FLOAT,8)) {
 520     // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
 521     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 522     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
 523       aligned_stack_mask.Remove(in);
 524       in = OptoReg::add(in, -1);
 525     }
 526      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
 527      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 528     *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
 529      idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
 530   }
 531   if (Matcher::vector_size_supported(T_FLOAT,16)) {
 532     // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
 533     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 534     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
 535       aligned_stack_mask.Remove(in);
 536       in = OptoReg::add(in, -1);
 537     }
 538      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
 539      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 540     *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
 541      idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
 542   }
 543    if (UseFPUForSpilling) {
 544      // This mask logic assumes that the spill operations are
 545      // symmetric and that the registers involved are the same size.
 546      // On sparc for instance we may have to use 64 bit moves will
 547      // kill 2 registers when used with F0-F31.
 548      idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
 549      idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
 550 #ifdef _LP64
 551      idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
 552      idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
 553      idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
 554      idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
 555 #else
 556      idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
 557 #ifdef ARM
 558      // ARM has support for moving 64bit values between a pair of
 559      // integer registers and a double register
 560      idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
 561      idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
 562 #endif
 563 #endif
 564    }
 565 
 566   // Make up debug masks.  Any spill slot plus callee-save registers.
 567   // Caller-save registers are assumed to be trashable by the various
 568   // inline-cache fixup routines.
 569   *idealreg2debugmask  [Op_RegN]= *idealreg2spillmask[Op_RegN];
 570   *idealreg2debugmask  [Op_RegI]= *idealreg2spillmask[Op_RegI];
 571   *idealreg2debugmask  [Op_RegL]= *idealreg2spillmask[Op_RegL];
 572   *idealreg2debugmask  [Op_RegF]= *idealreg2spillmask[Op_RegF];
 573   *idealreg2debugmask  [Op_RegD]= *idealreg2spillmask[Op_RegD];
 574   *idealreg2debugmask  [Op_RegP]= *idealreg2spillmask[Op_RegP];
 575 
 576   *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
 577   *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
 578   *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
 579   *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
 580   *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
 581   *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
 582 
 583   // Prevent stub compilations from attempting to reference
 584   // callee-saved registers from debug info
 585   bool exclude_soe = !Compile::current()->is_method_compilation();
 586 
 587   for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
 588     // registers the caller has to save do not work
 589     if( _register_save_policy[i] == 'C' ||
 590         _register_save_policy[i] == 'A' ||
 591         (_register_save_policy[i] == 'E' && exclude_soe) ) {
 592       idealreg2debugmask  [Op_RegN]->Remove(i);
 593       idealreg2debugmask  [Op_RegI]->Remove(i); // Exclude save-on-call
 594       idealreg2debugmask  [Op_RegL]->Remove(i); // registers from debug
 595       idealreg2debugmask  [Op_RegF]->Remove(i); // masks
 596       idealreg2debugmask  [Op_RegD]->Remove(i);
 597       idealreg2debugmask  [Op_RegP]->Remove(i);
 598 
 599       idealreg2mhdebugmask[Op_RegN]->Remove(i);
 600       idealreg2mhdebugmask[Op_RegI]->Remove(i);
 601       idealreg2mhdebugmask[Op_RegL]->Remove(i);
 602       idealreg2mhdebugmask[Op_RegF]->Remove(i);
 603       idealreg2mhdebugmask[Op_RegD]->Remove(i);
 604       idealreg2mhdebugmask[Op_RegP]->Remove(i);
 605     }
 606   }
 607 
 608   // Subtract the register we use to save the SP for MethodHandle
 609   // invokes to from the debug mask.
 610   const RegMask save_mask = method_handle_invoke_SP_save_mask();
 611   idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
 612   idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
 613   idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
 614   idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
 615   idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
 616   idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
 617 }
 618 
 619 //---------------------------is_save_on_entry----------------------------------
 620 bool Matcher::is_save_on_entry( int reg ) {
 621   return
 622     _register_save_policy[reg] == 'E' ||
 623     _register_save_policy[reg] == 'A' || // Save-on-entry register?
 624     // Also save argument registers in the trampolining stubs
 625     (C->save_argument_registers() && is_spillable_arg(reg));
 626 }
 627 
 628 //---------------------------Fixup_Save_On_Entry-------------------------------
 629 void Matcher::Fixup_Save_On_Entry( ) {
 630   init_first_stack_mask();
 631 
 632   Node *root = C->root();       // Short name for root
 633   // Count number of save-on-entry registers.
 634   uint soe_cnt = number_of_saved_registers();
 635   uint i;
 636 
 637   // Find the procedure Start Node
 638   StartNode *start = C->start();
 639   assert( start, "Expect a start node" );
 640 
 641   // Save argument registers in the trampolining stubs
 642   if( C->save_argument_registers() )
 643     for( i = 0; i < _last_Mach_Reg; i++ )
 644       if( is_spillable_arg(i) )
 645         soe_cnt++;
 646 
 647   // Input RegMask array shared by all Returns.
 648   // The type for doubles and longs has a count of 2, but
 649   // there is only 1 returned value
 650   uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
 651   RegMask *ret_rms  = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 652   // Returns have 0 or 1 returned values depending on call signature.
 653   // Return register is specified by return_value in the AD file.
 654   if (ret_edge_cnt > TypeFunc::Parms)
 655     ret_rms[TypeFunc::Parms+0] = _return_value_mask;
 656 
 657   // Input RegMask array shared by all Rethrows.
 658   uint reth_edge_cnt = TypeFunc::Parms+1;
 659   RegMask *reth_rms  = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 660   // Rethrow takes exception oop only, but in the argument 0 slot.
 661   reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
 662 #ifdef _LP64
 663   // Need two slots for ptrs in 64-bit land
 664   reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
 665 #endif
 666 
 667   // Input RegMask array shared by all TailCalls
 668   uint tail_call_edge_cnt = TypeFunc::Parms+2;
 669   RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 670 
 671   // Input RegMask array shared by all TailJumps
 672   uint tail_jump_edge_cnt = TypeFunc::Parms+2;
 673   RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 674 
 675   // TailCalls have 2 returned values (target & moop), whose masks come
 676   // from the usual MachNode/MachOper mechanism.  Find a sample
 677   // TailCall to extract these masks and put the correct masks into
 678   // the tail_call_rms array.
 679   for( i=1; i < root->req(); i++ ) {
 680     MachReturnNode *m = root->in(i)->as_MachReturn();
 681     if( m->ideal_Opcode() == Op_TailCall ) {
 682       tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
 683       tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
 684       break;
 685     }
 686   }
 687 
 688   // TailJumps have 2 returned values (target & ex_oop), whose masks come
 689   // from the usual MachNode/MachOper mechanism.  Find a sample
 690   // TailJump to extract these masks and put the correct masks into
 691   // the tail_jump_rms array.
 692   for( i=1; i < root->req(); i++ ) {
 693     MachReturnNode *m = root->in(i)->as_MachReturn();
 694     if( m->ideal_Opcode() == Op_TailJump ) {
 695       tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
 696       tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
 697       break;
 698     }
 699   }
 700 
 701   // Input RegMask array shared by all Halts
 702   uint halt_edge_cnt = TypeFunc::Parms;
 703   RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 704 
 705   // Capture the return input masks into each exit flavor
 706   for( i=1; i < root->req(); i++ ) {
 707     MachReturnNode *exit = root->in(i)->as_MachReturn();
 708     switch( exit->ideal_Opcode() ) {
 709       case Op_Return   : exit->_in_rms = ret_rms;  break;
 710       case Op_Rethrow  : exit->_in_rms = reth_rms; break;
 711       case Op_TailCall : exit->_in_rms = tail_call_rms; break;
 712       case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
 713       case Op_Halt     : exit->_in_rms = halt_rms; break;
 714       default          : ShouldNotReachHere();
 715     }
 716   }
 717 
 718   // Next unused projection number from Start.
 719   int proj_cnt = C->tf()->domain()->cnt();
 720 
 721   // Do all the save-on-entry registers.  Make projections from Start for
 722   // them, and give them a use at the exit points.  To the allocator, they
 723   // look like incoming register arguments.
 724   for( i = 0; i < _last_Mach_Reg; i++ ) {
 725     if( is_save_on_entry(i) ) {
 726 
 727       // Add the save-on-entry to the mask array
 728       ret_rms      [      ret_edge_cnt] = mreg2regmask[i];
 729       reth_rms     [     reth_edge_cnt] = mreg2regmask[i];
 730       tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
 731       tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
 732       // Halts need the SOE registers, but only in the stack as debug info.
 733       // A just-prior uncommon-trap or deoptimization will use the SOE regs.
 734       halt_rms     [     halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
 735 
 736       Node *mproj;
 737 
 738       // Is this a RegF low half of a RegD?  Double up 2 adjacent RegF's
 739       // into a single RegD.
 740       if( (i&1) == 0 &&
 741           _register_save_type[i  ] == Op_RegF &&
 742           _register_save_type[i+1] == Op_RegF &&
 743           is_save_on_entry(i+1) ) {
 744         // Add other bit for double
 745         ret_rms      [      ret_edge_cnt].Insert(OptoReg::Name(i+1));
 746         reth_rms     [     reth_edge_cnt].Insert(OptoReg::Name(i+1));
 747         tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
 748         tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
 749         halt_rms     [     halt_edge_cnt].Insert(OptoReg::Name(i+1));
 750         mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
 751         proj_cnt += 2;          // Skip 2 for doubles
 752       }
 753       else if( (i&1) == 1 &&    // Else check for high half of double
 754                _register_save_type[i-1] == Op_RegF &&
 755                _register_save_type[i  ] == Op_RegF &&
 756                is_save_on_entry(i-1) ) {
 757         ret_rms      [      ret_edge_cnt] = RegMask::Empty;
 758         reth_rms     [     reth_edge_cnt] = RegMask::Empty;
 759         tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
 760         tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
 761         halt_rms     [     halt_edge_cnt] = RegMask::Empty;
 762         mproj = C->top();
 763       }
 764       // Is this a RegI low half of a RegL?  Double up 2 adjacent RegI's
 765       // into a single RegL.
 766       else if( (i&1) == 0 &&
 767           _register_save_type[i  ] == Op_RegI &&
 768           _register_save_type[i+1] == Op_RegI &&
 769         is_save_on_entry(i+1) ) {
 770         // Add other bit for long
 771         ret_rms      [      ret_edge_cnt].Insert(OptoReg::Name(i+1));
 772         reth_rms     [     reth_edge_cnt].Insert(OptoReg::Name(i+1));
 773         tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
 774         tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
 775         halt_rms     [     halt_edge_cnt].Insert(OptoReg::Name(i+1));
 776         mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
 777         proj_cnt += 2;          // Skip 2 for longs
 778       }
 779       else if( (i&1) == 1 &&    // Else check for high half of long
 780                _register_save_type[i-1] == Op_RegI &&
 781                _register_save_type[i  ] == Op_RegI &&
 782                is_save_on_entry(i-1) ) {
 783         ret_rms      [      ret_edge_cnt] = RegMask::Empty;
 784         reth_rms     [     reth_edge_cnt] = RegMask::Empty;
 785         tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
 786         tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
 787         halt_rms     [     halt_edge_cnt] = RegMask::Empty;
 788         mproj = C->top();
 789       } else {
 790         // Make a projection for it off the Start
 791         mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
 792       }
 793 
 794       ret_edge_cnt ++;
 795       reth_edge_cnt ++;
 796       tail_call_edge_cnt ++;
 797       tail_jump_edge_cnt ++;
 798       halt_edge_cnt ++;
 799 
 800       // Add a use of the SOE register to all exit paths
 801       for( uint j=1; j < root->req(); j++ )
 802         root->in(j)->add_req(mproj);
 803     } // End of if a save-on-entry register
 804   } // End of for all machine registers
 805 }
 806 
 807 //------------------------------init_spill_mask--------------------------------
 808 void Matcher::init_spill_mask( Node *ret ) {
 809   if( idealreg2regmask[Op_RegI] ) return; // One time only init
 810 
 811   OptoReg::c_frame_pointer = c_frame_pointer();
 812   c_frame_ptr_mask = c_frame_pointer();
 813 #ifdef _LP64
 814   // pointers are twice as big
 815   c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
 816 #endif
 817 
 818   // Start at OptoReg::stack0()
 819   STACK_ONLY_mask.Clear();
 820   OptoReg::Name init = OptoReg::stack2reg(0);
 821   // STACK_ONLY_mask is all stack bits
 822   OptoReg::Name i;
 823   for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
 824     STACK_ONLY_mask.Insert(i);
 825   // Also set the "infinite stack" bit.
 826   STACK_ONLY_mask.set_AllStack();
 827 
 828   // Copy the register names over into the shared world
 829   for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
 830     // SharedInfo::regName[i] = regName[i];
 831     // Handy RegMasks per machine register
 832     mreg2regmask[i].Insert(i);
 833   }
 834 
 835   // Grab the Frame Pointer
 836   Node *fp  = ret->in(TypeFunc::FramePtr);
 837   Node *mem = ret->in(TypeFunc::Memory);
 838   const TypePtr* atp = TypePtr::BOTTOM;
 839   // Share frame pointer while making spill ops
 840   set_shared(fp);
 841 
 842   // Compute generic short-offset Loads
 843 #ifdef _LP64
 844   MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
 845 #endif
 846   MachNode *spillI  = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
 847   MachNode *spillL  = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered,false));
 848   MachNode *spillF  = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
 849   MachNode *spillD  = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
 850   MachNode *spillP  = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
 851   assert(spillI != NULL && spillL != NULL && spillF != NULL &&
 852          spillD != NULL && spillP != NULL, "");
 853   // Get the ADLC notion of the right regmask, for each basic type.
 854 #ifdef _LP64
 855   idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
 856 #endif
 857   idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
 858   idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
 859   idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
 860   idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
 861   idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
 862 
 863   // Vector regmasks.
 864   if (Matcher::vector_size_supported(T_BYTE,4)) {
 865     TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
 866     MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
 867     idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
 868   }
 869   if (Matcher::vector_size_supported(T_FLOAT,2)) {
 870     MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
 871     idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
 872   }
 873   if (Matcher::vector_size_supported(T_FLOAT,4)) {
 874     MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
 875     idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
 876   }
 877   if (Matcher::vector_size_supported(T_FLOAT,8)) {
 878     MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
 879     idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
 880   }
 881   if (Matcher::vector_size_supported(T_FLOAT,16)) {
 882     MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ));
 883     idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask();
 884   }
 885 }
 886 
 887 #ifdef ASSERT
 888 static void match_alias_type(Compile* C, Node* n, Node* m) {
 889   if (!VerifyAliases)  return;  // do not go looking for trouble by default
 890   const TypePtr* nat = n->adr_type();
 891   const TypePtr* mat = m->adr_type();
 892   int nidx = C->get_alias_index(nat);
 893   int midx = C->get_alias_index(mat);
 894   // Detune the assert for cases like (AndI 0xFF (LoadB p)).
 895   if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
 896     for (uint i = 1; i < n->req(); i++) {
 897       Node* n1 = n->in(i);
 898       const TypePtr* n1at = n1->adr_type();
 899       if (n1at != NULL) {
 900         nat = n1at;
 901         nidx = C->get_alias_index(n1at);
 902       }
 903     }
 904   }
 905   // %%% Kludgery.  Instead, fix ideal adr_type methods for all these cases:
 906   if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
 907     switch (n->Opcode()) {
 908     case Op_PrefetchAllocation:
 909       nidx = Compile::AliasIdxRaw;
 910       nat = TypeRawPtr::BOTTOM;
 911       break;
 912     }
 913   }
 914   if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
 915     switch (n->Opcode()) {
 916     case Op_ClearArray:
 917       midx = Compile::AliasIdxRaw;
 918       mat = TypeRawPtr::BOTTOM;
 919       break;
 920     }
 921   }
 922   if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
 923     switch (n->Opcode()) {
 924     case Op_Return:
 925     case Op_Rethrow:
 926     case Op_Halt:
 927     case Op_TailCall:
 928     case Op_TailJump:
 929       nidx = Compile::AliasIdxBot;
 930       nat = TypePtr::BOTTOM;
 931       break;
 932     }
 933   }
 934   if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
 935     switch (n->Opcode()) {
 936     case Op_StrComp:
 937     case Op_StrEquals:
 938     case Op_StrIndexOf:
 939     case Op_AryEq:
 940     case Op_MemBarVolatile:
 941     case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
 942     case Op_EncodeISOArray:
 943       nidx = Compile::AliasIdxTop;
 944       nat = NULL;
 945       break;
 946     }
 947   }
 948   if (nidx != midx) {
 949     if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
 950       tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
 951       n->dump();
 952       m->dump();
 953     }
 954     assert(C->subsume_loads() && C->must_alias(nat, midx),
 955            "must not lose alias info when matching");
 956   }
 957 }
 958 #endif
 959 
 960 
 961 //------------------------------MStack-----------------------------------------
 962 // State and MStack class used in xform() and find_shared() iterative methods.
 963 enum Node_State { Pre_Visit,  // node has to be pre-visited
 964                       Visit,  // visit node
 965                  Post_Visit,  // post-visit node
 966              Alt_Post_Visit   // alternative post-visit path
 967                 };
 968 
 969 class MStack: public Node_Stack {
 970   public:
 971     MStack(int size) : Node_Stack(size) { }
 972 
 973     void push(Node *n, Node_State ns) {
 974       Node_Stack::push(n, (uint)ns);
 975     }
 976     void push(Node *n, Node_State ns, Node *parent, int indx) {
 977       ++_inode_top;
 978       if ((_inode_top + 1) >= _inode_max) grow();
 979       _inode_top->node = parent;
 980       _inode_top->indx = (uint)indx;
 981       ++_inode_top;
 982       _inode_top->node = n;
 983       _inode_top->indx = (uint)ns;
 984     }
 985     Node *parent() {
 986       pop();
 987       return node();
 988     }
 989     Node_State state() const {
 990       return (Node_State)index();
 991     }
 992     void set_state(Node_State ns) {
 993       set_index((uint)ns);
 994     }
 995 };
 996 
 997 
 998 //------------------------------xform------------------------------------------
 999 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
1000 // Node in new-space.  Given a new-space Node, recursively walk his children.
1001 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
1002 Node *Matcher::xform( Node *n, int max_stack ) {
1003   // Use one stack to keep both: child's node/state and parent's node/index
1004   MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2
1005   mstack.push(n, Visit, NULL, -1);  // set NULL as parent to indicate root
1006 
1007   while (mstack.is_nonempty()) {
1008     C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1009     if (C->failing()) return NULL;
1010     n = mstack.node();          // Leave node on stack
1011     Node_State nstate = mstack.state();
1012     if (nstate == Visit) {
1013       mstack.set_state(Post_Visit);
1014       Node *oldn = n;
1015       // Old-space or new-space check
1016       if (!C->node_arena()->contains(n)) {
1017         // Old space!
1018         Node* m;
1019         if (has_new_node(n)) {  // Not yet Label/Reduced
1020           m = new_node(n);
1021         } else {
1022           if (!is_dontcare(n)) { // Matcher can match this guy
1023             // Calls match special.  They match alone with no children.
1024             // Their children, the incoming arguments, match normally.
1025             m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1026             if (C->failing())  return NULL;
1027             if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1028           } else {                  // Nothing the matcher cares about
1029             if( n->is_Proj() && n->in(0)->is_Multi()) {       // Projections?
1030               // Convert to machine-dependent projection
1031               m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1032 #ifdef ASSERT
1033               _new2old_map.map(m->_idx, n);
1034 #endif
1035               if (m->in(0) != NULL) // m might be top
1036                 collect_null_checks(m, n);
1037             } else {                // Else just a regular 'ol guy
1038               m = n->clone();       // So just clone into new-space
1039 #ifdef ASSERT
1040               _new2old_map.map(m->_idx, n);
1041 #endif
1042               // Def-Use edges will be added incrementally as Uses
1043               // of this node are matched.
1044               assert(m->outcnt() == 0, "no Uses of this clone yet");
1045             }
1046           }
1047 
1048           set_new_node(n, m);       // Map old to new
1049           if (_old_node_note_array != NULL) {
1050             Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1051                                                   n->_idx);
1052             C->set_node_notes_at(m->_idx, nn);
1053           }
1054           debug_only(match_alias_type(C, n, m));
1055         }
1056         n = m;    // n is now a new-space node
1057         mstack.set_node(n);
1058       }
1059 
1060       // New space!
1061       if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1062 
1063       int i;
1064       // Put precedence edges on stack first (match them last).
1065       for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1066         Node *m = oldn->in(i);
1067         if (m == NULL) break;
1068         // set -1 to call add_prec() instead of set_req() during Step1
1069         mstack.push(m, Visit, n, -1);
1070       }
1071 
1072       // For constant debug info, I'd rather have unmatched constants.
1073       int cnt = n->req();
1074       JVMState* jvms = n->jvms();
1075       int debug_cnt = jvms ? jvms->debug_start() : cnt;
1076 
1077       // Now do only debug info.  Clone constants rather than matching.
1078       // Constants are represented directly in the debug info without
1079       // the need for executable machine instructions.
1080       // Monitor boxes are also represented directly.
1081       for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1082         Node *m = n->in(i);          // Get input
1083         int op = m->Opcode();
1084         assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1085         if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1086             op == Op_ConF || op == Op_ConD || op == Op_ConL
1087             // || op == Op_BoxLock  // %%%% enable this and remove (+++) in chaitin.cpp
1088             ) {
1089           m = m->clone();
1090 #ifdef ASSERT
1091           _new2old_map.map(m->_idx, n);
1092 #endif
1093           mstack.push(m, Post_Visit, n, i); // Don't need to visit
1094           mstack.push(m->in(0), Visit, m, 0);
1095         } else {
1096           mstack.push(m, Visit, n, i);
1097         }
1098       }
1099 
1100       // And now walk his children, and convert his inputs to new-space.
1101       for( ; i >= 0; --i ) { // For all normal inputs do
1102         Node *m = n->in(i);  // Get input
1103         if(m != NULL)
1104           mstack.push(m, Visit, n, i);
1105       }
1106 
1107     }
1108     else if (nstate == Post_Visit) {
1109       // Set xformed input
1110       Node *p = mstack.parent();
1111       if (p != NULL) { // root doesn't have parent
1112         int i = (int)mstack.index();
1113         if (i >= 0)
1114           p->set_req(i, n); // required input
1115         else if (i == -1)
1116           p->add_prec(n);   // precedence input
1117         else
1118           ShouldNotReachHere();
1119       }
1120       mstack.pop(); // remove processed node from stack
1121     }
1122     else {
1123       ShouldNotReachHere();
1124     }
1125   } // while (mstack.is_nonempty())
1126   return n; // Return new-space Node
1127 }
1128 
1129 //------------------------------warp_outgoing_stk_arg------------------------
1130 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1131   // Convert outgoing argument location to a pre-biased stack offset
1132   if (reg->is_stack()) {
1133     OptoReg::Name warped = reg->reg2stack();
1134     // Adjust the stack slot offset to be the register number used
1135     // by the allocator.
1136     warped = OptoReg::add(begin_out_arg_area, warped);
1137     // Keep track of the largest numbered stack slot used for an arg.
1138     // Largest used slot per call-site indicates the amount of stack
1139     // that is killed by the call.
1140     if( warped >= out_arg_limit_per_call )
1141       out_arg_limit_per_call = OptoReg::add(warped,1);
1142     if (!RegMask::can_represent_arg(warped)) {
1143       C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1144       return OptoReg::Bad;
1145     }
1146     return warped;
1147   }
1148   return OptoReg::as_OptoReg(reg);
1149 }
1150 
1151 
1152 //------------------------------match_sfpt-------------------------------------
1153 // Helper function to match call instructions.  Calls match special.
1154 // They match alone with no children.  Their children, the incoming
1155 // arguments, match normally.
1156 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1157   MachSafePointNode *msfpt = NULL;
1158   MachCallNode      *mcall = NULL;
1159   uint               cnt;
1160   // Split out case for SafePoint vs Call
1161   CallNode *call;
1162   const TypeTuple *domain;
1163   ciMethod*        method = NULL;
1164   bool             is_method_handle_invoke = false;  // for special kill effects
1165   if( sfpt->is_Call() ) {
1166     call = sfpt->as_Call();
1167     domain = call->tf()->domain();
1168     cnt = domain->cnt();
1169 
1170     // Match just the call, nothing else
1171     MachNode *m = match_tree(call);
1172     if (C->failing())  return NULL;
1173     if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1174 
1175     // Copy data from the Ideal SafePoint to the machine version
1176     mcall = m->as_MachCall();
1177 
1178     mcall->set_tf(         call->tf());
1179     mcall->set_entry_point(call->entry_point());
1180     mcall->set_cnt(        call->cnt());
1181 
1182     if( mcall->is_MachCallJava() ) {
1183       MachCallJavaNode *mcall_java  = mcall->as_MachCallJava();
1184       const CallJavaNode *call_java =  call->as_CallJava();
1185       method = call_java->method();
1186       mcall_java->_method = method;
1187       mcall_java->_bci = call_java->_bci;
1188       mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1189       is_method_handle_invoke = call_java->is_method_handle_invoke();
1190       mcall_java->_method_handle_invoke = is_method_handle_invoke;
1191       if (is_method_handle_invoke) {
1192         C->set_has_method_handle_invokes(true);
1193       }
1194       if( mcall_java->is_MachCallStaticJava() )
1195         mcall_java->as_MachCallStaticJava()->_name =
1196          call_java->as_CallStaticJava()->_name;
1197       if( mcall_java->is_MachCallDynamicJava() )
1198         mcall_java->as_MachCallDynamicJava()->_vtable_index =
1199          call_java->as_CallDynamicJava()->_vtable_index;
1200     }
1201     else if( mcall->is_MachCallRuntime() ) {
1202       mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1203     }
1204     msfpt = mcall;
1205   }
1206   // This is a non-call safepoint
1207   else {
1208     call = NULL;
1209     domain = NULL;
1210     MachNode *mn = match_tree(sfpt);
1211     if (C->failing())  return NULL;
1212     msfpt = mn->as_MachSafePoint();
1213     cnt = TypeFunc::Parms;
1214   }
1215 
1216   // Advertise the correct memory effects (for anti-dependence computation).
1217   msfpt->set_adr_type(sfpt->adr_type());
1218 
1219   // Allocate a private array of RegMasks.  These RegMasks are not shared.
1220   msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1221   // Empty them all.
1222   memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1223 
1224   // Do all the pre-defined non-Empty register masks
1225   msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1226   msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1227 
1228   // Place first outgoing argument can possibly be put.
1229   OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1230   assert( is_even(begin_out_arg_area), "" );
1231   // Compute max outgoing register number per call site.
1232   OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1233   // Calls to C may hammer extra stack slots above and beyond any arguments.
1234   // These are usually backing store for register arguments for varargs.
1235   if( call != NULL && call->is_CallRuntime() )
1236     out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1237 
1238 
1239   // Do the normal argument list (parameters) register masks
1240   int argcnt = cnt - TypeFunc::Parms;
1241   if( argcnt > 0 ) {          // Skip it all if we have no args
1242     BasicType *sig_bt  = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1243     VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1244     int i;
1245     for( i = 0; i < argcnt; i++ ) {
1246       sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1247     }
1248     // V-call to pick proper calling convention
1249     call->calling_convention( sig_bt, parm_regs, argcnt );
1250 
1251 #ifdef ASSERT
1252     // Sanity check users' calling convention.  Really handy during
1253     // the initial porting effort.  Fairly expensive otherwise.
1254     { for (int i = 0; i<argcnt; i++) {
1255       if( !parm_regs[i].first()->is_valid() &&
1256           !parm_regs[i].second()->is_valid() ) continue;
1257       VMReg reg1 = parm_regs[i].first();
1258       VMReg reg2 = parm_regs[i].second();
1259       for (int j = 0; j < i; j++) {
1260         if( !parm_regs[j].first()->is_valid() &&
1261             !parm_regs[j].second()->is_valid() ) continue;
1262         VMReg reg3 = parm_regs[j].first();
1263         VMReg reg4 = parm_regs[j].second();
1264         if( !reg1->is_valid() ) {
1265           assert( !reg2->is_valid(), "valid halvsies" );
1266         } else if( !reg3->is_valid() ) {
1267           assert( !reg4->is_valid(), "valid halvsies" );
1268         } else {
1269           assert( reg1 != reg2, "calling conv. must produce distinct regs");
1270           assert( reg1 != reg3, "calling conv. must produce distinct regs");
1271           assert( reg1 != reg4, "calling conv. must produce distinct regs");
1272           assert( reg2 != reg3, "calling conv. must produce distinct regs");
1273           assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1274           assert( reg3 != reg4, "calling conv. must produce distinct regs");
1275         }
1276       }
1277     }
1278     }
1279 #endif
1280 
1281     // Visit each argument.  Compute its outgoing register mask.
1282     // Return results now can have 2 bits returned.
1283     // Compute max over all outgoing arguments both per call-site
1284     // and over the entire method.
1285     for( i = 0; i < argcnt; i++ ) {
1286       // Address of incoming argument mask to fill in
1287       RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1288       if( !parm_regs[i].first()->is_valid() &&
1289           !parm_regs[i].second()->is_valid() ) {
1290         continue;               // Avoid Halves
1291       }
1292       // Grab first register, adjust stack slots and insert in mask.
1293       OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1294       if (OptoReg::is_valid(reg1))
1295         rm->Insert( reg1 );
1296       // Grab second register (if any), adjust stack slots and insert in mask.
1297       OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1298       if (OptoReg::is_valid(reg2))
1299         rm->Insert( reg2 );
1300     } // End of for all arguments
1301 
1302     // Compute number of stack slots needed to restore stack in case of
1303     // Pascal-style argument popping.
1304     mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1305   }
1306 
1307   // Compute the max stack slot killed by any call.  These will not be
1308   // available for debug info, and will be used to adjust FIRST_STACK_mask
1309   // after all call sites have been visited.
1310   if( _out_arg_limit < out_arg_limit_per_call)
1311     _out_arg_limit = out_arg_limit_per_call;
1312 
1313   if (mcall) {
1314     // Kill the outgoing argument area, including any non-argument holes and
1315     // any legacy C-killed slots.  Use Fat-Projections to do the killing.
1316     // Since the max-per-method covers the max-per-call-site and debug info
1317     // is excluded on the max-per-method basis, debug info cannot land in
1318     // this killed area.
1319     uint r_cnt = mcall->tf()->range()->cnt();
1320     MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1321     if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1322       C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1323     } else {
1324       for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1325         proj->_rout.Insert(OptoReg::Name(i));
1326     }
1327     if (proj->_rout.is_NotEmpty()) {
1328       push_projection(proj);
1329     }
1330   }
1331   // Transfer the safepoint information from the call to the mcall
1332   // Move the JVMState list
1333   msfpt->set_jvms(sfpt->jvms());
1334   for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1335     jvms->set_map(sfpt);
1336   }
1337 
1338   // Debug inputs begin just after the last incoming parameter
1339   assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1340          (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1341 
1342   // Move the OopMap
1343   msfpt->_oop_map = sfpt->_oop_map;
1344 
1345   // Add additional edges.
1346   if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1347     // For these calls we can not add MachConstantBase in expand(), as the
1348     // ins are not complete then.
1349     msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1350     if (msfpt->jvms() &&
1351         msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1352       // We added an edge before jvms, so we must adapt the position of the ins.
1353       msfpt->jvms()->adapt_position(+1);
1354     }
1355   }
1356 
1357   // Registers killed by the call are set in the local scheduling pass
1358   // of Global Code Motion.
1359   return msfpt;
1360 }
1361 
1362 //---------------------------match_tree----------------------------------------
1363 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce.  Used as part
1364 // of the whole-sale conversion from Ideal to Mach Nodes.  Also used for
1365 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1366 // a Load's result RegMask for memoization in idealreg2regmask[]
1367 MachNode *Matcher::match_tree( const Node *n ) {
1368   assert( n->Opcode() != Op_Phi, "cannot match" );
1369   assert( !n->is_block_start(), "cannot match" );
1370   // Set the mark for all locally allocated State objects.
1371   // When this call returns, the _states_arena arena will be reset
1372   // freeing all State objects.
1373   ResourceMark rm( &_states_arena );
1374 
1375   LabelRootDepth = 0;
1376 
1377   // StoreNodes require their Memory input to match any LoadNodes
1378   Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1379 #ifdef ASSERT
1380   Node* save_mem_node = _mem_node;
1381   _mem_node = n->is_Store() ? (Node*)n : NULL;
1382 #endif
1383   // State object for root node of match tree
1384   // Allocate it on _states_arena - stack allocation can cause stack overflow.
1385   State *s = new (&_states_arena) State;
1386   s->_kids[0] = NULL;
1387   s->_kids[1] = NULL;
1388   s->_leaf = (Node*)n;
1389   // Label the input tree, allocating labels from top-level arena
1390   Label_Root( n, s, n->in(0), mem );
1391   if (C->failing())  return NULL;
1392 
1393   // The minimum cost match for the whole tree is found at the root State
1394   uint mincost = max_juint;
1395   uint cost = max_juint;
1396   uint i;
1397   for( i = 0; i < NUM_OPERANDS; i++ ) {
1398     if( s->valid(i) &&                // valid entry and
1399         s->_cost[i] < cost &&         // low cost and
1400         s->_rule[i] >= NUM_OPERANDS ) // not an operand
1401       cost = s->_cost[mincost=i];
1402   }
1403   if (mincost == max_juint) {
1404 #ifndef PRODUCT
1405     tty->print("No matching rule for:");
1406     s->dump();
1407 #endif
1408     Matcher::soft_match_failure();
1409     return NULL;
1410   }
1411   // Reduce input tree based upon the state labels to machine Nodes
1412   MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1413 #ifdef ASSERT
1414   _old2new_map.map(n->_idx, m);
1415   _new2old_map.map(m->_idx, (Node*)n);
1416 #endif
1417 
1418   // Add any Matcher-ignored edges
1419   uint cnt = n->req();
1420   uint start = 1;
1421   if( mem != (Node*)1 ) start = MemNode::Memory+1;
1422   if( n->is_AddP() ) {
1423     assert( mem == (Node*)1, "" );
1424     start = AddPNode::Base+1;
1425   }
1426   for( i = start; i < cnt; i++ ) {
1427     if( !n->match_edge(i) ) {
1428       if( i < m->req() )
1429         m->ins_req( i, n->in(i) );
1430       else
1431         m->add_req( n->in(i) );
1432     }
1433   }
1434 
1435   debug_only( _mem_node = save_mem_node; )
1436   return m;
1437 }
1438 
1439 
1440 //------------------------------match_into_reg---------------------------------
1441 // Choose to either match this Node in a register or part of the current
1442 // match tree.  Return true for requiring a register and false for matching
1443 // as part of the current match tree.
1444 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1445 
1446   const Type *t = m->bottom_type();
1447 
1448   if (t->singleton()) {
1449     // Never force constants into registers.  Allow them to match as
1450     // constants or registers.  Copies of the same value will share
1451     // the same register.  See find_shared_node.
1452     return false;
1453   } else {                      // Not a constant
1454     // Stop recursion if they have different Controls.
1455     Node* m_control = m->in(0);
1456     // Control of load's memory can post-dominates load's control.
1457     // So use it since load can't float above its memory.
1458     Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1459     if (control && m_control && control != m_control && control != mem_control) {
1460 
1461       // Actually, we can live with the most conservative control we
1462       // find, if it post-dominates the others.  This allows us to
1463       // pick up load/op/store trees where the load can float a little
1464       // above the store.
1465       Node *x = control;
1466       const uint max_scan = 6;  // Arbitrary scan cutoff
1467       uint j;
1468       for (j=0; j<max_scan; j++) {
1469         if (x->is_Region())     // Bail out at merge points
1470           return true;
1471         x = x->in(0);
1472         if (x == m_control)     // Does 'control' post-dominate
1473           break;                // m->in(0)?  If so, we can use it
1474         if (x == mem_control)   // Does 'control' post-dominate
1475           break;                // mem_control?  If so, we can use it
1476       }
1477       if (j == max_scan)        // No post-domination before scan end?
1478         return true;            // Then break the match tree up
1479     }
1480     if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1481         (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1482       // These are commonly used in address expressions and can
1483       // efficiently fold into them on X64 in some cases.
1484       return false;
1485     }
1486   }
1487 
1488   // Not forceable cloning.  If shared, put it into a register.
1489   return shared;
1490 }
1491 
1492 
1493 //------------------------------Instruction Selection--------------------------
1494 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1495 // ideal nodes to machine instructions.  Trees are delimited by shared Nodes,
1496 // things the Matcher does not match (e.g., Memory), and things with different
1497 // Controls (hence forced into different blocks).  We pass in the Control
1498 // selected for this entire State tree.
1499 
1500 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1501 // Store and the Load must have identical Memories (as well as identical
1502 // pointers).  Since the Matcher does not have anything for Memory (and
1503 // does not handle DAGs), I have to match the Memory input myself.  If the
1504 // Tree root is a Store, I require all Loads to have the identical memory.
1505 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1506   // Since Label_Root is a recursive function, its possible that we might run
1507   // out of stack space.  See bugs 6272980 & 6227033 for more info.
1508   LabelRootDepth++;
1509   if (LabelRootDepth > MaxLabelRootDepth) {
1510     C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1511     return NULL;
1512   }
1513   uint care = 0;                // Edges matcher cares about
1514   uint cnt = n->req();
1515   uint i = 0;
1516 
1517   // Examine children for memory state
1518   // Can only subsume a child into your match-tree if that child's memory state
1519   // is not modified along the path to another input.
1520   // It is unsafe even if the other inputs are separate roots.
1521   Node *input_mem = NULL;
1522   for( i = 1; i < cnt; i++ ) {
1523     if( !n->match_edge(i) ) continue;
1524     Node *m = n->in(i);         // Get ith input
1525     assert( m, "expect non-null children" );
1526     if( m->is_Load() ) {
1527       if( input_mem == NULL ) {
1528         input_mem = m->in(MemNode::Memory);
1529       } else if( input_mem != m->in(MemNode::Memory) ) {
1530         input_mem = NodeSentinel;
1531       }
1532     }
1533   }
1534 
1535   for( i = 1; i < cnt; i++ ){// For my children
1536     if( !n->match_edge(i) ) continue;
1537     Node *m = n->in(i);         // Get ith input
1538     // Allocate states out of a private arena
1539     State *s = new (&_states_arena) State;
1540     svec->_kids[care++] = s;
1541     assert( care <= 2, "binary only for now" );
1542 
1543     // Recursively label the State tree.
1544     s->_kids[0] = NULL;
1545     s->_kids[1] = NULL;
1546     s->_leaf = m;
1547 
1548     // Check for leaves of the State Tree; things that cannot be a part of
1549     // the current tree.  If it finds any, that value is matched as a
1550     // register operand.  If not, then the normal matching is used.
1551     if( match_into_reg(n, m, control, i, is_shared(m)) ||
1552         //
1553         // Stop recursion if this is LoadNode and the root of this tree is a
1554         // StoreNode and the load & store have different memories.
1555         ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1556         // Can NOT include the match of a subtree when its memory state
1557         // is used by any of the other subtrees
1558         (input_mem == NodeSentinel) ) {
1559 #ifndef PRODUCT
1560       // Print when we exclude matching due to different memory states at input-loads
1561       if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1562         && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1563         tty->print_cr("invalid input_mem");
1564       }
1565 #endif
1566       // Switch to a register-only opcode; this value must be in a register
1567       // and cannot be subsumed as part of a larger instruction.
1568       s->DFA( m->ideal_reg(), m );
1569 
1570     } else {
1571       // If match tree has no control and we do, adopt it for entire tree
1572       if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1573         control = m->in(0);         // Pick up control
1574       // Else match as a normal part of the match tree.
1575       control = Label_Root(m,s,control,mem);
1576       if (C->failing()) return NULL;
1577     }
1578   }
1579 
1580 
1581   // Call DFA to match this node, and return
1582   svec->DFA( n->Opcode(), n );
1583 
1584 #ifdef ASSERT
1585   uint x;
1586   for( x = 0; x < _LAST_MACH_OPER; x++ )
1587     if( svec->valid(x) )
1588       break;
1589 
1590   if (x >= _LAST_MACH_OPER) {
1591     n->dump();
1592     svec->dump();
1593     assert( false, "bad AD file" );
1594   }
1595 #endif
1596   return control;
1597 }
1598 
1599 
1600 // Con nodes reduced using the same rule can share their MachNode
1601 // which reduces the number of copies of a constant in the final
1602 // program.  The register allocator is free to split uses later to
1603 // split live ranges.
1604 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1605   if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1606 
1607   // See if this Con has already been reduced using this rule.
1608   if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1609   MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1610   if (last != NULL && rule == last->rule()) {
1611     // Don't expect control change for DecodeN
1612     if (leaf->is_DecodeNarrowPtr())
1613       return last;
1614     // Get the new space root.
1615     Node* xroot = new_node(C->root());
1616     if (xroot == NULL) {
1617       // This shouldn't happen give the order of matching.
1618       return NULL;
1619     }
1620 
1621     // Shared constants need to have their control be root so they
1622     // can be scheduled properly.
1623     Node* control = last->in(0);
1624     if (control != xroot) {
1625       if (control == NULL || control == C->root()) {
1626         last->set_req(0, xroot);
1627       } else {
1628         assert(false, "unexpected control");
1629         return NULL;
1630       }
1631     }
1632     return last;
1633   }
1634   return NULL;
1635 }
1636 
1637 
1638 //------------------------------ReduceInst-------------------------------------
1639 // Reduce a State tree (with given Control) into a tree of MachNodes.
1640 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1641 // complicated machine Nodes.  Each MachNode covers some tree of Ideal Nodes.
1642 // Each MachNode has a number of complicated MachOper operands; each
1643 // MachOper also covers a further tree of Ideal Nodes.
1644 
1645 // The root of the Ideal match tree is always an instruction, so we enter
1646 // the recursion here.  After building the MachNode, we need to recurse
1647 // the tree checking for these cases:
1648 // (1) Child is an instruction -
1649 //     Build the instruction (recursively), add it as an edge.
1650 //     Build a simple operand (register) to hold the result of the instruction.
1651 // (2) Child is an interior part of an instruction -
1652 //     Skip over it (do nothing)
1653 // (3) Child is the start of a operand -
1654 //     Build the operand, place it inside the instruction
1655 //     Call ReduceOper.
1656 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1657   assert( rule >= NUM_OPERANDS, "called with operand rule" );
1658 
1659   MachNode* shared_node = find_shared_node(s->_leaf, rule);
1660   if (shared_node != NULL) {
1661     return shared_node;
1662   }
1663 
1664   // Build the object to represent this state & prepare for recursive calls
1665   MachNode *mach = s->MachNodeGenerator(rule);
1666   mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1667   assert( mach->_opnds[0] != NULL, "Missing result operand" );
1668   Node *leaf = s->_leaf;
1669   // Check for instruction or instruction chain rule
1670   if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1671     assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1672            "duplicating node that's already been matched");
1673     // Instruction
1674     mach->add_req( leaf->in(0) ); // Set initial control
1675     // Reduce interior of complex instruction
1676     ReduceInst_Interior( s, rule, mem, mach, 1 );
1677   } else {
1678     // Instruction chain rules are data-dependent on their inputs
1679     mach->add_req(0);             // Set initial control to none
1680     ReduceInst_Chain_Rule( s, rule, mem, mach );
1681   }
1682 
1683   // If a Memory was used, insert a Memory edge
1684   if( mem != (Node*)1 ) {
1685     mach->ins_req(MemNode::Memory,mem);
1686 #ifdef ASSERT
1687     // Verify adr type after matching memory operation
1688     const MachOper* oper = mach->memory_operand();
1689     if (oper != NULL && oper != (MachOper*)-1) {
1690       // It has a unique memory operand.  Find corresponding ideal mem node.
1691       Node* m = NULL;
1692       if (leaf->is_Mem()) {
1693         m = leaf;
1694       } else {
1695         m = _mem_node;
1696         assert(m != NULL && m->is_Mem(), "expecting memory node");
1697       }
1698       const Type* mach_at = mach->adr_type();
1699       // DecodeN node consumed by an address may have different type
1700       // then its input. Don't compare types for such case.
1701       if (m->adr_type() != mach_at &&
1702           (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1703            m->in(MemNode::Address)->is_AddP() &&
1704            m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
1705            m->in(MemNode::Address)->is_AddP() &&
1706            m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1707            m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1708         mach_at = m->adr_type();
1709       }
1710       if (m->adr_type() != mach_at) {
1711         m->dump();
1712         tty->print_cr("mach:");
1713         mach->dump(1);
1714       }
1715       assert(m->adr_type() == mach_at, "matcher should not change adr type");
1716     }
1717 #endif
1718   }
1719 
1720   // If the _leaf is an AddP, insert the base edge
1721   if (leaf->is_AddP()) {
1722     mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1723   }
1724 
1725   uint number_of_projections_prior = number_of_projections();
1726 
1727   // Perform any 1-to-many expansions required
1728   MachNode *ex = mach->Expand(s, _projection_list, mem);
1729   if (ex != mach) {
1730     assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1731     if( ex->in(1)->is_Con() )
1732       ex->in(1)->set_req(0, C->root());
1733     // Remove old node from the graph
1734     for( uint i=0; i<mach->req(); i++ ) {
1735       mach->set_req(i,NULL);
1736     }
1737 #ifdef ASSERT
1738     _new2old_map.map(ex->_idx, s->_leaf);
1739 #endif
1740   }
1741 
1742   // PhaseChaitin::fixup_spills will sometimes generate spill code
1743   // via the matcher.  By the time, nodes have been wired into the CFG,
1744   // and any further nodes generated by expand rules will be left hanging
1745   // in space, and will not get emitted as output code.  Catch this.
1746   // Also, catch any new register allocation constraints ("projections")
1747   // generated belatedly during spill code generation.
1748   if (_allocation_started) {
1749     guarantee(ex == mach, "no expand rules during spill generation");
1750     guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1751   }
1752 
1753   if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1754     // Record the con for sharing
1755     _shared_nodes.map(leaf->_idx, ex);
1756   }
1757 
1758   return ex;
1759 }
1760 
1761 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1762   // 'op' is what I am expecting to receive
1763   int op = _leftOp[rule];
1764   // Operand type to catch childs result
1765   // This is what my child will give me.
1766   int opnd_class_instance = s->_rule[op];
1767   // Choose between operand class or not.
1768   // This is what I will receive.
1769   int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1770   // New rule for child.  Chase operand classes to get the actual rule.
1771   int newrule = s->_rule[catch_op];
1772 
1773   if( newrule < NUM_OPERANDS ) {
1774     // Chain from operand or operand class, may be output of shared node
1775     assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1776             "Bad AD file: Instruction chain rule must chain from operand");
1777     // Insert operand into array of operands for this instruction
1778     mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1779 
1780     ReduceOper( s, newrule, mem, mach );
1781   } else {
1782     // Chain from the result of an instruction
1783     assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1784     mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1785     Node *mem1 = (Node*)1;
1786     debug_only(Node *save_mem_node = _mem_node;)
1787     mach->add_req( ReduceInst(s, newrule, mem1) );
1788     debug_only(_mem_node = save_mem_node;)
1789   }
1790   return;
1791 }
1792 
1793 
1794 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1795   if( s->_leaf->is_Load() ) {
1796     Node *mem2 = s->_leaf->in(MemNode::Memory);
1797     assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1798     debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1799     mem = mem2;
1800   }
1801   if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1802     if( mach->in(0) == NULL )
1803       mach->set_req(0, s->_leaf->in(0));
1804   }
1805 
1806   // Now recursively walk the state tree & add operand list.
1807   for( uint i=0; i<2; i++ ) {   // binary tree
1808     State *newstate = s->_kids[i];
1809     if( newstate == NULL ) break;      // Might only have 1 child
1810     // 'op' is what I am expecting to receive
1811     int op;
1812     if( i == 0 ) {
1813       op = _leftOp[rule];
1814     } else {
1815       op = _rightOp[rule];
1816     }
1817     // Operand type to catch childs result
1818     // This is what my child will give me.
1819     int opnd_class_instance = newstate->_rule[op];
1820     // Choose between operand class or not.
1821     // This is what I will receive.
1822     int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1823     // New rule for child.  Chase operand classes to get the actual rule.
1824     int newrule = newstate->_rule[catch_op];
1825 
1826     if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1827       // Operand/operandClass
1828       // Insert operand into array of operands for this instruction
1829       mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
1830       ReduceOper( newstate, newrule, mem, mach );
1831 
1832     } else {                    // Child is internal operand or new instruction
1833       if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1834         // internal operand --> call ReduceInst_Interior
1835         // Interior of complex instruction.  Do nothing but recurse.
1836         num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1837       } else {
1838         // instruction --> call build operand(  ) to catch result
1839         //             --> ReduceInst( newrule )
1840         mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
1841         Node *mem1 = (Node*)1;
1842         debug_only(Node *save_mem_node = _mem_node;)
1843         mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1844         debug_only(_mem_node = save_mem_node;)
1845       }
1846     }
1847     assert( mach->_opnds[num_opnds-1], "" );
1848   }
1849   return num_opnds;
1850 }
1851 
1852 // This routine walks the interior of possible complex operands.
1853 // At each point we check our children in the match tree:
1854 // (1) No children -
1855 //     We are a leaf; add _leaf field as an input to the MachNode
1856 // (2) Child is an internal operand -
1857 //     Skip over it ( do nothing )
1858 // (3) Child is an instruction -
1859 //     Call ReduceInst recursively and
1860 //     and instruction as an input to the MachNode
1861 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1862   assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1863   State *kid = s->_kids[0];
1864   assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1865 
1866   // Leaf?  And not subsumed?
1867   if( kid == NULL && !_swallowed[rule] ) {
1868     mach->add_req( s->_leaf );  // Add leaf pointer
1869     return;                     // Bail out
1870   }
1871 
1872   if( s->_leaf->is_Load() ) {
1873     assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1874     mem = s->_leaf->in(MemNode::Memory);
1875     debug_only(_mem_node = s->_leaf;)
1876   }
1877   if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1878     if( !mach->in(0) )
1879       mach->set_req(0,s->_leaf->in(0));
1880     else {
1881       assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1882     }
1883   }
1884 
1885   for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) {   // binary tree
1886     int newrule;
1887     if( i == 0)
1888       newrule = kid->_rule[_leftOp[rule]];
1889     else
1890       newrule = kid->_rule[_rightOp[rule]];
1891 
1892     if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1893       // Internal operand; recurse but do nothing else
1894       ReduceOper( kid, newrule, mem, mach );
1895 
1896     } else {                    // Child is a new instruction
1897       // Reduce the instruction, and add a direct pointer from this
1898       // machine instruction to the newly reduced one.
1899       Node *mem1 = (Node*)1;
1900       debug_only(Node *save_mem_node = _mem_node;)
1901       mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1902       debug_only(_mem_node = save_mem_node;)
1903     }
1904   }
1905 }
1906 
1907 
1908 // -------------------------------------------------------------------------
1909 // Java-Java calling convention
1910 // (what you use when Java calls Java)
1911 
1912 //------------------------------find_receiver----------------------------------
1913 // For a given signature, return the OptoReg for parameter 0.
1914 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1915   VMRegPair regs;
1916   BasicType sig_bt = T_OBJECT;
1917   calling_convention(&sig_bt, &regs, 1, is_outgoing);
1918   // Return argument 0 register.  In the LP64 build pointers
1919   // take 2 registers, but the VM wants only the 'main' name.
1920   return OptoReg::as_OptoReg(regs.first());
1921 }
1922 
1923 // This function identifies sub-graphs in which a 'load' node is
1924 // input to two different nodes, and such that it can be matched
1925 // with BMI instructions like blsi, blsr, etc.
1926 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1927 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1928 // refers to the same node.
1929 #ifdef X86
1930 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1931 // This is a temporary solution until we make DAGs expressible in ADL.
1932 template<typename ConType>
1933 class FusedPatternMatcher {
1934   Node* _op1_node;
1935   Node* _mop_node;
1936   int _con_op;
1937 
1938   static int match_next(Node* n, int next_op, int next_op_idx) {
1939     if (n->in(1) == NULL || n->in(2) == NULL) {
1940       return -1;
1941     }
1942 
1943     if (next_op_idx == -1) { // n is commutative, try rotations
1944       if (n->in(1)->Opcode() == next_op) {
1945         return 1;
1946       } else if (n->in(2)->Opcode() == next_op) {
1947         return 2;
1948       }
1949     } else {
1950       assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1951       if (n->in(next_op_idx)->Opcode() == next_op) {
1952         return next_op_idx;
1953       }
1954     }
1955     return -1;
1956   }
1957 public:
1958   FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1959     _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1960 
1961   bool match(int op1, int op1_op2_idx,  // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1962              int op2, int op2_con_idx,  // op2 and the index of the op2->con edge, -1 if op2 is commutative
1963              typename ConType::NativeType con_value) {
1964     if (_op1_node->Opcode() != op1) {
1965       return false;
1966     }
1967     if (_mop_node->outcnt() > 2) {
1968       return false;
1969     }
1970     op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
1971     if (op1_op2_idx == -1) {
1972       return false;
1973     }
1974     // Memory operation must be the other edge
1975     int op1_mop_idx = (op1_op2_idx & 1) + 1;
1976 
1977     // Check that the mop node is really what we want
1978     if (_op1_node->in(op1_mop_idx) == _mop_node) {
1979       Node *op2_node = _op1_node->in(op1_op2_idx);
1980       if (op2_node->outcnt() > 1) {
1981         return false;
1982       }
1983       assert(op2_node->Opcode() == op2, "Should be");
1984       op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
1985       if (op2_con_idx == -1) {
1986         return false;
1987       }
1988       // Memory operation must be the other edge
1989       int op2_mop_idx = (op2_con_idx & 1) + 1;
1990       // Check that the memory operation is the same node
1991       if (op2_node->in(op2_mop_idx) == _mop_node) {
1992         // Now check the constant
1993         const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
1994         if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
1995           return true;
1996         }
1997       }
1998     }
1999     return false;
2000   }
2001 };
2002 
2003 
2004 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
2005   if (n != NULL && m != NULL) {
2006     if (m->Opcode() == Op_LoadI) {
2007       FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2008       return bmii.match(Op_AndI, -1, Op_SubI,  1,  0)  ||
2009              bmii.match(Op_AndI, -1, Op_AddI, -1, -1)  ||
2010              bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2011     } else if (m->Opcode() == Op_LoadL) {
2012       FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2013       return bmil.match(Op_AndL, -1, Op_SubL,  1,  0) ||
2014              bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2015              bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2016     }
2017   }
2018   return false;
2019 }
2020 #endif // X86
2021 
2022 // A method-klass-holder may be passed in the inline_cache_reg
2023 // and then expanded into the inline_cache_reg and a method_oop register
2024 //   defined in ad_<arch>.cpp
2025 
2026 
2027 //------------------------------find_shared------------------------------------
2028 // Set bits if Node is shared or otherwise a root
2029 void Matcher::find_shared( Node *n ) {
2030   // Allocate stack of size C->unique() * 2 to avoid frequent realloc
2031   MStack mstack(C->unique() * 2);
2032   // Mark nodes as address_visited if they are inputs to an address expression
2033   VectorSet address_visited(Thread::current()->resource_area());
2034   mstack.push(n, Visit);     // Don't need to pre-visit root node
2035   while (mstack.is_nonempty()) {
2036     n = mstack.node();       // Leave node on stack
2037     Node_State nstate = mstack.state();
2038     uint nop = n->Opcode();
2039     if (nstate == Pre_Visit) {
2040       if (address_visited.test(n->_idx)) { // Visited in address already?
2041         // Flag as visited and shared now.
2042         set_visited(n);
2043       }
2044       if (is_visited(n)) {   // Visited already?
2045         // Node is shared and has no reason to clone.  Flag it as shared.
2046         // This causes it to match into a register for the sharing.
2047         set_shared(n);       // Flag as shared and
2048         mstack.pop();        // remove node from stack
2049         continue;
2050       }
2051       nstate = Visit; // Not already visited; so visit now
2052     }
2053     if (nstate == Visit) {
2054       mstack.set_state(Post_Visit);
2055       set_visited(n);   // Flag as visited now
2056       bool mem_op = false;
2057 
2058       switch( nop ) {  // Handle some opcodes special
2059       case Op_Phi:             // Treat Phis as shared roots
2060       case Op_Parm:
2061       case Op_Proj:            // All handled specially during matching
2062       case Op_SafePointScalarObject:
2063         set_shared(n);
2064         set_dontcare(n);
2065         break;
2066       case Op_If:
2067       case Op_CountedLoopEnd:
2068         mstack.set_state(Alt_Post_Visit); // Alternative way
2069         // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)).  Helps
2070         // with matching cmp/branch in 1 instruction.  The Matcher needs the
2071         // Bool and CmpX side-by-side, because it can only get at constants
2072         // that are at the leaves of Match trees, and the Bool's condition acts
2073         // as a constant here.
2074         mstack.push(n->in(1), Visit);         // Clone the Bool
2075         mstack.push(n->in(0), Pre_Visit);     // Visit control input
2076         continue; // while (mstack.is_nonempty())
2077       case Op_ConvI2D:         // These forms efficiently match with a prior
2078       case Op_ConvI2F:         //   Load but not a following Store
2079         if( n->in(1)->is_Load() &&        // Prior load
2080             n->outcnt() == 1 &&           // Not already shared
2081             n->unique_out()->is_Store() ) // Following store
2082           set_shared(n);       // Force it to be a root
2083         break;
2084       case Op_ReverseBytesI:
2085       case Op_ReverseBytesL:
2086         if( n->in(1)->is_Load() &&        // Prior load
2087             n->outcnt() == 1 )            // Not already shared
2088           set_shared(n);                  // Force it to be a root
2089         break;
2090       case Op_BoxLock:         // Cant match until we get stack-regs in ADLC
2091       case Op_IfFalse:
2092       case Op_IfTrue:
2093       case Op_MachProj:
2094       case Op_MergeMem:
2095       case Op_Catch:
2096       case Op_CatchProj:
2097       case Op_CProj:
2098       case Op_JumpProj:
2099       case Op_JProj:
2100       case Op_NeverBranch:
2101         set_dontcare(n);
2102         break;
2103       case Op_Jump:
2104         mstack.push(n->in(1), Pre_Visit);     // Switch Value (could be shared)
2105         mstack.push(n->in(0), Pre_Visit);     // Visit Control input
2106         continue;                             // while (mstack.is_nonempty())
2107       case Op_StrComp:
2108       case Op_StrEquals:
2109       case Op_StrIndexOf:
2110       case Op_AryEq:
2111       case Op_EncodeISOArray:
2112         set_shared(n); // Force result into register (it will be anyways)
2113         break;
2114       case Op_ConP: {  // Convert pointers above the centerline to NUL
2115         TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2116         const TypePtr* tp = tn->type()->is_ptr();
2117         if (tp->_ptr == TypePtr::AnyNull) {
2118           tn->set_type(TypePtr::NULL_PTR);
2119         }
2120         break;
2121       }
2122       case Op_ConN: {  // Convert narrow pointers above the centerline to NUL
2123         TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2124         const TypePtr* tp = tn->type()->make_ptr();
2125         if (tp && tp->_ptr == TypePtr::AnyNull) {
2126           tn->set_type(TypeNarrowOop::NULL_PTR);
2127         }
2128         break;
2129       }
2130       case Op_Binary:         // These are introduced in the Post_Visit state.
2131         ShouldNotReachHere();
2132         break;
2133       case Op_ClearArray:
2134       case Op_SafePoint:
2135         mem_op = true;
2136         break;
2137       default:
2138         if( n->is_Store() ) {
2139           // Do match stores, despite no ideal reg
2140           mem_op = true;
2141           break;
2142         }
2143         if( n->is_Mem() ) { // Loads and LoadStores
2144           mem_op = true;
2145           // Loads must be root of match tree due to prior load conflict
2146           if( C->subsume_loads() == false )
2147             set_shared(n);
2148         }
2149         // Fall into default case
2150         if( !n->ideal_reg() )
2151           set_dontcare(n);  // Unmatchable Nodes
2152       } // end_switch
2153 
2154       for(int i = n->req() - 1; i >= 0; --i) { // For my children
2155         Node *m = n->in(i); // Get ith input
2156         if (m == NULL) continue;  // Ignore NULLs
2157         uint mop = m->Opcode();
2158 
2159         // Must clone all producers of flags, or we will not match correctly.
2160         // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2161         // then it will match into an ideal Op_RegFlags.  Alas, the fp-flags
2162         // are also there, so we may match a float-branch to int-flags and
2163         // expect the allocator to haul the flags from the int-side to the
2164         // fp-side.  No can do.
2165         if( _must_clone[mop] ) {
2166           mstack.push(m, Visit);
2167           continue; // for(int i = ...)
2168         }
2169 
2170         if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2171           // Bases used in addresses must be shared but since
2172           // they are shared through a DecodeN they may appear
2173           // to have a single use so force sharing here.
2174           set_shared(m->in(AddPNode::Base)->in(1));
2175         }
2176 
2177         // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2178 #ifdef X86
2179         if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2180           mstack.push(m, Visit);
2181           continue;
2182         }
2183 #endif
2184 
2185         // Clone addressing expressions as they are "free" in memory access instructions
2186         if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
2187           // Some inputs for address expression are not put on stack
2188           // to avoid marking them as shared and forcing them into register
2189           // if they are used only in address expressions.
2190           // But they should be marked as shared if there are other uses
2191           // besides address expressions.
2192 
2193           Node *off = m->in(AddPNode::Offset);
2194           if( off->is_Con() &&
2195               // When there are other uses besides address expressions
2196               // put it on stack and mark as shared.
2197               !is_visited(m) ) {
2198             address_visited.test_set(m->_idx); // Flag as address_visited
2199             Node *adr = m->in(AddPNode::Address);
2200 
2201             // Intel, ARM and friends can handle 2 adds in addressing mode
2202             if( clone_shift_expressions && adr->is_AddP() &&
2203                 // AtomicAdd is not an addressing expression.
2204                 // Cheap to find it by looking for screwy base.
2205                 !adr->in(AddPNode::Base)->is_top() &&
2206                 // Are there other uses besides address expressions?
2207                 !is_visited(adr) ) {
2208               address_visited.set(adr->_idx); // Flag as address_visited
2209               Node *shift = adr->in(AddPNode::Offset);
2210               // Check for shift by small constant as well
2211               if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2212                   shift->in(2)->get_int() <= 3 &&
2213                   // Are there other uses besides address expressions?
2214                   !is_visited(shift) ) {
2215                 address_visited.set(shift->_idx); // Flag as address_visited
2216                 mstack.push(shift->in(2), Visit);
2217                 Node *conv = shift->in(1);
2218 #ifdef _LP64
2219                 // Allow Matcher to match the rule which bypass
2220                 // ConvI2L operation for an array index on LP64
2221                 // if the index value is positive.
2222                 if( conv->Opcode() == Op_ConvI2L &&
2223                     conv->as_Type()->type()->is_long()->_lo >= 0 &&
2224                     // Are there other uses besides address expressions?
2225                     !is_visited(conv) ) {
2226                   address_visited.set(conv->_idx); // Flag as address_visited
2227                   mstack.push(conv->in(1), Pre_Visit);
2228                 } else
2229 #endif
2230                 mstack.push(conv, Pre_Visit);
2231               } else {
2232                 mstack.push(shift, Pre_Visit);
2233               }
2234               mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2235               mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2236             } else {  // Sparc, Alpha, PPC and friends
2237               mstack.push(adr, Pre_Visit);
2238             }
2239 
2240             // Clone X+offset as it also folds into most addressing expressions
2241             mstack.push(off, Visit);
2242             mstack.push(m->in(AddPNode::Base), Pre_Visit);
2243             continue; // for(int i = ...)
2244           } // if( off->is_Con() )
2245         }   // if( mem_op &&
2246         mstack.push(m, Pre_Visit);
2247       }     // for(int i = ...)
2248     }
2249     else if (nstate == Alt_Post_Visit) {
2250       mstack.pop(); // Remove node from stack
2251       // We cannot remove the Cmp input from the Bool here, as the Bool may be
2252       // shared and all users of the Bool need to move the Cmp in parallel.
2253       // This leaves both the Bool and the If pointing at the Cmp.  To
2254       // prevent the Matcher from trying to Match the Cmp along both paths
2255       // BoolNode::match_edge always returns a zero.
2256 
2257       // We reorder the Op_If in a pre-order manner, so we can visit without
2258       // accidentally sharing the Cmp (the Bool and the If make 2 users).
2259       n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2260     }
2261     else if (nstate == Post_Visit) {
2262       mstack.pop(); // Remove node from stack
2263 
2264       // Now hack a few special opcodes
2265       switch( n->Opcode() ) {       // Handle some opcodes special
2266       case Op_StorePConditional:
2267       case Op_StoreIConditional:
2268       case Op_StoreLConditional:
2269       case Op_CompareAndSwapI:
2270       case Op_CompareAndSwapL:
2271       case Op_CompareAndSwapP:
2272       case Op_CompareAndSwapN: {   // Convert trinary to binary-tree
2273         Node *newval = n->in(MemNode::ValueIn );
2274         Node *oldval  = n->in(LoadStoreConditionalNode::ExpectedIn);
2275         Node *pair = new BinaryNode( oldval, newval );
2276         n->set_req(MemNode::ValueIn,pair);
2277         n->del_req(LoadStoreConditionalNode::ExpectedIn);
2278         break;
2279       }
2280       case Op_CMoveD:              // Convert trinary to binary-tree
2281       case Op_CMoveF:
2282       case Op_CMoveI:
2283       case Op_CMoveL:
2284       case Op_CMoveN:
2285       case Op_CMoveP: {
2286         // Restructure into a binary tree for Matching.  It's possible that
2287         // we could move this code up next to the graph reshaping for IfNodes
2288         // or vice-versa, but I do not want to debug this for Ladybird.
2289         // 10/2/2000 CNC.
2290         Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1));
2291         n->set_req(1,pair1);
2292         Node *pair2 = new BinaryNode(n->in(2),n->in(3));
2293         n->set_req(2,pair2);
2294         n->del_req(3);
2295         break;
2296       }
2297       case Op_LoopLimit: {
2298         Node *pair1 = new BinaryNode(n->in(1),n->in(2));
2299         n->set_req(1,pair1);
2300         n->set_req(2,n->in(3));
2301         n->del_req(3);
2302         break;
2303       }
2304       case Op_StrEquals: {
2305         Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2306         n->set_req(2,pair1);
2307         n->set_req(3,n->in(4));
2308         n->del_req(4);
2309         break;
2310       }
2311       case Op_StrComp:
2312       case Op_StrIndexOf: {
2313         Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2314         n->set_req(2,pair1);
2315         Node *pair2 = new BinaryNode(n->in(4),n->in(5));
2316         n->set_req(3,pair2);
2317         n->del_req(5);
2318         n->del_req(4);
2319         break;
2320       }
2321       case Op_EncodeISOArray: {
2322         // Restructure into a binary tree for Matching.
2323         Node* pair = new BinaryNode(n->in(3), n->in(4));
2324         n->set_req(3, pair);
2325         n->del_req(4);
2326         break;
2327       }
2328       default:
2329         break;
2330       }
2331     }
2332     else {
2333       ShouldNotReachHere();
2334     }
2335   } // end of while (mstack.is_nonempty())
2336 }
2337 
2338 #ifdef ASSERT
2339 // machine-independent root to machine-dependent root
2340 void Matcher::dump_old2new_map() {
2341   _old2new_map.dump();
2342 }
2343 #endif
2344 
2345 //---------------------------collect_null_checks-------------------------------
2346 // Find null checks in the ideal graph; write a machine-specific node for
2347 // it.  Used by later implicit-null-check handling.  Actually collects
2348 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2349 // value being tested.
2350 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2351   Node *iff = proj->in(0);
2352   if( iff->Opcode() == Op_If ) {
2353     // During matching If's have Bool & Cmp side-by-side
2354     BoolNode *b = iff->in(1)->as_Bool();
2355     Node *cmp = iff->in(2);
2356     int opc = cmp->Opcode();
2357     if (opc != Op_CmpP && opc != Op_CmpN) return;
2358 
2359     const Type* ct = cmp->in(2)->bottom_type();
2360     if (ct == TypePtr::NULL_PTR ||
2361         (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2362 
2363       bool push_it = false;
2364       if( proj->Opcode() == Op_IfTrue ) {
2365         extern int all_null_checks_found;
2366         all_null_checks_found++;
2367         if( b->_test._test == BoolTest::ne ) {
2368           push_it = true;
2369         }
2370       } else {
2371         assert( proj->Opcode() == Op_IfFalse, "" );
2372         if( b->_test._test == BoolTest::eq ) {
2373           push_it = true;
2374         }
2375       }
2376       if( push_it ) {
2377         _null_check_tests.push(proj);
2378         Node* val = cmp->in(1);
2379 #ifdef _LP64
2380         if (val->bottom_type()->isa_narrowoop() &&
2381             !Matcher::narrow_oop_use_complex_address()) {
2382           //
2383           // Look for DecodeN node which should be pinned to orig_proj.
2384           // On platforms (Sparc) which can not handle 2 adds
2385           // in addressing mode we have to keep a DecodeN node and
2386           // use it to do implicit NULL check in address.
2387           //
2388           // DecodeN node was pinned to non-null path (orig_proj) during
2389           // CastPP transformation in final_graph_reshaping_impl().
2390           //
2391           uint cnt = orig_proj->outcnt();
2392           for (uint i = 0; i < orig_proj->outcnt(); i++) {
2393             Node* d = orig_proj->raw_out(i);
2394             if (d->is_DecodeN() && d->in(1) == val) {
2395               val = d;
2396               val->set_req(0, NULL); // Unpin now.
2397               // Mark this as special case to distinguish from
2398               // a regular case: CmpP(DecodeN, NULL).
2399               val = (Node*)(((intptr_t)val) | 1);
2400               break;
2401             }
2402           }
2403         }
2404 #endif
2405         _null_check_tests.push(val);
2406       }
2407     }
2408   }
2409 }
2410 
2411 //---------------------------validate_null_checks------------------------------
2412 // Its possible that the value being NULL checked is not the root of a match
2413 // tree.  If so, I cannot use the value in an implicit null check.
2414 void Matcher::validate_null_checks( ) {
2415   uint cnt = _null_check_tests.size();
2416   for( uint i=0; i < cnt; i+=2 ) {
2417     Node *test = _null_check_tests[i];
2418     Node *val = _null_check_tests[i+1];
2419     bool is_decoden = ((intptr_t)val) & 1;
2420     val = (Node*)(((intptr_t)val) & ~1);
2421     if (has_new_node(val)) {
2422       Node* new_val = new_node(val);
2423       if (is_decoden) {
2424         assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2425         // Note: new_val may have a control edge if
2426         // the original ideal node DecodeN was matched before
2427         // it was unpinned in Matcher::collect_null_checks().
2428         // Unpin the mach node and mark it.
2429         new_val->set_req(0, NULL);
2430         new_val = (Node*)(((intptr_t)new_val) | 1);
2431       }
2432       // Is a match-tree root, so replace with the matched value
2433       _null_check_tests.map(i+1, new_val);
2434     } else {
2435       // Yank from candidate list
2436       _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2437       _null_check_tests.map(i,_null_check_tests[--cnt]);
2438       _null_check_tests.pop();
2439       _null_check_tests.pop();
2440       i-=2;
2441     }
2442   }
2443 }
2444 
2445 // Used by the DFA in dfa_xxx.cpp.  Check for a following barrier or
2446 // atomic instruction acting as a store_load barrier without any
2447 // intervening volatile load, and thus we don't need a barrier here.
2448 // We retain the Node to act as a compiler ordering barrier.
2449 bool Matcher::post_store_load_barrier(const Node* vmb) {
2450   Compile* C = Compile::current();
2451   assert(vmb->is_MemBar(), "");
2452   assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2453   const MemBarNode* membar = vmb->as_MemBar();
2454 
2455   // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2456   Node* ctrl = NULL;
2457   for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2458     Node* p = membar->fast_out(i);
2459     assert(p->is_Proj(), "only projections here");
2460     if ((p->as_Proj()->_con == TypeFunc::Control) &&
2461         !C->node_arena()->contains(p)) { // Unmatched old-space only
2462       ctrl = p;
2463       break;
2464     }
2465   }
2466   assert((ctrl != NULL), "missing control projection");
2467 
2468   for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2469     Node *x = ctrl->fast_out(j);
2470     int xop = x->Opcode();
2471 
2472     // We don't need current barrier if we see another or a lock
2473     // before seeing volatile load.
2474     //
2475     // Op_Fastunlock previously appeared in the Op_* list below.
2476     // With the advent of 1-0 lock operations we're no longer guaranteed
2477     // that a monitor exit operation contains a serializing instruction.
2478 
2479     if (xop == Op_MemBarVolatile ||
2480         xop == Op_CompareAndSwapL ||
2481         xop == Op_CompareAndSwapP ||
2482         xop == Op_CompareAndSwapN ||
2483         xop == Op_CompareAndSwapI) {
2484       return true;
2485     }
2486 
2487     // Op_FastLock previously appeared in the Op_* list above.
2488     // With biased locking we're no longer guaranteed that a monitor
2489     // enter operation contains a serializing instruction.
2490     if ((xop == Op_FastLock) && !UseBiasedLocking) {
2491       return true;
2492     }
2493 
2494     if (x->is_MemBar()) {
2495       // We must retain this membar if there is an upcoming volatile
2496       // load, which will be followed by acquire membar.
2497       if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2498         return false;
2499       } else {
2500         // For other kinds of barriers, check by pretending we
2501         // are them, and seeing if we can be removed.
2502         return post_store_load_barrier(x->as_MemBar());
2503       }
2504     }
2505 
2506     // probably not necessary to check for these
2507     if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2508       return false;
2509     }
2510   }
2511   return false;
2512 }
2513 
2514 // Check whether node n is a branch to an uncommon trap that we could
2515 // optimize as test with very high branch costs in case of going to
2516 // the uncommon trap. The code must be able to be recompiled to use
2517 // a cheaper test.
2518 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2519   // Don't do it for natives, adapters, or runtime stubs
2520   Compile *C = Compile::current();
2521   if (!C->is_method_compilation()) return false;
2522 
2523   assert(n->is_If(), "You should only call this on if nodes.");
2524   IfNode *ifn = n->as_If();
2525 
2526   Node *ifFalse = NULL;
2527   for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2528     if (ifn->fast_out(i)->is_IfFalse()) {
2529       ifFalse = ifn->fast_out(i);
2530       break;
2531     }
2532   }
2533   assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2534 
2535   Node *reg = ifFalse;
2536   int cnt = 4; // We must protect against cycles.  Limit to 4 iterations.
2537                // Alternatively use visited set?  Seems too expensive.
2538   while (reg != NULL && cnt > 0) {
2539     CallNode *call = NULL;
2540     RegionNode *nxt_reg = NULL;
2541     for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2542       Node *o = reg->fast_out(i);
2543       if (o->is_Call()) {
2544         call = o->as_Call();
2545       }
2546       if (o->is_Region()) {
2547         nxt_reg = o->as_Region();
2548       }
2549     }
2550 
2551     if (call &&
2552         call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2553       const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2554       if (trtype->isa_int() && trtype->is_int()->is_con()) {
2555         jint tr_con = trtype->is_int()->get_con();
2556         Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2557         Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2558         assert((int)reason < (int)BitsPerInt, "recode bit map");
2559 
2560         if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2561             && action != Deoptimization::Action_none) {
2562           // This uncommon trap is sure to recompile, eventually.
2563           // When that happens, C->too_many_traps will prevent
2564           // this transformation from happening again.
2565           return true;
2566         }
2567       }
2568     }
2569 
2570     reg = nxt_reg;
2571     cnt--;
2572   }
2573 
2574   return false;
2575 }
2576 
2577 //=============================================================================
2578 //---------------------------State---------------------------------------------
2579 State::State(void) {
2580 #ifdef ASSERT
2581   _id = 0;
2582   _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2583   _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2584   //memset(_cost, -1, sizeof(_cost));
2585   //memset(_rule, -1, sizeof(_rule));
2586 #endif
2587   memset(_valid, 0, sizeof(_valid));
2588 }
2589 
2590 #ifdef ASSERT
2591 State::~State() {
2592   _id = 99;
2593   _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2594   _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2595   memset(_cost, -3, sizeof(_cost));
2596   memset(_rule, -3, sizeof(_rule));
2597 }
2598 #endif
2599 
2600 #ifndef PRODUCT
2601 //---------------------------dump----------------------------------------------
2602 void State::dump() {
2603   tty->print("\n");
2604   dump(0);
2605 }
2606 
2607 void State::dump(int depth) {
2608   for( int j = 0; j < depth; j++ )
2609     tty->print("   ");
2610   tty->print("--N: ");
2611   _leaf->dump();
2612   uint i;
2613   for( i = 0; i < _LAST_MACH_OPER; i++ )
2614     // Check for valid entry
2615     if( valid(i) ) {
2616       for( int j = 0; j < depth; j++ )
2617         tty->print("   ");
2618         assert(_cost[i] != max_juint, "cost must be a valid value");
2619         assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2620         tty->print_cr("%s  %d  %s",
2621                       ruleName[i], _cost[i], ruleName[_rule[i]] );
2622       }
2623   tty->cr();
2624 
2625   for( i=0; i<2; i++ )
2626     if( _kids[i] )
2627       _kids[i]->dump(depth+1);
2628 }
2629 #endif