src/cpu/x86/vm/vmreg_x86.hpp
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*** old/src/cpu/x86/vm/vmreg_x86.hpp Fri May 8 11:59:28 2015
--- new/src/cpu/x86/vm/vmreg_x86.hpp Fri May 8 11:59:28 2015
*** 34,44 ****
--- 34,61 ----
inline bool is_FloatRegister() {
return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr;
}
inline bool is_XMMRegister() {
! return value() >= ConcreteRegisterImpl::max_fpr && value() < ConcreteRegisterImpl::max_xmm;
! int uarch_max_xmm = ConcreteRegisterImpl::max_xmm;
+
+ #ifdef _LP64
+ if (UseAVX < 3) {
+ int half_xmm = (XMMRegisterImpl::max_slots_per_register * XMMRegisterImpl::number_of_registers) / 2;
+ uarch_max_xmm -= half_xmm;
+ }
+ #endif
+
+ return (value() >= ConcreteRegisterImpl::max_fpr && value() < uarch_max_xmm);
+ }
+
+ inline bool is_KRegister() {
+ if (UseAVX > 2) {
+ return value() >= ConcreteRegisterImpl::max_xmm && value() < ConcreteRegisterImpl::max_kpr;
+ } else {
+ return false;
+ }
}
inline Register as_Register() {
assert( is_Register(), "must be");
*** 57,67 ****
--- 74,90 ----
}
inline XMMRegister as_XMMRegister() {
assert( is_XMMRegister() && is_even(value()), "must be" );
// Yuk
! return ::as_XMMRegister((value() - ConcreteRegisterImpl::max_fpr) >> 3);
! return ::as_XMMRegister((value() - ConcreteRegisterImpl::max_fpr) >> 4);
+ }
+
+ inline KRegister as_KRegister() {
+ assert(is_KRegister(), "must be");
+ // Yuk
+ return ::as_KRegister((value() - ConcreteRegisterImpl::max_xmm));
}
inline bool is_concrete() {
assert(is_reg(), "must be");
#ifndef AMD64
src/cpu/x86/vm/vmreg_x86.hpp
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