1 //
2 // Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer registers (including RSP and RBP)
173 reg_class any_reg_with_rbp(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all pointer registers (including RSP, but excluding RBP)
191 reg_class any_reg_no_rbp(RAX, RAX_H,
192 RDX, RDX_H,
193 RDI, RDI_H,
194 RSI, RSI_H,
195 RCX, RCX_H,
196 RBX, RBX_H,
197 RSP, RSP_H,
198 R8, R8_H,
199 R9, R9_H,
200 R10, R10_H,
201 R11, R11_H,
202 R12, R12_H,
203 R13, R13_H,
204 R14, R14_H,
205 R15, R15_H);
206
207 // Dynamic register class that selects at runtime between register classes
208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
211
212 // Class for all pointer registers (excluding RSP)
213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
214 RDX, RDX_H,
215 RBP, RBP_H,
216 RDI, RDI_H,
217 RSI, RSI_H,
218 RCX, RCX_H,
219 RBX, RBX_H,
220 R8, R8_H,
221 R9, R9_H,
222 R10, R10_H,
223 R11, R11_H,
224 R13, R13_H,
225 R14, R14_H);
226
227 // Class for all pointer registers (excluding RSP and RBP)
228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
229 RDX, RDX_H,
230 RDI, RDI_H,
231 RSI, RSI_H,
232 RCX, RCX_H,
233 RBX, RBX_H,
234 R8, R8_H,
235 R9, R9_H,
236 R10, R10_H,
237 R11, R11_H,
238 R13, R13_H,
239 R14, R14_H);
240
241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
243
244 // Class for all pointer registers (excluding RAX and RSP)
245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
246 RBP, RBP_H,
247 RDI, RDI_H,
248 RSI, RSI_H,
249 RCX, RCX_H,
250 RBX, RBX_H,
251 R8, R8_H,
252 R9, R9_H,
253 R10, R10_H,
254 R11, R11_H,
255 R13, R13_H,
256 R14, R14_H);
257
258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
260 RDI, RDI_H,
261 RSI, RSI_H,
262 RCX, RCX_H,
263 RBX, RBX_H,
264 R8, R8_H,
265 R9, R9_H,
266 R10, R10_H,
267 R11, R11_H,
268 R13, R13_H,
269 R14, R14_H);
270
271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
273
274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
276 RBP, RBP_H,
277 RDI, RDI_H,
278 RSI, RSI_H,
279 RCX, RCX_H,
280 R8, R8_H,
281 R9, R9_H,
282 R10, R10_H,
283 R11, R11_H,
284 R13, R13_H,
285 R14, R14_H);
286
287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 R8, R8_H,
293 R9, R9_H,
294 R10, R10_H,
295 R11, R11_H,
296 R13, R13_H,
297 R14, R14_H);
298
299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
301
302 // Singleton class for RAX pointer register
303 reg_class ptr_rax_reg(RAX, RAX_H);
304
305 // Singleton class for RBX pointer register
306 reg_class ptr_rbx_reg(RBX, RBX_H);
307
308 // Singleton class for RSI pointer register
309 reg_class ptr_rsi_reg(RSI, RSI_H);
310
311 // Singleton class for RDI pointer register
312 reg_class ptr_rdi_reg(RDI, RDI_H);
313
314 // Singleton class for stack pointer
315 reg_class ptr_rsp_reg(RSP, RSP_H);
316
317 // Singleton class for TLS pointer
318 reg_class ptr_r15_reg(R15, R15_H);
319
320 // Class for all long registers (excluding RSP)
321 reg_class long_reg_with_rbp(RAX, RAX_H,
322 RDX, RDX_H,
323 RBP, RBP_H,
324 RDI, RDI_H,
325 RSI, RSI_H,
326 RCX, RCX_H,
327 RBX, RBX_H,
328 R8, R8_H,
329 R9, R9_H,
330 R10, R10_H,
331 R11, R11_H,
332 R13, R13_H,
333 R14, R14_H);
334
335 // Class for all long registers (excluding RSP and RBP)
336 reg_class long_reg_no_rbp(RAX, RAX_H,
337 RDX, RDX_H,
338 RDI, RDI_H,
339 RSI, RSI_H,
340 RCX, RCX_H,
341 RBX, RBX_H,
342 R8, R8_H,
343 R9, R9_H,
344 R10, R10_H,
345 R11, R11_H,
346 R13, R13_H,
347 R14, R14_H);
348
349 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
350 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
351
352 // Class for all long registers (excluding RAX, RDX and RSP)
353 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
354 RDI, RDI_H,
355 RSI, RSI_H,
356 RCX, RCX_H,
357 RBX, RBX_H,
358 R8, R8_H,
359 R9, R9_H,
360 R10, R10_H,
361 R11, R11_H,
362 R13, R13_H,
363 R14, R14_H);
364
365 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
366 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
367 RSI, RSI_H,
368 RCX, RCX_H,
369 RBX, RBX_H,
370 R8, R8_H,
371 R9, R9_H,
372 R10, R10_H,
373 R11, R11_H,
374 R13, R13_H,
375 R14, R14_H);
376
377 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
378 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
379
380 // Class for all long registers (excluding RCX and RSP)
381 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
382 RDI, RDI_H,
383 RSI, RSI_H,
384 RAX, RAX_H,
385 RDX, RDX_H,
386 RBX, RBX_H,
387 R8, R8_H,
388 R9, R9_H,
389 R10, R10_H,
390 R11, R11_H,
391 R13, R13_H,
392 R14, R14_H);
393
394 // Class for all long registers (excluding RCX, RSP, and RBP)
395 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
396 RSI, RSI_H,
397 RAX, RAX_H,
398 RDX, RDX_H,
399 RBX, RBX_H,
400 R8, R8_H,
401 R9, R9_H,
402 R10, R10_H,
403 R11, R11_H,
404 R13, R13_H,
405 R14, R14_H);
406
407 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
408 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
409
410 // Singleton class for RAX long register
411 reg_class long_rax_reg(RAX, RAX_H);
412
413 // Singleton class for RCX long register
414 reg_class long_rcx_reg(RCX, RCX_H);
415
416 // Singleton class for RDX long register
417 reg_class long_rdx_reg(RDX, RDX_H);
418
419 // Class for all int registers (excluding RSP)
420 reg_class int_reg_with_rbp(RAX,
421 RDX,
422 RBP,
423 RDI,
424 RSI,
425 RCX,
426 RBX,
427 R8,
428 R9,
429 R10,
430 R11,
431 R13,
432 R14);
433
434 // Class for all int registers (excluding RSP and RBP)
435 reg_class int_reg_no_rbp(RAX,
436 RDX,
437 RDI,
438 RSI,
439 RCX,
440 RBX,
441 R8,
442 R9,
443 R10,
444 R11,
445 R13,
446 R14);
447
448 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
449 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
450
451 // Class for all int registers (excluding RCX and RSP)
452 reg_class int_no_rcx_reg_with_rbp(RAX,
453 RDX,
454 RBP,
455 RDI,
456 RSI,
457 RBX,
458 R8,
459 R9,
460 R10,
461 R11,
462 R13,
463 R14);
464
465 // Class for all int registers (excluding RCX, RSP, and RBP)
466 reg_class int_no_rcx_reg_no_rbp(RAX,
467 RDX,
468 RDI,
469 RSI,
470 RBX,
471 R8,
472 R9,
473 R10,
474 R11,
475 R13,
476 R14);
477
478 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
479 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
480
481 // Class for all int registers (excluding RAX, RDX, and RSP)
482 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
483 RDI,
484 RSI,
485 RCX,
486 RBX,
487 R8,
488 R9,
489 R10,
490 R11,
491 R13,
492 R14);
493
494 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
495 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
496 RSI,
497 RCX,
498 RBX,
499 R8,
500 R9,
501 R10,
502 R11,
503 R13,
504 R14);
505
506 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
507 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
508
509 // Singleton class for RAX int register
510 reg_class int_rax_reg(RAX);
511
512 // Singleton class for RBX int register
513 reg_class int_rbx_reg(RBX);
514
515 // Singleton class for RCX int register
516 reg_class int_rcx_reg(RCX);
517
518 // Singleton class for RCX int register
519 reg_class int_rdx_reg(RDX);
520
521 // Singleton class for RCX int register
522 reg_class int_rdi_reg(RDI);
523
524 // Singleton class for instruction pointer
525 // reg_class ip_reg(RIP);
526
527 %}
528
529 //----------SOURCE BLOCK-------------------------------------------------------
530 // This is a block of C++ code which provides values, functions, and
531 // definitions necessary in the rest of the architecture description
532 source %{
533 #define RELOC_IMM64 Assembler::imm_operand
534 #define RELOC_DISP32 Assembler::disp32_operand
535
536 #define __ _masm.
537
538 static int clear_avx_size() {
539 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
540 }
541
542 // !!!!! Special hack to get all types of calls to specify the byte offset
543 // from the start of the call to the point where the return address
544 // will point.
545 int MachCallStaticJavaNode::ret_addr_offset()
546 {
547 int offset = 5; // 5 bytes from start of call to where return address points
548 offset += clear_avx_size();
549 return offset;
550 }
551
552 int MachCallDynamicJavaNode::ret_addr_offset()
553 {
554 int offset = 15; // 15 bytes from start of call to where return address points
555 offset += clear_avx_size();
556 return offset;
557 }
558
559 int MachCallRuntimeNode::ret_addr_offset() {
560 int offset = 13; // movq r10,#addr; callq (r10)
561 offset += clear_avx_size();
562 return offset;
563 }
564
565 // Indicate if the safepoint node needs the polling page as an input,
566 // it does if the polling page is more than disp32 away.
567 bool SafePointNode::needs_polling_address_input()
568 {
569 return Assembler::is_polling_page_far();
570 }
571
572 //
573 // Compute padding required for nodes which need alignment
574 //
575
576 // The address of the call instruction needs to be 4-byte aligned to
577 // ensure that it does not span a cache line so that it can be patched.
578 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
579 {
580 current_offset += clear_avx_size(); // skip vzeroupper
581 current_offset += 1; // skip call opcode byte
582 return round_to(current_offset, alignment_required()) - current_offset;
583 }
584
585 // The address of the call instruction needs to be 4-byte aligned to
586 // ensure that it does not span a cache line so that it can be patched.
587 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
588 {
589 current_offset += clear_avx_size(); // skip vzeroupper
590 current_offset += 11; // skip movq instruction + call opcode byte
591 return round_to(current_offset, alignment_required()) - current_offset;
592 }
593
594 // EMIT_RM()
595 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
596 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
597 cbuf.insts()->emit_int8(c);
598 }
599
600 // EMIT_CC()
601 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
602 unsigned char c = (unsigned char) (f1 | f2);
603 cbuf.insts()->emit_int8(c);
604 }
605
606 // EMIT_OPCODE()
607 void emit_opcode(CodeBuffer &cbuf, int code) {
608 cbuf.insts()->emit_int8((unsigned char) code);
609 }
610
611 // EMIT_OPCODE() w/ relocation information
612 void emit_opcode(CodeBuffer &cbuf,
613 int code, relocInfo::relocType reloc, int offset, int format)
614 {
615 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
616 emit_opcode(cbuf, code);
617 }
618
619 // EMIT_D8()
620 void emit_d8(CodeBuffer &cbuf, int d8) {
621 cbuf.insts()->emit_int8((unsigned char) d8);
622 }
623
624 // EMIT_D16()
625 void emit_d16(CodeBuffer &cbuf, int d16) {
626 cbuf.insts()->emit_int16(d16);
627 }
628
629 // EMIT_D32()
630 void emit_d32(CodeBuffer &cbuf, int d32) {
631 cbuf.insts()->emit_int32(d32);
632 }
633
634 // EMIT_D64()
635 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
636 cbuf.insts()->emit_int64(d64);
637 }
638
639 // emit 32 bit value and construct relocation entry from relocInfo::relocType
640 void emit_d32_reloc(CodeBuffer& cbuf,
641 int d32,
642 relocInfo::relocType reloc,
643 int format)
644 {
645 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
646 cbuf.relocate(cbuf.insts_mark(), reloc, format);
647 cbuf.insts()->emit_int32(d32);
648 }
649
650 // emit 32 bit value and construct relocation entry from RelocationHolder
651 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
652 #ifdef ASSERT
653 if (rspec.reloc()->type() == relocInfo::oop_type &&
654 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
655 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
656 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
657 }
658 #endif
659 cbuf.relocate(cbuf.insts_mark(), rspec, format);
660 cbuf.insts()->emit_int32(d32);
661 }
662
663 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
664 address next_ip = cbuf.insts_end() + 4;
665 emit_d32_reloc(cbuf, (int) (addr - next_ip),
666 external_word_Relocation::spec(addr),
667 RELOC_DISP32);
668 }
669
670
671 // emit 64 bit value and construct relocation entry from relocInfo::relocType
672 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
673 cbuf.relocate(cbuf.insts_mark(), reloc, format);
674 cbuf.insts()->emit_int64(d64);
675 }
676
677 // emit 64 bit value and construct relocation entry from RelocationHolder
678 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
679 #ifdef ASSERT
680 if (rspec.reloc()->type() == relocInfo::oop_type &&
681 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
682 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
683 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
684 "cannot embed scavengable oops in code");
685 }
686 #endif
687 cbuf.relocate(cbuf.insts_mark(), rspec, format);
688 cbuf.insts()->emit_int64(d64);
689 }
690
691 // Access stack slot for load or store
692 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
693 {
694 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
695 if (-0x80 <= disp && disp < 0x80) {
696 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
697 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
698 emit_d8(cbuf, disp); // Displacement // R/M byte
699 } else {
700 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
701 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
702 emit_d32(cbuf, disp); // Displacement // R/M byte
703 }
704 }
705
706 // rRegI ereg, memory mem) %{ // emit_reg_mem
707 void encode_RegMem(CodeBuffer &cbuf,
708 int reg,
709 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
710 {
711 assert(disp_reloc == relocInfo::none, "cannot have disp");
712 int regenc = reg & 7;
713 int baseenc = base & 7;
714 int indexenc = index & 7;
715
716 // There is no index & no scale, use form without SIB byte
717 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
718 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
719 if (disp == 0 && base != RBP_enc && base != R13_enc) {
720 emit_rm(cbuf, 0x0, regenc, baseenc); // *
721 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
722 // If 8-bit displacement, mode 0x1
723 emit_rm(cbuf, 0x1, regenc, baseenc); // *
724 emit_d8(cbuf, disp);
725 } else {
726 // If 32-bit displacement
727 if (base == -1) { // Special flag for absolute address
728 emit_rm(cbuf, 0x0, regenc, 0x5); // *
729 if (disp_reloc != relocInfo::none) {
730 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
731 } else {
732 emit_d32(cbuf, disp);
733 }
734 } else {
735 // Normal base + offset
736 emit_rm(cbuf, 0x2, regenc, baseenc); // *
737 if (disp_reloc != relocInfo::none) {
738 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
739 } else {
740 emit_d32(cbuf, disp);
741 }
742 }
743 }
744 } else {
745 // Else, encode with the SIB byte
746 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
747 if (disp == 0 && base != RBP_enc && base != R13_enc) {
748 // If no displacement
749 emit_rm(cbuf, 0x0, regenc, 0x4); // *
750 emit_rm(cbuf, scale, indexenc, baseenc);
751 } else {
752 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
753 // If 8-bit displacement, mode 0x1
754 emit_rm(cbuf, 0x1, regenc, 0x4); // *
755 emit_rm(cbuf, scale, indexenc, baseenc);
756 emit_d8(cbuf, disp);
757 } else {
758 // If 32-bit displacement
759 if (base == 0x04 ) {
760 emit_rm(cbuf, 0x2, regenc, 0x4);
761 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
762 } else {
763 emit_rm(cbuf, 0x2, regenc, 0x4);
764 emit_rm(cbuf, scale, indexenc, baseenc); // *
765 }
766 if (disp_reloc != relocInfo::none) {
767 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
768 } else {
769 emit_d32(cbuf, disp);
770 }
771 }
772 }
773 }
774 }
775
776 // This could be in MacroAssembler but it's fairly C2 specific
777 void emit_cmpfp_fixup(MacroAssembler& _masm) {
778 Label exit;
779 __ jccb(Assembler::noParity, exit);
780 __ pushf();
781 //
782 // comiss/ucomiss instructions set ZF,PF,CF flags and
783 // zero OF,AF,SF for NaN values.
784 // Fixup flags by zeroing ZF,PF so that compare of NaN
785 // values returns 'less than' result (CF is set).
786 // Leave the rest of flags unchanged.
787 //
788 // 7 6 5 4 3 2 1 0
789 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
790 // 0 0 1 0 1 0 1 1 (0x2B)
791 //
792 __ andq(Address(rsp, 0), 0xffffff2b);
793 __ popf();
794 __ bind(exit);
795 }
796
797 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
798 Label done;
799 __ movl(dst, -1);
800 __ jcc(Assembler::parity, done);
801 __ jcc(Assembler::below, done);
802 __ setb(Assembler::notEqual, dst);
803 __ movzbl(dst, dst);
804 __ bind(done);
805 }
806
807
808 //=============================================================================
809 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
810
811 int Compile::ConstantTable::calculate_table_base_offset() const {
812 return 0; // absolute addressing, no offset
813 }
814
815 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
816 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
817 ShouldNotReachHere();
818 }
819
820 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
821 // Empty encoding
822 }
823
824 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
825 return 0;
826 }
827
828 #ifndef PRODUCT
829 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
830 st->print("# MachConstantBaseNode (empty encoding)");
831 }
832 #endif
833
834
835 //=============================================================================
836 #ifndef PRODUCT
837 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
838 Compile* C = ra_->C;
839
840 int framesize = C->frame_size_in_bytes();
841 int bangsize = C->bang_size_in_bytes();
842 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
843 // Remove wordSize for return addr which is already pushed.
844 framesize -= wordSize;
845
846 if (C->need_stack_bang(bangsize)) {
847 framesize -= wordSize;
848 st->print("# stack bang (%d bytes)", bangsize);
849 st->print("\n\t");
850 st->print("pushq rbp\t# Save rbp");
851 if (PreserveFramePointer) {
852 st->print("\n\t");
853 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
854 }
855 if (framesize) {
856 st->print("\n\t");
857 st->print("subq rsp, #%d\t# Create frame",framesize);
858 }
859 } else {
860 st->print("subq rsp, #%d\t# Create frame",framesize);
861 st->print("\n\t");
862 framesize -= wordSize;
863 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
864 if (PreserveFramePointer) {
865 st->print("\n\t");
866 st->print("movq rbp, [rsp + #%d]\t# Save the caller's SP into rbp", (framesize + wordSize));
867 }
868 }
869
870 if (VerifyStackAtCalls) {
871 st->print("\n\t");
872 framesize -= wordSize;
873 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
874 #ifdef ASSERT
875 st->print("\n\t");
876 st->print("# stack alignment check");
877 #endif
878 }
879 st->cr();
880 }
881 #endif
882
883 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
884 Compile* C = ra_->C;
885 MacroAssembler _masm(&cbuf);
886
887 int framesize = C->frame_size_in_bytes();
888 int bangsize = C->bang_size_in_bytes();
889
890 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
891
892 C->set_frame_complete(cbuf.insts_size());
893
894 if (C->has_mach_constant_base_node()) {
895 // NOTE: We set the table base offset here because users might be
896 // emitted before MachConstantBaseNode.
897 Compile::ConstantTable& constant_table = C->constant_table();
898 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
899 }
900 }
901
902 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
903 {
904 return MachNode::size(ra_); // too many variables; just compute it
905 // the hard way
906 }
907
908 int MachPrologNode::reloc() const
909 {
910 return 0; // a large enough number
911 }
912
913 //=============================================================================
914 #ifndef PRODUCT
915 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
916 {
917 Compile* C = ra_->C;
918 if (C->max_vector_size() > 16) {
919 st->print("vzeroupper");
920 st->cr(); st->print("\t");
921 }
922
923 int framesize = C->frame_size_in_bytes();
924 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
925 // Remove word for return adr already pushed
926 // and RBP
927 framesize -= 2*wordSize;
928
929 if (framesize) {
930 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
931 st->print("\t");
932 }
933
934 st->print_cr("popq rbp");
935 if (do_polling() && C->is_method_compilation()) {
936 st->print("\t");
937 if (Assembler::is_polling_page_far()) {
938 st->print_cr("movq rscratch1, #polling_page_address\n\t"
939 "testl rax, [rscratch1]\t"
940 "# Safepoint: poll for GC");
941 } else {
942 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
943 "# Safepoint: poll for GC");
944 }
945 }
946 }
947 #endif
948
949 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
950 {
951 Compile* C = ra_->C;
952 if (C->max_vector_size() > 16) {
953 // Clear upper bits of YMM registers when current compiled code uses
954 // wide vectors to avoid AVX <-> SSE transition penalty during call.
955 MacroAssembler _masm(&cbuf);
956 __ vzeroupper();
957 }
958
959 int framesize = C->frame_size_in_bytes();
960 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
961 // Remove word for return adr already pushed
962 // and RBP
963 framesize -= 2*wordSize;
964
965 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
966
967 if (framesize) {
968 emit_opcode(cbuf, Assembler::REX_W);
969 if (framesize < 0x80) {
970 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
971 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
972 emit_d8(cbuf, framesize);
973 } else {
974 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
975 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
976 emit_d32(cbuf, framesize);
977 }
978 }
979
980 // popq rbp
981 emit_opcode(cbuf, 0x58 | RBP_enc);
982
983 if (do_polling() && C->is_method_compilation()) {
984 MacroAssembler _masm(&cbuf);
985 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
986 if (Assembler::is_polling_page_far()) {
987 __ lea(rscratch1, polling_page);
988 __ relocate(relocInfo::poll_return_type);
989 __ testl(rax, Address(rscratch1, 0));
990 } else {
991 __ testl(rax, polling_page);
992 }
993 }
994 }
995
996 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
997 {
998 return MachNode::size(ra_); // too many variables; just compute it
999 // the hard way
1000 }
1001
1002 int MachEpilogNode::reloc() const
1003 {
1004 return 2; // a large enough number
1005 }
1006
1007 const Pipeline* MachEpilogNode::pipeline() const
1008 {
1009 return MachNode::pipeline_class();
1010 }
1011
1012 int MachEpilogNode::safepoint_offset() const
1013 {
1014 return 0;
1015 }
1016
1017 //=============================================================================
1018
1019 enum RC {
1020 rc_bad,
1021 rc_int,
1022 rc_float,
1023 rc_stack
1024 };
1025
1026 static enum RC rc_class(OptoReg::Name reg)
1027 {
1028 if( !OptoReg::is_valid(reg) ) return rc_bad;
1029
1030 if (OptoReg::is_stack(reg)) return rc_stack;
1031
1032 VMReg r = OptoReg::as_VMReg(reg);
1033
1034 if (r->is_Register()) return rc_int;
1035
1036 assert(r->is_XMMRegister(), "must be");
1037 return rc_float;
1038 }
1039
1040 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1041 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1042 int src_hi, int dst_hi, uint ireg, outputStream* st);
1043
1044 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1045 int stack_offset, int reg, uint ireg, outputStream* st);
1046
1047 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1048 int dst_offset, uint ireg, outputStream* st) {
1049 if (cbuf) {
1050 MacroAssembler _masm(cbuf);
1051 switch (ireg) {
1052 case Op_VecS:
1053 __ movq(Address(rsp, -8), rax);
1054 __ movl(rax, Address(rsp, src_offset));
1055 __ movl(Address(rsp, dst_offset), rax);
1056 __ movq(rax, Address(rsp, -8));
1057 break;
1058 case Op_VecD:
1059 __ pushq(Address(rsp, src_offset));
1060 __ popq (Address(rsp, dst_offset));
1061 break;
1062 case Op_VecX:
1063 __ pushq(Address(rsp, src_offset));
1064 __ popq (Address(rsp, dst_offset));
1065 __ pushq(Address(rsp, src_offset+8));
1066 __ popq (Address(rsp, dst_offset+8));
1067 break;
1068 case Op_VecY:
1069 __ vmovdqu(Address(rsp, -32), xmm0);
1070 __ vmovdqu(xmm0, Address(rsp, src_offset));
1071 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1072 __ vmovdqu(xmm0, Address(rsp, -32));
1073 break;
1074 default:
1075 ShouldNotReachHere();
1076 }
1077 #ifndef PRODUCT
1078 } else {
1079 switch (ireg) {
1080 case Op_VecS:
1081 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1082 "movl rax, [rsp + #%d]\n\t"
1083 "movl [rsp + #%d], rax\n\t"
1084 "movq rax, [rsp - #8]",
1085 src_offset, dst_offset);
1086 break;
1087 case Op_VecD:
1088 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1089 "popq [rsp + #%d]",
1090 src_offset, dst_offset);
1091 break;
1092 case Op_VecX:
1093 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1094 "popq [rsp + #%d]\n\t"
1095 "pushq [rsp + #%d]\n\t"
1096 "popq [rsp + #%d]",
1097 src_offset, dst_offset, src_offset+8, dst_offset+8);
1098 break;
1099 case Op_VecY:
1100 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1101 "vmovdqu xmm0, [rsp + #%d]\n\t"
1102 "vmovdqu [rsp + #%d], xmm0\n\t"
1103 "vmovdqu xmm0, [rsp - #32]",
1104 src_offset, dst_offset);
1105 break;
1106 default:
1107 ShouldNotReachHere();
1108 }
1109 #endif
1110 }
1111 }
1112
1113 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1114 PhaseRegAlloc* ra_,
1115 bool do_size,
1116 outputStream* st) const {
1117 assert(cbuf != NULL || st != NULL, "sanity");
1118 // Get registers to move
1119 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1120 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1121 OptoReg::Name dst_second = ra_->get_reg_second(this);
1122 OptoReg::Name dst_first = ra_->get_reg_first(this);
1123
1124 enum RC src_second_rc = rc_class(src_second);
1125 enum RC src_first_rc = rc_class(src_first);
1126 enum RC dst_second_rc = rc_class(dst_second);
1127 enum RC dst_first_rc = rc_class(dst_first);
1128
1129 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1130 "must move at least 1 register" );
1131
1132 if (src_first == dst_first && src_second == dst_second) {
1133 // Self copy, no move
1134 return 0;
1135 }
1136 if (bottom_type()->isa_vect() != NULL) {
1137 uint ireg = ideal_reg();
1138 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1139 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1140 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1141 // mem -> mem
1142 int src_offset = ra_->reg2offset(src_first);
1143 int dst_offset = ra_->reg2offset(dst_first);
1144 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1145 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1146 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1147 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1148 int stack_offset = ra_->reg2offset(dst_first);
1149 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1150 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1151 int stack_offset = ra_->reg2offset(src_first);
1152 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1153 } else {
1154 ShouldNotReachHere();
1155 }
1156 return 0;
1157 }
1158 if (src_first_rc == rc_stack) {
1159 // mem ->
1160 if (dst_first_rc == rc_stack) {
1161 // mem -> mem
1162 assert(src_second != dst_first, "overlap");
1163 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1164 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1165 // 64-bit
1166 int src_offset = ra_->reg2offset(src_first);
1167 int dst_offset = ra_->reg2offset(dst_first);
1168 if (cbuf) {
1169 MacroAssembler _masm(cbuf);
1170 __ pushq(Address(rsp, src_offset));
1171 __ popq (Address(rsp, dst_offset));
1172 #ifndef PRODUCT
1173 } else {
1174 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1175 "popq [rsp + #%d]",
1176 src_offset, dst_offset);
1177 #endif
1178 }
1179 } else {
1180 // 32-bit
1181 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1182 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1183 // No pushl/popl, so:
1184 int src_offset = ra_->reg2offset(src_first);
1185 int dst_offset = ra_->reg2offset(dst_first);
1186 if (cbuf) {
1187 MacroAssembler _masm(cbuf);
1188 __ movq(Address(rsp, -8), rax);
1189 __ movl(rax, Address(rsp, src_offset));
1190 __ movl(Address(rsp, dst_offset), rax);
1191 __ movq(rax, Address(rsp, -8));
1192 #ifndef PRODUCT
1193 } else {
1194 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1195 "movl rax, [rsp + #%d]\n\t"
1196 "movl [rsp + #%d], rax\n\t"
1197 "movq rax, [rsp - #8]",
1198 src_offset, dst_offset);
1199 #endif
1200 }
1201 }
1202 return 0;
1203 } else if (dst_first_rc == rc_int) {
1204 // mem -> gpr
1205 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1206 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1207 // 64-bit
1208 int offset = ra_->reg2offset(src_first);
1209 if (cbuf) {
1210 MacroAssembler _masm(cbuf);
1211 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1212 #ifndef PRODUCT
1213 } else {
1214 st->print("movq %s, [rsp + #%d]\t# spill",
1215 Matcher::regName[dst_first],
1216 offset);
1217 #endif
1218 }
1219 } else {
1220 // 32-bit
1221 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1222 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1223 int offset = ra_->reg2offset(src_first);
1224 if (cbuf) {
1225 MacroAssembler _masm(cbuf);
1226 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1227 #ifndef PRODUCT
1228 } else {
1229 st->print("movl %s, [rsp + #%d]\t# spill",
1230 Matcher::regName[dst_first],
1231 offset);
1232 #endif
1233 }
1234 }
1235 return 0;
1236 } else if (dst_first_rc == rc_float) {
1237 // mem-> xmm
1238 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1239 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1240 // 64-bit
1241 int offset = ra_->reg2offset(src_first);
1242 if (cbuf) {
1243 MacroAssembler _masm(cbuf);
1244 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1245 #ifndef PRODUCT
1246 } else {
1247 st->print("%s %s, [rsp + #%d]\t# spill",
1248 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1249 Matcher::regName[dst_first],
1250 offset);
1251 #endif
1252 }
1253 } else {
1254 // 32-bit
1255 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1256 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1257 int offset = ra_->reg2offset(src_first);
1258 if (cbuf) {
1259 MacroAssembler _masm(cbuf);
1260 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1261 #ifndef PRODUCT
1262 } else {
1263 st->print("movss %s, [rsp + #%d]\t# spill",
1264 Matcher::regName[dst_first],
1265 offset);
1266 #endif
1267 }
1268 }
1269 return 0;
1270 }
1271 } else if (src_first_rc == rc_int) {
1272 // gpr ->
1273 if (dst_first_rc == rc_stack) {
1274 // gpr -> mem
1275 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1276 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1277 // 64-bit
1278 int offset = ra_->reg2offset(dst_first);
1279 if (cbuf) {
1280 MacroAssembler _masm(cbuf);
1281 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1282 #ifndef PRODUCT
1283 } else {
1284 st->print("movq [rsp + #%d], %s\t# spill",
1285 offset,
1286 Matcher::regName[src_first]);
1287 #endif
1288 }
1289 } else {
1290 // 32-bit
1291 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1292 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1293 int offset = ra_->reg2offset(dst_first);
1294 if (cbuf) {
1295 MacroAssembler _masm(cbuf);
1296 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1297 #ifndef PRODUCT
1298 } else {
1299 st->print("movl [rsp + #%d], %s\t# spill",
1300 offset,
1301 Matcher::regName[src_first]);
1302 #endif
1303 }
1304 }
1305 return 0;
1306 } else if (dst_first_rc == rc_int) {
1307 // gpr -> gpr
1308 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1309 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1310 // 64-bit
1311 if (cbuf) {
1312 MacroAssembler _masm(cbuf);
1313 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1314 as_Register(Matcher::_regEncode[src_first]));
1315 #ifndef PRODUCT
1316 } else {
1317 st->print("movq %s, %s\t# spill",
1318 Matcher::regName[dst_first],
1319 Matcher::regName[src_first]);
1320 #endif
1321 }
1322 return 0;
1323 } else {
1324 // 32-bit
1325 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1326 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1327 if (cbuf) {
1328 MacroAssembler _masm(cbuf);
1329 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1330 as_Register(Matcher::_regEncode[src_first]));
1331 #ifndef PRODUCT
1332 } else {
1333 st->print("movl %s, %s\t# spill",
1334 Matcher::regName[dst_first],
1335 Matcher::regName[src_first]);
1336 #endif
1337 }
1338 return 0;
1339 }
1340 } else if (dst_first_rc == rc_float) {
1341 // gpr -> xmm
1342 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1343 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1344 // 64-bit
1345 if (cbuf) {
1346 MacroAssembler _masm(cbuf);
1347 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1348 #ifndef PRODUCT
1349 } else {
1350 st->print("movdq %s, %s\t# spill",
1351 Matcher::regName[dst_first],
1352 Matcher::regName[src_first]);
1353 #endif
1354 }
1355 } else {
1356 // 32-bit
1357 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1358 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1359 if (cbuf) {
1360 MacroAssembler _masm(cbuf);
1361 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1362 #ifndef PRODUCT
1363 } else {
1364 st->print("movdl %s, %s\t# spill",
1365 Matcher::regName[dst_first],
1366 Matcher::regName[src_first]);
1367 #endif
1368 }
1369 }
1370 return 0;
1371 }
1372 } else if (src_first_rc == rc_float) {
1373 // xmm ->
1374 if (dst_first_rc == rc_stack) {
1375 // xmm -> mem
1376 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1377 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1378 // 64-bit
1379 int offset = ra_->reg2offset(dst_first);
1380 if (cbuf) {
1381 MacroAssembler _masm(cbuf);
1382 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1383 #ifndef PRODUCT
1384 } else {
1385 st->print("movsd [rsp + #%d], %s\t# spill",
1386 offset,
1387 Matcher::regName[src_first]);
1388 #endif
1389 }
1390 } else {
1391 // 32-bit
1392 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1393 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1394 int offset = ra_->reg2offset(dst_first);
1395 if (cbuf) {
1396 MacroAssembler _masm(cbuf);
1397 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1398 #ifndef PRODUCT
1399 } else {
1400 st->print("movss [rsp + #%d], %s\t# spill",
1401 offset,
1402 Matcher::regName[src_first]);
1403 #endif
1404 }
1405 }
1406 return 0;
1407 } else if (dst_first_rc == rc_int) {
1408 // xmm -> gpr
1409 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1410 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1411 // 64-bit
1412 if (cbuf) {
1413 MacroAssembler _masm(cbuf);
1414 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1415 #ifndef PRODUCT
1416 } else {
1417 st->print("movdq %s, %s\t# spill",
1418 Matcher::regName[dst_first],
1419 Matcher::regName[src_first]);
1420 #endif
1421 }
1422 } else {
1423 // 32-bit
1424 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1425 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1426 if (cbuf) {
1427 MacroAssembler _masm(cbuf);
1428 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1429 #ifndef PRODUCT
1430 } else {
1431 st->print("movdl %s, %s\t# spill",
1432 Matcher::regName[dst_first],
1433 Matcher::regName[src_first]);
1434 #endif
1435 }
1436 }
1437 return 0;
1438 } else if (dst_first_rc == rc_float) {
1439 // xmm -> xmm
1440 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1441 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1442 // 64-bit
1443 if (cbuf) {
1444 MacroAssembler _masm(cbuf);
1445 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1446 #ifndef PRODUCT
1447 } else {
1448 st->print("%s %s, %s\t# spill",
1449 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1450 Matcher::regName[dst_first],
1451 Matcher::regName[src_first]);
1452 #endif
1453 }
1454 } else {
1455 // 32-bit
1456 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1457 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1458 if (cbuf) {
1459 MacroAssembler _masm(cbuf);
1460 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1461 #ifndef PRODUCT
1462 } else {
1463 st->print("%s %s, %s\t# spill",
1464 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1465 Matcher::regName[dst_first],
1466 Matcher::regName[src_first]);
1467 #endif
1468 }
1469 }
1470 return 0;
1471 }
1472 }
1473
1474 assert(0," foo ");
1475 Unimplemented();
1476 return 0;
1477 }
1478
1479 #ifndef PRODUCT
1480 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1481 implementation(NULL, ra_, false, st);
1482 }
1483 #endif
1484
1485 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1486 implementation(&cbuf, ra_, false, NULL);
1487 }
1488
1489 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1490 return MachNode::size(ra_);
1491 }
1492
1493 //=============================================================================
1494 #ifndef PRODUCT
1495 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1496 {
1497 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1498 int reg = ra_->get_reg_first(this);
1499 st->print("leaq %s, [rsp + #%d]\t# box lock",
1500 Matcher::regName[reg], offset);
1501 }
1502 #endif
1503
1504 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1505 {
1506 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1507 int reg = ra_->get_encode(this);
1508 if (offset >= 0x80) {
1509 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1510 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1511 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1512 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1513 emit_d32(cbuf, offset);
1514 } else {
1515 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1516 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1517 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1518 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1519 emit_d8(cbuf, offset);
1520 }
1521 }
1522
1523 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1524 {
1525 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1526 return (offset < 0x80) ? 5 : 8; // REX
1527 }
1528
1529 //=============================================================================
1530 #ifndef PRODUCT
1531 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1532 {
1533 if (UseCompressedClassPointers) {
1534 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1535 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1536 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1537 } else {
1538 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1539 "# Inline cache check");
1540 }
1541 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1542 st->print_cr("\tnop\t# nops to align entry point");
1543 }
1544 #endif
1545
1546 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1547 {
1548 MacroAssembler masm(&cbuf);
1549 uint insts_size = cbuf.insts_size();
1550 if (UseCompressedClassPointers) {
1551 masm.load_klass(rscratch1, j_rarg0);
1552 masm.cmpptr(rax, rscratch1);
1553 } else {
1554 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1555 }
1556
1557 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1558
1559 /* WARNING these NOPs are critical so that verified entry point is properly
1560 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1561 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1562 if (OptoBreakpoint) {
1563 // Leave space for int3
1564 nops_cnt -= 1;
1565 }
1566 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1567 if (nops_cnt > 0)
1568 masm.nop(nops_cnt);
1569 }
1570
1571 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1572 {
1573 return MachNode::size(ra_); // too many variables; just compute it
1574 // the hard way
1575 }
1576
1577
1578 //=============================================================================
1579
1580 int Matcher::regnum_to_fpu_offset(int regnum)
1581 {
1582 return regnum - 32; // The FP registers are in the second chunk
1583 }
1584
1585 // This is UltraSparc specific, true just means we have fast l2f conversion
1586 const bool Matcher::convL2FSupported(void) {
1587 return true;
1588 }
1589
1590 // Is this branch offset short enough that a short branch can be used?
1591 //
1592 // NOTE: If the platform does not provide any short branch variants, then
1593 // this method should return false for offset 0.
1594 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1595 // The passed offset is relative to address of the branch.
1596 // On 86 a branch displacement is calculated relative to address
1597 // of a next instruction.
1598 offset -= br_size;
1599
1600 // the short version of jmpConUCF2 contains multiple branches,
1601 // making the reach slightly less
1602 if (rule == jmpConUCF2_rule)
1603 return (-126 <= offset && offset <= 125);
1604 return (-128 <= offset && offset <= 127);
1605 }
1606
1607 const bool Matcher::isSimpleConstant64(jlong value) {
1608 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1609 //return value == (int) value; // Cf. storeImmL and immL32.
1610
1611 // Probably always true, even if a temp register is required.
1612 return true;
1613 }
1614
1615 // The ecx parameter to rep stosq for the ClearArray node is in words.
1616 const bool Matcher::init_array_count_is_in_bytes = false;
1617
1618 // Threshold size for cleararray.
1619 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1620
1621 // No additional cost for CMOVL.
1622 const int Matcher::long_cmove_cost() { return 0; }
1623
1624 // No CMOVF/CMOVD with SSE2
1625 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1626
1627 // Does the CPU require late expand (see block.cpp for description of late expand)?
1628 const bool Matcher::require_postalloc_expand = false;
1629
1630 // Should the Matcher clone shifts on addressing modes, expecting them
1631 // to be subsumed into complex addressing expressions or compute them
1632 // into registers? True for Intel but false for most RISCs
1633 const bool Matcher::clone_shift_expressions = true;
1634
1635 // Do we need to mask the count passed to shift instructions or does
1636 // the cpu only look at the lower 5/6 bits anyway?
1637 const bool Matcher::need_masked_shift_count = false;
1638
1639 bool Matcher::narrow_oop_use_complex_address() {
1640 assert(UseCompressedOops, "only for compressed oops code");
1641 return (LogMinObjAlignmentInBytes <= 3);
1642 }
1643
1644 bool Matcher::narrow_klass_use_complex_address() {
1645 assert(UseCompressedClassPointers, "only for compressed klass code");
1646 return (LogKlassAlignmentInBytes <= 3);
1647 }
1648
1649 // Is it better to copy float constants, or load them directly from
1650 // memory? Intel can load a float constant from a direct address,
1651 // requiring no extra registers. Most RISCs will have to materialize
1652 // an address into a register first, so they would do better to copy
1653 // the constant from stack.
1654 const bool Matcher::rematerialize_float_constants = true; // XXX
1655
1656 // If CPU can load and store mis-aligned doubles directly then no
1657 // fixup is needed. Else we split the double into 2 integer pieces
1658 // and move it piece-by-piece. Only happens when passing doubles into
1659 // C code as the Java calling convention forces doubles to be aligned.
1660 const bool Matcher::misaligned_doubles_ok = true;
1661
1662 // No-op on amd64
1663 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1664
1665 // Advertise here if the CPU requires explicit rounding operations to
1666 // implement the UseStrictFP mode.
1667 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1668
1669 // Are floats conerted to double when stored to stack during deoptimization?
1670 // On x64 it is stored without convertion so we can use normal access.
1671 bool Matcher::float_in_double() { return false; }
1672
1673 // Do ints take an entire long register or just half?
1674 const bool Matcher::int_in_long = true;
1675
1676 // Return whether or not this register is ever used as an argument.
1677 // This function is used on startup to build the trampoline stubs in
1678 // generateOptoStub. Registers not mentioned will be killed by the VM
1679 // call in the trampoline, and arguments in those registers not be
1680 // available to the callee.
1681 bool Matcher::can_be_java_arg(int reg)
1682 {
1683 return
1684 reg == RDI_num || reg == RDI_H_num ||
1685 reg == RSI_num || reg == RSI_H_num ||
1686 reg == RDX_num || reg == RDX_H_num ||
1687 reg == RCX_num || reg == RCX_H_num ||
1688 reg == R8_num || reg == R8_H_num ||
1689 reg == R9_num || reg == R9_H_num ||
1690 reg == R12_num || reg == R12_H_num ||
1691 reg == XMM0_num || reg == XMM0b_num ||
1692 reg == XMM1_num || reg == XMM1b_num ||
1693 reg == XMM2_num || reg == XMM2b_num ||
1694 reg == XMM3_num || reg == XMM3b_num ||
1695 reg == XMM4_num || reg == XMM4b_num ||
1696 reg == XMM5_num || reg == XMM5b_num ||
1697 reg == XMM6_num || reg == XMM6b_num ||
1698 reg == XMM7_num || reg == XMM7b_num;
1699 }
1700
1701 bool Matcher::is_spillable_arg(int reg)
1702 {
1703 return can_be_java_arg(reg);
1704 }
1705
1706 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1707 // In 64 bit mode a code which use multiply when
1708 // devisor is constant is faster than hardware
1709 // DIV instruction (it uses MulHiL).
1710 return false;
1711 }
1712
1713 // Register for DIVI projection of divmodI
1714 RegMask Matcher::divI_proj_mask() {
1715 return INT_RAX_REG_mask();
1716 }
1717
1718 // Register for MODI projection of divmodI
1719 RegMask Matcher::modI_proj_mask() {
1720 return INT_RDX_REG_mask();
1721 }
1722
1723 // Register for DIVL projection of divmodL
1724 RegMask Matcher::divL_proj_mask() {
1725 return LONG_RAX_REG_mask();
1726 }
1727
1728 // Register for MODL projection of divmodL
1729 RegMask Matcher::modL_proj_mask() {
1730 return LONG_RDX_REG_mask();
1731 }
1732
1733 // Register for saving SP into on method handle invokes. Not used on x86_64.
1734 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1735 return NO_REG_mask();
1736 }
1737
1738 %}
1739
1740 //----------ENCODING BLOCK-----------------------------------------------------
1741 // This block specifies the encoding classes used by the compiler to
1742 // output byte streams. Encoding classes are parameterized macros
1743 // used by Machine Instruction Nodes in order to generate the bit
1744 // encoding of the instruction. Operands specify their base encoding
1745 // interface with the interface keyword. There are currently
1746 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1747 // COND_INTER. REG_INTER causes an operand to generate a function
1748 // which returns its register number when queried. CONST_INTER causes
1749 // an operand to generate a function which returns the value of the
1750 // constant when queried. MEMORY_INTER causes an operand to generate
1751 // four functions which return the Base Register, the Index Register,
1752 // the Scale Value, and the Offset Value of the operand when queried.
1753 // COND_INTER causes an operand to generate six functions which return
1754 // the encoding code (ie - encoding bits for the instruction)
1755 // associated with each basic boolean condition for a conditional
1756 // instruction.
1757 //
1758 // Instructions specify two basic values for encoding. Again, a
1759 // function is available to check if the constant displacement is an
1760 // oop. They use the ins_encode keyword to specify their encoding
1761 // classes (which must be a sequence of enc_class names, and their
1762 // parameters, specified in the encoding block), and they use the
1763 // opcode keyword to specify, in order, their primary, secondary, and
1764 // tertiary opcode. Only the opcode sections which a particular
1765 // instruction needs for encoding need to be specified.
1766 encode %{
1767 // Build emit functions for each basic byte or larger field in the
1768 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1769 // from C++ code in the enc_class source block. Emit functions will
1770 // live in the main source block for now. In future, we can
1771 // generalize this by adding a syntax that specifies the sizes of
1772 // fields in an order, so that the adlc can build the emit functions
1773 // automagically
1774
1775 // Emit primary opcode
1776 enc_class OpcP
1777 %{
1778 emit_opcode(cbuf, $primary);
1779 %}
1780
1781 // Emit secondary opcode
1782 enc_class OpcS
1783 %{
1784 emit_opcode(cbuf, $secondary);
1785 %}
1786
1787 // Emit tertiary opcode
1788 enc_class OpcT
1789 %{
1790 emit_opcode(cbuf, $tertiary);
1791 %}
1792
1793 // Emit opcode directly
1794 enc_class Opcode(immI d8)
1795 %{
1796 emit_opcode(cbuf, $d8$$constant);
1797 %}
1798
1799 // Emit size prefix
1800 enc_class SizePrefix
1801 %{
1802 emit_opcode(cbuf, 0x66);
1803 %}
1804
1805 enc_class reg(rRegI reg)
1806 %{
1807 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1808 %}
1809
1810 enc_class reg_reg(rRegI dst, rRegI src)
1811 %{
1812 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1813 %}
1814
1815 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1816 %{
1817 emit_opcode(cbuf, $opcode$$constant);
1818 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1819 %}
1820
1821 enc_class cdql_enc(no_rax_rdx_RegI div)
1822 %{
1823 // Full implementation of Java idiv and irem; checks for
1824 // special case as described in JVM spec., p.243 & p.271.
1825 //
1826 // normal case special case
1827 //
1828 // input : rax: dividend min_int
1829 // reg: divisor -1
1830 //
1831 // output: rax: quotient (= rax idiv reg) min_int
1832 // rdx: remainder (= rax irem reg) 0
1833 //
1834 // Code sequnce:
1835 //
1836 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1837 // 5: 75 07/08 jne e <normal>
1838 // 7: 33 d2 xor %edx,%edx
1839 // [div >= 8 -> offset + 1]
1840 // [REX_B]
1841 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1842 // c: 74 03/04 je 11 <done>
1843 // 000000000000000e <normal>:
1844 // e: 99 cltd
1845 // [div >= 8 -> offset + 1]
1846 // [REX_B]
1847 // f: f7 f9 idiv $div
1848 // 0000000000000011 <done>:
1849
1850 // cmp $0x80000000,%eax
1851 emit_opcode(cbuf, 0x3d);
1852 emit_d8(cbuf, 0x00);
1853 emit_d8(cbuf, 0x00);
1854 emit_d8(cbuf, 0x00);
1855 emit_d8(cbuf, 0x80);
1856
1857 // jne e <normal>
1858 emit_opcode(cbuf, 0x75);
1859 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1860
1861 // xor %edx,%edx
1862 emit_opcode(cbuf, 0x33);
1863 emit_d8(cbuf, 0xD2);
1864
1865 // cmp $0xffffffffffffffff,%ecx
1866 if ($div$$reg >= 8) {
1867 emit_opcode(cbuf, Assembler::REX_B);
1868 }
1869 emit_opcode(cbuf, 0x83);
1870 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1871 emit_d8(cbuf, 0xFF);
1872
1873 // je 11 <done>
1874 emit_opcode(cbuf, 0x74);
1875 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1876
1877 // <normal>
1878 // cltd
1879 emit_opcode(cbuf, 0x99);
1880
1881 // idivl (note: must be emitted by the user of this rule)
1882 // <done>
1883 %}
1884
1885 enc_class cdqq_enc(no_rax_rdx_RegL div)
1886 %{
1887 // Full implementation of Java ldiv and lrem; checks for
1888 // special case as described in JVM spec., p.243 & p.271.
1889 //
1890 // normal case special case
1891 //
1892 // input : rax: dividend min_long
1893 // reg: divisor -1
1894 //
1895 // output: rax: quotient (= rax idiv reg) min_long
1896 // rdx: remainder (= rax irem reg) 0
1897 //
1898 // Code sequnce:
1899 //
1900 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1901 // 7: 00 00 80
1902 // a: 48 39 d0 cmp %rdx,%rax
1903 // d: 75 08 jne 17 <normal>
1904 // f: 33 d2 xor %edx,%edx
1905 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1906 // 15: 74 05 je 1c <done>
1907 // 0000000000000017 <normal>:
1908 // 17: 48 99 cqto
1909 // 19: 48 f7 f9 idiv $div
1910 // 000000000000001c <done>:
1911
1912 // mov $0x8000000000000000,%rdx
1913 emit_opcode(cbuf, Assembler::REX_W);
1914 emit_opcode(cbuf, 0xBA);
1915 emit_d8(cbuf, 0x00);
1916 emit_d8(cbuf, 0x00);
1917 emit_d8(cbuf, 0x00);
1918 emit_d8(cbuf, 0x00);
1919 emit_d8(cbuf, 0x00);
1920 emit_d8(cbuf, 0x00);
1921 emit_d8(cbuf, 0x00);
1922 emit_d8(cbuf, 0x80);
1923
1924 // cmp %rdx,%rax
1925 emit_opcode(cbuf, Assembler::REX_W);
1926 emit_opcode(cbuf, 0x39);
1927 emit_d8(cbuf, 0xD0);
1928
1929 // jne 17 <normal>
1930 emit_opcode(cbuf, 0x75);
1931 emit_d8(cbuf, 0x08);
1932
1933 // xor %edx,%edx
1934 emit_opcode(cbuf, 0x33);
1935 emit_d8(cbuf, 0xD2);
1936
1937 // cmp $0xffffffffffffffff,$div
1938 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1939 emit_opcode(cbuf, 0x83);
1940 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1941 emit_d8(cbuf, 0xFF);
1942
1943 // je 1e <done>
1944 emit_opcode(cbuf, 0x74);
1945 emit_d8(cbuf, 0x05);
1946
1947 // <normal>
1948 // cqto
1949 emit_opcode(cbuf, Assembler::REX_W);
1950 emit_opcode(cbuf, 0x99);
1951
1952 // idivq (note: must be emitted by the user of this rule)
1953 // <done>
1954 %}
1955
1956 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1957 enc_class OpcSE(immI imm)
1958 %{
1959 // Emit primary opcode and set sign-extend bit
1960 // Check for 8-bit immediate, and set sign extend bit in opcode
1961 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1962 emit_opcode(cbuf, $primary | 0x02);
1963 } else {
1964 // 32-bit immediate
1965 emit_opcode(cbuf, $primary);
1966 }
1967 %}
1968
1969 enc_class OpcSErm(rRegI dst, immI imm)
1970 %{
1971 // OpcSEr/m
1972 int dstenc = $dst$$reg;
1973 if (dstenc >= 8) {
1974 emit_opcode(cbuf, Assembler::REX_B);
1975 dstenc -= 8;
1976 }
1977 // Emit primary opcode and set sign-extend bit
1978 // Check for 8-bit immediate, and set sign extend bit in opcode
1979 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1980 emit_opcode(cbuf, $primary | 0x02);
1981 } else {
1982 // 32-bit immediate
1983 emit_opcode(cbuf, $primary);
1984 }
1985 // Emit r/m byte with secondary opcode, after primary opcode.
1986 emit_rm(cbuf, 0x3, $secondary, dstenc);
1987 %}
1988
1989 enc_class OpcSErm_wide(rRegL dst, immI imm)
1990 %{
1991 // OpcSEr/m
1992 int dstenc = $dst$$reg;
1993 if (dstenc < 8) {
1994 emit_opcode(cbuf, Assembler::REX_W);
1995 } else {
1996 emit_opcode(cbuf, Assembler::REX_WB);
1997 dstenc -= 8;
1998 }
1999 // Emit primary opcode and set sign-extend bit
2000 // Check for 8-bit immediate, and set sign extend bit in opcode
2001 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2002 emit_opcode(cbuf, $primary | 0x02);
2003 } else {
2004 // 32-bit immediate
2005 emit_opcode(cbuf, $primary);
2006 }
2007 // Emit r/m byte with secondary opcode, after primary opcode.
2008 emit_rm(cbuf, 0x3, $secondary, dstenc);
2009 %}
2010
2011 enc_class Con8or32(immI imm)
2012 %{
2013 // Check for 8-bit immediate, and set sign extend bit in opcode
2014 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2015 $$$emit8$imm$$constant;
2016 } else {
2017 // 32-bit immediate
2018 $$$emit32$imm$$constant;
2019 }
2020 %}
2021
2022 enc_class opc2_reg(rRegI dst)
2023 %{
2024 // BSWAP
2025 emit_cc(cbuf, $secondary, $dst$$reg);
2026 %}
2027
2028 enc_class opc3_reg(rRegI dst)
2029 %{
2030 // BSWAP
2031 emit_cc(cbuf, $tertiary, $dst$$reg);
2032 %}
2033
2034 enc_class reg_opc(rRegI div)
2035 %{
2036 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2037 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2038 %}
2039
2040 enc_class enc_cmov(cmpOp cop)
2041 %{
2042 // CMOV
2043 $$$emit8$primary;
2044 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2045 %}
2046
2047 enc_class enc_PartialSubtypeCheck()
2048 %{
2049 Register Rrdi = as_Register(RDI_enc); // result register
2050 Register Rrax = as_Register(RAX_enc); // super class
2051 Register Rrcx = as_Register(RCX_enc); // killed
2052 Register Rrsi = as_Register(RSI_enc); // sub class
2053 Label miss;
2054 const bool set_cond_codes = true;
2055
2056 MacroAssembler _masm(&cbuf);
2057 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2058 NULL, &miss,
2059 /*set_cond_codes:*/ true);
2060 if ($primary) {
2061 __ xorptr(Rrdi, Rrdi);
2062 }
2063 __ bind(miss);
2064 %}
2065
2066 enc_class clear_avx %{
2067 debug_only(int off0 = cbuf.insts_size());
2068 if (ra_->C->max_vector_size() > 16) {
2069 // Clear upper bits of YMM registers when current compiled code uses
2070 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2071 MacroAssembler _masm(&cbuf);
2072 __ vzeroupper();
2073 }
2074 debug_only(int off1 = cbuf.insts_size());
2075 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2076 %}
2077
2078 enc_class Java_To_Runtime(method meth) %{
2079 // No relocation needed
2080 MacroAssembler _masm(&cbuf);
2081 __ mov64(r10, (int64_t) $meth$$method);
2082 __ call(r10);
2083 %}
2084
2085 enc_class Java_To_Interpreter(method meth)
2086 %{
2087 // CALL Java_To_Interpreter
2088 // This is the instruction starting address for relocation info.
2089 cbuf.set_insts_mark();
2090 $$$emit8$primary;
2091 // CALL directly to the runtime
2092 emit_d32_reloc(cbuf,
2093 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2094 runtime_call_Relocation::spec(),
2095 RELOC_DISP32);
2096 %}
2097
2098 enc_class Java_Static_Call(method meth)
2099 %{
2100 // JAVA STATIC CALL
2101 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2102 // determine who we intended to call.
2103 cbuf.set_insts_mark();
2104 $$$emit8$primary;
2105
2106 if (!_method) {
2107 emit_d32_reloc(cbuf,
2108 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2109 runtime_call_Relocation::spec(),
2110 RELOC_DISP32);
2111 } else if (_optimized_virtual) {
2112 emit_d32_reloc(cbuf,
2113 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2114 opt_virtual_call_Relocation::spec(),
2115 RELOC_DISP32);
2116 } else {
2117 emit_d32_reloc(cbuf,
2118 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2119 static_call_Relocation::spec(),
2120 RELOC_DISP32);
2121 }
2122 if (_method) {
2123 // Emit stub for static call.
2124 CompiledStaticCall::emit_to_interp_stub(cbuf);
2125 }
2126 %}
2127
2128 enc_class Java_Dynamic_Call(method meth) %{
2129 MacroAssembler _masm(&cbuf);
2130 __ ic_call((address)$meth$$method);
2131 %}
2132
2133 enc_class Java_Compiled_Call(method meth)
2134 %{
2135 // JAVA COMPILED CALL
2136 int disp = in_bytes(Method:: from_compiled_offset());
2137
2138 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2139 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2140
2141 // callq *disp(%rax)
2142 cbuf.set_insts_mark();
2143 $$$emit8$primary;
2144 if (disp < 0x80) {
2145 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2146 emit_d8(cbuf, disp); // Displacement
2147 } else {
2148 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2149 emit_d32(cbuf, disp); // Displacement
2150 }
2151 %}
2152
2153 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2154 %{
2155 // SAL, SAR, SHR
2156 int dstenc = $dst$$reg;
2157 if (dstenc >= 8) {
2158 emit_opcode(cbuf, Assembler::REX_B);
2159 dstenc -= 8;
2160 }
2161 $$$emit8$primary;
2162 emit_rm(cbuf, 0x3, $secondary, dstenc);
2163 $$$emit8$shift$$constant;
2164 %}
2165
2166 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2167 %{
2168 // SAL, SAR, SHR
2169 int dstenc = $dst$$reg;
2170 if (dstenc < 8) {
2171 emit_opcode(cbuf, Assembler::REX_W);
2172 } else {
2173 emit_opcode(cbuf, Assembler::REX_WB);
2174 dstenc -= 8;
2175 }
2176 $$$emit8$primary;
2177 emit_rm(cbuf, 0x3, $secondary, dstenc);
2178 $$$emit8$shift$$constant;
2179 %}
2180
2181 enc_class load_immI(rRegI dst, immI src)
2182 %{
2183 int dstenc = $dst$$reg;
2184 if (dstenc >= 8) {
2185 emit_opcode(cbuf, Assembler::REX_B);
2186 dstenc -= 8;
2187 }
2188 emit_opcode(cbuf, 0xB8 | dstenc);
2189 $$$emit32$src$$constant;
2190 %}
2191
2192 enc_class load_immL(rRegL dst, immL src)
2193 %{
2194 int dstenc = $dst$$reg;
2195 if (dstenc < 8) {
2196 emit_opcode(cbuf, Assembler::REX_W);
2197 } else {
2198 emit_opcode(cbuf, Assembler::REX_WB);
2199 dstenc -= 8;
2200 }
2201 emit_opcode(cbuf, 0xB8 | dstenc);
2202 emit_d64(cbuf, $src$$constant);
2203 %}
2204
2205 enc_class load_immUL32(rRegL dst, immUL32 src)
2206 %{
2207 // same as load_immI, but this time we care about zeroes in the high word
2208 int dstenc = $dst$$reg;
2209 if (dstenc >= 8) {
2210 emit_opcode(cbuf, Assembler::REX_B);
2211 dstenc -= 8;
2212 }
2213 emit_opcode(cbuf, 0xB8 | dstenc);
2214 $$$emit32$src$$constant;
2215 %}
2216
2217 enc_class load_immL32(rRegL dst, immL32 src)
2218 %{
2219 int dstenc = $dst$$reg;
2220 if (dstenc < 8) {
2221 emit_opcode(cbuf, Assembler::REX_W);
2222 } else {
2223 emit_opcode(cbuf, Assembler::REX_WB);
2224 dstenc -= 8;
2225 }
2226 emit_opcode(cbuf, 0xC7);
2227 emit_rm(cbuf, 0x03, 0x00, dstenc);
2228 $$$emit32$src$$constant;
2229 %}
2230
2231 enc_class load_immP31(rRegP dst, immP32 src)
2232 %{
2233 // same as load_immI, but this time we care about zeroes in the high word
2234 int dstenc = $dst$$reg;
2235 if (dstenc >= 8) {
2236 emit_opcode(cbuf, Assembler::REX_B);
2237 dstenc -= 8;
2238 }
2239 emit_opcode(cbuf, 0xB8 | dstenc);
2240 $$$emit32$src$$constant;
2241 %}
2242
2243 enc_class load_immP(rRegP dst, immP src)
2244 %{
2245 int dstenc = $dst$$reg;
2246 if (dstenc < 8) {
2247 emit_opcode(cbuf, Assembler::REX_W);
2248 } else {
2249 emit_opcode(cbuf, Assembler::REX_WB);
2250 dstenc -= 8;
2251 }
2252 emit_opcode(cbuf, 0xB8 | dstenc);
2253 // This next line should be generated from ADLC
2254 if ($src->constant_reloc() != relocInfo::none) {
2255 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2256 } else {
2257 emit_d64(cbuf, $src$$constant);
2258 }
2259 %}
2260
2261 enc_class Con32(immI src)
2262 %{
2263 // Output immediate
2264 $$$emit32$src$$constant;
2265 %}
2266
2267 enc_class Con32F_as_bits(immF src)
2268 %{
2269 // Output Float immediate bits
2270 jfloat jf = $src$$constant;
2271 jint jf_as_bits = jint_cast(jf);
2272 emit_d32(cbuf, jf_as_bits);
2273 %}
2274
2275 enc_class Con16(immI src)
2276 %{
2277 // Output immediate
2278 $$$emit16$src$$constant;
2279 %}
2280
2281 // How is this different from Con32??? XXX
2282 enc_class Con_d32(immI src)
2283 %{
2284 emit_d32(cbuf,$src$$constant);
2285 %}
2286
2287 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2288 // Output immediate memory reference
2289 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2290 emit_d32(cbuf, 0x00);
2291 %}
2292
2293 enc_class lock_prefix()
2294 %{
2295 if (os::is_MP()) {
2296 emit_opcode(cbuf, 0xF0); // lock
2297 }
2298 %}
2299
2300 enc_class REX_mem(memory mem)
2301 %{
2302 if ($mem$$base >= 8) {
2303 if ($mem$$index < 8) {
2304 emit_opcode(cbuf, Assembler::REX_B);
2305 } else {
2306 emit_opcode(cbuf, Assembler::REX_XB);
2307 }
2308 } else {
2309 if ($mem$$index >= 8) {
2310 emit_opcode(cbuf, Assembler::REX_X);
2311 }
2312 }
2313 %}
2314
2315 enc_class REX_mem_wide(memory mem)
2316 %{
2317 if ($mem$$base >= 8) {
2318 if ($mem$$index < 8) {
2319 emit_opcode(cbuf, Assembler::REX_WB);
2320 } else {
2321 emit_opcode(cbuf, Assembler::REX_WXB);
2322 }
2323 } else {
2324 if ($mem$$index < 8) {
2325 emit_opcode(cbuf, Assembler::REX_W);
2326 } else {
2327 emit_opcode(cbuf, Assembler::REX_WX);
2328 }
2329 }
2330 %}
2331
2332 // for byte regs
2333 enc_class REX_breg(rRegI reg)
2334 %{
2335 if ($reg$$reg >= 4) {
2336 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2337 }
2338 %}
2339
2340 // for byte regs
2341 enc_class REX_reg_breg(rRegI dst, rRegI src)
2342 %{
2343 if ($dst$$reg < 8) {
2344 if ($src$$reg >= 4) {
2345 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2346 }
2347 } else {
2348 if ($src$$reg < 8) {
2349 emit_opcode(cbuf, Assembler::REX_R);
2350 } else {
2351 emit_opcode(cbuf, Assembler::REX_RB);
2352 }
2353 }
2354 %}
2355
2356 // for byte regs
2357 enc_class REX_breg_mem(rRegI reg, memory mem)
2358 %{
2359 if ($reg$$reg < 8) {
2360 if ($mem$$base < 8) {
2361 if ($mem$$index >= 8) {
2362 emit_opcode(cbuf, Assembler::REX_X);
2363 } else if ($reg$$reg >= 4) {
2364 emit_opcode(cbuf, Assembler::REX);
2365 }
2366 } else {
2367 if ($mem$$index < 8) {
2368 emit_opcode(cbuf, Assembler::REX_B);
2369 } else {
2370 emit_opcode(cbuf, Assembler::REX_XB);
2371 }
2372 }
2373 } else {
2374 if ($mem$$base < 8) {
2375 if ($mem$$index < 8) {
2376 emit_opcode(cbuf, Assembler::REX_R);
2377 } else {
2378 emit_opcode(cbuf, Assembler::REX_RX);
2379 }
2380 } else {
2381 if ($mem$$index < 8) {
2382 emit_opcode(cbuf, Assembler::REX_RB);
2383 } else {
2384 emit_opcode(cbuf, Assembler::REX_RXB);
2385 }
2386 }
2387 }
2388 %}
2389
2390 enc_class REX_reg(rRegI reg)
2391 %{
2392 if ($reg$$reg >= 8) {
2393 emit_opcode(cbuf, Assembler::REX_B);
2394 }
2395 %}
2396
2397 enc_class REX_reg_wide(rRegI reg)
2398 %{
2399 if ($reg$$reg < 8) {
2400 emit_opcode(cbuf, Assembler::REX_W);
2401 } else {
2402 emit_opcode(cbuf, Assembler::REX_WB);
2403 }
2404 %}
2405
2406 enc_class REX_reg_reg(rRegI dst, rRegI src)
2407 %{
2408 if ($dst$$reg < 8) {
2409 if ($src$$reg >= 8) {
2410 emit_opcode(cbuf, Assembler::REX_B);
2411 }
2412 } else {
2413 if ($src$$reg < 8) {
2414 emit_opcode(cbuf, Assembler::REX_R);
2415 } else {
2416 emit_opcode(cbuf, Assembler::REX_RB);
2417 }
2418 }
2419 %}
2420
2421 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2422 %{
2423 if ($dst$$reg < 8) {
2424 if ($src$$reg < 8) {
2425 emit_opcode(cbuf, Assembler::REX_W);
2426 } else {
2427 emit_opcode(cbuf, Assembler::REX_WB);
2428 }
2429 } else {
2430 if ($src$$reg < 8) {
2431 emit_opcode(cbuf, Assembler::REX_WR);
2432 } else {
2433 emit_opcode(cbuf, Assembler::REX_WRB);
2434 }
2435 }
2436 %}
2437
2438 enc_class REX_reg_mem(rRegI reg, memory mem)
2439 %{
2440 if ($reg$$reg < 8) {
2441 if ($mem$$base < 8) {
2442 if ($mem$$index >= 8) {
2443 emit_opcode(cbuf, Assembler::REX_X);
2444 }
2445 } else {
2446 if ($mem$$index < 8) {
2447 emit_opcode(cbuf, Assembler::REX_B);
2448 } else {
2449 emit_opcode(cbuf, Assembler::REX_XB);
2450 }
2451 }
2452 } else {
2453 if ($mem$$base < 8) {
2454 if ($mem$$index < 8) {
2455 emit_opcode(cbuf, Assembler::REX_R);
2456 } else {
2457 emit_opcode(cbuf, Assembler::REX_RX);
2458 }
2459 } else {
2460 if ($mem$$index < 8) {
2461 emit_opcode(cbuf, Assembler::REX_RB);
2462 } else {
2463 emit_opcode(cbuf, Assembler::REX_RXB);
2464 }
2465 }
2466 }
2467 %}
2468
2469 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2470 %{
2471 if ($reg$$reg < 8) {
2472 if ($mem$$base < 8) {
2473 if ($mem$$index < 8) {
2474 emit_opcode(cbuf, Assembler::REX_W);
2475 } else {
2476 emit_opcode(cbuf, Assembler::REX_WX);
2477 }
2478 } else {
2479 if ($mem$$index < 8) {
2480 emit_opcode(cbuf, Assembler::REX_WB);
2481 } else {
2482 emit_opcode(cbuf, Assembler::REX_WXB);
2483 }
2484 }
2485 } else {
2486 if ($mem$$base < 8) {
2487 if ($mem$$index < 8) {
2488 emit_opcode(cbuf, Assembler::REX_WR);
2489 } else {
2490 emit_opcode(cbuf, Assembler::REX_WRX);
2491 }
2492 } else {
2493 if ($mem$$index < 8) {
2494 emit_opcode(cbuf, Assembler::REX_WRB);
2495 } else {
2496 emit_opcode(cbuf, Assembler::REX_WRXB);
2497 }
2498 }
2499 }
2500 %}
2501
2502 enc_class reg_mem(rRegI ereg, memory mem)
2503 %{
2504 // High registers handle in encode_RegMem
2505 int reg = $ereg$$reg;
2506 int base = $mem$$base;
2507 int index = $mem$$index;
2508 int scale = $mem$$scale;
2509 int disp = $mem$$disp;
2510 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2511
2512 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2513 %}
2514
2515 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2516 %{
2517 int rm_byte_opcode = $rm_opcode$$constant;
2518
2519 // High registers handle in encode_RegMem
2520 int base = $mem$$base;
2521 int index = $mem$$index;
2522 int scale = $mem$$scale;
2523 int displace = $mem$$disp;
2524
2525 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2526 // working with static
2527 // globals
2528 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2529 disp_reloc);
2530 %}
2531
2532 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2533 %{
2534 int reg_encoding = $dst$$reg;
2535 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2536 int index = 0x04; // 0x04 indicates no index
2537 int scale = 0x00; // 0x00 indicates no scale
2538 int displace = $src1$$constant; // 0x00 indicates no displacement
2539 relocInfo::relocType disp_reloc = relocInfo::none;
2540 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2541 disp_reloc);
2542 %}
2543
2544 enc_class neg_reg(rRegI dst)
2545 %{
2546 int dstenc = $dst$$reg;
2547 if (dstenc >= 8) {
2548 emit_opcode(cbuf, Assembler::REX_B);
2549 dstenc -= 8;
2550 }
2551 // NEG $dst
2552 emit_opcode(cbuf, 0xF7);
2553 emit_rm(cbuf, 0x3, 0x03, dstenc);
2554 %}
2555
2556 enc_class neg_reg_wide(rRegI dst)
2557 %{
2558 int dstenc = $dst$$reg;
2559 if (dstenc < 8) {
2560 emit_opcode(cbuf, Assembler::REX_W);
2561 } else {
2562 emit_opcode(cbuf, Assembler::REX_WB);
2563 dstenc -= 8;
2564 }
2565 // NEG $dst
2566 emit_opcode(cbuf, 0xF7);
2567 emit_rm(cbuf, 0x3, 0x03, dstenc);
2568 %}
2569
2570 enc_class setLT_reg(rRegI dst)
2571 %{
2572 int dstenc = $dst$$reg;
2573 if (dstenc >= 8) {
2574 emit_opcode(cbuf, Assembler::REX_B);
2575 dstenc -= 8;
2576 } else if (dstenc >= 4) {
2577 emit_opcode(cbuf, Assembler::REX);
2578 }
2579 // SETLT $dst
2580 emit_opcode(cbuf, 0x0F);
2581 emit_opcode(cbuf, 0x9C);
2582 emit_rm(cbuf, 0x3, 0x0, dstenc);
2583 %}
2584
2585 enc_class setNZ_reg(rRegI dst)
2586 %{
2587 int dstenc = $dst$$reg;
2588 if (dstenc >= 8) {
2589 emit_opcode(cbuf, Assembler::REX_B);
2590 dstenc -= 8;
2591 } else if (dstenc >= 4) {
2592 emit_opcode(cbuf, Assembler::REX);
2593 }
2594 // SETNZ $dst
2595 emit_opcode(cbuf, 0x0F);
2596 emit_opcode(cbuf, 0x95);
2597 emit_rm(cbuf, 0x3, 0x0, dstenc);
2598 %}
2599
2600
2601 // Compare the lonogs and set -1, 0, or 1 into dst
2602 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2603 %{
2604 int src1enc = $src1$$reg;
2605 int src2enc = $src2$$reg;
2606 int dstenc = $dst$$reg;
2607
2608 // cmpq $src1, $src2
2609 if (src1enc < 8) {
2610 if (src2enc < 8) {
2611 emit_opcode(cbuf, Assembler::REX_W);
2612 } else {
2613 emit_opcode(cbuf, Assembler::REX_WB);
2614 }
2615 } else {
2616 if (src2enc < 8) {
2617 emit_opcode(cbuf, Assembler::REX_WR);
2618 } else {
2619 emit_opcode(cbuf, Assembler::REX_WRB);
2620 }
2621 }
2622 emit_opcode(cbuf, 0x3B);
2623 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2624
2625 // movl $dst, -1
2626 if (dstenc >= 8) {
2627 emit_opcode(cbuf, Assembler::REX_B);
2628 }
2629 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2630 emit_d32(cbuf, -1);
2631
2632 // jl,s done
2633 emit_opcode(cbuf, 0x7C);
2634 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2635
2636 // setne $dst
2637 if (dstenc >= 4) {
2638 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2639 }
2640 emit_opcode(cbuf, 0x0F);
2641 emit_opcode(cbuf, 0x95);
2642 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2643
2644 // movzbl $dst, $dst
2645 if (dstenc >= 4) {
2646 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2647 }
2648 emit_opcode(cbuf, 0x0F);
2649 emit_opcode(cbuf, 0xB6);
2650 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2651 %}
2652
2653 enc_class Push_ResultXD(regD dst) %{
2654 MacroAssembler _masm(&cbuf);
2655 __ fstp_d(Address(rsp, 0));
2656 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2657 __ addptr(rsp, 8);
2658 %}
2659
2660 enc_class Push_SrcXD(regD src) %{
2661 MacroAssembler _masm(&cbuf);
2662 __ subptr(rsp, 8);
2663 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2664 __ fld_d(Address(rsp, 0));
2665 %}
2666
2667
2668 enc_class enc_rethrow()
2669 %{
2670 cbuf.set_insts_mark();
2671 emit_opcode(cbuf, 0xE9); // jmp entry
2672 emit_d32_reloc(cbuf,
2673 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2674 runtime_call_Relocation::spec(),
2675 RELOC_DISP32);
2676 %}
2677
2678 %}
2679
2680
2681
2682 //----------FRAME--------------------------------------------------------------
2683 // Definition of frame structure and management information.
2684 //
2685 // S T A C K L A Y O U T Allocators stack-slot number
2686 // | (to get allocators register number
2687 // G Owned by | | v add OptoReg::stack0())
2688 // r CALLER | |
2689 // o | +--------+ pad to even-align allocators stack-slot
2690 // w V | pad0 | numbers; owned by CALLER
2691 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2692 // h ^ | in | 5
2693 // | | args | 4 Holes in incoming args owned by SELF
2694 // | | | | 3
2695 // | | +--------+
2696 // V | | old out| Empty on Intel, window on Sparc
2697 // | old |preserve| Must be even aligned.
2698 // | SP-+--------+----> Matcher::_old_SP, even aligned
2699 // | | in | 3 area for Intel ret address
2700 // Owned by |preserve| Empty on Sparc.
2701 // SELF +--------+
2702 // | | pad2 | 2 pad to align old SP
2703 // | +--------+ 1
2704 // | | locks | 0
2705 // | +--------+----> OptoReg::stack0(), even aligned
2706 // | | pad1 | 11 pad to align new SP
2707 // | +--------+
2708 // | | | 10
2709 // | | spills | 9 spills
2710 // V | | 8 (pad0 slot for callee)
2711 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2712 // ^ | out | 7
2713 // | | args | 6 Holes in outgoing args owned by CALLEE
2714 // Owned by +--------+
2715 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2716 // | new |preserve| Must be even-aligned.
2717 // | SP-+--------+----> Matcher::_new_SP, even aligned
2718 // | | |
2719 //
2720 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2721 // known from SELF's arguments and the Java calling convention.
2722 // Region 6-7 is determined per call site.
2723 // Note 2: If the calling convention leaves holes in the incoming argument
2724 // area, those holes are owned by SELF. Holes in the outgoing area
2725 // are owned by the CALLEE. Holes should not be nessecary in the
2726 // incoming area, as the Java calling convention is completely under
2727 // the control of the AD file. Doubles can be sorted and packed to
2728 // avoid holes. Holes in the outgoing arguments may be nessecary for
2729 // varargs C calling conventions.
2730 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2731 // even aligned with pad0 as needed.
2732 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2733 // region 6-11 is even aligned; it may be padded out more so that
2734 // the region from SP to FP meets the minimum stack alignment.
2735 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2736 // alignment. Region 11, pad1, may be dynamically extended so that
2737 // SP meets the minimum alignment.
2738
2739 frame
2740 %{
2741 // What direction does stack grow in (assumed to be same for C & Java)
2742 stack_direction(TOWARDS_LOW);
2743
2744 // These three registers define part of the calling convention
2745 // between compiled code and the interpreter.
2746 inline_cache_reg(RAX); // Inline Cache Register
2747 interpreter_method_oop_reg(RBX); // Method Oop Register when
2748 // calling interpreter
2749
2750 // Optional: name the operand used by cisc-spilling to access
2751 // [stack_pointer + offset]
2752 cisc_spilling_operand_name(indOffset32);
2753
2754 // Number of stack slots consumed by locking an object
2755 sync_stack_slots(2);
2756
2757 // Compiled code's Frame Pointer
2758 frame_pointer(RSP);
2759
2760 // Interpreter stores its frame pointer in a register which is
2761 // stored to the stack by I2CAdaptors.
2762 // I2CAdaptors convert from interpreted java to compiled java.
2763 interpreter_frame_pointer(RBP);
2764
2765 // Stack alignment requirement
2766 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2767
2768 // Number of stack slots between incoming argument block and the start of
2769 // a new frame. The PROLOG must add this many slots to the stack. The
2770 // EPILOG must remove this many slots. amd64 needs two slots for
2771 // return address.
2772 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2773
2774 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2775 // for calls to C. Supports the var-args backing area for register parms.
2776 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2777
2778 // The after-PROLOG location of the return address. Location of
2779 // return address specifies a type (REG or STACK) and a number
2780 // representing the register number (i.e. - use a register name) or
2781 // stack slot.
2782 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2783 // Otherwise, it is above the locks and verification slot and alignment word
2784 return_addr(STACK - 2 +
2785 round_to((Compile::current()->in_preserve_stack_slots() +
2786 Compile::current()->fixed_slots()),
2787 stack_alignment_in_slots()));
2788
2789 // Body of function which returns an integer array locating
2790 // arguments either in registers or in stack slots. Passed an array
2791 // of ideal registers called "sig" and a "length" count. Stack-slot
2792 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2793 // arguments for a CALLEE. Incoming stack arguments are
2794 // automatically biased by the preserve_stack_slots field above.
2795
2796 calling_convention
2797 %{
2798 // No difference between ingoing/outgoing just pass false
2799 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2800 %}
2801
2802 c_calling_convention
2803 %{
2804 // This is obviously always outgoing
2805 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2806 %}
2807
2808 // Location of compiled Java return values. Same as C for now.
2809 return_value
2810 %{
2811 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2812 "only return normal values");
2813
2814 static const int lo[Op_RegL + 1] = {
2815 0,
2816 0,
2817 RAX_num, // Op_RegN
2818 RAX_num, // Op_RegI
2819 RAX_num, // Op_RegP
2820 XMM0_num, // Op_RegF
2821 XMM0_num, // Op_RegD
2822 RAX_num // Op_RegL
2823 };
2824 static const int hi[Op_RegL + 1] = {
2825 0,
2826 0,
2827 OptoReg::Bad, // Op_RegN
2828 OptoReg::Bad, // Op_RegI
2829 RAX_H_num, // Op_RegP
2830 OptoReg::Bad, // Op_RegF
2831 XMM0b_num, // Op_RegD
2832 RAX_H_num // Op_RegL
2833 };
2834 // Excluded flags and vector registers.
2835 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type");
2836 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2837 %}
2838 %}
2839
2840 //----------ATTRIBUTES---------------------------------------------------------
2841 //----------Operand Attributes-------------------------------------------------
2842 op_attrib op_cost(0); // Required cost attribute
2843
2844 //----------Instruction Attributes---------------------------------------------
2845 ins_attrib ins_cost(100); // Required cost attribute
2846 ins_attrib ins_size(8); // Required size attribute (in bits)
2847 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2848 // a non-matching short branch variant
2849 // of some long branch?
2850 ins_attrib ins_alignment(1); // Required alignment attribute (must
2851 // be a power of 2) specifies the
2852 // alignment that some part of the
2853 // instruction (not necessarily the
2854 // start) requires. If > 1, a
2855 // compute_padding() function must be
2856 // provided for the instruction
2857
2858 //----------OPERANDS-----------------------------------------------------------
2859 // Operand definitions must precede instruction definitions for correct parsing
2860 // in the ADLC because operands constitute user defined types which are used in
2861 // instruction definitions.
2862
2863 //----------Simple Operands----------------------------------------------------
2864 // Immediate Operands
2865 // Integer Immediate
2866 operand immI()
2867 %{
2868 match(ConI);
2869
2870 op_cost(10);
2871 format %{ %}
2872 interface(CONST_INTER);
2873 %}
2874
2875 // Constant for test vs zero
2876 operand immI0()
2877 %{
2878 predicate(n->get_int() == 0);
2879 match(ConI);
2880
2881 op_cost(0);
2882 format %{ %}
2883 interface(CONST_INTER);
2884 %}
2885
2886 // Constant for increment
2887 operand immI1()
2888 %{
2889 predicate(n->get_int() == 1);
2890 match(ConI);
2891
2892 op_cost(0);
2893 format %{ %}
2894 interface(CONST_INTER);
2895 %}
2896
2897 // Constant for decrement
2898 operand immI_M1()
2899 %{
2900 predicate(n->get_int() == -1);
2901 match(ConI);
2902
2903 op_cost(0);
2904 format %{ %}
2905 interface(CONST_INTER);
2906 %}
2907
2908 // Valid scale values for addressing modes
2909 operand immI2()
2910 %{
2911 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2912 match(ConI);
2913
2914 format %{ %}
2915 interface(CONST_INTER);
2916 %}
2917
2918 operand immI8()
2919 %{
2920 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2921 match(ConI);
2922
2923 op_cost(5);
2924 format %{ %}
2925 interface(CONST_INTER);
2926 %}
2927
2928 operand immI16()
2929 %{
2930 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2931 match(ConI);
2932
2933 op_cost(10);
2934 format %{ %}
2935 interface(CONST_INTER);
2936 %}
2937
2938 // Int Immediate non-negative
2939 operand immU31()
2940 %{
2941 predicate(n->get_int() >= 0);
2942 match(ConI);
2943
2944 op_cost(0);
2945 format %{ %}
2946 interface(CONST_INTER);
2947 %}
2948
2949 // Constant for long shifts
2950 operand immI_32()
2951 %{
2952 predicate( n->get_int() == 32 );
2953 match(ConI);
2954
2955 op_cost(0);
2956 format %{ %}
2957 interface(CONST_INTER);
2958 %}
2959
2960 // Constant for long shifts
2961 operand immI_64()
2962 %{
2963 predicate( n->get_int() == 64 );
2964 match(ConI);
2965
2966 op_cost(0);
2967 format %{ %}
2968 interface(CONST_INTER);
2969 %}
2970
2971 // Pointer Immediate
2972 operand immP()
2973 %{
2974 match(ConP);
2975
2976 op_cost(10);
2977 format %{ %}
2978 interface(CONST_INTER);
2979 %}
2980
2981 // NULL Pointer Immediate
2982 operand immP0()
2983 %{
2984 predicate(n->get_ptr() == 0);
2985 match(ConP);
2986
2987 op_cost(5);
2988 format %{ %}
2989 interface(CONST_INTER);
2990 %}
2991
2992 // Pointer Immediate
2993 operand immN() %{
2994 match(ConN);
2995
2996 op_cost(10);
2997 format %{ %}
2998 interface(CONST_INTER);
2999 %}
3000
3001 operand immNKlass() %{
3002 match(ConNKlass);
3003
3004 op_cost(10);
3005 format %{ %}
3006 interface(CONST_INTER);
3007 %}
3008
3009 // NULL Pointer Immediate
3010 operand immN0() %{
3011 predicate(n->get_narrowcon() == 0);
3012 match(ConN);
3013
3014 op_cost(5);
3015 format %{ %}
3016 interface(CONST_INTER);
3017 %}
3018
3019 operand immP31()
3020 %{
3021 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3022 && (n->get_ptr() >> 31) == 0);
3023 match(ConP);
3024
3025 op_cost(5);
3026 format %{ %}
3027 interface(CONST_INTER);
3028 %}
3029
3030
3031 // Long Immediate
3032 operand immL()
3033 %{
3034 match(ConL);
3035
3036 op_cost(20);
3037 format %{ %}
3038 interface(CONST_INTER);
3039 %}
3040
3041 // Long Immediate 8-bit
3042 operand immL8()
3043 %{
3044 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3045 match(ConL);
3046
3047 op_cost(5);
3048 format %{ %}
3049 interface(CONST_INTER);
3050 %}
3051
3052 // Long Immediate 32-bit unsigned
3053 operand immUL32()
3054 %{
3055 predicate(n->get_long() == (unsigned int) (n->get_long()));
3056 match(ConL);
3057
3058 op_cost(10);
3059 format %{ %}
3060 interface(CONST_INTER);
3061 %}
3062
3063 // Long Immediate 32-bit signed
3064 operand immL32()
3065 %{
3066 predicate(n->get_long() == (int) (n->get_long()));
3067 match(ConL);
3068
3069 op_cost(15);
3070 format %{ %}
3071 interface(CONST_INTER);
3072 %}
3073
3074 // Long Immediate zero
3075 operand immL0()
3076 %{
3077 predicate(n->get_long() == 0L);
3078 match(ConL);
3079
3080 op_cost(10);
3081 format %{ %}
3082 interface(CONST_INTER);
3083 %}
3084
3085 // Constant for increment
3086 operand immL1()
3087 %{
3088 predicate(n->get_long() == 1);
3089 match(ConL);
3090
3091 format %{ %}
3092 interface(CONST_INTER);
3093 %}
3094
3095 // Constant for decrement
3096 operand immL_M1()
3097 %{
3098 predicate(n->get_long() == -1);
3099 match(ConL);
3100
3101 format %{ %}
3102 interface(CONST_INTER);
3103 %}
3104
3105 // Long Immediate: the value 10
3106 operand immL10()
3107 %{
3108 predicate(n->get_long() == 10);
3109 match(ConL);
3110
3111 format %{ %}
3112 interface(CONST_INTER);
3113 %}
3114
3115 // Long immediate from 0 to 127.
3116 // Used for a shorter form of long mul by 10.
3117 operand immL_127()
3118 %{
3119 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3120 match(ConL);
3121
3122 op_cost(10);
3123 format %{ %}
3124 interface(CONST_INTER);
3125 %}
3126
3127 // Long Immediate: low 32-bit mask
3128 operand immL_32bits()
3129 %{
3130 predicate(n->get_long() == 0xFFFFFFFFL);
3131 match(ConL);
3132 op_cost(20);
3133
3134 format %{ %}
3135 interface(CONST_INTER);
3136 %}
3137
3138 // Float Immediate zero
3139 operand immF0()
3140 %{
3141 predicate(jint_cast(n->getf()) == 0);
3142 match(ConF);
3143
3144 op_cost(5);
3145 format %{ %}
3146 interface(CONST_INTER);
3147 %}
3148
3149 // Float Immediate
3150 operand immF()
3151 %{
3152 match(ConF);
3153
3154 op_cost(15);
3155 format %{ %}
3156 interface(CONST_INTER);
3157 %}
3158
3159 // Double Immediate zero
3160 operand immD0()
3161 %{
3162 predicate(jlong_cast(n->getd()) == 0);
3163 match(ConD);
3164
3165 op_cost(5);
3166 format %{ %}
3167 interface(CONST_INTER);
3168 %}
3169
3170 // Double Immediate
3171 operand immD()
3172 %{
3173 match(ConD);
3174
3175 op_cost(15);
3176 format %{ %}
3177 interface(CONST_INTER);
3178 %}
3179
3180 // Immediates for special shifts (sign extend)
3181
3182 // Constants for increment
3183 operand immI_16()
3184 %{
3185 predicate(n->get_int() == 16);
3186 match(ConI);
3187
3188 format %{ %}
3189 interface(CONST_INTER);
3190 %}
3191
3192 operand immI_24()
3193 %{
3194 predicate(n->get_int() == 24);
3195 match(ConI);
3196
3197 format %{ %}
3198 interface(CONST_INTER);
3199 %}
3200
3201 // Constant for byte-wide masking
3202 operand immI_255()
3203 %{
3204 predicate(n->get_int() == 255);
3205 match(ConI);
3206
3207 format %{ %}
3208 interface(CONST_INTER);
3209 %}
3210
3211 // Constant for short-wide masking
3212 operand immI_65535()
3213 %{
3214 predicate(n->get_int() == 65535);
3215 match(ConI);
3216
3217 format %{ %}
3218 interface(CONST_INTER);
3219 %}
3220
3221 // Constant for byte-wide masking
3222 operand immL_255()
3223 %{
3224 predicate(n->get_long() == 255);
3225 match(ConL);
3226
3227 format %{ %}
3228 interface(CONST_INTER);
3229 %}
3230
3231 // Constant for short-wide masking
3232 operand immL_65535()
3233 %{
3234 predicate(n->get_long() == 65535);
3235 match(ConL);
3236
3237 format %{ %}
3238 interface(CONST_INTER);
3239 %}
3240
3241 // Register Operands
3242 // Integer Register
3243 operand rRegI()
3244 %{
3245 constraint(ALLOC_IN_RC(int_reg));
3246 match(RegI);
3247
3248 match(rax_RegI);
3249 match(rbx_RegI);
3250 match(rcx_RegI);
3251 match(rdx_RegI);
3252 match(rdi_RegI);
3253
3254 format %{ %}
3255 interface(REG_INTER);
3256 %}
3257
3258 // Special Registers
3259 operand rax_RegI()
3260 %{
3261 constraint(ALLOC_IN_RC(int_rax_reg));
3262 match(RegI);
3263 match(rRegI);
3264
3265 format %{ "RAX" %}
3266 interface(REG_INTER);
3267 %}
3268
3269 // Special Registers
3270 operand rbx_RegI()
3271 %{
3272 constraint(ALLOC_IN_RC(int_rbx_reg));
3273 match(RegI);
3274 match(rRegI);
3275
3276 format %{ "RBX" %}
3277 interface(REG_INTER);
3278 %}
3279
3280 operand rcx_RegI()
3281 %{
3282 constraint(ALLOC_IN_RC(int_rcx_reg));
3283 match(RegI);
3284 match(rRegI);
3285
3286 format %{ "RCX" %}
3287 interface(REG_INTER);
3288 %}
3289
3290 operand rdx_RegI()
3291 %{
3292 constraint(ALLOC_IN_RC(int_rdx_reg));
3293 match(RegI);
3294 match(rRegI);
3295
3296 format %{ "RDX" %}
3297 interface(REG_INTER);
3298 %}
3299
3300 operand rdi_RegI()
3301 %{
3302 constraint(ALLOC_IN_RC(int_rdi_reg));
3303 match(RegI);
3304 match(rRegI);
3305
3306 format %{ "RDI" %}
3307 interface(REG_INTER);
3308 %}
3309
3310 operand no_rcx_RegI()
3311 %{
3312 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3313 match(RegI);
3314 match(rax_RegI);
3315 match(rbx_RegI);
3316 match(rdx_RegI);
3317 match(rdi_RegI);
3318
3319 format %{ %}
3320 interface(REG_INTER);
3321 %}
3322
3323 operand no_rax_rdx_RegI()
3324 %{
3325 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3326 match(RegI);
3327 match(rbx_RegI);
3328 match(rcx_RegI);
3329 match(rdi_RegI);
3330
3331 format %{ %}
3332 interface(REG_INTER);
3333 %}
3334
3335 // Pointer Register
3336 operand any_RegP()
3337 %{
3338 constraint(ALLOC_IN_RC(any_reg));
3339 match(RegP);
3340 match(rax_RegP);
3341 match(rbx_RegP);
3342 match(rdi_RegP);
3343 match(rsi_RegP);
3344 match(rbp_RegP);
3345 match(r15_RegP);
3346 match(rRegP);
3347
3348 format %{ %}
3349 interface(REG_INTER);
3350 %}
3351
3352 operand rRegP()
3353 %{
3354 constraint(ALLOC_IN_RC(ptr_reg));
3355 match(RegP);
3356 match(rax_RegP);
3357 match(rbx_RegP);
3358 match(rdi_RegP);
3359 match(rsi_RegP);
3360 match(rbp_RegP); // See Q&A below about
3361 match(r15_RegP); // r15_RegP and rbp_RegP.
3362
3363 format %{ %}
3364 interface(REG_INTER);
3365 %}
3366
3367 operand rRegN() %{
3368 constraint(ALLOC_IN_RC(int_reg));
3369 match(RegN);
3370
3371 format %{ %}
3372 interface(REG_INTER);
3373 %}
3374
3375 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3376 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3377 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3378 // The output of an instruction is controlled by the allocator, which respects
3379 // register class masks, not match rules. Unless an instruction mentions
3380 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3381 // by the allocator as an input.
3382 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3383 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3384 // result, RBP is not included in the output of the instruction either.
3385
3386 operand no_rax_RegP()
3387 %{
3388 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3389 match(RegP);
3390 match(rbx_RegP);
3391 match(rsi_RegP);
3392 match(rdi_RegP);
3393
3394 format %{ %}
3395 interface(REG_INTER);
3396 %}
3397
3398 // This operand is not allowed to use RBP even if
3399 // RBP is not used to hold the frame pointer.
3400 operand no_rbp_RegP()
3401 %{
3402 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3403 match(RegP);
3404 match(rbx_RegP);
3405 match(rsi_RegP);
3406 match(rdi_RegP);
3407
3408 format %{ %}
3409 interface(REG_INTER);
3410 %}
3411
3412 operand no_rax_rbx_RegP()
3413 %{
3414 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3415 match(RegP);
3416 match(rsi_RegP);
3417 match(rdi_RegP);
3418
3419 format %{ %}
3420 interface(REG_INTER);
3421 %}
3422
3423 // Special Registers
3424 // Return a pointer value
3425 operand rax_RegP()
3426 %{
3427 constraint(ALLOC_IN_RC(ptr_rax_reg));
3428 match(RegP);
3429 match(rRegP);
3430
3431 format %{ %}
3432 interface(REG_INTER);
3433 %}
3434
3435 // Special Registers
3436 // Return a compressed pointer value
3437 operand rax_RegN()
3438 %{
3439 constraint(ALLOC_IN_RC(int_rax_reg));
3440 match(RegN);
3441 match(rRegN);
3442
3443 format %{ %}
3444 interface(REG_INTER);
3445 %}
3446
3447 // Used in AtomicAdd
3448 operand rbx_RegP()
3449 %{
3450 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3451 match(RegP);
3452 match(rRegP);
3453
3454 format %{ %}
3455 interface(REG_INTER);
3456 %}
3457
3458 operand rsi_RegP()
3459 %{
3460 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3461 match(RegP);
3462 match(rRegP);
3463
3464 format %{ %}
3465 interface(REG_INTER);
3466 %}
3467
3468 // Used in rep stosq
3469 operand rdi_RegP()
3470 %{
3471 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3472 match(RegP);
3473 match(rRegP);
3474
3475 format %{ %}
3476 interface(REG_INTER);
3477 %}
3478
3479 operand r15_RegP()
3480 %{
3481 constraint(ALLOC_IN_RC(ptr_r15_reg));
3482 match(RegP);
3483 match(rRegP);
3484
3485 format %{ %}
3486 interface(REG_INTER);
3487 %}
3488
3489 operand rRegL()
3490 %{
3491 constraint(ALLOC_IN_RC(long_reg));
3492 match(RegL);
3493 match(rax_RegL);
3494 match(rdx_RegL);
3495
3496 format %{ %}
3497 interface(REG_INTER);
3498 %}
3499
3500 // Special Registers
3501 operand no_rax_rdx_RegL()
3502 %{
3503 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3504 match(RegL);
3505 match(rRegL);
3506
3507 format %{ %}
3508 interface(REG_INTER);
3509 %}
3510
3511 operand no_rax_RegL()
3512 %{
3513 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3514 match(RegL);
3515 match(rRegL);
3516 match(rdx_RegL);
3517
3518 format %{ %}
3519 interface(REG_INTER);
3520 %}
3521
3522 operand no_rcx_RegL()
3523 %{
3524 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3525 match(RegL);
3526 match(rRegL);
3527
3528 format %{ %}
3529 interface(REG_INTER);
3530 %}
3531
3532 operand rax_RegL()
3533 %{
3534 constraint(ALLOC_IN_RC(long_rax_reg));
3535 match(RegL);
3536 match(rRegL);
3537
3538 format %{ "RAX" %}
3539 interface(REG_INTER);
3540 %}
3541
3542 operand rcx_RegL()
3543 %{
3544 constraint(ALLOC_IN_RC(long_rcx_reg));
3545 match(RegL);
3546 match(rRegL);
3547
3548 format %{ %}
3549 interface(REG_INTER);
3550 %}
3551
3552 operand rdx_RegL()
3553 %{
3554 constraint(ALLOC_IN_RC(long_rdx_reg));
3555 match(RegL);
3556 match(rRegL);
3557
3558 format %{ %}
3559 interface(REG_INTER);
3560 %}
3561
3562 // Flags register, used as output of compare instructions
3563 operand rFlagsReg()
3564 %{
3565 constraint(ALLOC_IN_RC(int_flags));
3566 match(RegFlags);
3567
3568 format %{ "RFLAGS" %}
3569 interface(REG_INTER);
3570 %}
3571
3572 // Flags register, used as output of FLOATING POINT compare instructions
3573 operand rFlagsRegU()
3574 %{
3575 constraint(ALLOC_IN_RC(int_flags));
3576 match(RegFlags);
3577
3578 format %{ "RFLAGS_U" %}
3579 interface(REG_INTER);
3580 %}
3581
3582 operand rFlagsRegUCF() %{
3583 constraint(ALLOC_IN_RC(int_flags));
3584 match(RegFlags);
3585 predicate(false);
3586
3587 format %{ "RFLAGS_U_CF" %}
3588 interface(REG_INTER);
3589 %}
3590
3591 // Float register operands
3592 operand regF()
3593 %{
3594 constraint(ALLOC_IN_RC(float_reg));
3595 match(RegF);
3596
3597 format %{ %}
3598 interface(REG_INTER);
3599 %}
3600
3601 // Double register operands
3602 operand regD()
3603 %{
3604 constraint(ALLOC_IN_RC(double_reg));
3605 match(RegD);
3606
3607 format %{ %}
3608 interface(REG_INTER);
3609 %}
3610
3611 //----------Memory Operands----------------------------------------------------
3612 // Direct Memory Operand
3613 // operand direct(immP addr)
3614 // %{
3615 // match(addr);
3616
3617 // format %{ "[$addr]" %}
3618 // interface(MEMORY_INTER) %{
3619 // base(0xFFFFFFFF);
3620 // index(0x4);
3621 // scale(0x0);
3622 // disp($addr);
3623 // %}
3624 // %}
3625
3626 // Indirect Memory Operand
3627 operand indirect(any_RegP reg)
3628 %{
3629 constraint(ALLOC_IN_RC(ptr_reg));
3630 match(reg);
3631
3632 format %{ "[$reg]" %}
3633 interface(MEMORY_INTER) %{
3634 base($reg);
3635 index(0x4);
3636 scale(0x0);
3637 disp(0x0);
3638 %}
3639 %}
3640
3641 // Indirect Memory Plus Short Offset Operand
3642 operand indOffset8(any_RegP reg, immL8 off)
3643 %{
3644 constraint(ALLOC_IN_RC(ptr_reg));
3645 match(AddP reg off);
3646
3647 format %{ "[$reg + $off (8-bit)]" %}
3648 interface(MEMORY_INTER) %{
3649 base($reg);
3650 index(0x4);
3651 scale(0x0);
3652 disp($off);
3653 %}
3654 %}
3655
3656 // Indirect Memory Plus Long Offset Operand
3657 operand indOffset32(any_RegP reg, immL32 off)
3658 %{
3659 constraint(ALLOC_IN_RC(ptr_reg));
3660 match(AddP reg off);
3661
3662 format %{ "[$reg + $off (32-bit)]" %}
3663 interface(MEMORY_INTER) %{
3664 base($reg);
3665 index(0x4);
3666 scale(0x0);
3667 disp($off);
3668 %}
3669 %}
3670
3671 // Indirect Memory Plus Index Register Plus Offset Operand
3672 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3673 %{
3674 constraint(ALLOC_IN_RC(ptr_reg));
3675 match(AddP (AddP reg lreg) off);
3676
3677 op_cost(10);
3678 format %{"[$reg + $off + $lreg]" %}
3679 interface(MEMORY_INTER) %{
3680 base($reg);
3681 index($lreg);
3682 scale(0x0);
3683 disp($off);
3684 %}
3685 %}
3686
3687 // Indirect Memory Plus Index Register Plus Offset Operand
3688 operand indIndex(any_RegP reg, rRegL lreg)
3689 %{
3690 constraint(ALLOC_IN_RC(ptr_reg));
3691 match(AddP reg lreg);
3692
3693 op_cost(10);
3694 format %{"[$reg + $lreg]" %}
3695 interface(MEMORY_INTER) %{
3696 base($reg);
3697 index($lreg);
3698 scale(0x0);
3699 disp(0x0);
3700 %}
3701 %}
3702
3703 // Indirect Memory Times Scale Plus Index Register
3704 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3705 %{
3706 constraint(ALLOC_IN_RC(ptr_reg));
3707 match(AddP reg (LShiftL lreg scale));
3708
3709 op_cost(10);
3710 format %{"[$reg + $lreg << $scale]" %}
3711 interface(MEMORY_INTER) %{
3712 base($reg);
3713 index($lreg);
3714 scale($scale);
3715 disp(0x0);
3716 %}
3717 %}
3718
3719 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3720 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3721 %{
3722 constraint(ALLOC_IN_RC(ptr_reg));
3723 match(AddP (AddP reg (LShiftL lreg scale)) off);
3724
3725 op_cost(10);
3726 format %{"[$reg + $off + $lreg << $scale]" %}
3727 interface(MEMORY_INTER) %{
3728 base($reg);
3729 index($lreg);
3730 scale($scale);
3731 disp($off);
3732 %}
3733 %}
3734
3735 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3736 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3737 %{
3738 constraint(ALLOC_IN_RC(ptr_reg));
3739 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3740 match(AddP (AddP reg (ConvI2L idx)) off);
3741
3742 op_cost(10);
3743 format %{"[$reg + $off + $idx]" %}
3744 interface(MEMORY_INTER) %{
3745 base($reg);
3746 index($idx);
3747 scale(0x0);
3748 disp($off);
3749 %}
3750 %}
3751
3752 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3753 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3754 %{
3755 constraint(ALLOC_IN_RC(ptr_reg));
3756 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3757 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3758
3759 op_cost(10);
3760 format %{"[$reg + $off + $idx << $scale]" %}
3761 interface(MEMORY_INTER) %{
3762 base($reg);
3763 index($idx);
3764 scale($scale);
3765 disp($off);
3766 %}
3767 %}
3768
3769 // Indirect Narrow Oop Plus Offset Operand
3770 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3771 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3772 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3773 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3774 constraint(ALLOC_IN_RC(ptr_reg));
3775 match(AddP (DecodeN reg) off);
3776
3777 op_cost(10);
3778 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3779 interface(MEMORY_INTER) %{
3780 base(0xc); // R12
3781 index($reg);
3782 scale(0x3);
3783 disp($off);
3784 %}
3785 %}
3786
3787 // Indirect Memory Operand
3788 operand indirectNarrow(rRegN reg)
3789 %{
3790 predicate(Universe::narrow_oop_shift() == 0);
3791 constraint(ALLOC_IN_RC(ptr_reg));
3792 match(DecodeN reg);
3793
3794 format %{ "[$reg]" %}
3795 interface(MEMORY_INTER) %{
3796 base($reg);
3797 index(0x4);
3798 scale(0x0);
3799 disp(0x0);
3800 %}
3801 %}
3802
3803 // Indirect Memory Plus Short Offset Operand
3804 operand indOffset8Narrow(rRegN reg, immL8 off)
3805 %{
3806 predicate(Universe::narrow_oop_shift() == 0);
3807 constraint(ALLOC_IN_RC(ptr_reg));
3808 match(AddP (DecodeN reg) off);
3809
3810 format %{ "[$reg + $off (8-bit)]" %}
3811 interface(MEMORY_INTER) %{
3812 base($reg);
3813 index(0x4);
3814 scale(0x0);
3815 disp($off);
3816 %}
3817 %}
3818
3819 // Indirect Memory Plus Long Offset Operand
3820 operand indOffset32Narrow(rRegN reg, immL32 off)
3821 %{
3822 predicate(Universe::narrow_oop_shift() == 0);
3823 constraint(ALLOC_IN_RC(ptr_reg));
3824 match(AddP (DecodeN reg) off);
3825
3826 format %{ "[$reg + $off (32-bit)]" %}
3827 interface(MEMORY_INTER) %{
3828 base($reg);
3829 index(0x4);
3830 scale(0x0);
3831 disp($off);
3832 %}
3833 %}
3834
3835 // Indirect Memory Plus Index Register Plus Offset Operand
3836 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3837 %{
3838 predicate(Universe::narrow_oop_shift() == 0);
3839 constraint(ALLOC_IN_RC(ptr_reg));
3840 match(AddP (AddP (DecodeN reg) lreg) off);
3841
3842 op_cost(10);
3843 format %{"[$reg + $off + $lreg]" %}
3844 interface(MEMORY_INTER) %{
3845 base($reg);
3846 index($lreg);
3847 scale(0x0);
3848 disp($off);
3849 %}
3850 %}
3851
3852 // Indirect Memory Plus Index Register Plus Offset Operand
3853 operand indIndexNarrow(rRegN reg, rRegL lreg)
3854 %{
3855 predicate(Universe::narrow_oop_shift() == 0);
3856 constraint(ALLOC_IN_RC(ptr_reg));
3857 match(AddP (DecodeN reg) lreg);
3858
3859 op_cost(10);
3860 format %{"[$reg + $lreg]" %}
3861 interface(MEMORY_INTER) %{
3862 base($reg);
3863 index($lreg);
3864 scale(0x0);
3865 disp(0x0);
3866 %}
3867 %}
3868
3869 // Indirect Memory Times Scale Plus Index Register
3870 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3871 %{
3872 predicate(Universe::narrow_oop_shift() == 0);
3873 constraint(ALLOC_IN_RC(ptr_reg));
3874 match(AddP (DecodeN reg) (LShiftL lreg scale));
3875
3876 op_cost(10);
3877 format %{"[$reg + $lreg << $scale]" %}
3878 interface(MEMORY_INTER) %{
3879 base($reg);
3880 index($lreg);
3881 scale($scale);
3882 disp(0x0);
3883 %}
3884 %}
3885
3886 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3887 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3888 %{
3889 predicate(Universe::narrow_oop_shift() == 0);
3890 constraint(ALLOC_IN_RC(ptr_reg));
3891 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3892
3893 op_cost(10);
3894 format %{"[$reg + $off + $lreg << $scale]" %}
3895 interface(MEMORY_INTER) %{
3896 base($reg);
3897 index($lreg);
3898 scale($scale);
3899 disp($off);
3900 %}
3901 %}
3902
3903 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
3904 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
3905 %{
3906 constraint(ALLOC_IN_RC(ptr_reg));
3907 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3908 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
3909
3910 op_cost(10);
3911 format %{"[$reg + $off + $idx]" %}
3912 interface(MEMORY_INTER) %{
3913 base($reg);
3914 index($idx);
3915 scale(0x0);
3916 disp($off);
3917 %}
3918 %}
3919
3920 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3921 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3922 %{
3923 constraint(ALLOC_IN_RC(ptr_reg));
3924 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3925 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
3926
3927 op_cost(10);
3928 format %{"[$reg + $off + $idx << $scale]" %}
3929 interface(MEMORY_INTER) %{
3930 base($reg);
3931 index($idx);
3932 scale($scale);
3933 disp($off);
3934 %}
3935 %}
3936
3937 //----------Special Memory Operands--------------------------------------------
3938 // Stack Slot Operand - This operand is used for loading and storing temporary
3939 // values on the stack where a match requires a value to
3940 // flow through memory.
3941 operand stackSlotP(sRegP reg)
3942 %{
3943 constraint(ALLOC_IN_RC(stack_slots));
3944 // No match rule because this operand is only generated in matching
3945
3946 format %{ "[$reg]" %}
3947 interface(MEMORY_INTER) %{
3948 base(0x4); // RSP
3949 index(0x4); // No Index
3950 scale(0x0); // No Scale
3951 disp($reg); // Stack Offset
3952 %}
3953 %}
3954
3955 operand stackSlotI(sRegI reg)
3956 %{
3957 constraint(ALLOC_IN_RC(stack_slots));
3958 // No match rule because this operand is only generated in matching
3959
3960 format %{ "[$reg]" %}
3961 interface(MEMORY_INTER) %{
3962 base(0x4); // RSP
3963 index(0x4); // No Index
3964 scale(0x0); // No Scale
3965 disp($reg); // Stack Offset
3966 %}
3967 %}
3968
3969 operand stackSlotF(sRegF reg)
3970 %{
3971 constraint(ALLOC_IN_RC(stack_slots));
3972 // No match rule because this operand is only generated in matching
3973
3974 format %{ "[$reg]" %}
3975 interface(MEMORY_INTER) %{
3976 base(0x4); // RSP
3977 index(0x4); // No Index
3978 scale(0x0); // No Scale
3979 disp($reg); // Stack Offset
3980 %}
3981 %}
3982
3983 operand stackSlotD(sRegD reg)
3984 %{
3985 constraint(ALLOC_IN_RC(stack_slots));
3986 // No match rule because this operand is only generated in matching
3987
3988 format %{ "[$reg]" %}
3989 interface(MEMORY_INTER) %{
3990 base(0x4); // RSP
3991 index(0x4); // No Index
3992 scale(0x0); // No Scale
3993 disp($reg); // Stack Offset
3994 %}
3995 %}
3996 operand stackSlotL(sRegL reg)
3997 %{
3998 constraint(ALLOC_IN_RC(stack_slots));
3999 // No match rule because this operand is only generated in matching
4000
4001 format %{ "[$reg]" %}
4002 interface(MEMORY_INTER) %{
4003 base(0x4); // RSP
4004 index(0x4); // No Index
4005 scale(0x0); // No Scale
4006 disp($reg); // Stack Offset
4007 %}
4008 %}
4009
4010 //----------Conditional Branch Operands----------------------------------------
4011 // Comparison Op - This is the operation of the comparison, and is limited to
4012 // the following set of codes:
4013 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4014 //
4015 // Other attributes of the comparison, such as unsignedness, are specified
4016 // by the comparison instruction that sets a condition code flags register.
4017 // That result is represented by a flags operand whose subtype is appropriate
4018 // to the unsignedness (etc.) of the comparison.
4019 //
4020 // Later, the instruction which matches both the Comparison Op (a Bool) and
4021 // the flags (produced by the Cmp) specifies the coding of the comparison op
4022 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4023
4024 // Comparision Code
4025 operand cmpOp()
4026 %{
4027 match(Bool);
4028
4029 format %{ "" %}
4030 interface(COND_INTER) %{
4031 equal(0x4, "e");
4032 not_equal(0x5, "ne");
4033 less(0xC, "l");
4034 greater_equal(0xD, "ge");
4035 less_equal(0xE, "le");
4036 greater(0xF, "g");
4037 overflow(0x0, "o");
4038 no_overflow(0x1, "no");
4039 %}
4040 %}
4041
4042 // Comparison Code, unsigned compare. Used by FP also, with
4043 // C2 (unordered) turned into GT or LT already. The other bits
4044 // C0 and C3 are turned into Carry & Zero flags.
4045 operand cmpOpU()
4046 %{
4047 match(Bool);
4048
4049 format %{ "" %}
4050 interface(COND_INTER) %{
4051 equal(0x4, "e");
4052 not_equal(0x5, "ne");
4053 less(0x2, "b");
4054 greater_equal(0x3, "nb");
4055 less_equal(0x6, "be");
4056 greater(0x7, "nbe");
4057 overflow(0x0, "o");
4058 no_overflow(0x1, "no");
4059 %}
4060 %}
4061
4062
4063 // Floating comparisons that don't require any fixup for the unordered case
4064 operand cmpOpUCF() %{
4065 match(Bool);
4066 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4067 n->as_Bool()->_test._test == BoolTest::ge ||
4068 n->as_Bool()->_test._test == BoolTest::le ||
4069 n->as_Bool()->_test._test == BoolTest::gt);
4070 format %{ "" %}
4071 interface(COND_INTER) %{
4072 equal(0x4, "e");
4073 not_equal(0x5, "ne");
4074 less(0x2, "b");
4075 greater_equal(0x3, "nb");
4076 less_equal(0x6, "be");
4077 greater(0x7, "nbe");
4078 overflow(0x0, "o");
4079 no_overflow(0x1, "no");
4080 %}
4081 %}
4082
4083
4084 // Floating comparisons that can be fixed up with extra conditional jumps
4085 operand cmpOpUCF2() %{
4086 match(Bool);
4087 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4088 n->as_Bool()->_test._test == BoolTest::eq);
4089 format %{ "" %}
4090 interface(COND_INTER) %{
4091 equal(0x4, "e");
4092 not_equal(0x5, "ne");
4093 less(0x2, "b");
4094 greater_equal(0x3, "nb");
4095 less_equal(0x6, "be");
4096 greater(0x7, "nbe");
4097 overflow(0x0, "o");
4098 no_overflow(0x1, "no");
4099 %}
4100 %}
4101
4102
4103 //----------OPERAND CLASSES----------------------------------------------------
4104 // Operand Classes are groups of operands that are used as to simplify
4105 // instruction definitions by not requiring the AD writer to specify separate
4106 // instructions for every form of operand when the instruction accepts
4107 // multiple operand types with the same basic encoding and format. The classic
4108 // case of this is memory operands.
4109
4110 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4111 indIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4112 indCompressedOopOffset,
4113 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4114 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4115 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4116
4117 //----------PIPELINE-----------------------------------------------------------
4118 // Rules which define the behavior of the target architectures pipeline.
4119 pipeline %{
4120
4121 //----------ATTRIBUTES---------------------------------------------------------
4122 attributes %{
4123 variable_size_instructions; // Fixed size instructions
4124 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4125 instruction_unit_size = 1; // An instruction is 1 bytes long
4126 instruction_fetch_unit_size = 16; // The processor fetches one line
4127 instruction_fetch_units = 1; // of 16 bytes
4128
4129 // List of nop instructions
4130 nops( MachNop );
4131 %}
4132
4133 //----------RESOURCES----------------------------------------------------------
4134 // Resources are the functional units available to the machine
4135
4136 // Generic P2/P3 pipeline
4137 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4138 // 3 instructions decoded per cycle.
4139 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4140 // 3 ALU op, only ALU0 handles mul instructions.
4141 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4142 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4143 BR, FPU,
4144 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4145
4146 //----------PIPELINE DESCRIPTION-----------------------------------------------
4147 // Pipeline Description specifies the stages in the machine's pipeline
4148
4149 // Generic P2/P3 pipeline
4150 pipe_desc(S0, S1, S2, S3, S4, S5);
4151
4152 //----------PIPELINE CLASSES---------------------------------------------------
4153 // Pipeline Classes describe the stages in which input and output are
4154 // referenced by the hardware pipeline.
4155
4156 // Naming convention: ialu or fpu
4157 // Then: _reg
4158 // Then: _reg if there is a 2nd register
4159 // Then: _long if it's a pair of instructions implementing a long
4160 // Then: _fat if it requires the big decoder
4161 // Or: _mem if it requires the big decoder and a memory unit.
4162
4163 // Integer ALU reg operation
4164 pipe_class ialu_reg(rRegI dst)
4165 %{
4166 single_instruction;
4167 dst : S4(write);
4168 dst : S3(read);
4169 DECODE : S0; // any decoder
4170 ALU : S3; // any alu
4171 %}
4172
4173 // Long ALU reg operation
4174 pipe_class ialu_reg_long(rRegL dst)
4175 %{
4176 instruction_count(2);
4177 dst : S4(write);
4178 dst : S3(read);
4179 DECODE : S0(2); // any 2 decoders
4180 ALU : S3(2); // both alus
4181 %}
4182
4183 // Integer ALU reg operation using big decoder
4184 pipe_class ialu_reg_fat(rRegI dst)
4185 %{
4186 single_instruction;
4187 dst : S4(write);
4188 dst : S3(read);
4189 D0 : S0; // big decoder only
4190 ALU : S3; // any alu
4191 %}
4192
4193 // Long ALU reg operation using big decoder
4194 pipe_class ialu_reg_long_fat(rRegL dst)
4195 %{
4196 instruction_count(2);
4197 dst : S4(write);
4198 dst : S3(read);
4199 D0 : S0(2); // big decoder only; twice
4200 ALU : S3(2); // any 2 alus
4201 %}
4202
4203 // Integer ALU reg-reg operation
4204 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4205 %{
4206 single_instruction;
4207 dst : S4(write);
4208 src : S3(read);
4209 DECODE : S0; // any decoder
4210 ALU : S3; // any alu
4211 %}
4212
4213 // Long ALU reg-reg operation
4214 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4215 %{
4216 instruction_count(2);
4217 dst : S4(write);
4218 src : S3(read);
4219 DECODE : S0(2); // any 2 decoders
4220 ALU : S3(2); // both alus
4221 %}
4222
4223 // Integer ALU reg-reg operation
4224 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4225 %{
4226 single_instruction;
4227 dst : S4(write);
4228 src : S3(read);
4229 D0 : S0; // big decoder only
4230 ALU : S3; // any alu
4231 %}
4232
4233 // Long ALU reg-reg operation
4234 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4235 %{
4236 instruction_count(2);
4237 dst : S4(write);
4238 src : S3(read);
4239 D0 : S0(2); // big decoder only; twice
4240 ALU : S3(2); // both alus
4241 %}
4242
4243 // Integer ALU reg-mem operation
4244 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4245 %{
4246 single_instruction;
4247 dst : S5(write);
4248 mem : S3(read);
4249 D0 : S0; // big decoder only
4250 ALU : S4; // any alu
4251 MEM : S3; // any mem
4252 %}
4253
4254 // Integer mem operation (prefetch)
4255 pipe_class ialu_mem(memory mem)
4256 %{
4257 single_instruction;
4258 mem : S3(read);
4259 D0 : S0; // big decoder only
4260 MEM : S3; // any mem
4261 %}
4262
4263 // Integer Store to Memory
4264 pipe_class ialu_mem_reg(memory mem, rRegI src)
4265 %{
4266 single_instruction;
4267 mem : S3(read);
4268 src : S5(read);
4269 D0 : S0; // big decoder only
4270 ALU : S4; // any alu
4271 MEM : S3;
4272 %}
4273
4274 // // Long Store to Memory
4275 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4276 // %{
4277 // instruction_count(2);
4278 // mem : S3(read);
4279 // src : S5(read);
4280 // D0 : S0(2); // big decoder only; twice
4281 // ALU : S4(2); // any 2 alus
4282 // MEM : S3(2); // Both mems
4283 // %}
4284
4285 // Integer Store to Memory
4286 pipe_class ialu_mem_imm(memory mem)
4287 %{
4288 single_instruction;
4289 mem : S3(read);
4290 D0 : S0; // big decoder only
4291 ALU : S4; // any alu
4292 MEM : S3;
4293 %}
4294
4295 // Integer ALU0 reg-reg operation
4296 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4297 %{
4298 single_instruction;
4299 dst : S4(write);
4300 src : S3(read);
4301 D0 : S0; // Big decoder only
4302 ALU0 : S3; // only alu0
4303 %}
4304
4305 // Integer ALU0 reg-mem operation
4306 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4307 %{
4308 single_instruction;
4309 dst : S5(write);
4310 mem : S3(read);
4311 D0 : S0; // big decoder only
4312 ALU0 : S4; // ALU0 only
4313 MEM : S3; // any mem
4314 %}
4315
4316 // Integer ALU reg-reg operation
4317 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4318 %{
4319 single_instruction;
4320 cr : S4(write);
4321 src1 : S3(read);
4322 src2 : S3(read);
4323 DECODE : S0; // any decoder
4324 ALU : S3; // any alu
4325 %}
4326
4327 // Integer ALU reg-imm operation
4328 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4329 %{
4330 single_instruction;
4331 cr : S4(write);
4332 src1 : S3(read);
4333 DECODE : S0; // any decoder
4334 ALU : S3; // any alu
4335 %}
4336
4337 // Integer ALU reg-mem operation
4338 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4339 %{
4340 single_instruction;
4341 cr : S4(write);
4342 src1 : S3(read);
4343 src2 : S3(read);
4344 D0 : S0; // big decoder only
4345 ALU : S4; // any alu
4346 MEM : S3;
4347 %}
4348
4349 // Conditional move reg-reg
4350 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4351 %{
4352 instruction_count(4);
4353 y : S4(read);
4354 q : S3(read);
4355 p : S3(read);
4356 DECODE : S0(4); // any decoder
4357 %}
4358
4359 // Conditional move reg-reg
4360 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4361 %{
4362 single_instruction;
4363 dst : S4(write);
4364 src : S3(read);
4365 cr : S3(read);
4366 DECODE : S0; // any decoder
4367 %}
4368
4369 // Conditional move reg-mem
4370 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4371 %{
4372 single_instruction;
4373 dst : S4(write);
4374 src : S3(read);
4375 cr : S3(read);
4376 DECODE : S0; // any decoder
4377 MEM : S3;
4378 %}
4379
4380 // Conditional move reg-reg long
4381 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4382 %{
4383 single_instruction;
4384 dst : S4(write);
4385 src : S3(read);
4386 cr : S3(read);
4387 DECODE : S0(2); // any 2 decoders
4388 %}
4389
4390 // XXX
4391 // // Conditional move double reg-reg
4392 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4393 // %{
4394 // single_instruction;
4395 // dst : S4(write);
4396 // src : S3(read);
4397 // cr : S3(read);
4398 // DECODE : S0; // any decoder
4399 // %}
4400
4401 // Float reg-reg operation
4402 pipe_class fpu_reg(regD dst)
4403 %{
4404 instruction_count(2);
4405 dst : S3(read);
4406 DECODE : S0(2); // any 2 decoders
4407 FPU : S3;
4408 %}
4409
4410 // Float reg-reg operation
4411 pipe_class fpu_reg_reg(regD dst, regD src)
4412 %{
4413 instruction_count(2);
4414 dst : S4(write);
4415 src : S3(read);
4416 DECODE : S0(2); // any 2 decoders
4417 FPU : S3;
4418 %}
4419
4420 // Float reg-reg operation
4421 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4422 %{
4423 instruction_count(3);
4424 dst : S4(write);
4425 src1 : S3(read);
4426 src2 : S3(read);
4427 DECODE : S0(3); // any 3 decoders
4428 FPU : S3(2);
4429 %}
4430
4431 // Float reg-reg operation
4432 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4433 %{
4434 instruction_count(4);
4435 dst : S4(write);
4436 src1 : S3(read);
4437 src2 : S3(read);
4438 src3 : S3(read);
4439 DECODE : S0(4); // any 3 decoders
4440 FPU : S3(2);
4441 %}
4442
4443 // Float reg-reg operation
4444 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4445 %{
4446 instruction_count(4);
4447 dst : S4(write);
4448 src1 : S3(read);
4449 src2 : S3(read);
4450 src3 : S3(read);
4451 DECODE : S1(3); // any 3 decoders
4452 D0 : S0; // Big decoder only
4453 FPU : S3(2);
4454 MEM : S3;
4455 %}
4456
4457 // Float reg-mem operation
4458 pipe_class fpu_reg_mem(regD dst, memory mem)
4459 %{
4460 instruction_count(2);
4461 dst : S5(write);
4462 mem : S3(read);
4463 D0 : S0; // big decoder only
4464 DECODE : S1; // any decoder for FPU POP
4465 FPU : S4;
4466 MEM : S3; // any mem
4467 %}
4468
4469 // Float reg-mem operation
4470 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4471 %{
4472 instruction_count(3);
4473 dst : S5(write);
4474 src1 : S3(read);
4475 mem : S3(read);
4476 D0 : S0; // big decoder only
4477 DECODE : S1(2); // any decoder for FPU POP
4478 FPU : S4;
4479 MEM : S3; // any mem
4480 %}
4481
4482 // Float mem-reg operation
4483 pipe_class fpu_mem_reg(memory mem, regD src)
4484 %{
4485 instruction_count(2);
4486 src : S5(read);
4487 mem : S3(read);
4488 DECODE : S0; // any decoder for FPU PUSH
4489 D0 : S1; // big decoder only
4490 FPU : S4;
4491 MEM : S3; // any mem
4492 %}
4493
4494 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4495 %{
4496 instruction_count(3);
4497 src1 : S3(read);
4498 src2 : S3(read);
4499 mem : S3(read);
4500 DECODE : S0(2); // any decoder for FPU PUSH
4501 D0 : S1; // big decoder only
4502 FPU : S4;
4503 MEM : S3; // any mem
4504 %}
4505
4506 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4507 %{
4508 instruction_count(3);
4509 src1 : S3(read);
4510 src2 : S3(read);
4511 mem : S4(read);
4512 DECODE : S0; // any decoder for FPU PUSH
4513 D0 : S0(2); // big decoder only
4514 FPU : S4;
4515 MEM : S3(2); // any mem
4516 %}
4517
4518 pipe_class fpu_mem_mem(memory dst, memory src1)
4519 %{
4520 instruction_count(2);
4521 src1 : S3(read);
4522 dst : S4(read);
4523 D0 : S0(2); // big decoder only
4524 MEM : S3(2); // any mem
4525 %}
4526
4527 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4528 %{
4529 instruction_count(3);
4530 src1 : S3(read);
4531 src2 : S3(read);
4532 dst : S4(read);
4533 D0 : S0(3); // big decoder only
4534 FPU : S4;
4535 MEM : S3(3); // any mem
4536 %}
4537
4538 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4539 %{
4540 instruction_count(3);
4541 src1 : S4(read);
4542 mem : S4(read);
4543 DECODE : S0; // any decoder for FPU PUSH
4544 D0 : S0(2); // big decoder only
4545 FPU : S4;
4546 MEM : S3(2); // any mem
4547 %}
4548
4549 // Float load constant
4550 pipe_class fpu_reg_con(regD dst)
4551 %{
4552 instruction_count(2);
4553 dst : S5(write);
4554 D0 : S0; // big decoder only for the load
4555 DECODE : S1; // any decoder for FPU POP
4556 FPU : S4;
4557 MEM : S3; // any mem
4558 %}
4559
4560 // Float load constant
4561 pipe_class fpu_reg_reg_con(regD dst, regD src)
4562 %{
4563 instruction_count(3);
4564 dst : S5(write);
4565 src : S3(read);
4566 D0 : S0; // big decoder only for the load
4567 DECODE : S1(2); // any decoder for FPU POP
4568 FPU : S4;
4569 MEM : S3; // any mem
4570 %}
4571
4572 // UnConditional branch
4573 pipe_class pipe_jmp(label labl)
4574 %{
4575 single_instruction;
4576 BR : S3;
4577 %}
4578
4579 // Conditional branch
4580 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4581 %{
4582 single_instruction;
4583 cr : S1(read);
4584 BR : S3;
4585 %}
4586
4587 // Allocation idiom
4588 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4589 %{
4590 instruction_count(1); force_serialization;
4591 fixed_latency(6);
4592 heap_ptr : S3(read);
4593 DECODE : S0(3);
4594 D0 : S2;
4595 MEM : S3;
4596 ALU : S3(2);
4597 dst : S5(write);
4598 BR : S5;
4599 %}
4600
4601 // Generic big/slow expanded idiom
4602 pipe_class pipe_slow()
4603 %{
4604 instruction_count(10); multiple_bundles; force_serialization;
4605 fixed_latency(100);
4606 D0 : S0(2);
4607 MEM : S3(2);
4608 %}
4609
4610 // The real do-nothing guy
4611 pipe_class empty()
4612 %{
4613 instruction_count(0);
4614 %}
4615
4616 // Define the class for the Nop node
4617 define
4618 %{
4619 MachNop = empty;
4620 %}
4621
4622 %}
4623
4624 //----------INSTRUCTIONS-------------------------------------------------------
4625 //
4626 // match -- States which machine-independent subtree may be replaced
4627 // by this instruction.
4628 // ins_cost -- The estimated cost of this instruction is used by instruction
4629 // selection to identify a minimum cost tree of machine
4630 // instructions that matches a tree of machine-independent
4631 // instructions.
4632 // format -- A string providing the disassembly for this instruction.
4633 // The value of an instruction's operand may be inserted
4634 // by referring to it with a '$' prefix.
4635 // opcode -- Three instruction opcodes may be provided. These are referred
4636 // to within an encode class as $primary, $secondary, and $tertiary
4637 // rrspectively. The primary opcode is commonly used to
4638 // indicate the type of machine instruction, while secondary
4639 // and tertiary are often used for prefix options or addressing
4640 // modes.
4641 // ins_encode -- A list of encode classes with parameters. The encode class
4642 // name must have been defined in an 'enc_class' specification
4643 // in the encode section of the architecture description.
4644
4645
4646 //----------Load/Store/Move Instructions---------------------------------------
4647 //----------Load Instructions--------------------------------------------------
4648
4649 // Load Byte (8 bit signed)
4650 instruct loadB(rRegI dst, memory mem)
4651 %{
4652 match(Set dst (LoadB mem));
4653
4654 ins_cost(125);
4655 format %{ "movsbl $dst, $mem\t# byte" %}
4656
4657 ins_encode %{
4658 __ movsbl($dst$$Register, $mem$$Address);
4659 %}
4660
4661 ins_pipe(ialu_reg_mem);
4662 %}
4663
4664 // Load Byte (8 bit signed) into Long Register
4665 instruct loadB2L(rRegL dst, memory mem)
4666 %{
4667 match(Set dst (ConvI2L (LoadB mem)));
4668
4669 ins_cost(125);
4670 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4671
4672 ins_encode %{
4673 __ movsbq($dst$$Register, $mem$$Address);
4674 %}
4675
4676 ins_pipe(ialu_reg_mem);
4677 %}
4678
4679 // Load Unsigned Byte (8 bit UNsigned)
4680 instruct loadUB(rRegI dst, memory mem)
4681 %{
4682 match(Set dst (LoadUB mem));
4683
4684 ins_cost(125);
4685 format %{ "movzbl $dst, $mem\t# ubyte" %}
4686
4687 ins_encode %{
4688 __ movzbl($dst$$Register, $mem$$Address);
4689 %}
4690
4691 ins_pipe(ialu_reg_mem);
4692 %}
4693
4694 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4695 instruct loadUB2L(rRegL dst, memory mem)
4696 %{
4697 match(Set dst (ConvI2L (LoadUB mem)));
4698
4699 ins_cost(125);
4700 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4701
4702 ins_encode %{
4703 __ movzbq($dst$$Register, $mem$$Address);
4704 %}
4705
4706 ins_pipe(ialu_reg_mem);
4707 %}
4708
4709 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register
4710 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{
4711 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4712 effect(KILL cr);
4713
4714 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t"
4715 "andl $dst, $mask" %}
4716 ins_encode %{
4717 Register Rdst = $dst$$Register;
4718 __ movzbq(Rdst, $mem$$Address);
4719 __ andl(Rdst, $mask$$constant);
4720 %}
4721 ins_pipe(ialu_reg_mem);
4722 %}
4723
4724 // Load Short (16 bit signed)
4725 instruct loadS(rRegI dst, memory mem)
4726 %{
4727 match(Set dst (LoadS mem));
4728
4729 ins_cost(125);
4730 format %{ "movswl $dst, $mem\t# short" %}
4731
4732 ins_encode %{
4733 __ movswl($dst$$Register, $mem$$Address);
4734 %}
4735
4736 ins_pipe(ialu_reg_mem);
4737 %}
4738
4739 // Load Short (16 bit signed) to Byte (8 bit signed)
4740 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4741 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4742
4743 ins_cost(125);
4744 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4745 ins_encode %{
4746 __ movsbl($dst$$Register, $mem$$Address);
4747 %}
4748 ins_pipe(ialu_reg_mem);
4749 %}
4750
4751 // Load Short (16 bit signed) into Long Register
4752 instruct loadS2L(rRegL dst, memory mem)
4753 %{
4754 match(Set dst (ConvI2L (LoadS mem)));
4755
4756 ins_cost(125);
4757 format %{ "movswq $dst, $mem\t# short -> long" %}
4758
4759 ins_encode %{
4760 __ movswq($dst$$Register, $mem$$Address);
4761 %}
4762
4763 ins_pipe(ialu_reg_mem);
4764 %}
4765
4766 // Load Unsigned Short/Char (16 bit UNsigned)
4767 instruct loadUS(rRegI dst, memory mem)
4768 %{
4769 match(Set dst (LoadUS mem));
4770
4771 ins_cost(125);
4772 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4773
4774 ins_encode %{
4775 __ movzwl($dst$$Register, $mem$$Address);
4776 %}
4777
4778 ins_pipe(ialu_reg_mem);
4779 %}
4780
4781 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4782 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4783 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4784
4785 ins_cost(125);
4786 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4787 ins_encode %{
4788 __ movsbl($dst$$Register, $mem$$Address);
4789 %}
4790 ins_pipe(ialu_reg_mem);
4791 %}
4792
4793 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4794 instruct loadUS2L(rRegL dst, memory mem)
4795 %{
4796 match(Set dst (ConvI2L (LoadUS mem)));
4797
4798 ins_cost(125);
4799 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4800
4801 ins_encode %{
4802 __ movzwq($dst$$Register, $mem$$Address);
4803 %}
4804
4805 ins_pipe(ialu_reg_mem);
4806 %}
4807
4808 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4809 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4810 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4811
4812 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4813 ins_encode %{
4814 __ movzbq($dst$$Register, $mem$$Address);
4815 %}
4816 ins_pipe(ialu_reg_mem);
4817 %}
4818
4819 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register
4820 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{
4821 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4822 effect(KILL cr);
4823
4824 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t"
4825 "andl $dst, $mask" %}
4826 ins_encode %{
4827 Register Rdst = $dst$$Register;
4828 __ movzwq(Rdst, $mem$$Address);
4829 __ andl(Rdst, $mask$$constant);
4830 %}
4831 ins_pipe(ialu_reg_mem);
4832 %}
4833
4834 // Load Integer
4835 instruct loadI(rRegI dst, memory mem)
4836 %{
4837 match(Set dst (LoadI mem));
4838
4839 ins_cost(125);
4840 format %{ "movl $dst, $mem\t# int" %}
4841
4842 ins_encode %{
4843 __ movl($dst$$Register, $mem$$Address);
4844 %}
4845
4846 ins_pipe(ialu_reg_mem);
4847 %}
4848
4849 // Load Integer (32 bit signed) to Byte (8 bit signed)
4850 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4851 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4852
4853 ins_cost(125);
4854 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4855 ins_encode %{
4856 __ movsbl($dst$$Register, $mem$$Address);
4857 %}
4858 ins_pipe(ialu_reg_mem);
4859 %}
4860
4861 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4862 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4863 match(Set dst (AndI (LoadI mem) mask));
4864
4865 ins_cost(125);
4866 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4867 ins_encode %{
4868 __ movzbl($dst$$Register, $mem$$Address);
4869 %}
4870 ins_pipe(ialu_reg_mem);
4871 %}
4872
4873 // Load Integer (32 bit signed) to Short (16 bit signed)
4874 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4875 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4876
4877 ins_cost(125);
4878 format %{ "movswl $dst, $mem\t# int -> short" %}
4879 ins_encode %{
4880 __ movswl($dst$$Register, $mem$$Address);
4881 %}
4882 ins_pipe(ialu_reg_mem);
4883 %}
4884
4885 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4886 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4887 match(Set dst (AndI (LoadI mem) mask));
4888
4889 ins_cost(125);
4890 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4891 ins_encode %{
4892 __ movzwl($dst$$Register, $mem$$Address);
4893 %}
4894 ins_pipe(ialu_reg_mem);
4895 %}
4896
4897 // Load Integer into Long Register
4898 instruct loadI2L(rRegL dst, memory mem)
4899 %{
4900 match(Set dst (ConvI2L (LoadI mem)));
4901
4902 ins_cost(125);
4903 format %{ "movslq $dst, $mem\t# int -> long" %}
4904
4905 ins_encode %{
4906 __ movslq($dst$$Register, $mem$$Address);
4907 %}
4908
4909 ins_pipe(ialu_reg_mem);
4910 %}
4911
4912 // Load Integer with mask 0xFF into Long Register
4913 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4914 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4915
4916 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
4917 ins_encode %{
4918 __ movzbq($dst$$Register, $mem$$Address);
4919 %}
4920 ins_pipe(ialu_reg_mem);
4921 %}
4922
4923 // Load Integer with mask 0xFFFF into Long Register
4924 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
4925 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4926
4927 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
4928 ins_encode %{
4929 __ movzwq($dst$$Register, $mem$$Address);
4930 %}
4931 ins_pipe(ialu_reg_mem);
4932 %}
4933
4934 // Load Integer with a 31-bit mask into Long Register
4935 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
4936 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4937 effect(KILL cr);
4938
4939 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
4940 "andl $dst, $mask" %}
4941 ins_encode %{
4942 Register Rdst = $dst$$Register;
4943 __ movl(Rdst, $mem$$Address);
4944 __ andl(Rdst, $mask$$constant);
4945 %}
4946 ins_pipe(ialu_reg_mem);
4947 %}
4948
4949 // Load Unsigned Integer into Long Register
4950 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
4951 %{
4952 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4953
4954 ins_cost(125);
4955 format %{ "movl $dst, $mem\t# uint -> long" %}
4956
4957 ins_encode %{
4958 __ movl($dst$$Register, $mem$$Address);
4959 %}
4960
4961 ins_pipe(ialu_reg_mem);
4962 %}
4963
4964 // Load Long
4965 instruct loadL(rRegL dst, memory mem)
4966 %{
4967 match(Set dst (LoadL mem));
4968
4969 ins_cost(125);
4970 format %{ "movq $dst, $mem\t# long" %}
4971
4972 ins_encode %{
4973 __ movq($dst$$Register, $mem$$Address);
4974 %}
4975
4976 ins_pipe(ialu_reg_mem); // XXX
4977 %}
4978
4979 // Load Range
4980 instruct loadRange(rRegI dst, memory mem)
4981 %{
4982 match(Set dst (LoadRange mem));
4983
4984 ins_cost(125); // XXX
4985 format %{ "movl $dst, $mem\t# range" %}
4986 opcode(0x8B);
4987 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
4988 ins_pipe(ialu_reg_mem);
4989 %}
4990
4991 // Load Pointer
4992 instruct loadP(rRegP dst, memory mem)
4993 %{
4994 match(Set dst (LoadP mem));
4995
4996 ins_cost(125); // XXX
4997 format %{ "movq $dst, $mem\t# ptr" %}
4998 opcode(0x8B);
4999 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5000 ins_pipe(ialu_reg_mem); // XXX
5001 %}
5002
5003 // Load Compressed Pointer
5004 instruct loadN(rRegN dst, memory mem)
5005 %{
5006 match(Set dst (LoadN mem));
5007
5008 ins_cost(125); // XXX
5009 format %{ "movl $dst, $mem\t# compressed ptr" %}
5010 ins_encode %{
5011 __ movl($dst$$Register, $mem$$Address);
5012 %}
5013 ins_pipe(ialu_reg_mem); // XXX
5014 %}
5015
5016
5017 // Load Klass Pointer
5018 instruct loadKlass(rRegP dst, memory mem)
5019 %{
5020 match(Set dst (LoadKlass mem));
5021
5022 ins_cost(125); // XXX
5023 format %{ "movq $dst, $mem\t# class" %}
5024 opcode(0x8B);
5025 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5026 ins_pipe(ialu_reg_mem); // XXX
5027 %}
5028
5029 // Load narrow Klass Pointer
5030 instruct loadNKlass(rRegN dst, memory mem)
5031 %{
5032 match(Set dst (LoadNKlass mem));
5033
5034 ins_cost(125); // XXX
5035 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5036 ins_encode %{
5037 __ movl($dst$$Register, $mem$$Address);
5038 %}
5039 ins_pipe(ialu_reg_mem); // XXX
5040 %}
5041
5042 // Load Float
5043 instruct loadF(regF dst, memory mem)
5044 %{
5045 match(Set dst (LoadF mem));
5046
5047 ins_cost(145); // XXX
5048 format %{ "movss $dst, $mem\t# float" %}
5049 ins_encode %{
5050 __ movflt($dst$$XMMRegister, $mem$$Address);
5051 %}
5052 ins_pipe(pipe_slow); // XXX
5053 %}
5054
5055 // Load Double
5056 instruct loadD_partial(regD dst, memory mem)
5057 %{
5058 predicate(!UseXmmLoadAndClearUpper);
5059 match(Set dst (LoadD mem));
5060
5061 ins_cost(145); // XXX
5062 format %{ "movlpd $dst, $mem\t# double" %}
5063 ins_encode %{
5064 __ movdbl($dst$$XMMRegister, $mem$$Address);
5065 %}
5066 ins_pipe(pipe_slow); // XXX
5067 %}
5068
5069 instruct loadD(regD dst, memory mem)
5070 %{
5071 predicate(UseXmmLoadAndClearUpper);
5072 match(Set dst (LoadD mem));
5073
5074 ins_cost(145); // XXX
5075 format %{ "movsd $dst, $mem\t# double" %}
5076 ins_encode %{
5077 __ movdbl($dst$$XMMRegister, $mem$$Address);
5078 %}
5079 ins_pipe(pipe_slow); // XXX
5080 %}
5081
5082 // Load Effective Address
5083 instruct leaP8(rRegP dst, indOffset8 mem)
5084 %{
5085 match(Set dst mem);
5086
5087 ins_cost(110); // XXX
5088 format %{ "leaq $dst, $mem\t# ptr 8" %}
5089 opcode(0x8D);
5090 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5091 ins_pipe(ialu_reg_reg_fat);
5092 %}
5093
5094 instruct leaP32(rRegP dst, indOffset32 mem)
5095 %{
5096 match(Set dst mem);
5097
5098 ins_cost(110);
5099 format %{ "leaq $dst, $mem\t# ptr 32" %}
5100 opcode(0x8D);
5101 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5102 ins_pipe(ialu_reg_reg_fat);
5103 %}
5104
5105 // instruct leaPIdx(rRegP dst, indIndex mem)
5106 // %{
5107 // match(Set dst mem);
5108
5109 // ins_cost(110);
5110 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5111 // opcode(0x8D);
5112 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5113 // ins_pipe(ialu_reg_reg_fat);
5114 // %}
5115
5116 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5117 %{
5118 match(Set dst mem);
5119
5120 ins_cost(110);
5121 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5122 opcode(0x8D);
5123 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5124 ins_pipe(ialu_reg_reg_fat);
5125 %}
5126
5127 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5128 %{
5129 match(Set dst mem);
5130
5131 ins_cost(110);
5132 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5133 opcode(0x8D);
5134 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5135 ins_pipe(ialu_reg_reg_fat);
5136 %}
5137
5138 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5139 %{
5140 match(Set dst mem);
5141
5142 ins_cost(110);
5143 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5144 opcode(0x8D);
5145 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5146 ins_pipe(ialu_reg_reg_fat);
5147 %}
5148
5149 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5150 %{
5151 match(Set dst mem);
5152
5153 ins_cost(110);
5154 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5155 opcode(0x8D);
5156 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5157 ins_pipe(ialu_reg_reg_fat);
5158 %}
5159
5160 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5161 %{
5162 match(Set dst mem);
5163
5164 ins_cost(110);
5165 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5166 opcode(0x8D);
5167 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5168 ins_pipe(ialu_reg_reg_fat);
5169 %}
5170
5171 // Load Effective Address which uses Narrow (32-bits) oop
5172 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5173 %{
5174 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5175 match(Set dst mem);
5176
5177 ins_cost(110);
5178 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5179 opcode(0x8D);
5180 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5181 ins_pipe(ialu_reg_reg_fat);
5182 %}
5183
5184 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5185 %{
5186 predicate(Universe::narrow_oop_shift() == 0);
5187 match(Set dst mem);
5188
5189 ins_cost(110); // XXX
5190 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5191 opcode(0x8D);
5192 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5193 ins_pipe(ialu_reg_reg_fat);
5194 %}
5195
5196 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5197 %{
5198 predicate(Universe::narrow_oop_shift() == 0);
5199 match(Set dst mem);
5200
5201 ins_cost(110);
5202 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5203 opcode(0x8D);
5204 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5205 ins_pipe(ialu_reg_reg_fat);
5206 %}
5207
5208 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5209 %{
5210 predicate(Universe::narrow_oop_shift() == 0);
5211 match(Set dst mem);
5212
5213 ins_cost(110);
5214 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5215 opcode(0x8D);
5216 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5217 ins_pipe(ialu_reg_reg_fat);
5218 %}
5219
5220 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5221 %{
5222 predicate(Universe::narrow_oop_shift() == 0);
5223 match(Set dst mem);
5224
5225 ins_cost(110);
5226 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5227 opcode(0x8D);
5228 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5229 ins_pipe(ialu_reg_reg_fat);
5230 %}
5231
5232 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5233 %{
5234 predicate(Universe::narrow_oop_shift() == 0);
5235 match(Set dst mem);
5236
5237 ins_cost(110);
5238 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5239 opcode(0x8D);
5240 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5241 ins_pipe(ialu_reg_reg_fat);
5242 %}
5243
5244 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5245 %{
5246 predicate(Universe::narrow_oop_shift() == 0);
5247 match(Set dst mem);
5248
5249 ins_cost(110);
5250 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5251 opcode(0x8D);
5252 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5253 ins_pipe(ialu_reg_reg_fat);
5254 %}
5255
5256 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5257 %{
5258 predicate(Universe::narrow_oop_shift() == 0);
5259 match(Set dst mem);
5260
5261 ins_cost(110);
5262 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5263 opcode(0x8D);
5264 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5265 ins_pipe(ialu_reg_reg_fat);
5266 %}
5267
5268 instruct loadConI(rRegI dst, immI src)
5269 %{
5270 match(Set dst src);
5271
5272 format %{ "movl $dst, $src\t# int" %}
5273 ins_encode(load_immI(dst, src));
5274 ins_pipe(ialu_reg_fat); // XXX
5275 %}
5276
5277 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5278 %{
5279 match(Set dst src);
5280 effect(KILL cr);
5281
5282 ins_cost(50);
5283 format %{ "xorl $dst, $dst\t# int" %}
5284 opcode(0x33); /* + rd */
5285 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5286 ins_pipe(ialu_reg);
5287 %}
5288
5289 instruct loadConL(rRegL dst, immL src)
5290 %{
5291 match(Set dst src);
5292
5293 ins_cost(150);
5294 format %{ "movq $dst, $src\t# long" %}
5295 ins_encode(load_immL(dst, src));
5296 ins_pipe(ialu_reg);
5297 %}
5298
5299 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5300 %{
5301 match(Set dst src);
5302 effect(KILL cr);
5303
5304 ins_cost(50);
5305 format %{ "xorl $dst, $dst\t# long" %}
5306 opcode(0x33); /* + rd */
5307 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5308 ins_pipe(ialu_reg); // XXX
5309 %}
5310
5311 instruct loadConUL32(rRegL dst, immUL32 src)
5312 %{
5313 match(Set dst src);
5314
5315 ins_cost(60);
5316 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5317 ins_encode(load_immUL32(dst, src));
5318 ins_pipe(ialu_reg);
5319 %}
5320
5321 instruct loadConL32(rRegL dst, immL32 src)
5322 %{
5323 match(Set dst src);
5324
5325 ins_cost(70);
5326 format %{ "movq $dst, $src\t# long (32-bit)" %}
5327 ins_encode(load_immL32(dst, src));
5328 ins_pipe(ialu_reg);
5329 %}
5330
5331 instruct loadConP(rRegP dst, immP con) %{
5332 match(Set dst con);
5333
5334 format %{ "movq $dst, $con\t# ptr" %}
5335 ins_encode(load_immP(dst, con));
5336 ins_pipe(ialu_reg_fat); // XXX
5337 %}
5338
5339 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5340 %{
5341 match(Set dst src);
5342 effect(KILL cr);
5343
5344 ins_cost(50);
5345 format %{ "xorl $dst, $dst\t# ptr" %}
5346 opcode(0x33); /* + rd */
5347 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5348 ins_pipe(ialu_reg);
5349 %}
5350
5351 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5352 %{
5353 match(Set dst src);
5354 effect(KILL cr);
5355
5356 ins_cost(60);
5357 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5358 ins_encode(load_immP31(dst, src));
5359 ins_pipe(ialu_reg);
5360 %}
5361
5362 instruct loadConF(regF dst, immF con) %{
5363 match(Set dst con);
5364 ins_cost(125);
5365 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5366 ins_encode %{
5367 __ movflt($dst$$XMMRegister, $constantaddress($con));
5368 %}
5369 ins_pipe(pipe_slow);
5370 %}
5371
5372 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5373 match(Set dst src);
5374 effect(KILL cr);
5375 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5376 ins_encode %{
5377 __ xorq($dst$$Register, $dst$$Register);
5378 %}
5379 ins_pipe(ialu_reg);
5380 %}
5381
5382 instruct loadConN(rRegN dst, immN src) %{
5383 match(Set dst src);
5384
5385 ins_cost(125);
5386 format %{ "movl $dst, $src\t# compressed ptr" %}
5387 ins_encode %{
5388 address con = (address)$src$$constant;
5389 if (con == NULL) {
5390 ShouldNotReachHere();
5391 } else {
5392 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5393 }
5394 %}
5395 ins_pipe(ialu_reg_fat); // XXX
5396 %}
5397
5398 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5399 match(Set dst src);
5400
5401 ins_cost(125);
5402 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5403 ins_encode %{
5404 address con = (address)$src$$constant;
5405 if (con == NULL) {
5406 ShouldNotReachHere();
5407 } else {
5408 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5409 }
5410 %}
5411 ins_pipe(ialu_reg_fat); // XXX
5412 %}
5413
5414 instruct loadConF0(regF dst, immF0 src)
5415 %{
5416 match(Set dst src);
5417 ins_cost(100);
5418
5419 format %{ "xorps $dst, $dst\t# float 0.0" %}
5420 ins_encode %{
5421 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5422 %}
5423 ins_pipe(pipe_slow);
5424 %}
5425
5426 // Use the same format since predicate() can not be used here.
5427 instruct loadConD(regD dst, immD con) %{
5428 match(Set dst con);
5429 ins_cost(125);
5430 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5431 ins_encode %{
5432 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5433 %}
5434 ins_pipe(pipe_slow);
5435 %}
5436
5437 instruct loadConD0(regD dst, immD0 src)
5438 %{
5439 match(Set dst src);
5440 ins_cost(100);
5441
5442 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5443 ins_encode %{
5444 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5445 %}
5446 ins_pipe(pipe_slow);
5447 %}
5448
5449 instruct loadSSI(rRegI dst, stackSlotI src)
5450 %{
5451 match(Set dst src);
5452
5453 ins_cost(125);
5454 format %{ "movl $dst, $src\t# int stk" %}
5455 opcode(0x8B);
5456 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5457 ins_pipe(ialu_reg_mem);
5458 %}
5459
5460 instruct loadSSL(rRegL dst, stackSlotL src)
5461 %{
5462 match(Set dst src);
5463
5464 ins_cost(125);
5465 format %{ "movq $dst, $src\t# long stk" %}
5466 opcode(0x8B);
5467 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5468 ins_pipe(ialu_reg_mem);
5469 %}
5470
5471 instruct loadSSP(rRegP dst, stackSlotP src)
5472 %{
5473 match(Set dst src);
5474
5475 ins_cost(125);
5476 format %{ "movq $dst, $src\t# ptr stk" %}
5477 opcode(0x8B);
5478 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5479 ins_pipe(ialu_reg_mem);
5480 %}
5481
5482 instruct loadSSF(regF dst, stackSlotF src)
5483 %{
5484 match(Set dst src);
5485
5486 ins_cost(125);
5487 format %{ "movss $dst, $src\t# float stk" %}
5488 ins_encode %{
5489 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5490 %}
5491 ins_pipe(pipe_slow); // XXX
5492 %}
5493
5494 // Use the same format since predicate() can not be used here.
5495 instruct loadSSD(regD dst, stackSlotD src)
5496 %{
5497 match(Set dst src);
5498
5499 ins_cost(125);
5500 format %{ "movsd $dst, $src\t# double stk" %}
5501 ins_encode %{
5502 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5503 %}
5504 ins_pipe(pipe_slow); // XXX
5505 %}
5506
5507 // Prefetch instructions for allocation.
5508 // Must be safe to execute with invalid address (cannot fault).
5509
5510 instruct prefetchAlloc( memory mem ) %{
5511 predicate(AllocatePrefetchInstr==3);
5512 match(PrefetchAllocation mem);
5513 ins_cost(125);
5514
5515 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5516 ins_encode %{
5517 __ prefetchw($mem$$Address);
5518 %}
5519 ins_pipe(ialu_mem);
5520 %}
5521
5522 instruct prefetchAllocNTA( memory mem ) %{
5523 predicate(AllocatePrefetchInstr==0);
5524 match(PrefetchAllocation mem);
5525 ins_cost(125);
5526
5527 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5528 ins_encode %{
5529 __ prefetchnta($mem$$Address);
5530 %}
5531 ins_pipe(ialu_mem);
5532 %}
5533
5534 instruct prefetchAllocT0( memory mem ) %{
5535 predicate(AllocatePrefetchInstr==1);
5536 match(PrefetchAllocation mem);
5537 ins_cost(125);
5538
5539 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5540 ins_encode %{
5541 __ prefetcht0($mem$$Address);
5542 %}
5543 ins_pipe(ialu_mem);
5544 %}
5545
5546 instruct prefetchAllocT2( memory mem ) %{
5547 predicate(AllocatePrefetchInstr==2);
5548 match(PrefetchAllocation mem);
5549 ins_cost(125);
5550
5551 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5552 ins_encode %{
5553 __ prefetcht2($mem$$Address);
5554 %}
5555 ins_pipe(ialu_mem);
5556 %}
5557
5558 //----------Store Instructions-------------------------------------------------
5559
5560 // Store Byte
5561 instruct storeB(memory mem, rRegI src)
5562 %{
5563 match(Set mem (StoreB mem src));
5564
5565 ins_cost(125); // XXX
5566 format %{ "movb $mem, $src\t# byte" %}
5567 opcode(0x88);
5568 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5569 ins_pipe(ialu_mem_reg);
5570 %}
5571
5572 // Store Char/Short
5573 instruct storeC(memory mem, rRegI src)
5574 %{
5575 match(Set mem (StoreC mem src));
5576
5577 ins_cost(125); // XXX
5578 format %{ "movw $mem, $src\t# char/short" %}
5579 opcode(0x89);
5580 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5581 ins_pipe(ialu_mem_reg);
5582 %}
5583
5584 // Store Integer
5585 instruct storeI(memory mem, rRegI src)
5586 %{
5587 match(Set mem (StoreI mem src));
5588
5589 ins_cost(125); // XXX
5590 format %{ "movl $mem, $src\t# int" %}
5591 opcode(0x89);
5592 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5593 ins_pipe(ialu_mem_reg);
5594 %}
5595
5596 // Store Long
5597 instruct storeL(memory mem, rRegL src)
5598 %{
5599 match(Set mem (StoreL mem src));
5600
5601 ins_cost(125); // XXX
5602 format %{ "movq $mem, $src\t# long" %}
5603 opcode(0x89);
5604 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5605 ins_pipe(ialu_mem_reg); // XXX
5606 %}
5607
5608 // Store Pointer
5609 instruct storeP(memory mem, any_RegP src)
5610 %{
5611 match(Set mem (StoreP mem src));
5612
5613 ins_cost(125); // XXX
5614 format %{ "movq $mem, $src\t# ptr" %}
5615 opcode(0x89);
5616 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5617 ins_pipe(ialu_mem_reg);
5618 %}
5619
5620 instruct storeImmP0(memory mem, immP0 zero)
5621 %{
5622 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5623 match(Set mem (StoreP mem zero));
5624
5625 ins_cost(125); // XXX
5626 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5627 ins_encode %{
5628 __ movq($mem$$Address, r12);
5629 %}
5630 ins_pipe(ialu_mem_reg);
5631 %}
5632
5633 // Store NULL Pointer, mark word, or other simple pointer constant.
5634 instruct storeImmP(memory mem, immP31 src)
5635 %{
5636 match(Set mem (StoreP mem src));
5637
5638 ins_cost(150); // XXX
5639 format %{ "movq $mem, $src\t# ptr" %}
5640 opcode(0xC7); /* C7 /0 */
5641 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5642 ins_pipe(ialu_mem_imm);
5643 %}
5644
5645 // Store Compressed Pointer
5646 instruct storeN(memory mem, rRegN src)
5647 %{
5648 match(Set mem (StoreN mem src));
5649
5650 ins_cost(125); // XXX
5651 format %{ "movl $mem, $src\t# compressed ptr" %}
5652 ins_encode %{
5653 __ movl($mem$$Address, $src$$Register);
5654 %}
5655 ins_pipe(ialu_mem_reg);
5656 %}
5657
5658 instruct storeNKlass(memory mem, rRegN src)
5659 %{
5660 match(Set mem (StoreNKlass mem src));
5661
5662 ins_cost(125); // XXX
5663 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5664 ins_encode %{
5665 __ movl($mem$$Address, $src$$Register);
5666 %}
5667 ins_pipe(ialu_mem_reg);
5668 %}
5669
5670 instruct storeImmN0(memory mem, immN0 zero)
5671 %{
5672 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
5673 match(Set mem (StoreN mem zero));
5674
5675 ins_cost(125); // XXX
5676 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5677 ins_encode %{
5678 __ movl($mem$$Address, r12);
5679 %}
5680 ins_pipe(ialu_mem_reg);
5681 %}
5682
5683 instruct storeImmN(memory mem, immN src)
5684 %{
5685 match(Set mem (StoreN mem src));
5686
5687 ins_cost(150); // XXX
5688 format %{ "movl $mem, $src\t# compressed ptr" %}
5689 ins_encode %{
5690 address con = (address)$src$$constant;
5691 if (con == NULL) {
5692 __ movl($mem$$Address, (int32_t)0);
5693 } else {
5694 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5695 }
5696 %}
5697 ins_pipe(ialu_mem_imm);
5698 %}
5699
5700 instruct storeImmNKlass(memory mem, immNKlass src)
5701 %{
5702 match(Set mem (StoreNKlass mem src));
5703
5704 ins_cost(150); // XXX
5705 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5706 ins_encode %{
5707 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5708 %}
5709 ins_pipe(ialu_mem_imm);
5710 %}
5711
5712 // Store Integer Immediate
5713 instruct storeImmI0(memory mem, immI0 zero)
5714 %{
5715 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5716 match(Set mem (StoreI mem zero));
5717
5718 ins_cost(125); // XXX
5719 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5720 ins_encode %{
5721 __ movl($mem$$Address, r12);
5722 %}
5723 ins_pipe(ialu_mem_reg);
5724 %}
5725
5726 instruct storeImmI(memory mem, immI src)
5727 %{
5728 match(Set mem (StoreI mem src));
5729
5730 ins_cost(150);
5731 format %{ "movl $mem, $src\t# int" %}
5732 opcode(0xC7); /* C7 /0 */
5733 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5734 ins_pipe(ialu_mem_imm);
5735 %}
5736
5737 // Store Long Immediate
5738 instruct storeImmL0(memory mem, immL0 zero)
5739 %{
5740 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5741 match(Set mem (StoreL mem zero));
5742
5743 ins_cost(125); // XXX
5744 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5745 ins_encode %{
5746 __ movq($mem$$Address, r12);
5747 %}
5748 ins_pipe(ialu_mem_reg);
5749 %}
5750
5751 instruct storeImmL(memory mem, immL32 src)
5752 %{
5753 match(Set mem (StoreL mem src));
5754
5755 ins_cost(150);
5756 format %{ "movq $mem, $src\t# long" %}
5757 opcode(0xC7); /* C7 /0 */
5758 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5759 ins_pipe(ialu_mem_imm);
5760 %}
5761
5762 // Store Short/Char Immediate
5763 instruct storeImmC0(memory mem, immI0 zero)
5764 %{
5765 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5766 match(Set mem (StoreC mem zero));
5767
5768 ins_cost(125); // XXX
5769 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5770 ins_encode %{
5771 __ movw($mem$$Address, r12);
5772 %}
5773 ins_pipe(ialu_mem_reg);
5774 %}
5775
5776 instruct storeImmI16(memory mem, immI16 src)
5777 %{
5778 predicate(UseStoreImmI16);
5779 match(Set mem (StoreC mem src));
5780
5781 ins_cost(150);
5782 format %{ "movw $mem, $src\t# short/char" %}
5783 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
5784 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
5785 ins_pipe(ialu_mem_imm);
5786 %}
5787
5788 // Store Byte Immediate
5789 instruct storeImmB0(memory mem, immI0 zero)
5790 %{
5791 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5792 match(Set mem (StoreB mem zero));
5793
5794 ins_cost(125); // XXX
5795 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5796 ins_encode %{
5797 __ movb($mem$$Address, r12);
5798 %}
5799 ins_pipe(ialu_mem_reg);
5800 %}
5801
5802 instruct storeImmB(memory mem, immI8 src)
5803 %{
5804 match(Set mem (StoreB mem src));
5805
5806 ins_cost(150); // XXX
5807 format %{ "movb $mem, $src\t# byte" %}
5808 opcode(0xC6); /* C6 /0 */
5809 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5810 ins_pipe(ialu_mem_imm);
5811 %}
5812
5813 // Store CMS card-mark Immediate
5814 instruct storeImmCM0_reg(memory mem, immI0 zero)
5815 %{
5816 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5817 match(Set mem (StoreCM mem zero));
5818
5819 ins_cost(125); // XXX
5820 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5821 ins_encode %{
5822 __ movb($mem$$Address, r12);
5823 %}
5824 ins_pipe(ialu_mem_reg);
5825 %}
5826
5827 instruct storeImmCM0(memory mem, immI0 src)
5828 %{
5829 match(Set mem (StoreCM mem src));
5830
5831 ins_cost(150); // XXX
5832 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5833 opcode(0xC6); /* C6 /0 */
5834 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5835 ins_pipe(ialu_mem_imm);
5836 %}
5837
5838 // Store Float
5839 instruct storeF(memory mem, regF src)
5840 %{
5841 match(Set mem (StoreF mem src));
5842
5843 ins_cost(95); // XXX
5844 format %{ "movss $mem, $src\t# float" %}
5845 ins_encode %{
5846 __ movflt($mem$$Address, $src$$XMMRegister);
5847 %}
5848 ins_pipe(pipe_slow); // XXX
5849 %}
5850
5851 // Store immediate Float value (it is faster than store from XMM register)
5852 instruct storeF0(memory mem, immF0 zero)
5853 %{
5854 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5855 match(Set mem (StoreF mem zero));
5856
5857 ins_cost(25); // XXX
5858 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5859 ins_encode %{
5860 __ movl($mem$$Address, r12);
5861 %}
5862 ins_pipe(ialu_mem_reg);
5863 %}
5864
5865 instruct storeF_imm(memory mem, immF src)
5866 %{
5867 match(Set mem (StoreF mem src));
5868
5869 ins_cost(50);
5870 format %{ "movl $mem, $src\t# float" %}
5871 opcode(0xC7); /* C7 /0 */
5872 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5873 ins_pipe(ialu_mem_imm);
5874 %}
5875
5876 // Store Double
5877 instruct storeD(memory mem, regD src)
5878 %{
5879 match(Set mem (StoreD mem src));
5880
5881 ins_cost(95); // XXX
5882 format %{ "movsd $mem, $src\t# double" %}
5883 ins_encode %{
5884 __ movdbl($mem$$Address, $src$$XMMRegister);
5885 %}
5886 ins_pipe(pipe_slow); // XXX
5887 %}
5888
5889 // Store immediate double 0.0 (it is faster than store from XMM register)
5890 instruct storeD0_imm(memory mem, immD0 src)
5891 %{
5892 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
5893 match(Set mem (StoreD mem src));
5894
5895 ins_cost(50);
5896 format %{ "movq $mem, $src\t# double 0." %}
5897 opcode(0xC7); /* C7 /0 */
5898 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5899 ins_pipe(ialu_mem_imm);
5900 %}
5901
5902 instruct storeD0(memory mem, immD0 zero)
5903 %{
5904 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5905 match(Set mem (StoreD mem zero));
5906
5907 ins_cost(25); // XXX
5908 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
5909 ins_encode %{
5910 __ movq($mem$$Address, r12);
5911 %}
5912 ins_pipe(ialu_mem_reg);
5913 %}
5914
5915 instruct storeSSI(stackSlotI dst, rRegI src)
5916 %{
5917 match(Set dst src);
5918
5919 ins_cost(100);
5920 format %{ "movl $dst, $src\t# int stk" %}
5921 opcode(0x89);
5922 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
5923 ins_pipe( ialu_mem_reg );
5924 %}
5925
5926 instruct storeSSL(stackSlotL dst, rRegL src)
5927 %{
5928 match(Set dst src);
5929
5930 ins_cost(100);
5931 format %{ "movq $dst, $src\t# long stk" %}
5932 opcode(0x89);
5933 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
5934 ins_pipe(ialu_mem_reg);
5935 %}
5936
5937 instruct storeSSP(stackSlotP dst, rRegP src)
5938 %{
5939 match(Set dst src);
5940
5941 ins_cost(100);
5942 format %{ "movq $dst, $src\t# ptr stk" %}
5943 opcode(0x89);
5944 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
5945 ins_pipe(ialu_mem_reg);
5946 %}
5947
5948 instruct storeSSF(stackSlotF dst, regF src)
5949 %{
5950 match(Set dst src);
5951
5952 ins_cost(95); // XXX
5953 format %{ "movss $dst, $src\t# float stk" %}
5954 ins_encode %{
5955 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
5956 %}
5957 ins_pipe(pipe_slow); // XXX
5958 %}
5959
5960 instruct storeSSD(stackSlotD dst, regD src)
5961 %{
5962 match(Set dst src);
5963
5964 ins_cost(95); // XXX
5965 format %{ "movsd $dst, $src\t# double stk" %}
5966 ins_encode %{
5967 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
5968 %}
5969 ins_pipe(pipe_slow); // XXX
5970 %}
5971
5972 //----------BSWAP Instructions-------------------------------------------------
5973 instruct bytes_reverse_int(rRegI dst) %{
5974 match(Set dst (ReverseBytesI dst));
5975
5976 format %{ "bswapl $dst" %}
5977 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
5978 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
5979 ins_pipe( ialu_reg );
5980 %}
5981
5982 instruct bytes_reverse_long(rRegL dst) %{
5983 match(Set dst (ReverseBytesL dst));
5984
5985 format %{ "bswapq $dst" %}
5986 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
5987 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
5988 ins_pipe( ialu_reg);
5989 %}
5990
5991 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
5992 match(Set dst (ReverseBytesUS dst));
5993 effect(KILL cr);
5994
5995 format %{ "bswapl $dst\n\t"
5996 "shrl $dst,16\n\t" %}
5997 ins_encode %{
5998 __ bswapl($dst$$Register);
5999 __ shrl($dst$$Register, 16);
6000 %}
6001 ins_pipe( ialu_reg );
6002 %}
6003
6004 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6005 match(Set dst (ReverseBytesS dst));
6006 effect(KILL cr);
6007
6008 format %{ "bswapl $dst\n\t"
6009 "sar $dst,16\n\t" %}
6010 ins_encode %{
6011 __ bswapl($dst$$Register);
6012 __ sarl($dst$$Register, 16);
6013 %}
6014 ins_pipe( ialu_reg );
6015 %}
6016
6017 //---------- Zeros Count Instructions ------------------------------------------
6018
6019 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6020 predicate(UseCountLeadingZerosInstruction);
6021 match(Set dst (CountLeadingZerosI src));
6022 effect(KILL cr);
6023
6024 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6025 ins_encode %{
6026 __ lzcntl($dst$$Register, $src$$Register);
6027 %}
6028 ins_pipe(ialu_reg);
6029 %}
6030
6031 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6032 predicate(!UseCountLeadingZerosInstruction);
6033 match(Set dst (CountLeadingZerosI src));
6034 effect(KILL cr);
6035
6036 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6037 "jnz skip\n\t"
6038 "movl $dst, -1\n"
6039 "skip:\n\t"
6040 "negl $dst\n\t"
6041 "addl $dst, 31" %}
6042 ins_encode %{
6043 Register Rdst = $dst$$Register;
6044 Register Rsrc = $src$$Register;
6045 Label skip;
6046 __ bsrl(Rdst, Rsrc);
6047 __ jccb(Assembler::notZero, skip);
6048 __ movl(Rdst, -1);
6049 __ bind(skip);
6050 __ negl(Rdst);
6051 __ addl(Rdst, BitsPerInt - 1);
6052 %}
6053 ins_pipe(ialu_reg);
6054 %}
6055
6056 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6057 predicate(UseCountLeadingZerosInstruction);
6058 match(Set dst (CountLeadingZerosL src));
6059 effect(KILL cr);
6060
6061 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6062 ins_encode %{
6063 __ lzcntq($dst$$Register, $src$$Register);
6064 %}
6065 ins_pipe(ialu_reg);
6066 %}
6067
6068 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6069 predicate(!UseCountLeadingZerosInstruction);
6070 match(Set dst (CountLeadingZerosL src));
6071 effect(KILL cr);
6072
6073 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6074 "jnz skip\n\t"
6075 "movl $dst, -1\n"
6076 "skip:\n\t"
6077 "negl $dst\n\t"
6078 "addl $dst, 63" %}
6079 ins_encode %{
6080 Register Rdst = $dst$$Register;
6081 Register Rsrc = $src$$Register;
6082 Label skip;
6083 __ bsrq(Rdst, Rsrc);
6084 __ jccb(Assembler::notZero, skip);
6085 __ movl(Rdst, -1);
6086 __ bind(skip);
6087 __ negl(Rdst);
6088 __ addl(Rdst, BitsPerLong - 1);
6089 %}
6090 ins_pipe(ialu_reg);
6091 %}
6092
6093 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6094 predicate(UseCountTrailingZerosInstruction);
6095 match(Set dst (CountTrailingZerosI src));
6096 effect(KILL cr);
6097
6098 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6099 ins_encode %{
6100 __ tzcntl($dst$$Register, $src$$Register);
6101 %}
6102 ins_pipe(ialu_reg);
6103 %}
6104
6105 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6106 predicate(!UseCountTrailingZerosInstruction);
6107 match(Set dst (CountTrailingZerosI src));
6108 effect(KILL cr);
6109
6110 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6111 "jnz done\n\t"
6112 "movl $dst, 32\n"
6113 "done:" %}
6114 ins_encode %{
6115 Register Rdst = $dst$$Register;
6116 Label done;
6117 __ bsfl(Rdst, $src$$Register);
6118 __ jccb(Assembler::notZero, done);
6119 __ movl(Rdst, BitsPerInt);
6120 __ bind(done);
6121 %}
6122 ins_pipe(ialu_reg);
6123 %}
6124
6125 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6126 predicate(UseCountTrailingZerosInstruction);
6127 match(Set dst (CountTrailingZerosL src));
6128 effect(KILL cr);
6129
6130 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6131 ins_encode %{
6132 __ tzcntq($dst$$Register, $src$$Register);
6133 %}
6134 ins_pipe(ialu_reg);
6135 %}
6136
6137 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6138 predicate(!UseCountTrailingZerosInstruction);
6139 match(Set dst (CountTrailingZerosL src));
6140 effect(KILL cr);
6141
6142 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6143 "jnz done\n\t"
6144 "movl $dst, 64\n"
6145 "done:" %}
6146 ins_encode %{
6147 Register Rdst = $dst$$Register;
6148 Label done;
6149 __ bsfq(Rdst, $src$$Register);
6150 __ jccb(Assembler::notZero, done);
6151 __ movl(Rdst, BitsPerLong);
6152 __ bind(done);
6153 %}
6154 ins_pipe(ialu_reg);
6155 %}
6156
6157
6158 //---------- Population Count Instructions -------------------------------------
6159
6160 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6161 predicate(UsePopCountInstruction);
6162 match(Set dst (PopCountI src));
6163 effect(KILL cr);
6164
6165 format %{ "popcnt $dst, $src" %}
6166 ins_encode %{
6167 __ popcntl($dst$$Register, $src$$Register);
6168 %}
6169 ins_pipe(ialu_reg);
6170 %}
6171
6172 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6173 predicate(UsePopCountInstruction);
6174 match(Set dst (PopCountI (LoadI mem)));
6175 effect(KILL cr);
6176
6177 format %{ "popcnt $dst, $mem" %}
6178 ins_encode %{
6179 __ popcntl($dst$$Register, $mem$$Address);
6180 %}
6181 ins_pipe(ialu_reg);
6182 %}
6183
6184 // Note: Long.bitCount(long) returns an int.
6185 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6186 predicate(UsePopCountInstruction);
6187 match(Set dst (PopCountL src));
6188 effect(KILL cr);
6189
6190 format %{ "popcnt $dst, $src" %}
6191 ins_encode %{
6192 __ popcntq($dst$$Register, $src$$Register);
6193 %}
6194 ins_pipe(ialu_reg);
6195 %}
6196
6197 // Note: Long.bitCount(long) returns an int.
6198 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6199 predicate(UsePopCountInstruction);
6200 match(Set dst (PopCountL (LoadL mem)));
6201 effect(KILL cr);
6202
6203 format %{ "popcnt $dst, $mem" %}
6204 ins_encode %{
6205 __ popcntq($dst$$Register, $mem$$Address);
6206 %}
6207 ins_pipe(ialu_reg);
6208 %}
6209
6210
6211 //----------MemBar Instructions-----------------------------------------------
6212 // Memory barrier flavors
6213
6214 instruct membar_acquire()
6215 %{
6216 match(MemBarAcquire);
6217 match(LoadFence);
6218 ins_cost(0);
6219
6220 size(0);
6221 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6222 ins_encode();
6223 ins_pipe(empty);
6224 %}
6225
6226 instruct membar_acquire_lock()
6227 %{
6228 match(MemBarAcquireLock);
6229 ins_cost(0);
6230
6231 size(0);
6232 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6233 ins_encode();
6234 ins_pipe(empty);
6235 %}
6236
6237 instruct membar_release()
6238 %{
6239 match(MemBarRelease);
6240 match(StoreFence);
6241 ins_cost(0);
6242
6243 size(0);
6244 format %{ "MEMBAR-release ! (empty encoding)" %}
6245 ins_encode();
6246 ins_pipe(empty);
6247 %}
6248
6249 instruct membar_release_lock()
6250 %{
6251 match(MemBarReleaseLock);
6252 ins_cost(0);
6253
6254 size(0);
6255 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6256 ins_encode();
6257 ins_pipe(empty);
6258 %}
6259
6260 instruct membar_volatile(rFlagsReg cr) %{
6261 match(MemBarVolatile);
6262 effect(KILL cr);
6263 ins_cost(400);
6264
6265 format %{
6266 $$template
6267 if (os::is_MP()) {
6268 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6269 } else {
6270 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6271 }
6272 %}
6273 ins_encode %{
6274 __ membar(Assembler::StoreLoad);
6275 %}
6276 ins_pipe(pipe_slow);
6277 %}
6278
6279 instruct unnecessary_membar_volatile()
6280 %{
6281 match(MemBarVolatile);
6282 predicate(Matcher::post_store_load_barrier(n));
6283 ins_cost(0);
6284
6285 size(0);
6286 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6287 ins_encode();
6288 ins_pipe(empty);
6289 %}
6290
6291 instruct membar_storestore() %{
6292 match(MemBarStoreStore);
6293 ins_cost(0);
6294
6295 size(0);
6296 format %{ "MEMBAR-storestore (empty encoding)" %}
6297 ins_encode( );
6298 ins_pipe(empty);
6299 %}
6300
6301 //----------Move Instructions--------------------------------------------------
6302
6303 instruct castX2P(rRegP dst, rRegL src)
6304 %{
6305 match(Set dst (CastX2P src));
6306
6307 format %{ "movq $dst, $src\t# long->ptr" %}
6308 ins_encode %{
6309 if ($dst$$reg != $src$$reg) {
6310 __ movptr($dst$$Register, $src$$Register);
6311 }
6312 %}
6313 ins_pipe(ialu_reg_reg); // XXX
6314 %}
6315
6316 instruct castP2X(rRegL dst, rRegP src)
6317 %{
6318 match(Set dst (CastP2X src));
6319
6320 format %{ "movq $dst, $src\t# ptr -> long" %}
6321 ins_encode %{
6322 if ($dst$$reg != $src$$reg) {
6323 __ movptr($dst$$Register, $src$$Register);
6324 }
6325 %}
6326 ins_pipe(ialu_reg_reg); // XXX
6327 %}
6328
6329 // Convert oop into int for vectors alignment masking
6330 instruct convP2I(rRegI dst, rRegP src)
6331 %{
6332 match(Set dst (ConvL2I (CastP2X src)));
6333
6334 format %{ "movl $dst, $src\t# ptr -> int" %}
6335 ins_encode %{
6336 __ movl($dst$$Register, $src$$Register);
6337 %}
6338 ins_pipe(ialu_reg_reg); // XXX
6339 %}
6340
6341 // Convert compressed oop into int for vectors alignment masking
6342 // in case of 32bit oops (heap < 4Gb).
6343 instruct convN2I(rRegI dst, rRegN src)
6344 %{
6345 predicate(Universe::narrow_oop_shift() == 0);
6346 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6347
6348 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6349 ins_encode %{
6350 __ movl($dst$$Register, $src$$Register);
6351 %}
6352 ins_pipe(ialu_reg_reg); // XXX
6353 %}
6354
6355 // Convert oop pointer into compressed form
6356 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6357 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6358 match(Set dst (EncodeP src));
6359 effect(KILL cr);
6360 format %{ "encode_heap_oop $dst,$src" %}
6361 ins_encode %{
6362 Register s = $src$$Register;
6363 Register d = $dst$$Register;
6364 if (s != d) {
6365 __ movq(d, s);
6366 }
6367 __ encode_heap_oop(d);
6368 %}
6369 ins_pipe(ialu_reg_long);
6370 %}
6371
6372 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6373 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6374 match(Set dst (EncodeP src));
6375 effect(KILL cr);
6376 format %{ "encode_heap_oop_not_null $dst,$src" %}
6377 ins_encode %{
6378 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6379 %}
6380 ins_pipe(ialu_reg_long);
6381 %}
6382
6383 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6384 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6385 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6386 match(Set dst (DecodeN src));
6387 effect(KILL cr);
6388 format %{ "decode_heap_oop $dst,$src" %}
6389 ins_encode %{
6390 Register s = $src$$Register;
6391 Register d = $dst$$Register;
6392 if (s != d) {
6393 __ movq(d, s);
6394 }
6395 __ decode_heap_oop(d);
6396 %}
6397 ins_pipe(ialu_reg_long);
6398 %}
6399
6400 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6401 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6402 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6403 match(Set dst (DecodeN src));
6404 effect(KILL cr);
6405 format %{ "decode_heap_oop_not_null $dst,$src" %}
6406 ins_encode %{
6407 Register s = $src$$Register;
6408 Register d = $dst$$Register;
6409 if (s != d) {
6410 __ decode_heap_oop_not_null(d, s);
6411 } else {
6412 __ decode_heap_oop_not_null(d);
6413 }
6414 %}
6415 ins_pipe(ialu_reg_long);
6416 %}
6417
6418 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6419 match(Set dst (EncodePKlass src));
6420 effect(KILL cr);
6421 format %{ "encode_klass_not_null $dst,$src" %}
6422 ins_encode %{
6423 __ encode_klass_not_null($dst$$Register, $src$$Register);
6424 %}
6425 ins_pipe(ialu_reg_long);
6426 %}
6427
6428 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6429 match(Set dst (DecodeNKlass src));
6430 effect(KILL cr);
6431 format %{ "decode_klass_not_null $dst,$src" %}
6432 ins_encode %{
6433 Register s = $src$$Register;
6434 Register d = $dst$$Register;
6435 if (s != d) {
6436 __ decode_klass_not_null(d, s);
6437 } else {
6438 __ decode_klass_not_null(d);
6439 }
6440 %}
6441 ins_pipe(ialu_reg_long);
6442 %}
6443
6444
6445 //----------Conditional Move---------------------------------------------------
6446 // Jump
6447 // dummy instruction for generating temp registers
6448 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6449 match(Jump (LShiftL switch_val shift));
6450 ins_cost(350);
6451 predicate(false);
6452 effect(TEMP dest);
6453
6454 format %{ "leaq $dest, [$constantaddress]\n\t"
6455 "jmp [$dest + $switch_val << $shift]\n\t" %}
6456 ins_encode %{
6457 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6458 // to do that and the compiler is using that register as one it can allocate.
6459 // So we build it all by hand.
6460 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6461 // ArrayAddress dispatch(table, index);
6462 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6463 __ lea($dest$$Register, $constantaddress);
6464 __ jmp(dispatch);
6465 %}
6466 ins_pipe(pipe_jmp);
6467 %}
6468
6469 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6470 match(Jump (AddL (LShiftL switch_val shift) offset));
6471 ins_cost(350);
6472 effect(TEMP dest);
6473
6474 format %{ "leaq $dest, [$constantaddress]\n\t"
6475 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6476 ins_encode %{
6477 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6478 // to do that and the compiler is using that register as one it can allocate.
6479 // So we build it all by hand.
6480 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6481 // ArrayAddress dispatch(table, index);
6482 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6483 __ lea($dest$$Register, $constantaddress);
6484 __ jmp(dispatch);
6485 %}
6486 ins_pipe(pipe_jmp);
6487 %}
6488
6489 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6490 match(Jump switch_val);
6491 ins_cost(350);
6492 effect(TEMP dest);
6493
6494 format %{ "leaq $dest, [$constantaddress]\n\t"
6495 "jmp [$dest + $switch_val]\n\t" %}
6496 ins_encode %{
6497 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6498 // to do that and the compiler is using that register as one it can allocate.
6499 // So we build it all by hand.
6500 // Address index(noreg, switch_reg, Address::times_1);
6501 // ArrayAddress dispatch(table, index);
6502 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6503 __ lea($dest$$Register, $constantaddress);
6504 __ jmp(dispatch);
6505 %}
6506 ins_pipe(pipe_jmp);
6507 %}
6508
6509 // Conditional move
6510 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6511 %{
6512 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6513
6514 ins_cost(200); // XXX
6515 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6516 opcode(0x0F, 0x40);
6517 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6518 ins_pipe(pipe_cmov_reg);
6519 %}
6520
6521 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6522 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6523
6524 ins_cost(200); // XXX
6525 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6526 opcode(0x0F, 0x40);
6527 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6528 ins_pipe(pipe_cmov_reg);
6529 %}
6530
6531 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6532 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6533 ins_cost(200);
6534 expand %{
6535 cmovI_regU(cop, cr, dst, src);
6536 %}
6537 %}
6538
6539 // Conditional move
6540 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6541 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6542
6543 ins_cost(250); // XXX
6544 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6545 opcode(0x0F, 0x40);
6546 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6547 ins_pipe(pipe_cmov_mem);
6548 %}
6549
6550 // Conditional move
6551 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6552 %{
6553 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6554
6555 ins_cost(250); // XXX
6556 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6557 opcode(0x0F, 0x40);
6558 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6559 ins_pipe(pipe_cmov_mem);
6560 %}
6561
6562 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6563 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6564 ins_cost(250);
6565 expand %{
6566 cmovI_memU(cop, cr, dst, src);
6567 %}
6568 %}
6569
6570 // Conditional move
6571 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6572 %{
6573 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6574
6575 ins_cost(200); // XXX
6576 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6577 opcode(0x0F, 0x40);
6578 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6579 ins_pipe(pipe_cmov_reg);
6580 %}
6581
6582 // Conditional move
6583 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6584 %{
6585 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6586
6587 ins_cost(200); // XXX
6588 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6589 opcode(0x0F, 0x40);
6590 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6591 ins_pipe(pipe_cmov_reg);
6592 %}
6593
6594 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6595 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6596 ins_cost(200);
6597 expand %{
6598 cmovN_regU(cop, cr, dst, src);
6599 %}
6600 %}
6601
6602 // Conditional move
6603 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6604 %{
6605 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6606
6607 ins_cost(200); // XXX
6608 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6609 opcode(0x0F, 0x40);
6610 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6611 ins_pipe(pipe_cmov_reg); // XXX
6612 %}
6613
6614 // Conditional move
6615 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6616 %{
6617 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6618
6619 ins_cost(200); // XXX
6620 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6621 opcode(0x0F, 0x40);
6622 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6623 ins_pipe(pipe_cmov_reg); // XXX
6624 %}
6625
6626 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6627 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6628 ins_cost(200);
6629 expand %{
6630 cmovP_regU(cop, cr, dst, src);
6631 %}
6632 %}
6633
6634 // DISABLED: Requires the ADLC to emit a bottom_type call that
6635 // correctly meets the two pointer arguments; one is an incoming
6636 // register but the other is a memory operand. ALSO appears to
6637 // be buggy with implicit null checks.
6638 //
6639 //// Conditional move
6640 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6641 //%{
6642 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6643 // ins_cost(250);
6644 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6645 // opcode(0x0F,0x40);
6646 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6647 // ins_pipe( pipe_cmov_mem );
6648 //%}
6649 //
6650 //// Conditional move
6651 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6652 //%{
6653 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6654 // ins_cost(250);
6655 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6656 // opcode(0x0F,0x40);
6657 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6658 // ins_pipe( pipe_cmov_mem );
6659 //%}
6660
6661 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6662 %{
6663 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6664
6665 ins_cost(200); // XXX
6666 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6667 opcode(0x0F, 0x40);
6668 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6669 ins_pipe(pipe_cmov_reg); // XXX
6670 %}
6671
6672 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6673 %{
6674 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6675
6676 ins_cost(200); // XXX
6677 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6678 opcode(0x0F, 0x40);
6679 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6680 ins_pipe(pipe_cmov_mem); // XXX
6681 %}
6682
6683 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6684 %{
6685 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6686
6687 ins_cost(200); // XXX
6688 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6689 opcode(0x0F, 0x40);
6690 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6691 ins_pipe(pipe_cmov_reg); // XXX
6692 %}
6693
6694 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6695 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6696 ins_cost(200);
6697 expand %{
6698 cmovL_regU(cop, cr, dst, src);
6699 %}
6700 %}
6701
6702 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6703 %{
6704 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6705
6706 ins_cost(200); // XXX
6707 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6708 opcode(0x0F, 0x40);
6709 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6710 ins_pipe(pipe_cmov_mem); // XXX
6711 %}
6712
6713 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6714 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6715 ins_cost(200);
6716 expand %{
6717 cmovL_memU(cop, cr, dst, src);
6718 %}
6719 %}
6720
6721 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6722 %{
6723 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6724
6725 ins_cost(200); // XXX
6726 format %{ "jn$cop skip\t# signed cmove float\n\t"
6727 "movss $dst, $src\n"
6728 "skip:" %}
6729 ins_encode %{
6730 Label Lskip;
6731 // Invert sense of branch from sense of CMOV
6732 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6733 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6734 __ bind(Lskip);
6735 %}
6736 ins_pipe(pipe_slow);
6737 %}
6738
6739 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
6740 // %{
6741 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
6742
6743 // ins_cost(200); // XXX
6744 // format %{ "jn$cop skip\t# signed cmove float\n\t"
6745 // "movss $dst, $src\n"
6746 // "skip:" %}
6747 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
6748 // ins_pipe(pipe_slow);
6749 // %}
6750
6751 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6752 %{
6753 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6754
6755 ins_cost(200); // XXX
6756 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6757 "movss $dst, $src\n"
6758 "skip:" %}
6759 ins_encode %{
6760 Label Lskip;
6761 // Invert sense of branch from sense of CMOV
6762 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6763 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6764 __ bind(Lskip);
6765 %}
6766 ins_pipe(pipe_slow);
6767 %}
6768
6769 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6770 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6771 ins_cost(200);
6772 expand %{
6773 cmovF_regU(cop, cr, dst, src);
6774 %}
6775 %}
6776
6777 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6778 %{
6779 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6780
6781 ins_cost(200); // XXX
6782 format %{ "jn$cop skip\t# signed cmove double\n\t"
6783 "movsd $dst, $src\n"
6784 "skip:" %}
6785 ins_encode %{
6786 Label Lskip;
6787 // Invert sense of branch from sense of CMOV
6788 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6789 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6790 __ bind(Lskip);
6791 %}
6792 ins_pipe(pipe_slow);
6793 %}
6794
6795 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6796 %{
6797 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6798
6799 ins_cost(200); // XXX
6800 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6801 "movsd $dst, $src\n"
6802 "skip:" %}
6803 ins_encode %{
6804 Label Lskip;
6805 // Invert sense of branch from sense of CMOV
6806 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6807 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6808 __ bind(Lskip);
6809 %}
6810 ins_pipe(pipe_slow);
6811 %}
6812
6813 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6814 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6815 ins_cost(200);
6816 expand %{
6817 cmovD_regU(cop, cr, dst, src);
6818 %}
6819 %}
6820
6821 //----------Arithmetic Instructions--------------------------------------------
6822 //----------Addition Instructions----------------------------------------------
6823
6824 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6825 %{
6826 match(Set dst (AddI dst src));
6827 effect(KILL cr);
6828
6829 format %{ "addl $dst, $src\t# int" %}
6830 opcode(0x03);
6831 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6832 ins_pipe(ialu_reg_reg);
6833 %}
6834
6835 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6836 %{
6837 match(Set dst (AddI dst src));
6838 effect(KILL cr);
6839
6840 format %{ "addl $dst, $src\t# int" %}
6841 opcode(0x81, 0x00); /* /0 id */
6842 ins_encode(OpcSErm(dst, src), Con8or32(src));
6843 ins_pipe( ialu_reg );
6844 %}
6845
6846 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6847 %{
6848 match(Set dst (AddI dst (LoadI src)));
6849 effect(KILL cr);
6850
6851 ins_cost(125); // XXX
6852 format %{ "addl $dst, $src\t# int" %}
6853 opcode(0x03);
6854 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6855 ins_pipe(ialu_reg_mem);
6856 %}
6857
6858 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6859 %{
6860 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6861 effect(KILL cr);
6862
6863 ins_cost(150); // XXX
6864 format %{ "addl $dst, $src\t# int" %}
6865 opcode(0x01); /* Opcode 01 /r */
6866 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6867 ins_pipe(ialu_mem_reg);
6868 %}
6869
6870 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
6871 %{
6872 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6873 effect(KILL cr);
6874
6875 ins_cost(125); // XXX
6876 format %{ "addl $dst, $src\t# int" %}
6877 opcode(0x81); /* Opcode 81 /0 id */
6878 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
6879 ins_pipe(ialu_mem_imm);
6880 %}
6881
6882 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
6883 %{
6884 predicate(UseIncDec);
6885 match(Set dst (AddI dst src));
6886 effect(KILL cr);
6887
6888 format %{ "incl $dst\t# int" %}
6889 opcode(0xFF, 0x00); // FF /0
6890 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6891 ins_pipe(ialu_reg);
6892 %}
6893
6894 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
6895 %{
6896 predicate(UseIncDec);
6897 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6898 effect(KILL cr);
6899
6900 ins_cost(125); // XXX
6901 format %{ "incl $dst\t# int" %}
6902 opcode(0xFF); /* Opcode FF /0 */
6903 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
6904 ins_pipe(ialu_mem_imm);
6905 %}
6906
6907 // XXX why does that use AddI
6908 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
6909 %{
6910 predicate(UseIncDec);
6911 match(Set dst (AddI dst src));
6912 effect(KILL cr);
6913
6914 format %{ "decl $dst\t# int" %}
6915 opcode(0xFF, 0x01); // FF /1
6916 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6917 ins_pipe(ialu_reg);
6918 %}
6919
6920 // XXX why does that use AddI
6921 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
6922 %{
6923 predicate(UseIncDec);
6924 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6925 effect(KILL cr);
6926
6927 ins_cost(125); // XXX
6928 format %{ "decl $dst\t# int" %}
6929 opcode(0xFF); /* Opcode FF /1 */
6930 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
6931 ins_pipe(ialu_mem_imm);
6932 %}
6933
6934 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
6935 %{
6936 match(Set dst (AddI src0 src1));
6937
6938 ins_cost(110);
6939 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
6940 opcode(0x8D); /* 0x8D /r */
6941 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
6942 ins_pipe(ialu_reg_reg);
6943 %}
6944
6945 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
6946 %{
6947 match(Set dst (AddL dst src));
6948 effect(KILL cr);
6949
6950 format %{ "addq $dst, $src\t# long" %}
6951 opcode(0x03);
6952 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
6953 ins_pipe(ialu_reg_reg);
6954 %}
6955
6956 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
6957 %{
6958 match(Set dst (AddL dst src));
6959 effect(KILL cr);
6960
6961 format %{ "addq $dst, $src\t# long" %}
6962 opcode(0x81, 0x00); /* /0 id */
6963 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
6964 ins_pipe( ialu_reg );
6965 %}
6966
6967 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
6968 %{
6969 match(Set dst (AddL dst (LoadL src)));
6970 effect(KILL cr);
6971
6972 ins_cost(125); // XXX
6973 format %{ "addq $dst, $src\t# long" %}
6974 opcode(0x03);
6975 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6976 ins_pipe(ialu_reg_mem);
6977 %}
6978
6979 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
6980 %{
6981 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6982 effect(KILL cr);
6983
6984 ins_cost(150); // XXX
6985 format %{ "addq $dst, $src\t# long" %}
6986 opcode(0x01); /* Opcode 01 /r */
6987 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6988 ins_pipe(ialu_mem_reg);
6989 %}
6990
6991 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
6992 %{
6993 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6994 effect(KILL cr);
6995
6996 ins_cost(125); // XXX
6997 format %{ "addq $dst, $src\t# long" %}
6998 opcode(0x81); /* Opcode 81 /0 id */
6999 ins_encode(REX_mem_wide(dst),
7000 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7001 ins_pipe(ialu_mem_imm);
7002 %}
7003
7004 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7005 %{
7006 predicate(UseIncDec);
7007 match(Set dst (AddL dst src));
7008 effect(KILL cr);
7009
7010 format %{ "incq $dst\t# long" %}
7011 opcode(0xFF, 0x00); // FF /0
7012 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7013 ins_pipe(ialu_reg);
7014 %}
7015
7016 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7017 %{
7018 predicate(UseIncDec);
7019 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7020 effect(KILL cr);
7021
7022 ins_cost(125); // XXX
7023 format %{ "incq $dst\t# long" %}
7024 opcode(0xFF); /* Opcode FF /0 */
7025 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7026 ins_pipe(ialu_mem_imm);
7027 %}
7028
7029 // XXX why does that use AddL
7030 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7031 %{
7032 predicate(UseIncDec);
7033 match(Set dst (AddL dst src));
7034 effect(KILL cr);
7035
7036 format %{ "decq $dst\t# long" %}
7037 opcode(0xFF, 0x01); // FF /1
7038 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7039 ins_pipe(ialu_reg);
7040 %}
7041
7042 // XXX why does that use AddL
7043 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7044 %{
7045 predicate(UseIncDec);
7046 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7047 effect(KILL cr);
7048
7049 ins_cost(125); // XXX
7050 format %{ "decq $dst\t# long" %}
7051 opcode(0xFF); /* Opcode FF /1 */
7052 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7053 ins_pipe(ialu_mem_imm);
7054 %}
7055
7056 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7057 %{
7058 match(Set dst (AddL src0 src1));
7059
7060 ins_cost(110);
7061 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7062 opcode(0x8D); /* 0x8D /r */
7063 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7064 ins_pipe(ialu_reg_reg);
7065 %}
7066
7067 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7068 %{
7069 match(Set dst (AddP dst src));
7070 effect(KILL cr);
7071
7072 format %{ "addq $dst, $src\t# ptr" %}
7073 opcode(0x03);
7074 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7075 ins_pipe(ialu_reg_reg);
7076 %}
7077
7078 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7079 %{
7080 match(Set dst (AddP dst src));
7081 effect(KILL cr);
7082
7083 format %{ "addq $dst, $src\t# ptr" %}
7084 opcode(0x81, 0x00); /* /0 id */
7085 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7086 ins_pipe( ialu_reg );
7087 %}
7088
7089 // XXX addP mem ops ????
7090
7091 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7092 %{
7093 match(Set dst (AddP src0 src1));
7094
7095 ins_cost(110);
7096 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7097 opcode(0x8D); /* 0x8D /r */
7098 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7099 ins_pipe(ialu_reg_reg);
7100 %}
7101
7102 instruct checkCastPP(rRegP dst)
7103 %{
7104 match(Set dst (CheckCastPP dst));
7105
7106 size(0);
7107 format %{ "# checkcastPP of $dst" %}
7108 ins_encode(/* empty encoding */);
7109 ins_pipe(empty);
7110 %}
7111
7112 instruct castPP(rRegP dst)
7113 %{
7114 match(Set dst (CastPP dst));
7115
7116 size(0);
7117 format %{ "# castPP of $dst" %}
7118 ins_encode(/* empty encoding */);
7119 ins_pipe(empty);
7120 %}
7121
7122 instruct castII(rRegI dst)
7123 %{
7124 match(Set dst (CastII dst));
7125
7126 size(0);
7127 format %{ "# castII of $dst" %}
7128 ins_encode(/* empty encoding */);
7129 ins_cost(0);
7130 ins_pipe(empty);
7131 %}
7132
7133 // LoadP-locked same as a regular LoadP when used with compare-swap
7134 instruct loadPLocked(rRegP dst, memory mem)
7135 %{
7136 match(Set dst (LoadPLocked mem));
7137
7138 ins_cost(125); // XXX
7139 format %{ "movq $dst, $mem\t# ptr locked" %}
7140 opcode(0x8B);
7141 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7142 ins_pipe(ialu_reg_mem); // XXX
7143 %}
7144
7145 // Conditional-store of the updated heap-top.
7146 // Used during allocation of the shared heap.
7147 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7148
7149 instruct storePConditional(memory heap_top_ptr,
7150 rax_RegP oldval, rRegP newval,
7151 rFlagsReg cr)
7152 %{
7153 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7154
7155 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7156 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7157 opcode(0x0F, 0xB1);
7158 ins_encode(lock_prefix,
7159 REX_reg_mem_wide(newval, heap_top_ptr),
7160 OpcP, OpcS,
7161 reg_mem(newval, heap_top_ptr));
7162 ins_pipe(pipe_cmpxchg);
7163 %}
7164
7165 // Conditional-store of an int value.
7166 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7167 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7168 %{
7169 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7170 effect(KILL oldval);
7171
7172 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7173 opcode(0x0F, 0xB1);
7174 ins_encode(lock_prefix,
7175 REX_reg_mem(newval, mem),
7176 OpcP, OpcS,
7177 reg_mem(newval, mem));
7178 ins_pipe(pipe_cmpxchg);
7179 %}
7180
7181 // Conditional-store of a long value.
7182 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7183 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7184 %{
7185 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7186 effect(KILL oldval);
7187
7188 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7189 opcode(0x0F, 0xB1);
7190 ins_encode(lock_prefix,
7191 REX_reg_mem_wide(newval, mem),
7192 OpcP, OpcS,
7193 reg_mem(newval, mem));
7194 ins_pipe(pipe_cmpxchg);
7195 %}
7196
7197
7198 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7199 instruct compareAndSwapP(rRegI res,
7200 memory mem_ptr,
7201 rax_RegP oldval, rRegP newval,
7202 rFlagsReg cr)
7203 %{
7204 predicate(VM_Version::supports_cx8());
7205 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7206 effect(KILL cr, KILL oldval);
7207
7208 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7209 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7210 "sete $res\n\t"
7211 "movzbl $res, $res" %}
7212 opcode(0x0F, 0xB1);
7213 ins_encode(lock_prefix,
7214 REX_reg_mem_wide(newval, mem_ptr),
7215 OpcP, OpcS,
7216 reg_mem(newval, mem_ptr),
7217 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7218 REX_reg_breg(res, res), // movzbl
7219 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7220 ins_pipe( pipe_cmpxchg );
7221 %}
7222
7223 instruct compareAndSwapL(rRegI res,
7224 memory mem_ptr,
7225 rax_RegL oldval, rRegL newval,
7226 rFlagsReg cr)
7227 %{
7228 predicate(VM_Version::supports_cx8());
7229 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7230 effect(KILL cr, KILL oldval);
7231
7232 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7233 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7234 "sete $res\n\t"
7235 "movzbl $res, $res" %}
7236 opcode(0x0F, 0xB1);
7237 ins_encode(lock_prefix,
7238 REX_reg_mem_wide(newval, mem_ptr),
7239 OpcP, OpcS,
7240 reg_mem(newval, mem_ptr),
7241 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7242 REX_reg_breg(res, res), // movzbl
7243 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7244 ins_pipe( pipe_cmpxchg );
7245 %}
7246
7247 instruct compareAndSwapI(rRegI res,
7248 memory mem_ptr,
7249 rax_RegI oldval, rRegI newval,
7250 rFlagsReg cr)
7251 %{
7252 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7253 effect(KILL cr, KILL oldval);
7254
7255 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7256 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7257 "sete $res\n\t"
7258 "movzbl $res, $res" %}
7259 opcode(0x0F, 0xB1);
7260 ins_encode(lock_prefix,
7261 REX_reg_mem(newval, mem_ptr),
7262 OpcP, OpcS,
7263 reg_mem(newval, mem_ptr),
7264 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7265 REX_reg_breg(res, res), // movzbl
7266 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7267 ins_pipe( pipe_cmpxchg );
7268 %}
7269
7270
7271 instruct compareAndSwapN(rRegI res,
7272 memory mem_ptr,
7273 rax_RegN oldval, rRegN newval,
7274 rFlagsReg cr) %{
7275 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7276 effect(KILL cr, KILL oldval);
7277
7278 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7279 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7280 "sete $res\n\t"
7281 "movzbl $res, $res" %}
7282 opcode(0x0F, 0xB1);
7283 ins_encode(lock_prefix,
7284 REX_reg_mem(newval, mem_ptr),
7285 OpcP, OpcS,
7286 reg_mem(newval, mem_ptr),
7287 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7288 REX_reg_breg(res, res), // movzbl
7289 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7290 ins_pipe( pipe_cmpxchg );
7291 %}
7292
7293 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7294 predicate(n->as_LoadStore()->result_not_used());
7295 match(Set dummy (GetAndAddI mem add));
7296 effect(KILL cr);
7297 format %{ "ADDL [$mem],$add" %}
7298 ins_encode %{
7299 if (os::is_MP()) { __ lock(); }
7300 __ addl($mem$$Address, $add$$constant);
7301 %}
7302 ins_pipe( pipe_cmpxchg );
7303 %}
7304
7305 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7306 match(Set newval (GetAndAddI mem newval));
7307 effect(KILL cr);
7308 format %{ "XADDL [$mem],$newval" %}
7309 ins_encode %{
7310 if (os::is_MP()) { __ lock(); }
7311 __ xaddl($mem$$Address, $newval$$Register);
7312 %}
7313 ins_pipe( pipe_cmpxchg );
7314 %}
7315
7316 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7317 predicate(n->as_LoadStore()->result_not_used());
7318 match(Set dummy (GetAndAddL mem add));
7319 effect(KILL cr);
7320 format %{ "ADDQ [$mem],$add" %}
7321 ins_encode %{
7322 if (os::is_MP()) { __ lock(); }
7323 __ addq($mem$$Address, $add$$constant);
7324 %}
7325 ins_pipe( pipe_cmpxchg );
7326 %}
7327
7328 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7329 match(Set newval (GetAndAddL mem newval));
7330 effect(KILL cr);
7331 format %{ "XADDQ [$mem],$newval" %}
7332 ins_encode %{
7333 if (os::is_MP()) { __ lock(); }
7334 __ xaddq($mem$$Address, $newval$$Register);
7335 %}
7336 ins_pipe( pipe_cmpxchg );
7337 %}
7338
7339 instruct xchgI( memory mem, rRegI newval) %{
7340 match(Set newval (GetAndSetI mem newval));
7341 format %{ "XCHGL $newval,[$mem]" %}
7342 ins_encode %{
7343 __ xchgl($newval$$Register, $mem$$Address);
7344 %}
7345 ins_pipe( pipe_cmpxchg );
7346 %}
7347
7348 instruct xchgL( memory mem, rRegL newval) %{
7349 match(Set newval (GetAndSetL mem newval));
7350 format %{ "XCHGL $newval,[$mem]" %}
7351 ins_encode %{
7352 __ xchgq($newval$$Register, $mem$$Address);
7353 %}
7354 ins_pipe( pipe_cmpxchg );
7355 %}
7356
7357 instruct xchgP( memory mem, rRegP newval) %{
7358 match(Set newval (GetAndSetP mem newval));
7359 format %{ "XCHGQ $newval,[$mem]" %}
7360 ins_encode %{
7361 __ xchgq($newval$$Register, $mem$$Address);
7362 %}
7363 ins_pipe( pipe_cmpxchg );
7364 %}
7365
7366 instruct xchgN( memory mem, rRegN newval) %{
7367 match(Set newval (GetAndSetN mem newval));
7368 format %{ "XCHGL $newval,$mem]" %}
7369 ins_encode %{
7370 __ xchgl($newval$$Register, $mem$$Address);
7371 %}
7372 ins_pipe( pipe_cmpxchg );
7373 %}
7374
7375 //----------Subtraction Instructions-------------------------------------------
7376
7377 // Integer Subtraction Instructions
7378 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7379 %{
7380 match(Set dst (SubI dst src));
7381 effect(KILL cr);
7382
7383 format %{ "subl $dst, $src\t# int" %}
7384 opcode(0x2B);
7385 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7386 ins_pipe(ialu_reg_reg);
7387 %}
7388
7389 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7390 %{
7391 match(Set dst (SubI dst src));
7392 effect(KILL cr);
7393
7394 format %{ "subl $dst, $src\t# int" %}
7395 opcode(0x81, 0x05); /* Opcode 81 /5 */
7396 ins_encode(OpcSErm(dst, src), Con8or32(src));
7397 ins_pipe(ialu_reg);
7398 %}
7399
7400 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7401 %{
7402 match(Set dst (SubI dst (LoadI src)));
7403 effect(KILL cr);
7404
7405 ins_cost(125);
7406 format %{ "subl $dst, $src\t# int" %}
7407 opcode(0x2B);
7408 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7409 ins_pipe(ialu_reg_mem);
7410 %}
7411
7412 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7413 %{
7414 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7415 effect(KILL cr);
7416
7417 ins_cost(150);
7418 format %{ "subl $dst, $src\t# int" %}
7419 opcode(0x29); /* Opcode 29 /r */
7420 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7421 ins_pipe(ialu_mem_reg);
7422 %}
7423
7424 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7425 %{
7426 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7427 effect(KILL cr);
7428
7429 ins_cost(125); // XXX
7430 format %{ "subl $dst, $src\t# int" %}
7431 opcode(0x81); /* Opcode 81 /5 id */
7432 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7433 ins_pipe(ialu_mem_imm);
7434 %}
7435
7436 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7437 %{
7438 match(Set dst (SubL dst src));
7439 effect(KILL cr);
7440
7441 format %{ "subq $dst, $src\t# long" %}
7442 opcode(0x2B);
7443 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7444 ins_pipe(ialu_reg_reg);
7445 %}
7446
7447 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7448 %{
7449 match(Set dst (SubL dst src));
7450 effect(KILL cr);
7451
7452 format %{ "subq $dst, $src\t# long" %}
7453 opcode(0x81, 0x05); /* Opcode 81 /5 */
7454 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7455 ins_pipe(ialu_reg);
7456 %}
7457
7458 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7459 %{
7460 match(Set dst (SubL dst (LoadL src)));
7461 effect(KILL cr);
7462
7463 ins_cost(125);
7464 format %{ "subq $dst, $src\t# long" %}
7465 opcode(0x2B);
7466 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7467 ins_pipe(ialu_reg_mem);
7468 %}
7469
7470 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7471 %{
7472 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7473 effect(KILL cr);
7474
7475 ins_cost(150);
7476 format %{ "subq $dst, $src\t# long" %}
7477 opcode(0x29); /* Opcode 29 /r */
7478 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7479 ins_pipe(ialu_mem_reg);
7480 %}
7481
7482 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7483 %{
7484 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7485 effect(KILL cr);
7486
7487 ins_cost(125); // XXX
7488 format %{ "subq $dst, $src\t# long" %}
7489 opcode(0x81); /* Opcode 81 /5 id */
7490 ins_encode(REX_mem_wide(dst),
7491 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7492 ins_pipe(ialu_mem_imm);
7493 %}
7494
7495 // Subtract from a pointer
7496 // XXX hmpf???
7497 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7498 %{
7499 match(Set dst (AddP dst (SubI zero src)));
7500 effect(KILL cr);
7501
7502 format %{ "subq $dst, $src\t# ptr - int" %}
7503 opcode(0x2B);
7504 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7505 ins_pipe(ialu_reg_reg);
7506 %}
7507
7508 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7509 %{
7510 match(Set dst (SubI zero dst));
7511 effect(KILL cr);
7512
7513 format %{ "negl $dst\t# int" %}
7514 opcode(0xF7, 0x03); // Opcode F7 /3
7515 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7516 ins_pipe(ialu_reg);
7517 %}
7518
7519 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7520 %{
7521 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7522 effect(KILL cr);
7523
7524 format %{ "negl $dst\t# int" %}
7525 opcode(0xF7, 0x03); // Opcode F7 /3
7526 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7527 ins_pipe(ialu_reg);
7528 %}
7529
7530 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7531 %{
7532 match(Set dst (SubL zero dst));
7533 effect(KILL cr);
7534
7535 format %{ "negq $dst\t# long" %}
7536 opcode(0xF7, 0x03); // Opcode F7 /3
7537 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7538 ins_pipe(ialu_reg);
7539 %}
7540
7541 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7542 %{
7543 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7544 effect(KILL cr);
7545
7546 format %{ "negq $dst\t# long" %}
7547 opcode(0xF7, 0x03); // Opcode F7 /3
7548 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7549 ins_pipe(ialu_reg);
7550 %}
7551
7552 //----------Multiplication/Division Instructions-------------------------------
7553 // Integer Multiplication Instructions
7554 // Multiply Register
7555
7556 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7557 %{
7558 match(Set dst (MulI dst src));
7559 effect(KILL cr);
7560
7561 ins_cost(300);
7562 format %{ "imull $dst, $src\t# int" %}
7563 opcode(0x0F, 0xAF);
7564 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7565 ins_pipe(ialu_reg_reg_alu0);
7566 %}
7567
7568 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7569 %{
7570 match(Set dst (MulI src imm));
7571 effect(KILL cr);
7572
7573 ins_cost(300);
7574 format %{ "imull $dst, $src, $imm\t# int" %}
7575 opcode(0x69); /* 69 /r id */
7576 ins_encode(REX_reg_reg(dst, src),
7577 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7578 ins_pipe(ialu_reg_reg_alu0);
7579 %}
7580
7581 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7582 %{
7583 match(Set dst (MulI dst (LoadI src)));
7584 effect(KILL cr);
7585
7586 ins_cost(350);
7587 format %{ "imull $dst, $src\t# int" %}
7588 opcode(0x0F, 0xAF);
7589 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7590 ins_pipe(ialu_reg_mem_alu0);
7591 %}
7592
7593 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7594 %{
7595 match(Set dst (MulI (LoadI src) imm));
7596 effect(KILL cr);
7597
7598 ins_cost(300);
7599 format %{ "imull $dst, $src, $imm\t# int" %}
7600 opcode(0x69); /* 69 /r id */
7601 ins_encode(REX_reg_mem(dst, src),
7602 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7603 ins_pipe(ialu_reg_mem_alu0);
7604 %}
7605
7606 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7607 %{
7608 match(Set dst (MulL dst src));
7609 effect(KILL cr);
7610
7611 ins_cost(300);
7612 format %{ "imulq $dst, $src\t# long" %}
7613 opcode(0x0F, 0xAF);
7614 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7615 ins_pipe(ialu_reg_reg_alu0);
7616 %}
7617
7618 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7619 %{
7620 match(Set dst (MulL src imm));
7621 effect(KILL cr);
7622
7623 ins_cost(300);
7624 format %{ "imulq $dst, $src, $imm\t# long" %}
7625 opcode(0x69); /* 69 /r id */
7626 ins_encode(REX_reg_reg_wide(dst, src),
7627 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7628 ins_pipe(ialu_reg_reg_alu0);
7629 %}
7630
7631 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7632 %{
7633 match(Set dst (MulL dst (LoadL src)));
7634 effect(KILL cr);
7635
7636 ins_cost(350);
7637 format %{ "imulq $dst, $src\t# long" %}
7638 opcode(0x0F, 0xAF);
7639 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
7640 ins_pipe(ialu_reg_mem_alu0);
7641 %}
7642
7643 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7644 %{
7645 match(Set dst (MulL (LoadL src) imm));
7646 effect(KILL cr);
7647
7648 ins_cost(300);
7649 format %{ "imulq $dst, $src, $imm\t# long" %}
7650 opcode(0x69); /* 69 /r id */
7651 ins_encode(REX_reg_mem_wide(dst, src),
7652 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7653 ins_pipe(ialu_reg_mem_alu0);
7654 %}
7655
7656 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7657 %{
7658 match(Set dst (MulHiL src rax));
7659 effect(USE_KILL rax, KILL cr);
7660
7661 ins_cost(300);
7662 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7663 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7664 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7665 ins_pipe(ialu_reg_reg_alu0);
7666 %}
7667
7668 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7669 rFlagsReg cr)
7670 %{
7671 match(Set rax (DivI rax div));
7672 effect(KILL rdx, KILL cr);
7673
7674 ins_cost(30*100+10*100); // XXX
7675 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7676 "jne,s normal\n\t"
7677 "xorl rdx, rdx\n\t"
7678 "cmpl $div, -1\n\t"
7679 "je,s done\n"
7680 "normal: cdql\n\t"
7681 "idivl $div\n"
7682 "done:" %}
7683 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7684 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7685 ins_pipe(ialu_reg_reg_alu0);
7686 %}
7687
7688 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7689 rFlagsReg cr)
7690 %{
7691 match(Set rax (DivL rax div));
7692 effect(KILL rdx, KILL cr);
7693
7694 ins_cost(30*100+10*100); // XXX
7695 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7696 "cmpq rax, rdx\n\t"
7697 "jne,s normal\n\t"
7698 "xorl rdx, rdx\n\t"
7699 "cmpq $div, -1\n\t"
7700 "je,s done\n"
7701 "normal: cdqq\n\t"
7702 "idivq $div\n"
7703 "done:" %}
7704 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7705 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7706 ins_pipe(ialu_reg_reg_alu0);
7707 %}
7708
7709 // Integer DIVMOD with Register, both quotient and mod results
7710 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7711 rFlagsReg cr)
7712 %{
7713 match(DivModI rax div);
7714 effect(KILL cr);
7715
7716 ins_cost(30*100+10*100); // XXX
7717 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7718 "jne,s normal\n\t"
7719 "xorl rdx, rdx\n\t"
7720 "cmpl $div, -1\n\t"
7721 "je,s done\n"
7722 "normal: cdql\n\t"
7723 "idivl $div\n"
7724 "done:" %}
7725 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7726 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7727 ins_pipe(pipe_slow);
7728 %}
7729
7730 // Long DIVMOD with Register, both quotient and mod results
7731 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7732 rFlagsReg cr)
7733 %{
7734 match(DivModL rax div);
7735 effect(KILL cr);
7736
7737 ins_cost(30*100+10*100); // XXX
7738 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7739 "cmpq rax, rdx\n\t"
7740 "jne,s normal\n\t"
7741 "xorl rdx, rdx\n\t"
7742 "cmpq $div, -1\n\t"
7743 "je,s done\n"
7744 "normal: cdqq\n\t"
7745 "idivq $div\n"
7746 "done:" %}
7747 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7748 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7749 ins_pipe(pipe_slow);
7750 %}
7751
7752 //----------- DivL-By-Constant-Expansions--------------------------------------
7753 // DivI cases are handled by the compiler
7754
7755 // Magic constant, reciprocal of 10
7756 instruct loadConL_0x6666666666666667(rRegL dst)
7757 %{
7758 effect(DEF dst);
7759
7760 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
7761 ins_encode(load_immL(dst, 0x6666666666666667));
7762 ins_pipe(ialu_reg);
7763 %}
7764
7765 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7766 %{
7767 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
7768
7769 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
7770 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7771 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7772 ins_pipe(ialu_reg_reg_alu0);
7773 %}
7774
7775 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
7776 %{
7777 effect(USE_DEF dst, KILL cr);
7778
7779 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
7780 opcode(0xC1, 0x7); /* C1 /7 ib */
7781 ins_encode(reg_opc_imm_wide(dst, 0x3F));
7782 ins_pipe(ialu_reg);
7783 %}
7784
7785 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
7786 %{
7787 effect(USE_DEF dst, KILL cr);
7788
7789 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
7790 opcode(0xC1, 0x7); /* C1 /7 ib */
7791 ins_encode(reg_opc_imm_wide(dst, 0x2));
7792 ins_pipe(ialu_reg);
7793 %}
7794
7795 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
7796 %{
7797 match(Set dst (DivL src div));
7798
7799 ins_cost((5+8)*100);
7800 expand %{
7801 rax_RegL rax; // Killed temp
7802 rFlagsReg cr; // Killed
7803 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
7804 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
7805 sarL_rReg_63(src, cr); // sarq src, 63
7806 sarL_rReg_2(dst, cr); // sarq rdx, 2
7807 subL_rReg(dst, src, cr); // subl rdx, src
7808 %}
7809 %}
7810
7811 //-----------------------------------------------------------------------------
7812
7813 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
7814 rFlagsReg cr)
7815 %{
7816 match(Set rdx (ModI rax div));
7817 effect(KILL rax, KILL cr);
7818
7819 ins_cost(300); // XXX
7820 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
7821 "jne,s normal\n\t"
7822 "xorl rdx, rdx\n\t"
7823 "cmpl $div, -1\n\t"
7824 "je,s done\n"
7825 "normal: cdql\n\t"
7826 "idivl $div\n"
7827 "done:" %}
7828 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7829 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7830 ins_pipe(ialu_reg_reg_alu0);
7831 %}
7832
7833 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
7834 rFlagsReg cr)
7835 %{
7836 match(Set rdx (ModL rax div));
7837 effect(KILL rax, KILL cr);
7838
7839 ins_cost(300); // XXX
7840 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
7841 "cmpq rax, rdx\n\t"
7842 "jne,s normal\n\t"
7843 "xorl rdx, rdx\n\t"
7844 "cmpq $div, -1\n\t"
7845 "je,s done\n"
7846 "normal: cdqq\n\t"
7847 "idivq $div\n"
7848 "done:" %}
7849 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7850 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7851 ins_pipe(ialu_reg_reg_alu0);
7852 %}
7853
7854 // Integer Shift Instructions
7855 // Shift Left by one
7856 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7857 %{
7858 match(Set dst (LShiftI dst shift));
7859 effect(KILL cr);
7860
7861 format %{ "sall $dst, $shift" %}
7862 opcode(0xD1, 0x4); /* D1 /4 */
7863 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7864 ins_pipe(ialu_reg);
7865 %}
7866
7867 // Shift Left by one
7868 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7869 %{
7870 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7871 effect(KILL cr);
7872
7873 format %{ "sall $dst, $shift\t" %}
7874 opcode(0xD1, 0x4); /* D1 /4 */
7875 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7876 ins_pipe(ialu_mem_imm);
7877 %}
7878
7879 // Shift Left by 8-bit immediate
7880 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7881 %{
7882 match(Set dst (LShiftI dst shift));
7883 effect(KILL cr);
7884
7885 format %{ "sall $dst, $shift" %}
7886 opcode(0xC1, 0x4); /* C1 /4 ib */
7887 ins_encode(reg_opc_imm(dst, shift));
7888 ins_pipe(ialu_reg);
7889 %}
7890
7891 // Shift Left by 8-bit immediate
7892 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7893 %{
7894 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7895 effect(KILL cr);
7896
7897 format %{ "sall $dst, $shift" %}
7898 opcode(0xC1, 0x4); /* C1 /4 ib */
7899 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
7900 ins_pipe(ialu_mem_imm);
7901 %}
7902
7903 // Shift Left by variable
7904 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
7905 %{
7906 match(Set dst (LShiftI dst shift));
7907 effect(KILL cr);
7908
7909 format %{ "sall $dst, $shift" %}
7910 opcode(0xD3, 0x4); /* D3 /4 */
7911 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7912 ins_pipe(ialu_reg_reg);
7913 %}
7914
7915 // Shift Left by variable
7916 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
7917 %{
7918 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7919 effect(KILL cr);
7920
7921 format %{ "sall $dst, $shift" %}
7922 opcode(0xD3, 0x4); /* D3 /4 */
7923 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7924 ins_pipe(ialu_mem_reg);
7925 %}
7926
7927 // Arithmetic shift right by one
7928 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7929 %{
7930 match(Set dst (RShiftI dst shift));
7931 effect(KILL cr);
7932
7933 format %{ "sarl $dst, $shift" %}
7934 opcode(0xD1, 0x7); /* D1 /7 */
7935 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7936 ins_pipe(ialu_reg);
7937 %}
7938
7939 // Arithmetic shift right by one
7940 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7941 %{
7942 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7943 effect(KILL cr);
7944
7945 format %{ "sarl $dst, $shift" %}
7946 opcode(0xD1, 0x7); /* D1 /7 */
7947 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7948 ins_pipe(ialu_mem_imm);
7949 %}
7950
7951 // Arithmetic Shift Right by 8-bit immediate
7952 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7953 %{
7954 match(Set dst (RShiftI dst shift));
7955 effect(KILL cr);
7956
7957 format %{ "sarl $dst, $shift" %}
7958 opcode(0xC1, 0x7); /* C1 /7 ib */
7959 ins_encode(reg_opc_imm(dst, shift));
7960 ins_pipe(ialu_mem_imm);
7961 %}
7962
7963 // Arithmetic Shift Right by 8-bit immediate
7964 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7965 %{
7966 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7967 effect(KILL cr);
7968
7969 format %{ "sarl $dst, $shift" %}
7970 opcode(0xC1, 0x7); /* C1 /7 ib */
7971 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
7972 ins_pipe(ialu_mem_imm);
7973 %}
7974
7975 // Arithmetic Shift Right by variable
7976 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
7977 %{
7978 match(Set dst (RShiftI dst shift));
7979 effect(KILL cr);
7980
7981 format %{ "sarl $dst, $shift" %}
7982 opcode(0xD3, 0x7); /* D3 /7 */
7983 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7984 ins_pipe(ialu_reg_reg);
7985 %}
7986
7987 // Arithmetic Shift Right by variable
7988 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
7989 %{
7990 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7991 effect(KILL cr);
7992
7993 format %{ "sarl $dst, $shift" %}
7994 opcode(0xD3, 0x7); /* D3 /7 */
7995 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7996 ins_pipe(ialu_mem_reg);
7997 %}
7998
7999 // Logical shift right by one
8000 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8001 %{
8002 match(Set dst (URShiftI dst shift));
8003 effect(KILL cr);
8004
8005 format %{ "shrl $dst, $shift" %}
8006 opcode(0xD1, 0x5); /* D1 /5 */
8007 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8008 ins_pipe(ialu_reg);
8009 %}
8010
8011 // Logical shift right by one
8012 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8013 %{
8014 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8015 effect(KILL cr);
8016
8017 format %{ "shrl $dst, $shift" %}
8018 opcode(0xD1, 0x5); /* D1 /5 */
8019 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8020 ins_pipe(ialu_mem_imm);
8021 %}
8022
8023 // Logical Shift Right by 8-bit immediate
8024 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8025 %{
8026 match(Set dst (URShiftI dst shift));
8027 effect(KILL cr);
8028
8029 format %{ "shrl $dst, $shift" %}
8030 opcode(0xC1, 0x5); /* C1 /5 ib */
8031 ins_encode(reg_opc_imm(dst, shift));
8032 ins_pipe(ialu_reg);
8033 %}
8034
8035 // Logical Shift Right by 8-bit immediate
8036 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8037 %{
8038 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8039 effect(KILL cr);
8040
8041 format %{ "shrl $dst, $shift" %}
8042 opcode(0xC1, 0x5); /* C1 /5 ib */
8043 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8044 ins_pipe(ialu_mem_imm);
8045 %}
8046
8047 // Logical Shift Right by variable
8048 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8049 %{
8050 match(Set dst (URShiftI dst shift));
8051 effect(KILL cr);
8052
8053 format %{ "shrl $dst, $shift" %}
8054 opcode(0xD3, 0x5); /* D3 /5 */
8055 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8056 ins_pipe(ialu_reg_reg);
8057 %}
8058
8059 // Logical Shift Right by variable
8060 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8061 %{
8062 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8063 effect(KILL cr);
8064
8065 format %{ "shrl $dst, $shift" %}
8066 opcode(0xD3, 0x5); /* D3 /5 */
8067 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8068 ins_pipe(ialu_mem_reg);
8069 %}
8070
8071 // Long Shift Instructions
8072 // Shift Left by one
8073 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8074 %{
8075 match(Set dst (LShiftL dst shift));
8076 effect(KILL cr);
8077
8078 format %{ "salq $dst, $shift" %}
8079 opcode(0xD1, 0x4); /* D1 /4 */
8080 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8081 ins_pipe(ialu_reg);
8082 %}
8083
8084 // Shift Left by one
8085 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8086 %{
8087 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8088 effect(KILL cr);
8089
8090 format %{ "salq $dst, $shift" %}
8091 opcode(0xD1, 0x4); /* D1 /4 */
8092 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8093 ins_pipe(ialu_mem_imm);
8094 %}
8095
8096 // Shift Left by 8-bit immediate
8097 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8098 %{
8099 match(Set dst (LShiftL dst shift));
8100 effect(KILL cr);
8101
8102 format %{ "salq $dst, $shift" %}
8103 opcode(0xC1, 0x4); /* C1 /4 ib */
8104 ins_encode(reg_opc_imm_wide(dst, shift));
8105 ins_pipe(ialu_reg);
8106 %}
8107
8108 // Shift Left by 8-bit immediate
8109 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8110 %{
8111 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8112 effect(KILL cr);
8113
8114 format %{ "salq $dst, $shift" %}
8115 opcode(0xC1, 0x4); /* C1 /4 ib */
8116 ins_encode(REX_mem_wide(dst), OpcP,
8117 RM_opc_mem(secondary, dst), Con8or32(shift));
8118 ins_pipe(ialu_mem_imm);
8119 %}
8120
8121 // Shift Left by variable
8122 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8123 %{
8124 match(Set dst (LShiftL dst shift));
8125 effect(KILL cr);
8126
8127 format %{ "salq $dst, $shift" %}
8128 opcode(0xD3, 0x4); /* D3 /4 */
8129 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8130 ins_pipe(ialu_reg_reg);
8131 %}
8132
8133 // Shift Left by variable
8134 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8135 %{
8136 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8137 effect(KILL cr);
8138
8139 format %{ "salq $dst, $shift" %}
8140 opcode(0xD3, 0x4); /* D3 /4 */
8141 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8142 ins_pipe(ialu_mem_reg);
8143 %}
8144
8145 // Arithmetic shift right by one
8146 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8147 %{
8148 match(Set dst (RShiftL dst shift));
8149 effect(KILL cr);
8150
8151 format %{ "sarq $dst, $shift" %}
8152 opcode(0xD1, 0x7); /* D1 /7 */
8153 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8154 ins_pipe(ialu_reg);
8155 %}
8156
8157 // Arithmetic shift right by one
8158 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8159 %{
8160 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8161 effect(KILL cr);
8162
8163 format %{ "sarq $dst, $shift" %}
8164 opcode(0xD1, 0x7); /* D1 /7 */
8165 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8166 ins_pipe(ialu_mem_imm);
8167 %}
8168
8169 // Arithmetic Shift Right by 8-bit immediate
8170 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8171 %{
8172 match(Set dst (RShiftL dst shift));
8173 effect(KILL cr);
8174
8175 format %{ "sarq $dst, $shift" %}
8176 opcode(0xC1, 0x7); /* C1 /7 ib */
8177 ins_encode(reg_opc_imm_wide(dst, shift));
8178 ins_pipe(ialu_mem_imm);
8179 %}
8180
8181 // Arithmetic Shift Right by 8-bit immediate
8182 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8183 %{
8184 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8185 effect(KILL cr);
8186
8187 format %{ "sarq $dst, $shift" %}
8188 opcode(0xC1, 0x7); /* C1 /7 ib */
8189 ins_encode(REX_mem_wide(dst), OpcP,
8190 RM_opc_mem(secondary, dst), Con8or32(shift));
8191 ins_pipe(ialu_mem_imm);
8192 %}
8193
8194 // Arithmetic Shift Right by variable
8195 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8196 %{
8197 match(Set dst (RShiftL dst shift));
8198 effect(KILL cr);
8199
8200 format %{ "sarq $dst, $shift" %}
8201 opcode(0xD3, 0x7); /* D3 /7 */
8202 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8203 ins_pipe(ialu_reg_reg);
8204 %}
8205
8206 // Arithmetic Shift Right by variable
8207 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8208 %{
8209 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8210 effect(KILL cr);
8211
8212 format %{ "sarq $dst, $shift" %}
8213 opcode(0xD3, 0x7); /* D3 /7 */
8214 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8215 ins_pipe(ialu_mem_reg);
8216 %}
8217
8218 // Logical shift right by one
8219 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8220 %{
8221 match(Set dst (URShiftL dst shift));
8222 effect(KILL cr);
8223
8224 format %{ "shrq $dst, $shift" %}
8225 opcode(0xD1, 0x5); /* D1 /5 */
8226 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8227 ins_pipe(ialu_reg);
8228 %}
8229
8230 // Logical shift right by one
8231 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8232 %{
8233 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8234 effect(KILL cr);
8235
8236 format %{ "shrq $dst, $shift" %}
8237 opcode(0xD1, 0x5); /* D1 /5 */
8238 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8239 ins_pipe(ialu_mem_imm);
8240 %}
8241
8242 // Logical Shift Right by 8-bit immediate
8243 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8244 %{
8245 match(Set dst (URShiftL dst shift));
8246 effect(KILL cr);
8247
8248 format %{ "shrq $dst, $shift" %}
8249 opcode(0xC1, 0x5); /* C1 /5 ib */
8250 ins_encode(reg_opc_imm_wide(dst, shift));
8251 ins_pipe(ialu_reg);
8252 %}
8253
8254
8255 // Logical Shift Right by 8-bit immediate
8256 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8257 %{
8258 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8259 effect(KILL cr);
8260
8261 format %{ "shrq $dst, $shift" %}
8262 opcode(0xC1, 0x5); /* C1 /5 ib */
8263 ins_encode(REX_mem_wide(dst), OpcP,
8264 RM_opc_mem(secondary, dst), Con8or32(shift));
8265 ins_pipe(ialu_mem_imm);
8266 %}
8267
8268 // Logical Shift Right by variable
8269 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8270 %{
8271 match(Set dst (URShiftL dst shift));
8272 effect(KILL cr);
8273
8274 format %{ "shrq $dst, $shift" %}
8275 opcode(0xD3, 0x5); /* D3 /5 */
8276 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8277 ins_pipe(ialu_reg_reg);
8278 %}
8279
8280 // Logical Shift Right by variable
8281 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8282 %{
8283 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8284 effect(KILL cr);
8285
8286 format %{ "shrq $dst, $shift" %}
8287 opcode(0xD3, 0x5); /* D3 /5 */
8288 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8289 ins_pipe(ialu_mem_reg);
8290 %}
8291
8292 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8293 // This idiom is used by the compiler for the i2b bytecode.
8294 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8295 %{
8296 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8297
8298 format %{ "movsbl $dst, $src\t# i2b" %}
8299 opcode(0x0F, 0xBE);
8300 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8301 ins_pipe(ialu_reg_reg);
8302 %}
8303
8304 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8305 // This idiom is used by the compiler the i2s bytecode.
8306 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8307 %{
8308 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8309
8310 format %{ "movswl $dst, $src\t# i2s" %}
8311 opcode(0x0F, 0xBF);
8312 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8313 ins_pipe(ialu_reg_reg);
8314 %}
8315
8316 // ROL/ROR instructions
8317
8318 // ROL expand
8319 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8320 effect(KILL cr, USE_DEF dst);
8321
8322 format %{ "roll $dst" %}
8323 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8324 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8325 ins_pipe(ialu_reg);
8326 %}
8327
8328 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8329 effect(USE_DEF dst, USE shift, KILL cr);
8330
8331 format %{ "roll $dst, $shift" %}
8332 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8333 ins_encode( reg_opc_imm(dst, shift) );
8334 ins_pipe(ialu_reg);
8335 %}
8336
8337 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8338 %{
8339 effect(USE_DEF dst, USE shift, KILL cr);
8340
8341 format %{ "roll $dst, $shift" %}
8342 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8343 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8344 ins_pipe(ialu_reg_reg);
8345 %}
8346 // end of ROL expand
8347
8348 // Rotate Left by one
8349 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8350 %{
8351 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8352
8353 expand %{
8354 rolI_rReg_imm1(dst, cr);
8355 %}
8356 %}
8357
8358 // Rotate Left by 8-bit immediate
8359 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8360 %{
8361 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8362 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8363
8364 expand %{
8365 rolI_rReg_imm8(dst, lshift, cr);
8366 %}
8367 %}
8368
8369 // Rotate Left by variable
8370 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8371 %{
8372 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8373
8374 expand %{
8375 rolI_rReg_CL(dst, shift, cr);
8376 %}
8377 %}
8378
8379 // Rotate Left by variable
8380 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8381 %{
8382 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8383
8384 expand %{
8385 rolI_rReg_CL(dst, shift, cr);
8386 %}
8387 %}
8388
8389 // ROR expand
8390 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8391 %{
8392 effect(USE_DEF dst, KILL cr);
8393
8394 format %{ "rorl $dst" %}
8395 opcode(0xD1, 0x1); /* D1 /1 */
8396 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8397 ins_pipe(ialu_reg);
8398 %}
8399
8400 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8401 %{
8402 effect(USE_DEF dst, USE shift, KILL cr);
8403
8404 format %{ "rorl $dst, $shift" %}
8405 opcode(0xC1, 0x1); /* C1 /1 ib */
8406 ins_encode(reg_opc_imm(dst, shift));
8407 ins_pipe(ialu_reg);
8408 %}
8409
8410 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8411 %{
8412 effect(USE_DEF dst, USE shift, KILL cr);
8413
8414 format %{ "rorl $dst, $shift" %}
8415 opcode(0xD3, 0x1); /* D3 /1 */
8416 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8417 ins_pipe(ialu_reg_reg);
8418 %}
8419 // end of ROR expand
8420
8421 // Rotate Right by one
8422 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8423 %{
8424 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8425
8426 expand %{
8427 rorI_rReg_imm1(dst, cr);
8428 %}
8429 %}
8430
8431 // Rotate Right by 8-bit immediate
8432 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8433 %{
8434 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8435 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8436
8437 expand %{
8438 rorI_rReg_imm8(dst, rshift, cr);
8439 %}
8440 %}
8441
8442 // Rotate Right by variable
8443 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8444 %{
8445 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8446
8447 expand %{
8448 rorI_rReg_CL(dst, shift, cr);
8449 %}
8450 %}
8451
8452 // Rotate Right by variable
8453 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8454 %{
8455 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8456
8457 expand %{
8458 rorI_rReg_CL(dst, shift, cr);
8459 %}
8460 %}
8461
8462 // for long rotate
8463 // ROL expand
8464 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8465 effect(USE_DEF dst, KILL cr);
8466
8467 format %{ "rolq $dst" %}
8468 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8469 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8470 ins_pipe(ialu_reg);
8471 %}
8472
8473 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8474 effect(USE_DEF dst, USE shift, KILL cr);
8475
8476 format %{ "rolq $dst, $shift" %}
8477 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8478 ins_encode( reg_opc_imm_wide(dst, shift) );
8479 ins_pipe(ialu_reg);
8480 %}
8481
8482 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8483 %{
8484 effect(USE_DEF dst, USE shift, KILL cr);
8485
8486 format %{ "rolq $dst, $shift" %}
8487 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8488 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8489 ins_pipe(ialu_reg_reg);
8490 %}
8491 // end of ROL expand
8492
8493 // Rotate Left by one
8494 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8495 %{
8496 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8497
8498 expand %{
8499 rolL_rReg_imm1(dst, cr);
8500 %}
8501 %}
8502
8503 // Rotate Left by 8-bit immediate
8504 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8505 %{
8506 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8507 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8508
8509 expand %{
8510 rolL_rReg_imm8(dst, lshift, cr);
8511 %}
8512 %}
8513
8514 // Rotate Left by variable
8515 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8516 %{
8517 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8518
8519 expand %{
8520 rolL_rReg_CL(dst, shift, cr);
8521 %}
8522 %}
8523
8524 // Rotate Left by variable
8525 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8526 %{
8527 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8528
8529 expand %{
8530 rolL_rReg_CL(dst, shift, cr);
8531 %}
8532 %}
8533
8534 // ROR expand
8535 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8536 %{
8537 effect(USE_DEF dst, KILL cr);
8538
8539 format %{ "rorq $dst" %}
8540 opcode(0xD1, 0x1); /* D1 /1 */
8541 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8542 ins_pipe(ialu_reg);
8543 %}
8544
8545 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8546 %{
8547 effect(USE_DEF dst, USE shift, KILL cr);
8548
8549 format %{ "rorq $dst, $shift" %}
8550 opcode(0xC1, 0x1); /* C1 /1 ib */
8551 ins_encode(reg_opc_imm_wide(dst, shift));
8552 ins_pipe(ialu_reg);
8553 %}
8554
8555 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8556 %{
8557 effect(USE_DEF dst, USE shift, KILL cr);
8558
8559 format %{ "rorq $dst, $shift" %}
8560 opcode(0xD3, 0x1); /* D3 /1 */
8561 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8562 ins_pipe(ialu_reg_reg);
8563 %}
8564 // end of ROR expand
8565
8566 // Rotate Right by one
8567 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8568 %{
8569 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8570
8571 expand %{
8572 rorL_rReg_imm1(dst, cr);
8573 %}
8574 %}
8575
8576 // Rotate Right by 8-bit immediate
8577 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8578 %{
8579 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8580 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8581
8582 expand %{
8583 rorL_rReg_imm8(dst, rshift, cr);
8584 %}
8585 %}
8586
8587 // Rotate Right by variable
8588 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8589 %{
8590 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8591
8592 expand %{
8593 rorL_rReg_CL(dst, shift, cr);
8594 %}
8595 %}
8596
8597 // Rotate Right by variable
8598 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8599 %{
8600 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8601
8602 expand %{
8603 rorL_rReg_CL(dst, shift, cr);
8604 %}
8605 %}
8606
8607 // Logical Instructions
8608
8609 // Integer Logical Instructions
8610
8611 // And Instructions
8612 // And Register with Register
8613 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8614 %{
8615 match(Set dst (AndI dst src));
8616 effect(KILL cr);
8617
8618 format %{ "andl $dst, $src\t# int" %}
8619 opcode(0x23);
8620 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8621 ins_pipe(ialu_reg_reg);
8622 %}
8623
8624 // And Register with Immediate 255
8625 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
8626 %{
8627 match(Set dst (AndI dst src));
8628
8629 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
8630 opcode(0x0F, 0xB6);
8631 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8632 ins_pipe(ialu_reg);
8633 %}
8634
8635 // And Register with Immediate 255 and promote to long
8636 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8637 %{
8638 match(Set dst (ConvI2L (AndI src mask)));
8639
8640 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8641 opcode(0x0F, 0xB6);
8642 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8643 ins_pipe(ialu_reg);
8644 %}
8645
8646 // And Register with Immediate 65535
8647 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
8648 %{
8649 match(Set dst (AndI dst src));
8650
8651 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
8652 opcode(0x0F, 0xB7);
8653 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8654 ins_pipe(ialu_reg);
8655 %}
8656
8657 // And Register with Immediate 65535 and promote to long
8658 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
8659 %{
8660 match(Set dst (ConvI2L (AndI src mask)));
8661
8662 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
8663 opcode(0x0F, 0xB7);
8664 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8665 ins_pipe(ialu_reg);
8666 %}
8667
8668 // And Register with Immediate
8669 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8670 %{
8671 match(Set dst (AndI dst src));
8672 effect(KILL cr);
8673
8674 format %{ "andl $dst, $src\t# int" %}
8675 opcode(0x81, 0x04); /* Opcode 81 /4 */
8676 ins_encode(OpcSErm(dst, src), Con8or32(src));
8677 ins_pipe(ialu_reg);
8678 %}
8679
8680 // And Register with Memory
8681 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8682 %{
8683 match(Set dst (AndI dst (LoadI src)));
8684 effect(KILL cr);
8685
8686 ins_cost(125);
8687 format %{ "andl $dst, $src\t# int" %}
8688 opcode(0x23);
8689 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8690 ins_pipe(ialu_reg_mem);
8691 %}
8692
8693 // And Memory with Register
8694 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8695 %{
8696 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8697 effect(KILL cr);
8698
8699 ins_cost(150);
8700 format %{ "andl $dst, $src\t# int" %}
8701 opcode(0x21); /* Opcode 21 /r */
8702 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8703 ins_pipe(ialu_mem_reg);
8704 %}
8705
8706 // And Memory with Immediate
8707 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
8708 %{
8709 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8710 effect(KILL cr);
8711
8712 ins_cost(125);
8713 format %{ "andl $dst, $src\t# int" %}
8714 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8715 ins_encode(REX_mem(dst), OpcSE(src),
8716 RM_opc_mem(secondary, dst), Con8or32(src));
8717 ins_pipe(ialu_mem_imm);
8718 %}
8719
8720 // BMI1 instructions
8721 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
8722 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
8723 predicate(UseBMI1Instructions);
8724 effect(KILL cr);
8725
8726 ins_cost(125);
8727 format %{ "andnl $dst, $src1, $src2" %}
8728
8729 ins_encode %{
8730 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
8731 %}
8732 ins_pipe(ialu_reg_mem);
8733 %}
8734
8735 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
8736 match(Set dst (AndI (XorI src1 minus_1) src2));
8737 predicate(UseBMI1Instructions);
8738 effect(KILL cr);
8739
8740 format %{ "andnl $dst, $src1, $src2" %}
8741
8742 ins_encode %{
8743 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
8744 %}
8745 ins_pipe(ialu_reg);
8746 %}
8747
8748 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
8749 match(Set dst (AndI (SubI imm_zero src) src));
8750 predicate(UseBMI1Instructions);
8751 effect(KILL cr);
8752
8753 format %{ "blsil $dst, $src" %}
8754
8755 ins_encode %{
8756 __ blsil($dst$$Register, $src$$Register);
8757 %}
8758 ins_pipe(ialu_reg);
8759 %}
8760
8761 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
8762 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
8763 predicate(UseBMI1Instructions);
8764 effect(KILL cr);
8765
8766 ins_cost(125);
8767 format %{ "blsil $dst, $src" %}
8768
8769 ins_encode %{
8770 __ blsil($dst$$Register, $src$$Address);
8771 %}
8772 ins_pipe(ialu_reg_mem);
8773 %}
8774
8775 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
8776 %{
8777 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
8778 predicate(UseBMI1Instructions);
8779 effect(KILL cr);
8780
8781 ins_cost(125);
8782 format %{ "blsmskl $dst, $src" %}
8783
8784 ins_encode %{
8785 __ blsmskl($dst$$Register, $src$$Address);
8786 %}
8787 ins_pipe(ialu_reg_mem);
8788 %}
8789
8790 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
8791 %{
8792 match(Set dst (XorI (AddI src minus_1) src));
8793 predicate(UseBMI1Instructions);
8794 effect(KILL cr);
8795
8796 format %{ "blsmskl $dst, $src" %}
8797
8798 ins_encode %{
8799 __ blsmskl($dst$$Register, $src$$Register);
8800 %}
8801
8802 ins_pipe(ialu_reg);
8803 %}
8804
8805 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
8806 %{
8807 match(Set dst (AndI (AddI src minus_1) src) );
8808 predicate(UseBMI1Instructions);
8809 effect(KILL cr);
8810
8811 format %{ "blsrl $dst, $src" %}
8812
8813 ins_encode %{
8814 __ blsrl($dst$$Register, $src$$Register);
8815 %}
8816
8817 ins_pipe(ialu_reg_mem);
8818 %}
8819
8820 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
8821 %{
8822 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
8823 predicate(UseBMI1Instructions);
8824 effect(KILL cr);
8825
8826 ins_cost(125);
8827 format %{ "blsrl $dst, $src" %}
8828
8829 ins_encode %{
8830 __ blsrl($dst$$Register, $src$$Address);
8831 %}
8832
8833 ins_pipe(ialu_reg);
8834 %}
8835
8836 // Or Instructions
8837 // Or Register with Register
8838 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8839 %{
8840 match(Set dst (OrI dst src));
8841 effect(KILL cr);
8842
8843 format %{ "orl $dst, $src\t# int" %}
8844 opcode(0x0B);
8845 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8846 ins_pipe(ialu_reg_reg);
8847 %}
8848
8849 // Or Register with Immediate
8850 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8851 %{
8852 match(Set dst (OrI dst src));
8853 effect(KILL cr);
8854
8855 format %{ "orl $dst, $src\t# int" %}
8856 opcode(0x81, 0x01); /* Opcode 81 /1 id */
8857 ins_encode(OpcSErm(dst, src), Con8or32(src));
8858 ins_pipe(ialu_reg);
8859 %}
8860
8861 // Or Register with Memory
8862 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8863 %{
8864 match(Set dst (OrI dst (LoadI src)));
8865 effect(KILL cr);
8866
8867 ins_cost(125);
8868 format %{ "orl $dst, $src\t# int" %}
8869 opcode(0x0B);
8870 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8871 ins_pipe(ialu_reg_mem);
8872 %}
8873
8874 // Or Memory with Register
8875 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8876 %{
8877 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8878 effect(KILL cr);
8879
8880 ins_cost(150);
8881 format %{ "orl $dst, $src\t# int" %}
8882 opcode(0x09); /* Opcode 09 /r */
8883 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8884 ins_pipe(ialu_mem_reg);
8885 %}
8886
8887 // Or Memory with Immediate
8888 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
8889 %{
8890 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8891 effect(KILL cr);
8892
8893 ins_cost(125);
8894 format %{ "orl $dst, $src\t# int" %}
8895 opcode(0x81, 0x1); /* Opcode 81 /1 id */
8896 ins_encode(REX_mem(dst), OpcSE(src),
8897 RM_opc_mem(secondary, dst), Con8or32(src));
8898 ins_pipe(ialu_mem_imm);
8899 %}
8900
8901 // Xor Instructions
8902 // Xor Register with Register
8903 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8904 %{
8905 match(Set dst (XorI dst src));
8906 effect(KILL cr);
8907
8908 format %{ "xorl $dst, $src\t# int" %}
8909 opcode(0x33);
8910 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8911 ins_pipe(ialu_reg_reg);
8912 %}
8913
8914 // Xor Register with Immediate -1
8915 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
8916 match(Set dst (XorI dst imm));
8917
8918 format %{ "not $dst" %}
8919 ins_encode %{
8920 __ notl($dst$$Register);
8921 %}
8922 ins_pipe(ialu_reg);
8923 %}
8924
8925 // Xor Register with Immediate
8926 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8927 %{
8928 match(Set dst (XorI dst src));
8929 effect(KILL cr);
8930
8931 format %{ "xorl $dst, $src\t# int" %}
8932 opcode(0x81, 0x06); /* Opcode 81 /6 id */
8933 ins_encode(OpcSErm(dst, src), Con8or32(src));
8934 ins_pipe(ialu_reg);
8935 %}
8936
8937 // Xor Register with Memory
8938 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8939 %{
8940 match(Set dst (XorI dst (LoadI src)));
8941 effect(KILL cr);
8942
8943 ins_cost(125);
8944 format %{ "xorl $dst, $src\t# int" %}
8945 opcode(0x33);
8946 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8947 ins_pipe(ialu_reg_mem);
8948 %}
8949
8950 // Xor Memory with Register
8951 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8952 %{
8953 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8954 effect(KILL cr);
8955
8956 ins_cost(150);
8957 format %{ "xorl $dst, $src\t# int" %}
8958 opcode(0x31); /* Opcode 31 /r */
8959 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8960 ins_pipe(ialu_mem_reg);
8961 %}
8962
8963 // Xor Memory with Immediate
8964 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
8965 %{
8966 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8967 effect(KILL cr);
8968
8969 ins_cost(125);
8970 format %{ "xorl $dst, $src\t# int" %}
8971 opcode(0x81, 0x6); /* Opcode 81 /6 id */
8972 ins_encode(REX_mem(dst), OpcSE(src),
8973 RM_opc_mem(secondary, dst), Con8or32(src));
8974 ins_pipe(ialu_mem_imm);
8975 %}
8976
8977
8978 // Long Logical Instructions
8979
8980 // And Instructions
8981 // And Register with Register
8982 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8983 %{
8984 match(Set dst (AndL dst src));
8985 effect(KILL cr);
8986
8987 format %{ "andq $dst, $src\t# long" %}
8988 opcode(0x23);
8989 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8990 ins_pipe(ialu_reg_reg);
8991 %}
8992
8993 // And Register with Immediate 255
8994 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
8995 %{
8996 match(Set dst (AndL dst src));
8997
8998 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
8999 opcode(0x0F, 0xB6);
9000 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9001 ins_pipe(ialu_reg);
9002 %}
9003
9004 // And Register with Immediate 65535
9005 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9006 %{
9007 match(Set dst (AndL dst src));
9008
9009 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9010 opcode(0x0F, 0xB7);
9011 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9012 ins_pipe(ialu_reg);
9013 %}
9014
9015 // And Register with Immediate
9016 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9017 %{
9018 match(Set dst (AndL dst src));
9019 effect(KILL cr);
9020
9021 format %{ "andq $dst, $src\t# long" %}
9022 opcode(0x81, 0x04); /* Opcode 81 /4 */
9023 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9024 ins_pipe(ialu_reg);
9025 %}
9026
9027 // And Register with Memory
9028 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9029 %{
9030 match(Set dst (AndL dst (LoadL src)));
9031 effect(KILL cr);
9032
9033 ins_cost(125);
9034 format %{ "andq $dst, $src\t# long" %}
9035 opcode(0x23);
9036 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9037 ins_pipe(ialu_reg_mem);
9038 %}
9039
9040 // And Memory with Register
9041 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9042 %{
9043 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9044 effect(KILL cr);
9045
9046 ins_cost(150);
9047 format %{ "andq $dst, $src\t# long" %}
9048 opcode(0x21); /* Opcode 21 /r */
9049 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9050 ins_pipe(ialu_mem_reg);
9051 %}
9052
9053 // And Memory with Immediate
9054 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9055 %{
9056 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9057 effect(KILL cr);
9058
9059 ins_cost(125);
9060 format %{ "andq $dst, $src\t# long" %}
9061 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9062 ins_encode(REX_mem_wide(dst), OpcSE(src),
9063 RM_opc_mem(secondary, dst), Con8or32(src));
9064 ins_pipe(ialu_mem_imm);
9065 %}
9066
9067 // BMI1 instructions
9068 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9069 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9070 predicate(UseBMI1Instructions);
9071 effect(KILL cr);
9072
9073 ins_cost(125);
9074 format %{ "andnq $dst, $src1, $src2" %}
9075
9076 ins_encode %{
9077 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9078 %}
9079 ins_pipe(ialu_reg_mem);
9080 %}
9081
9082 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9083 match(Set dst (AndL (XorL src1 minus_1) src2));
9084 predicate(UseBMI1Instructions);
9085 effect(KILL cr);
9086
9087 format %{ "andnq $dst, $src1, $src2" %}
9088
9089 ins_encode %{
9090 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9091 %}
9092 ins_pipe(ialu_reg_mem);
9093 %}
9094
9095 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9096 match(Set dst (AndL (SubL imm_zero src) src));
9097 predicate(UseBMI1Instructions);
9098 effect(KILL cr);
9099
9100 format %{ "blsiq $dst, $src" %}
9101
9102 ins_encode %{
9103 __ blsiq($dst$$Register, $src$$Register);
9104 %}
9105 ins_pipe(ialu_reg);
9106 %}
9107
9108 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9109 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9110 predicate(UseBMI1Instructions);
9111 effect(KILL cr);
9112
9113 ins_cost(125);
9114 format %{ "blsiq $dst, $src" %}
9115
9116 ins_encode %{
9117 __ blsiq($dst$$Register, $src$$Address);
9118 %}
9119 ins_pipe(ialu_reg_mem);
9120 %}
9121
9122 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9123 %{
9124 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9125 predicate(UseBMI1Instructions);
9126 effect(KILL cr);
9127
9128 ins_cost(125);
9129 format %{ "blsmskq $dst, $src" %}
9130
9131 ins_encode %{
9132 __ blsmskq($dst$$Register, $src$$Address);
9133 %}
9134 ins_pipe(ialu_reg_mem);
9135 %}
9136
9137 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9138 %{
9139 match(Set dst (XorL (AddL src minus_1) src));
9140 predicate(UseBMI1Instructions);
9141 effect(KILL cr);
9142
9143 format %{ "blsmskq $dst, $src" %}
9144
9145 ins_encode %{
9146 __ blsmskq($dst$$Register, $src$$Register);
9147 %}
9148
9149 ins_pipe(ialu_reg);
9150 %}
9151
9152 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9153 %{
9154 match(Set dst (AndL (AddL src minus_1) src) );
9155 predicate(UseBMI1Instructions);
9156 effect(KILL cr);
9157
9158 format %{ "blsrq $dst, $src" %}
9159
9160 ins_encode %{
9161 __ blsrq($dst$$Register, $src$$Register);
9162 %}
9163
9164 ins_pipe(ialu_reg);
9165 %}
9166
9167 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9168 %{
9169 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9170 predicate(UseBMI1Instructions);
9171 effect(KILL cr);
9172
9173 ins_cost(125);
9174 format %{ "blsrq $dst, $src" %}
9175
9176 ins_encode %{
9177 __ blsrq($dst$$Register, $src$$Address);
9178 %}
9179
9180 ins_pipe(ialu_reg);
9181 %}
9182
9183 // Or Instructions
9184 // Or Register with Register
9185 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9186 %{
9187 match(Set dst (OrL dst src));
9188 effect(KILL cr);
9189
9190 format %{ "orq $dst, $src\t# long" %}
9191 opcode(0x0B);
9192 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9193 ins_pipe(ialu_reg_reg);
9194 %}
9195
9196 // Use any_RegP to match R15 (TLS register) without spilling.
9197 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9198 match(Set dst (OrL dst (CastP2X src)));
9199 effect(KILL cr);
9200
9201 format %{ "orq $dst, $src\t# long" %}
9202 opcode(0x0B);
9203 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9204 ins_pipe(ialu_reg_reg);
9205 %}
9206
9207
9208 // Or Register with Immediate
9209 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9210 %{
9211 match(Set dst (OrL dst src));
9212 effect(KILL cr);
9213
9214 format %{ "orq $dst, $src\t# long" %}
9215 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9216 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9217 ins_pipe(ialu_reg);
9218 %}
9219
9220 // Or Register with Memory
9221 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9222 %{
9223 match(Set dst (OrL dst (LoadL src)));
9224 effect(KILL cr);
9225
9226 ins_cost(125);
9227 format %{ "orq $dst, $src\t# long" %}
9228 opcode(0x0B);
9229 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9230 ins_pipe(ialu_reg_mem);
9231 %}
9232
9233 // Or Memory with Register
9234 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9235 %{
9236 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9237 effect(KILL cr);
9238
9239 ins_cost(150);
9240 format %{ "orq $dst, $src\t# long" %}
9241 opcode(0x09); /* Opcode 09 /r */
9242 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9243 ins_pipe(ialu_mem_reg);
9244 %}
9245
9246 // Or Memory with Immediate
9247 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9248 %{
9249 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9250 effect(KILL cr);
9251
9252 ins_cost(125);
9253 format %{ "orq $dst, $src\t# long" %}
9254 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9255 ins_encode(REX_mem_wide(dst), OpcSE(src),
9256 RM_opc_mem(secondary, dst), Con8or32(src));
9257 ins_pipe(ialu_mem_imm);
9258 %}
9259
9260 // Xor Instructions
9261 // Xor Register with Register
9262 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9263 %{
9264 match(Set dst (XorL dst src));
9265 effect(KILL cr);
9266
9267 format %{ "xorq $dst, $src\t# long" %}
9268 opcode(0x33);
9269 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9270 ins_pipe(ialu_reg_reg);
9271 %}
9272
9273 // Xor Register with Immediate -1
9274 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9275 match(Set dst (XorL dst imm));
9276
9277 format %{ "notq $dst" %}
9278 ins_encode %{
9279 __ notq($dst$$Register);
9280 %}
9281 ins_pipe(ialu_reg);
9282 %}
9283
9284 // Xor Register with Immediate
9285 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9286 %{
9287 match(Set dst (XorL dst src));
9288 effect(KILL cr);
9289
9290 format %{ "xorq $dst, $src\t# long" %}
9291 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9292 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9293 ins_pipe(ialu_reg);
9294 %}
9295
9296 // Xor Register with Memory
9297 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9298 %{
9299 match(Set dst (XorL dst (LoadL src)));
9300 effect(KILL cr);
9301
9302 ins_cost(125);
9303 format %{ "xorq $dst, $src\t# long" %}
9304 opcode(0x33);
9305 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9306 ins_pipe(ialu_reg_mem);
9307 %}
9308
9309 // Xor Memory with Register
9310 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9311 %{
9312 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9313 effect(KILL cr);
9314
9315 ins_cost(150);
9316 format %{ "xorq $dst, $src\t# long" %}
9317 opcode(0x31); /* Opcode 31 /r */
9318 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9319 ins_pipe(ialu_mem_reg);
9320 %}
9321
9322 // Xor Memory with Immediate
9323 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9324 %{
9325 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9326 effect(KILL cr);
9327
9328 ins_cost(125);
9329 format %{ "xorq $dst, $src\t# long" %}
9330 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9331 ins_encode(REX_mem_wide(dst), OpcSE(src),
9332 RM_opc_mem(secondary, dst), Con8or32(src));
9333 ins_pipe(ialu_mem_imm);
9334 %}
9335
9336 // Convert Int to Boolean
9337 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9338 %{
9339 match(Set dst (Conv2B src));
9340 effect(KILL cr);
9341
9342 format %{ "testl $src, $src\t# ci2b\n\t"
9343 "setnz $dst\n\t"
9344 "movzbl $dst, $dst" %}
9345 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9346 setNZ_reg(dst),
9347 REX_reg_breg(dst, dst), // movzbl
9348 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9349 ins_pipe(pipe_slow); // XXX
9350 %}
9351
9352 // Convert Pointer to Boolean
9353 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9354 %{
9355 match(Set dst (Conv2B src));
9356 effect(KILL cr);
9357
9358 format %{ "testq $src, $src\t# cp2b\n\t"
9359 "setnz $dst\n\t"
9360 "movzbl $dst, $dst" %}
9361 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9362 setNZ_reg(dst),
9363 REX_reg_breg(dst, dst), // movzbl
9364 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9365 ins_pipe(pipe_slow); // XXX
9366 %}
9367
9368 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9369 %{
9370 match(Set dst (CmpLTMask p q));
9371 effect(KILL cr);
9372
9373 ins_cost(400);
9374 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9375 "setlt $dst\n\t"
9376 "movzbl $dst, $dst\n\t"
9377 "negl $dst" %}
9378 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9379 setLT_reg(dst),
9380 REX_reg_breg(dst, dst), // movzbl
9381 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9382 neg_reg(dst));
9383 ins_pipe(pipe_slow);
9384 %}
9385
9386 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9387 %{
9388 match(Set dst (CmpLTMask dst zero));
9389 effect(KILL cr);
9390
9391 ins_cost(100);
9392 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9393 ins_encode %{
9394 __ sarl($dst$$Register, 31);
9395 %}
9396 ins_pipe(ialu_reg);
9397 %}
9398
9399 /* Better to save a register than avoid a branch */
9400 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9401 %{
9402 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9403 effect(KILL cr);
9404 ins_cost(300);
9405 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
9406 "jge done\n\t"
9407 "addl $p,$y\n"
9408 "done: " %}
9409 ins_encode %{
9410 Register Rp = $p$$Register;
9411 Register Rq = $q$$Register;
9412 Register Ry = $y$$Register;
9413 Label done;
9414 __ subl(Rp, Rq);
9415 __ jccb(Assembler::greaterEqual, done);
9416 __ addl(Rp, Ry);
9417 __ bind(done);
9418 %}
9419 ins_pipe(pipe_cmplt);
9420 %}
9421
9422 /* Better to save a register than avoid a branch */
9423 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9424 %{
9425 match(Set y (AndI (CmpLTMask p q) y));
9426 effect(KILL cr);
9427
9428 ins_cost(300);
9429
9430 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
9431 "jlt done\n\t"
9432 "xorl $y, $y\n"
9433 "done: " %}
9434 ins_encode %{
9435 Register Rp = $p$$Register;
9436 Register Rq = $q$$Register;
9437 Register Ry = $y$$Register;
9438 Label done;
9439 __ cmpl(Rp, Rq);
9440 __ jccb(Assembler::less, done);
9441 __ xorl(Ry, Ry);
9442 __ bind(done);
9443 %}
9444 ins_pipe(pipe_cmplt);
9445 %}
9446
9447
9448 //---------- FP Instructions------------------------------------------------
9449
9450 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9451 %{
9452 match(Set cr (CmpF src1 src2));
9453
9454 ins_cost(145);
9455 format %{ "ucomiss $src1, $src2\n\t"
9456 "jnp,s exit\n\t"
9457 "pushfq\t# saw NaN, set CF\n\t"
9458 "andq [rsp], #0xffffff2b\n\t"
9459 "popfq\n"
9460 "exit:" %}
9461 ins_encode %{
9462 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9463 emit_cmpfp_fixup(_masm);
9464 %}
9465 ins_pipe(pipe_slow);
9466 %}
9467
9468 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9469 match(Set cr (CmpF src1 src2));
9470
9471 ins_cost(100);
9472 format %{ "ucomiss $src1, $src2" %}
9473 ins_encode %{
9474 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9475 %}
9476 ins_pipe(pipe_slow);
9477 %}
9478
9479 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9480 %{
9481 match(Set cr (CmpF src1 (LoadF src2)));
9482
9483 ins_cost(145);
9484 format %{ "ucomiss $src1, $src2\n\t"
9485 "jnp,s exit\n\t"
9486 "pushfq\t# saw NaN, set CF\n\t"
9487 "andq [rsp], #0xffffff2b\n\t"
9488 "popfq\n"
9489 "exit:" %}
9490 ins_encode %{
9491 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9492 emit_cmpfp_fixup(_masm);
9493 %}
9494 ins_pipe(pipe_slow);
9495 %}
9496
9497 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9498 match(Set cr (CmpF src1 (LoadF src2)));
9499
9500 ins_cost(100);
9501 format %{ "ucomiss $src1, $src2" %}
9502 ins_encode %{
9503 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9504 %}
9505 ins_pipe(pipe_slow);
9506 %}
9507
9508 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9509 match(Set cr (CmpF src con));
9510
9511 ins_cost(145);
9512 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9513 "jnp,s exit\n\t"
9514 "pushfq\t# saw NaN, set CF\n\t"
9515 "andq [rsp], #0xffffff2b\n\t"
9516 "popfq\n"
9517 "exit:" %}
9518 ins_encode %{
9519 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9520 emit_cmpfp_fixup(_masm);
9521 %}
9522 ins_pipe(pipe_slow);
9523 %}
9524
9525 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9526 match(Set cr (CmpF src con));
9527 ins_cost(100);
9528 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9529 ins_encode %{
9530 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9531 %}
9532 ins_pipe(pipe_slow);
9533 %}
9534
9535 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9536 %{
9537 match(Set cr (CmpD src1 src2));
9538
9539 ins_cost(145);
9540 format %{ "ucomisd $src1, $src2\n\t"
9541 "jnp,s exit\n\t"
9542 "pushfq\t# saw NaN, set CF\n\t"
9543 "andq [rsp], #0xffffff2b\n\t"
9544 "popfq\n"
9545 "exit:" %}
9546 ins_encode %{
9547 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9548 emit_cmpfp_fixup(_masm);
9549 %}
9550 ins_pipe(pipe_slow);
9551 %}
9552
9553 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9554 match(Set cr (CmpD src1 src2));
9555
9556 ins_cost(100);
9557 format %{ "ucomisd $src1, $src2 test" %}
9558 ins_encode %{
9559 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9560 %}
9561 ins_pipe(pipe_slow);
9562 %}
9563
9564 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9565 %{
9566 match(Set cr (CmpD src1 (LoadD src2)));
9567
9568 ins_cost(145);
9569 format %{ "ucomisd $src1, $src2\n\t"
9570 "jnp,s exit\n\t"
9571 "pushfq\t# saw NaN, set CF\n\t"
9572 "andq [rsp], #0xffffff2b\n\t"
9573 "popfq\n"
9574 "exit:" %}
9575 ins_encode %{
9576 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9577 emit_cmpfp_fixup(_masm);
9578 %}
9579 ins_pipe(pipe_slow);
9580 %}
9581
9582 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9583 match(Set cr (CmpD src1 (LoadD src2)));
9584
9585 ins_cost(100);
9586 format %{ "ucomisd $src1, $src2" %}
9587 ins_encode %{
9588 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9589 %}
9590 ins_pipe(pipe_slow);
9591 %}
9592
9593 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9594 match(Set cr (CmpD src con));
9595
9596 ins_cost(145);
9597 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9598 "jnp,s exit\n\t"
9599 "pushfq\t# saw NaN, set CF\n\t"
9600 "andq [rsp], #0xffffff2b\n\t"
9601 "popfq\n"
9602 "exit:" %}
9603 ins_encode %{
9604 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9605 emit_cmpfp_fixup(_masm);
9606 %}
9607 ins_pipe(pipe_slow);
9608 %}
9609
9610 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9611 match(Set cr (CmpD src con));
9612 ins_cost(100);
9613 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9614 ins_encode %{
9615 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9616 %}
9617 ins_pipe(pipe_slow);
9618 %}
9619
9620 // Compare into -1,0,1
9621 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9622 %{
9623 match(Set dst (CmpF3 src1 src2));
9624 effect(KILL cr);
9625
9626 ins_cost(275);
9627 format %{ "ucomiss $src1, $src2\n\t"
9628 "movl $dst, #-1\n\t"
9629 "jp,s done\n\t"
9630 "jb,s done\n\t"
9631 "setne $dst\n\t"
9632 "movzbl $dst, $dst\n"
9633 "done:" %}
9634 ins_encode %{
9635 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9636 emit_cmpfp3(_masm, $dst$$Register);
9637 %}
9638 ins_pipe(pipe_slow);
9639 %}
9640
9641 // Compare into -1,0,1
9642 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9643 %{
9644 match(Set dst (CmpF3 src1 (LoadF src2)));
9645 effect(KILL cr);
9646
9647 ins_cost(275);
9648 format %{ "ucomiss $src1, $src2\n\t"
9649 "movl $dst, #-1\n\t"
9650 "jp,s done\n\t"
9651 "jb,s done\n\t"
9652 "setne $dst\n\t"
9653 "movzbl $dst, $dst\n"
9654 "done:" %}
9655 ins_encode %{
9656 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9657 emit_cmpfp3(_masm, $dst$$Register);
9658 %}
9659 ins_pipe(pipe_slow);
9660 %}
9661
9662 // Compare into -1,0,1
9663 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9664 match(Set dst (CmpF3 src con));
9665 effect(KILL cr);
9666
9667 ins_cost(275);
9668 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9669 "movl $dst, #-1\n\t"
9670 "jp,s done\n\t"
9671 "jb,s done\n\t"
9672 "setne $dst\n\t"
9673 "movzbl $dst, $dst\n"
9674 "done:" %}
9675 ins_encode %{
9676 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9677 emit_cmpfp3(_masm, $dst$$Register);
9678 %}
9679 ins_pipe(pipe_slow);
9680 %}
9681
9682 // Compare into -1,0,1
9683 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9684 %{
9685 match(Set dst (CmpD3 src1 src2));
9686 effect(KILL cr);
9687
9688 ins_cost(275);
9689 format %{ "ucomisd $src1, $src2\n\t"
9690 "movl $dst, #-1\n\t"
9691 "jp,s done\n\t"
9692 "jb,s done\n\t"
9693 "setne $dst\n\t"
9694 "movzbl $dst, $dst\n"
9695 "done:" %}
9696 ins_encode %{
9697 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9698 emit_cmpfp3(_masm, $dst$$Register);
9699 %}
9700 ins_pipe(pipe_slow);
9701 %}
9702
9703 // Compare into -1,0,1
9704 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
9705 %{
9706 match(Set dst (CmpD3 src1 (LoadD src2)));
9707 effect(KILL cr);
9708
9709 ins_cost(275);
9710 format %{ "ucomisd $src1, $src2\n\t"
9711 "movl $dst, #-1\n\t"
9712 "jp,s done\n\t"
9713 "jb,s done\n\t"
9714 "setne $dst\n\t"
9715 "movzbl $dst, $dst\n"
9716 "done:" %}
9717 ins_encode %{
9718 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9719 emit_cmpfp3(_masm, $dst$$Register);
9720 %}
9721 ins_pipe(pipe_slow);
9722 %}
9723
9724 // Compare into -1,0,1
9725 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
9726 match(Set dst (CmpD3 src con));
9727 effect(KILL cr);
9728
9729 ins_cost(275);
9730 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9731 "movl $dst, #-1\n\t"
9732 "jp,s done\n\t"
9733 "jb,s done\n\t"
9734 "setne $dst\n\t"
9735 "movzbl $dst, $dst\n"
9736 "done:" %}
9737 ins_encode %{
9738 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9739 emit_cmpfp3(_masm, $dst$$Register);
9740 %}
9741 ins_pipe(pipe_slow);
9742 %}
9743
9744 // -----------Trig and Trancendental Instructions------------------------------
9745 instruct cosD_reg(regD dst) %{
9746 match(Set dst (CosD dst));
9747
9748 format %{ "dcos $dst\n\t" %}
9749 opcode(0xD9, 0xFF);
9750 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9751 ins_pipe( pipe_slow );
9752 %}
9753
9754 instruct sinD_reg(regD dst) %{
9755 match(Set dst (SinD dst));
9756
9757 format %{ "dsin $dst\n\t" %}
9758 opcode(0xD9, 0xFE);
9759 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9760 ins_pipe( pipe_slow );
9761 %}
9762
9763 instruct tanD_reg(regD dst) %{
9764 match(Set dst (TanD dst));
9765
9766 format %{ "dtan $dst\n\t" %}
9767 ins_encode( Push_SrcXD(dst),
9768 Opcode(0xD9), Opcode(0xF2), //fptan
9769 Opcode(0xDD), Opcode(0xD8), //fstp st
9770 Push_ResultXD(dst) );
9771 ins_pipe( pipe_slow );
9772 %}
9773
9774 instruct log10D_reg(regD dst) %{
9775 // The source and result Double operands in XMM registers
9776 match(Set dst (Log10D dst));
9777 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9778 // fyl2x ; compute log_10(2) * log_2(x)
9779 format %{ "fldlg2\t\t\t#Log10\n\t"
9780 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
9781 %}
9782 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
9783 Push_SrcXD(dst),
9784 Opcode(0xD9), Opcode(0xF1), // fyl2x
9785 Push_ResultXD(dst));
9786
9787 ins_pipe( pipe_slow );
9788 %}
9789
9790 instruct logD_reg(regD dst) %{
9791 // The source and result Double operands in XMM registers
9792 match(Set dst (LogD dst));
9793 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9794 // fyl2x ; compute log_e(2) * log_2(x)
9795 format %{ "fldln2\t\t\t#Log_e\n\t"
9796 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
9797 %}
9798 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9799 Push_SrcXD(dst),
9800 Opcode(0xD9), Opcode(0xF1), // fyl2x
9801 Push_ResultXD(dst));
9802 ins_pipe( pipe_slow );
9803 %}
9804
9805 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9806 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9807 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9808 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9809 ins_encode %{
9810 __ subptr(rsp, 8);
9811 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9812 __ fld_d(Address(rsp, 0));
9813 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9814 __ fld_d(Address(rsp, 0));
9815 __ fast_pow();
9816 __ fstp_d(Address(rsp, 0));
9817 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9818 __ addptr(rsp, 8);
9819 %}
9820 ins_pipe( pipe_slow );
9821 %}
9822
9823 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9824 match(Set dst (ExpD src));
9825 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9826 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9827 ins_encode %{
9828 __ subptr(rsp, 8);
9829 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9830 __ fld_d(Address(rsp, 0));
9831 __ fast_exp();
9832 __ fstp_d(Address(rsp, 0));
9833 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9834 __ addptr(rsp, 8);
9835 %}
9836 ins_pipe( pipe_slow );
9837 %}
9838
9839 //----------Arithmetic Conversion Instructions---------------------------------
9840
9841 instruct roundFloat_nop(regF dst)
9842 %{
9843 match(Set dst (RoundFloat dst));
9844
9845 ins_cost(0);
9846 ins_encode();
9847 ins_pipe(empty);
9848 %}
9849
9850 instruct roundDouble_nop(regD dst)
9851 %{
9852 match(Set dst (RoundDouble dst));
9853
9854 ins_cost(0);
9855 ins_encode();
9856 ins_pipe(empty);
9857 %}
9858
9859 instruct convF2D_reg_reg(regD dst, regF src)
9860 %{
9861 match(Set dst (ConvF2D src));
9862
9863 format %{ "cvtss2sd $dst, $src" %}
9864 ins_encode %{
9865 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
9866 %}
9867 ins_pipe(pipe_slow); // XXX
9868 %}
9869
9870 instruct convF2D_reg_mem(regD dst, memory src)
9871 %{
9872 match(Set dst (ConvF2D (LoadF src)));
9873
9874 format %{ "cvtss2sd $dst, $src" %}
9875 ins_encode %{
9876 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
9877 %}
9878 ins_pipe(pipe_slow); // XXX
9879 %}
9880
9881 instruct convD2F_reg_reg(regF dst, regD src)
9882 %{
9883 match(Set dst (ConvD2F src));
9884
9885 format %{ "cvtsd2ss $dst, $src" %}
9886 ins_encode %{
9887 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
9888 %}
9889 ins_pipe(pipe_slow); // XXX
9890 %}
9891
9892 instruct convD2F_reg_mem(regF dst, memory src)
9893 %{
9894 match(Set dst (ConvD2F (LoadD src)));
9895
9896 format %{ "cvtsd2ss $dst, $src" %}
9897 ins_encode %{
9898 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
9899 %}
9900 ins_pipe(pipe_slow); // XXX
9901 %}
9902
9903 // XXX do mem variants
9904 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
9905 %{
9906 match(Set dst (ConvF2I src));
9907 effect(KILL cr);
9908
9909 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
9910 "cmpl $dst, #0x80000000\n\t"
9911 "jne,s done\n\t"
9912 "subq rsp, #8\n\t"
9913 "movss [rsp], $src\n\t"
9914 "call f2i_fixup\n\t"
9915 "popq $dst\n"
9916 "done: "%}
9917 ins_encode %{
9918 Label done;
9919 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
9920 __ cmpl($dst$$Register, 0x80000000);
9921 __ jccb(Assembler::notEqual, done);
9922 __ subptr(rsp, 8);
9923 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9924 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9925 __ pop($dst$$Register);
9926 __ bind(done);
9927 %}
9928 ins_pipe(pipe_slow);
9929 %}
9930
9931 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
9932 %{
9933 match(Set dst (ConvF2L src));
9934 effect(KILL cr);
9935
9936 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
9937 "cmpq $dst, [0x8000000000000000]\n\t"
9938 "jne,s done\n\t"
9939 "subq rsp, #8\n\t"
9940 "movss [rsp], $src\n\t"
9941 "call f2l_fixup\n\t"
9942 "popq $dst\n"
9943 "done: "%}
9944 ins_encode %{
9945 Label done;
9946 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
9947 __ cmp64($dst$$Register,
9948 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9949 __ jccb(Assembler::notEqual, done);
9950 __ subptr(rsp, 8);
9951 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9952 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
9953 __ pop($dst$$Register);
9954 __ bind(done);
9955 %}
9956 ins_pipe(pipe_slow);
9957 %}
9958
9959 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
9960 %{
9961 match(Set dst (ConvD2I src));
9962 effect(KILL cr);
9963
9964 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
9965 "cmpl $dst, #0x80000000\n\t"
9966 "jne,s done\n\t"
9967 "subq rsp, #8\n\t"
9968 "movsd [rsp], $src\n\t"
9969 "call d2i_fixup\n\t"
9970 "popq $dst\n"
9971 "done: "%}
9972 ins_encode %{
9973 Label done;
9974 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
9975 __ cmpl($dst$$Register, 0x80000000);
9976 __ jccb(Assembler::notEqual, done);
9977 __ subptr(rsp, 8);
9978 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9979 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
9980 __ pop($dst$$Register);
9981 __ bind(done);
9982 %}
9983 ins_pipe(pipe_slow);
9984 %}
9985
9986 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
9987 %{
9988 match(Set dst (ConvD2L src));
9989 effect(KILL cr);
9990
9991 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
9992 "cmpq $dst, [0x8000000000000000]\n\t"
9993 "jne,s done\n\t"
9994 "subq rsp, #8\n\t"
9995 "movsd [rsp], $src\n\t"
9996 "call d2l_fixup\n\t"
9997 "popq $dst\n"
9998 "done: "%}
9999 ins_encode %{
10000 Label done;
10001 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10002 __ cmp64($dst$$Register,
10003 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10004 __ jccb(Assembler::notEqual, done);
10005 __ subptr(rsp, 8);
10006 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10007 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10008 __ pop($dst$$Register);
10009 __ bind(done);
10010 %}
10011 ins_pipe(pipe_slow);
10012 %}
10013
10014 instruct convI2F_reg_reg(regF dst, rRegI src)
10015 %{
10016 predicate(!UseXmmI2F);
10017 match(Set dst (ConvI2F src));
10018
10019 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10020 ins_encode %{
10021 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10022 %}
10023 ins_pipe(pipe_slow); // XXX
10024 %}
10025
10026 instruct convI2F_reg_mem(regF dst, memory src)
10027 %{
10028 match(Set dst (ConvI2F (LoadI src)));
10029
10030 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10031 ins_encode %{
10032 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10033 %}
10034 ins_pipe(pipe_slow); // XXX
10035 %}
10036
10037 instruct convI2D_reg_reg(regD dst, rRegI src)
10038 %{
10039 predicate(!UseXmmI2D);
10040 match(Set dst (ConvI2D src));
10041
10042 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10043 ins_encode %{
10044 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10045 %}
10046 ins_pipe(pipe_slow); // XXX
10047 %}
10048
10049 instruct convI2D_reg_mem(regD dst, memory src)
10050 %{
10051 match(Set dst (ConvI2D (LoadI src)));
10052
10053 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10054 ins_encode %{
10055 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10056 %}
10057 ins_pipe(pipe_slow); // XXX
10058 %}
10059
10060 instruct convXI2F_reg(regF dst, rRegI src)
10061 %{
10062 predicate(UseXmmI2F);
10063 match(Set dst (ConvI2F src));
10064
10065 format %{ "movdl $dst, $src\n\t"
10066 "cvtdq2psl $dst, $dst\t# i2f" %}
10067 ins_encode %{
10068 __ movdl($dst$$XMMRegister, $src$$Register);
10069 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10070 %}
10071 ins_pipe(pipe_slow); // XXX
10072 %}
10073
10074 instruct convXI2D_reg(regD dst, rRegI src)
10075 %{
10076 predicate(UseXmmI2D);
10077 match(Set dst (ConvI2D src));
10078
10079 format %{ "movdl $dst, $src\n\t"
10080 "cvtdq2pdl $dst, $dst\t# i2d" %}
10081 ins_encode %{
10082 __ movdl($dst$$XMMRegister, $src$$Register);
10083 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10084 %}
10085 ins_pipe(pipe_slow); // XXX
10086 %}
10087
10088 instruct convL2F_reg_reg(regF dst, rRegL src)
10089 %{
10090 match(Set dst (ConvL2F src));
10091
10092 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10093 ins_encode %{
10094 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10095 %}
10096 ins_pipe(pipe_slow); // XXX
10097 %}
10098
10099 instruct convL2F_reg_mem(regF dst, memory src)
10100 %{
10101 match(Set dst (ConvL2F (LoadL src)));
10102
10103 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10104 ins_encode %{
10105 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10106 %}
10107 ins_pipe(pipe_slow); // XXX
10108 %}
10109
10110 instruct convL2D_reg_reg(regD dst, rRegL src)
10111 %{
10112 match(Set dst (ConvL2D src));
10113
10114 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10115 ins_encode %{
10116 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10117 %}
10118 ins_pipe(pipe_slow); // XXX
10119 %}
10120
10121 instruct convL2D_reg_mem(regD dst, memory src)
10122 %{
10123 match(Set dst (ConvL2D (LoadL src)));
10124
10125 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10126 ins_encode %{
10127 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10128 %}
10129 ins_pipe(pipe_slow); // XXX
10130 %}
10131
10132 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10133 %{
10134 match(Set dst (ConvI2L src));
10135
10136 ins_cost(125);
10137 format %{ "movslq $dst, $src\t# i2l" %}
10138 ins_encode %{
10139 __ movslq($dst$$Register, $src$$Register);
10140 %}
10141 ins_pipe(ialu_reg_reg);
10142 %}
10143
10144 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10145 // %{
10146 // match(Set dst (ConvI2L src));
10147 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10148 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10149 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10150 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10151 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10152 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10153
10154 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10155 // ins_encode(enc_copy(dst, src));
10156 // // opcode(0x63); // needs REX.W
10157 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10158 // ins_pipe(ialu_reg_reg);
10159 // %}
10160
10161 // Zero-extend convert int to long
10162 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10163 %{
10164 match(Set dst (AndL (ConvI2L src) mask));
10165
10166 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10167 ins_encode %{
10168 if ($dst$$reg != $src$$reg) {
10169 __ movl($dst$$Register, $src$$Register);
10170 }
10171 %}
10172 ins_pipe(ialu_reg_reg);
10173 %}
10174
10175 // Zero-extend convert int to long
10176 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10177 %{
10178 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10179
10180 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10181 ins_encode %{
10182 __ movl($dst$$Register, $src$$Address);
10183 %}
10184 ins_pipe(ialu_reg_mem);
10185 %}
10186
10187 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10188 %{
10189 match(Set dst (AndL src mask));
10190
10191 format %{ "movl $dst, $src\t# zero-extend long" %}
10192 ins_encode %{
10193 __ movl($dst$$Register, $src$$Register);
10194 %}
10195 ins_pipe(ialu_reg_reg);
10196 %}
10197
10198 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10199 %{
10200 match(Set dst (ConvL2I src));
10201
10202 format %{ "movl $dst, $src\t# l2i" %}
10203 ins_encode %{
10204 __ movl($dst$$Register, $src$$Register);
10205 %}
10206 ins_pipe(ialu_reg_reg);
10207 %}
10208
10209
10210 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10211 match(Set dst (MoveF2I src));
10212 effect(DEF dst, USE src);
10213
10214 ins_cost(125);
10215 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10216 ins_encode %{
10217 __ movl($dst$$Register, Address(rsp, $src$$disp));
10218 %}
10219 ins_pipe(ialu_reg_mem);
10220 %}
10221
10222 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10223 match(Set dst (MoveI2F src));
10224 effect(DEF dst, USE src);
10225
10226 ins_cost(125);
10227 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10228 ins_encode %{
10229 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10230 %}
10231 ins_pipe(pipe_slow);
10232 %}
10233
10234 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10235 match(Set dst (MoveD2L src));
10236 effect(DEF dst, USE src);
10237
10238 ins_cost(125);
10239 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10240 ins_encode %{
10241 __ movq($dst$$Register, Address(rsp, $src$$disp));
10242 %}
10243 ins_pipe(ialu_reg_mem);
10244 %}
10245
10246 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10247 predicate(!UseXmmLoadAndClearUpper);
10248 match(Set dst (MoveL2D src));
10249 effect(DEF dst, USE src);
10250
10251 ins_cost(125);
10252 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10253 ins_encode %{
10254 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10255 %}
10256 ins_pipe(pipe_slow);
10257 %}
10258
10259 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10260 predicate(UseXmmLoadAndClearUpper);
10261 match(Set dst (MoveL2D src));
10262 effect(DEF dst, USE src);
10263
10264 ins_cost(125);
10265 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10266 ins_encode %{
10267 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10268 %}
10269 ins_pipe(pipe_slow);
10270 %}
10271
10272
10273 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10274 match(Set dst (MoveF2I src));
10275 effect(DEF dst, USE src);
10276
10277 ins_cost(95); // XXX
10278 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10279 ins_encode %{
10280 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10281 %}
10282 ins_pipe(pipe_slow);
10283 %}
10284
10285 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10286 match(Set dst (MoveI2F src));
10287 effect(DEF dst, USE src);
10288
10289 ins_cost(100);
10290 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10291 ins_encode %{
10292 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10293 %}
10294 ins_pipe( ialu_mem_reg );
10295 %}
10296
10297 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10298 match(Set dst (MoveD2L src));
10299 effect(DEF dst, USE src);
10300
10301 ins_cost(95); // XXX
10302 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10303 ins_encode %{
10304 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10305 %}
10306 ins_pipe(pipe_slow);
10307 %}
10308
10309 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10310 match(Set dst (MoveL2D src));
10311 effect(DEF dst, USE src);
10312
10313 ins_cost(100);
10314 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10315 ins_encode %{
10316 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10317 %}
10318 ins_pipe(ialu_mem_reg);
10319 %}
10320
10321 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10322 match(Set dst (MoveF2I src));
10323 effect(DEF dst, USE src);
10324 ins_cost(85);
10325 format %{ "movd $dst,$src\t# MoveF2I" %}
10326 ins_encode %{
10327 __ movdl($dst$$Register, $src$$XMMRegister);
10328 %}
10329 ins_pipe( pipe_slow );
10330 %}
10331
10332 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10333 match(Set dst (MoveD2L src));
10334 effect(DEF dst, USE src);
10335 ins_cost(85);
10336 format %{ "movd $dst,$src\t# MoveD2L" %}
10337 ins_encode %{
10338 __ movdq($dst$$Register, $src$$XMMRegister);
10339 %}
10340 ins_pipe( pipe_slow );
10341 %}
10342
10343 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10344 match(Set dst (MoveI2F src));
10345 effect(DEF dst, USE src);
10346 ins_cost(100);
10347 format %{ "movd $dst,$src\t# MoveI2F" %}
10348 ins_encode %{
10349 __ movdl($dst$$XMMRegister, $src$$Register);
10350 %}
10351 ins_pipe( pipe_slow );
10352 %}
10353
10354 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10355 match(Set dst (MoveL2D src));
10356 effect(DEF dst, USE src);
10357 ins_cost(100);
10358 format %{ "movd $dst,$src\t# MoveL2D" %}
10359 ins_encode %{
10360 __ movdq($dst$$XMMRegister, $src$$Register);
10361 %}
10362 ins_pipe( pipe_slow );
10363 %}
10364
10365
10366 // =======================================================================
10367 // fast clearing of an array
10368 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10369 rFlagsReg cr)
10370 %{
10371 predicate(!UseFastStosb);
10372 match(Set dummy (ClearArray cnt base));
10373 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10374
10375 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10376 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
10377 ins_encode %{
10378 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10379 %}
10380 ins_pipe(pipe_slow);
10381 %}
10382
10383 instruct rep_fast_stosb(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10384 rFlagsReg cr)
10385 %{
10386 predicate(UseFastStosb);
10387 match(Set dummy (ClearArray cnt base));
10388 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10389 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10390 "shlq rcx,3\t# Convert doublewords to bytes\n\t"
10391 "rep stosb\t# Store rax to *rdi++ while rcx--" %}
10392 ins_encode %{
10393 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10394 %}
10395 ins_pipe( pipe_slow );
10396 %}
10397
10398 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10399 rax_RegI result, regD tmp1, rFlagsReg cr)
10400 %{
10401 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10402 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10403
10404 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10405 ins_encode %{
10406 __ string_compare($str1$$Register, $str2$$Register,
10407 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10408 $tmp1$$XMMRegister);
10409 %}
10410 ins_pipe( pipe_slow );
10411 %}
10412
10413 // fast search of substring with known size.
10414 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10415 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10416 %{
10417 predicate(UseSSE42Intrinsics);
10418 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10419 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10420
10421 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10422 ins_encode %{
10423 int icnt2 = (int)$int_cnt2$$constant;
10424 if (icnt2 >= 8) {
10425 // IndexOf for constant substrings with size >= 8 elements
10426 // which don't need to be loaded through stack.
10427 __ string_indexofC8($str1$$Register, $str2$$Register,
10428 $cnt1$$Register, $cnt2$$Register,
10429 icnt2, $result$$Register,
10430 $vec$$XMMRegister, $tmp$$Register);
10431 } else {
10432 // Small strings are loaded through stack if they cross page boundary.
10433 __ string_indexof($str1$$Register, $str2$$Register,
10434 $cnt1$$Register, $cnt2$$Register,
10435 icnt2, $result$$Register,
10436 $vec$$XMMRegister, $tmp$$Register);
10437 }
10438 %}
10439 ins_pipe( pipe_slow );
10440 %}
10441
10442 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10443 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10444 %{
10445 predicate(UseSSE42Intrinsics);
10446 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10447 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10448
10449 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10450 ins_encode %{
10451 __ string_indexof($str1$$Register, $str2$$Register,
10452 $cnt1$$Register, $cnt2$$Register,
10453 (-1), $result$$Register,
10454 $vec$$XMMRegister, $tmp$$Register);
10455 %}
10456 ins_pipe( pipe_slow );
10457 %}
10458
10459 // fast string equals
10460 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10461 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10462 %{
10463 match(Set result (StrEquals (Binary str1 str2) cnt));
10464 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10465
10466 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10467 ins_encode %{
10468 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
10469 $cnt$$Register, $result$$Register, $tmp3$$Register,
10470 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10471 %}
10472 ins_pipe( pipe_slow );
10473 %}
10474
10475 // fast array equals
10476 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10477 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10478 %{
10479 match(Set result (AryEq ary1 ary2));
10480 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10481 //ins_cost(300);
10482
10483 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10484 ins_encode %{
10485 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
10486 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10487 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10488 %}
10489 ins_pipe( pipe_slow );
10490 %}
10491
10492 // encode char[] to byte[] in ISO_8859_1
10493 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10494 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10495 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10496 match(Set result (EncodeISOArray src (Binary dst len)));
10497 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10498
10499 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10500 ins_encode %{
10501 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10502 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10503 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10504 %}
10505 ins_pipe( pipe_slow );
10506 %}
10507
10508 //----------Overflow Math Instructions-----------------------------------------
10509
10510 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10511 %{
10512 match(Set cr (OverflowAddI op1 op2));
10513 effect(DEF cr, USE_KILL op1, USE op2);
10514
10515 format %{ "addl $op1, $op2\t# overflow check int" %}
10516
10517 ins_encode %{
10518 __ addl($op1$$Register, $op2$$Register);
10519 %}
10520 ins_pipe(ialu_reg_reg);
10521 %}
10522
10523 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10524 %{
10525 match(Set cr (OverflowAddI op1 op2));
10526 effect(DEF cr, USE_KILL op1, USE op2);
10527
10528 format %{ "addl $op1, $op2\t# overflow check int" %}
10529
10530 ins_encode %{
10531 __ addl($op1$$Register, $op2$$constant);
10532 %}
10533 ins_pipe(ialu_reg_reg);
10534 %}
10535
10536 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10537 %{
10538 match(Set cr (OverflowAddL op1 op2));
10539 effect(DEF cr, USE_KILL op1, USE op2);
10540
10541 format %{ "addq $op1, $op2\t# overflow check long" %}
10542 ins_encode %{
10543 __ addq($op1$$Register, $op2$$Register);
10544 %}
10545 ins_pipe(ialu_reg_reg);
10546 %}
10547
10548 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
10549 %{
10550 match(Set cr (OverflowAddL op1 op2));
10551 effect(DEF cr, USE_KILL op1, USE op2);
10552
10553 format %{ "addq $op1, $op2\t# overflow check long" %}
10554 ins_encode %{
10555 __ addq($op1$$Register, $op2$$constant);
10556 %}
10557 ins_pipe(ialu_reg_reg);
10558 %}
10559
10560 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10561 %{
10562 match(Set cr (OverflowSubI op1 op2));
10563
10564 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10565 ins_encode %{
10566 __ cmpl($op1$$Register, $op2$$Register);
10567 %}
10568 ins_pipe(ialu_reg_reg);
10569 %}
10570
10571 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10572 %{
10573 match(Set cr (OverflowSubI op1 op2));
10574
10575 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10576 ins_encode %{
10577 __ cmpl($op1$$Register, $op2$$constant);
10578 %}
10579 ins_pipe(ialu_reg_reg);
10580 %}
10581
10582 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10583 %{
10584 match(Set cr (OverflowSubL op1 op2));
10585
10586 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10587 ins_encode %{
10588 __ cmpq($op1$$Register, $op2$$Register);
10589 %}
10590 ins_pipe(ialu_reg_reg);
10591 %}
10592
10593 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10594 %{
10595 match(Set cr (OverflowSubL op1 op2));
10596
10597 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10598 ins_encode %{
10599 __ cmpq($op1$$Register, $op2$$constant);
10600 %}
10601 ins_pipe(ialu_reg_reg);
10602 %}
10603
10604 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
10605 %{
10606 match(Set cr (OverflowSubI zero op2));
10607 effect(DEF cr, USE_KILL op2);
10608
10609 format %{ "negl $op2\t# overflow check int" %}
10610 ins_encode %{
10611 __ negl($op2$$Register);
10612 %}
10613 ins_pipe(ialu_reg_reg);
10614 %}
10615
10616 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
10617 %{
10618 match(Set cr (OverflowSubL zero op2));
10619 effect(DEF cr, USE_KILL op2);
10620
10621 format %{ "negq $op2\t# overflow check long" %}
10622 ins_encode %{
10623 __ negq($op2$$Register);
10624 %}
10625 ins_pipe(ialu_reg_reg);
10626 %}
10627
10628 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10629 %{
10630 match(Set cr (OverflowMulI op1 op2));
10631 effect(DEF cr, USE_KILL op1, USE op2);
10632
10633 format %{ "imull $op1, $op2\t# overflow check int" %}
10634 ins_encode %{
10635 __ imull($op1$$Register, $op2$$Register);
10636 %}
10637 ins_pipe(ialu_reg_reg_alu0);
10638 %}
10639
10640 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
10641 %{
10642 match(Set cr (OverflowMulI op1 op2));
10643 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10644
10645 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
10646 ins_encode %{
10647 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
10648 %}
10649 ins_pipe(ialu_reg_reg_alu0);
10650 %}
10651
10652 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10653 %{
10654 match(Set cr (OverflowMulL op1 op2));
10655 effect(DEF cr, USE_KILL op1, USE op2);
10656
10657 format %{ "imulq $op1, $op2\t# overflow check long" %}
10658 ins_encode %{
10659 __ imulq($op1$$Register, $op2$$Register);
10660 %}
10661 ins_pipe(ialu_reg_reg_alu0);
10662 %}
10663
10664 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
10665 %{
10666 match(Set cr (OverflowMulL op1 op2));
10667 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10668
10669 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
10670 ins_encode %{
10671 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
10672 %}
10673 ins_pipe(ialu_reg_reg_alu0);
10674 %}
10675
10676
10677 //----------Control Flow Instructions------------------------------------------
10678 // Signed compare Instructions
10679
10680 // XXX more variants!!
10681 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10682 %{
10683 match(Set cr (CmpI op1 op2));
10684 effect(DEF cr, USE op1, USE op2);
10685
10686 format %{ "cmpl $op1, $op2" %}
10687 opcode(0x3B); /* Opcode 3B /r */
10688 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10689 ins_pipe(ialu_cr_reg_reg);
10690 %}
10691
10692 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10693 %{
10694 match(Set cr (CmpI op1 op2));
10695
10696 format %{ "cmpl $op1, $op2" %}
10697 opcode(0x81, 0x07); /* Opcode 81 /7 */
10698 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10699 ins_pipe(ialu_cr_reg_imm);
10700 %}
10701
10702 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
10703 %{
10704 match(Set cr (CmpI op1 (LoadI op2)));
10705
10706 ins_cost(500); // XXX
10707 format %{ "cmpl $op1, $op2" %}
10708 opcode(0x3B); /* Opcode 3B /r */
10709 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10710 ins_pipe(ialu_cr_reg_mem);
10711 %}
10712
10713 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
10714 %{
10715 match(Set cr (CmpI src zero));
10716
10717 format %{ "testl $src, $src" %}
10718 opcode(0x85);
10719 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10720 ins_pipe(ialu_cr_reg_imm);
10721 %}
10722
10723 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
10724 %{
10725 match(Set cr (CmpI (AndI src con) zero));
10726
10727 format %{ "testl $src, $con" %}
10728 opcode(0xF7, 0x00);
10729 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
10730 ins_pipe(ialu_cr_reg_imm);
10731 %}
10732
10733 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
10734 %{
10735 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
10736
10737 format %{ "testl $src, $mem" %}
10738 opcode(0x85);
10739 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
10740 ins_pipe(ialu_cr_reg_mem);
10741 %}
10742
10743 // Unsigned compare Instructions; really, same as signed except they
10744 // produce an rFlagsRegU instead of rFlagsReg.
10745 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
10746 %{
10747 match(Set cr (CmpU op1 op2));
10748
10749 format %{ "cmpl $op1, $op2\t# unsigned" %}
10750 opcode(0x3B); /* Opcode 3B /r */
10751 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10752 ins_pipe(ialu_cr_reg_reg);
10753 %}
10754
10755 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
10756 %{
10757 match(Set cr (CmpU op1 op2));
10758
10759 format %{ "cmpl $op1, $op2\t# unsigned" %}
10760 opcode(0x81,0x07); /* Opcode 81 /7 */
10761 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10762 ins_pipe(ialu_cr_reg_imm);
10763 %}
10764
10765 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
10766 %{
10767 match(Set cr (CmpU op1 (LoadI op2)));
10768
10769 ins_cost(500); // XXX
10770 format %{ "cmpl $op1, $op2\t# unsigned" %}
10771 opcode(0x3B); /* Opcode 3B /r */
10772 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10773 ins_pipe(ialu_cr_reg_mem);
10774 %}
10775
10776 // // // Cisc-spilled version of cmpU_rReg
10777 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
10778 // //%{
10779 // // match(Set cr (CmpU (LoadI op1) op2));
10780 // //
10781 // // format %{ "CMPu $op1,$op2" %}
10782 // // ins_cost(500);
10783 // // opcode(0x39); /* Opcode 39 /r */
10784 // // ins_encode( OpcP, reg_mem( op1, op2) );
10785 // //%}
10786
10787 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
10788 %{
10789 match(Set cr (CmpU src zero));
10790
10791 format %{ "testl $src, $src\t# unsigned" %}
10792 opcode(0x85);
10793 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10794 ins_pipe(ialu_cr_reg_imm);
10795 %}
10796
10797 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
10798 %{
10799 match(Set cr (CmpP op1 op2));
10800
10801 format %{ "cmpq $op1, $op2\t# ptr" %}
10802 opcode(0x3B); /* Opcode 3B /r */
10803 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10804 ins_pipe(ialu_cr_reg_reg);
10805 %}
10806
10807 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
10808 %{
10809 match(Set cr (CmpP op1 (LoadP op2)));
10810
10811 ins_cost(500); // XXX
10812 format %{ "cmpq $op1, $op2\t# ptr" %}
10813 opcode(0x3B); /* Opcode 3B /r */
10814 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10815 ins_pipe(ialu_cr_reg_mem);
10816 %}
10817
10818 // // // Cisc-spilled version of cmpP_rReg
10819 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
10820 // //%{
10821 // // match(Set cr (CmpP (LoadP op1) op2));
10822 // //
10823 // // format %{ "CMPu $op1,$op2" %}
10824 // // ins_cost(500);
10825 // // opcode(0x39); /* Opcode 39 /r */
10826 // // ins_encode( OpcP, reg_mem( op1, op2) );
10827 // //%}
10828
10829 // XXX this is generalized by compP_rReg_mem???
10830 // Compare raw pointer (used in out-of-heap check).
10831 // Only works because non-oop pointers must be raw pointers
10832 // and raw pointers have no anti-dependencies.
10833 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
10834 %{
10835 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
10836 match(Set cr (CmpP op1 (LoadP op2)));
10837
10838 format %{ "cmpq $op1, $op2\t# raw ptr" %}
10839 opcode(0x3B); /* Opcode 3B /r */
10840 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10841 ins_pipe(ialu_cr_reg_mem);
10842 %}
10843
10844 // This will generate a signed flags result. This should be OK since
10845 // any compare to a zero should be eq/neq.
10846 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
10847 %{
10848 match(Set cr (CmpP src zero));
10849
10850 format %{ "testq $src, $src\t# ptr" %}
10851 opcode(0x85);
10852 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10853 ins_pipe(ialu_cr_reg_imm);
10854 %}
10855
10856 // This will generate a signed flags result. This should be OK since
10857 // any compare to a zero should be eq/neq.
10858 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
10859 %{
10860 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
10861 match(Set cr (CmpP (LoadP op) zero));
10862
10863 ins_cost(500); // XXX
10864 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
10865 opcode(0xF7); /* Opcode F7 /0 */
10866 ins_encode(REX_mem_wide(op),
10867 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
10868 ins_pipe(ialu_cr_reg_imm);
10869 %}
10870
10871 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
10872 %{
10873 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
10874 match(Set cr (CmpP (LoadP mem) zero));
10875
10876 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
10877 ins_encode %{
10878 __ cmpq(r12, $mem$$Address);
10879 %}
10880 ins_pipe(ialu_cr_reg_mem);
10881 %}
10882
10883 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
10884 %{
10885 match(Set cr (CmpN op1 op2));
10886
10887 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10888 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
10889 ins_pipe(ialu_cr_reg_reg);
10890 %}
10891
10892 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
10893 %{
10894 match(Set cr (CmpN src (LoadN mem)));
10895
10896 format %{ "cmpl $src, $mem\t# compressed ptr" %}
10897 ins_encode %{
10898 __ cmpl($src$$Register, $mem$$Address);
10899 %}
10900 ins_pipe(ialu_cr_reg_mem);
10901 %}
10902
10903 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
10904 match(Set cr (CmpN op1 op2));
10905
10906 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10907 ins_encode %{
10908 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
10909 %}
10910 ins_pipe(ialu_cr_reg_imm);
10911 %}
10912
10913 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
10914 %{
10915 match(Set cr (CmpN src (LoadN mem)));
10916
10917 format %{ "cmpl $mem, $src\t# compressed ptr" %}
10918 ins_encode %{
10919 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
10920 %}
10921 ins_pipe(ialu_cr_reg_mem);
10922 %}
10923
10924 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
10925 match(Set cr (CmpN op1 op2));
10926
10927 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
10928 ins_encode %{
10929 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
10930 %}
10931 ins_pipe(ialu_cr_reg_imm);
10932 %}
10933
10934 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
10935 %{
10936 match(Set cr (CmpN src (LoadNKlass mem)));
10937
10938 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
10939 ins_encode %{
10940 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
10941 %}
10942 ins_pipe(ialu_cr_reg_mem);
10943 %}
10944
10945 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
10946 match(Set cr (CmpN src zero));
10947
10948 format %{ "testl $src, $src\t# compressed ptr" %}
10949 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
10950 ins_pipe(ialu_cr_reg_imm);
10951 %}
10952
10953 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
10954 %{
10955 predicate(Universe::narrow_oop_base() != NULL);
10956 match(Set cr (CmpN (LoadN mem) zero));
10957
10958 ins_cost(500); // XXX
10959 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
10960 ins_encode %{
10961 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
10962 %}
10963 ins_pipe(ialu_cr_reg_mem);
10964 %}
10965
10966 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
10967 %{
10968 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
10969 match(Set cr (CmpN (LoadN mem) zero));
10970
10971 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
10972 ins_encode %{
10973 __ cmpl(r12, $mem$$Address);
10974 %}
10975 ins_pipe(ialu_cr_reg_mem);
10976 %}
10977
10978 // Yanked all unsigned pointer compare operations.
10979 // Pointer compares are done with CmpP which is already unsigned.
10980
10981 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10982 %{
10983 match(Set cr (CmpL op1 op2));
10984
10985 format %{ "cmpq $op1, $op2" %}
10986 opcode(0x3B); /* Opcode 3B /r */
10987 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10988 ins_pipe(ialu_cr_reg_reg);
10989 %}
10990
10991 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10992 %{
10993 match(Set cr (CmpL op1 op2));
10994
10995 format %{ "cmpq $op1, $op2" %}
10996 opcode(0x81, 0x07); /* Opcode 81 /7 */
10997 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
10998 ins_pipe(ialu_cr_reg_imm);
10999 %}
11000
11001 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11002 %{
11003 match(Set cr (CmpL op1 (LoadL op2)));
11004
11005 format %{ "cmpq $op1, $op2" %}
11006 opcode(0x3B); /* Opcode 3B /r */
11007 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11008 ins_pipe(ialu_cr_reg_mem);
11009 %}
11010
11011 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11012 %{
11013 match(Set cr (CmpL src zero));
11014
11015 format %{ "testq $src, $src" %}
11016 opcode(0x85);
11017 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11018 ins_pipe(ialu_cr_reg_imm);
11019 %}
11020
11021 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11022 %{
11023 match(Set cr (CmpL (AndL src con) zero));
11024
11025 format %{ "testq $src, $con\t# long" %}
11026 opcode(0xF7, 0x00);
11027 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11028 ins_pipe(ialu_cr_reg_imm);
11029 %}
11030
11031 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11032 %{
11033 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11034
11035 format %{ "testq $src, $mem" %}
11036 opcode(0x85);
11037 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11038 ins_pipe(ialu_cr_reg_mem);
11039 %}
11040
11041 // Manifest a CmpL result in an integer register. Very painful.
11042 // This is the test to avoid.
11043 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11044 %{
11045 match(Set dst (CmpL3 src1 src2));
11046 effect(KILL flags);
11047
11048 ins_cost(275); // XXX
11049 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11050 "movl $dst, -1\n\t"
11051 "jl,s done\n\t"
11052 "setne $dst\n\t"
11053 "movzbl $dst, $dst\n\t"
11054 "done:" %}
11055 ins_encode(cmpl3_flag(src1, src2, dst));
11056 ins_pipe(pipe_slow);
11057 %}
11058
11059 //----------Max and Min--------------------------------------------------------
11060 // Min Instructions
11061
11062 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11063 %{
11064 effect(USE_DEF dst, USE src, USE cr);
11065
11066 format %{ "cmovlgt $dst, $src\t# min" %}
11067 opcode(0x0F, 0x4F);
11068 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11069 ins_pipe(pipe_cmov_reg);
11070 %}
11071
11072
11073 instruct minI_rReg(rRegI dst, rRegI src)
11074 %{
11075 match(Set dst (MinI dst src));
11076
11077 ins_cost(200);
11078 expand %{
11079 rFlagsReg cr;
11080 compI_rReg(cr, dst, src);
11081 cmovI_reg_g(dst, src, cr);
11082 %}
11083 %}
11084
11085 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11086 %{
11087 effect(USE_DEF dst, USE src, USE cr);
11088
11089 format %{ "cmovllt $dst, $src\t# max" %}
11090 opcode(0x0F, 0x4C);
11091 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11092 ins_pipe(pipe_cmov_reg);
11093 %}
11094
11095
11096 instruct maxI_rReg(rRegI dst, rRegI src)
11097 %{
11098 match(Set dst (MaxI dst src));
11099
11100 ins_cost(200);
11101 expand %{
11102 rFlagsReg cr;
11103 compI_rReg(cr, dst, src);
11104 cmovI_reg_l(dst, src, cr);
11105 %}
11106 %}
11107
11108 // ============================================================================
11109 // Branch Instructions
11110
11111 // Jump Direct - Label defines a relative address from JMP+1
11112 instruct jmpDir(label labl)
11113 %{
11114 match(Goto);
11115 effect(USE labl);
11116
11117 ins_cost(300);
11118 format %{ "jmp $labl" %}
11119 size(5);
11120 ins_encode %{
11121 Label* L = $labl$$label;
11122 __ jmp(*L, false); // Always long jump
11123 %}
11124 ins_pipe(pipe_jmp);
11125 %}
11126
11127 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11128 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11129 %{
11130 match(If cop cr);
11131 effect(USE labl);
11132
11133 ins_cost(300);
11134 format %{ "j$cop $labl" %}
11135 size(6);
11136 ins_encode %{
11137 Label* L = $labl$$label;
11138 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11139 %}
11140 ins_pipe(pipe_jcc);
11141 %}
11142
11143 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11144 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11145 %{
11146 match(CountedLoopEnd cop cr);
11147 effect(USE labl);
11148
11149 ins_cost(300);
11150 format %{ "j$cop $labl\t# loop end" %}
11151 size(6);
11152 ins_encode %{
11153 Label* L = $labl$$label;
11154 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11155 %}
11156 ins_pipe(pipe_jcc);
11157 %}
11158
11159 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11160 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11161 match(CountedLoopEnd cop cmp);
11162 effect(USE labl);
11163
11164 ins_cost(300);
11165 format %{ "j$cop,u $labl\t# loop end" %}
11166 size(6);
11167 ins_encode %{
11168 Label* L = $labl$$label;
11169 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11170 %}
11171 ins_pipe(pipe_jcc);
11172 %}
11173
11174 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11175 match(CountedLoopEnd cop cmp);
11176 effect(USE labl);
11177
11178 ins_cost(200);
11179 format %{ "j$cop,u $labl\t# loop end" %}
11180 size(6);
11181 ins_encode %{
11182 Label* L = $labl$$label;
11183 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11184 %}
11185 ins_pipe(pipe_jcc);
11186 %}
11187
11188 // Jump Direct Conditional - using unsigned comparison
11189 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11190 match(If cop cmp);
11191 effect(USE labl);
11192
11193 ins_cost(300);
11194 format %{ "j$cop,u $labl" %}
11195 size(6);
11196 ins_encode %{
11197 Label* L = $labl$$label;
11198 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11199 %}
11200 ins_pipe(pipe_jcc);
11201 %}
11202
11203 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11204 match(If cop cmp);
11205 effect(USE labl);
11206
11207 ins_cost(200);
11208 format %{ "j$cop,u $labl" %}
11209 size(6);
11210 ins_encode %{
11211 Label* L = $labl$$label;
11212 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11213 %}
11214 ins_pipe(pipe_jcc);
11215 %}
11216
11217 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11218 match(If cop cmp);
11219 effect(USE labl);
11220
11221 ins_cost(200);
11222 format %{ $$template
11223 if ($cop$$cmpcode == Assembler::notEqual) {
11224 $$emit$$"jp,u $labl\n\t"
11225 $$emit$$"j$cop,u $labl"
11226 } else {
11227 $$emit$$"jp,u done\n\t"
11228 $$emit$$"j$cop,u $labl\n\t"
11229 $$emit$$"done:"
11230 }
11231 %}
11232 ins_encode %{
11233 Label* l = $labl$$label;
11234 if ($cop$$cmpcode == Assembler::notEqual) {
11235 __ jcc(Assembler::parity, *l, false);
11236 __ jcc(Assembler::notEqual, *l, false);
11237 } else if ($cop$$cmpcode == Assembler::equal) {
11238 Label done;
11239 __ jccb(Assembler::parity, done);
11240 __ jcc(Assembler::equal, *l, false);
11241 __ bind(done);
11242 } else {
11243 ShouldNotReachHere();
11244 }
11245 %}
11246 ins_pipe(pipe_jcc);
11247 %}
11248
11249 // ============================================================================
11250 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11251 // superklass array for an instance of the superklass. Set a hidden
11252 // internal cache on a hit (cache is checked with exposed code in
11253 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11254 // encoding ALSO sets flags.
11255
11256 instruct partialSubtypeCheck(rdi_RegP result,
11257 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11258 rFlagsReg cr)
11259 %{
11260 match(Set result (PartialSubtypeCheck sub super));
11261 effect(KILL rcx, KILL cr);
11262
11263 ins_cost(1100); // slightly larger than the next version
11264 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11265 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11266 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11267 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
11268 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
11269 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11270 "xorq $result, $result\t\t Hit: rdi zero\n\t"
11271 "miss:\t" %}
11272
11273 opcode(0x1); // Force a XOR of RDI
11274 ins_encode(enc_PartialSubtypeCheck());
11275 ins_pipe(pipe_slow);
11276 %}
11277
11278 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
11279 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11280 immP0 zero,
11281 rdi_RegP result)
11282 %{
11283 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11284 effect(KILL rcx, KILL result);
11285
11286 ins_cost(1000);
11287 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11288 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11289 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11290 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
11291 "jne,s miss\t\t# Missed: flags nz\n\t"
11292 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11293 "miss:\t" %}
11294
11295 opcode(0x0); // No need to XOR RDI
11296 ins_encode(enc_PartialSubtypeCheck());
11297 ins_pipe(pipe_slow);
11298 %}
11299
11300 // ============================================================================
11301 // Branch Instructions -- short offset versions
11302 //
11303 // These instructions are used to replace jumps of a long offset (the default
11304 // match) with jumps of a shorter offset. These instructions are all tagged
11305 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11306 // match rules in general matching. Instead, the ADLC generates a conversion
11307 // method in the MachNode which can be used to do in-place replacement of the
11308 // long variant with the shorter variant. The compiler will determine if a
11309 // branch can be taken by the is_short_branch_offset() predicate in the machine
11310 // specific code section of the file.
11311
11312 // Jump Direct - Label defines a relative address from JMP+1
11313 instruct jmpDir_short(label labl) %{
11314 match(Goto);
11315 effect(USE labl);
11316
11317 ins_cost(300);
11318 format %{ "jmp,s $labl" %}
11319 size(2);
11320 ins_encode %{
11321 Label* L = $labl$$label;
11322 __ jmpb(*L);
11323 %}
11324 ins_pipe(pipe_jmp);
11325 ins_short_branch(1);
11326 %}
11327
11328 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11329 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
11330 match(If cop cr);
11331 effect(USE labl);
11332
11333 ins_cost(300);
11334 format %{ "j$cop,s $labl" %}
11335 size(2);
11336 ins_encode %{
11337 Label* L = $labl$$label;
11338 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11339 %}
11340 ins_pipe(pipe_jcc);
11341 ins_short_branch(1);
11342 %}
11343
11344 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11345 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
11346 match(CountedLoopEnd cop cr);
11347 effect(USE labl);
11348
11349 ins_cost(300);
11350 format %{ "j$cop,s $labl\t# loop end" %}
11351 size(2);
11352 ins_encode %{
11353 Label* L = $labl$$label;
11354 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11355 %}
11356 ins_pipe(pipe_jcc);
11357 ins_short_branch(1);
11358 %}
11359
11360 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11361 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11362 match(CountedLoopEnd cop cmp);
11363 effect(USE labl);
11364
11365 ins_cost(300);
11366 format %{ "j$cop,us $labl\t# loop end" %}
11367 size(2);
11368 ins_encode %{
11369 Label* L = $labl$$label;
11370 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11371 %}
11372 ins_pipe(pipe_jcc);
11373 ins_short_branch(1);
11374 %}
11375
11376 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11377 match(CountedLoopEnd cop cmp);
11378 effect(USE labl);
11379
11380 ins_cost(300);
11381 format %{ "j$cop,us $labl\t# loop end" %}
11382 size(2);
11383 ins_encode %{
11384 Label* L = $labl$$label;
11385 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11386 %}
11387 ins_pipe(pipe_jcc);
11388 ins_short_branch(1);
11389 %}
11390
11391 // Jump Direct Conditional - using unsigned comparison
11392 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11393 match(If cop cmp);
11394 effect(USE labl);
11395
11396 ins_cost(300);
11397 format %{ "j$cop,us $labl" %}
11398 size(2);
11399 ins_encode %{
11400 Label* L = $labl$$label;
11401 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11402 %}
11403 ins_pipe(pipe_jcc);
11404 ins_short_branch(1);
11405 %}
11406
11407 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11408 match(If cop cmp);
11409 effect(USE labl);
11410
11411 ins_cost(300);
11412 format %{ "j$cop,us $labl" %}
11413 size(2);
11414 ins_encode %{
11415 Label* L = $labl$$label;
11416 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11417 %}
11418 ins_pipe(pipe_jcc);
11419 ins_short_branch(1);
11420 %}
11421
11422 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11423 match(If cop cmp);
11424 effect(USE labl);
11425
11426 ins_cost(300);
11427 format %{ $$template
11428 if ($cop$$cmpcode == Assembler::notEqual) {
11429 $$emit$$"jp,u,s $labl\n\t"
11430 $$emit$$"j$cop,u,s $labl"
11431 } else {
11432 $$emit$$"jp,u,s done\n\t"
11433 $$emit$$"j$cop,u,s $labl\n\t"
11434 $$emit$$"done:"
11435 }
11436 %}
11437 size(4);
11438 ins_encode %{
11439 Label* l = $labl$$label;
11440 if ($cop$$cmpcode == Assembler::notEqual) {
11441 __ jccb(Assembler::parity, *l);
11442 __ jccb(Assembler::notEqual, *l);
11443 } else if ($cop$$cmpcode == Assembler::equal) {
11444 Label done;
11445 __ jccb(Assembler::parity, done);
11446 __ jccb(Assembler::equal, *l);
11447 __ bind(done);
11448 } else {
11449 ShouldNotReachHere();
11450 }
11451 %}
11452 ins_pipe(pipe_jcc);
11453 ins_short_branch(1);
11454 %}
11455
11456 // ============================================================================
11457 // inlined locking and unlocking
11458
11459 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
11460 predicate(Compile::current()->use_rtm());
11461 match(Set cr (FastLock object box));
11462 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
11463 ins_cost(300);
11464 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
11465 ins_encode %{
11466 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
11467 $scr$$Register, $cx1$$Register, $cx2$$Register,
11468 _counters, _rtm_counters, _stack_rtm_counters,
11469 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
11470 true, ra_->C->profile_rtm());
11471 %}
11472 ins_pipe(pipe_slow);
11473 %}
11474
11475 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
11476 predicate(!Compile::current()->use_rtm());
11477 match(Set cr (FastLock object box));
11478 effect(TEMP tmp, TEMP scr, USE_KILL box);
11479 ins_cost(300);
11480 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
11481 ins_encode %{
11482 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
11483 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
11484 %}
11485 ins_pipe(pipe_slow);
11486 %}
11487
11488 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
11489 match(Set cr (FastUnlock object box));
11490 effect(TEMP tmp, USE_KILL box);
11491 ins_cost(300);
11492 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
11493 ins_encode %{
11494 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
11495 %}
11496 ins_pipe(pipe_slow);
11497 %}
11498
11499
11500 // ============================================================================
11501 // Safepoint Instructions
11502 instruct safePoint_poll(rFlagsReg cr)
11503 %{
11504 predicate(!Assembler::is_polling_page_far());
11505 match(SafePoint);
11506 effect(KILL cr);
11507
11508 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
11509 "# Safepoint: poll for GC" %}
11510 ins_cost(125);
11511 ins_encode %{
11512 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
11513 __ testl(rax, addr);
11514 %}
11515 ins_pipe(ialu_reg_mem);
11516 %}
11517
11518 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
11519 %{
11520 predicate(Assembler::is_polling_page_far());
11521 match(SafePoint poll);
11522 effect(KILL cr, USE poll);
11523
11524 format %{ "testl rax, [$poll]\t"
11525 "# Safepoint: poll for GC" %}
11526 ins_cost(125);
11527 ins_encode %{
11528 __ relocate(relocInfo::poll_type);
11529 __ testl(rax, Address($poll$$Register, 0));
11530 %}
11531 ins_pipe(ialu_reg_mem);
11532 %}
11533
11534 // ============================================================================
11535 // Procedure Call/Return Instructions
11536 // Call Java Static Instruction
11537 // Note: If this code changes, the corresponding ret_addr_offset() and
11538 // compute_padding() functions will have to be adjusted.
11539 instruct CallStaticJavaDirect(method meth) %{
11540 match(CallStaticJava);
11541 effect(USE meth);
11542
11543 ins_cost(300);
11544 format %{ "call,static " %}
11545 opcode(0xE8); /* E8 cd */
11546 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
11547 ins_pipe(pipe_slow);
11548 ins_alignment(4);
11549 %}
11550
11551 // Call Java Dynamic Instruction
11552 // Note: If this code changes, the corresponding ret_addr_offset() and
11553 // compute_padding() functions will have to be adjusted.
11554 instruct CallDynamicJavaDirect(method meth)
11555 %{
11556 match(CallDynamicJava);
11557 effect(USE meth);
11558
11559 ins_cost(300);
11560 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11561 "call,dynamic " %}
11562 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
11563 ins_pipe(pipe_slow);
11564 ins_alignment(4);
11565 %}
11566
11567 // Call Runtime Instruction
11568 instruct CallRuntimeDirect(method meth)
11569 %{
11570 match(CallRuntime);
11571 effect(USE meth);
11572
11573 ins_cost(300);
11574 format %{ "call,runtime " %}
11575 ins_encode(clear_avx, Java_To_Runtime(meth));
11576 ins_pipe(pipe_slow);
11577 %}
11578
11579 // Call runtime without safepoint
11580 instruct CallLeafDirect(method meth)
11581 %{
11582 match(CallLeaf);
11583 effect(USE meth);
11584
11585 ins_cost(300);
11586 format %{ "call_leaf,runtime " %}
11587 ins_encode(clear_avx, Java_To_Runtime(meth));
11588 ins_pipe(pipe_slow);
11589 %}
11590
11591 // Call runtime without safepoint
11592 instruct CallLeafNoFPDirect(method meth)
11593 %{
11594 match(CallLeafNoFP);
11595 effect(USE meth);
11596
11597 ins_cost(300);
11598 format %{ "call_leaf_nofp,runtime " %}
11599 ins_encode(Java_To_Runtime(meth));
11600 ins_pipe(pipe_slow);
11601 %}
11602
11603 // Return Instruction
11604 // Remove the return address & jump to it.
11605 // Notice: We always emit a nop after a ret to make sure there is room
11606 // for safepoint patching
11607 instruct Ret()
11608 %{
11609 match(Return);
11610
11611 format %{ "ret" %}
11612 opcode(0xC3);
11613 ins_encode(OpcP);
11614 ins_pipe(pipe_jmp);
11615 %}
11616
11617 // Tail Call; Jump from runtime stub to Java code.
11618 // Also known as an 'interprocedural jump'.
11619 // Target of jump will eventually return to caller.
11620 // TailJump below removes the return address.
11621 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
11622 %{
11623 match(TailCall jump_target method_oop);
11624
11625 ins_cost(300);
11626 format %{ "jmp $jump_target\t# rbx holds method oop" %}
11627 opcode(0xFF, 0x4); /* Opcode FF /4 */
11628 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
11629 ins_pipe(pipe_jmp);
11630 %}
11631
11632 // Tail Jump; remove the return address; jump to target.
11633 // TailCall above leaves the return address around.
11634 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
11635 %{
11636 match(TailJump jump_target ex_oop);
11637
11638 ins_cost(300);
11639 format %{ "popq rdx\t# pop return address\n\t"
11640 "jmp $jump_target" %}
11641 opcode(0xFF, 0x4); /* Opcode FF /4 */
11642 ins_encode(Opcode(0x5a), // popq rdx
11643 REX_reg(jump_target), OpcP, reg_opc(jump_target));
11644 ins_pipe(pipe_jmp);
11645 %}
11646
11647 // Create exception oop: created by stack-crawling runtime code.
11648 // Created exception is now available to this handler, and is setup
11649 // just prior to jumping to this handler. No code emitted.
11650 instruct CreateException(rax_RegP ex_oop)
11651 %{
11652 match(Set ex_oop (CreateEx));
11653
11654 size(0);
11655 // use the following format syntax
11656 format %{ "# exception oop is in rax; no code emitted" %}
11657 ins_encode();
11658 ins_pipe(empty);
11659 %}
11660
11661 // Rethrow exception:
11662 // The exception oop will come in the first argument position.
11663 // Then JUMP (not call) to the rethrow stub code.
11664 instruct RethrowException()
11665 %{
11666 match(Rethrow);
11667
11668 // use the following format syntax
11669 format %{ "jmp rethrow_stub" %}
11670 ins_encode(enc_rethrow);
11671 ins_pipe(pipe_jmp);
11672 %}
11673
11674
11675 // ============================================================================
11676 // This name is KNOWN by the ADLC and cannot be changed.
11677 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11678 // for this guy.
11679 instruct tlsLoadP(r15_RegP dst) %{
11680 match(Set dst (ThreadLocal));
11681 effect(DEF dst);
11682
11683 size(0);
11684 format %{ "# TLS is in R15" %}
11685 ins_encode( /*empty encoding*/ );
11686 ins_pipe(ialu_reg_reg);
11687 %}
11688
11689
11690 //----------PEEPHOLE RULES-----------------------------------------------------
11691 // These must follow all instruction definitions as they use the names
11692 // defined in the instructions definitions.
11693 //
11694 // peepmatch ( root_instr_name [preceding_instruction]* );
11695 //
11696 // peepconstraint %{
11697 // (instruction_number.operand_name relational_op instruction_number.operand_name
11698 // [, ...] );
11699 // // instruction numbers are zero-based using left to right order in peepmatch
11700 //
11701 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11702 // // provide an instruction_number.operand_name for each operand that appears
11703 // // in the replacement instruction's match rule
11704 //
11705 // ---------VM FLAGS---------------------------------------------------------
11706 //
11707 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11708 //
11709 // Each peephole rule is given an identifying number starting with zero and
11710 // increasing by one in the order seen by the parser. An individual peephole
11711 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11712 // on the command-line.
11713 //
11714 // ---------CURRENT LIMITATIONS----------------------------------------------
11715 //
11716 // Only match adjacent instructions in same basic block
11717 // Only equality constraints
11718 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11719 // Only one replacement instruction
11720 //
11721 // ---------EXAMPLE----------------------------------------------------------
11722 //
11723 // // pertinent parts of existing instructions in architecture description
11724 // instruct movI(rRegI dst, rRegI src)
11725 // %{
11726 // match(Set dst (CopyI src));
11727 // %}
11728 //
11729 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
11730 // %{
11731 // match(Set dst (AddI dst src));
11732 // effect(KILL cr);
11733 // %}
11734 //
11735 // // Change (inc mov) to lea
11736 // peephole %{
11737 // // increment preceeded by register-register move
11738 // peepmatch ( incI_rReg movI );
11739 // // require that the destination register of the increment
11740 // // match the destination register of the move
11741 // peepconstraint ( 0.dst == 1.dst );
11742 // // construct a replacement instruction that sets
11743 // // the destination to ( move's source register + one )
11744 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
11745 // %}
11746 //
11747
11748 // Implementation no longer uses movX instructions since
11749 // machine-independent system no longer uses CopyX nodes.
11750 //
11751 // peephole
11752 // %{
11753 // peepmatch (incI_rReg movI);
11754 // peepconstraint (0.dst == 1.dst);
11755 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11756 // %}
11757
11758 // peephole
11759 // %{
11760 // peepmatch (decI_rReg movI);
11761 // peepconstraint (0.dst == 1.dst);
11762 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11763 // %}
11764
11765 // peephole
11766 // %{
11767 // peepmatch (addI_rReg_imm movI);
11768 // peepconstraint (0.dst == 1.dst);
11769 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11770 // %}
11771
11772 // peephole
11773 // %{
11774 // peepmatch (incL_rReg movL);
11775 // peepconstraint (0.dst == 1.dst);
11776 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11777 // %}
11778
11779 // peephole
11780 // %{
11781 // peepmatch (decL_rReg movL);
11782 // peepconstraint (0.dst == 1.dst);
11783 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11784 // %}
11785
11786 // peephole
11787 // %{
11788 // peepmatch (addL_rReg_imm movL);
11789 // peepconstraint (0.dst == 1.dst);
11790 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11791 // %}
11792
11793 // peephole
11794 // %{
11795 // peepmatch (addP_rReg_imm movP);
11796 // peepconstraint (0.dst == 1.dst);
11797 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
11798 // %}
11799
11800 // // Change load of spilled value to only a spill
11801 // instruct storeI(memory mem, rRegI src)
11802 // %{
11803 // match(Set mem (StoreI mem src));
11804 // %}
11805 //
11806 // instruct loadI(rRegI dst, memory mem)
11807 // %{
11808 // match(Set dst (LoadI mem));
11809 // %}
11810 //
11811
11812 peephole
11813 %{
11814 peepmatch (loadI storeI);
11815 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11816 peepreplace (storeI(1.mem 1.mem 1.src));
11817 %}
11818
11819 peephole
11820 %{
11821 peepmatch (loadL storeL);
11822 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11823 peepreplace (storeL(1.mem 1.mem 1.src));
11824 %}
11825
11826 //----------SMARTSPILL RULES---------------------------------------------------
11827 // These must follow all instruction definitions as they use the names
11828 // defined in the instructions definitions.