src/cpu/x86/vm/x86_64.ad

rev 8344 : 8076276: Add support for AVX512
Reviewed-by: kvn, roland
Contributed-by: michael.c.berg@intel.com

*** 534,544 ****
--- 534,548 ----
  #define   RELOC_DISP32   Assembler::disp32_operand
  
  #define __ _masm.
  
  static int clear_avx_size() {
+   if(UseAVX > 2) {
+     return 0; // vzeroupper is ignored
+   } else {
      return (Compile::current()->max_vector_size() > 16) ? 3 : 0;  // vzeroupper
+   }
  }
  
  // !!!!! Special hack to get all types of calls to specify the byte offset
  //       from the start of the call to the point where the return address
  //       will point.
*** 1068,1077 ****
--- 1072,1086 ----
      case Op_VecY:
        __ vmovdqu(Address(rsp, -32), xmm0);
        __ vmovdqu(xmm0, Address(rsp, src_offset));
        __ vmovdqu(Address(rsp, dst_offset), xmm0);
        __ vmovdqu(xmm0, Address(rsp, -32));
+     case Op_VecZ:
+       __ evmovdqu(Address(rsp, -64), xmm0, 2);
+       __ evmovdqu(xmm0, Address(rsp, src_offset), 2);
+       __ evmovdqu(Address(rsp, dst_offset), xmm0, 2);
+       __ evmovdqu(xmm0, Address(rsp, -64), 2);
        break;
      default:
        ShouldNotReachHere();
      }
  #ifndef PRODUCT
*** 1101,1110 ****
--- 1110,1126 ----
                  "vmovdqu xmm0, [rsp + #%d]\n\t"
                  "vmovdqu [rsp + #%d], xmm0\n\t"
                  "vmovdqu xmm0, [rsp - #32]",
                  src_offset, dst_offset);
        break;
+     case Op_VecZ:
+       st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
+                 "vmovdqu xmm0, [rsp + #%d]\n\t"
+                 "vmovdqu [rsp + #%d], xmm0\n\t"
+                 "vmovdqu xmm0, [rsp - #64]",
+                 src_offset, dst_offset);
+       break;
      default:
        ShouldNotReachHere();
      }
  #endif
    }
*** 1134,1144 ****
      return 0;
    }
    if (bottom_type()->isa_vect() != NULL) {
      uint ireg = ideal_reg();
      assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
!     assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
      if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
        // mem -> mem
        int src_offset = ra_->reg2offset(src_first);
        int dst_offset = ra_->reg2offset(dst_first);
        vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
--- 1150,1160 ----
      return 0;
    }
    if (bottom_type()->isa_vect() != NULL) {
      uint ireg = ideal_reg();
      assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
!     assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
      if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
        // mem -> mem
        int src_offset = ra_->reg2offset(src_first);
        int dst_offset = ra_->reg2offset(dst_first);
        vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
*** 2830,2840 ****
        OptoReg::Bad, // Op_RegF
        XMM0b_num,    // Op_RegD
        RAX_H_num     // Op_RegL
      };
      // Excluded flags and vector registers.
!     assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type");
      return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
    %}
  %}
  
  //----------ATTRIBUTES---------------------------------------------------------
--- 2846,2856 ----
        OptoReg::Bad, // Op_RegF
        XMM0b_num,    // Op_RegD
        RAX_H_num     // Op_RegL
      };
      // Excluded flags and vector registers.
!     assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
      return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
    %}
  %}
  
  //----------ATTRIBUTES---------------------------------------------------------
*** 3587,3615 ****
    format %{ "RFLAGS_U_CF" %}
    interface(REG_INTER);
  %}
  
  // Float register operands
! operand regF()
! %{
    constraint(ALLOC_IN_RC(float_reg));
    match(RegF);
  
    format %{ %}
    interface(REG_INTER);
  %}
  
  // Double register operands
! operand regD()
! %{
    constraint(ALLOC_IN_RC(double_reg));
    match(RegD);
  
    format %{ %}
    interface(REG_INTER);
  %}
  
  //----------Memory Operands----------------------------------------------------
  // Direct Memory Operand
  // operand direct(immP addr)
  // %{
  //   match(addr);
--- 3603,3662 ----
    format %{ "RFLAGS_U_CF" %}
    interface(REG_INTER);
  %}
  
  // Float register operands
! operand regF() %{
     constraint(ALLOC_IN_RC(float_reg));
     match(RegF);
  
     format %{ %}
     interface(REG_INTER);
  %}
  
  // Double register operands
! operand regD() %{
     constraint(ALLOC_IN_RC(double_reg));
     match(RegD);
  
     format %{ %}
     interface(REG_INTER);
  %}
  
+ // Vectors
+ operand vecS() %{
+   constraint(ALLOC_IN_RC(vectors_reg));
+   match(VecS);
+ 
+   format %{ %}
+   interface(REG_INTER);
+ %}
+ 
+ operand vecD() %{
+   constraint(ALLOC_IN_RC(vectord_reg));
+   match(VecD);
+ 
+   format %{ %}
+   interface(REG_INTER);
+ %}
+ 
+ operand vecX() %{
+   constraint(ALLOC_IN_RC(vectorx_reg));
+   match(VecX);
+ 
+   format %{ %}
+   interface(REG_INTER);
+ %}
+ 
+ operand vecY() %{
+   constraint(ALLOC_IN_RC(vectory_reg));
+   match(VecY);
+ 
+   format %{ %}
+   interface(REG_INTER);
+ %}
+ 
  //----------Memory Operands----------------------------------------------------
  // Direct Memory Operand
  // operand direct(immP addr)
  // %{
  //   match(addr);