1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
27
28 #include "asm/register.hpp"
29 #include "vm_version_x86.hpp"
30
31 class BiasedLockingCounters;
32
33 // Contains all the definitions needed for x86 assembly code generation.
34
35 // Calling convention
36 class Argument VALUE_OBJ_CLASS_SPEC {
37 public:
38 enum {
39 #ifdef _LP64
40 #ifdef _WIN64
41 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
42 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
43 #else
44 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
45 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
46 #endif // _WIN64
47 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
48 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
49 #else
50 n_register_parameters = 0 // 0 registers used to pass arguments
51 #endif // _LP64
52 };
53 };
54
55
56 #ifdef _LP64
57 // Symbolically name the register arguments used by the c calling convention.
58 // Windows is different from linux/solaris. So much for standards...
59
60 #ifdef _WIN64
61
62 REGISTER_DECLARATION(Register, c_rarg0, rcx);
63 REGISTER_DECLARATION(Register, c_rarg1, rdx);
64 REGISTER_DECLARATION(Register, c_rarg2, r8);
65 REGISTER_DECLARATION(Register, c_rarg3, r9);
66
67 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
68 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
69 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
70 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
71
72 #else
73
74 REGISTER_DECLARATION(Register, c_rarg0, rdi);
75 REGISTER_DECLARATION(Register, c_rarg1, rsi);
76 REGISTER_DECLARATION(Register, c_rarg2, rdx);
77 REGISTER_DECLARATION(Register, c_rarg3, rcx);
78 REGISTER_DECLARATION(Register, c_rarg4, r8);
79 REGISTER_DECLARATION(Register, c_rarg5, r9);
80
81 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
82 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
83 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
84 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
85 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
86 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
87 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
88 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
89
90 #endif // _WIN64
91
92 // Symbolically name the register arguments used by the Java calling convention.
93 // We have control over the convention for java so we can do what we please.
94 // What pleases us is to offset the java calling convention so that when
95 // we call a suitable jni method the arguments are lined up and we don't
96 // have to do little shuffling. A suitable jni method is non-static and a
97 // small number of arguments (two fewer args on windows)
98 //
99 // |-------------------------------------------------------|
100 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
101 // |-------------------------------------------------------|
102 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
103 // | rdi rsi rdx rcx r8 r9 | solaris/linux
104 // |-------------------------------------------------------|
105 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
106 // |-------------------------------------------------------|
107
108 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
109 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
110 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
111 // Windows runs out of register args here
112 #ifdef _WIN64
113 REGISTER_DECLARATION(Register, j_rarg3, rdi);
114 REGISTER_DECLARATION(Register, j_rarg4, rsi);
115 #else
116 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
117 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
118 #endif /* _WIN64 */
119 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
120
121 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
122 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
123 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
124 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
125 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
126 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
127 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
128 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
129
130 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
131 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
132
133 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
134 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
135
136 #else
137 // rscratch1 will apear in 32bit code that is dead but of course must compile
138 // Using noreg ensures if the dead code is incorrectly live and executed it
139 // will cause an assertion failure
140 #define rscratch1 noreg
141 #define rscratch2 noreg
142
143 #endif // _LP64
144
145 // JSR 292 fixed register usages:
146 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp);
147
148 // Address is an abstraction used to represent a memory location
149 // using any of the amd64 addressing modes with one object.
150 //
151 // Note: A register location is represented via a Register, not
152 // via an address for efficiency & simplicity reasons.
153
154 class ArrayAddress;
155
156 class Address VALUE_OBJ_CLASS_SPEC {
157 public:
158 enum ScaleFactor {
159 no_scale = -1,
160 times_1 = 0,
161 times_2 = 1,
162 times_4 = 2,
163 times_8 = 3,
164 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
165 };
166 static ScaleFactor times(int size) {
167 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
168 if (size == 8) return times_8;
169 if (size == 4) return times_4;
170 if (size == 2) return times_2;
171 return times_1;
172 }
173 static int scale_size(ScaleFactor scale) {
174 assert(scale != no_scale, "");
175 assert(((1 << (int)times_1) == 1 &&
176 (1 << (int)times_2) == 2 &&
177 (1 << (int)times_4) == 4 &&
178 (1 << (int)times_8) == 8), "");
179 return (1 << (int)scale);
180 }
181
182 private:
183 Register _base;
184 Register _index;
185 ScaleFactor _scale;
186 int _disp;
187 RelocationHolder _rspec;
188
189 // Easily misused constructors make them private
190 // %%% can we make these go away?
191 NOT_LP64(Address(address loc, RelocationHolder spec);)
192 Address(int disp, address loc, relocInfo::relocType rtype);
193 Address(int disp, address loc, RelocationHolder spec);
194
195 public:
196
197 int disp() { return _disp; }
198 // creation
199 Address()
200 : _base(noreg),
201 _index(noreg),
202 _scale(no_scale),
203 _disp(0) {
204 }
205
206 // No default displacement otherwise Register can be implicitly
207 // converted to 0(Register) which is quite a different animal.
208
209 Address(Register base, int disp)
210 : _base(base),
211 _index(noreg),
212 _scale(no_scale),
213 _disp(disp) {
214 }
215
216 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
217 : _base (base),
218 _index(index),
219 _scale(scale),
220 _disp (disp) {
221 assert(!index->is_valid() == (scale == Address::no_scale),
222 "inconsistent address");
223 }
224
225 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
226 : _base (base),
227 _index(index.register_or_noreg()),
228 _scale(scale),
229 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
230 if (!index.is_register()) scale = Address::no_scale;
231 assert(!_index->is_valid() == (scale == Address::no_scale),
232 "inconsistent address");
233 }
234
235 Address plus_disp(int disp) const {
236 Address a = (*this);
237 a._disp += disp;
238 return a;
239 }
240 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
241 Address a = (*this);
242 a._disp += disp.constant_or_zero() * scale_size(scale);
243 if (disp.is_register()) {
244 assert(!a.index()->is_valid(), "competing indexes");
245 a._index = disp.as_register();
246 a._scale = scale;
247 }
248 return a;
249 }
250 bool is_same_address(Address a) const {
251 // disregard _rspec
252 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
253 }
254
255 // The following two overloads are used in connection with the
256 // ByteSize type (see sizes.hpp). They simplify the use of
257 // ByteSize'd arguments in assembly code. Note that their equivalent
258 // for the optimized build are the member functions with int disp
259 // argument since ByteSize is mapped to an int type in that case.
260 //
261 // Note: DO NOT introduce similar overloaded functions for WordSize
262 // arguments as in the optimized mode, both ByteSize and WordSize
263 // are mapped to the same type and thus the compiler cannot make a
264 // distinction anymore (=> compiler errors).
265
266 #ifdef ASSERT
267 Address(Register base, ByteSize disp)
268 : _base(base),
269 _index(noreg),
270 _scale(no_scale),
271 _disp(in_bytes(disp)) {
272 }
273
274 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
275 : _base(base),
276 _index(index),
277 _scale(scale),
278 _disp(in_bytes(disp)) {
279 assert(!index->is_valid() == (scale == Address::no_scale),
280 "inconsistent address");
281 }
282
283 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
284 : _base (base),
285 _index(index.register_or_noreg()),
286 _scale(scale),
287 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
288 if (!index.is_register()) scale = Address::no_scale;
289 assert(!_index->is_valid() == (scale == Address::no_scale),
290 "inconsistent address");
291 }
292
293 #endif // ASSERT
294
295 // accessors
296 bool uses(Register reg) const { return _base == reg || _index == reg; }
297 Register base() const { return _base; }
298 Register index() const { return _index; }
299 ScaleFactor scale() const { return _scale; }
300 int disp() const { return _disp; }
301
302 // Convert the raw encoding form into the form expected by the constructor for
303 // Address. An index of 4 (rsp) corresponds to having no index, so convert
304 // that to noreg for the Address constructor.
305 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
306
307 static Address make_array(ArrayAddress);
308
309 private:
310 bool base_needs_rex() const {
311 return _base != noreg && _base->encoding() >= 8;
312 }
313
314 bool index_needs_rex() const {
315 return _index != noreg &&_index->encoding() >= 8;
316 }
317
318 relocInfo::relocType reloc() const { return _rspec.type(); }
319
320 friend class Assembler;
321 friend class MacroAssembler;
322 friend class LIR_Assembler; // base/index/scale/disp
323 };
324
325 //
326 // AddressLiteral has been split out from Address because operands of this type
327 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
328 // the few instructions that need to deal with address literals are unique and the
329 // MacroAssembler does not have to implement every instruction in the Assembler
330 // in order to search for address literals that may need special handling depending
331 // on the instruction and the platform. As small step on the way to merging i486/amd64
332 // directories.
333 //
334 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
335 friend class ArrayAddress;
336 RelocationHolder _rspec;
337 // Typically we use AddressLiterals we want to use their rval
338 // However in some situations we want the lval (effect address) of the item.
339 // We provide a special factory for making those lvals.
340 bool _is_lval;
341
342 // If the target is far we'll need to load the ea of this to
343 // a register to reach it. Otherwise if near we can do rip
344 // relative addressing.
345
346 address _target;
347
348 protected:
349 // creation
350 AddressLiteral()
351 : _is_lval(false),
352 _target(NULL)
353 {}
354
355 public:
356
357
358 AddressLiteral(address target, relocInfo::relocType rtype);
359
360 AddressLiteral(address target, RelocationHolder const& rspec)
361 : _rspec(rspec),
362 _is_lval(false),
363 _target(target)
364 {}
365
366 AddressLiteral addr() {
367 AddressLiteral ret = *this;
368 ret._is_lval = true;
369 return ret;
370 }
371
372
373 private:
374
375 address target() { return _target; }
376 bool is_lval() { return _is_lval; }
377
378 relocInfo::relocType reloc() const { return _rspec.type(); }
379 const RelocationHolder& rspec() const { return _rspec; }
380
381 friend class Assembler;
382 friend class MacroAssembler;
383 friend class Address;
384 friend class LIR_Assembler;
385 };
386
387 // Convience classes
388 class RuntimeAddress: public AddressLiteral {
389
390 public:
391
392 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
393
394 };
395
396 class ExternalAddress: public AddressLiteral {
397 private:
398 static relocInfo::relocType reloc_for_target(address target) {
399 // Sometimes ExternalAddress is used for values which aren't
400 // exactly addresses, like the card table base.
401 // external_word_type can't be used for values in the first page
402 // so just skip the reloc in that case.
403 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
404 }
405
406 public:
407
408 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
409
410 };
411
412 class InternalAddress: public AddressLiteral {
413
414 public:
415
416 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
417
418 };
419
420 // x86 can do array addressing as a single operation since disp can be an absolute
421 // address amd64 can't. We create a class that expresses the concept but does extra
422 // magic on amd64 to get the final result
423
424 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
425 private:
426
427 AddressLiteral _base;
428 Address _index;
429
430 public:
431
432 ArrayAddress() {};
433 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
434 AddressLiteral base() { return _base; }
435 Address index() { return _index; }
436
437 };
438
439 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
440
441 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
442 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
443 // is what you get. The Assembler is generating code into a CodeBuffer.
444
445 class Assembler : public AbstractAssembler {
446 friend class AbstractAssembler; // for the non-virtual hack
447 friend class LIR_Assembler; // as_Address()
448 friend class StubGenerator;
449
450 public:
451 enum Condition { // The x86 condition codes used for conditional jumps/moves.
452 zero = 0x4,
453 notZero = 0x5,
454 equal = 0x4,
455 notEqual = 0x5,
456 less = 0xc,
457 lessEqual = 0xe,
458 greater = 0xf,
459 greaterEqual = 0xd,
460 below = 0x2,
461 belowEqual = 0x6,
462 above = 0x7,
463 aboveEqual = 0x3,
464 overflow = 0x0,
465 noOverflow = 0x1,
466 carrySet = 0x2,
467 carryClear = 0x3,
468 negative = 0x8,
469 positive = 0x9,
470 parity = 0xa,
471 noParity = 0xb
472 };
473
474 enum Prefix {
475 // segment overrides
476 CS_segment = 0x2e,
477 SS_segment = 0x36,
478 DS_segment = 0x3e,
479 ES_segment = 0x26,
480 FS_segment = 0x64,
481 GS_segment = 0x65,
482
483 REX = 0x40,
484
485 REX_B = 0x41,
486 REX_X = 0x42,
487 REX_XB = 0x43,
488 REX_R = 0x44,
489 REX_RB = 0x45,
490 REX_RX = 0x46,
491 REX_RXB = 0x47,
492
493 REX_W = 0x48,
494
495 REX_WB = 0x49,
496 REX_WX = 0x4A,
497 REX_WXB = 0x4B,
498 REX_WR = 0x4C,
499 REX_WRB = 0x4D,
500 REX_WRX = 0x4E,
501 REX_WRXB = 0x4F,
502
503 VEX_3bytes = 0xC4,
504 VEX_2bytes = 0xC5,
505 EVEX_4bytes = 0x62
506 };
507
508 enum VexPrefix {
509 VEX_B = 0x20,
510 VEX_X = 0x40,
511 VEX_R = 0x80,
512 VEX_W = 0x80
513 };
514
515 enum ExexPrefix {
516 EVEX_F = 0x04,
517 EVEX_V = 0x08,
518 EVEX_Rb = 0x10,
519 EVEX_X = 0x40,
520 EVEX_Z = 0x80
521 };
522
523 enum VexSimdPrefix {
524 VEX_SIMD_NONE = 0x0,
525 VEX_SIMD_66 = 0x1,
526 VEX_SIMD_F3 = 0x2,
527 VEX_SIMD_F2 = 0x3
528 };
529
530 enum VexOpcode {
531 VEX_OPCODE_NONE = 0x0,
532 VEX_OPCODE_0F = 0x1,
533 VEX_OPCODE_0F_38 = 0x2,
534 VEX_OPCODE_0F_3A = 0x3
535 };
536
537 enum AvxVectorLen {
538 AVX_128bit = 0x0,
539 AVX_256bit = 0x1,
540 AVX_512bit = 0x2,
541 AVX_NoVec = 0x4
542 };
543
544 enum EvexTupleType {
545 EVEX_FV = 0,
546 EVEX_HV = 4,
547 EVEX_FVM = 6,
548 EVEX_T1S = 7,
549 EVEX_T1F = 11,
550 EVEX_T2 = 13,
551 EVEX_T4 = 15,
552 EVEX_T8 = 17,
553 EVEX_HVM = 18,
554 EVEX_QVM = 19,
555 EVEX_OVM = 20,
556 EVEX_M128 = 21,
557 EVEX_DUP = 22,
558 EVEX_ETUP = 23
559 };
560
561 enum EvexInputSizeInBits {
562 EVEX_8bit = 0,
563 EVEX_16bit = 1,
564 EVEX_32bit = 2,
565 EVEX_64bit = 3
566 };
567
568 enum WhichOperand {
569 // input to locate_operand, and format code for relocations
570 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
571 disp32_operand = 1, // embedded 32-bit displacement or address
572 call32_operand = 2, // embedded 32-bit self-relative displacement
573 #ifndef _LP64
574 _WhichOperand_limit = 3
575 #else
576 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
577 _WhichOperand_limit = 4
578 #endif
579 };
580
581
582
583 // NOTE: The general philopsophy of the declarations here is that 64bit versions
584 // of instructions are freely declared without the need for wrapping them an ifdef.
585 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
586 // In the .cpp file the implementations are wrapped so that they are dropped out
587 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
588 // to the size it was prior to merging up the 32bit and 64bit assemblers.
589 //
590 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
591 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
592
593 private:
594
595 int evex_encoding;
596 int input_size_in_bits;
597 int avx_vector_len;
598 int tuple_type;
599 bool is_evex_instruction;
600
601 // 64bit prefixes
602 int prefix_and_encode(int reg_enc, bool byteinst = false);
603 int prefixq_and_encode(int reg_enc);
604
605 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
606 int prefixq_and_encode(int dst_enc, int src_enc);
607
608 void prefix(Register reg);
609 void prefix(Address adr);
610 void prefixq(Address adr);
611
612 void prefix(Address adr, Register reg, bool byteinst = false);
613 void prefix(Address adr, XMMRegister reg);
614 void prefixq(Address adr, Register reg);
615 void prefixq(Address adr, XMMRegister reg);
616
617 void prefetch_prefix(Address src);
618
619 void rex_prefix(Address adr, XMMRegister xreg,
620 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
621 int rex_prefix_and_encode(int dst_enc, int src_enc,
622 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
623
624 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w,
625 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
626 int vector_len);
627
628 void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, bool evex_r, bool evex_v,
629 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
630 bool is_extended_context, bool is_merge_context,
631 int vector_len, bool no_mask_reg );
632
633 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
634 VexSimdPrefix pre, VexOpcode opc,
635 bool vex_w, int vector_len,
636 bool legacy_mode = false, bool no_mask_reg = false);
637
638 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src,
639 VexSimdPrefix pre, int vector_len = AVX_128bit,
640 bool no_mask_reg = false) {
641 int dst_enc = dst->encoding();
642 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
643 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector_len, false, no_mask_reg);
644 }
645
646 void vex_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
647 VexSimdPrefix pre, int vector_len = AVX_128bit,
648 bool no_mask_reg = false) {
649 int dst_enc = dst->encoding();
650 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
651 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
652 }
653
654 void vex_prefix_0F38(Register dst, Register nds, Address src, bool no_mask_reg = false) {
655 bool vex_w = false;
656 int vector_len = AVX_128bit;
657 vex_prefix(src, nds->encoding(), dst->encoding(),
658 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w,
659 vector_len, no_mask_reg);
660 }
661
662 void vex_prefix_0F38_q(Register dst, Register nds, Address src, bool no_mask_reg = false) {
663 bool vex_w = true;
664 int vector_len = AVX_128bit;
665 vex_prefix(src, nds->encoding(), dst->encoding(),
666 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w,
667 vector_len, no_mask_reg);
668 }
669 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
670 VexSimdPrefix pre, VexOpcode opc,
671 bool vex_w, int vector_len,
672 bool legacy_mode, bool no_mask_reg);
673
674 int vex_prefix_0F38_and_encode(Register dst, Register nds, Register src, bool no_mask_reg = false) {
675 bool vex_w = false;
676 int vector_len = AVX_128bit;
677 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
678 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector_len,
679 false, no_mask_reg);
680 }
681 int vex_prefix_0F38_and_encode_q(Register dst, Register nds, Register src, bool no_mask_reg = false) {
682 bool vex_w = true;
683 int vector_len = AVX_128bit;
684 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
685 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector_len,
686 false, no_mask_reg);
687 }
688 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
689 VexSimdPrefix pre, int vector_len = AVX_128bit,
690 VexOpcode opc = VEX_OPCODE_0F, bool legacy_mode = false,
691 bool no_mask_reg = false) {
692 int src_enc = src->encoding();
693 int dst_enc = dst->encoding();
694 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
695 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector_len, legacy_mode, no_mask_reg);
696 }
697
698 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr,
699 VexSimdPrefix pre, bool no_mask_reg, VexOpcode opc = VEX_OPCODE_0F,
700 bool rex_w = false, int vector_len = AVX_128bit, bool legacy_mode = false);
701
702 void simd_prefix(XMMRegister dst, Address src, VexSimdPrefix pre,
703 bool no_mask_reg, VexOpcode opc = VEX_OPCODE_0F) {
704 simd_prefix(dst, xnoreg, src, pre, no_mask_reg, opc);
705 }
706
707 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
708 simd_prefix(src, dst, pre, no_mask_reg);
709 }
710 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
711 VexSimdPrefix pre, bool no_mask_reg = false) {
712 bool rex_w = true;
713 simd_prefix(dst, nds, src, pre, no_mask_reg, VEX_OPCODE_0F, rex_w);
714 }
715
716 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
717 VexSimdPrefix pre, bool no_mask_reg,
718 VexOpcode opc = VEX_OPCODE_0F,
719 bool rex_w = false, int vector_len = AVX_128bit,
720 bool legacy_mode = false);
721
722 int kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src,
723 VexSimdPrefix pre, bool no_mask_reg,
724 VexOpcode opc = VEX_OPCODE_0F,
725 bool rex_w = false, int vector_len = AVX_128bit);
726
727 int kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src,
728 VexSimdPrefix pre, bool no_mask_reg,
729 VexOpcode opc = VEX_OPCODE_0F,
730 bool rex_w = false, int vector_len = AVX_128bit);
731
732 // Move/convert 32-bit integer value.
733 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src,
734 VexSimdPrefix pre, bool no_mask_reg) {
735 // It is OK to cast from Register to XMMRegister to pass argument here
736 // since only encoding is used in simd_prefix_and_encode() and number of
737 // Gen and Xmm registers are the same.
738 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, no_mask_reg, VEX_OPCODE_0F);
739 }
740 int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre, bool no_mask_reg) {
741 return simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg);
742 }
743 int simd_prefix_and_encode(Register dst, XMMRegister src,
744 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
745 bool no_mask_reg = false) {
746 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, no_mask_reg, opc);
747 }
748
749 // Move/convert 64-bit integer value.
750 int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src,
751 VexSimdPrefix pre, bool no_mask_reg = false) {
752 bool rex_w = true;
753 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, no_mask_reg, VEX_OPCODE_0F, rex_w);
754 }
755 int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre, bool no_mask_reg) {
756 return simd_prefix_and_encode_q(dst, xnoreg, src, pre, no_mask_reg);
757 }
758 int simd_prefix_and_encode_q(Register dst, XMMRegister src,
759 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
760 bool no_mask_reg = false) {
761 bool rex_w = true;
762 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, no_mask_reg, opc, rex_w);
763 }
764
765 // Helper functions for groups of instructions
766 void emit_arith_b(int op1, int op2, Register dst, int imm8);
767
768 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
769 // Force generation of a 4 byte immediate value even if it fits into 8bit
770 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
771 void emit_arith(int op1, int op2, Register dst, Register src);
772
773 void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false);
774 void emit_simd_arith_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false);
775 void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false);
776 void emit_simd_arith_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false);
777 void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false);
778 void emit_simd_arith_nonds_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg = false);
779 void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false);
780 void emit_simd_arith_nonds_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg = false);
781 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
782 Address src, VexSimdPrefix pre, int vector_len,
783 bool no_mask_reg = false);
784 void emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
785 Address src, VexSimdPrefix pre, int vector_len,
786 bool no_mask_reg = false);
787 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
788 XMMRegister src, VexSimdPrefix pre, int vector_len,
789 bool no_mask_reg = false);
790 void emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
791 XMMRegister src, VexSimdPrefix pre, int vector_len,
792 bool no_mask_reg = false);
793
794 bool emit_compressed_disp_byte(int &disp);
795
796 void emit_operand(Register reg,
797 Register base, Register index, Address::ScaleFactor scale,
798 int disp,
799 RelocationHolder const& rspec,
800 int rip_relative_correction = 0);
801
802 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
803
804 // operands that only take the original 32bit registers
805 void emit_operand32(Register reg, Address adr);
806
807 void emit_operand(XMMRegister reg,
808 Register base, Register index, Address::ScaleFactor scale,
809 int disp,
810 RelocationHolder const& rspec);
811
812 void emit_operand(XMMRegister reg, Address adr);
813
814 void emit_operand(MMXRegister reg, Address adr);
815
816 // workaround gcc (3.2.1-7) bug
817 void emit_operand(Address adr, MMXRegister reg);
818
819
820 // Immediate-to-memory forms
821 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
822
823 void emit_farith(int b1, int b2, int i);
824
825
826 protected:
827 #ifdef ASSERT
828 void check_relocation(RelocationHolder const& rspec, int format);
829 #endif
830
831 void emit_data(jint data, relocInfo::relocType rtype, int format);
832 void emit_data(jint data, RelocationHolder const& rspec, int format);
833 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
834 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
835
836 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
837
838 // These are all easily abused and hence protected
839
840 // 32BIT ONLY SECTION
841 #ifndef _LP64
842 // Make these disappear in 64bit mode since they would never be correct
843 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
844 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
845
846 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
847 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
848
849 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
850 #else
851 // 64BIT ONLY SECTION
852 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
853
854 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
855 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
856
857 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
858 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
859 #endif // _LP64
860
861 // These are unique in that we are ensured by the caller that the 32bit
862 // relative in these instructions will always be able to reach the potentially
863 // 64bit address described by entry. Since they can take a 64bit address they
864 // don't have the 32 suffix like the other instructions in this class.
865
866 void call_literal(address entry, RelocationHolder const& rspec);
867 void jmp_literal(address entry, RelocationHolder const& rspec);
868
869 // Avoid using directly section
870 // Instructions in this section are actually usable by anyone without danger
871 // of failure but have performance issues that are addressed my enhanced
872 // instructions which will do the proper thing base on the particular cpu.
873 // We protect them because we don't trust you...
874
875 // Don't use next inc() and dec() methods directly. INC & DEC instructions
876 // could cause a partial flag stall since they don't set CF flag.
877 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
878 // which call inc() & dec() or add() & sub() in accordance with
879 // the product flag UseIncDec value.
880
881 void decl(Register dst);
882 void decl(Address dst);
883 void decq(Register dst);
884 void decq(Address dst);
885
886 void incl(Register dst);
887 void incl(Address dst);
888 void incq(Register dst);
889 void incq(Address dst);
890
891 // New cpus require use of movsd and movss to avoid partial register stall
892 // when loading from memory. But for old Opteron use movlpd instead of movsd.
893 // The selection is done in MacroAssembler::movdbl() and movflt().
894
895 // Move Scalar Single-Precision Floating-Point Values
896 void movss(XMMRegister dst, Address src);
897 void movss(XMMRegister dst, XMMRegister src);
898 void movss(Address dst, XMMRegister src);
899
900 // Move Scalar Double-Precision Floating-Point Values
901 void movsd(XMMRegister dst, Address src);
902 void movsd(XMMRegister dst, XMMRegister src);
903 void movsd(Address dst, XMMRegister src);
904 void movlpd(XMMRegister dst, Address src);
905
906 // New cpus require use of movaps and movapd to avoid partial register stall
907 // when moving between registers.
908 void movaps(XMMRegister dst, XMMRegister src);
909 void movapd(XMMRegister dst, XMMRegister src);
910
911 // End avoid using directly
912
913
914 // Instruction prefixes
915 void prefix(Prefix p);
916
917 public:
918
919 // Creation
920 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
921 init_attributes();
922 }
923
924 // Decoding
925 static address locate_operand(address inst, WhichOperand which);
926 static address locate_next_instruction(address inst);
927
928 // Utilities
929 static bool is_polling_page_far() NOT_LP64({ return false;});
930
931 // Generic instructions
932 // Does 32bit or 64bit as needed for the platform. In some sense these
933 // belong in macro assembler but there is no need for both varieties to exist
934
935 void init_attributes(void) {
936 evex_encoding = 0;
937 input_size_in_bits = 0;
938 avx_vector_len = AVX_NoVec;
939 tuple_type = EVEX_ETUP;
940 is_evex_instruction = false;
941 }
942
943 void lea(Register dst, Address src);
944
945 void mov(Register dst, Register src);
946
947 void pusha();
948 void popa();
949
950 void pushf();
951 void popf();
952
953 void push(int32_t imm32);
954
955 void push(Register src);
956
957 void pop(Register dst);
958
959 // These are dummies to prevent surprise implicit conversions to Register
960 void push(void* v);
961 void pop(void* v);
962
963 // These do register sized moves/scans
964 void rep_mov();
965 void rep_stos();
966 void rep_stosb();
967 void repne_scan();
968 #ifdef _LP64
969 void repne_scanl();
970 #endif
971
972 // Vanilla instructions in lexical order
973
974 void adcl(Address dst, int32_t imm32);
975 void adcl(Address dst, Register src);
976 void adcl(Register dst, int32_t imm32);
977 void adcl(Register dst, Address src);
978 void adcl(Register dst, Register src);
979
980 void adcq(Register dst, int32_t imm32);
981 void adcq(Register dst, Address src);
982 void adcq(Register dst, Register src);
983
984 void addl(Address dst, int32_t imm32);
985 void addl(Address dst, Register src);
986 void addl(Register dst, int32_t imm32);
987 void addl(Register dst, Address src);
988 void addl(Register dst, Register src);
989
990 void addq(Address dst, int32_t imm32);
991 void addq(Address dst, Register src);
992 void addq(Register dst, int32_t imm32);
993 void addq(Register dst, Address src);
994 void addq(Register dst, Register src);
995
996 #ifdef _LP64
997 //Add Unsigned Integers with Carry Flag
998 void adcxq(Register dst, Register src);
999
1000 //Add Unsigned Integers with Overflow Flag
1001 void adoxq(Register dst, Register src);
1002 #endif
1003
1004 void addr_nop_4();
1005 void addr_nop_5();
1006 void addr_nop_7();
1007 void addr_nop_8();
1008
1009 // Add Scalar Double-Precision Floating-Point Values
1010 void addsd(XMMRegister dst, Address src);
1011 void addsd(XMMRegister dst, XMMRegister src);
1012
1013 // Add Scalar Single-Precision Floating-Point Values
1014 void addss(XMMRegister dst, Address src);
1015 void addss(XMMRegister dst, XMMRegister src);
1016
1017 // AES instructions
1018 void aesdec(XMMRegister dst, Address src);
1019 void aesdec(XMMRegister dst, XMMRegister src);
1020 void aesdeclast(XMMRegister dst, Address src);
1021 void aesdeclast(XMMRegister dst, XMMRegister src);
1022 void aesenc(XMMRegister dst, Address src);
1023 void aesenc(XMMRegister dst, XMMRegister src);
1024 void aesenclast(XMMRegister dst, Address src);
1025 void aesenclast(XMMRegister dst, XMMRegister src);
1026
1027
1028 void andl(Address dst, int32_t imm32);
1029 void andl(Register dst, int32_t imm32);
1030 void andl(Register dst, Address src);
1031 void andl(Register dst, Register src);
1032
1033 void andq(Address dst, int32_t imm32);
1034 void andq(Register dst, int32_t imm32);
1035 void andq(Register dst, Address src);
1036 void andq(Register dst, Register src);
1037
1038 // BMI instructions
1039 void andnl(Register dst, Register src1, Register src2);
1040 void andnl(Register dst, Register src1, Address src2);
1041 void andnq(Register dst, Register src1, Register src2);
1042 void andnq(Register dst, Register src1, Address src2);
1043
1044 void blsil(Register dst, Register src);
1045 void blsil(Register dst, Address src);
1046 void blsiq(Register dst, Register src);
1047 void blsiq(Register dst, Address src);
1048
1049 void blsmskl(Register dst, Register src);
1050 void blsmskl(Register dst, Address src);
1051 void blsmskq(Register dst, Register src);
1052 void blsmskq(Register dst, Address src);
1053
1054 void blsrl(Register dst, Register src);
1055 void blsrl(Register dst, Address src);
1056 void blsrq(Register dst, Register src);
1057 void blsrq(Register dst, Address src);
1058
1059 void bsfl(Register dst, Register src);
1060 void bsrl(Register dst, Register src);
1061
1062 #ifdef _LP64
1063 void bsfq(Register dst, Register src);
1064 void bsrq(Register dst, Register src);
1065 #endif
1066
1067 void bswapl(Register reg);
1068
1069 void bswapq(Register reg);
1070
1071 void call(Label& L, relocInfo::relocType rtype);
1072 void call(Register reg); // push pc; pc <- reg
1073 void call(Address adr); // push pc; pc <- adr
1074
1075 void cdql();
1076
1077 void cdqq();
1078
1079 void cld();
1080
1081 void clflush(Address adr);
1082
1083 void cmovl(Condition cc, Register dst, Register src);
1084 void cmovl(Condition cc, Register dst, Address src);
1085
1086 void cmovq(Condition cc, Register dst, Register src);
1087 void cmovq(Condition cc, Register dst, Address src);
1088
1089
1090 void cmpb(Address dst, int imm8);
1091
1092 void cmpl(Address dst, int32_t imm32);
1093
1094 void cmpl(Register dst, int32_t imm32);
1095 void cmpl(Register dst, Register src);
1096 void cmpl(Register dst, Address src);
1097
1098 void cmpq(Address dst, int32_t imm32);
1099 void cmpq(Address dst, Register src);
1100
1101 void cmpq(Register dst, int32_t imm32);
1102 void cmpq(Register dst, Register src);
1103 void cmpq(Register dst, Address src);
1104
1105 // these are dummies used to catch attempting to convert NULL to Register
1106 void cmpl(Register dst, void* junk); // dummy
1107 void cmpq(Register dst, void* junk); // dummy
1108
1109 void cmpw(Address dst, int imm16);
1110
1111 void cmpxchg8 (Address adr);
1112
1113 void cmpxchgb(Register reg, Address adr);
1114 void cmpxchgl(Register reg, Address adr);
1115
1116 void cmpxchgq(Register reg, Address adr);
1117
1118 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1119 void comisd(XMMRegister dst, Address src);
1120 void comisd(XMMRegister dst, XMMRegister src);
1121
1122 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1123 void comiss(XMMRegister dst, Address src);
1124 void comiss(XMMRegister dst, XMMRegister src);
1125
1126 // Identify processor type and features
1127 void cpuid();
1128
1129 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1130 void cvtsd2ss(XMMRegister dst, XMMRegister src);
1131 void cvtsd2ss(XMMRegister dst, Address src);
1132
1133 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1134 void cvtsi2sdl(XMMRegister dst, Register src);
1135 void cvtsi2sdl(XMMRegister dst, Address src);
1136 void cvtsi2sdq(XMMRegister dst, Register src);
1137 void cvtsi2sdq(XMMRegister dst, Address src);
1138
1139 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1140 void cvtsi2ssl(XMMRegister dst, Register src);
1141 void cvtsi2ssl(XMMRegister dst, Address src);
1142 void cvtsi2ssq(XMMRegister dst, Register src);
1143 void cvtsi2ssq(XMMRegister dst, Address src);
1144
1145 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1146 void cvtdq2pd(XMMRegister dst, XMMRegister src);
1147
1148 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1149 void cvtdq2ps(XMMRegister dst, XMMRegister src);
1150
1151 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1152 void cvtss2sd(XMMRegister dst, XMMRegister src);
1153 void cvtss2sd(XMMRegister dst, Address src);
1154
1155 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1156 void cvttsd2sil(Register dst, Address src);
1157 void cvttsd2sil(Register dst, XMMRegister src);
1158 void cvttsd2siq(Register dst, XMMRegister src);
1159
1160 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1161 void cvttss2sil(Register dst, XMMRegister src);
1162 void cvttss2siq(Register dst, XMMRegister src);
1163
1164 // Divide Scalar Double-Precision Floating-Point Values
1165 void divsd(XMMRegister dst, Address src);
1166 void divsd(XMMRegister dst, XMMRegister src);
1167
1168 // Divide Scalar Single-Precision Floating-Point Values
1169 void divss(XMMRegister dst, Address src);
1170 void divss(XMMRegister dst, XMMRegister src);
1171
1172 void emms();
1173
1174 void fabs();
1175
1176 void fadd(int i);
1177
1178 void fadd_d(Address src);
1179 void fadd_s(Address src);
1180
1181 // "Alternate" versions of x87 instructions place result down in FPU
1182 // stack instead of on TOS
1183
1184 void fadda(int i); // "alternate" fadd
1185 void faddp(int i = 1);
1186
1187 void fchs();
1188
1189 void fcom(int i);
1190
1191 void fcomp(int i = 1);
1192 void fcomp_d(Address src);
1193 void fcomp_s(Address src);
1194
1195 void fcompp();
1196
1197 void fcos();
1198
1199 void fdecstp();
1200
1201 void fdiv(int i);
1202 void fdiv_d(Address src);
1203 void fdivr_s(Address src);
1204 void fdiva(int i); // "alternate" fdiv
1205 void fdivp(int i = 1);
1206
1207 void fdivr(int i);
1208 void fdivr_d(Address src);
1209 void fdiv_s(Address src);
1210
1211 void fdivra(int i); // "alternate" reversed fdiv
1212
1213 void fdivrp(int i = 1);
1214
1215 void ffree(int i = 0);
1216
1217 void fild_d(Address adr);
1218 void fild_s(Address adr);
1219
1220 void fincstp();
1221
1222 void finit();
1223
1224 void fist_s (Address adr);
1225 void fistp_d(Address adr);
1226 void fistp_s(Address adr);
1227
1228 void fld1();
1229
1230 void fld_d(Address adr);
1231 void fld_s(Address adr);
1232 void fld_s(int index);
1233 void fld_x(Address adr); // extended-precision (80-bit) format
1234
1235 void fldcw(Address src);
1236
1237 void fldenv(Address src);
1238
1239 void fldlg2();
1240
1241 void fldln2();
1242
1243 void fldz();
1244
1245 void flog();
1246 void flog10();
1247
1248 void fmul(int i);
1249
1250 void fmul_d(Address src);
1251 void fmul_s(Address src);
1252
1253 void fmula(int i); // "alternate" fmul
1254
1255 void fmulp(int i = 1);
1256
1257 void fnsave(Address dst);
1258
1259 void fnstcw(Address src);
1260
1261 void fnstsw_ax();
1262
1263 void fprem();
1264 void fprem1();
1265
1266 void frstor(Address src);
1267
1268 void fsin();
1269
1270 void fsqrt();
1271
1272 void fst_d(Address adr);
1273 void fst_s(Address adr);
1274
1275 void fstp_d(Address adr);
1276 void fstp_d(int index);
1277 void fstp_s(Address adr);
1278 void fstp_x(Address adr); // extended-precision (80-bit) format
1279
1280 void fsub(int i);
1281 void fsub_d(Address src);
1282 void fsub_s(Address src);
1283
1284 void fsuba(int i); // "alternate" fsub
1285
1286 void fsubp(int i = 1);
1287
1288 void fsubr(int i);
1289 void fsubr_d(Address src);
1290 void fsubr_s(Address src);
1291
1292 void fsubra(int i); // "alternate" reversed fsub
1293
1294 void fsubrp(int i = 1);
1295
1296 void ftan();
1297
1298 void ftst();
1299
1300 void fucomi(int i = 1);
1301 void fucomip(int i = 1);
1302
1303 void fwait();
1304
1305 void fxch(int i = 1);
1306
1307 void fxrstor(Address src);
1308
1309 void fxsave(Address dst);
1310
1311 void fyl2x();
1312 void frndint();
1313 void f2xm1();
1314 void fldl2e();
1315
1316 void hlt();
1317
1318 void idivl(Register src);
1319 void divl(Register src); // Unsigned division
1320
1321 #ifdef _LP64
1322 void idivq(Register src);
1323 #endif
1324
1325 void imull(Register dst, Register src);
1326 void imull(Register dst, Register src, int value);
1327 void imull(Register dst, Address src);
1328
1329 #ifdef _LP64
1330 void imulq(Register dst, Register src);
1331 void imulq(Register dst, Register src, int value);
1332 void imulq(Register dst, Address src);
1333 #endif
1334
1335 // jcc is the generic conditional branch generator to run-
1336 // time routines, jcc is used for branches to labels. jcc
1337 // takes a branch opcode (cc) and a label (L) and generates
1338 // either a backward branch or a forward branch and links it
1339 // to the label fixup chain. Usage:
1340 //
1341 // Label L; // unbound label
1342 // jcc(cc, L); // forward branch to unbound label
1343 // bind(L); // bind label to the current pc
1344 // jcc(cc, L); // backward branch to bound label
1345 // bind(L); // illegal: a label may be bound only once
1346 //
1347 // Note: The same Label can be used for forward and backward branches
1348 // but it may be bound only once.
1349
1350 void jcc(Condition cc, Label& L, bool maybe_short = true);
1351
1352 // Conditional jump to a 8-bit offset to L.
1353 // WARNING: be very careful using this for forward jumps. If the label is
1354 // not bound within an 8-bit offset of this instruction, a run-time error
1355 // will occur.
1356 void jccb(Condition cc, Label& L);
1357
1358 void jmp(Address entry); // pc <- entry
1359
1360 // Label operations & relative jumps (PPUM Appendix D)
1361 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L
1362
1363 void jmp(Register entry); // pc <- entry
1364
1365 // Unconditional 8-bit offset jump to L.
1366 // WARNING: be very careful using this for forward jumps. If the label is
1367 // not bound within an 8-bit offset of this instruction, a run-time error
1368 // will occur.
1369 void jmpb(Label& L);
1370
1371 void ldmxcsr( Address src );
1372
1373 void leal(Register dst, Address src);
1374
1375 void leaq(Register dst, Address src);
1376
1377 void lfence();
1378
1379 void lock();
1380
1381 void lzcntl(Register dst, Register src);
1382
1383 #ifdef _LP64
1384 void lzcntq(Register dst, Register src);
1385 #endif
1386
1387 enum Membar_mask_bits {
1388 StoreStore = 1 << 3,
1389 LoadStore = 1 << 2,
1390 StoreLoad = 1 << 1,
1391 LoadLoad = 1 << 0
1392 };
1393
1394 // Serializes memory and blows flags
1395 void membar(Membar_mask_bits order_constraint) {
1396 if (os::is_MP()) {
1397 // We only have to handle StoreLoad
1398 if (order_constraint & StoreLoad) {
1399 // All usable chips support "locked" instructions which suffice
1400 // as barriers, and are much faster than the alternative of
1401 // using cpuid instruction. We use here a locked add [esp-C],0.
1402 // This is conveniently otherwise a no-op except for blowing
1403 // flags, and introducing a false dependency on target memory
1404 // location. We can't do anything with flags, but we can avoid
1405 // memory dependencies in the current method by locked-adding
1406 // somewhere else on the stack. Doing [esp+C] will collide with
1407 // something on stack in current method, hence we go for [esp-C].
1408 // It is convenient since it is almost always in data cache, for
1409 // any small C. We need to step back from SP to avoid data
1410 // dependencies with other things on below SP (callee-saves, for
1411 // example). Without a clear way to figure out the minimal safe
1412 // distance from SP, it makes sense to step back the complete
1413 // cache line, as this will also avoid possible second-order effects
1414 // with locked ops against the cache line. Our choice of offset
1415 // is bounded by x86 operand encoding, which should stay within
1416 // [-128; +127] to have the 8-byte displacement encoding.
1417 //
1418 // Any change to this code may need to revisit other places in
1419 // the code where this idiom is used, in particular the
1420 // orderAccess code.
1421
1422 int offset = -VM_Version::L1_line_size();
1423 if (offset < -128) {
1424 offset = -128;
1425 }
1426
1427 lock();
1428 addl(Address(rsp, offset), 0);// Assert the lock# signal here
1429 }
1430 }
1431 }
1432
1433 void mfence();
1434
1435 // Moves
1436
1437 void mov64(Register dst, int64_t imm64);
1438
1439 void movb(Address dst, Register src);
1440 void movb(Address dst, int imm8);
1441 void movb(Register dst, Address src);
1442
1443 void kmovq(KRegister dst, KRegister src);
1444 void kmovql(KRegister dst, Register src);
1445 void kmovq(Address dst, KRegister src);
1446 void kmovq(KRegister dst, Address src);
1447
1448 void movdl(XMMRegister dst, Register src);
1449 void movdl(Register dst, XMMRegister src);
1450 void movdl(XMMRegister dst, Address src);
1451 void movdl(Address dst, XMMRegister src);
1452
1453 // Move Double Quadword
1454 void movdq(XMMRegister dst, Register src);
1455 void movdq(Register dst, XMMRegister src);
1456
1457 // Move Aligned Double Quadword
1458 void movdqa(XMMRegister dst, XMMRegister src);
1459 void movdqa(XMMRegister dst, Address src);
1460
1461 // Move Unaligned Double Quadword
1462 void movdqu(Address dst, XMMRegister src);
1463 void movdqu(XMMRegister dst, Address src);
1464 void movdqu(XMMRegister dst, XMMRegister src);
1465
1466 // Move Unaligned 256bit Vector
1467 void vmovdqu(Address dst, XMMRegister src);
1468 void vmovdqu(XMMRegister dst, Address src);
1469 void vmovdqu(XMMRegister dst, XMMRegister src);
1470
1471 // Move Unaligned 512bit Vector
1472 void evmovdqu(Address dst, XMMRegister src, int vector_len);
1473 void evmovdqu(XMMRegister dst, Address src, int vector_len);
1474 void evmovdqu(XMMRegister dst, XMMRegister src, int vector_len);
1475
1476 // Move lower 64bit to high 64bit in 128bit register
1477 void movlhps(XMMRegister dst, XMMRegister src);
1478
1479 void movl(Register dst, int32_t imm32);
1480 void movl(Address dst, int32_t imm32);
1481 void movl(Register dst, Register src);
1482 void movl(Register dst, Address src);
1483 void movl(Address dst, Register src);
1484
1485 // These dummies prevent using movl from converting a zero (like NULL) into Register
1486 // by giving the compiler two choices it can't resolve
1487
1488 void movl(Address dst, void* junk);
1489 void movl(Register dst, void* junk);
1490
1491 #ifdef _LP64
1492 void movq(Register dst, Register src);
1493 void movq(Register dst, Address src);
1494 void movq(Address dst, Register src);
1495 #endif
1496
1497 void movq(Address dst, MMXRegister src );
1498 void movq(MMXRegister dst, Address src );
1499
1500 #ifdef _LP64
1501 // These dummies prevent using movq from converting a zero (like NULL) into Register
1502 // by giving the compiler two choices it can't resolve
1503
1504 void movq(Address dst, void* dummy);
1505 void movq(Register dst, void* dummy);
1506 #endif
1507
1508 // Move Quadword
1509 void movq(Address dst, XMMRegister src);
1510 void movq(XMMRegister dst, Address src);
1511
1512 void movsbl(Register dst, Address src);
1513 void movsbl(Register dst, Register src);
1514
1515 #ifdef _LP64
1516 void movsbq(Register dst, Address src);
1517 void movsbq(Register dst, Register src);
1518
1519 // Move signed 32bit immediate to 64bit extending sign
1520 void movslq(Address dst, int32_t imm64);
1521 void movslq(Register dst, int32_t imm64);
1522
1523 void movslq(Register dst, Address src);
1524 void movslq(Register dst, Register src);
1525 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1526 #endif
1527
1528 void movswl(Register dst, Address src);
1529 void movswl(Register dst, Register src);
1530
1531 #ifdef _LP64
1532 void movswq(Register dst, Address src);
1533 void movswq(Register dst, Register src);
1534 #endif
1535
1536 void movw(Address dst, int imm16);
1537 void movw(Register dst, Address src);
1538 void movw(Address dst, Register src);
1539
1540 void movzbl(Register dst, Address src);
1541 void movzbl(Register dst, Register src);
1542
1543 #ifdef _LP64
1544 void movzbq(Register dst, Address src);
1545 void movzbq(Register dst, Register src);
1546 #endif
1547
1548 void movzwl(Register dst, Address src);
1549 void movzwl(Register dst, Register src);
1550
1551 #ifdef _LP64
1552 void movzwq(Register dst, Address src);
1553 void movzwq(Register dst, Register src);
1554 #endif
1555
1556 // Unsigned multiply with RAX destination register
1557 void mull(Address src);
1558 void mull(Register src);
1559
1560 #ifdef _LP64
1561 void mulq(Address src);
1562 void mulq(Register src);
1563 void mulxq(Register dst1, Register dst2, Register src);
1564 #endif
1565
1566 // Multiply Scalar Double-Precision Floating-Point Values
1567 void mulsd(XMMRegister dst, Address src);
1568 void mulsd(XMMRegister dst, XMMRegister src);
1569
1570 // Multiply Scalar Single-Precision Floating-Point Values
1571 void mulss(XMMRegister dst, Address src);
1572 void mulss(XMMRegister dst, XMMRegister src);
1573
1574 void negl(Register dst);
1575
1576 #ifdef _LP64
1577 void negq(Register dst);
1578 #endif
1579
1580 void nop(int i = 1);
1581
1582 void notl(Register dst);
1583
1584 #ifdef _LP64
1585 void notq(Register dst);
1586 #endif
1587
1588 void orl(Address dst, int32_t imm32);
1589 void orl(Register dst, int32_t imm32);
1590 void orl(Register dst, Address src);
1591 void orl(Register dst, Register src);
1592
1593 void orq(Address dst, int32_t imm32);
1594 void orq(Register dst, int32_t imm32);
1595 void orq(Register dst, Address src);
1596 void orq(Register dst, Register src);
1597
1598 // Pack with unsigned saturation
1599 void packuswb(XMMRegister dst, XMMRegister src);
1600 void packuswb(XMMRegister dst, Address src);
1601 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1602
1603 // Pemutation of 64bit words
1604 void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1605
1606 void pause();
1607
1608 // SSE4.2 string instructions
1609 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1610 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1611
1612 // SSE 4.1 extract
1613 void pextrd(Register dst, XMMRegister src, int imm8);
1614 void pextrq(Register dst, XMMRegister src, int imm8);
1615
1616 // SSE 4.1 insert
1617 void pinsrd(XMMRegister dst, Register src, int imm8);
1618 void pinsrq(XMMRegister dst, Register src, int imm8);
1619
1620 // SSE4.1 packed move
1621 void pmovzxbw(XMMRegister dst, XMMRegister src);
1622 void pmovzxbw(XMMRegister dst, Address src);
1623
1624 #ifndef _LP64 // no 32bit push/pop on amd64
1625 void popl(Address dst);
1626 #endif
1627
1628 #ifdef _LP64
1629 void popq(Address dst);
1630 #endif
1631
1632 void popcntl(Register dst, Address src);
1633 void popcntl(Register dst, Register src);
1634
1635 #ifdef _LP64
1636 void popcntq(Register dst, Address src);
1637 void popcntq(Register dst, Register src);
1638 #endif
1639
1640 // Prefetches (SSE, SSE2, 3DNOW only)
1641
1642 void prefetchnta(Address src);
1643 void prefetchr(Address src);
1644 void prefetcht0(Address src);
1645 void prefetcht1(Address src);
1646 void prefetcht2(Address src);
1647 void prefetchw(Address src);
1648
1649 // Shuffle Bytes
1650 void pshufb(XMMRegister dst, XMMRegister src);
1651 void pshufb(XMMRegister dst, Address src);
1652
1653 // Shuffle Packed Doublewords
1654 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1655 void pshufd(XMMRegister dst, Address src, int mode);
1656
1657 // Shuffle Packed Low Words
1658 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1659 void pshuflw(XMMRegister dst, Address src, int mode);
1660
1661 // Shift Right by bytes Logical DoubleQuadword Immediate
1662 void psrldq(XMMRegister dst, int shift);
1663
1664 // Logical Compare 128bit
1665 void ptest(XMMRegister dst, XMMRegister src);
1666 void ptest(XMMRegister dst, Address src);
1667 // Logical Compare 256bit
1668 void vptest(XMMRegister dst, XMMRegister src);
1669 void vptest(XMMRegister dst, Address src);
1670
1671 // Interleave Low Bytes
1672 void punpcklbw(XMMRegister dst, XMMRegister src);
1673 void punpcklbw(XMMRegister dst, Address src);
1674
1675 // Interleave Low Doublewords
1676 void punpckldq(XMMRegister dst, XMMRegister src);
1677 void punpckldq(XMMRegister dst, Address src);
1678
1679 // Interleave Low Quadwords
1680 void punpcklqdq(XMMRegister dst, XMMRegister src);
1681
1682 #ifndef _LP64 // no 32bit push/pop on amd64
1683 void pushl(Address src);
1684 #endif
1685
1686 void pushq(Address src);
1687
1688 void rcll(Register dst, int imm8);
1689
1690 void rclq(Register dst, int imm8);
1691
1692 void rdtsc();
1693
1694 void ret(int imm16);
1695
1696 #ifdef _LP64
1697 void rorq(Register dst, int imm8);
1698 void rorxq(Register dst, Register src, int imm8);
1699 #endif
1700
1701 void sahf();
1702
1703 void sarl(Register dst, int imm8);
1704 void sarl(Register dst);
1705
1706 void sarq(Register dst, int imm8);
1707 void sarq(Register dst);
1708
1709 void sbbl(Address dst, int32_t imm32);
1710 void sbbl(Register dst, int32_t imm32);
1711 void sbbl(Register dst, Address src);
1712 void sbbl(Register dst, Register src);
1713
1714 void sbbq(Address dst, int32_t imm32);
1715 void sbbq(Register dst, int32_t imm32);
1716 void sbbq(Register dst, Address src);
1717 void sbbq(Register dst, Register src);
1718
1719 void setb(Condition cc, Register dst);
1720
1721 void shldl(Register dst, Register src);
1722
1723 void shll(Register dst, int imm8);
1724 void shll(Register dst);
1725
1726 void shlq(Register dst, int imm8);
1727 void shlq(Register dst);
1728
1729 void shrdl(Register dst, Register src);
1730
1731 void shrl(Register dst, int imm8);
1732 void shrl(Register dst);
1733
1734 void shrq(Register dst, int imm8);
1735 void shrq(Register dst);
1736
1737 void smovl(); // QQQ generic?
1738
1739 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1740 void sqrtsd(XMMRegister dst, Address src);
1741 void sqrtsd(XMMRegister dst, XMMRegister src);
1742
1743 // Compute Square Root of Scalar Single-Precision Floating-Point Value
1744 void sqrtss(XMMRegister dst, Address src);
1745 void sqrtss(XMMRegister dst, XMMRegister src);
1746
1747 void std();
1748
1749 void stmxcsr( Address dst );
1750
1751 void subl(Address dst, int32_t imm32);
1752 void subl(Address dst, Register src);
1753 void subl(Register dst, int32_t imm32);
1754 void subl(Register dst, Address src);
1755 void subl(Register dst, Register src);
1756
1757 void subq(Address dst, int32_t imm32);
1758 void subq(Address dst, Register src);
1759 void subq(Register dst, int32_t imm32);
1760 void subq(Register dst, Address src);
1761 void subq(Register dst, Register src);
1762
1763 // Force generation of a 4 byte immediate value even if it fits into 8bit
1764 void subl_imm32(Register dst, int32_t imm32);
1765 void subq_imm32(Register dst, int32_t imm32);
1766
1767 // Subtract Scalar Double-Precision Floating-Point Values
1768 void subsd(XMMRegister dst, Address src);
1769 void subsd(XMMRegister dst, XMMRegister src);
1770
1771 // Subtract Scalar Single-Precision Floating-Point Values
1772 void subss(XMMRegister dst, Address src);
1773 void subss(XMMRegister dst, XMMRegister src);
1774
1775 void testb(Register dst, int imm8);
1776
1777 void testl(Register dst, int32_t imm32);
1778 void testl(Register dst, Register src);
1779 void testl(Register dst, Address src);
1780
1781 void testq(Register dst, int32_t imm32);
1782 void testq(Register dst, Register src);
1783
1784 // BMI - count trailing zeros
1785 void tzcntl(Register dst, Register src);
1786 void tzcntq(Register dst, Register src);
1787
1788 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1789 void ucomisd(XMMRegister dst, Address src);
1790 void ucomisd(XMMRegister dst, XMMRegister src);
1791
1792 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1793 void ucomiss(XMMRegister dst, Address src);
1794 void ucomiss(XMMRegister dst, XMMRegister src);
1795
1796 void xabort(int8_t imm8);
1797
1798 void xaddl(Address dst, Register src);
1799
1800 void xaddq(Address dst, Register src);
1801
1802 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
1803
1804 void xchgl(Register reg, Address adr);
1805 void xchgl(Register dst, Register src);
1806
1807 void xchgq(Register reg, Address adr);
1808 void xchgq(Register dst, Register src);
1809
1810 void xend();
1811
1812 // Get Value of Extended Control Register
1813 void xgetbv();
1814
1815 void xorl(Register dst, int32_t imm32);
1816 void xorl(Register dst, Address src);
1817 void xorl(Register dst, Register src);
1818
1819 void xorq(Register dst, Address src);
1820 void xorq(Register dst, Register src);
1821
1822 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1823
1824 // AVX 3-operands scalar instructions (encoded with VEX prefix)
1825
1826 void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1827 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1828 void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1829 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1830 void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1831 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1832 void vdivss(XMMRegister dst, XMMRegister nds, Address src);
1833 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1834 void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
1835 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1836 void vmulss(XMMRegister dst, XMMRegister nds, Address src);
1837 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1838 void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1839 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1840 void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1841 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1842
1843
1844 //====================VECTOR ARITHMETIC=====================================
1845
1846 // Add Packed Floating-Point Values
1847 void addpd(XMMRegister dst, XMMRegister src);
1848 void addps(XMMRegister dst, XMMRegister src);
1849 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1850 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1851 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1852 void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1853
1854 // Subtract Packed Floating-Point Values
1855 void subpd(XMMRegister dst, XMMRegister src);
1856 void subps(XMMRegister dst, XMMRegister src);
1857 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1858 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1859 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1860 void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1861
1862 // Multiply Packed Floating-Point Values
1863 void mulpd(XMMRegister dst, XMMRegister src);
1864 void mulps(XMMRegister dst, XMMRegister src);
1865 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1866 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1867 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1868 void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1869
1870 // Divide Packed Floating-Point Values
1871 void divpd(XMMRegister dst, XMMRegister src);
1872 void divps(XMMRegister dst, XMMRegister src);
1873 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1874 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1875 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1876 void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1877
1878 // Bitwise Logical AND of Packed Floating-Point Values
1879 void andpd(XMMRegister dst, XMMRegister src);
1880 void andps(XMMRegister dst, XMMRegister src);
1881 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1882 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1883 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1884 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1885
1886 // Bitwise Logical XOR of Packed Floating-Point Values
1887 void xorpd(XMMRegister dst, XMMRegister src);
1888 void xorps(XMMRegister dst, XMMRegister src);
1889 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1890 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1891 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1892 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1893
1894 // Add horizontal packed integers
1895 void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1896 void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1897 void phaddw(XMMRegister dst, XMMRegister src);
1898 void phaddd(XMMRegister dst, XMMRegister src);
1899
1900 // Add packed integers
1901 void paddb(XMMRegister dst, XMMRegister src);
1902 void paddw(XMMRegister dst, XMMRegister src);
1903 void paddd(XMMRegister dst, XMMRegister src);
1904 void paddq(XMMRegister dst, XMMRegister src);
1905 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1906 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1907 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1908 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1909 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1910 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1911 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1912 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1913
1914 // Sub packed integers
1915 void psubb(XMMRegister dst, XMMRegister src);
1916 void psubw(XMMRegister dst, XMMRegister src);
1917 void psubd(XMMRegister dst, XMMRegister src);
1918 void psubq(XMMRegister dst, XMMRegister src);
1919 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1920 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1921 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1922 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1923 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1924 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1925 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1926 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1927
1928 // Multiply packed integers (only shorts and ints)
1929 void pmullw(XMMRegister dst, XMMRegister src);
1930 void pmulld(XMMRegister dst, XMMRegister src);
1931 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1932 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1933 void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1934 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1935 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1936 void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1937
1938 // Shift left packed integers
1939 void psllw(XMMRegister dst, int shift);
1940 void pslld(XMMRegister dst, int shift);
1941 void psllq(XMMRegister dst, int shift);
1942 void psllw(XMMRegister dst, XMMRegister shift);
1943 void pslld(XMMRegister dst, XMMRegister shift);
1944 void psllq(XMMRegister dst, XMMRegister shift);
1945 void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1946 void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1947 void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1948 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1949 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1950 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1951
1952 // Logical shift right packed integers
1953 void psrlw(XMMRegister dst, int shift);
1954 void psrld(XMMRegister dst, int shift);
1955 void psrlq(XMMRegister dst, int shift);
1956 void psrlw(XMMRegister dst, XMMRegister shift);
1957 void psrld(XMMRegister dst, XMMRegister shift);
1958 void psrlq(XMMRegister dst, XMMRegister shift);
1959 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1960 void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1961 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1962 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1963 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1964 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1965
1966 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
1967 void psraw(XMMRegister dst, int shift);
1968 void psrad(XMMRegister dst, int shift);
1969 void psraw(XMMRegister dst, XMMRegister shift);
1970 void psrad(XMMRegister dst, XMMRegister shift);
1971 void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1972 void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
1973 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1974 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
1975
1976 // And packed integers
1977 void pand(XMMRegister dst, XMMRegister src);
1978 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1979 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1980
1981 // Or packed integers
1982 void por(XMMRegister dst, XMMRegister src);
1983 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1984 void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1985
1986 // Xor packed integers
1987 void pxor(XMMRegister dst, XMMRegister src);
1988 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1989 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1990
1991 // Copy low 128bit into high 128bit of YMM registers.
1992 void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
1993 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
1994 void vextractf128h(XMMRegister dst, XMMRegister src);
1995 void vextracti128h(XMMRegister dst, XMMRegister src);
1996
1997 // Load/store high 128bit of YMM registers which does not destroy other half.
1998 void vinsertf128h(XMMRegister dst, Address src);
1999 void vinserti128h(XMMRegister dst, Address src);
2000 void vextractf128h(Address dst, XMMRegister src);
2001 void vextracti128h(Address dst, XMMRegister src);
2002
2003 // Copy low 256bit into high 256bit of ZMM registers.
2004 void vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2005 void vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src);
2006 void vextracti64x4h(XMMRegister dst, XMMRegister src);
2007 void vextractf64x4h(XMMRegister dst, XMMRegister src);
2008 void vextracti64x2h(XMMRegister dst, XMMRegister src, int value);
2009 void vextractf64x2h(XMMRegister dst, XMMRegister src, int value);
2010 void vextractf32x4h(XMMRegister dst, XMMRegister src, int value);
2011
2012 // duplicate 4-bytes integer data from src into 8 locations in dest
2013 void vpbroadcastd(XMMRegister dst, XMMRegister src);
2014
2015 // duplicate 4-bytes integer data from src into vector_len locations in dest
2016 void evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2017
2018 // Carry-Less Multiplication Quadword
2019 void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2020 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2021
2022 // AVX instruction which is used to clear upper 128 bits of YMM registers and
2023 // to avoid transaction penalty between AVX and SSE states. There is no
2024 // penalty if legacy SSE instructions are encoded using VEX prefix because
2025 // they always clear upper 128 bits. It should be used before calling
2026 // runtime code and native libraries.
2027 void vzeroupper();
2028
2029 protected:
2030 // Next instructions require address alignment 16 bytes SSE mode.
2031 // They should be called only from corresponding MacroAssembler instructions.
2032 void andpd(XMMRegister dst, Address src);
2033 void andps(XMMRegister dst, Address src);
2034 void xorpd(XMMRegister dst, Address src);
2035 void xorps(XMMRegister dst, Address src);
2036
2037 };
2038
2039 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP