1 /*
2 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_C1_LINEARSCAN_X86_HPP
26 #define CPU_X86_VM_C1_LINEARSCAN_X86_HPP
27
28 inline bool LinearScan::is_processed_reg_num(int reg_num) {
29 #ifndef _LP64
30 // rsp and rbp (numbers 6 ancd 7) are ignored
31 assert(FrameMap::rsp_opr->cpu_regnr() == 6, "wrong assumption below");
32 assert(FrameMap::rbp_opr->cpu_regnr() == 7, "wrong assumption below");
33 assert(reg_num >= 0, "invalid reg_num");
34 #else
35 // rsp and rbp, r10, r15 (numbers [12,15]) are ignored
36 // r12 (number 11) is conditional on compressed oops.
37 assert(FrameMap::r12_opr->cpu_regnr() == 11, "wrong assumption below");
38 assert(FrameMap::r10_opr->cpu_regnr() == 12, "wrong assumption below");
39 assert(FrameMap::r15_opr->cpu_regnr() == 13, "wrong assumption below");
40 assert(FrameMap::rsp_opr->cpu_regnrLo() == 14, "wrong assumption below");
41 assert(FrameMap::rbp_opr->cpu_regnrLo() == 15, "wrong assumption below");
42 assert(reg_num >= 0, "invalid reg_num");
43 #endif // _LP64
44 return reg_num <= FrameMap::last_cpu_reg() || reg_num >= pd_nof_cpu_regs_frame_map;
45 }
46
47 inline int LinearScan::num_physical_regs(BasicType type) {
48 // Intel requires two cpu registers for long,
49 // but requires only one fpu register for double
50 if (LP64_ONLY(false &&) type == T_LONG) {
51 return 2;
52 }
53 return 1;
54 }
55
56
57 inline bool LinearScan::requires_adjacent_regs(BasicType type) {
58 return false;
59 }
60
61 inline bool LinearScan::is_caller_save(int assigned_reg) {
62 assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers");
63 return true; // no callee-saved registers on Intel
64
65 }
66
67
68 inline void LinearScan::pd_add_temps(LIR_Op* op) {
69 switch (op->code()) {
70 case lir_tan:
71 case lir_sin:
72 case lir_cos: {
73 // The slow path for these functions may need to save and
74 // restore all live registers but we don't want to save and
75 // restore everything all the time, so mark the xmms as being
76 // killed. If the slow path were explicit or we could propagate
77 // live register masks down to the assembly we could do better
78 // but we don't have any easy way to do that right now. We
79 // could also consider not killing all xmm registers if we
80 // assume that slow paths are uncommon but it's not clear that
81 // would be a good idea.
82 if (UseSSE > 0) {
83 #ifndef PRODUCT
84 if (TraceLinearScanLevel >= 2) {
85 tty->print_cr("killing XMMs for trig");
86 }
87 #endif
88 int num_caller_save_xmm_regs = FrameMap::nof_caller_save_xmm_regs;
89 #if _LP64
90 if (UseAVX < 3) {
91 num_caller_save_xmm_regs = num_caller_save_xmm_regs / 2;
92 }
93 #endif
94 int op_id = op->id();
95 for (int xmm = 0; xmm < num_caller_save_xmm_regs; xmm++) {
96 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(xmm);
97 add_temp(reg_num(opr), op_id, noUse, T_ILLEGAL);
98 }
99 }
100 break;
101 }
102 }
103 }
104
105
106 // Implementation of LinearScanWalker
107
108 inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) {
109 int last_xmm_reg = pd_last_xmm_reg;
110 if (UseAVX < 3) {
111 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
112 }
113 if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::byte_reg)) {
114 assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only");
115 _first_reg = pd_first_byte_reg;
116 _last_reg = FrameMap::last_byte_reg();
117 return true;
118 } else if ((UseSSE >= 1 && cur->type() == T_FLOAT) || (UseSSE >= 2 && cur->type() == T_DOUBLE)) {
119 _first_reg = pd_first_xmm_reg;
120 _last_reg = last_xmm_reg;
121 return true;
122 }
123
124 return false;
125 }
126
127
128 class FpuStackAllocator VALUE_OBJ_CLASS_SPEC {
129 private:
130 Compilation* _compilation;
131 LinearScan* _allocator;
132
133 LIR_OpVisitState visitor;
134
135 LIR_List* _lir;
136 int _pos;
137 FpuStackSim _sim;
138 FpuStackSim _temp_sim;
139
140 bool _debug_information_computed;
141
142 LinearScan* allocator() { return _allocator; }
143 Compilation* compilation() const { return _compilation; }
144
145 // unified bailout support
146 void bailout(const char* msg) const { compilation()->bailout(msg); }
147 bool bailed_out() const { return compilation()->bailed_out(); }
148
149 int pos() { return _pos; }
150 void set_pos(int pos) { _pos = pos; }
151 LIR_Op* cur_op() { return lir()->instructions_list()->at(pos()); }
152 LIR_List* lir() { return _lir; }
153 void set_lir(LIR_List* lir) { _lir = lir; }
154 FpuStackSim* sim() { return &_sim; }
155 FpuStackSim* temp_sim() { return &_temp_sim; }
156
157 int fpu_num(LIR_Opr opr);
158 int tos_offset(LIR_Opr opr);
159 LIR_Opr to_fpu_stack_top(LIR_Opr opr, bool dont_check_offset = false);
160
161 // Helper functions for handling operations
162 void insert_op(LIR_Op* op);
163 void insert_exchange(int offset);
164 void insert_exchange(LIR_Opr opr);
165 void insert_free(int offset);
166 void insert_free_if_dead(LIR_Opr opr);
167 void insert_free_if_dead(LIR_Opr opr, LIR_Opr ignore);
168 void insert_copy(LIR_Opr from, LIR_Opr to);
169 void do_rename(LIR_Opr from, LIR_Opr to);
170 void do_push(LIR_Opr opr);
171 void pop_if_last_use(LIR_Op* op, LIR_Opr opr);
172 void pop_always(LIR_Op* op, LIR_Opr opr);
173 void clear_fpu_stack(LIR_Opr preserve);
174 void handle_op1(LIR_Op1* op1);
175 void handle_op2(LIR_Op2* op2);
176 void handle_opCall(LIR_OpCall* opCall);
177 void compute_debug_information(LIR_Op* op);
178 void allocate_exception_handler(XHandler* xhandler);
179 void allocate_block(BlockBegin* block);
180
181 #ifndef PRODUCT
182 void check_invalid_lir_op(LIR_Op* op);
183 #endif
184
185 // Helper functions for merging of fpu stacks
186 void merge_insert_add(LIR_List* instrs, FpuStackSim* cur_sim, int reg);
187 void merge_insert_xchg(LIR_List* instrs, FpuStackSim* cur_sim, int slot);
188 void merge_insert_pop(LIR_List* instrs, FpuStackSim* cur_sim);
189 bool merge_rename(FpuStackSim* cur_sim, FpuStackSim* sux_sim, int start_slot, int change_slot);
190 void merge_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, FpuStackSim* sux_sim);
191 void merge_cleanup_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, BitMap& live_fpu_regs);
192 bool merge_fpu_stack_with_successors(BlockBegin* block);
193
194 public:
195 LIR_Opr to_fpu_stack(LIR_Opr opr); // used by LinearScan for creation of debug information
196
197 FpuStackAllocator(Compilation* compilation, LinearScan* allocator);
198 void allocate();
199 };
200
201 #endif // CPU_X86_VM_C1_LINEARSCAN_X86_HPP