1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc_interface/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/cardTableModRefBS.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "prims/methodHandles.hpp"
35 #include "runtime/biasedLocking.hpp"
36 #include "runtime/interfaceSupport.hpp"
37 #include "runtime/objectMonitor.hpp"
38 #include "runtime/os.hpp"
39 #include "runtime/sharedRuntime.hpp"
40 #include "runtime/stubRoutines.hpp"
41 #include "utilities/macros.hpp"
42 #if INCLUDE_ALL_GCS
43 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
44 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
45 #include "gc_implementation/g1/heapRegion.hpp"
46 #endif // INCLUDE_ALL_GCS
47
48 #ifdef PRODUCT
49 #define BLOCK_COMMENT(str) /* nothing */
50 #define STOP(error) stop(error)
51 #else
52 #define BLOCK_COMMENT(str) block_comment(str)
53 #define STOP(error) block_comment(error); stop(error)
54 #endif
55
56 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
57
58 PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC
59
60 #ifdef ASSERT
61 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
62 #endif
63
64 static Assembler::Condition reverse[] = {
65 Assembler::noOverflow /* overflow = 0x0 */ ,
66 Assembler::overflow /* noOverflow = 0x1 */ ,
67 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
68 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
69 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
70 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
71 Assembler::above /* belowEqual = 0x6 */ ,
72 Assembler::belowEqual /* above = 0x7 */ ,
73 Assembler::positive /* negative = 0x8 */ ,
74 Assembler::negative /* positive = 0x9 */ ,
75 Assembler::noParity /* parity = 0xa */ ,
76 Assembler::parity /* noParity = 0xb */ ,
77 Assembler::greaterEqual /* less = 0xc */ ,
78 Assembler::less /* greaterEqual = 0xd */ ,
79 Assembler::greater /* lessEqual = 0xe */ ,
80 Assembler::lessEqual /* greater = 0xf, */
81
82 };
83
84
85 // Implementation of MacroAssembler
86
87 // First all the versions that have distinct versions depending on 32/64 bit
88 // Unless the difference is trivial (1 line or so).
89
90 #ifndef _LP64
91
92 // 32bit versions
93
94 Address MacroAssembler::as_Address(AddressLiteral adr) {
95 return Address(adr.target(), adr.rspec());
96 }
97
98 Address MacroAssembler::as_Address(ArrayAddress adr) {
99 return Address::make_array(adr);
100 }
101
102 void MacroAssembler::call_VM_leaf_base(address entry_point,
103 int number_of_arguments) {
104 call(RuntimeAddress(entry_point));
105 increment(rsp, number_of_arguments * wordSize);
106 }
107
108 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
109 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
110 }
111
112 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
114 }
115
116 void MacroAssembler::cmpoop(Address src1, jobject obj) {
117 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
118 }
119
120 void MacroAssembler::cmpoop(Register src1, jobject obj) {
121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
122 }
123
124 void MacroAssembler::extend_sign(Register hi, Register lo) {
125 // According to Intel Doc. AP-526, "Integer Divide", p.18.
126 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
127 cdql();
128 } else {
129 movl(hi, lo);
130 sarl(hi, 31);
131 }
132 }
133
134 void MacroAssembler::jC2(Register tmp, Label& L) {
135 // set parity bit if FPU flag C2 is set (via rax)
136 save_rax(tmp);
137 fwait(); fnstsw_ax();
138 sahf();
139 restore_rax(tmp);
140 // branch
141 jcc(Assembler::parity, L);
142 }
143
144 void MacroAssembler::jnC2(Register tmp, Label& L) {
145 // set parity bit if FPU flag C2 is set (via rax)
146 save_rax(tmp);
147 fwait(); fnstsw_ax();
148 sahf();
149 restore_rax(tmp);
150 // branch
151 jcc(Assembler::noParity, L);
152 }
153
154 // 32bit can do a case table jump in one instruction but we no longer allow the base
155 // to be installed in the Address class
156 void MacroAssembler::jump(ArrayAddress entry) {
157 jmp(as_Address(entry));
158 }
159
160 // Note: y_lo will be destroyed
161 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
162 // Long compare for Java (semantics as described in JVM spec.)
163 Label high, low, done;
164
165 cmpl(x_hi, y_hi);
166 jcc(Assembler::less, low);
167 jcc(Assembler::greater, high);
168 // x_hi is the return register
169 xorl(x_hi, x_hi);
170 cmpl(x_lo, y_lo);
171 jcc(Assembler::below, low);
172 jcc(Assembler::equal, done);
173
174 bind(high);
175 xorl(x_hi, x_hi);
176 increment(x_hi);
177 jmp(done);
178
179 bind(low);
180 xorl(x_hi, x_hi);
181 decrementl(x_hi);
182
183 bind(done);
184 }
185
186 void MacroAssembler::lea(Register dst, AddressLiteral src) {
187 mov_literal32(dst, (int32_t)src.target(), src.rspec());
188 }
189
190 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
191 // leal(dst, as_Address(adr));
192 // see note in movl as to why we must use a move
193 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
194 }
195
196 void MacroAssembler::leave() {
197 mov(rsp, rbp);
198 pop(rbp);
199 }
200
201 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
202 // Multiplication of two Java long values stored on the stack
203 // as illustrated below. Result is in rdx:rax.
204 //
205 // rsp ---> [ ?? ] \ \
206 // .... | y_rsp_offset |
207 // [ y_lo ] / (in bytes) | x_rsp_offset
208 // [ y_hi ] | (in bytes)
209 // .... |
210 // [ x_lo ] /
211 // [ x_hi ]
212 // ....
213 //
214 // Basic idea: lo(result) = lo(x_lo * y_lo)
215 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
216 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
217 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
218 Label quick;
219 // load x_hi, y_hi and check if quick
220 // multiplication is possible
221 movl(rbx, x_hi);
222 movl(rcx, y_hi);
223 movl(rax, rbx);
224 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
225 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
226 // do full multiplication
227 // 1st step
228 mull(y_lo); // x_hi * y_lo
229 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
230 // 2nd step
231 movl(rax, x_lo);
232 mull(rcx); // x_lo * y_hi
233 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
234 // 3rd step
235 bind(quick); // note: rbx, = 0 if quick multiply!
236 movl(rax, x_lo);
237 mull(y_lo); // x_lo * y_lo
238 addl(rdx, rbx); // correct hi(x_lo * y_lo)
239 }
240
241 void MacroAssembler::lneg(Register hi, Register lo) {
242 negl(lo);
243 adcl(hi, 0);
244 negl(hi);
245 }
246
247 void MacroAssembler::lshl(Register hi, Register lo) {
248 // Java shift left long support (semantics as described in JVM spec., p.305)
249 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
250 // shift value is in rcx !
251 assert(hi != rcx, "must not use rcx");
252 assert(lo != rcx, "must not use rcx");
253 const Register s = rcx; // shift count
254 const int n = BitsPerWord;
255 Label L;
256 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
257 cmpl(s, n); // if (s < n)
258 jcc(Assembler::less, L); // else (s >= n)
259 movl(hi, lo); // x := x << n
260 xorl(lo, lo);
261 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
262 bind(L); // s (mod n) < n
263 shldl(hi, lo); // x := x << s
264 shll(lo);
265 }
266
267
268 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
269 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
270 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
271 assert(hi != rcx, "must not use rcx");
272 assert(lo != rcx, "must not use rcx");
273 const Register s = rcx; // shift count
274 const int n = BitsPerWord;
275 Label L;
276 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
277 cmpl(s, n); // if (s < n)
278 jcc(Assembler::less, L); // else (s >= n)
279 movl(lo, hi); // x := x >> n
280 if (sign_extension) sarl(hi, 31);
281 else xorl(hi, hi);
282 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
283 bind(L); // s (mod n) < n
284 shrdl(lo, hi); // x := x >> s
285 if (sign_extension) sarl(hi);
286 else shrl(hi);
287 }
288
289 void MacroAssembler::movoop(Register dst, jobject obj) {
290 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
291 }
292
293 void MacroAssembler::movoop(Address dst, jobject obj) {
294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
295 }
296
297 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
298 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
299 }
300
301 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
303 }
304
305 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
306 // scratch register is not used,
307 // it is defined to match parameters of 64-bit version of this method.
308 if (src.is_lval()) {
309 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
310 } else {
311 movl(dst, as_Address(src));
312 }
313 }
314
315 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
316 movl(as_Address(dst), src);
317 }
318
319 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
320 movl(dst, as_Address(src));
321 }
322
323 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
324 void MacroAssembler::movptr(Address dst, intptr_t src) {
325 movl(dst, src);
326 }
327
328
329 void MacroAssembler::pop_callee_saved_registers() {
330 pop(rcx);
331 pop(rdx);
332 pop(rdi);
333 pop(rsi);
334 }
335
336 void MacroAssembler::pop_fTOS() {
337 fld_d(Address(rsp, 0));
338 addl(rsp, 2 * wordSize);
339 }
340
341 void MacroAssembler::push_callee_saved_registers() {
342 push(rsi);
343 push(rdi);
344 push(rdx);
345 push(rcx);
346 }
347
348 void MacroAssembler::push_fTOS() {
349 subl(rsp, 2 * wordSize);
350 fstp_d(Address(rsp, 0));
351 }
352
353
354 void MacroAssembler::pushoop(jobject obj) {
355 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
356 }
357
358 void MacroAssembler::pushklass(Metadata* obj) {
359 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
360 }
361
362 void MacroAssembler::pushptr(AddressLiteral src) {
363 if (src.is_lval()) {
364 push_literal32((int32_t)src.target(), src.rspec());
365 } else {
366 pushl(as_Address(src));
367 }
368 }
369
370 void MacroAssembler::set_word_if_not_zero(Register dst) {
371 xorl(dst, dst);
372 set_byte_if_not_zero(dst);
373 }
374
375 static void pass_arg0(MacroAssembler* masm, Register arg) {
376 masm->push(arg);
377 }
378
379 static void pass_arg1(MacroAssembler* masm, Register arg) {
380 masm->push(arg);
381 }
382
383 static void pass_arg2(MacroAssembler* masm, Register arg) {
384 masm->push(arg);
385 }
386
387 static void pass_arg3(MacroAssembler* masm, Register arg) {
388 masm->push(arg);
389 }
390
391 #ifndef PRODUCT
392 extern "C" void findpc(intptr_t x);
393 #endif
394
395 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
396 // In order to get locks to work, we need to fake a in_VM state
397 JavaThread* thread = JavaThread::current();
398 JavaThreadState saved_state = thread->thread_state();
399 thread->set_thread_state(_thread_in_vm);
400 if (ShowMessageBoxOnError) {
401 JavaThread* thread = JavaThread::current();
402 JavaThreadState saved_state = thread->thread_state();
403 thread->set_thread_state(_thread_in_vm);
404 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
405 ttyLocker ttyl;
406 BytecodeCounter::print();
407 }
408 // To see where a verify_oop failed, get $ebx+40/X for this frame.
409 // This is the value of eip which points to where verify_oop will return.
410 if (os::message_box(msg, "Execution stopped, print registers?")) {
411 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
412 BREAKPOINT;
413 }
414 } else {
415 ttyLocker ttyl;
416 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
417 }
418 // Don't assert holding the ttyLock
419 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
420 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
421 }
422
423 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
424 ttyLocker ttyl;
425 FlagSetting fs(Debugging, true);
426 tty->print_cr("eip = 0x%08x", eip);
427 #ifndef PRODUCT
428 if ((WizardMode || Verbose) && PrintMiscellaneous) {
429 tty->cr();
430 findpc(eip);
431 tty->cr();
432 }
433 #endif
434 #define PRINT_REG(rax) \
435 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
436 PRINT_REG(rax);
437 PRINT_REG(rbx);
438 PRINT_REG(rcx);
439 PRINT_REG(rdx);
440 PRINT_REG(rdi);
441 PRINT_REG(rsi);
442 PRINT_REG(rbp);
443 PRINT_REG(rsp);
444 #undef PRINT_REG
445 // Print some words near top of staack.
446 int* dump_sp = (int*) rsp;
447 for (int col1 = 0; col1 < 8; col1++) {
448 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
449 os::print_location(tty, *dump_sp++);
450 }
451 for (int row = 0; row < 16; row++) {
452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
453 for (int col = 0; col < 8; col++) {
454 tty->print(" 0x%08x", *dump_sp++);
455 }
456 tty->cr();
457 }
458 // Print some instructions around pc:
459 Disassembler::decode((address)eip-64, (address)eip);
460 tty->print_cr("--------");
461 Disassembler::decode((address)eip, (address)eip+32);
462 }
463
464 void MacroAssembler::stop(const char* msg) {
465 ExternalAddress message((address)msg);
466 // push address of message
467 pushptr(message.addr());
468 { Label L; call(L, relocInfo::none); bind(L); } // push eip
469 pusha(); // push registers
470 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
471 hlt();
472 }
473
474 void MacroAssembler::warn(const char* msg) {
475 push_CPU_state();
476
477 ExternalAddress message((address) msg);
478 // push address of message
479 pushptr(message.addr());
480
481 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
482 addl(rsp, wordSize); // discard argument
483 pop_CPU_state();
484 }
485
486 void MacroAssembler::print_state() {
487 { Label L; call(L, relocInfo::none); bind(L); } // push eip
488 pusha(); // push registers
489
490 push_CPU_state();
491 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
492 pop_CPU_state();
493
494 popa();
495 addl(rsp, wordSize);
496 }
497
498 #else // _LP64
499
500 // 64 bit versions
501
502 Address MacroAssembler::as_Address(AddressLiteral adr) {
503 // amd64 always does this as a pc-rel
504 // we can be absolute or disp based on the instruction type
505 // jmp/call are displacements others are absolute
506 assert(!adr.is_lval(), "must be rval");
507 assert(reachable(adr), "must be");
508 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
509
510 }
511
512 Address MacroAssembler::as_Address(ArrayAddress adr) {
513 AddressLiteral base = adr.base();
514 lea(rscratch1, base);
515 Address index = adr.index();
516 assert(index._disp == 0, "must not have disp"); // maybe it can?
517 Address array(rscratch1, index._index, index._scale, index._disp);
518 return array;
519 }
520
521 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
522 Label L, E;
523
524 #ifdef _WIN64
525 // Windows always allocates space for it's register args
526 assert(num_args <= 4, "only register arguments supported");
527 subq(rsp, frame::arg_reg_save_area_bytes);
528 #endif
529
530 // Align stack if necessary
531 testl(rsp, 15);
532 jcc(Assembler::zero, L);
533
534 subq(rsp, 8);
535 {
536 call(RuntimeAddress(entry_point));
537 }
538 addq(rsp, 8);
539 jmp(E);
540
541 bind(L);
542 {
543 call(RuntimeAddress(entry_point));
544 }
545
546 bind(E);
547
548 #ifdef _WIN64
549 // restore stack pointer
550 addq(rsp, frame::arg_reg_save_area_bytes);
551 #endif
552
553 }
554
555 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
556 assert(!src2.is_lval(), "should use cmpptr");
557
558 if (reachable(src2)) {
559 cmpq(src1, as_Address(src2));
560 } else {
561 lea(rscratch1, src2);
562 Assembler::cmpq(src1, Address(rscratch1, 0));
563 }
564 }
565
566 int MacroAssembler::corrected_idivq(Register reg) {
567 // Full implementation of Java ldiv and lrem; checks for special
568 // case as described in JVM spec., p.243 & p.271. The function
569 // returns the (pc) offset of the idivl instruction - may be needed
570 // for implicit exceptions.
571 //
572 // normal case special case
573 //
574 // input : rax: dividend min_long
575 // reg: divisor (may not be eax/edx) -1
576 //
577 // output: rax: quotient (= rax idiv reg) min_long
578 // rdx: remainder (= rax irem reg) 0
579 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
580 static const int64_t min_long = 0x8000000000000000;
581 Label normal_case, special_case;
582
583 // check for special case
584 cmp64(rax, ExternalAddress((address) &min_long));
585 jcc(Assembler::notEqual, normal_case);
586 xorl(rdx, rdx); // prepare rdx for possible special case (where
587 // remainder = 0)
588 cmpq(reg, -1);
589 jcc(Assembler::equal, special_case);
590
591 // handle normal case
592 bind(normal_case);
593 cdqq();
594 int idivq_offset = offset();
595 idivq(reg);
596
597 // normal and special case exit
598 bind(special_case);
599
600 return idivq_offset;
601 }
602
603 void MacroAssembler::decrementq(Register reg, int value) {
604 if (value == min_jint) { subq(reg, value); return; }
605 if (value < 0) { incrementq(reg, -value); return; }
606 if (value == 0) { ; return; }
607 if (value == 1 && UseIncDec) { decq(reg) ; return; }
608 /* else */ { subq(reg, value) ; return; }
609 }
610
611 void MacroAssembler::decrementq(Address dst, int value) {
612 if (value == min_jint) { subq(dst, value); return; }
613 if (value < 0) { incrementq(dst, -value); return; }
614 if (value == 0) { ; return; }
615 if (value == 1 && UseIncDec) { decq(dst) ; return; }
616 /* else */ { subq(dst, value) ; return; }
617 }
618
619 void MacroAssembler::incrementq(AddressLiteral dst) {
620 if (reachable(dst)) {
621 incrementq(as_Address(dst));
622 } else {
623 lea(rscratch1, dst);
624 incrementq(Address(rscratch1, 0));
625 }
626 }
627
628 void MacroAssembler::incrementq(Register reg, int value) {
629 if (value == min_jint) { addq(reg, value); return; }
630 if (value < 0) { decrementq(reg, -value); return; }
631 if (value == 0) { ; return; }
632 if (value == 1 && UseIncDec) { incq(reg) ; return; }
633 /* else */ { addq(reg, value) ; return; }
634 }
635
636 void MacroAssembler::incrementq(Address dst, int value) {
637 if (value == min_jint) { addq(dst, value); return; }
638 if (value < 0) { decrementq(dst, -value); return; }
639 if (value == 0) { ; return; }
640 if (value == 1 && UseIncDec) { incq(dst) ; return; }
641 /* else */ { addq(dst, value) ; return; }
642 }
643
644 // 32bit can do a case table jump in one instruction but we no longer allow the base
645 // to be installed in the Address class
646 void MacroAssembler::jump(ArrayAddress entry) {
647 lea(rscratch1, entry.base());
648 Address dispatch = entry.index();
649 assert(dispatch._base == noreg, "must be");
650 dispatch._base = rscratch1;
651 jmp(dispatch);
652 }
653
654 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
655 ShouldNotReachHere(); // 64bit doesn't use two regs
656 cmpq(x_lo, y_lo);
657 }
658
659 void MacroAssembler::lea(Register dst, AddressLiteral src) {
660 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
661 }
662
663 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
664 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
665 movptr(dst, rscratch1);
666 }
667
668 void MacroAssembler::leave() {
669 // %%% is this really better? Why not on 32bit too?
670 emit_int8((unsigned char)0xC9); // LEAVE
671 }
672
673 void MacroAssembler::lneg(Register hi, Register lo) {
674 ShouldNotReachHere(); // 64bit doesn't use two regs
675 negq(lo);
676 }
677
678 void MacroAssembler::movoop(Register dst, jobject obj) {
679 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
680 }
681
682 void MacroAssembler::movoop(Address dst, jobject obj) {
683 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
684 movq(dst, rscratch1);
685 }
686
687 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
688 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
689 }
690
691 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
692 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
693 movq(dst, rscratch1);
694 }
695
696 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
697 if (src.is_lval()) {
698 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
699 } else {
700 if (reachable(src)) {
701 movq(dst, as_Address(src));
702 } else {
703 lea(scratch, src);
704 movq(dst, Address(scratch, 0));
705 }
706 }
707 }
708
709 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
710 movq(as_Address(dst), src);
711 }
712
713 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
714 movq(dst, as_Address(src));
715 }
716
717 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
718 void MacroAssembler::movptr(Address dst, intptr_t src) {
719 mov64(rscratch1, src);
720 movq(dst, rscratch1);
721 }
722
723 // These are mostly for initializing NULL
724 void MacroAssembler::movptr(Address dst, int32_t src) {
725 movslq(dst, src);
726 }
727
728 void MacroAssembler::movptr(Register dst, int32_t src) {
729 mov64(dst, (intptr_t)src);
730 }
731
732 void MacroAssembler::pushoop(jobject obj) {
733 movoop(rscratch1, obj);
734 push(rscratch1);
735 }
736
737 void MacroAssembler::pushklass(Metadata* obj) {
738 mov_metadata(rscratch1, obj);
739 push(rscratch1);
740 }
741
742 void MacroAssembler::pushptr(AddressLiteral src) {
743 lea(rscratch1, src);
744 if (src.is_lval()) {
745 push(rscratch1);
746 } else {
747 pushq(Address(rscratch1, 0));
748 }
749 }
750
751 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
752 bool clear_pc) {
753 // we must set sp to zero to clear frame
754 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
755 // must clear fp, so that compiled frames are not confused; it is
756 // possible that we need it only for debugging
757 if (clear_fp) {
758 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
759 }
760
761 if (clear_pc) {
762 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
763 }
764 }
765
766 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
767 Register last_java_fp,
768 address last_java_pc) {
769 // determine last_java_sp register
770 if (!last_java_sp->is_valid()) {
771 last_java_sp = rsp;
772 }
773
774 // last_java_fp is optional
775 if (last_java_fp->is_valid()) {
776 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
777 last_java_fp);
778 }
779
780 // last_java_pc is optional
781 if (last_java_pc != NULL) {
782 Address java_pc(r15_thread,
783 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
784 lea(rscratch1, InternalAddress(last_java_pc));
785 movptr(java_pc, rscratch1);
786 }
787
788 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
789 }
790
791 static void pass_arg0(MacroAssembler* masm, Register arg) {
792 if (c_rarg0 != arg ) {
793 masm->mov(c_rarg0, arg);
794 }
795 }
796
797 static void pass_arg1(MacroAssembler* masm, Register arg) {
798 if (c_rarg1 != arg ) {
799 masm->mov(c_rarg1, arg);
800 }
801 }
802
803 static void pass_arg2(MacroAssembler* masm, Register arg) {
804 if (c_rarg2 != arg ) {
805 masm->mov(c_rarg2, arg);
806 }
807 }
808
809 static void pass_arg3(MacroAssembler* masm, Register arg) {
810 if (c_rarg3 != arg ) {
811 masm->mov(c_rarg3, arg);
812 }
813 }
814
815 void MacroAssembler::stop(const char* msg) {
816 address rip = pc();
817 pusha(); // get regs on stack
818 lea(c_rarg0, ExternalAddress((address) msg));
819 lea(c_rarg1, InternalAddress(rip));
820 movq(c_rarg2, rsp); // pass pointer to regs array
821 andq(rsp, -16); // align stack as required by ABI
822 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
823 hlt();
824 }
825
826 void MacroAssembler::warn(const char* msg) {
827 push(rbp);
828 movq(rbp, rsp);
829 andq(rsp, -16); // align stack as required by push_CPU_state and call
830 push_CPU_state(); // keeps alignment at 16 bytes
831 lea(c_rarg0, ExternalAddress((address) msg));
832 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
833 pop_CPU_state();
834 mov(rsp, rbp);
835 pop(rbp);
836 }
837
838 void MacroAssembler::print_state() {
839 address rip = pc();
840 pusha(); // get regs on stack
841 push(rbp);
842 movq(rbp, rsp);
843 andq(rsp, -16); // align stack as required by push_CPU_state and call
844 push_CPU_state(); // keeps alignment at 16 bytes
845
846 lea(c_rarg0, InternalAddress(rip));
847 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
848 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
849
850 pop_CPU_state();
851 mov(rsp, rbp);
852 pop(rbp);
853 popa();
854 }
855
856 #ifndef PRODUCT
857 extern "C" void findpc(intptr_t x);
858 #endif
859
860 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
861 // In order to get locks to work, we need to fake a in_VM state
862 if (ShowMessageBoxOnError) {
863 JavaThread* thread = JavaThread::current();
864 JavaThreadState saved_state = thread->thread_state();
865 thread->set_thread_state(_thread_in_vm);
866 #ifndef PRODUCT
867 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
868 ttyLocker ttyl;
869 BytecodeCounter::print();
870 }
871 #endif
872 // To see where a verify_oop failed, get $ebx+40/X for this frame.
873 // XXX correct this offset for amd64
874 // This is the value of eip which points to where verify_oop will return.
875 if (os::message_box(msg, "Execution stopped, print registers?")) {
876 print_state64(pc, regs);
877 BREAKPOINT;
878 assert(false, "start up GDB");
879 }
880 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
881 } else {
882 ttyLocker ttyl;
883 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
884 msg);
885 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
886 }
887 }
888
889 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
890 ttyLocker ttyl;
891 FlagSetting fs(Debugging, true);
892 tty->print_cr("rip = 0x%016lx", pc);
893 #ifndef PRODUCT
894 tty->cr();
895 findpc(pc);
896 tty->cr();
897 #endif
898 #define PRINT_REG(rax, value) \
899 { tty->print("%s = ", #rax); os::print_location(tty, value); }
900 PRINT_REG(rax, regs[15]);
901 PRINT_REG(rbx, regs[12]);
902 PRINT_REG(rcx, regs[14]);
903 PRINT_REG(rdx, regs[13]);
904 PRINT_REG(rdi, regs[8]);
905 PRINT_REG(rsi, regs[9]);
906 PRINT_REG(rbp, regs[10]);
907 PRINT_REG(rsp, regs[11]);
908 PRINT_REG(r8 , regs[7]);
909 PRINT_REG(r9 , regs[6]);
910 PRINT_REG(r10, regs[5]);
911 PRINT_REG(r11, regs[4]);
912 PRINT_REG(r12, regs[3]);
913 PRINT_REG(r13, regs[2]);
914 PRINT_REG(r14, regs[1]);
915 PRINT_REG(r15, regs[0]);
916 #undef PRINT_REG
917 // Print some words near top of staack.
918 int64_t* rsp = (int64_t*) regs[11];
919 int64_t* dump_sp = rsp;
920 for (int col1 = 0; col1 < 8; col1++) {
921 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
922 os::print_location(tty, *dump_sp++);
923 }
924 for (int row = 0; row < 25; row++) {
925 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
926 for (int col = 0; col < 4; col++) {
927 tty->print(" 0x%016lx", *dump_sp++);
928 }
929 tty->cr();
930 }
931 // Print some instructions around pc:
932 Disassembler::decode((address)pc-64, (address)pc);
933 tty->print_cr("--------");
934 Disassembler::decode((address)pc, (address)pc+32);
935 }
936
937 #endif // _LP64
938
939 // Now versions that are common to 32/64 bit
940
941 void MacroAssembler::addptr(Register dst, int32_t imm32) {
942 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
943 }
944
945 void MacroAssembler::addptr(Register dst, Register src) {
946 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
947 }
948
949 void MacroAssembler::addptr(Address dst, Register src) {
950 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
951 }
952
953 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
954 if (reachable(src)) {
955 Assembler::addsd(dst, as_Address(src));
956 } else {
957 lea(rscratch1, src);
958 Assembler::addsd(dst, Address(rscratch1, 0));
959 }
960 }
961
962 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
963 if (reachable(src)) {
964 addss(dst, as_Address(src));
965 } else {
966 lea(rscratch1, src);
967 addss(dst, Address(rscratch1, 0));
968 }
969 }
970
971 void MacroAssembler::align(int modulus) {
972 if (offset() % modulus != 0) {
973 nop(modulus - (offset() % modulus));
974 }
975 }
976
977 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
978 // Used in sign-masking with aligned address.
979 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
980 if (reachable(src)) {
981 Assembler::andpd(dst, as_Address(src));
982 } else {
983 lea(rscratch1, src);
984 Assembler::andpd(dst, Address(rscratch1, 0));
985 }
986 }
987
988 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
989 // Used in sign-masking with aligned address.
990 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
991 if (reachable(src)) {
992 Assembler::andps(dst, as_Address(src));
993 } else {
994 lea(rscratch1, src);
995 Assembler::andps(dst, Address(rscratch1, 0));
996 }
997 }
998
999 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1000 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1001 }
1002
1003 void MacroAssembler::atomic_incl(Address counter_addr) {
1004 if (os::is_MP())
1005 lock();
1006 incrementl(counter_addr);
1007 }
1008
1009 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1010 if (reachable(counter_addr)) {
1011 atomic_incl(as_Address(counter_addr));
1012 } else {
1013 lea(scr, counter_addr);
1014 atomic_incl(Address(scr, 0));
1015 }
1016 }
1017
1018 #ifdef _LP64
1019 void MacroAssembler::atomic_incq(Address counter_addr) {
1020 if (os::is_MP())
1021 lock();
1022 incrementq(counter_addr);
1023 }
1024
1025 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1026 if (reachable(counter_addr)) {
1027 atomic_incq(as_Address(counter_addr));
1028 } else {
1029 lea(scr, counter_addr);
1030 atomic_incq(Address(scr, 0));
1031 }
1032 }
1033 #endif
1034
1035 // Writes to stack successive pages until offset reached to check for
1036 // stack overflow + shadow pages. This clobbers tmp.
1037 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1038 movptr(tmp, rsp);
1039 // Bang stack for total size given plus shadow page size.
1040 // Bang one page at a time because large size can bang beyond yellow and
1041 // red zones.
1042 Label loop;
1043 bind(loop);
1044 movl(Address(tmp, (-os::vm_page_size())), size );
1045 subptr(tmp, os::vm_page_size());
1046 subl(size, os::vm_page_size());
1047 jcc(Assembler::greater, loop);
1048
1049 // Bang down shadow pages too.
1050 // At this point, (tmp-0) is the last address touched, so don't
1051 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1052 // was post-decremented.) Skip this address by starting at i=1, and
1053 // touch a few more pages below. N.B. It is important to touch all
1054 // the way down to and including i=StackShadowPages.
1055 for (int i = 1; i < StackShadowPages; i++) {
1056 // this could be any sized move but this is can be a debugging crumb
1057 // so the bigger the better.
1058 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1059 }
1060 }
1061
1062 int MacroAssembler::biased_locking_enter(Register lock_reg,
1063 Register obj_reg,
1064 Register swap_reg,
1065 Register tmp_reg,
1066 bool swap_reg_contains_mark,
1067 Label& done,
1068 Label* slow_case,
1069 BiasedLockingCounters* counters) {
1070 assert(UseBiasedLocking, "why call this otherwise?");
1071 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1072 LP64_ONLY( assert(tmp_reg != noreg, "tmp_reg must be supplied"); )
1073 bool need_tmp_reg = false;
1074 if (tmp_reg == noreg) {
1075 need_tmp_reg = true;
1076 tmp_reg = lock_reg;
1077 assert_different_registers(lock_reg, obj_reg, swap_reg);
1078 } else {
1079 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1080 }
1081 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1082 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1083 Address saved_mark_addr(lock_reg, 0);
1084
1085 if (PrintBiasedLockingStatistics && counters == NULL) {
1086 counters = BiasedLocking::counters();
1087 }
1088 // Biased locking
1089 // See whether the lock is currently biased toward our thread and
1090 // whether the epoch is still valid
1091 // Note that the runtime guarantees sufficient alignment of JavaThread
1092 // pointers to allow age to be placed into low bits
1093 // First check to see whether biasing is even enabled for this object
1094 Label cas_label;
1095 int null_check_offset = -1;
1096 if (!swap_reg_contains_mark) {
1097 null_check_offset = offset();
1098 movptr(swap_reg, mark_addr);
1099 }
1100 if (need_tmp_reg) {
1101 push(tmp_reg);
1102 }
1103 movptr(tmp_reg, swap_reg);
1104 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1105 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1106 if (need_tmp_reg) {
1107 pop(tmp_reg);
1108 }
1109 jcc(Assembler::notEqual, cas_label);
1110 // The bias pattern is present in the object's header. Need to check
1111 // whether the bias owner and the epoch are both still current.
1112 #ifndef _LP64
1113 // Note that because there is no current thread register on x86_32 we
1114 // need to store off the mark word we read out of the object to
1115 // avoid reloading it and needing to recheck invariants below. This
1116 // store is unfortunate but it makes the overall code shorter and
1117 // simpler.
1118 movptr(saved_mark_addr, swap_reg);
1119 #endif
1120 if (need_tmp_reg) {
1121 push(tmp_reg);
1122 }
1123 if (swap_reg_contains_mark) {
1124 null_check_offset = offset();
1125 }
1126 load_prototype_header(tmp_reg, obj_reg);
1127 #ifdef _LP64
1128 orptr(tmp_reg, r15_thread);
1129 xorptr(tmp_reg, swap_reg);
1130 Register header_reg = tmp_reg;
1131 #else
1132 xorptr(tmp_reg, swap_reg);
1133 get_thread(swap_reg);
1134 xorptr(swap_reg, tmp_reg);
1135 Register header_reg = swap_reg;
1136 #endif
1137 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1138 if (need_tmp_reg) {
1139 pop(tmp_reg);
1140 }
1141 if (counters != NULL) {
1142 cond_inc32(Assembler::zero,
1143 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1144 }
1145 jcc(Assembler::equal, done);
1146
1147 Label try_revoke_bias;
1148 Label try_rebias;
1149
1150 // At this point we know that the header has the bias pattern and
1151 // that we are not the bias owner in the current epoch. We need to
1152 // figure out more details about the state of the header in order to
1153 // know what operations can be legally performed on the object's
1154 // header.
1155
1156 // If the low three bits in the xor result aren't clear, that means
1157 // the prototype header is no longer biased and we have to revoke
1158 // the bias on this object.
1159 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1160 jccb(Assembler::notZero, try_revoke_bias);
1161
1162 // Biasing is still enabled for this data type. See whether the
1163 // epoch of the current bias is still valid, meaning that the epoch
1164 // bits of the mark word are equal to the epoch bits of the
1165 // prototype header. (Note that the prototype header's epoch bits
1166 // only change at a safepoint.) If not, attempt to rebias the object
1167 // toward the current thread. Note that we must be absolutely sure
1168 // that the current epoch is invalid in order to do this because
1169 // otherwise the manipulations it performs on the mark word are
1170 // illegal.
1171 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1172 jccb(Assembler::notZero, try_rebias);
1173
1174 // The epoch of the current bias is still valid but we know nothing
1175 // about the owner; it might be set or it might be clear. Try to
1176 // acquire the bias of the object using an atomic operation. If this
1177 // fails we will go in to the runtime to revoke the object's bias.
1178 // Note that we first construct the presumed unbiased header so we
1179 // don't accidentally blow away another thread's valid bias.
1180 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1181 andptr(swap_reg,
1182 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1183 if (need_tmp_reg) {
1184 push(tmp_reg);
1185 }
1186 #ifdef _LP64
1187 movptr(tmp_reg, swap_reg);
1188 orptr(tmp_reg, r15_thread);
1189 #else
1190 get_thread(tmp_reg);
1191 orptr(tmp_reg, swap_reg);
1192 #endif
1193 if (os::is_MP()) {
1194 lock();
1195 }
1196 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1197 if (need_tmp_reg) {
1198 pop(tmp_reg);
1199 }
1200 // If the biasing toward our thread failed, this means that
1201 // another thread succeeded in biasing it toward itself and we
1202 // need to revoke that bias. The revocation will occur in the
1203 // interpreter runtime in the slow case.
1204 if (counters != NULL) {
1205 cond_inc32(Assembler::zero,
1206 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1207 }
1208 if (slow_case != NULL) {
1209 jcc(Assembler::notZero, *slow_case);
1210 }
1211 jmp(done);
1212
1213 bind(try_rebias);
1214 // At this point we know the epoch has expired, meaning that the
1215 // current "bias owner", if any, is actually invalid. Under these
1216 // circumstances _only_, we are allowed to use the current header's
1217 // value as the comparison value when doing the cas to acquire the
1218 // bias in the current epoch. In other words, we allow transfer of
1219 // the bias from one thread to another directly in this situation.
1220 //
1221 // FIXME: due to a lack of registers we currently blow away the age
1222 // bits in this situation. Should attempt to preserve them.
1223 if (need_tmp_reg) {
1224 push(tmp_reg);
1225 }
1226 load_prototype_header(tmp_reg, obj_reg);
1227 #ifdef _LP64
1228 orptr(tmp_reg, r15_thread);
1229 #else
1230 get_thread(swap_reg);
1231 orptr(tmp_reg, swap_reg);
1232 movptr(swap_reg, saved_mark_addr);
1233 #endif
1234 if (os::is_MP()) {
1235 lock();
1236 }
1237 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1238 if (need_tmp_reg) {
1239 pop(tmp_reg);
1240 }
1241 // If the biasing toward our thread failed, then another thread
1242 // succeeded in biasing it toward itself and we need to revoke that
1243 // bias. The revocation will occur in the runtime in the slow case.
1244 if (counters != NULL) {
1245 cond_inc32(Assembler::zero,
1246 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1247 }
1248 if (slow_case != NULL) {
1249 jcc(Assembler::notZero, *slow_case);
1250 }
1251 jmp(done);
1252
1253 bind(try_revoke_bias);
1254 // The prototype mark in the klass doesn't have the bias bit set any
1255 // more, indicating that objects of this data type are not supposed
1256 // to be biased any more. We are going to try to reset the mark of
1257 // this object to the prototype value and fall through to the
1258 // CAS-based locking scheme. Note that if our CAS fails, it means
1259 // that another thread raced us for the privilege of revoking the
1260 // bias of this particular object, so it's okay to continue in the
1261 // normal locking code.
1262 //
1263 // FIXME: due to a lack of registers we currently blow away the age
1264 // bits in this situation. Should attempt to preserve them.
1265 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1266 if (need_tmp_reg) {
1267 push(tmp_reg);
1268 }
1269 load_prototype_header(tmp_reg, obj_reg);
1270 if (os::is_MP()) {
1271 lock();
1272 }
1273 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1274 if (need_tmp_reg) {
1275 pop(tmp_reg);
1276 }
1277 // Fall through to the normal CAS-based lock, because no matter what
1278 // the result of the above CAS, some thread must have succeeded in
1279 // removing the bias bit from the object's header.
1280 if (counters != NULL) {
1281 cond_inc32(Assembler::zero,
1282 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1283 }
1284
1285 bind(cas_label);
1286
1287 return null_check_offset;
1288 }
1289
1290 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1291 assert(UseBiasedLocking, "why call this otherwise?");
1292
1293 // Check for biased locking unlock case, which is a no-op
1294 // Note: we do not have to check the thread ID for two reasons.
1295 // First, the interpreter checks for IllegalMonitorStateException at
1296 // a higher level. Second, if the bias was revoked while we held the
1297 // lock, the object could not be rebiased toward another thread, so
1298 // the bias bit would be clear.
1299 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1300 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1301 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1302 jcc(Assembler::equal, done);
1303 }
1304
1305 #ifdef COMPILER2
1306
1307 #if INCLUDE_RTM_OPT
1308
1309 // Update rtm_counters based on abort status
1310 // input: abort_status
1311 // rtm_counters (RTMLockingCounters*)
1312 // flags are killed
1313 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1314
1315 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1316 if (PrintPreciseRTMLockingStatistics) {
1317 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1318 Label check_abort;
1319 testl(abort_status, (1<<i));
1320 jccb(Assembler::equal, check_abort);
1321 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1322 bind(check_abort);
1323 }
1324 }
1325 }
1326
1327 // Branch if (random & (count-1) != 0), count is 2^n
1328 // tmp, scr and flags are killed
1329 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1330 assert(tmp == rax, "");
1331 assert(scr == rdx, "");
1332 rdtsc(); // modifies EDX:EAX
1333 andptr(tmp, count-1);
1334 jccb(Assembler::notZero, brLabel);
1335 }
1336
1337 // Perform abort ratio calculation, set no_rtm bit if high ratio
1338 // input: rtm_counters_Reg (RTMLockingCounters* address)
1339 // tmpReg, rtm_counters_Reg and flags are killed
1340 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1341 Register rtm_counters_Reg,
1342 RTMLockingCounters* rtm_counters,
1343 Metadata* method_data) {
1344 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1345
1346 if (RTMLockingCalculationDelay > 0) {
1347 // Delay calculation
1348 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1349 testptr(tmpReg, tmpReg);
1350 jccb(Assembler::equal, L_done);
1351 }
1352 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1353 // Aborted transactions = abort_count * 100
1354 // All transactions = total_count * RTMTotalCountIncrRate
1355 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1356
1357 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1358 cmpptr(tmpReg, RTMAbortThreshold);
1359 jccb(Assembler::below, L_check_always_rtm2);
1360 imulptr(tmpReg, tmpReg, 100);
1361
1362 Register scrReg = rtm_counters_Reg;
1363 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1364 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1365 imulptr(scrReg, scrReg, RTMAbortRatio);
1366 cmpptr(tmpReg, scrReg);
1367 jccb(Assembler::below, L_check_always_rtm1);
1368 if (method_data != NULL) {
1369 // set rtm_state to "no rtm" in MDO
1370 mov_metadata(tmpReg, method_data);
1371 if (os::is_MP()) {
1372 lock();
1373 }
1374 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1375 }
1376 jmpb(L_done);
1377 bind(L_check_always_rtm1);
1378 // Reload RTMLockingCounters* address
1379 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1380 bind(L_check_always_rtm2);
1381 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1382 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1383 jccb(Assembler::below, L_done);
1384 if (method_data != NULL) {
1385 // set rtm_state to "always rtm" in MDO
1386 mov_metadata(tmpReg, method_data);
1387 if (os::is_MP()) {
1388 lock();
1389 }
1390 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1391 }
1392 bind(L_done);
1393 }
1394
1395 // Update counters and perform abort ratio calculation
1396 // input: abort_status_Reg
1397 // rtm_counters_Reg, flags are killed
1398 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1399 Register rtm_counters_Reg,
1400 RTMLockingCounters* rtm_counters,
1401 Metadata* method_data,
1402 bool profile_rtm) {
1403
1404 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1405 // update rtm counters based on rax value at abort
1406 // reads abort_status_Reg, updates flags
1407 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1408 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1409 if (profile_rtm) {
1410 // Save abort status because abort_status_Reg is used by following code.
1411 if (RTMRetryCount > 0) {
1412 push(abort_status_Reg);
1413 }
1414 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1415 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1416 // restore abort status
1417 if (RTMRetryCount > 0) {
1418 pop(abort_status_Reg);
1419 }
1420 }
1421 }
1422
1423 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1424 // inputs: retry_count_Reg
1425 // : abort_status_Reg
1426 // output: retry_count_Reg decremented by 1
1427 // flags are killed
1428 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1429 Label doneRetry;
1430 assert(abort_status_Reg == rax, "");
1431 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1432 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1433 // if reason is in 0x6 and retry count != 0 then retry
1434 andptr(abort_status_Reg, 0x6);
1435 jccb(Assembler::zero, doneRetry);
1436 testl(retry_count_Reg, retry_count_Reg);
1437 jccb(Assembler::zero, doneRetry);
1438 pause();
1439 decrementl(retry_count_Reg);
1440 jmp(retryLabel);
1441 bind(doneRetry);
1442 }
1443
1444 // Spin and retry if lock is busy,
1445 // inputs: box_Reg (monitor address)
1446 // : retry_count_Reg
1447 // output: retry_count_Reg decremented by 1
1448 // : clear z flag if retry count exceeded
1449 // tmp_Reg, scr_Reg, flags are killed
1450 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1451 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1452 Label SpinLoop, SpinExit, doneRetry;
1453 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1454
1455 testl(retry_count_Reg, retry_count_Reg);
1456 jccb(Assembler::zero, doneRetry);
1457 decrementl(retry_count_Reg);
1458 movptr(scr_Reg, RTMSpinLoopCount);
1459
1460 bind(SpinLoop);
1461 pause();
1462 decrementl(scr_Reg);
1463 jccb(Assembler::lessEqual, SpinExit);
1464 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1465 testptr(tmp_Reg, tmp_Reg);
1466 jccb(Assembler::notZero, SpinLoop);
1467
1468 bind(SpinExit);
1469 jmp(retryLabel);
1470 bind(doneRetry);
1471 incrementl(retry_count_Reg); // clear z flag
1472 }
1473
1474 // Use RTM for normal stack locks
1475 // Input: objReg (object to lock)
1476 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1477 Register retry_on_abort_count_Reg,
1478 RTMLockingCounters* stack_rtm_counters,
1479 Metadata* method_data, bool profile_rtm,
1480 Label& DONE_LABEL, Label& IsInflated) {
1481 assert(UseRTMForStackLocks, "why call this otherwise?");
1482 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1483 assert(tmpReg == rax, "");
1484 assert(scrReg == rdx, "");
1485 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1486
1487 if (RTMRetryCount > 0) {
1488 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1489 bind(L_rtm_retry);
1490 }
1491 movptr(tmpReg, Address(objReg, 0));
1492 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1493 jcc(Assembler::notZero, IsInflated);
1494
1495 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1496 Label L_noincrement;
1497 if (RTMTotalCountIncrRate > 1) {
1498 // tmpReg, scrReg and flags are killed
1499 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1500 }
1501 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1502 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1503 bind(L_noincrement);
1504 }
1505 xbegin(L_on_abort);
1506 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1507 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1508 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1509 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1510
1511 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1512 if (UseRTMXendForLockBusy) {
1513 xend();
1514 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1515 jmp(L_decrement_retry);
1516 }
1517 else {
1518 xabort(0);
1519 }
1520 bind(L_on_abort);
1521 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1522 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1523 }
1524 bind(L_decrement_retry);
1525 if (RTMRetryCount > 0) {
1526 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1527 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1528 }
1529 }
1530
1531 // Use RTM for inflating locks
1532 // inputs: objReg (object to lock)
1533 // boxReg (on-stack box address (displaced header location) - KILLED)
1534 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1535 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1536 Register scrReg, Register retry_on_busy_count_Reg,
1537 Register retry_on_abort_count_Reg,
1538 RTMLockingCounters* rtm_counters,
1539 Metadata* method_data, bool profile_rtm,
1540 Label& DONE_LABEL) {
1541 assert(UseRTMLocking, "why call this otherwise?");
1542 assert(tmpReg == rax, "");
1543 assert(scrReg == rdx, "");
1544 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1545 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1546
1547 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1548 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1549 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1550
1551 if (RTMRetryCount > 0) {
1552 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1553 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1554 bind(L_rtm_retry);
1555 }
1556 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1557 Label L_noincrement;
1558 if (RTMTotalCountIncrRate > 1) {
1559 // tmpReg, scrReg and flags are killed
1560 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1561 }
1562 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1563 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1564 bind(L_noincrement);
1565 }
1566 xbegin(L_on_abort);
1567 movptr(tmpReg, Address(objReg, 0));
1568 movptr(tmpReg, Address(tmpReg, owner_offset));
1569 testptr(tmpReg, tmpReg);
1570 jcc(Assembler::zero, DONE_LABEL);
1571 if (UseRTMXendForLockBusy) {
1572 xend();
1573 jmp(L_decrement_retry);
1574 }
1575 else {
1576 xabort(0);
1577 }
1578 bind(L_on_abort);
1579 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1580 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1581 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1582 }
1583 if (RTMRetryCount > 0) {
1584 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1585 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1586 }
1587
1588 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1589 testptr(tmpReg, tmpReg) ;
1590 jccb(Assembler::notZero, L_decrement_retry) ;
1591
1592 // Appears unlocked - try to swing _owner from null to non-null.
1593 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1594 #ifdef _LP64
1595 Register threadReg = r15_thread;
1596 #else
1597 get_thread(scrReg);
1598 Register threadReg = scrReg;
1599 #endif
1600 if (os::is_MP()) {
1601 lock();
1602 }
1603 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1604
1605 if (RTMRetryCount > 0) {
1606 // success done else retry
1607 jccb(Assembler::equal, DONE_LABEL) ;
1608 bind(L_decrement_retry);
1609 // Spin and retry if lock is busy.
1610 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1611 }
1612 else {
1613 bind(L_decrement_retry);
1614 }
1615 }
1616
1617 #endif // INCLUDE_RTM_OPT
1618
1619 // Fast_Lock and Fast_Unlock used by C2
1620
1621 // Because the transitions from emitted code to the runtime
1622 // monitorenter/exit helper stubs are so slow it's critical that
1623 // we inline both the stack-locking fast-path and the inflated fast path.
1624 //
1625 // See also: cmpFastLock and cmpFastUnlock.
1626 //
1627 // What follows is a specialized inline transliteration of the code
1628 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1629 // another option would be to emit TrySlowEnter and TrySlowExit methods
1630 // at startup-time. These methods would accept arguments as
1631 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1632 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1633 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1634 // In practice, however, the # of lock sites is bounded and is usually small.
1635 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1636 // if the processor uses simple bimodal branch predictors keyed by EIP
1637 // Since the helper routines would be called from multiple synchronization
1638 // sites.
1639 //
1640 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1641 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1642 // to those specialized methods. That'd give us a mostly platform-independent
1643 // implementation that the JITs could optimize and inline at their pleasure.
1644 // Done correctly, the only time we'd need to cross to native could would be
1645 // to park() or unpark() threads. We'd also need a few more unsafe operators
1646 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1647 // (b) explicit barriers or fence operations.
1648 //
1649 // TODO:
1650 //
1651 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1652 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1653 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1654 // the lock operators would typically be faster than reifying Self.
1655 //
1656 // * Ideally I'd define the primitives as:
1657 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1658 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1659 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1660 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1661 // Furthermore the register assignments are overconstrained, possibly resulting in
1662 // sub-optimal code near the synchronization site.
1663 //
1664 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1665 // Alternately, use a better sp-proximity test.
1666 //
1667 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1668 // Either one is sufficient to uniquely identify a thread.
1669 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1670 //
1671 // * Intrinsify notify() and notifyAll() for the common cases where the
1672 // object is locked by the calling thread but the waitlist is empty.
1673 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1674 //
1675 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1676 // But beware of excessive branch density on AMD Opterons.
1677 //
1678 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1679 // or failure of the fast-path. If the fast-path fails then we pass
1680 // control to the slow-path, typically in C. In Fast_Lock and
1681 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1682 // will emit a conditional branch immediately after the node.
1683 // So we have branches to branches and lots of ICC.ZF games.
1684 // Instead, it might be better to have C2 pass a "FailureLabel"
1685 // into Fast_Lock and Fast_Unlock. In the case of success, control
1686 // will drop through the node. ICC.ZF is undefined at exit.
1687 // In the case of failure, the node will branch directly to the
1688 // FailureLabel
1689
1690
1691 // obj: object to lock
1692 // box: on-stack box address (displaced header location) - KILLED
1693 // rax,: tmp -- KILLED
1694 // scr: tmp -- KILLED
1695 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1696 Register scrReg, Register cx1Reg, Register cx2Reg,
1697 BiasedLockingCounters* counters,
1698 RTMLockingCounters* rtm_counters,
1699 RTMLockingCounters* stack_rtm_counters,
1700 Metadata* method_data,
1701 bool use_rtm, bool profile_rtm) {
1702 // Ensure the register assignents are disjoint
1703 assert(tmpReg == rax, "");
1704
1705 if (use_rtm) {
1706 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1707 } else {
1708 assert(cx1Reg == noreg, "");
1709 assert(cx2Reg == noreg, "");
1710 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1711 }
1712
1713 if (counters != NULL) {
1714 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1715 }
1716 if (EmitSync & 1) {
1717 // set box->dhw = markOopDesc::unused_mark()
1718 // Force all sync thru slow-path: slow_enter() and slow_exit()
1719 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1720 cmpptr (rsp, (int32_t)NULL_WORD);
1721 } else {
1722 // Possible cases that we'll encounter in fast_lock
1723 // ------------------------------------------------
1724 // * Inflated
1725 // -- unlocked
1726 // -- Locked
1727 // = by self
1728 // = by other
1729 // * biased
1730 // -- by Self
1731 // -- by other
1732 // * neutral
1733 // * stack-locked
1734 // -- by self
1735 // = sp-proximity test hits
1736 // = sp-proximity test generates false-negative
1737 // -- by other
1738 //
1739
1740 Label IsInflated, DONE_LABEL;
1741
1742 // it's stack-locked, biased or neutral
1743 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1744 // order to reduce the number of conditional branches in the most common cases.
1745 // Beware -- there's a subtle invariant that fetch of the markword
1746 // at [FETCH], below, will never observe a biased encoding (*101b).
1747 // If this invariant is not held we risk exclusion (safety) failure.
1748 if (UseBiasedLocking && !UseOptoBiasInlining) {
1749 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1750 }
1751
1752 #if INCLUDE_RTM_OPT
1753 if (UseRTMForStackLocks && use_rtm) {
1754 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1755 stack_rtm_counters, method_data, profile_rtm,
1756 DONE_LABEL, IsInflated);
1757 }
1758 #endif // INCLUDE_RTM_OPT
1759
1760 movptr(tmpReg, Address(objReg, 0)); // [FETCH]
1761 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1762 jccb(Assembler::notZero, IsInflated);
1763
1764 // Attempt stack-locking ...
1765 orptr (tmpReg, markOopDesc::unlocked_value);
1766 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1767 if (os::is_MP()) {
1768 lock();
1769 }
1770 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1771 if (counters != NULL) {
1772 cond_inc32(Assembler::equal,
1773 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1774 }
1775 jcc(Assembler::equal, DONE_LABEL); // Success
1776
1777 // Recursive locking.
1778 // The object is stack-locked: markword contains stack pointer to BasicLock.
1779 // Locked by current thread if difference with current SP is less than one page.
1780 subptr(tmpReg, rsp);
1781 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1782 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1783 movptr(Address(boxReg, 0), tmpReg);
1784 if (counters != NULL) {
1785 cond_inc32(Assembler::equal,
1786 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1787 }
1788 jmp(DONE_LABEL);
1789
1790 bind(IsInflated);
1791 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1792
1793 #if INCLUDE_RTM_OPT
1794 // Use the same RTM locking code in 32- and 64-bit VM.
1795 if (use_rtm) {
1796 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1797 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1798 } else {
1799 #endif // INCLUDE_RTM_OPT
1800
1801 #ifndef _LP64
1802 // The object is inflated.
1803
1804 // boxReg refers to the on-stack BasicLock in the current frame.
1805 // We'd like to write:
1806 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1807 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1808 // additional latency as we have another ST in the store buffer that must drain.
1809
1810 if (EmitSync & 8192) {
1811 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1812 get_thread (scrReg);
1813 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1814 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1815 if (os::is_MP()) {
1816 lock();
1817 }
1818 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1819 } else
1820 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1821 movptr(scrReg, boxReg);
1822 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1823
1824 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1825 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1826 // prefetchw [eax + Offset(_owner)-2]
1827 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1828 }
1829
1830 if ((EmitSync & 64) == 0) {
1831 // Optimistic form: consider XORL tmpReg,tmpReg
1832 movptr(tmpReg, NULL_WORD);
1833 } else {
1834 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1835 // Test-And-CAS instead of CAS
1836 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1837 testptr(tmpReg, tmpReg); // Locked ?
1838 jccb (Assembler::notZero, DONE_LABEL);
1839 }
1840
1841 // Appears unlocked - try to swing _owner from null to non-null.
1842 // Ideally, I'd manifest "Self" with get_thread and then attempt
1843 // to CAS the register containing Self into m->Owner.
1844 // But we don't have enough registers, so instead we can either try to CAS
1845 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1846 // we later store "Self" into m->Owner. Transiently storing a stack address
1847 // (rsp or the address of the box) into m->owner is harmless.
1848 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1849 if (os::is_MP()) {
1850 lock();
1851 }
1852 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1853 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1854 jccb (Assembler::notZero, DONE_LABEL);
1855 get_thread (scrReg); // beware: clobbers ICCs
1856 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1857 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1858
1859 // If the CAS fails we can either retry or pass control to the slow-path.
1860 // We use the latter tactic.
1861 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1862 // If the CAS was successful ...
1863 // Self has acquired the lock
1864 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1865 // Intentional fall-through into DONE_LABEL ...
1866 } else {
1867 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1868 movptr(boxReg, tmpReg);
1869
1870 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1871 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1872 // prefetchw [eax + Offset(_owner)-2]
1873 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1874 }
1875
1876 if ((EmitSync & 64) == 0) {
1877 // Optimistic form
1878 xorptr (tmpReg, tmpReg);
1879 } else {
1880 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1881 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1882 testptr(tmpReg, tmpReg); // Locked ?
1883 jccb (Assembler::notZero, DONE_LABEL);
1884 }
1885
1886 // Appears unlocked - try to swing _owner from null to non-null.
1887 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1888 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1889 get_thread (scrReg);
1890 if (os::is_MP()) {
1891 lock();
1892 }
1893 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1894
1895 // If the CAS fails we can either retry or pass control to the slow-path.
1896 // We use the latter tactic.
1897 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1898 // If the CAS was successful ...
1899 // Self has acquired the lock
1900 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1901 // Intentional fall-through into DONE_LABEL ...
1902 }
1903 #else // _LP64
1904 // It's inflated
1905 movq(scrReg, tmpReg);
1906 xorq(tmpReg, tmpReg);
1907
1908 if (os::is_MP()) {
1909 lock();
1910 }
1911 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1912 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1913 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1914 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1915 // Intentional fall-through into DONE_LABEL ...
1916 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1917 #endif // _LP64
1918 #if INCLUDE_RTM_OPT
1919 } // use_rtm()
1920 #endif
1921 // DONE_LABEL is a hot target - we'd really like to place it at the
1922 // start of cache line by padding with NOPs.
1923 // See the AMD and Intel software optimization manuals for the
1924 // most efficient "long" NOP encodings.
1925 // Unfortunately none of our alignment mechanisms suffice.
1926 bind(DONE_LABEL);
1927
1928 // At DONE_LABEL the icc ZFlag is set as follows ...
1929 // Fast_Unlock uses the same protocol.
1930 // ZFlag == 1 -> Success
1931 // ZFlag == 0 -> Failure - force control through the slow-path
1932 }
1933 }
1934
1935 // obj: object to unlock
1936 // box: box address (displaced header location), killed. Must be EAX.
1937 // tmp: killed, cannot be obj nor box.
1938 //
1939 // Some commentary on balanced locking:
1940 //
1941 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1942 // Methods that don't have provably balanced locking are forced to run in the
1943 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1944 // The interpreter provides two properties:
1945 // I1: At return-time the interpreter automatically and quietly unlocks any
1946 // objects acquired the current activation (frame). Recall that the
1947 // interpreter maintains an on-stack list of locks currently held by
1948 // a frame.
1949 // I2: If a method attempts to unlock an object that is not held by the
1950 // the frame the interpreter throws IMSX.
1951 //
1952 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1953 // B() doesn't have provably balanced locking so it runs in the interpreter.
1954 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1955 // is still locked by A().
1956 //
1957 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1958 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1959 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1960 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1961
1962 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1963 assert(boxReg == rax, "");
1964 assert_different_registers(objReg, boxReg, tmpReg);
1965
1966 if (EmitSync & 4) {
1967 // Disable - inhibit all inlining. Force control through the slow-path
1968 cmpptr (rsp, 0);
1969 } else
1970 if (EmitSync & 8) {
1971 Label DONE_LABEL;
1972 if (UseBiasedLocking) {
1973 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1974 }
1975 // Classic stack-locking code ...
1976 // Check whether the displaced header is 0
1977 //(=> recursive unlock)
1978 movptr(tmpReg, Address(boxReg, 0));
1979 testptr(tmpReg, tmpReg);
1980 jccb(Assembler::zero, DONE_LABEL);
1981 // If not recursive lock, reset the header to displaced header
1982 if (os::is_MP()) {
1983 lock();
1984 }
1985 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
1986 bind(DONE_LABEL);
1987 } else {
1988 Label DONE_LABEL, Stacked, CheckSucc;
1989
1990 // Critically, the biased locking test must have precedence over
1991 // and appear before the (box->dhw == 0) recursive stack-lock test.
1992 if (UseBiasedLocking && !UseOptoBiasInlining) {
1993 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1994 }
1995
1996 #if INCLUDE_RTM_OPT
1997 if (UseRTMForStackLocks && use_rtm) {
1998 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1999 Label L_regular_unlock;
2000 movptr(tmpReg, Address(objReg, 0)); // fetch markword
2001 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
2002 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
2003 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
2004 xend(); // otherwise end...
2005 jmp(DONE_LABEL); // ... and we're done
2006 bind(L_regular_unlock);
2007 }
2008 #endif
2009
2010 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
2011 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
2012 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword
2013 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2014 jccb (Assembler::zero, Stacked);
2015
2016 // It's inflated.
2017 #if INCLUDE_RTM_OPT
2018 if (use_rtm) {
2019 Label L_regular_inflated_unlock;
2020 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2021 movptr(boxReg, Address(tmpReg, owner_offset));
2022 testptr(boxReg, boxReg);
2023 jccb(Assembler::notZero, L_regular_inflated_unlock);
2024 xend();
2025 jmpb(DONE_LABEL);
2026 bind(L_regular_inflated_unlock);
2027 }
2028 #endif
2029
2030 // Despite our balanced locking property we still check that m->_owner == Self
2031 // as java routines or native JNI code called by this thread might
2032 // have released the lock.
2033 // Refer to the comments in synchronizer.cpp for how we might encode extra
2034 // state in _succ so we can avoid fetching EntryList|cxq.
2035 //
2036 // I'd like to add more cases in fast_lock() and fast_unlock() --
2037 // such as recursive enter and exit -- but we have to be wary of
2038 // I$ bloat, T$ effects and BP$ effects.
2039 //
2040 // If there's no contention try a 1-0 exit. That is, exit without
2041 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2042 // we detect and recover from the race that the 1-0 exit admits.
2043 //
2044 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2045 // before it STs null into _owner, releasing the lock. Updates
2046 // to data protected by the critical section must be visible before
2047 // we drop the lock (and thus before any other thread could acquire
2048 // the lock and observe the fields protected by the lock).
2049 // IA32's memory-model is SPO, so STs are ordered with respect to
2050 // each other and there's no need for an explicit barrier (fence).
2051 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2052 #ifndef _LP64
2053 get_thread (boxReg);
2054 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2055 // prefetchw [ebx + Offset(_owner)-2]
2056 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2057 }
2058
2059 // Note that we could employ various encoding schemes to reduce
2060 // the number of loads below (currently 4) to just 2 or 3.
2061 // Refer to the comments in synchronizer.cpp.
2062 // In practice the chain of fetches doesn't seem to impact performance, however.
2063 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2064 // Attempt to reduce branch density - AMD's branch predictor.
2065 xorptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2066 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2067 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2068 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2069 jccb (Assembler::notZero, DONE_LABEL);
2070 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2071 jmpb (DONE_LABEL);
2072 } else {
2073 xorptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2074 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2075 jccb (Assembler::notZero, DONE_LABEL);
2076 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2077 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2078 jccb (Assembler::notZero, CheckSucc);
2079 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2080 jmpb (DONE_LABEL);
2081 }
2082
2083 // The Following code fragment (EmitSync & 65536) improves the performance of
2084 // contended applications and contended synchronization microbenchmarks.
2085 // Unfortunately the emission of the code - even though not executed - causes regressions
2086 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2087 // with an equal number of never-executed NOPs results in the same regression.
2088 // We leave it off by default.
2089
2090 if ((EmitSync & 65536) != 0) {
2091 Label LSuccess, LGoSlowPath ;
2092
2093 bind (CheckSucc);
2094
2095 // Optional pre-test ... it's safe to elide this
2096 if ((EmitSync & 16) == 0) {
2097 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2098 jccb (Assembler::zero, LGoSlowPath);
2099 }
2100
2101 // We have a classic Dekker-style idiom:
2102 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2103 // There are a number of ways to implement the barrier:
2104 // (1) lock:andl &m->_owner, 0
2105 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2106 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2107 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2108 // (2) If supported, an explicit MFENCE is appealing.
2109 // In older IA32 processors MFENCE is slower than lock:add or xchg
2110 // particularly if the write-buffer is full as might be the case if
2111 // if stores closely precede the fence or fence-equivalent instruction.
2112 // In more modern implementations MFENCE appears faster, however.
2113 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2114 // The $lines underlying the top-of-stack should be in M-state.
2115 // The locked add instruction is serializing, of course.
2116 // (4) Use xchg, which is serializing
2117 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2118 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2119 // The integer condition codes will tell us if succ was 0.
2120 // Since _succ and _owner should reside in the same $line and
2121 // we just stored into _owner, it's likely that the $line
2122 // remains in M-state for the lock:orl.
2123 //
2124 // We currently use (3), although it's likely that switching to (2)
2125 // is correct for the future.
2126
2127 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2128 if (os::is_MP()) {
2129 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
2130 mfence();
2131 } else {
2132 lock (); addptr(Address(rsp, 0), 0);
2133 }
2134 }
2135 // Ratify _succ remains non-null
2136 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2137 jccb (Assembler::notZero, LSuccess);
2138
2139 xorptr(boxReg, boxReg); // box is really EAX
2140 if (os::is_MP()) { lock(); }
2141 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2142 jccb (Assembler::notEqual, LSuccess);
2143 // Since we're low on registers we installed rsp as a placeholding in _owner.
2144 // Now install Self over rsp. This is safe as we're transitioning from
2145 // non-null to non=null
2146 get_thread (boxReg);
2147 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2148 // Intentional fall-through into LGoSlowPath ...
2149
2150 bind (LGoSlowPath);
2151 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2152 jmpb (DONE_LABEL);
2153
2154 bind (LSuccess);
2155 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2156 jmpb (DONE_LABEL);
2157 }
2158
2159 bind (Stacked);
2160 // It's not inflated and it's not recursively stack-locked and it's not biased.
2161 // It must be stack-locked.
2162 // Try to reset the header to displaced header.
2163 // The "box" value on the stack is stable, so we can reload
2164 // and be assured we observe the same value as above.
2165 movptr(tmpReg, Address(boxReg, 0));
2166 if (os::is_MP()) {
2167 lock();
2168 }
2169 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2170 // Intention fall-thru into DONE_LABEL
2171
2172 // DONE_LABEL is a hot target - we'd really like to place it at the
2173 // start of cache line by padding with NOPs.
2174 // See the AMD and Intel software optimization manuals for the
2175 // most efficient "long" NOP encodings.
2176 // Unfortunately none of our alignment mechanisms suffice.
2177 if ((EmitSync & 65536) == 0) {
2178 bind (CheckSucc);
2179 }
2180 #else // _LP64
2181 // It's inflated
2182 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2183 xorptr(boxReg, r15_thread);
2184 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2185 jccb (Assembler::notZero, DONE_LABEL);
2186 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2187 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2188 jccb (Assembler::notZero, CheckSucc);
2189 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2190 jmpb (DONE_LABEL);
2191
2192 if ((EmitSync & 65536) == 0) {
2193 Label LSuccess, LGoSlowPath ;
2194 bind (CheckSucc);
2195 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2196 jccb (Assembler::zero, LGoSlowPath);
2197
2198 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
2199 // the explicit ST;MEMBAR combination, but masm doesn't currently support
2200 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
2201 // are all faster when the write buffer is populated.
2202 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2203 if (os::is_MP()) {
2204 lock (); addl (Address(rsp, 0), 0);
2205 }
2206 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2207 jccb (Assembler::notZero, LSuccess);
2208
2209 movptr (boxReg, (int32_t)NULL_WORD); // box is really EAX
2210 if (os::is_MP()) { lock(); }
2211 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2212 jccb (Assembler::notEqual, LSuccess);
2213 // Intentional fall-through into slow-path
2214
2215 bind (LGoSlowPath);
2216 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2217 jmpb (DONE_LABEL);
2218
2219 bind (LSuccess);
2220 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2221 jmpb (DONE_LABEL);
2222 }
2223
2224 bind (Stacked);
2225 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2226 if (os::is_MP()) { lock(); }
2227 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2228
2229 if (EmitSync & 65536) {
2230 bind (CheckSucc);
2231 }
2232 #endif
2233 bind(DONE_LABEL);
2234 // Avoid branch to branch on AMD processors
2235 if (EmitSync & 32768) {
2236 nop();
2237 }
2238 }
2239 }
2240 #endif // COMPILER2
2241
2242 void MacroAssembler::c2bool(Register x) {
2243 // implements x == 0 ? 0 : 1
2244 // note: must only look at least-significant byte of x
2245 // since C-style booleans are stored in one byte
2246 // only! (was bug)
2247 andl(x, 0xFF);
2248 setb(Assembler::notZero, x);
2249 }
2250
2251 // Wouldn't need if AddressLiteral version had new name
2252 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2253 Assembler::call(L, rtype);
2254 }
2255
2256 void MacroAssembler::call(Register entry) {
2257 Assembler::call(entry);
2258 }
2259
2260 void MacroAssembler::call(AddressLiteral entry) {
2261 if (reachable(entry)) {
2262 Assembler::call_literal(entry.target(), entry.rspec());
2263 } else {
2264 lea(rscratch1, entry);
2265 Assembler::call(rscratch1);
2266 }
2267 }
2268
2269 void MacroAssembler::ic_call(address entry) {
2270 RelocationHolder rh = virtual_call_Relocation::spec(pc());
2271 movptr(rax, (intptr_t)Universe::non_oop_word());
2272 call(AddressLiteral(entry, rh));
2273 }
2274
2275 // Implementation of call_VM versions
2276
2277 void MacroAssembler::call_VM(Register oop_result,
2278 address entry_point,
2279 bool check_exceptions) {
2280 Label C, E;
2281 call(C, relocInfo::none);
2282 jmp(E);
2283
2284 bind(C);
2285 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2286 ret(0);
2287
2288 bind(E);
2289 }
2290
2291 void MacroAssembler::call_VM(Register oop_result,
2292 address entry_point,
2293 Register arg_1,
2294 bool check_exceptions) {
2295 Label C, E;
2296 call(C, relocInfo::none);
2297 jmp(E);
2298
2299 bind(C);
2300 pass_arg1(this, arg_1);
2301 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2302 ret(0);
2303
2304 bind(E);
2305 }
2306
2307 void MacroAssembler::call_VM(Register oop_result,
2308 address entry_point,
2309 Register arg_1,
2310 Register arg_2,
2311 bool check_exceptions) {
2312 Label C, E;
2313 call(C, relocInfo::none);
2314 jmp(E);
2315
2316 bind(C);
2317
2318 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2319
2320 pass_arg2(this, arg_2);
2321 pass_arg1(this, arg_1);
2322 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2323 ret(0);
2324
2325 bind(E);
2326 }
2327
2328 void MacroAssembler::call_VM(Register oop_result,
2329 address entry_point,
2330 Register arg_1,
2331 Register arg_2,
2332 Register arg_3,
2333 bool check_exceptions) {
2334 Label C, E;
2335 call(C, relocInfo::none);
2336 jmp(E);
2337
2338 bind(C);
2339
2340 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2341 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2342 pass_arg3(this, arg_3);
2343
2344 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2345 pass_arg2(this, arg_2);
2346
2347 pass_arg1(this, arg_1);
2348 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2349 ret(0);
2350
2351 bind(E);
2352 }
2353
2354 void MacroAssembler::call_VM(Register oop_result,
2355 Register last_java_sp,
2356 address entry_point,
2357 int number_of_arguments,
2358 bool check_exceptions) {
2359 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2360 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2361 }
2362
2363 void MacroAssembler::call_VM(Register oop_result,
2364 Register last_java_sp,
2365 address entry_point,
2366 Register arg_1,
2367 bool check_exceptions) {
2368 pass_arg1(this, arg_1);
2369 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2370 }
2371
2372 void MacroAssembler::call_VM(Register oop_result,
2373 Register last_java_sp,
2374 address entry_point,
2375 Register arg_1,
2376 Register arg_2,
2377 bool check_exceptions) {
2378
2379 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2380 pass_arg2(this, arg_2);
2381 pass_arg1(this, arg_1);
2382 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2383 }
2384
2385 void MacroAssembler::call_VM(Register oop_result,
2386 Register last_java_sp,
2387 address entry_point,
2388 Register arg_1,
2389 Register arg_2,
2390 Register arg_3,
2391 bool check_exceptions) {
2392 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2393 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2394 pass_arg3(this, arg_3);
2395 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2396 pass_arg2(this, arg_2);
2397 pass_arg1(this, arg_1);
2398 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2399 }
2400
2401 void MacroAssembler::super_call_VM(Register oop_result,
2402 Register last_java_sp,
2403 address entry_point,
2404 int number_of_arguments,
2405 bool check_exceptions) {
2406 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2407 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2408 }
2409
2410 void MacroAssembler::super_call_VM(Register oop_result,
2411 Register last_java_sp,
2412 address entry_point,
2413 Register arg_1,
2414 bool check_exceptions) {
2415 pass_arg1(this, arg_1);
2416 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2417 }
2418
2419 void MacroAssembler::super_call_VM(Register oop_result,
2420 Register last_java_sp,
2421 address entry_point,
2422 Register arg_1,
2423 Register arg_2,
2424 bool check_exceptions) {
2425
2426 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2427 pass_arg2(this, arg_2);
2428 pass_arg1(this, arg_1);
2429 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2430 }
2431
2432 void MacroAssembler::super_call_VM(Register oop_result,
2433 Register last_java_sp,
2434 address entry_point,
2435 Register arg_1,
2436 Register arg_2,
2437 Register arg_3,
2438 bool check_exceptions) {
2439 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2440 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2441 pass_arg3(this, arg_3);
2442 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2443 pass_arg2(this, arg_2);
2444 pass_arg1(this, arg_1);
2445 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2446 }
2447
2448 void MacroAssembler::call_VM_base(Register oop_result,
2449 Register java_thread,
2450 Register last_java_sp,
2451 address entry_point,
2452 int number_of_arguments,
2453 bool check_exceptions) {
2454 // determine java_thread register
2455 if (!java_thread->is_valid()) {
2456 #ifdef _LP64
2457 java_thread = r15_thread;
2458 #else
2459 java_thread = rdi;
2460 get_thread(java_thread);
2461 #endif // LP64
2462 }
2463 // determine last_java_sp register
2464 if (!last_java_sp->is_valid()) {
2465 last_java_sp = rsp;
2466 }
2467 // debugging support
2468 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2469 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2470 #ifdef ASSERT
2471 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2472 // r12 is the heapbase.
2473 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2474 #endif // ASSERT
2475
2476 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2477 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2478
2479 // push java thread (becomes first argument of C function)
2480
2481 NOT_LP64(push(java_thread); number_of_arguments++);
2482 LP64_ONLY(mov(c_rarg0, r15_thread));
2483
2484 // set last Java frame before call
2485 assert(last_java_sp != rbp, "can't use ebp/rbp");
2486
2487 // Only interpreter should have to set fp
2488 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2489
2490 // do the call, remove parameters
2491 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2492
2493 // restore the thread (cannot use the pushed argument since arguments
2494 // may be overwritten by C code generated by an optimizing compiler);
2495 // however can use the register value directly if it is callee saved.
2496 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2497 // rdi & rsi (also r15) are callee saved -> nothing to do
2498 #ifdef ASSERT
2499 guarantee(java_thread != rax, "change this code");
2500 push(rax);
2501 { Label L;
2502 get_thread(rax);
2503 cmpptr(java_thread, rax);
2504 jcc(Assembler::equal, L);
2505 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2506 bind(L);
2507 }
2508 pop(rax);
2509 #endif
2510 } else {
2511 get_thread(java_thread);
2512 }
2513 // reset last Java frame
2514 // Only interpreter should have to clear fp
2515 reset_last_Java_frame(java_thread, true, false);
2516
2517 #ifndef CC_INTERP
2518 // C++ interp handles this in the interpreter
2519 check_and_handle_popframe(java_thread);
2520 check_and_handle_earlyret(java_thread);
2521 #endif /* CC_INTERP */
2522
2523 if (check_exceptions) {
2524 // check for pending exceptions (java_thread is set upon return)
2525 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2526 #ifndef _LP64
2527 jump_cc(Assembler::notEqual,
2528 RuntimeAddress(StubRoutines::forward_exception_entry()));
2529 #else
2530 // This used to conditionally jump to forward_exception however it is
2531 // possible if we relocate that the branch will not reach. So we must jump
2532 // around so we can always reach
2533
2534 Label ok;
2535 jcc(Assembler::equal, ok);
2536 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2537 bind(ok);
2538 #endif // LP64
2539 }
2540
2541 // get oop result if there is one and reset the value in the thread
2542 if (oop_result->is_valid()) {
2543 get_vm_result(oop_result, java_thread);
2544 }
2545 }
2546
2547 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2548
2549 // Calculate the value for last_Java_sp
2550 // somewhat subtle. call_VM does an intermediate call
2551 // which places a return address on the stack just under the
2552 // stack pointer as the user finsihed with it. This allows
2553 // use to retrieve last_Java_pc from last_Java_sp[-1].
2554 // On 32bit we then have to push additional args on the stack to accomplish
2555 // the actual requested call. On 64bit call_VM only can use register args
2556 // so the only extra space is the return address that call_VM created.
2557 // This hopefully explains the calculations here.
2558
2559 #ifdef _LP64
2560 // We've pushed one address, correct last_Java_sp
2561 lea(rax, Address(rsp, wordSize));
2562 #else
2563 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2564 #endif // LP64
2565
2566 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2567
2568 }
2569
2570 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2571 call_VM_leaf_base(entry_point, number_of_arguments);
2572 }
2573
2574 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2575 pass_arg0(this, arg_0);
2576 call_VM_leaf(entry_point, 1);
2577 }
2578
2579 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2580
2581 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2582 pass_arg1(this, arg_1);
2583 pass_arg0(this, arg_0);
2584 call_VM_leaf(entry_point, 2);
2585 }
2586
2587 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2588 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2589 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2590 pass_arg2(this, arg_2);
2591 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2592 pass_arg1(this, arg_1);
2593 pass_arg0(this, arg_0);
2594 call_VM_leaf(entry_point, 3);
2595 }
2596
2597 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2598 pass_arg0(this, arg_0);
2599 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2600 }
2601
2602 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2603
2604 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2605 pass_arg1(this, arg_1);
2606 pass_arg0(this, arg_0);
2607 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2608 }
2609
2610 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2611 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2612 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2613 pass_arg2(this, arg_2);
2614 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2615 pass_arg1(this, arg_1);
2616 pass_arg0(this, arg_0);
2617 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2618 }
2619
2620 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2621 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2622 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2623 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2624 pass_arg3(this, arg_3);
2625 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2626 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2627 pass_arg2(this, arg_2);
2628 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2629 pass_arg1(this, arg_1);
2630 pass_arg0(this, arg_0);
2631 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2632 }
2633
2634 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2635 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2636 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2637 verify_oop(oop_result, "broken oop in call_VM_base");
2638 }
2639
2640 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2641 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2642 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2643 }
2644
2645 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2646 }
2647
2648 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2649 }
2650
2651 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2652 if (reachable(src1)) {
2653 cmpl(as_Address(src1), imm);
2654 } else {
2655 lea(rscratch1, src1);
2656 cmpl(Address(rscratch1, 0), imm);
2657 }
2658 }
2659
2660 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2661 assert(!src2.is_lval(), "use cmpptr");
2662 if (reachable(src2)) {
2663 cmpl(src1, as_Address(src2));
2664 } else {
2665 lea(rscratch1, src2);
2666 cmpl(src1, Address(rscratch1, 0));
2667 }
2668 }
2669
2670 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2671 Assembler::cmpl(src1, imm);
2672 }
2673
2674 void MacroAssembler::cmp32(Register src1, Address src2) {
2675 Assembler::cmpl(src1, src2);
2676 }
2677
2678 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2679 ucomisd(opr1, opr2);
2680
2681 Label L;
2682 if (unordered_is_less) {
2683 movl(dst, -1);
2684 jcc(Assembler::parity, L);
2685 jcc(Assembler::below , L);
2686 movl(dst, 0);
2687 jcc(Assembler::equal , L);
2688 increment(dst);
2689 } else { // unordered is greater
2690 movl(dst, 1);
2691 jcc(Assembler::parity, L);
2692 jcc(Assembler::above , L);
2693 movl(dst, 0);
2694 jcc(Assembler::equal , L);
2695 decrementl(dst);
2696 }
2697 bind(L);
2698 }
2699
2700 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2701 ucomiss(opr1, opr2);
2702
2703 Label L;
2704 if (unordered_is_less) {
2705 movl(dst, -1);
2706 jcc(Assembler::parity, L);
2707 jcc(Assembler::below , L);
2708 movl(dst, 0);
2709 jcc(Assembler::equal , L);
2710 increment(dst);
2711 } else { // unordered is greater
2712 movl(dst, 1);
2713 jcc(Assembler::parity, L);
2714 jcc(Assembler::above , L);
2715 movl(dst, 0);
2716 jcc(Assembler::equal , L);
2717 decrementl(dst);
2718 }
2719 bind(L);
2720 }
2721
2722
2723 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2724 if (reachable(src1)) {
2725 cmpb(as_Address(src1), imm);
2726 } else {
2727 lea(rscratch1, src1);
2728 cmpb(Address(rscratch1, 0), imm);
2729 }
2730 }
2731
2732 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2733 #ifdef _LP64
2734 if (src2.is_lval()) {
2735 movptr(rscratch1, src2);
2736 Assembler::cmpq(src1, rscratch1);
2737 } else if (reachable(src2)) {
2738 cmpq(src1, as_Address(src2));
2739 } else {
2740 lea(rscratch1, src2);
2741 Assembler::cmpq(src1, Address(rscratch1, 0));
2742 }
2743 #else
2744 if (src2.is_lval()) {
2745 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2746 } else {
2747 cmpl(src1, as_Address(src2));
2748 }
2749 #endif // _LP64
2750 }
2751
2752 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2753 assert(src2.is_lval(), "not a mem-mem compare");
2754 #ifdef _LP64
2755 // moves src2's literal address
2756 movptr(rscratch1, src2);
2757 Assembler::cmpq(src1, rscratch1);
2758 #else
2759 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2760 #endif // _LP64
2761 }
2762
2763 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2764 if (reachable(adr)) {
2765 if (os::is_MP())
2766 lock();
2767 cmpxchgptr(reg, as_Address(adr));
2768 } else {
2769 lea(rscratch1, adr);
2770 if (os::is_MP())
2771 lock();
2772 cmpxchgptr(reg, Address(rscratch1, 0));
2773 }
2774 }
2775
2776 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2777 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2778 }
2779
2780 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2781 if (reachable(src)) {
2782 Assembler::comisd(dst, as_Address(src));
2783 } else {
2784 lea(rscratch1, src);
2785 Assembler::comisd(dst, Address(rscratch1, 0));
2786 }
2787 }
2788
2789 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2790 if (reachable(src)) {
2791 Assembler::comiss(dst, as_Address(src));
2792 } else {
2793 lea(rscratch1, src);
2794 Assembler::comiss(dst, Address(rscratch1, 0));
2795 }
2796 }
2797
2798
2799 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2800 Condition negated_cond = negate_condition(cond);
2801 Label L;
2802 jcc(negated_cond, L);
2803 pushf(); // Preserve flags
2804 atomic_incl(counter_addr);
2805 popf();
2806 bind(L);
2807 }
2808
2809 int MacroAssembler::corrected_idivl(Register reg) {
2810 // Full implementation of Java idiv and irem; checks for
2811 // special case as described in JVM spec., p.243 & p.271.
2812 // The function returns the (pc) offset of the idivl
2813 // instruction - may be needed for implicit exceptions.
2814 //
2815 // normal case special case
2816 //
2817 // input : rax,: dividend min_int
2818 // reg: divisor (may not be rax,/rdx) -1
2819 //
2820 // output: rax,: quotient (= rax, idiv reg) min_int
2821 // rdx: remainder (= rax, irem reg) 0
2822 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2823 const int min_int = 0x80000000;
2824 Label normal_case, special_case;
2825
2826 // check for special case
2827 cmpl(rax, min_int);
2828 jcc(Assembler::notEqual, normal_case);
2829 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2830 cmpl(reg, -1);
2831 jcc(Assembler::equal, special_case);
2832
2833 // handle normal case
2834 bind(normal_case);
2835 cdql();
2836 int idivl_offset = offset();
2837 idivl(reg);
2838
2839 // normal and special case exit
2840 bind(special_case);
2841
2842 return idivl_offset;
2843 }
2844
2845
2846
2847 void MacroAssembler::decrementl(Register reg, int value) {
2848 if (value == min_jint) {subl(reg, value) ; return; }
2849 if (value < 0) { incrementl(reg, -value); return; }
2850 if (value == 0) { ; return; }
2851 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2852 /* else */ { subl(reg, value) ; return; }
2853 }
2854
2855 void MacroAssembler::decrementl(Address dst, int value) {
2856 if (value == min_jint) {subl(dst, value) ; return; }
2857 if (value < 0) { incrementl(dst, -value); return; }
2858 if (value == 0) { ; return; }
2859 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2860 /* else */ { subl(dst, value) ; return; }
2861 }
2862
2863 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2864 assert (shift_value > 0, "illegal shift value");
2865 Label _is_positive;
2866 testl (reg, reg);
2867 jcc (Assembler::positive, _is_positive);
2868 int offset = (1 << shift_value) - 1 ;
2869
2870 if (offset == 1) {
2871 incrementl(reg);
2872 } else {
2873 addl(reg, offset);
2874 }
2875
2876 bind (_is_positive);
2877 sarl(reg, shift_value);
2878 }
2879
2880 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2881 if (reachable(src)) {
2882 Assembler::divsd(dst, as_Address(src));
2883 } else {
2884 lea(rscratch1, src);
2885 Assembler::divsd(dst, Address(rscratch1, 0));
2886 }
2887 }
2888
2889 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2890 if (reachable(src)) {
2891 Assembler::divss(dst, as_Address(src));
2892 } else {
2893 lea(rscratch1, src);
2894 Assembler::divss(dst, Address(rscratch1, 0));
2895 }
2896 }
2897
2898 // !defined(COMPILER2) is because of stupid core builds
2899 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
2900 void MacroAssembler::empty_FPU_stack() {
2901 if (VM_Version::supports_mmx()) {
2902 emms();
2903 } else {
2904 for (int i = 8; i-- > 0; ) ffree(i);
2905 }
2906 }
2907 #endif // !LP64 || C1 || !C2
2908
2909
2910 // Defines obj, preserves var_size_in_bytes
2911 void MacroAssembler::eden_allocate(Register obj,
2912 Register var_size_in_bytes,
2913 int con_size_in_bytes,
2914 Register t1,
2915 Label& slow_case) {
2916 assert(obj == rax, "obj must be in rax, for cmpxchg");
2917 assert_different_registers(obj, var_size_in_bytes, t1);
2918 if (!Universe::heap()->supports_inline_contig_alloc()) {
2919 jmp(slow_case);
2920 } else {
2921 Register end = t1;
2922 Label retry;
2923 bind(retry);
2924 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2925 movptr(obj, heap_top);
2926 if (var_size_in_bytes == noreg) {
2927 lea(end, Address(obj, con_size_in_bytes));
2928 } else {
2929 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2930 }
2931 // if end < obj then we wrapped around => object too long => slow case
2932 cmpptr(end, obj);
2933 jcc(Assembler::below, slow_case);
2934 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2935 jcc(Assembler::above, slow_case);
2936 // Compare obj with the top addr, and if still equal, store the new top addr in
2937 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2938 // it otherwise. Use lock prefix for atomicity on MPs.
2939 locked_cmpxchgptr(end, heap_top);
2940 jcc(Assembler::notEqual, retry);
2941 }
2942 }
2943
2944 void MacroAssembler::enter() {
2945 push(rbp);
2946 mov(rbp, rsp);
2947 }
2948
2949 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2950 void MacroAssembler::fat_nop() {
2951 if (UseAddressNop) {
2952 addr_nop_5();
2953 } else {
2954 emit_int8(0x26); // es:
2955 emit_int8(0x2e); // cs:
2956 emit_int8(0x64); // fs:
2957 emit_int8(0x65); // gs:
2958 emit_int8((unsigned char)0x90);
2959 }
2960 }
2961
2962 void MacroAssembler::fcmp(Register tmp) {
2963 fcmp(tmp, 1, true, true);
2964 }
2965
2966 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2967 assert(!pop_right || pop_left, "usage error");
2968 if (VM_Version::supports_cmov()) {
2969 assert(tmp == noreg, "unneeded temp");
2970 if (pop_left) {
2971 fucomip(index);
2972 } else {
2973 fucomi(index);
2974 }
2975 if (pop_right) {
2976 fpop();
2977 }
2978 } else {
2979 assert(tmp != noreg, "need temp");
2980 if (pop_left) {
2981 if (pop_right) {
2982 fcompp();
2983 } else {
2984 fcomp(index);
2985 }
2986 } else {
2987 fcom(index);
2988 }
2989 // convert FPU condition into eflags condition via rax,
2990 save_rax(tmp);
2991 fwait(); fnstsw_ax();
2992 sahf();
2993 restore_rax(tmp);
2994 }
2995 // condition codes set as follows:
2996 //
2997 // CF (corresponds to C0) if x < y
2998 // PF (corresponds to C2) if unordered
2999 // ZF (corresponds to C3) if x = y
3000 }
3001
3002 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3003 fcmp2int(dst, unordered_is_less, 1, true, true);
3004 }
3005
3006 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3007 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3008 Label L;
3009 if (unordered_is_less) {
3010 movl(dst, -1);
3011 jcc(Assembler::parity, L);
3012 jcc(Assembler::below , L);
3013 movl(dst, 0);
3014 jcc(Assembler::equal , L);
3015 increment(dst);
3016 } else { // unordered is greater
3017 movl(dst, 1);
3018 jcc(Assembler::parity, L);
3019 jcc(Assembler::above , L);
3020 movl(dst, 0);
3021 jcc(Assembler::equal , L);
3022 decrementl(dst);
3023 }
3024 bind(L);
3025 }
3026
3027 void MacroAssembler::fld_d(AddressLiteral src) {
3028 fld_d(as_Address(src));
3029 }
3030
3031 void MacroAssembler::fld_s(AddressLiteral src) {
3032 fld_s(as_Address(src));
3033 }
3034
3035 void MacroAssembler::fld_x(AddressLiteral src) {
3036 Assembler::fld_x(as_Address(src));
3037 }
3038
3039 void MacroAssembler::fldcw(AddressLiteral src) {
3040 Assembler::fldcw(as_Address(src));
3041 }
3042
3043 void MacroAssembler::pow_exp_core_encoding() {
3044 // kills rax, rcx, rdx
3045 subptr(rsp,sizeof(jdouble));
3046 // computes 2^X. Stack: X ...
3047 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and
3048 // keep it on the thread's stack to compute 2^int(X) later
3049 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1)
3050 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X))
3051 fld_s(0); // Stack: X X ...
3052 frndint(); // Stack: int(X) X ...
3053 fsuba(1); // Stack: int(X) X-int(X) ...
3054 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ...
3055 f2xm1(); // Stack: 2^(X-int(X))-1 ...
3056 fld1(); // Stack: 1 2^(X-int(X))-1 ...
3057 faddp(1); // Stack: 2^(X-int(X))
3058 // computes 2^(int(X)): add exponent bias (1023) to int(X), then
3059 // shift int(X)+1023 to exponent position.
3060 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11
3061 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent
3062 // values so detect them and set result to NaN.
3063 movl(rax,Address(rsp,0));
3064 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding
3065 addl(rax, 1023);
3066 movl(rdx,rax);
3067 shll(rax,20);
3068 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN.
3069 addl(rdx,1);
3070 // Check that 1 < int(X)+1023+1 < 2048
3071 // in 3 steps:
3072 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048
3073 // 2- (int(X)+1023+1)&-2048 != 0
3074 // 3- (int(X)+1023+1)&-2048 != 1
3075 // Do 2- first because addl just updated the flags.
3076 cmov32(Assembler::equal,rax,rcx);
3077 cmpl(rdx,1);
3078 cmov32(Assembler::equal,rax,rcx);
3079 testl(rdx,rcx);
3080 cmov32(Assembler::notEqual,rax,rcx);
3081 movl(Address(rsp,4),rax);
3082 movl(Address(rsp,0),0);
3083 fmul_d(Address(rsp,0)); // Stack: 2^X ...
3084 addptr(rsp,sizeof(jdouble));
3085 }
3086
3087 void MacroAssembler::increase_precision() {
3088 subptr(rsp, BytesPerWord);
3089 fnstcw(Address(rsp, 0));
3090 movl(rax, Address(rsp, 0));
3091 orl(rax, 0x300);
3092 push(rax);
3093 fldcw(Address(rsp, 0));
3094 pop(rax);
3095 }
3096
3097 void MacroAssembler::restore_precision() {
3098 fldcw(Address(rsp, 0));
3099 addptr(rsp, BytesPerWord);
3100 }
3101
3102 void MacroAssembler::fast_pow() {
3103 // computes X^Y = 2^(Y * log2(X))
3104 // if fast computation is not possible, result is NaN. Requires
3105 // fallback from user of this macro.
3106 // increase precision for intermediate steps of the computation
3107 BLOCK_COMMENT("fast_pow {");
3108 increase_precision();
3109 fyl2x(); // Stack: (Y*log2(X)) ...
3110 pow_exp_core_encoding(); // Stack: exp(X) ...
3111 restore_precision();
3112 BLOCK_COMMENT("} fast_pow");
3113 }
3114
3115 void MacroAssembler::fast_exp() {
3116 // computes exp(X) = 2^(X * log2(e))
3117 // if fast computation is not possible, result is NaN. Requires
3118 // fallback from user of this macro.
3119 // increase precision for intermediate steps of the computation
3120 increase_precision();
3121 fldl2e(); // Stack: log2(e) X ...
3122 fmulp(1); // Stack: (X*log2(e)) ...
3123 pow_exp_core_encoding(); // Stack: exp(X) ...
3124 restore_precision();
3125 }
3126
3127 void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) {
3128 // kills rax, rcx, rdx
3129 // pow and exp needs 2 extra registers on the fpu stack.
3130 Label slow_case, done;
3131 Register tmp = noreg;
3132 if (!VM_Version::supports_cmov()) {
3133 // fcmp needs a temporary so preserve rdx,
3134 tmp = rdx;
3135 }
3136 Register tmp2 = rax;
3137 Register tmp3 = rcx;
3138
3139 if (is_exp) {
3140 // Stack: X
3141 fld_s(0); // duplicate argument for runtime call. Stack: X X
3142 fast_exp(); // Stack: exp(X) X
3143 fcmp(tmp, 0, false, false); // Stack: exp(X) X
3144 // exp(X) not equal to itself: exp(X) is NaN go to slow case.
3145 jcc(Assembler::parity, slow_case);
3146 // get rid of duplicate argument. Stack: exp(X)
3147 if (num_fpu_regs_in_use > 0) {
3148 fxch();
3149 fpop();
3150 } else {
3151 ffree(1);
3152 }
3153 jmp(done);
3154 } else {
3155 // Stack: X Y
3156 Label x_negative, y_not_2;
3157
3158 static double two = 2.0;
3159 ExternalAddress two_addr((address)&two);
3160
3161 // constant maybe too far on 64 bit
3162 lea(tmp2, two_addr);
3163 fld_d(Address(tmp2, 0)); // Stack: 2 X Y
3164 fcmp(tmp, 2, true, false); // Stack: X Y
3165 jcc(Assembler::parity, y_not_2);
3166 jcc(Assembler::notEqual, y_not_2);
3167
3168 fxch(); fpop(); // Stack: X
3169 fmul(0); // Stack: X*X
3170
3171 jmp(done);
3172
3173 bind(y_not_2);
3174
3175 fldz(); // Stack: 0 X Y
3176 fcmp(tmp, 1, true, false); // Stack: X Y
3177 jcc(Assembler::above, x_negative);
3178
3179 // X >= 0
3180
3181 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3182 fld_s(1); // Stack: X Y X Y
3183 fast_pow(); // Stack: X^Y X Y
3184 fcmp(tmp, 0, false, false); // Stack: X^Y X Y
3185 // X^Y not equal to itself: X^Y is NaN go to slow case.
3186 jcc(Assembler::parity, slow_case);
3187 // get rid of duplicate arguments. Stack: X^Y
3188 if (num_fpu_regs_in_use > 0) {
3189 fxch(); fpop();
3190 fxch(); fpop();
3191 } else {
3192 ffree(2);
3193 ffree(1);
3194 }
3195 jmp(done);
3196
3197 // X <= 0
3198 bind(x_negative);
3199
3200 fld_s(1); // Stack: Y X Y
3201 frndint(); // Stack: int(Y) X Y
3202 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y
3203 jcc(Assembler::notEqual, slow_case);
3204
3205 subptr(rsp, 8);
3206
3207 // For X^Y, when X < 0, Y has to be an integer and the final
3208 // result depends on whether it's odd or even. We just checked
3209 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit
3210 // integer to test its parity. If int(Y) is huge and doesn't fit
3211 // in the 64 bit integer range, the integer indefinite value will
3212 // end up in the gp registers. Huge numbers are all even, the
3213 // integer indefinite number is even so it's fine.
3214
3215 #ifdef ASSERT
3216 // Let's check we don't end up with an integer indefinite number
3217 // when not expected. First test for huge numbers: check whether
3218 // int(Y)+1 == int(Y) which is true for very large numbers and
3219 // those are all even. A 64 bit integer is guaranteed to not
3220 // overflow for numbers where y+1 != y (when precision is set to
3221 // double precision).
3222 Label y_not_huge;
3223
3224 fld1(); // Stack: 1 int(Y) X Y
3225 fadd(1); // Stack: 1+int(Y) int(Y) X Y
3226
3227 #ifdef _LP64
3228 // trip to memory to force the precision down from double extended
3229 // precision
3230 fstp_d(Address(rsp, 0));
3231 fld_d(Address(rsp, 0));
3232 #endif
3233
3234 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y
3235 #endif
3236
3237 // move int(Y) as 64 bit integer to thread's stack
3238 fistp_d(Address(rsp,0)); // Stack: X Y
3239
3240 #ifdef ASSERT
3241 jcc(Assembler::notEqual, y_not_huge);
3242
3243 // Y is huge so we know it's even. It may not fit in a 64 bit
3244 // integer and we don't want the debug code below to see the
3245 // integer indefinite value so overwrite int(Y) on the thread's
3246 // stack with 0.
3247 movl(Address(rsp, 0), 0);
3248 movl(Address(rsp, 4), 0);
3249
3250 bind(y_not_huge);
3251 #endif
3252
3253 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3254 fld_s(1); // Stack: X Y X Y
3255 fabs(); // Stack: abs(X) Y X Y
3256 fast_pow(); // Stack: abs(X)^Y X Y
3257 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y
3258 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case.
3259
3260 pop(tmp2);
3261 NOT_LP64(pop(tmp3));
3262 jcc(Assembler::parity, slow_case);
3263
3264 #ifdef ASSERT
3265 // Check that int(Y) is not integer indefinite value (int
3266 // overflow). Shouldn't happen because for values that would
3267 // overflow, 1+int(Y)==Y which was tested earlier.
3268 #ifndef _LP64
3269 {
3270 Label integer;
3271 testl(tmp2, tmp2);
3272 jcc(Assembler::notZero, integer);
3273 cmpl(tmp3, 0x80000000);
3274 jcc(Assembler::notZero, integer);
3275 STOP("integer indefinite value shouldn't be seen here");
3276 bind(integer);
3277 }
3278 #else
3279 {
3280 Label integer;
3281 mov(tmp3, tmp2); // preserve tmp2 for parity check below
3282 shlq(tmp3, 1);
3283 jcc(Assembler::carryClear, integer);
3284 jcc(Assembler::notZero, integer);
3285 STOP("integer indefinite value shouldn't be seen here");
3286 bind(integer);
3287 }
3288 #endif
3289 #endif
3290
3291 // get rid of duplicate arguments. Stack: X^Y
3292 if (num_fpu_regs_in_use > 0) {
3293 fxch(); fpop();
3294 fxch(); fpop();
3295 } else {
3296 ffree(2);
3297 ffree(1);
3298 }
3299
3300 testl(tmp2, 1);
3301 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y
3302 // X <= 0, Y even: X^Y = -abs(X)^Y
3303
3304 fchs(); // Stack: -abs(X)^Y Y
3305 jmp(done);
3306 }
3307
3308 // slow case: runtime call
3309 bind(slow_case);
3310
3311 fpop(); // pop incorrect result or int(Y)
3312
3313 fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow),
3314 is_exp ? 1 : 2, num_fpu_regs_in_use);
3315
3316 // Come here with result in F-TOS
3317 bind(done);
3318 }
3319
3320 void MacroAssembler::fpop() {
3321 ffree();
3322 fincstp();
3323 }
3324
3325 void MacroAssembler::fremr(Register tmp) {
3326 save_rax(tmp);
3327 { Label L;
3328 bind(L);
3329 fprem();
3330 fwait(); fnstsw_ax();
3331 #ifdef _LP64
3332 testl(rax, 0x400);
3333 jcc(Assembler::notEqual, L);
3334 #else
3335 sahf();
3336 jcc(Assembler::parity, L);
3337 #endif // _LP64
3338 }
3339 restore_rax(tmp);
3340 // Result is in ST0.
3341 // Note: fxch & fpop to get rid of ST1
3342 // (otherwise FPU stack could overflow eventually)
3343 fxch(1);
3344 fpop();
3345 }
3346
3347
3348 void MacroAssembler::incrementl(AddressLiteral dst) {
3349 if (reachable(dst)) {
3350 incrementl(as_Address(dst));
3351 } else {
3352 lea(rscratch1, dst);
3353 incrementl(Address(rscratch1, 0));
3354 }
3355 }
3356
3357 void MacroAssembler::incrementl(ArrayAddress dst) {
3358 incrementl(as_Address(dst));
3359 }
3360
3361 void MacroAssembler::incrementl(Register reg, int value) {
3362 if (value == min_jint) {addl(reg, value) ; return; }
3363 if (value < 0) { decrementl(reg, -value); return; }
3364 if (value == 0) { ; return; }
3365 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3366 /* else */ { addl(reg, value) ; return; }
3367 }
3368
3369 void MacroAssembler::incrementl(Address dst, int value) {
3370 if (value == min_jint) {addl(dst, value) ; return; }
3371 if (value < 0) { decrementl(dst, -value); return; }
3372 if (value == 0) { ; return; }
3373 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3374 /* else */ { addl(dst, value) ; return; }
3375 }
3376
3377 void MacroAssembler::jump(AddressLiteral dst) {
3378 if (reachable(dst)) {
3379 jmp_literal(dst.target(), dst.rspec());
3380 } else {
3381 lea(rscratch1, dst);
3382 jmp(rscratch1);
3383 }
3384 }
3385
3386 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3387 if (reachable(dst)) {
3388 InstructionMark im(this);
3389 relocate(dst.reloc());
3390 const int short_size = 2;
3391 const int long_size = 6;
3392 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3393 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3394 // 0111 tttn #8-bit disp
3395 emit_int8(0x70 | cc);
3396 emit_int8((offs - short_size) & 0xFF);
3397 } else {
3398 // 0000 1111 1000 tttn #32-bit disp
3399 emit_int8(0x0F);
3400 emit_int8((unsigned char)(0x80 | cc));
3401 emit_int32(offs - long_size);
3402 }
3403 } else {
3404 #ifdef ASSERT
3405 warning("reversing conditional branch");
3406 #endif /* ASSERT */
3407 Label skip;
3408 jccb(reverse[cc], skip);
3409 lea(rscratch1, dst);
3410 Assembler::jmp(rscratch1);
3411 bind(skip);
3412 }
3413 }
3414
3415 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3416 if (reachable(src)) {
3417 Assembler::ldmxcsr(as_Address(src));
3418 } else {
3419 lea(rscratch1, src);
3420 Assembler::ldmxcsr(Address(rscratch1, 0));
3421 }
3422 }
3423
3424 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3425 int off;
3426 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3427 off = offset();
3428 movsbl(dst, src); // movsxb
3429 } else {
3430 off = load_unsigned_byte(dst, src);
3431 shll(dst, 24);
3432 sarl(dst, 24);
3433 }
3434 return off;
3435 }
3436
3437 // Note: load_signed_short used to be called load_signed_word.
3438 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3439 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3440 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3441 int MacroAssembler::load_signed_short(Register dst, Address src) {
3442 int off;
3443 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3444 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3445 // version but this is what 64bit has always done. This seems to imply
3446 // that users are only using 32bits worth.
3447 off = offset();
3448 movswl(dst, src); // movsxw
3449 } else {
3450 off = load_unsigned_short(dst, src);
3451 shll(dst, 16);
3452 sarl(dst, 16);
3453 }
3454 return off;
3455 }
3456
3457 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3458 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3459 // and "3.9 Partial Register Penalties", p. 22).
3460 int off;
3461 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3462 off = offset();
3463 movzbl(dst, src); // movzxb
3464 } else {
3465 xorl(dst, dst);
3466 off = offset();
3467 movb(dst, src);
3468 }
3469 return off;
3470 }
3471
3472 // Note: load_unsigned_short used to be called load_unsigned_word.
3473 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3474 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3475 // and "3.9 Partial Register Penalties", p. 22).
3476 int off;
3477 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3478 off = offset();
3479 movzwl(dst, src); // movzxw
3480 } else {
3481 xorl(dst, dst);
3482 off = offset();
3483 movw(dst, src);
3484 }
3485 return off;
3486 }
3487
3488 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3489 switch (size_in_bytes) {
3490 #ifndef _LP64
3491 case 8:
3492 assert(dst2 != noreg, "second dest register required");
3493 movl(dst, src);
3494 movl(dst2, src.plus_disp(BytesPerInt));
3495 break;
3496 #else
3497 case 8: movq(dst, src); break;
3498 #endif
3499 case 4: movl(dst, src); break;
3500 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3501 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3502 default: ShouldNotReachHere();
3503 }
3504 }
3505
3506 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3507 switch (size_in_bytes) {
3508 #ifndef _LP64
3509 case 8:
3510 assert(src2 != noreg, "second source register required");
3511 movl(dst, src);
3512 movl(dst.plus_disp(BytesPerInt), src2);
3513 break;
3514 #else
3515 case 8: movq(dst, src); break;
3516 #endif
3517 case 4: movl(dst, src); break;
3518 case 2: movw(dst, src); break;
3519 case 1: movb(dst, src); break;
3520 default: ShouldNotReachHere();
3521 }
3522 }
3523
3524 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3525 if (reachable(dst)) {
3526 movl(as_Address(dst), src);
3527 } else {
3528 lea(rscratch1, dst);
3529 movl(Address(rscratch1, 0), src);
3530 }
3531 }
3532
3533 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3534 if (reachable(src)) {
3535 movl(dst, as_Address(src));
3536 } else {
3537 lea(rscratch1, src);
3538 movl(dst, Address(rscratch1, 0));
3539 }
3540 }
3541
3542 // C++ bool manipulation
3543
3544 void MacroAssembler::movbool(Register dst, Address src) {
3545 if(sizeof(bool) == 1)
3546 movb(dst, src);
3547 else if(sizeof(bool) == 2)
3548 movw(dst, src);
3549 else if(sizeof(bool) == 4)
3550 movl(dst, src);
3551 else
3552 // unsupported
3553 ShouldNotReachHere();
3554 }
3555
3556 void MacroAssembler::movbool(Address dst, bool boolconst) {
3557 if(sizeof(bool) == 1)
3558 movb(dst, (int) boolconst);
3559 else if(sizeof(bool) == 2)
3560 movw(dst, (int) boolconst);
3561 else if(sizeof(bool) == 4)
3562 movl(dst, (int) boolconst);
3563 else
3564 // unsupported
3565 ShouldNotReachHere();
3566 }
3567
3568 void MacroAssembler::movbool(Address dst, Register src) {
3569 if(sizeof(bool) == 1)
3570 movb(dst, src);
3571 else if(sizeof(bool) == 2)
3572 movw(dst, src);
3573 else if(sizeof(bool) == 4)
3574 movl(dst, src);
3575 else
3576 // unsupported
3577 ShouldNotReachHere();
3578 }
3579
3580 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3581 movb(as_Address(dst), src);
3582 }
3583
3584 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3585 if (reachable(src)) {
3586 movdl(dst, as_Address(src));
3587 } else {
3588 lea(rscratch1, src);
3589 movdl(dst, Address(rscratch1, 0));
3590 }
3591 }
3592
3593 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3594 if (reachable(src)) {
3595 movq(dst, as_Address(src));
3596 } else {
3597 lea(rscratch1, src);
3598 movq(dst, Address(rscratch1, 0));
3599 }
3600 }
3601
3602 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3603 if (reachable(src)) {
3604 if (UseXmmLoadAndClearUpper) {
3605 movsd (dst, as_Address(src));
3606 } else {
3607 movlpd(dst, as_Address(src));
3608 }
3609 } else {
3610 lea(rscratch1, src);
3611 if (UseXmmLoadAndClearUpper) {
3612 movsd (dst, Address(rscratch1, 0));
3613 } else {
3614 movlpd(dst, Address(rscratch1, 0));
3615 }
3616 }
3617 }
3618
3619 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3620 if (reachable(src)) {
3621 movss(dst, as_Address(src));
3622 } else {
3623 lea(rscratch1, src);
3624 movss(dst, Address(rscratch1, 0));
3625 }
3626 }
3627
3628 void MacroAssembler::movptr(Register dst, Register src) {
3629 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3630 }
3631
3632 void MacroAssembler::movptr(Register dst, Address src) {
3633 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3634 }
3635
3636 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3637 void MacroAssembler::movptr(Register dst, intptr_t src) {
3638 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3639 }
3640
3641 void MacroAssembler::movptr(Address dst, Register src) {
3642 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3643 }
3644
3645 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
3646 if (reachable(src)) {
3647 Assembler::movdqu(dst, as_Address(src));
3648 } else {
3649 lea(rscratch1, src);
3650 Assembler::movdqu(dst, Address(rscratch1, 0));
3651 }
3652 }
3653
3654 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3655 if (reachable(src)) {
3656 Assembler::movdqa(dst, as_Address(src));
3657 } else {
3658 lea(rscratch1, src);
3659 Assembler::movdqa(dst, Address(rscratch1, 0));
3660 }
3661 }
3662
3663 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3664 if (reachable(src)) {
3665 Assembler::movsd(dst, as_Address(src));
3666 } else {
3667 lea(rscratch1, src);
3668 Assembler::movsd(dst, Address(rscratch1, 0));
3669 }
3670 }
3671
3672 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3673 if (reachable(src)) {
3674 Assembler::movss(dst, as_Address(src));
3675 } else {
3676 lea(rscratch1, src);
3677 Assembler::movss(dst, Address(rscratch1, 0));
3678 }
3679 }
3680
3681 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3682 if (reachable(src)) {
3683 Assembler::mulsd(dst, as_Address(src));
3684 } else {
3685 lea(rscratch1, src);
3686 Assembler::mulsd(dst, Address(rscratch1, 0));
3687 }
3688 }
3689
3690 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3691 if (reachable(src)) {
3692 Assembler::mulss(dst, as_Address(src));
3693 } else {
3694 lea(rscratch1, src);
3695 Assembler::mulss(dst, Address(rscratch1, 0));
3696 }
3697 }
3698
3699 void MacroAssembler::null_check(Register reg, int offset) {
3700 if (needs_explicit_null_check(offset)) {
3701 // provoke OS NULL exception if reg = NULL by
3702 // accessing M[reg] w/o changing any (non-CC) registers
3703 // NOTE: cmpl is plenty here to provoke a segv
3704 cmpptr(rax, Address(reg, 0));
3705 // Note: should probably use testl(rax, Address(reg, 0));
3706 // may be shorter code (however, this version of
3707 // testl needs to be implemented first)
3708 } else {
3709 // nothing to do, (later) access of M[reg + offset]
3710 // will provoke OS NULL exception if reg = NULL
3711 }
3712 }
3713
3714 void MacroAssembler::os_breakpoint() {
3715 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3716 // (e.g., MSVC can't call ps() otherwise)
3717 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3718 }
3719
3720 void MacroAssembler::pop_CPU_state() {
3721 pop_FPU_state();
3722 pop_IU_state();
3723 }
3724
3725 void MacroAssembler::pop_FPU_state() {
3726 NOT_LP64(frstor(Address(rsp, 0));)
3727 LP64_ONLY(fxrstor(Address(rsp, 0));)
3728 addptr(rsp, FPUStateSizeInWords * wordSize);
3729 }
3730
3731 void MacroAssembler::pop_IU_state() {
3732 popa();
3733 LP64_ONLY(addq(rsp, 8));
3734 popf();
3735 }
3736
3737 // Save Integer and Float state
3738 // Warning: Stack must be 16 byte aligned (64bit)
3739 void MacroAssembler::push_CPU_state() {
3740 push_IU_state();
3741 push_FPU_state();
3742 }
3743
3744 void MacroAssembler::push_FPU_state() {
3745 subptr(rsp, FPUStateSizeInWords * wordSize);
3746 #ifndef _LP64
3747 fnsave(Address(rsp, 0));
3748 fwait();
3749 #else
3750 fxsave(Address(rsp, 0));
3751 #endif // LP64
3752 }
3753
3754 void MacroAssembler::push_IU_state() {
3755 // Push flags first because pusha kills them
3756 pushf();
3757 // Make sure rsp stays 16-byte aligned
3758 LP64_ONLY(subq(rsp, 8));
3759 pusha();
3760 }
3761
3762 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
3763 // determine java_thread register
3764 if (!java_thread->is_valid()) {
3765 java_thread = rdi;
3766 get_thread(java_thread);
3767 }
3768 // we must set sp to zero to clear frame
3769 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3770 if (clear_fp) {
3771 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3772 }
3773
3774 if (clear_pc)
3775 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3776
3777 }
3778
3779 void MacroAssembler::restore_rax(Register tmp) {
3780 if (tmp == noreg) pop(rax);
3781 else if (tmp != rax) mov(rax, tmp);
3782 }
3783
3784 void MacroAssembler::round_to(Register reg, int modulus) {
3785 addptr(reg, modulus - 1);
3786 andptr(reg, -modulus);
3787 }
3788
3789 void MacroAssembler::save_rax(Register tmp) {
3790 if (tmp == noreg) push(rax);
3791 else if (tmp != rax) mov(tmp, rax);
3792 }
3793
3794 // Write serialization page so VM thread can do a pseudo remote membar.
3795 // We use the current thread pointer to calculate a thread specific
3796 // offset to write to within the page. This minimizes bus traffic
3797 // due to cache line collision.
3798 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3799 movl(tmp, thread);
3800 shrl(tmp, os::get_serialize_page_shift_count());
3801 andl(tmp, (os::vm_page_size() - sizeof(int)));
3802
3803 Address index(noreg, tmp, Address::times_1);
3804 ExternalAddress page(os::get_memory_serialize_page());
3805
3806 // Size of store must match masking code above
3807 movl(as_Address(ArrayAddress(page, index)), tmp);
3808 }
3809
3810 // Calls to C land
3811 //
3812 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3813 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3814 // has to be reset to 0. This is required to allow proper stack traversal.
3815 void MacroAssembler::set_last_Java_frame(Register java_thread,
3816 Register last_java_sp,
3817 Register last_java_fp,
3818 address last_java_pc) {
3819 // determine java_thread register
3820 if (!java_thread->is_valid()) {
3821 java_thread = rdi;
3822 get_thread(java_thread);
3823 }
3824 // determine last_java_sp register
3825 if (!last_java_sp->is_valid()) {
3826 last_java_sp = rsp;
3827 }
3828
3829 // last_java_fp is optional
3830
3831 if (last_java_fp->is_valid()) {
3832 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3833 }
3834
3835 // last_java_pc is optional
3836
3837 if (last_java_pc != NULL) {
3838 lea(Address(java_thread,
3839 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3840 InternalAddress(last_java_pc));
3841
3842 }
3843 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3844 }
3845
3846 void MacroAssembler::shlptr(Register dst, int imm8) {
3847 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3848 }
3849
3850 void MacroAssembler::shrptr(Register dst, int imm8) {
3851 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3852 }
3853
3854 void MacroAssembler::sign_extend_byte(Register reg) {
3855 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3856 movsbl(reg, reg); // movsxb
3857 } else {
3858 shll(reg, 24);
3859 sarl(reg, 24);
3860 }
3861 }
3862
3863 void MacroAssembler::sign_extend_short(Register reg) {
3864 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3865 movswl(reg, reg); // movsxw
3866 } else {
3867 shll(reg, 16);
3868 sarl(reg, 16);
3869 }
3870 }
3871
3872 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3873 assert(reachable(src), "Address should be reachable");
3874 testl(dst, as_Address(src));
3875 }
3876
3877 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3878 if (reachable(src)) {
3879 Assembler::sqrtsd(dst, as_Address(src));
3880 } else {
3881 lea(rscratch1, src);
3882 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3883 }
3884 }
3885
3886 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3887 if (reachable(src)) {
3888 Assembler::sqrtss(dst, as_Address(src));
3889 } else {
3890 lea(rscratch1, src);
3891 Assembler::sqrtss(dst, Address(rscratch1, 0));
3892 }
3893 }
3894
3895 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3896 if (reachable(src)) {
3897 Assembler::subsd(dst, as_Address(src));
3898 } else {
3899 lea(rscratch1, src);
3900 Assembler::subsd(dst, Address(rscratch1, 0));
3901 }
3902 }
3903
3904 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3905 if (reachable(src)) {
3906 Assembler::subss(dst, as_Address(src));
3907 } else {
3908 lea(rscratch1, src);
3909 Assembler::subss(dst, Address(rscratch1, 0));
3910 }
3911 }
3912
3913 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3914 if (reachable(src)) {
3915 Assembler::ucomisd(dst, as_Address(src));
3916 } else {
3917 lea(rscratch1, src);
3918 Assembler::ucomisd(dst, Address(rscratch1, 0));
3919 }
3920 }
3921
3922 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3923 if (reachable(src)) {
3924 Assembler::ucomiss(dst, as_Address(src));
3925 } else {
3926 lea(rscratch1, src);
3927 Assembler::ucomiss(dst, Address(rscratch1, 0));
3928 }
3929 }
3930
3931 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
3932 // Used in sign-bit flipping with aligned address.
3933 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3934 if (reachable(src)) {
3935 Assembler::xorpd(dst, as_Address(src));
3936 } else {
3937 lea(rscratch1, src);
3938 Assembler::xorpd(dst, Address(rscratch1, 0));
3939 }
3940 }
3941
3942 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
3943 // Used in sign-bit flipping with aligned address.
3944 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3945 if (reachable(src)) {
3946 Assembler::xorps(dst, as_Address(src));
3947 } else {
3948 lea(rscratch1, src);
3949 Assembler::xorps(dst, Address(rscratch1, 0));
3950 }
3951 }
3952
3953 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3954 // Used in sign-bit flipping with aligned address.
3955 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3956 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3957 if (reachable(src)) {
3958 Assembler::pshufb(dst, as_Address(src));
3959 } else {
3960 lea(rscratch1, src);
3961 Assembler::pshufb(dst, Address(rscratch1, 0));
3962 }
3963 }
3964
3965 // AVX 3-operands instructions
3966
3967 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3968 if (reachable(src)) {
3969 vaddsd(dst, nds, as_Address(src));
3970 } else {
3971 lea(rscratch1, src);
3972 vaddsd(dst, nds, Address(rscratch1, 0));
3973 }
3974 }
3975
3976 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3977 if (reachable(src)) {
3978 vaddss(dst, nds, as_Address(src));
3979 } else {
3980 lea(rscratch1, src);
3981 vaddss(dst, nds, Address(rscratch1, 0));
3982 }
3983 }
3984
3985 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
3986 if (reachable(src)) {
3987 vandpd(dst, nds, as_Address(src), vector_len);
3988 } else {
3989 lea(rscratch1, src);
3990 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
3991 }
3992 }
3993
3994 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
3995 if (reachable(src)) {
3996 vandps(dst, nds, as_Address(src), vector_len);
3997 } else {
3998 lea(rscratch1, src);
3999 vandps(dst, nds, Address(rscratch1, 0), vector_len);
4000 }
4001 }
4002
4003 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4004 if (reachable(src)) {
4005 vdivsd(dst, nds, as_Address(src));
4006 } else {
4007 lea(rscratch1, src);
4008 vdivsd(dst, nds, Address(rscratch1, 0));
4009 }
4010 }
4011
4012 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4013 if (reachable(src)) {
4014 vdivss(dst, nds, as_Address(src));
4015 } else {
4016 lea(rscratch1, src);
4017 vdivss(dst, nds, Address(rscratch1, 0));
4018 }
4019 }
4020
4021 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4022 if (reachable(src)) {
4023 vmulsd(dst, nds, as_Address(src));
4024 } else {
4025 lea(rscratch1, src);
4026 vmulsd(dst, nds, Address(rscratch1, 0));
4027 }
4028 }
4029
4030 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4031 if (reachable(src)) {
4032 vmulss(dst, nds, as_Address(src));
4033 } else {
4034 lea(rscratch1, src);
4035 vmulss(dst, nds, Address(rscratch1, 0));
4036 }
4037 }
4038
4039 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4040 if (reachable(src)) {
4041 vsubsd(dst, nds, as_Address(src));
4042 } else {
4043 lea(rscratch1, src);
4044 vsubsd(dst, nds, Address(rscratch1, 0));
4045 }
4046 }
4047
4048 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4049 if (reachable(src)) {
4050 vsubss(dst, nds, as_Address(src));
4051 } else {
4052 lea(rscratch1, src);
4053 vsubss(dst, nds, Address(rscratch1, 0));
4054 }
4055 }
4056
4057 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4058 if (reachable(src)) {
4059 vxorpd(dst, nds, as_Address(src), vector_len);
4060 } else {
4061 lea(rscratch1, src);
4062 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
4063 }
4064 }
4065
4066 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4067 if (reachable(src)) {
4068 vxorps(dst, nds, as_Address(src), vector_len);
4069 } else {
4070 lea(rscratch1, src);
4071 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
4072 }
4073 }
4074
4075
4076 //////////////////////////////////////////////////////////////////////////////////
4077 #if INCLUDE_ALL_GCS
4078
4079 void MacroAssembler::g1_write_barrier_pre(Register obj,
4080 Register pre_val,
4081 Register thread,
4082 Register tmp,
4083 bool tosca_live,
4084 bool expand_call) {
4085
4086 // If expand_call is true then we expand the call_VM_leaf macro
4087 // directly to skip generating the check by
4088 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
4089
4090 #ifdef _LP64
4091 assert(thread == r15_thread, "must be");
4092 #endif // _LP64
4093
4094 Label done;
4095 Label runtime;
4096
4097 assert(pre_val != noreg, "check this code");
4098
4099 if (obj != noreg) {
4100 assert_different_registers(obj, pre_val, tmp);
4101 assert(pre_val != rax, "check this code");
4102 }
4103
4104 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4105 PtrQueue::byte_offset_of_active()));
4106 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4107 PtrQueue::byte_offset_of_index()));
4108 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4109 PtrQueue::byte_offset_of_buf()));
4110
4111
4112 // Is marking active?
4113 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4114 cmpl(in_progress, 0);
4115 } else {
4116 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
4117 cmpb(in_progress, 0);
4118 }
4119 jcc(Assembler::equal, done);
4120
4121 // Do we need to load the previous value?
4122 if (obj != noreg) {
4123 load_heap_oop(pre_val, Address(obj, 0));
4124 }
4125
4126 // Is the previous value null?
4127 cmpptr(pre_val, (int32_t) NULL_WORD);
4128 jcc(Assembler::equal, done);
4129
4130 // Can we store original value in the thread's buffer?
4131 // Is index == 0?
4132 // (The index field is typed as size_t.)
4133
4134 movptr(tmp, index); // tmp := *index_adr
4135 cmpptr(tmp, 0); // tmp == 0?
4136 jcc(Assembler::equal, runtime); // If yes, goto runtime
4137
4138 subptr(tmp, wordSize); // tmp := tmp - wordSize
4139 movptr(index, tmp); // *index_adr := tmp
4140 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
4141
4142 // Record the previous value
4143 movptr(Address(tmp, 0), pre_val);
4144 jmp(done);
4145
4146 bind(runtime);
4147 // save the live input values
4148 if(tosca_live) push(rax);
4149
4150 if (obj != noreg && obj != rax)
4151 push(obj);
4152
4153 if (pre_val != rax)
4154 push(pre_val);
4155
4156 // Calling the runtime using the regular call_VM_leaf mechanism generates
4157 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
4158 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
4159 //
4160 // If we care generating the pre-barrier without a frame (e.g. in the
4161 // intrinsified Reference.get() routine) then ebp might be pointing to
4162 // the caller frame and so this check will most likely fail at runtime.
4163 //
4164 // Expanding the call directly bypasses the generation of the check.
4165 // So when we do not have have a full interpreter frame on the stack
4166 // expand_call should be passed true.
4167
4168 NOT_LP64( push(thread); )
4169
4170 if (expand_call) {
4171 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
4172 pass_arg1(this, thread);
4173 pass_arg0(this, pre_val);
4174 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
4175 } else {
4176 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
4177 }
4178
4179 NOT_LP64( pop(thread); )
4180
4181 // save the live input values
4182 if (pre_val != rax)
4183 pop(pre_val);
4184
4185 if (obj != noreg && obj != rax)
4186 pop(obj);
4187
4188 if(tosca_live) pop(rax);
4189
4190 bind(done);
4191 }
4192
4193 void MacroAssembler::g1_write_barrier_post(Register store_addr,
4194 Register new_val,
4195 Register thread,
4196 Register tmp,
4197 Register tmp2) {
4198 #ifdef _LP64
4199 assert(thread == r15_thread, "must be");
4200 #endif // _LP64
4201
4202 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4203 PtrQueue::byte_offset_of_index()));
4204 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4205 PtrQueue::byte_offset_of_buf()));
4206
4207 CardTableModRefBS* ct =
4208 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set());
4209 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4210
4211 Label done;
4212 Label runtime;
4213
4214 // Does store cross heap regions?
4215
4216 movptr(tmp, store_addr);
4217 xorptr(tmp, new_val);
4218 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
4219 jcc(Assembler::equal, done);
4220
4221 // crosses regions, storing NULL?
4222
4223 cmpptr(new_val, (int32_t) NULL_WORD);
4224 jcc(Assembler::equal, done);
4225
4226 // storing region crossing non-NULL, is card already dirty?
4227
4228 const Register card_addr = tmp;
4229 const Register cardtable = tmp2;
4230
4231 movptr(card_addr, store_addr);
4232 shrptr(card_addr, CardTableModRefBS::card_shift);
4233 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
4234 // a valid address and therefore is not properly handled by the relocation code.
4235 movptr(cardtable, (intptr_t)ct->byte_map_base);
4236 addptr(card_addr, cardtable);
4237
4238 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
4239 jcc(Assembler::equal, done);
4240
4241 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4242 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4243 jcc(Assembler::equal, done);
4244
4245
4246 // storing a region crossing, non-NULL oop, card is clean.
4247 // dirty card and log.
4248
4249 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4250
4251 cmpl(queue_index, 0);
4252 jcc(Assembler::equal, runtime);
4253 subl(queue_index, wordSize);
4254 movptr(tmp2, buffer);
4255 #ifdef _LP64
4256 movslq(rscratch1, queue_index);
4257 addq(tmp2, rscratch1);
4258 movq(Address(tmp2, 0), card_addr);
4259 #else
4260 addl(tmp2, queue_index);
4261 movl(Address(tmp2, 0), card_addr);
4262 #endif
4263 jmp(done);
4264
4265 bind(runtime);
4266 // save the live input values
4267 push(store_addr);
4268 push(new_val);
4269 #ifdef _LP64
4270 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
4271 #else
4272 push(thread);
4273 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
4274 pop(thread);
4275 #endif
4276 pop(new_val);
4277 pop(store_addr);
4278
4279 bind(done);
4280 }
4281
4282 #endif // INCLUDE_ALL_GCS
4283 //////////////////////////////////////////////////////////////////////////////////
4284
4285
4286 void MacroAssembler::store_check(Register obj) {
4287 // Does a store check for the oop in register obj. The content of
4288 // register obj is destroyed afterwards.
4289 store_check_part_1(obj);
4290 store_check_part_2(obj);
4291 }
4292
4293 void MacroAssembler::store_check(Register obj, Address dst) {
4294 store_check(obj);
4295 }
4296
4297
4298 // split the store check operation so that other instructions can be scheduled inbetween
4299 void MacroAssembler::store_check_part_1(Register obj) {
4300 BarrierSet* bs = Universe::heap()->barrier_set();
4301 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4302 shrptr(obj, CardTableModRefBS::card_shift);
4303 }
4304
4305 void MacroAssembler::store_check_part_2(Register obj) {
4306 BarrierSet* bs = Universe::heap()->barrier_set();
4307 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4308 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
4309 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4310
4311 // The calculation for byte_map_base is as follows:
4312 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
4313 // So this essentially converts an address to a displacement and it will
4314 // never need to be relocated. On 64bit however the value may be too
4315 // large for a 32bit displacement.
4316 intptr_t disp = (intptr_t) ct->byte_map_base;
4317 if (is_simm32(disp)) {
4318 Address cardtable(noreg, obj, Address::times_1, disp);
4319 movb(cardtable, 0);
4320 } else {
4321 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
4322 // displacement and done in a single instruction given favorable mapping and a
4323 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
4324 // entry and that entry is not properly handled by the relocation code.
4325 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
4326 Address index(noreg, obj, Address::times_1);
4327 movb(as_Address(ArrayAddress(cardtable, index)), 0);
4328 }
4329 }
4330
4331 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4332 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4333 }
4334
4335 // Force generation of a 4 byte immediate value even if it fits into 8bit
4336 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4337 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4338 }
4339
4340 void MacroAssembler::subptr(Register dst, Register src) {
4341 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4342 }
4343
4344 // C++ bool manipulation
4345 void MacroAssembler::testbool(Register dst) {
4346 if(sizeof(bool) == 1)
4347 testb(dst, 0xff);
4348 else if(sizeof(bool) == 2) {
4349 // testw implementation needed for two byte bools
4350 ShouldNotReachHere();
4351 } else if(sizeof(bool) == 4)
4352 testl(dst, dst);
4353 else
4354 // unsupported
4355 ShouldNotReachHere();
4356 }
4357
4358 void MacroAssembler::testptr(Register dst, Register src) {
4359 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4360 }
4361
4362 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4363 void MacroAssembler::tlab_allocate(Register obj,
4364 Register var_size_in_bytes,
4365 int con_size_in_bytes,
4366 Register t1,
4367 Register t2,
4368 Label& slow_case) {
4369 assert_different_registers(obj, t1, t2);
4370 assert_different_registers(obj, var_size_in_bytes, t1);
4371 Register end = t2;
4372 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
4373
4374 verify_tlab();
4375
4376 NOT_LP64(get_thread(thread));
4377
4378 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
4379 if (var_size_in_bytes == noreg) {
4380 lea(end, Address(obj, con_size_in_bytes));
4381 } else {
4382 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
4383 }
4384 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
4385 jcc(Assembler::above, slow_case);
4386
4387 // update the tlab top pointer
4388 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
4389
4390 // recover var_size_in_bytes if necessary
4391 if (var_size_in_bytes == end) {
4392 subptr(var_size_in_bytes, obj);
4393 }
4394 verify_tlab();
4395 }
4396
4397 // Preserves rbx, and rdx.
4398 Register MacroAssembler::tlab_refill(Label& retry,
4399 Label& try_eden,
4400 Label& slow_case) {
4401 Register top = rax;
4402 Register t1 = rcx;
4403 Register t2 = rsi;
4404 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
4405 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
4406 Label do_refill, discard_tlab;
4407
4408 if (!Universe::heap()->supports_inline_contig_alloc()) {
4409 // No allocation in the shared eden.
4410 jmp(slow_case);
4411 }
4412
4413 NOT_LP64(get_thread(thread_reg));
4414
4415 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4416 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4417
4418 // calculate amount of free space
4419 subptr(t1, top);
4420 shrptr(t1, LogHeapWordSize);
4421
4422 // Retain tlab and allocate object in shared space if
4423 // the amount free in the tlab is too large to discard.
4424 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
4425 jcc(Assembler::lessEqual, discard_tlab);
4426
4427 // Retain
4428 // %%% yuck as movptr...
4429 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
4430 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
4431 if (TLABStats) {
4432 // increment number of slow_allocations
4433 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
4434 }
4435 jmp(try_eden);
4436
4437 bind(discard_tlab);
4438 if (TLABStats) {
4439 // increment number of refills
4440 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
4441 // accumulate wastage -- t1 is amount free in tlab
4442 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
4443 }
4444
4445 // if tlab is currently allocated (top or end != null) then
4446 // fill [top, end + alignment_reserve) with array object
4447 testptr(top, top);
4448 jcc(Assembler::zero, do_refill);
4449
4450 // set up the mark word
4451 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
4452 // set the length to the remaining space
4453 subptr(t1, typeArrayOopDesc::header_size(T_INT));
4454 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
4455 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
4456 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
4457 // set klass to intArrayKlass
4458 // dubious reloc why not an oop reloc?
4459 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
4460 // store klass last. concurrent gcs assumes klass length is valid if
4461 // klass field is not null.
4462 store_klass(top, t1);
4463
4464 movptr(t1, top);
4465 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4466 incr_allocated_bytes(thread_reg, t1, 0);
4467
4468 // refill the tlab with an eden allocation
4469 bind(do_refill);
4470 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4471 shlptr(t1, LogHeapWordSize);
4472 // allocate new tlab, address returned in top
4473 eden_allocate(top, t1, 0, t2, slow_case);
4474
4475 // Check that t1 was preserved in eden_allocate.
4476 #ifdef ASSERT
4477 if (UseTLAB) {
4478 Label ok;
4479 Register tsize = rsi;
4480 assert_different_registers(tsize, thread_reg, t1);
4481 push(tsize);
4482 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4483 shlptr(tsize, LogHeapWordSize);
4484 cmpptr(t1, tsize);
4485 jcc(Assembler::equal, ok);
4486 STOP("assert(t1 != tlab size)");
4487 should_not_reach_here();
4488
4489 bind(ok);
4490 pop(tsize);
4491 }
4492 #endif
4493 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
4494 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
4495 addptr(top, t1);
4496 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
4497 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
4498 verify_tlab();
4499 jmp(retry);
4500
4501 return thread_reg; // for use by caller
4502 }
4503
4504 void MacroAssembler::incr_allocated_bytes(Register thread,
4505 Register var_size_in_bytes,
4506 int con_size_in_bytes,
4507 Register t1) {
4508 if (!thread->is_valid()) {
4509 #ifdef _LP64
4510 thread = r15_thread;
4511 #else
4512 assert(t1->is_valid(), "need temp reg");
4513 thread = t1;
4514 get_thread(thread);
4515 #endif
4516 }
4517
4518 #ifdef _LP64
4519 if (var_size_in_bytes->is_valid()) {
4520 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4521 } else {
4522 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4523 }
4524 #else
4525 if (var_size_in_bytes->is_valid()) {
4526 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4527 } else {
4528 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4529 }
4530 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
4531 #endif
4532 }
4533
4534 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
4535 pusha();
4536
4537 // if we are coming from c1, xmm registers may be live
4538 int off = 0;
4539 if (UseSSE == 1) {
4540 subptr(rsp, sizeof(jdouble)*8);
4541 movflt(Address(rsp,off++*sizeof(jdouble)),xmm0);
4542 movflt(Address(rsp,off++*sizeof(jdouble)),xmm1);
4543 movflt(Address(rsp,off++*sizeof(jdouble)),xmm2);
4544 movflt(Address(rsp,off++*sizeof(jdouble)),xmm3);
4545 movflt(Address(rsp,off++*sizeof(jdouble)),xmm4);
4546 movflt(Address(rsp,off++*sizeof(jdouble)),xmm5);
4547 movflt(Address(rsp,off++*sizeof(jdouble)),xmm6);
4548 movflt(Address(rsp,off++*sizeof(jdouble)),xmm7);
4549 } else if (UseSSE >= 2) {
4550 if (UseAVX > 2) {
4551 movl(rbx, 0xffff);
4552 kmovql(k1, rbx);
4553 }
4554 #ifdef COMPILER2
4555 if (MaxVectorSize > 16) {
4556 assert(UseAVX > 0, "256bit vectors are supported only with AVX");
4557 // Save upper half of YMM registes
4558 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4559 vextractf128h(Address(rsp, 0),xmm0);
4560 vextractf128h(Address(rsp, 16),xmm1);
4561 vextractf128h(Address(rsp, 32),xmm2);
4562 vextractf128h(Address(rsp, 48),xmm3);
4563 vextractf128h(Address(rsp, 64),xmm4);
4564 vextractf128h(Address(rsp, 80),xmm5);
4565 vextractf128h(Address(rsp, 96),xmm6);
4566 vextractf128h(Address(rsp,112),xmm7);
4567 #ifdef _LP64
4568 vextractf128h(Address(rsp,128),xmm8);
4569 vextractf128h(Address(rsp,144),xmm9);
4570 vextractf128h(Address(rsp,160),xmm10);
4571 vextractf128h(Address(rsp,176),xmm11);
4572 vextractf128h(Address(rsp,192),xmm12);
4573 vextractf128h(Address(rsp,208),xmm13);
4574 vextractf128h(Address(rsp,224),xmm14);
4575 vextractf128h(Address(rsp,240),xmm15);
4576 #endif
4577 }
4578 #endif
4579 // Save whole 128bit (16 bytes) XMM regiters
4580 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4581 movdqu(Address(rsp,off++*16),xmm0);
4582 movdqu(Address(rsp,off++*16),xmm1);
4583 movdqu(Address(rsp,off++*16),xmm2);
4584 movdqu(Address(rsp,off++*16),xmm3);
4585 movdqu(Address(rsp,off++*16),xmm4);
4586 movdqu(Address(rsp,off++*16),xmm5);
4587 movdqu(Address(rsp,off++*16),xmm6);
4588 movdqu(Address(rsp,off++*16),xmm7);
4589 #ifdef _LP64
4590 movdqu(Address(rsp,off++*16),xmm8);
4591 movdqu(Address(rsp,off++*16),xmm9);
4592 movdqu(Address(rsp,off++*16),xmm10);
4593 movdqu(Address(rsp,off++*16),xmm11);
4594 movdqu(Address(rsp,off++*16),xmm12);
4595 movdqu(Address(rsp,off++*16),xmm13);
4596 movdqu(Address(rsp,off++*16),xmm14);
4597 movdqu(Address(rsp,off++*16),xmm15);
4598 #endif
4599 }
4600
4601 // Preserve registers across runtime call
4602 int incoming_argument_and_return_value_offset = -1;
4603 if (num_fpu_regs_in_use > 1) {
4604 // Must preserve all other FPU regs (could alternatively convert
4605 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
4606 // FPU state, but can not trust C compiler)
4607 NEEDS_CLEANUP;
4608 // NOTE that in this case we also push the incoming argument(s) to
4609 // the stack and restore it later; we also use this stack slot to
4610 // hold the return value from dsin, dcos etc.
4611 for (int i = 0; i < num_fpu_regs_in_use; i++) {
4612 subptr(rsp, sizeof(jdouble));
4613 fstp_d(Address(rsp, 0));
4614 }
4615 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
4616 for (int i = nb_args-1; i >= 0; i--) {
4617 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
4618 }
4619 }
4620
4621 subptr(rsp, nb_args*sizeof(jdouble));
4622 for (int i = 0; i < nb_args; i++) {
4623 fstp_d(Address(rsp, i*sizeof(jdouble)));
4624 }
4625
4626 #ifdef _LP64
4627 if (nb_args > 0) {
4628 movdbl(xmm0, Address(rsp, 0));
4629 }
4630 if (nb_args > 1) {
4631 movdbl(xmm1, Address(rsp, sizeof(jdouble)));
4632 }
4633 assert(nb_args <= 2, "unsupported number of args");
4634 #endif // _LP64
4635
4636 // NOTE: we must not use call_VM_leaf here because that requires a
4637 // complete interpreter frame in debug mode -- same bug as 4387334
4638 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
4639 // do proper 64bit abi
4640
4641 NEEDS_CLEANUP;
4642 // Need to add stack banging before this runtime call if it needs to
4643 // be taken; however, there is no generic stack banging routine at
4644 // the MacroAssembler level
4645
4646 MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
4647
4648 #ifdef _LP64
4649 movsd(Address(rsp, 0), xmm0);
4650 fld_d(Address(rsp, 0));
4651 #endif // _LP64
4652 addptr(rsp, sizeof(jdouble) * nb_args);
4653 if (num_fpu_regs_in_use > 1) {
4654 // Must save return value to stack and then restore entire FPU
4655 // stack except incoming arguments
4656 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
4657 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
4658 fld_d(Address(rsp, 0));
4659 addptr(rsp, sizeof(jdouble));
4660 }
4661 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
4662 addptr(rsp, sizeof(jdouble) * nb_args);
4663 }
4664
4665 off = 0;
4666 if (UseSSE == 1) {
4667 movflt(xmm0, Address(rsp,off++*sizeof(jdouble)));
4668 movflt(xmm1, Address(rsp,off++*sizeof(jdouble)));
4669 movflt(xmm2, Address(rsp,off++*sizeof(jdouble)));
4670 movflt(xmm3, Address(rsp,off++*sizeof(jdouble)));
4671 movflt(xmm4, Address(rsp,off++*sizeof(jdouble)));
4672 movflt(xmm5, Address(rsp,off++*sizeof(jdouble)));
4673 movflt(xmm6, Address(rsp,off++*sizeof(jdouble)));
4674 movflt(xmm7, Address(rsp,off++*sizeof(jdouble)));
4675 addptr(rsp, sizeof(jdouble)*8);
4676 } else if (UseSSE >= 2) {
4677 // Restore whole 128bit (16 bytes) XMM regiters
4678 movdqu(xmm0, Address(rsp,off++*16));
4679 movdqu(xmm1, Address(rsp,off++*16));
4680 movdqu(xmm2, Address(rsp,off++*16));
4681 movdqu(xmm3, Address(rsp,off++*16));
4682 movdqu(xmm4, Address(rsp,off++*16));
4683 movdqu(xmm5, Address(rsp,off++*16));
4684 movdqu(xmm6, Address(rsp,off++*16));
4685 movdqu(xmm7, Address(rsp,off++*16));
4686 #ifdef _LP64
4687 movdqu(xmm8, Address(rsp,off++*16));
4688 movdqu(xmm9, Address(rsp,off++*16));
4689 movdqu(xmm10, Address(rsp,off++*16));
4690 movdqu(xmm11, Address(rsp,off++*16));
4691 movdqu(xmm12, Address(rsp,off++*16));
4692 movdqu(xmm13, Address(rsp,off++*16));
4693 movdqu(xmm14, Address(rsp,off++*16));
4694 movdqu(xmm15, Address(rsp,off++*16));
4695 #endif
4696 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4697 #ifdef COMPILER2
4698 if (MaxVectorSize > 16) {
4699 // Restore upper half of YMM registes.
4700 vinsertf128h(xmm0, Address(rsp, 0));
4701 vinsertf128h(xmm1, Address(rsp, 16));
4702 vinsertf128h(xmm2, Address(rsp, 32));
4703 vinsertf128h(xmm3, Address(rsp, 48));
4704 vinsertf128h(xmm4, Address(rsp, 64));
4705 vinsertf128h(xmm5, Address(rsp, 80));
4706 vinsertf128h(xmm6, Address(rsp, 96));
4707 vinsertf128h(xmm7, Address(rsp,112));
4708 #ifdef _LP64
4709 vinsertf128h(xmm8, Address(rsp,128));
4710 vinsertf128h(xmm9, Address(rsp,144));
4711 vinsertf128h(xmm10, Address(rsp,160));
4712 vinsertf128h(xmm11, Address(rsp,176));
4713 vinsertf128h(xmm12, Address(rsp,192));
4714 vinsertf128h(xmm13, Address(rsp,208));
4715 vinsertf128h(xmm14, Address(rsp,224));
4716 vinsertf128h(xmm15, Address(rsp,240));
4717 #endif
4718 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4719 }
4720 #endif
4721 }
4722 popa();
4723 }
4724
4725 static const double pi_4 = 0.7853981633974483;
4726
4727 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
4728 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
4729 // was attempted in this code; unfortunately it appears that the
4730 // switch to 80-bit precision and back causes this to be
4731 // unprofitable compared with simply performing a runtime call if
4732 // the argument is out of the (-pi/4, pi/4) range.
4733
4734 Register tmp = noreg;
4735 if (!VM_Version::supports_cmov()) {
4736 // fcmp needs a temporary so preserve rbx,
4737 tmp = rbx;
4738 push(tmp);
4739 }
4740
4741 Label slow_case, done;
4742
4743 ExternalAddress pi4_adr = (address)&pi_4;
4744 if (reachable(pi4_adr)) {
4745 // x ?<= pi/4
4746 fld_d(pi4_adr);
4747 fld_s(1); // Stack: X PI/4 X
4748 fabs(); // Stack: |X| PI/4 X
4749 fcmp(tmp);
4750 jcc(Assembler::above, slow_case);
4751
4752 // fastest case: -pi/4 <= x <= pi/4
4753 switch(trig) {
4754 case 's':
4755 fsin();
4756 break;
4757 case 'c':
4758 fcos();
4759 break;
4760 case 't':
4761 ftan();
4762 break;
4763 default:
4764 assert(false, "bad intrinsic");
4765 break;
4766 }
4767 jmp(done);
4768 }
4769
4770 // slow case: runtime call
4771 bind(slow_case);
4772
4773 switch(trig) {
4774 case 's':
4775 {
4776 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
4777 }
4778 break;
4779 case 'c':
4780 {
4781 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
4782 }
4783 break;
4784 case 't':
4785 {
4786 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
4787 }
4788 break;
4789 default:
4790 assert(false, "bad intrinsic");
4791 break;
4792 }
4793
4794 // Come here with result in F-TOS
4795 bind(done);
4796
4797 if (tmp != noreg) {
4798 pop(tmp);
4799 }
4800 }
4801
4802
4803 // Look up the method for a megamorphic invokeinterface call.
4804 // The target method is determined by <intf_klass, itable_index>.
4805 // The receiver klass is in recv_klass.
4806 // On success, the result will be in method_result, and execution falls through.
4807 // On failure, execution transfers to the given label.
4808 void MacroAssembler::lookup_interface_method(Register recv_klass,
4809 Register intf_klass,
4810 RegisterOrConstant itable_index,
4811 Register method_result,
4812 Register scan_temp,
4813 Label& L_no_such_interface) {
4814 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
4815 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4816 "caller must use same register for non-constant itable index as for method");
4817
4818 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4819 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
4820 int itentry_off = itableMethodEntry::method_offset_in_bytes();
4821 int scan_step = itableOffsetEntry::size() * wordSize;
4822 int vte_size = vtableEntry::size() * wordSize;
4823 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4824 assert(vte_size == wordSize, "else adjust times_vte_scale");
4825
4826 movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
4827
4828 // %%% Could store the aligned, prescaled offset in the klassoop.
4829 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4830 if (HeapWordsPerLong > 1) {
4831 // Round up to align_object_offset boundary
4832 // see code for InstanceKlass::start_of_itable!
4833 round_to(scan_temp, BytesPerLong);
4834 }
4835
4836 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4837 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4838 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4839
4840 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4841 // if (scan->interface() == intf) {
4842 // result = (klass + scan->offset() + itable_index);
4843 // }
4844 // }
4845 Label search, found_method;
4846
4847 for (int peel = 1; peel >= 0; peel--) {
4848 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4849 cmpptr(intf_klass, method_result);
4850
4851 if (peel) {
4852 jccb(Assembler::equal, found_method);
4853 } else {
4854 jccb(Assembler::notEqual, search);
4855 // (invert the test to fall through to found_method...)
4856 }
4857
4858 if (!peel) break;
4859
4860 bind(search);
4861
4862 // Check that the previous entry is non-null. A null entry means that
4863 // the receiver class doesn't implement the interface, and wasn't the
4864 // same as when the caller was compiled.
4865 testptr(method_result, method_result);
4866 jcc(Assembler::zero, L_no_such_interface);
4867 addptr(scan_temp, scan_step);
4868 }
4869
4870 bind(found_method);
4871
4872 // Got a hit.
4873 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4874 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4875 }
4876
4877
4878 // virtual method calling
4879 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4880 RegisterOrConstant vtable_index,
4881 Register method_result) {
4882 const int base = InstanceKlass::vtable_start_offset() * wordSize;
4883 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4884 Address vtable_entry_addr(recv_klass,
4885 vtable_index, Address::times_ptr,
4886 base + vtableEntry::method_offset_in_bytes());
4887 movptr(method_result, vtable_entry_addr);
4888 }
4889
4890
4891 void MacroAssembler::check_klass_subtype(Register sub_klass,
4892 Register super_klass,
4893 Register temp_reg,
4894 Label& L_success) {
4895 Label L_failure;
4896 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
4897 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4898 bind(L_failure);
4899 }
4900
4901
4902 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4903 Register super_klass,
4904 Register temp_reg,
4905 Label* L_success,
4906 Label* L_failure,
4907 Label* L_slow_path,
4908 RegisterOrConstant super_check_offset) {
4909 assert_different_registers(sub_klass, super_klass, temp_reg);
4910 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4911 if (super_check_offset.is_register()) {
4912 assert_different_registers(sub_klass, super_klass,
4913 super_check_offset.as_register());
4914 } else if (must_load_sco) {
4915 assert(temp_reg != noreg, "supply either a temp or a register offset");
4916 }
4917
4918 Label L_fallthrough;
4919 int label_nulls = 0;
4920 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4921 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4922 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4923 assert(label_nulls <= 1, "at most one NULL in the batch");
4924
4925 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4926 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4927 Address super_check_offset_addr(super_klass, sco_offset);
4928
4929 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4930 // range of a jccb. If this routine grows larger, reconsider at
4931 // least some of these.
4932 #define local_jcc(assembler_cond, label) \
4933 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4934 else jcc( assembler_cond, label) /*omit semi*/
4935
4936 // Hacked jmp, which may only be used just before L_fallthrough.
4937 #define final_jmp(label) \
4938 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4939 else jmp(label) /*omit semi*/
4940
4941 // If the pointers are equal, we are done (e.g., String[] elements).
4942 // This self-check enables sharing of secondary supertype arrays among
4943 // non-primary types such as array-of-interface. Otherwise, each such
4944 // type would need its own customized SSA.
4945 // We move this check to the front of the fast path because many
4946 // type checks are in fact trivially successful in this manner,
4947 // so we get a nicely predicted branch right at the start of the check.
4948 cmpptr(sub_klass, super_klass);
4949 local_jcc(Assembler::equal, *L_success);
4950
4951 // Check the supertype display:
4952 if (must_load_sco) {
4953 // Positive movl does right thing on LP64.
4954 movl(temp_reg, super_check_offset_addr);
4955 super_check_offset = RegisterOrConstant(temp_reg);
4956 }
4957 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4958 cmpptr(super_klass, super_check_addr); // load displayed supertype
4959
4960 // This check has worked decisively for primary supers.
4961 // Secondary supers are sought in the super_cache ('super_cache_addr').
4962 // (Secondary supers are interfaces and very deeply nested subtypes.)
4963 // This works in the same check above because of a tricky aliasing
4964 // between the super_cache and the primary super display elements.
4965 // (The 'super_check_addr' can address either, as the case requires.)
4966 // Note that the cache is updated below if it does not help us find
4967 // what we need immediately.
4968 // So if it was a primary super, we can just fail immediately.
4969 // Otherwise, it's the slow path for us (no success at this point).
4970
4971 if (super_check_offset.is_register()) {
4972 local_jcc(Assembler::equal, *L_success);
4973 cmpl(super_check_offset.as_register(), sc_offset);
4974 if (L_failure == &L_fallthrough) {
4975 local_jcc(Assembler::equal, *L_slow_path);
4976 } else {
4977 local_jcc(Assembler::notEqual, *L_failure);
4978 final_jmp(*L_slow_path);
4979 }
4980 } else if (super_check_offset.as_constant() == sc_offset) {
4981 // Need a slow path; fast failure is impossible.
4982 if (L_slow_path == &L_fallthrough) {
4983 local_jcc(Assembler::equal, *L_success);
4984 } else {
4985 local_jcc(Assembler::notEqual, *L_slow_path);
4986 final_jmp(*L_success);
4987 }
4988 } else {
4989 // No slow path; it's a fast decision.
4990 if (L_failure == &L_fallthrough) {
4991 local_jcc(Assembler::equal, *L_success);
4992 } else {
4993 local_jcc(Assembler::notEqual, *L_failure);
4994 final_jmp(*L_success);
4995 }
4996 }
4997
4998 bind(L_fallthrough);
4999
5000 #undef local_jcc
5001 #undef final_jmp
5002 }
5003
5004
5005 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5006 Register super_klass,
5007 Register temp_reg,
5008 Register temp2_reg,
5009 Label* L_success,
5010 Label* L_failure,
5011 bool set_cond_codes) {
5012 assert_different_registers(sub_klass, super_klass, temp_reg);
5013 if (temp2_reg != noreg)
5014 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5015 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5016
5017 Label L_fallthrough;
5018 int label_nulls = 0;
5019 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5020 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5021 assert(label_nulls <= 1, "at most one NULL in the batch");
5022
5023 // a couple of useful fields in sub_klass:
5024 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5025 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5026 Address secondary_supers_addr(sub_klass, ss_offset);
5027 Address super_cache_addr( sub_klass, sc_offset);
5028
5029 // Do a linear scan of the secondary super-klass chain.
5030 // This code is rarely used, so simplicity is a virtue here.
5031 // The repne_scan instruction uses fixed registers, which we must spill.
5032 // Don't worry too much about pre-existing connections with the input regs.
5033
5034 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5035 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5036
5037 // Get super_klass value into rax (even if it was in rdi or rcx).
5038 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5039 if (super_klass != rax || UseCompressedOops) {
5040 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5041 mov(rax, super_klass);
5042 }
5043 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5044 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5045
5046 #ifndef PRODUCT
5047 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5048 ExternalAddress pst_counter_addr((address) pst_counter);
5049 NOT_LP64( incrementl(pst_counter_addr) );
5050 LP64_ONLY( lea(rcx, pst_counter_addr) );
5051 LP64_ONLY( incrementl(Address(rcx, 0)) );
5052 #endif //PRODUCT
5053
5054 // We will consult the secondary-super array.
5055 movptr(rdi, secondary_supers_addr);
5056 // Load the array length. (Positive movl does right thing on LP64.)
5057 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5058 // Skip to start of data.
5059 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5060
5061 // Scan RCX words at [RDI] for an occurrence of RAX.
5062 // Set NZ/Z based on last compare.
5063 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5064 // not change flags (only scas instruction which is repeated sets flags).
5065 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5066
5067 testptr(rax,rax); // Set Z = 0
5068 repne_scan();
5069
5070 // Unspill the temp. registers:
5071 if (pushed_rdi) pop(rdi);
5072 if (pushed_rcx) pop(rcx);
5073 if (pushed_rax) pop(rax);
5074
5075 if (set_cond_codes) {
5076 // Special hack for the AD files: rdi is guaranteed non-zero.
5077 assert(!pushed_rdi, "rdi must be left non-NULL");
5078 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5079 }
5080
5081 if (L_failure == &L_fallthrough)
5082 jccb(Assembler::notEqual, *L_failure);
5083 else jcc(Assembler::notEqual, *L_failure);
5084
5085 // Success. Cache the super we found and proceed in triumph.
5086 movptr(super_cache_addr, super_klass);
5087
5088 if (L_success != &L_fallthrough) {
5089 jmp(*L_success);
5090 }
5091
5092 #undef IS_A_TEMP
5093
5094 bind(L_fallthrough);
5095 }
5096
5097
5098 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5099 if (VM_Version::supports_cmov()) {
5100 cmovl(cc, dst, src);
5101 } else {
5102 Label L;
5103 jccb(negate_condition(cc), L);
5104 movl(dst, src);
5105 bind(L);
5106 }
5107 }
5108
5109 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5110 if (VM_Version::supports_cmov()) {
5111 cmovl(cc, dst, src);
5112 } else {
5113 Label L;
5114 jccb(negate_condition(cc), L);
5115 movl(dst, src);
5116 bind(L);
5117 }
5118 }
5119
5120 void MacroAssembler::verify_oop(Register reg, const char* s) {
5121 if (!VerifyOops) return;
5122
5123 // Pass register number to verify_oop_subroutine
5124 const char* b = NULL;
5125 {
5126 ResourceMark rm;
5127 stringStream ss;
5128 ss.print("verify_oop: %s: %s", reg->name(), s);
5129 b = code_string(ss.as_string());
5130 }
5131 BLOCK_COMMENT("verify_oop {");
5132 #ifdef _LP64
5133 push(rscratch1); // save r10, trashed by movptr()
5134 #endif
5135 push(rax); // save rax,
5136 push(reg); // pass register argument
5137 ExternalAddress buffer((address) b);
5138 // avoid using pushptr, as it modifies scratch registers
5139 // and our contract is not to modify anything
5140 movptr(rax, buffer.addr());
5141 push(rax);
5142 // call indirectly to solve generation ordering problem
5143 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5144 call(rax);
5145 // Caller pops the arguments (oop, message) and restores rax, r10
5146 BLOCK_COMMENT("} verify_oop");
5147 }
5148
5149
5150 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
5151 Register tmp,
5152 int offset) {
5153 intptr_t value = *delayed_value_addr;
5154 if (value != 0)
5155 return RegisterOrConstant(value + offset);
5156
5157 // load indirectly to solve generation ordering problem
5158 movptr(tmp, ExternalAddress((address) delayed_value_addr));
5159
5160 #ifdef ASSERT
5161 { Label L;
5162 testptr(tmp, tmp);
5163 if (WizardMode) {
5164 const char* buf = NULL;
5165 {
5166 ResourceMark rm;
5167 stringStream ss;
5168 ss.print("DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]);
5169 buf = code_string(ss.as_string());
5170 }
5171 jcc(Assembler::notZero, L);
5172 STOP(buf);
5173 } else {
5174 jccb(Assembler::notZero, L);
5175 hlt();
5176 }
5177 bind(L);
5178 }
5179 #endif
5180
5181 if (offset != 0)
5182 addptr(tmp, offset);
5183
5184 return RegisterOrConstant(tmp);
5185 }
5186
5187
5188 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5189 int extra_slot_offset) {
5190 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5191 int stackElementSize = Interpreter::stackElementSize;
5192 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5193 #ifdef ASSERT
5194 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5195 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5196 #endif
5197 Register scale_reg = noreg;
5198 Address::ScaleFactor scale_factor = Address::no_scale;
5199 if (arg_slot.is_constant()) {
5200 offset += arg_slot.as_constant() * stackElementSize;
5201 } else {
5202 scale_reg = arg_slot.as_register();
5203 scale_factor = Address::times(stackElementSize);
5204 }
5205 offset += wordSize; // return PC is on stack
5206 return Address(rsp, scale_reg, scale_factor, offset);
5207 }
5208
5209
5210 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
5211 if (!VerifyOops) return;
5212
5213 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
5214 // Pass register number to verify_oop_subroutine
5215 const char* b = NULL;
5216 {
5217 ResourceMark rm;
5218 stringStream ss;
5219 ss.print("verify_oop_addr: %s", s);
5220 b = code_string(ss.as_string());
5221 }
5222 #ifdef _LP64
5223 push(rscratch1); // save r10, trashed by movptr()
5224 #endif
5225 push(rax); // save rax,
5226 // addr may contain rsp so we will have to adjust it based on the push
5227 // we just did (and on 64 bit we do two pushes)
5228 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5229 // stores rax into addr which is backwards of what was intended.
5230 if (addr.uses(rsp)) {
5231 lea(rax, addr);
5232 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5233 } else {
5234 pushptr(addr);
5235 }
5236
5237 ExternalAddress buffer((address) b);
5238 // pass msg argument
5239 // avoid using pushptr, as it modifies scratch registers
5240 // and our contract is not to modify anything
5241 movptr(rax, buffer.addr());
5242 push(rax);
5243
5244 // call indirectly to solve generation ordering problem
5245 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5246 call(rax);
5247 // Caller pops the arguments (addr, message) and restores rax, r10.
5248 }
5249
5250 void MacroAssembler::verify_tlab() {
5251 #ifdef ASSERT
5252 if (UseTLAB && VerifyOops) {
5253 Label next, ok;
5254 Register t1 = rsi;
5255 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5256
5257 push(t1);
5258 NOT_LP64(push(thread_reg));
5259 NOT_LP64(get_thread(thread_reg));
5260
5261 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5262 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5263 jcc(Assembler::aboveEqual, next);
5264 STOP("assert(top >= start)");
5265 should_not_reach_here();
5266
5267 bind(next);
5268 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5269 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5270 jcc(Assembler::aboveEqual, ok);
5271 STOP("assert(top <= end)");
5272 should_not_reach_here();
5273
5274 bind(ok);
5275 NOT_LP64(pop(thread_reg));
5276 pop(t1);
5277 }
5278 #endif
5279 }
5280
5281 class ControlWord {
5282 public:
5283 int32_t _value;
5284
5285 int rounding_control() const { return (_value >> 10) & 3 ; }
5286 int precision_control() const { return (_value >> 8) & 3 ; }
5287 bool precision() const { return ((_value >> 5) & 1) != 0; }
5288 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5289 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5290 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5291 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5292 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5293
5294 void print() const {
5295 // rounding control
5296 const char* rc;
5297 switch (rounding_control()) {
5298 case 0: rc = "round near"; break;
5299 case 1: rc = "round down"; break;
5300 case 2: rc = "round up "; break;
5301 case 3: rc = "chop "; break;
5302 };
5303 // precision control
5304 const char* pc;
5305 switch (precision_control()) {
5306 case 0: pc = "24 bits "; break;
5307 case 1: pc = "reserved"; break;
5308 case 2: pc = "53 bits "; break;
5309 case 3: pc = "64 bits "; break;
5310 };
5311 // flags
5312 char f[9];
5313 f[0] = ' ';
5314 f[1] = ' ';
5315 f[2] = (precision ()) ? 'P' : 'p';
5316 f[3] = (underflow ()) ? 'U' : 'u';
5317 f[4] = (overflow ()) ? 'O' : 'o';
5318 f[5] = (zero_divide ()) ? 'Z' : 'z';
5319 f[6] = (denormalized()) ? 'D' : 'd';
5320 f[7] = (invalid ()) ? 'I' : 'i';
5321 f[8] = '\x0';
5322 // output
5323 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5324 }
5325
5326 };
5327
5328 class StatusWord {
5329 public:
5330 int32_t _value;
5331
5332 bool busy() const { return ((_value >> 15) & 1) != 0; }
5333 bool C3() const { return ((_value >> 14) & 1) != 0; }
5334 bool C2() const { return ((_value >> 10) & 1) != 0; }
5335 bool C1() const { return ((_value >> 9) & 1) != 0; }
5336 bool C0() const { return ((_value >> 8) & 1) != 0; }
5337 int top() const { return (_value >> 11) & 7 ; }
5338 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5339 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5340 bool precision() const { return ((_value >> 5) & 1) != 0; }
5341 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5342 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5343 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5344 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5345 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5346
5347 void print() const {
5348 // condition codes
5349 char c[5];
5350 c[0] = (C3()) ? '3' : '-';
5351 c[1] = (C2()) ? '2' : '-';
5352 c[2] = (C1()) ? '1' : '-';
5353 c[3] = (C0()) ? '0' : '-';
5354 c[4] = '\x0';
5355 // flags
5356 char f[9];
5357 f[0] = (error_status()) ? 'E' : '-';
5358 f[1] = (stack_fault ()) ? 'S' : '-';
5359 f[2] = (precision ()) ? 'P' : '-';
5360 f[3] = (underflow ()) ? 'U' : '-';
5361 f[4] = (overflow ()) ? 'O' : '-';
5362 f[5] = (zero_divide ()) ? 'Z' : '-';
5363 f[6] = (denormalized()) ? 'D' : '-';
5364 f[7] = (invalid ()) ? 'I' : '-';
5365 f[8] = '\x0';
5366 // output
5367 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5368 }
5369
5370 };
5371
5372 class TagWord {
5373 public:
5374 int32_t _value;
5375
5376 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5377
5378 void print() const {
5379 printf("%04x", _value & 0xFFFF);
5380 }
5381
5382 };
5383
5384 class FPU_Register {
5385 public:
5386 int32_t _m0;
5387 int32_t _m1;
5388 int16_t _ex;
5389
5390 bool is_indefinite() const {
5391 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5392 }
5393
5394 void print() const {
5395 char sign = (_ex < 0) ? '-' : '+';
5396 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5397 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5398 };
5399
5400 };
5401
5402 class FPU_State {
5403 public:
5404 enum {
5405 register_size = 10,
5406 number_of_registers = 8,
5407 register_mask = 7
5408 };
5409
5410 ControlWord _control_word;
5411 StatusWord _status_word;
5412 TagWord _tag_word;
5413 int32_t _error_offset;
5414 int32_t _error_selector;
5415 int32_t _data_offset;
5416 int32_t _data_selector;
5417 int8_t _register[register_size * number_of_registers];
5418
5419 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5420 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5421
5422 const char* tag_as_string(int tag) const {
5423 switch (tag) {
5424 case 0: return "valid";
5425 case 1: return "zero";
5426 case 2: return "special";
5427 case 3: return "empty";
5428 }
5429 ShouldNotReachHere();
5430 return NULL;
5431 }
5432
5433 void print() const {
5434 // print computation registers
5435 { int t = _status_word.top();
5436 for (int i = 0; i < number_of_registers; i++) {
5437 int j = (i - t) & register_mask;
5438 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5439 st(j)->print();
5440 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5441 }
5442 }
5443 printf("\n");
5444 // print control registers
5445 printf("ctrl = "); _control_word.print(); printf("\n");
5446 printf("stat = "); _status_word .print(); printf("\n");
5447 printf("tags = "); _tag_word .print(); printf("\n");
5448 }
5449
5450 };
5451
5452 class Flag_Register {
5453 public:
5454 int32_t _value;
5455
5456 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5457 bool direction() const { return ((_value >> 10) & 1) != 0; }
5458 bool sign() const { return ((_value >> 7) & 1) != 0; }
5459 bool zero() const { return ((_value >> 6) & 1) != 0; }
5460 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5461 bool parity() const { return ((_value >> 2) & 1) != 0; }
5462 bool carry() const { return ((_value >> 0) & 1) != 0; }
5463
5464 void print() const {
5465 // flags
5466 char f[8];
5467 f[0] = (overflow ()) ? 'O' : '-';
5468 f[1] = (direction ()) ? 'D' : '-';
5469 f[2] = (sign ()) ? 'S' : '-';
5470 f[3] = (zero ()) ? 'Z' : '-';
5471 f[4] = (auxiliary_carry()) ? 'A' : '-';
5472 f[5] = (parity ()) ? 'P' : '-';
5473 f[6] = (carry ()) ? 'C' : '-';
5474 f[7] = '\x0';
5475 // output
5476 printf("%08x flags = %s", _value, f);
5477 }
5478
5479 };
5480
5481 class IU_Register {
5482 public:
5483 int32_t _value;
5484
5485 void print() const {
5486 printf("%08x %11d", _value, _value);
5487 }
5488
5489 };
5490
5491 class IU_State {
5492 public:
5493 Flag_Register _eflags;
5494 IU_Register _rdi;
5495 IU_Register _rsi;
5496 IU_Register _rbp;
5497 IU_Register _rsp;
5498 IU_Register _rbx;
5499 IU_Register _rdx;
5500 IU_Register _rcx;
5501 IU_Register _rax;
5502
5503 void print() const {
5504 // computation registers
5505 printf("rax, = "); _rax.print(); printf("\n");
5506 printf("rbx, = "); _rbx.print(); printf("\n");
5507 printf("rcx = "); _rcx.print(); printf("\n");
5508 printf("rdx = "); _rdx.print(); printf("\n");
5509 printf("rdi = "); _rdi.print(); printf("\n");
5510 printf("rsi = "); _rsi.print(); printf("\n");
5511 printf("rbp, = "); _rbp.print(); printf("\n");
5512 printf("rsp = "); _rsp.print(); printf("\n");
5513 printf("\n");
5514 // control registers
5515 printf("flgs = "); _eflags.print(); printf("\n");
5516 }
5517 };
5518
5519
5520 class CPU_State {
5521 public:
5522 FPU_State _fpu_state;
5523 IU_State _iu_state;
5524
5525 void print() const {
5526 printf("--------------------------------------------------\n");
5527 _iu_state .print();
5528 printf("\n");
5529 _fpu_state.print();
5530 printf("--------------------------------------------------\n");
5531 }
5532
5533 };
5534
5535
5536 static void _print_CPU_state(CPU_State* state) {
5537 state->print();
5538 };
5539
5540
5541 void MacroAssembler::print_CPU_state() {
5542 push_CPU_state();
5543 push(rsp); // pass CPU state
5544 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5545 addptr(rsp, wordSize); // discard argument
5546 pop_CPU_state();
5547 }
5548
5549
5550 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5551 static int counter = 0;
5552 FPU_State* fs = &state->_fpu_state;
5553 counter++;
5554 // For leaf calls, only verify that the top few elements remain empty.
5555 // We only need 1 empty at the top for C2 code.
5556 if( stack_depth < 0 ) {
5557 if( fs->tag_for_st(7) != 3 ) {
5558 printf("FPR7 not empty\n");
5559 state->print();
5560 assert(false, "error");
5561 return false;
5562 }
5563 return true; // All other stack states do not matter
5564 }
5565
5566 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5567 "bad FPU control word");
5568
5569 // compute stack depth
5570 int i = 0;
5571 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5572 int d = i;
5573 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5574 // verify findings
5575 if (i != FPU_State::number_of_registers) {
5576 // stack not contiguous
5577 printf("%s: stack not contiguous at ST%d\n", s, i);
5578 state->print();
5579 assert(false, "error");
5580 return false;
5581 }
5582 // check if computed stack depth corresponds to expected stack depth
5583 if (stack_depth < 0) {
5584 // expected stack depth is -stack_depth or less
5585 if (d > -stack_depth) {
5586 // too many elements on the stack
5587 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5588 state->print();
5589 assert(false, "error");
5590 return false;
5591 }
5592 } else {
5593 // expected stack depth is stack_depth
5594 if (d != stack_depth) {
5595 // wrong stack depth
5596 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5597 state->print();
5598 assert(false, "error");
5599 return false;
5600 }
5601 }
5602 // everything is cool
5603 return true;
5604 }
5605
5606
5607 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5608 if (!VerifyFPU) return;
5609 push_CPU_state();
5610 push(rsp); // pass CPU state
5611 ExternalAddress msg((address) s);
5612 // pass message string s
5613 pushptr(msg.addr());
5614 push(stack_depth); // pass stack depth
5615 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5616 addptr(rsp, 3 * wordSize); // discard arguments
5617 // check for error
5618 { Label L;
5619 testl(rax, rax);
5620 jcc(Assembler::notZero, L);
5621 int3(); // break if error condition
5622 bind(L);
5623 }
5624 pop_CPU_state();
5625 }
5626
5627 void MacroAssembler::restore_cpu_control_state_after_jni() {
5628 // Either restore the MXCSR register after returning from the JNI Call
5629 // or verify that it wasn't changed (with -Xcheck:jni flag).
5630 if (VM_Version::supports_sse()) {
5631 if (RestoreMXCSROnJNICalls) {
5632 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5633 } else if (CheckJNICalls) {
5634 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5635 }
5636 }
5637 if (VM_Version::supports_avx()) {
5638 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5639 vzeroupper();
5640 }
5641
5642 #ifndef _LP64
5643 // Either restore the x87 floating pointer control word after returning
5644 // from the JNI call or verify that it wasn't changed.
5645 if (CheckJNICalls) {
5646 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5647 }
5648 #endif // _LP64
5649 }
5650
5651
5652 void MacroAssembler::load_klass(Register dst, Register src) {
5653 #ifdef _LP64
5654 if (UseCompressedClassPointers) {
5655 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5656 decode_klass_not_null(dst);
5657 } else
5658 #endif
5659 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5660 }
5661
5662 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5663 load_klass(dst, src);
5664 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5665 }
5666
5667 void MacroAssembler::store_klass(Register dst, Register src) {
5668 #ifdef _LP64
5669 if (UseCompressedClassPointers) {
5670 encode_klass_not_null(src);
5671 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5672 } else
5673 #endif
5674 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5675 }
5676
5677 void MacroAssembler::load_heap_oop(Register dst, Address src) {
5678 #ifdef _LP64
5679 // FIXME: Must change all places where we try to load the klass.
5680 if (UseCompressedOops) {
5681 movl(dst, src);
5682 decode_heap_oop(dst);
5683 } else
5684 #endif
5685 movptr(dst, src);
5686 }
5687
5688 // Doesn't do verfication, generates fixed size code
5689 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
5690 #ifdef _LP64
5691 if (UseCompressedOops) {
5692 movl(dst, src);
5693 decode_heap_oop_not_null(dst);
5694 } else
5695 #endif
5696 movptr(dst, src);
5697 }
5698
5699 void MacroAssembler::store_heap_oop(Address dst, Register src) {
5700 #ifdef _LP64
5701 if (UseCompressedOops) {
5702 assert(!dst.uses(src), "not enough registers");
5703 encode_heap_oop(src);
5704 movl(dst, src);
5705 } else
5706 #endif
5707 movptr(dst, src);
5708 }
5709
5710 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
5711 assert_different_registers(src1, tmp);
5712 #ifdef _LP64
5713 if (UseCompressedOops) {
5714 bool did_push = false;
5715 if (tmp == noreg) {
5716 tmp = rax;
5717 push(tmp);
5718 did_push = true;
5719 assert(!src2.uses(rsp), "can't push");
5720 }
5721 load_heap_oop(tmp, src2);
5722 cmpptr(src1, tmp);
5723 if (did_push) pop(tmp);
5724 } else
5725 #endif
5726 cmpptr(src1, src2);
5727 }
5728
5729 // Used for storing NULLs.
5730 void MacroAssembler::store_heap_oop_null(Address dst) {
5731 #ifdef _LP64
5732 if (UseCompressedOops) {
5733 movl(dst, (int32_t)NULL_WORD);
5734 } else {
5735 movslq(dst, (int32_t)NULL_WORD);
5736 }
5737 #else
5738 movl(dst, (int32_t)NULL_WORD);
5739 #endif
5740 }
5741
5742 #ifdef _LP64
5743 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5744 if (UseCompressedClassPointers) {
5745 // Store to klass gap in destination
5746 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5747 }
5748 }
5749
5750 #ifdef ASSERT
5751 void MacroAssembler::verify_heapbase(const char* msg) {
5752 assert (UseCompressedOops, "should be compressed");
5753 assert (Universe::heap() != NULL, "java heap should be initialized");
5754 if (CheckCompressedOops) {
5755 Label ok;
5756 push(rscratch1); // cmpptr trashes rscratch1
5757 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5758 jcc(Assembler::equal, ok);
5759 STOP(msg);
5760 bind(ok);
5761 pop(rscratch1);
5762 }
5763 }
5764 #endif
5765
5766 // Algorithm must match oop.inline.hpp encode_heap_oop.
5767 void MacroAssembler::encode_heap_oop(Register r) {
5768 #ifdef ASSERT
5769 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5770 #endif
5771 verify_oop(r, "broken oop in encode_heap_oop");
5772 if (Universe::narrow_oop_base() == NULL) {
5773 if (Universe::narrow_oop_shift() != 0) {
5774 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5775 shrq(r, LogMinObjAlignmentInBytes);
5776 }
5777 return;
5778 }
5779 testq(r, r);
5780 cmovq(Assembler::equal, r, r12_heapbase);
5781 subq(r, r12_heapbase);
5782 shrq(r, LogMinObjAlignmentInBytes);
5783 }
5784
5785 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5786 #ifdef ASSERT
5787 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5788 if (CheckCompressedOops) {
5789 Label ok;
5790 testq(r, r);
5791 jcc(Assembler::notEqual, ok);
5792 STOP("null oop passed to encode_heap_oop_not_null");
5793 bind(ok);
5794 }
5795 #endif
5796 verify_oop(r, "broken oop in encode_heap_oop_not_null");
5797 if (Universe::narrow_oop_base() != NULL) {
5798 subq(r, r12_heapbase);
5799 }
5800 if (Universe::narrow_oop_shift() != 0) {
5801 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5802 shrq(r, LogMinObjAlignmentInBytes);
5803 }
5804 }
5805
5806 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5807 #ifdef ASSERT
5808 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5809 if (CheckCompressedOops) {
5810 Label ok;
5811 testq(src, src);
5812 jcc(Assembler::notEqual, ok);
5813 STOP("null oop passed to encode_heap_oop_not_null2");
5814 bind(ok);
5815 }
5816 #endif
5817 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5818 if (dst != src) {
5819 movq(dst, src);
5820 }
5821 if (Universe::narrow_oop_base() != NULL) {
5822 subq(dst, r12_heapbase);
5823 }
5824 if (Universe::narrow_oop_shift() != 0) {
5825 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5826 shrq(dst, LogMinObjAlignmentInBytes);
5827 }
5828 }
5829
5830 void MacroAssembler::decode_heap_oop(Register r) {
5831 #ifdef ASSERT
5832 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5833 #endif
5834 if (Universe::narrow_oop_base() == NULL) {
5835 if (Universe::narrow_oop_shift() != 0) {
5836 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5837 shlq(r, LogMinObjAlignmentInBytes);
5838 }
5839 } else {
5840 Label done;
5841 shlq(r, LogMinObjAlignmentInBytes);
5842 jccb(Assembler::equal, done);
5843 addq(r, r12_heapbase);
5844 bind(done);
5845 }
5846 verify_oop(r, "broken oop in decode_heap_oop");
5847 }
5848
5849 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5850 // Note: it will change flags
5851 assert (UseCompressedOops, "should only be used for compressed headers");
5852 assert (Universe::heap() != NULL, "java heap should be initialized");
5853 // Cannot assert, unverified entry point counts instructions (see .ad file)
5854 // vtableStubs also counts instructions in pd_code_size_limit.
5855 // Also do not verify_oop as this is called by verify_oop.
5856 if (Universe::narrow_oop_shift() != 0) {
5857 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5858 shlq(r, LogMinObjAlignmentInBytes);
5859 if (Universe::narrow_oop_base() != NULL) {
5860 addq(r, r12_heapbase);
5861 }
5862 } else {
5863 assert (Universe::narrow_oop_base() == NULL, "sanity");
5864 }
5865 }
5866
5867 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5868 // Note: it will change flags
5869 assert (UseCompressedOops, "should only be used for compressed headers");
5870 assert (Universe::heap() != NULL, "java heap should be initialized");
5871 // Cannot assert, unverified entry point counts instructions (see .ad file)
5872 // vtableStubs also counts instructions in pd_code_size_limit.
5873 // Also do not verify_oop as this is called by verify_oop.
5874 if (Universe::narrow_oop_shift() != 0) {
5875 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5876 if (LogMinObjAlignmentInBytes == Address::times_8) {
5877 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5878 } else {
5879 if (dst != src) {
5880 movq(dst, src);
5881 }
5882 shlq(dst, LogMinObjAlignmentInBytes);
5883 if (Universe::narrow_oop_base() != NULL) {
5884 addq(dst, r12_heapbase);
5885 }
5886 }
5887 } else {
5888 assert (Universe::narrow_oop_base() == NULL, "sanity");
5889 if (dst != src) {
5890 movq(dst, src);
5891 }
5892 }
5893 }
5894
5895 void MacroAssembler::encode_klass_not_null(Register r) {
5896 if (Universe::narrow_klass_base() != NULL) {
5897 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5898 assert(r != r12_heapbase, "Encoding a klass in r12");
5899 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5900 subq(r, r12_heapbase);
5901 }
5902 if (Universe::narrow_klass_shift() != 0) {
5903 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5904 shrq(r, LogKlassAlignmentInBytes);
5905 }
5906 if (Universe::narrow_klass_base() != NULL) {
5907 reinit_heapbase();
5908 }
5909 }
5910
5911 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5912 if (dst == src) {
5913 encode_klass_not_null(src);
5914 } else {
5915 if (Universe::narrow_klass_base() != NULL) {
5916 mov64(dst, (int64_t)Universe::narrow_klass_base());
5917 negq(dst);
5918 addq(dst, src);
5919 } else {
5920 movptr(dst, src);
5921 }
5922 if (Universe::narrow_klass_shift() != 0) {
5923 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5924 shrq(dst, LogKlassAlignmentInBytes);
5925 }
5926 }
5927 }
5928
5929 // Function instr_size_for_decode_klass_not_null() counts the instructions
5930 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5931 // when (Universe::heap() != NULL). Hence, if the instructions they
5932 // generate change, then this method needs to be updated.
5933 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5934 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5935 if (Universe::narrow_klass_base() != NULL) {
5936 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
5937 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
5938 } else {
5939 // longest load decode klass function, mov64, leaq
5940 return 16;
5941 }
5942 }
5943
5944 // !!! If the instructions that get generated here change then function
5945 // instr_size_for_decode_klass_not_null() needs to get updated.
5946 void MacroAssembler::decode_klass_not_null(Register r) {
5947 // Note: it will change flags
5948 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5949 assert(r != r12_heapbase, "Decoding a klass in r12");
5950 // Cannot assert, unverified entry point counts instructions (see .ad file)
5951 // vtableStubs also counts instructions in pd_code_size_limit.
5952 // Also do not verify_oop as this is called by verify_oop.
5953 if (Universe::narrow_klass_shift() != 0) {
5954 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5955 shlq(r, LogKlassAlignmentInBytes);
5956 }
5957 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5958 if (Universe::narrow_klass_base() != NULL) {
5959 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5960 addq(r, r12_heapbase);
5961 reinit_heapbase();
5962 }
5963 }
5964
5965 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5966 // Note: it will change flags
5967 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5968 if (dst == src) {
5969 decode_klass_not_null(dst);
5970 } else {
5971 // Cannot assert, unverified entry point counts instructions (see .ad file)
5972 // vtableStubs also counts instructions in pd_code_size_limit.
5973 // Also do not verify_oop as this is called by verify_oop.
5974 mov64(dst, (int64_t)Universe::narrow_klass_base());
5975 if (Universe::narrow_klass_shift() != 0) {
5976 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5977 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
5978 leaq(dst, Address(dst, src, Address::times_8, 0));
5979 } else {
5980 addq(dst, src);
5981 }
5982 }
5983 }
5984
5985 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5986 assert (UseCompressedOops, "should only be used for compressed headers");
5987 assert (Universe::heap() != NULL, "java heap should be initialized");
5988 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5989 int oop_index = oop_recorder()->find_index(obj);
5990 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5991 mov_narrow_oop(dst, oop_index, rspec);
5992 }
5993
5994 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5995 assert (UseCompressedOops, "should only be used for compressed headers");
5996 assert (Universe::heap() != NULL, "java heap should be initialized");
5997 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5998 int oop_index = oop_recorder()->find_index(obj);
5999 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6000 mov_narrow_oop(dst, oop_index, rspec);
6001 }
6002
6003 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6004 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6005 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6006 int klass_index = oop_recorder()->find_index(k);
6007 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6008 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6009 }
6010
6011 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6012 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6013 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6014 int klass_index = oop_recorder()->find_index(k);
6015 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6016 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6017 }
6018
6019 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6020 assert (UseCompressedOops, "should only be used for compressed headers");
6021 assert (Universe::heap() != NULL, "java heap should be initialized");
6022 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6023 int oop_index = oop_recorder()->find_index(obj);
6024 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6025 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6026 }
6027
6028 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6029 assert (UseCompressedOops, "should only be used for compressed headers");
6030 assert (Universe::heap() != NULL, "java heap should be initialized");
6031 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6032 int oop_index = oop_recorder()->find_index(obj);
6033 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6034 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6035 }
6036
6037 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6038 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6039 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6040 int klass_index = oop_recorder()->find_index(k);
6041 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6042 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6043 }
6044
6045 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6046 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6047 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6048 int klass_index = oop_recorder()->find_index(k);
6049 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6050 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6051 }
6052
6053 void MacroAssembler::reinit_heapbase() {
6054 if (UseCompressedOops || UseCompressedClassPointers) {
6055 if (Universe::heap() != NULL) {
6056 if (Universe::narrow_oop_base() == NULL) {
6057 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6058 } else {
6059 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6060 }
6061 } else {
6062 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6063 }
6064 }
6065 }
6066
6067 #endif // _LP64
6068
6069
6070 // C2 compiled method's prolog code.
6071 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6072
6073 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6074 // NativeJump::patch_verified_entry will be able to patch out the entry
6075 // code safely. The push to verify stack depth is ok at 5 bytes,
6076 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6077 // stack bang then we must use the 6 byte frame allocation even if
6078 // we have no frame. :-(
6079 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6080
6081 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6082 // Remove word for return addr
6083 framesize -= wordSize;
6084 stack_bang_size -= wordSize;
6085
6086 // Calls to C2R adapters often do not accept exceptional returns.
6087 // We require that their callers must bang for them. But be careful, because
6088 // some VM calls (such as call site linkage) can use several kilobytes of
6089 // stack. But the stack safety zone should account for that.
6090 // See bugs 4446381, 4468289, 4497237.
6091 if (stack_bang_size > 0) {
6092 generate_stack_overflow_check(stack_bang_size);
6093
6094 // We always push rbp, so that on return to interpreter rbp, will be
6095 // restored correctly and we can correct the stack.
6096 push(rbp);
6097 // Remove word for ebp
6098 framesize -= wordSize;
6099
6100 // Create frame
6101 if (framesize) {
6102 subptr(rsp, framesize);
6103 }
6104 } else {
6105 // Create frame (force generation of a 4 byte immediate value)
6106 subptr_imm32(rsp, framesize);
6107
6108 // Save RBP register now.
6109 framesize -= wordSize;
6110 movptr(Address(rsp, framesize), rbp);
6111 }
6112
6113 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6114 framesize -= wordSize;
6115 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6116 }
6117
6118 #ifndef _LP64
6119 // If method sets FPU control word do it now
6120 if (fp_mode_24b) {
6121 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6122 }
6123 if (UseSSE >= 2 && VerifyFPU) {
6124 verify_FPU(0, "FPU stack must be clean on entry");
6125 }
6126 #endif
6127
6128 #ifdef ASSERT
6129 if (VerifyStackAtCalls) {
6130 Label L;
6131 push(rax);
6132 mov(rax, rsp);
6133 andptr(rax, StackAlignmentInBytes-1);
6134 cmpptr(rax, StackAlignmentInBytes-wordSize);
6135 pop(rax);
6136 jcc(Assembler::equal, L);
6137 STOP("Stack is not properly aligned!");
6138 bind(L);
6139 }
6140 #endif
6141
6142 }
6143
6144 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) {
6145 // cnt - number of qwords (8-byte words).
6146 // base - start address, qword aligned.
6147 assert(base==rdi, "base register must be edi for rep stos");
6148 assert(tmp==rax, "tmp register must be eax for rep stos");
6149 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6150
6151 xorptr(tmp, tmp);
6152 if (UseFastStosb) {
6153 shlptr(cnt,3); // convert to number of bytes
6154 rep_stosb();
6155 } else {
6156 NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM
6157 rep_stos();
6158 }
6159 }
6160
6161 // IndexOf for constant substrings with size >= 8 chars
6162 // which don't need to be loaded through stack.
6163 void MacroAssembler::string_indexofC8(Register str1, Register str2,
6164 Register cnt1, Register cnt2,
6165 int int_cnt2, Register result,
6166 XMMRegister vec, Register tmp) {
6167 ShortBranchVerifier sbv(this);
6168 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6169
6170 // This method uses pcmpestri instruction with bound registers
6171 // inputs:
6172 // xmm - substring
6173 // rax - substring length (elements count)
6174 // mem - scanned string
6175 // rdx - string length (elements count)
6176 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6177 // outputs:
6178 // rcx - matched index in string
6179 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6180
6181 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
6182 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
6183 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
6184
6185 // Note, inline_string_indexOf() generates checks:
6186 // if (substr.count > string.count) return -1;
6187 // if (substr.count == 0) return 0;
6188 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars");
6189
6190 // Load substring.
6191 movdqu(vec, Address(str2, 0));
6192 movl(cnt2, int_cnt2);
6193 movptr(result, str1); // string addr
6194
6195 if (int_cnt2 > 8) {
6196 jmpb(SCAN_TO_SUBSTR);
6197
6198 // Reload substr for rescan, this code
6199 // is executed only for large substrings (> 8 chars)
6200 bind(RELOAD_SUBSTR);
6201 movdqu(vec, Address(str2, 0));
6202 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
6203
6204 bind(RELOAD_STR);
6205 // We came here after the beginning of the substring was
6206 // matched but the rest of it was not so we need to search
6207 // again. Start from the next element after the previous match.
6208
6209 // cnt2 is number of substring reminding elements and
6210 // cnt1 is number of string reminding elements when cmp failed.
6211 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
6212 subl(cnt1, cnt2);
6213 addl(cnt1, int_cnt2);
6214 movl(cnt2, int_cnt2); // Now restore cnt2
6215
6216 decrementl(cnt1); // Shift to next element
6217 cmpl(cnt1, cnt2);
6218 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6219
6220 addptr(result, 2);
6221
6222 } // (int_cnt2 > 8)
6223
6224 // Scan string for start of substr in 16-byte vectors
6225 bind(SCAN_TO_SUBSTR);
6226 pcmpestri(vec, Address(result, 0), 0x0d);
6227 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6228 subl(cnt1, 8);
6229 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6230 cmpl(cnt1, cnt2);
6231 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6232 addptr(result, 16);
6233 jmpb(SCAN_TO_SUBSTR);
6234
6235 // Found a potential substr
6236 bind(FOUND_CANDIDATE);
6237 // Matched whole vector if first element matched (tmp(rcx) == 0).
6238 if (int_cnt2 == 8) {
6239 jccb(Assembler::overflow, RET_FOUND); // OF == 1
6240 } else { // int_cnt2 > 8
6241 jccb(Assembler::overflow, FOUND_SUBSTR);
6242 }
6243 // After pcmpestri tmp(rcx) contains matched element index
6244 // Compute start addr of substr
6245 lea(result, Address(result, tmp, Address::times_2));
6246
6247 // Make sure string is still long enough
6248 subl(cnt1, tmp);
6249 cmpl(cnt1, cnt2);
6250 if (int_cnt2 == 8) {
6251 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6252 } else { // int_cnt2 > 8
6253 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
6254 }
6255 // Left less then substring.
6256
6257 bind(RET_NOT_FOUND);
6258 movl(result, -1);
6259 jmpb(EXIT);
6260
6261 if (int_cnt2 > 8) {
6262 // This code is optimized for the case when whole substring
6263 // is matched if its head is matched.
6264 bind(MATCH_SUBSTR_HEAD);
6265 pcmpestri(vec, Address(result, 0), 0x0d);
6266 // Reload only string if does not match
6267 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
6268
6269 Label CONT_SCAN_SUBSTR;
6270 // Compare the rest of substring (> 8 chars).
6271 bind(FOUND_SUBSTR);
6272 // First 8 chars are already matched.
6273 negptr(cnt2);
6274 addptr(cnt2, 8);
6275
6276 bind(SCAN_SUBSTR);
6277 subl(cnt1, 8);
6278 cmpl(cnt2, -8); // Do not read beyond substring
6279 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
6280 // Back-up strings to avoid reading beyond substring:
6281 // cnt1 = cnt1 - cnt2 + 8
6282 addl(cnt1, cnt2); // cnt2 is negative
6283 addl(cnt1, 8);
6284 movl(cnt2, 8); negptr(cnt2);
6285 bind(CONT_SCAN_SUBSTR);
6286 if (int_cnt2 < (int)G) {
6287 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2));
6288 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d);
6289 } else {
6290 // calculate index in register to avoid integer overflow (int_cnt2*2)
6291 movl(tmp, int_cnt2);
6292 addptr(tmp, cnt2);
6293 movdqu(vec, Address(str2, tmp, Address::times_2, 0));
6294 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d);
6295 }
6296 // Need to reload strings pointers if not matched whole vector
6297 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6298 addptr(cnt2, 8);
6299 jcc(Assembler::negative, SCAN_SUBSTR);
6300 // Fall through if found full substring
6301
6302 } // (int_cnt2 > 8)
6303
6304 bind(RET_FOUND);
6305 // Found result if we matched full small substring.
6306 // Compute substr offset
6307 subptr(result, str1);
6308 shrl(result, 1); // index
6309 bind(EXIT);
6310
6311 } // string_indexofC8
6312
6313 // Small strings are loaded through stack if they cross page boundary.
6314 void MacroAssembler::string_indexof(Register str1, Register str2,
6315 Register cnt1, Register cnt2,
6316 int int_cnt2, Register result,
6317 XMMRegister vec, Register tmp) {
6318 ShortBranchVerifier sbv(this);
6319 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6320 //
6321 // int_cnt2 is length of small (< 8 chars) constant substring
6322 // or (-1) for non constant substring in which case its length
6323 // is in cnt2 register.
6324 //
6325 // Note, inline_string_indexOf() generates checks:
6326 // if (substr.count > string.count) return -1;
6327 // if (substr.count == 0) return 0;
6328 //
6329 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0");
6330
6331 // This method uses pcmpestri instruction with bound registers
6332 // inputs:
6333 // xmm - substring
6334 // rax - substring length (elements count)
6335 // mem - scanned string
6336 // rdx - string length (elements count)
6337 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6338 // outputs:
6339 // rcx - matched index in string
6340 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6341
6342 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6343 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6344 FOUND_CANDIDATE;
6345
6346 { //========================================================
6347 // We don't know where these strings are located
6348 // and we can't read beyond them. Load them through stack.
6349 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6350
6351 movptr(tmp, rsp); // save old SP
6352
6353 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6354 if (int_cnt2 == 1) { // One char
6355 load_unsigned_short(result, Address(str2, 0));
6356 movdl(vec, result); // move 32 bits
6357 } else if (int_cnt2 == 2) { // Two chars
6358 movdl(vec, Address(str2, 0)); // move 32 bits
6359 } else if (int_cnt2 == 4) { // Four chars
6360 movq(vec, Address(str2, 0)); // move 64 bits
6361 } else { // cnt2 = { 3, 5, 6, 7 }
6362 // Array header size is 12 bytes in 32-bit VM
6363 // + 6 bytes for 3 chars == 18 bytes,
6364 // enough space to load vec and shift.
6365 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6366 movdqu(vec, Address(str2, (int_cnt2*2)-16));
6367 psrldq(vec, 16-(int_cnt2*2));
6368 }
6369 } else { // not constant substring
6370 cmpl(cnt2, 8);
6371 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6372
6373 // We can read beyond string if srt+16 does not cross page boundary
6374 // since heaps are aligned and mapped by pages.
6375 assert(os::vm_page_size() < (int)G, "default page should be small");
6376 movl(result, str2); // We need only low 32 bits
6377 andl(result, (os::vm_page_size()-1));
6378 cmpl(result, (os::vm_page_size()-16));
6379 jccb(Assembler::belowEqual, CHECK_STR);
6380
6381 // Move small strings to stack to allow load 16 bytes into vec.
6382 subptr(rsp, 16);
6383 int stk_offset = wordSize-2;
6384 push(cnt2);
6385
6386 bind(COPY_SUBSTR);
6387 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2));
6388 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6389 decrement(cnt2);
6390 jccb(Assembler::notZero, COPY_SUBSTR);
6391
6392 pop(cnt2);
6393 movptr(str2, rsp); // New substring address
6394 } // non constant
6395
6396 bind(CHECK_STR);
6397 cmpl(cnt1, 8);
6398 jccb(Assembler::aboveEqual, BIG_STRINGS);
6399
6400 // Check cross page boundary.
6401 movl(result, str1); // We need only low 32 bits
6402 andl(result, (os::vm_page_size()-1));
6403 cmpl(result, (os::vm_page_size()-16));
6404 jccb(Assembler::belowEqual, BIG_STRINGS);
6405
6406 subptr(rsp, 16);
6407 int stk_offset = -2;
6408 if (int_cnt2 < 0) { // not constant
6409 push(cnt2);
6410 stk_offset += wordSize;
6411 }
6412 movl(cnt2, cnt1);
6413
6414 bind(COPY_STR);
6415 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2));
6416 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6417 decrement(cnt2);
6418 jccb(Assembler::notZero, COPY_STR);
6419
6420 if (int_cnt2 < 0) { // not constant
6421 pop(cnt2);
6422 }
6423 movptr(str1, rsp); // New string address
6424
6425 bind(BIG_STRINGS);
6426 // Load substring.
6427 if (int_cnt2 < 0) { // -1
6428 movdqu(vec, Address(str2, 0));
6429 push(cnt2); // substr count
6430 push(str2); // substr addr
6431 push(str1); // string addr
6432 } else {
6433 // Small (< 8 chars) constant substrings are loaded already.
6434 movl(cnt2, int_cnt2);
6435 }
6436 push(tmp); // original SP
6437
6438 } // Finished loading
6439
6440 //========================================================
6441 // Start search
6442 //
6443
6444 movptr(result, str1); // string addr
6445
6446 if (int_cnt2 < 0) { // Only for non constant substring
6447 jmpb(SCAN_TO_SUBSTR);
6448
6449 // SP saved at sp+0
6450 // String saved at sp+1*wordSize
6451 // Substr saved at sp+2*wordSize
6452 // Substr count saved at sp+3*wordSize
6453
6454 // Reload substr for rescan, this code
6455 // is executed only for large substrings (> 8 chars)
6456 bind(RELOAD_SUBSTR);
6457 movptr(str2, Address(rsp, 2*wordSize));
6458 movl(cnt2, Address(rsp, 3*wordSize));
6459 movdqu(vec, Address(str2, 0));
6460 // We came here after the beginning of the substring was
6461 // matched but the rest of it was not so we need to search
6462 // again. Start from the next element after the previous match.
6463 subptr(str1, result); // Restore counter
6464 shrl(str1, 1);
6465 addl(cnt1, str1);
6466 decrementl(cnt1); // Shift to next element
6467 cmpl(cnt1, cnt2);
6468 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6469
6470 addptr(result, 2);
6471 } // non constant
6472
6473 // Scan string for start of substr in 16-byte vectors
6474 bind(SCAN_TO_SUBSTR);
6475 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6476 pcmpestri(vec, Address(result, 0), 0x0d);
6477 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6478 subl(cnt1, 8);
6479 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6480 cmpl(cnt1, cnt2);
6481 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6482 addptr(result, 16);
6483
6484 bind(ADJUST_STR);
6485 cmpl(cnt1, 8); // Do not read beyond string
6486 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6487 // Back-up string to avoid reading beyond string.
6488 lea(result, Address(result, cnt1, Address::times_2, -16));
6489 movl(cnt1, 8);
6490 jmpb(SCAN_TO_SUBSTR);
6491
6492 // Found a potential substr
6493 bind(FOUND_CANDIDATE);
6494 // After pcmpestri tmp(rcx) contains matched element index
6495
6496 // Make sure string is still long enough
6497 subl(cnt1, tmp);
6498 cmpl(cnt1, cnt2);
6499 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6500 // Left less then substring.
6501
6502 bind(RET_NOT_FOUND);
6503 movl(result, -1);
6504 jmpb(CLEANUP);
6505
6506 bind(FOUND_SUBSTR);
6507 // Compute start addr of substr
6508 lea(result, Address(result, tmp, Address::times_2));
6509
6510 if (int_cnt2 > 0) { // Constant substring
6511 // Repeat search for small substring (< 8 chars)
6512 // from new point without reloading substring.
6513 // Have to check that we don't read beyond string.
6514 cmpl(tmp, 8-int_cnt2);
6515 jccb(Assembler::greater, ADJUST_STR);
6516 // Fall through if matched whole substring.
6517 } else { // non constant
6518 assert(int_cnt2 == -1, "should be != 0");
6519
6520 addl(tmp, cnt2);
6521 // Found result if we matched whole substring.
6522 cmpl(tmp, 8);
6523 jccb(Assembler::lessEqual, RET_FOUND);
6524
6525 // Repeat search for small substring (<= 8 chars)
6526 // from new point 'str1' without reloading substring.
6527 cmpl(cnt2, 8);
6528 // Have to check that we don't read beyond string.
6529 jccb(Assembler::lessEqual, ADJUST_STR);
6530
6531 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6532 // Compare the rest of substring (> 8 chars).
6533 movptr(str1, result);
6534
6535 cmpl(tmp, cnt2);
6536 // First 8 chars are already matched.
6537 jccb(Assembler::equal, CHECK_NEXT);
6538
6539 bind(SCAN_SUBSTR);
6540 pcmpestri(vec, Address(str1, 0), 0x0d);
6541 // Need to reload strings pointers if not matched whole vector
6542 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6543
6544 bind(CHECK_NEXT);
6545 subl(cnt2, 8);
6546 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6547 addptr(str1, 16);
6548 addptr(str2, 16);
6549 subl(cnt1, 8);
6550 cmpl(cnt2, 8); // Do not read beyond substring
6551 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6552 // Back-up strings to avoid reading beyond substring.
6553 lea(str2, Address(str2, cnt2, Address::times_2, -16));
6554 lea(str1, Address(str1, cnt2, Address::times_2, -16));
6555 subl(cnt1, cnt2);
6556 movl(cnt2, 8);
6557 addl(cnt1, 8);
6558 bind(CONT_SCAN_SUBSTR);
6559 movdqu(vec, Address(str2, 0));
6560 jmpb(SCAN_SUBSTR);
6561
6562 bind(RET_FOUND_LONG);
6563 movptr(str1, Address(rsp, wordSize));
6564 } // non constant
6565
6566 bind(RET_FOUND);
6567 // Compute substr offset
6568 subptr(result, str1);
6569 shrl(result, 1); // index
6570
6571 bind(CLEANUP);
6572 pop(rsp); // restore SP
6573
6574 } // string_indexof
6575
6576 // Compare strings.
6577 void MacroAssembler::string_compare(Register str1, Register str2,
6578 Register cnt1, Register cnt2, Register result,
6579 XMMRegister vec1) {
6580 ShortBranchVerifier sbv(this);
6581 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6582
6583 // Compute the minimum of the string lengths and the
6584 // difference of the string lengths (stack).
6585 // Do the conditional move stuff
6586 movl(result, cnt1);
6587 subl(cnt1, cnt2);
6588 push(cnt1);
6589 cmov32(Assembler::lessEqual, cnt2, result);
6590
6591 // Is the minimum length zero?
6592 testl(cnt2, cnt2);
6593 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6594
6595 // Compare first characters
6596 load_unsigned_short(result, Address(str1, 0));
6597 load_unsigned_short(cnt1, Address(str2, 0));
6598 subl(result, cnt1);
6599 jcc(Assembler::notZero, POP_LABEL);
6600 cmpl(cnt2, 1);
6601 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6602
6603 // Check if the strings start at the same location.
6604 cmpptr(str1, str2);
6605 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6606
6607 Address::ScaleFactor scale = Address::times_2;
6608 int stride = 8;
6609
6610 if (UseAVX >= 2 && UseSSE42Intrinsics) {
6611 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6612 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6613 Label COMPARE_TAIL_LONG;
6614 int pcmpmask = 0x19;
6615
6616 // Setup to compare 16-chars (32-bytes) vectors,
6617 // start from first character again because it has aligned address.
6618 int stride2 = 16;
6619 int adr_stride = stride << scale;
6620
6621 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6622 // rax and rdx are used by pcmpestri as elements counters
6623 movl(result, cnt2);
6624 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
6625 jcc(Assembler::zero, COMPARE_TAIL_LONG);
6626
6627 // fast path : compare first 2 8-char vectors.
6628 bind(COMPARE_16_CHARS);
6629 movdqu(vec1, Address(str1, 0));
6630 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6631 jccb(Assembler::below, COMPARE_INDEX_CHAR);
6632
6633 movdqu(vec1, Address(str1, adr_stride));
6634 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6635 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6636 addl(cnt1, stride);
6637
6638 // Compare the characters at index in cnt1
6639 bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character
6640 load_unsigned_short(result, Address(str1, cnt1, scale));
6641 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6642 subl(result, cnt2);
6643 jmp(POP_LABEL);
6644
6645 // Setup the registers to start vector comparison loop
6646 bind(COMPARE_WIDE_VECTORS);
6647 lea(str1, Address(str1, result, scale));
6648 lea(str2, Address(str2, result, scale));
6649 subl(result, stride2);
6650 subl(cnt2, stride2);
6651 jccb(Assembler::zero, COMPARE_WIDE_TAIL);
6652 negptr(result);
6653
6654 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6655 bind(COMPARE_WIDE_VECTORS_LOOP);
6656 vmovdqu(vec1, Address(str1, result, scale));
6657 vpxor(vec1, Address(str2, result, scale));
6658 vptest(vec1, vec1);
6659 jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
6660 addptr(result, stride2);
6661 subl(cnt2, stride2);
6662 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6663 // clean upper bits of YMM registers
6664 vzeroupper();
6665
6666 // compare wide vectors tail
6667 bind(COMPARE_WIDE_TAIL);
6668 testptr(result, result);
6669 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6670
6671 movl(result, stride2);
6672 movl(cnt2, result);
6673 negptr(result);
6674 jmpb(COMPARE_WIDE_VECTORS_LOOP);
6675
6676 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6677 bind(VECTOR_NOT_EQUAL);
6678 // clean upper bits of YMM registers
6679 vzeroupper();
6680 lea(str1, Address(str1, result, scale));
6681 lea(str2, Address(str2, result, scale));
6682 jmp(COMPARE_16_CHARS);
6683
6684 // Compare tail chars, length between 1 to 15 chars
6685 bind(COMPARE_TAIL_LONG);
6686 movl(cnt2, result);
6687 cmpl(cnt2, stride);
6688 jccb(Assembler::less, COMPARE_SMALL_STR);
6689
6690 movdqu(vec1, Address(str1, 0));
6691 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6692 jcc(Assembler::below, COMPARE_INDEX_CHAR);
6693 subptr(cnt2, stride);
6694 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6695 lea(str1, Address(str1, result, scale));
6696 lea(str2, Address(str2, result, scale));
6697 negptr(cnt2);
6698 jmpb(WHILE_HEAD_LABEL);
6699
6700 bind(COMPARE_SMALL_STR);
6701 } else if (UseSSE42Intrinsics) {
6702 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6703 int pcmpmask = 0x19;
6704 // Setup to compare 8-char (16-byte) vectors,
6705 // start from first character again because it has aligned address.
6706 movl(result, cnt2);
6707 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
6708 jccb(Assembler::zero, COMPARE_TAIL);
6709
6710 lea(str1, Address(str1, result, scale));
6711 lea(str2, Address(str2, result, scale));
6712 negptr(result);
6713
6714 // pcmpestri
6715 // inputs:
6716 // vec1- substring
6717 // rax - negative string length (elements count)
6718 // mem - scanned string
6719 // rdx - string length (elements count)
6720 // pcmpmask - cmp mode: 11000 (string compare with negated result)
6721 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
6722 // outputs:
6723 // rcx - first mismatched element index
6724 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6725
6726 bind(COMPARE_WIDE_VECTORS);
6727 movdqu(vec1, Address(str1, result, scale));
6728 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6729 // After pcmpestri cnt1(rcx) contains mismatched element index
6730
6731 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
6732 addptr(result, stride);
6733 subptr(cnt2, stride);
6734 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6735
6736 // compare wide vectors tail
6737 testptr(result, result);
6738 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6739
6740 movl(cnt2, stride);
6741 movl(result, stride);
6742 negptr(result);
6743 movdqu(vec1, Address(str1, result, scale));
6744 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6745 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6746
6747 // Mismatched characters in the vectors
6748 bind(VECTOR_NOT_EQUAL);
6749 addptr(cnt1, result);
6750 load_unsigned_short(result, Address(str1, cnt1, scale));
6751 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6752 subl(result, cnt2);
6753 jmpb(POP_LABEL);
6754
6755 bind(COMPARE_TAIL); // limit is zero
6756 movl(cnt2, result);
6757 // Fallthru to tail compare
6758 }
6759 // Shift str2 and str1 to the end of the arrays, negate min
6760 lea(str1, Address(str1, cnt2, scale));
6761 lea(str2, Address(str2, cnt2, scale));
6762 decrementl(cnt2); // first character was compared already
6763 negptr(cnt2);
6764
6765 // Compare the rest of the elements
6766 bind(WHILE_HEAD_LABEL);
6767 load_unsigned_short(result, Address(str1, cnt2, scale, 0));
6768 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0));
6769 subl(result, cnt1);
6770 jccb(Assembler::notZero, POP_LABEL);
6771 increment(cnt2);
6772 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6773
6774 // Strings are equal up to min length. Return the length difference.
6775 bind(LENGTH_DIFF_LABEL);
6776 pop(result);
6777 jmpb(DONE_LABEL);
6778
6779 // Discard the stored length difference
6780 bind(POP_LABEL);
6781 pop(cnt1);
6782
6783 // That's it
6784 bind(DONE_LABEL);
6785 }
6786
6787 // Compare char[] arrays aligned to 4 bytes or substrings.
6788 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
6789 Register limit, Register result, Register chr,
6790 XMMRegister vec1, XMMRegister vec2) {
6791 ShortBranchVerifier sbv(this);
6792 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
6793
6794 int length_offset = arrayOopDesc::length_offset_in_bytes();
6795 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
6796
6797 // Check the input args
6798 cmpptr(ary1, ary2);
6799 jcc(Assembler::equal, TRUE_LABEL);
6800
6801 if (is_array_equ) {
6802 // Need additional checks for arrays_equals.
6803 testptr(ary1, ary1);
6804 jcc(Assembler::zero, FALSE_LABEL);
6805 testptr(ary2, ary2);
6806 jcc(Assembler::zero, FALSE_LABEL);
6807
6808 // Check the lengths
6809 movl(limit, Address(ary1, length_offset));
6810 cmpl(limit, Address(ary2, length_offset));
6811 jcc(Assembler::notEqual, FALSE_LABEL);
6812 }
6813
6814 // count == 0
6815 testl(limit, limit);
6816 jcc(Assembler::zero, TRUE_LABEL);
6817
6818 if (is_array_equ) {
6819 // Load array address
6820 lea(ary1, Address(ary1, base_offset));
6821 lea(ary2, Address(ary2, base_offset));
6822 }
6823
6824 shll(limit, 1); // byte count != 0
6825 movl(result, limit); // copy
6826
6827 if (UseAVX >= 2) {
6828 // With AVX2, use 32-byte vector compare
6829 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6830
6831 // Compare 32-byte vectors
6832 andl(result, 0x0000001e); // tail count (in bytes)
6833 andl(limit, 0xffffffe0); // vector count (in bytes)
6834 jccb(Assembler::zero, COMPARE_TAIL);
6835
6836 lea(ary1, Address(ary1, limit, Address::times_1));
6837 lea(ary2, Address(ary2, limit, Address::times_1));
6838 negptr(limit);
6839
6840 bind(COMPARE_WIDE_VECTORS);
6841 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
6842 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
6843 vpxor(vec1, vec2);
6844
6845 vptest(vec1, vec1);
6846 jccb(Assembler::notZero, FALSE_LABEL);
6847 addptr(limit, 32);
6848 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6849
6850 testl(result, result);
6851 jccb(Assembler::zero, TRUE_LABEL);
6852
6853 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6854 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
6855 vpxor(vec1, vec2);
6856
6857 vptest(vec1, vec1);
6858 jccb(Assembler::notZero, FALSE_LABEL);
6859 jmpb(TRUE_LABEL);
6860
6861 bind(COMPARE_TAIL); // limit is zero
6862 movl(limit, result);
6863 // Fallthru to tail compare
6864 } else if (UseSSE42Intrinsics) {
6865 // With SSE4.2, use double quad vector compare
6866 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6867
6868 // Compare 16-byte vectors
6869 andl(result, 0x0000000e); // tail count (in bytes)
6870 andl(limit, 0xfffffff0); // vector count (in bytes)
6871 jccb(Assembler::zero, COMPARE_TAIL);
6872
6873 lea(ary1, Address(ary1, limit, Address::times_1));
6874 lea(ary2, Address(ary2, limit, Address::times_1));
6875 negptr(limit);
6876
6877 bind(COMPARE_WIDE_VECTORS);
6878 movdqu(vec1, Address(ary1, limit, Address::times_1));
6879 movdqu(vec2, Address(ary2, limit, Address::times_1));
6880 pxor(vec1, vec2);
6881
6882 ptest(vec1, vec1);
6883 jccb(Assembler::notZero, FALSE_LABEL);
6884 addptr(limit, 16);
6885 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6886
6887 testl(result, result);
6888 jccb(Assembler::zero, TRUE_LABEL);
6889
6890 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
6891 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
6892 pxor(vec1, vec2);
6893
6894 ptest(vec1, vec1);
6895 jccb(Assembler::notZero, FALSE_LABEL);
6896 jmpb(TRUE_LABEL);
6897
6898 bind(COMPARE_TAIL); // limit is zero
6899 movl(limit, result);
6900 // Fallthru to tail compare
6901 }
6902
6903 // Compare 4-byte vectors
6904 andl(limit, 0xfffffffc); // vector count (in bytes)
6905 jccb(Assembler::zero, COMPARE_CHAR);
6906
6907 lea(ary1, Address(ary1, limit, Address::times_1));
6908 lea(ary2, Address(ary2, limit, Address::times_1));
6909 negptr(limit);
6910
6911 bind(COMPARE_VECTORS);
6912 movl(chr, Address(ary1, limit, Address::times_1));
6913 cmpl(chr, Address(ary2, limit, Address::times_1));
6914 jccb(Assembler::notEqual, FALSE_LABEL);
6915 addptr(limit, 4);
6916 jcc(Assembler::notZero, COMPARE_VECTORS);
6917
6918 // Compare trailing char (final 2 bytes), if any
6919 bind(COMPARE_CHAR);
6920 testl(result, 0x2); // tail char
6921 jccb(Assembler::zero, TRUE_LABEL);
6922 load_unsigned_short(chr, Address(ary1, 0));
6923 load_unsigned_short(limit, Address(ary2, 0));
6924 cmpl(chr, limit);
6925 jccb(Assembler::notEqual, FALSE_LABEL);
6926
6927 bind(TRUE_LABEL);
6928 movl(result, 1); // return true
6929 jmpb(DONE);
6930
6931 bind(FALSE_LABEL);
6932 xorl(result, result); // return false
6933
6934 // That's it
6935 bind(DONE);
6936 if (UseAVX >= 2) {
6937 // clean upper bits of YMM registers
6938 vzeroupper();
6939 }
6940 }
6941
6942 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6943 Register to, Register value, Register count,
6944 Register rtmp, XMMRegister xtmp) {
6945 ShortBranchVerifier sbv(this);
6946 assert_different_registers(to, value, count, rtmp);
6947 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
6948 Label L_fill_2_bytes, L_fill_4_bytes;
6949
6950 int shift = -1;
6951 switch (t) {
6952 case T_BYTE:
6953 shift = 2;
6954 break;
6955 case T_SHORT:
6956 shift = 1;
6957 break;
6958 case T_INT:
6959 shift = 0;
6960 break;
6961 default: ShouldNotReachHere();
6962 }
6963
6964 if (t == T_BYTE) {
6965 andl(value, 0xff);
6966 movl(rtmp, value);
6967 shll(rtmp, 8);
6968 orl(value, rtmp);
6969 }
6970 if (t == T_SHORT) {
6971 andl(value, 0xffff);
6972 }
6973 if (t == T_BYTE || t == T_SHORT) {
6974 movl(rtmp, value);
6975 shll(rtmp, 16);
6976 orl(value, rtmp);
6977 }
6978
6979 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
6980 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6981 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6982 // align source address at 4 bytes address boundary
6983 if (t == T_BYTE) {
6984 // One byte misalignment happens only for byte arrays
6985 testptr(to, 1);
6986 jccb(Assembler::zero, L_skip_align1);
6987 movb(Address(to, 0), value);
6988 increment(to);
6989 decrement(count);
6990 BIND(L_skip_align1);
6991 }
6992 // Two bytes misalignment happens only for byte and short (char) arrays
6993 testptr(to, 2);
6994 jccb(Assembler::zero, L_skip_align2);
6995 movw(Address(to, 0), value);
6996 addptr(to, 2);
6997 subl(count, 1<<(shift-1));
6998 BIND(L_skip_align2);
6999 }
7000 if (UseSSE < 2) {
7001 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7002 // Fill 32-byte chunks
7003 subl(count, 8 << shift);
7004 jcc(Assembler::less, L_check_fill_8_bytes);
7005 align(16);
7006
7007 BIND(L_fill_32_bytes_loop);
7008
7009 for (int i = 0; i < 32; i += 4) {
7010 movl(Address(to, i), value);
7011 }
7012
7013 addptr(to, 32);
7014 subl(count, 8 << shift);
7015 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7016 BIND(L_check_fill_8_bytes);
7017 addl(count, 8 << shift);
7018 jccb(Assembler::zero, L_exit);
7019 jmpb(L_fill_8_bytes);
7020
7021 //
7022 // length is too short, just fill qwords
7023 //
7024 BIND(L_fill_8_bytes_loop);
7025 movl(Address(to, 0), value);
7026 movl(Address(to, 4), value);
7027 addptr(to, 8);
7028 BIND(L_fill_8_bytes);
7029 subl(count, 1 << (shift + 1));
7030 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7031 // fall through to fill 4 bytes
7032 } else {
7033 Label L_fill_32_bytes;
7034 if (!UseUnalignedLoadStores) {
7035 // align to 8 bytes, we know we are 4 byte aligned to start
7036 testptr(to, 4);
7037 jccb(Assembler::zero, L_fill_32_bytes);
7038 movl(Address(to, 0), value);
7039 addptr(to, 4);
7040 subl(count, 1<<shift);
7041 }
7042 BIND(L_fill_32_bytes);
7043 {
7044 assert( UseSSE >= 2, "supported cpu only" );
7045 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7046 if (UseAVX > 2) {
7047 movl(rtmp, 0xffff);
7048 kmovql(k1, rtmp);
7049 }
7050 movdl(xtmp, value);
7051 if (UseAVX > 2 && UseUnalignedLoadStores) {
7052 // Fill 64-byte chunks
7053 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7054 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
7055
7056 subl(count, 16 << shift);
7057 jcc(Assembler::less, L_check_fill_32_bytes);
7058 align(16);
7059
7060 BIND(L_fill_64_bytes_loop);
7061 evmovdqu(Address(to, 0), xtmp, Assembler::AVX_512bit);
7062 addptr(to, 64);
7063 subl(count, 16 << shift);
7064 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7065
7066 BIND(L_check_fill_32_bytes);
7067 addl(count, 8 << shift);
7068 jccb(Assembler::less, L_check_fill_8_bytes);
7069 evmovdqu(Address(to, 0), xtmp, Assembler::AVX_256bit);
7070 addptr(to, 32);
7071 subl(count, 8 << shift);
7072
7073 BIND(L_check_fill_8_bytes);
7074 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
7075 // Fill 64-byte chunks
7076 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7077 vpbroadcastd(xtmp, xtmp);
7078
7079 subl(count, 16 << shift);
7080 jcc(Assembler::less, L_check_fill_32_bytes);
7081 align(16);
7082
7083 BIND(L_fill_64_bytes_loop);
7084 vmovdqu(Address(to, 0), xtmp);
7085 vmovdqu(Address(to, 32), xtmp);
7086 addptr(to, 64);
7087 subl(count, 16 << shift);
7088 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7089
7090 BIND(L_check_fill_32_bytes);
7091 addl(count, 8 << shift);
7092 jccb(Assembler::less, L_check_fill_8_bytes);
7093 vmovdqu(Address(to, 0), xtmp);
7094 addptr(to, 32);
7095 subl(count, 8 << shift);
7096
7097 BIND(L_check_fill_8_bytes);
7098 // clean upper bits of YMM registers
7099 vzeroupper();
7100 } else {
7101 // Fill 32-byte chunks
7102 pshufd(xtmp, xtmp, 0);
7103
7104 subl(count, 8 << shift);
7105 jcc(Assembler::less, L_check_fill_8_bytes);
7106 align(16);
7107
7108 BIND(L_fill_32_bytes_loop);
7109
7110 if (UseUnalignedLoadStores) {
7111 movdqu(Address(to, 0), xtmp);
7112 movdqu(Address(to, 16), xtmp);
7113 } else {
7114 movq(Address(to, 0), xtmp);
7115 movq(Address(to, 8), xtmp);
7116 movq(Address(to, 16), xtmp);
7117 movq(Address(to, 24), xtmp);
7118 }
7119
7120 addptr(to, 32);
7121 subl(count, 8 << shift);
7122 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7123
7124 BIND(L_check_fill_8_bytes);
7125 }
7126 addl(count, 8 << shift);
7127 jccb(Assembler::zero, L_exit);
7128 jmpb(L_fill_8_bytes);
7129
7130 //
7131 // length is too short, just fill qwords
7132 //
7133 BIND(L_fill_8_bytes_loop);
7134 movq(Address(to, 0), xtmp);
7135 addptr(to, 8);
7136 BIND(L_fill_8_bytes);
7137 subl(count, 1 << (shift + 1));
7138 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7139 }
7140 }
7141 // fill trailing 4 bytes
7142 BIND(L_fill_4_bytes);
7143 testl(count, 1<<shift);
7144 jccb(Assembler::zero, L_fill_2_bytes);
7145 movl(Address(to, 0), value);
7146 if (t == T_BYTE || t == T_SHORT) {
7147 addptr(to, 4);
7148 BIND(L_fill_2_bytes);
7149 // fill trailing 2 bytes
7150 testl(count, 1<<(shift-1));
7151 jccb(Assembler::zero, L_fill_byte);
7152 movw(Address(to, 0), value);
7153 if (t == T_BYTE) {
7154 addptr(to, 2);
7155 BIND(L_fill_byte);
7156 // fill trailing byte
7157 testl(count, 1);
7158 jccb(Assembler::zero, L_exit);
7159 movb(Address(to, 0), value);
7160 } else {
7161 BIND(L_fill_byte);
7162 }
7163 } else {
7164 BIND(L_fill_2_bytes);
7165 }
7166 BIND(L_exit);
7167 }
7168
7169 // encode char[] to byte[] in ISO_8859_1
7170 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7171 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7172 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7173 Register tmp5, Register result) {
7174 // rsi: src
7175 // rdi: dst
7176 // rdx: len
7177 // rcx: tmp5
7178 // rax: result
7179 ShortBranchVerifier sbv(this);
7180 assert_different_registers(src, dst, len, tmp5, result);
7181 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7182
7183 // set result
7184 xorl(result, result);
7185 // check for zero length
7186 testl(len, len);
7187 jcc(Assembler::zero, L_done);
7188 movl(result, len);
7189
7190 // Setup pointers
7191 lea(src, Address(src, len, Address::times_2)); // char[]
7192 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7193 negptr(len);
7194
7195 if (UseSSE42Intrinsics || UseAVX >= 2) {
7196 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
7197 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7198
7199 if (UseAVX >= 2) {
7200 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7201 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7202 movdl(tmp1Reg, tmp5);
7203 vpbroadcastd(tmp1Reg, tmp1Reg);
7204 jmpb(L_chars_32_check);
7205
7206 bind(L_copy_32_chars);
7207 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7208 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7209 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7210 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7211 jccb(Assembler::notZero, L_copy_32_chars_exit);
7212 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7213 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7214 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7215
7216 bind(L_chars_32_check);
7217 addptr(len, 32);
7218 jccb(Assembler::lessEqual, L_copy_32_chars);
7219
7220 bind(L_copy_32_chars_exit);
7221 subptr(len, 16);
7222 jccb(Assembler::greater, L_copy_16_chars_exit);
7223
7224 } else if (UseSSE42Intrinsics) {
7225 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7226 movdl(tmp1Reg, tmp5);
7227 pshufd(tmp1Reg, tmp1Reg, 0);
7228 jmpb(L_chars_16_check);
7229 }
7230
7231 bind(L_copy_16_chars);
7232 if (UseAVX >= 2) {
7233 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7234 vptest(tmp2Reg, tmp1Reg);
7235 jccb(Assembler::notZero, L_copy_16_chars_exit);
7236 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7237 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7238 } else {
7239 if (UseAVX > 0) {
7240 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7241 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7242 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7243 } else {
7244 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7245 por(tmp2Reg, tmp3Reg);
7246 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7247 por(tmp2Reg, tmp4Reg);
7248 }
7249 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7250 jccb(Assembler::notZero, L_copy_16_chars_exit);
7251 packuswb(tmp3Reg, tmp4Reg);
7252 }
7253 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7254
7255 bind(L_chars_16_check);
7256 addptr(len, 16);
7257 jccb(Assembler::lessEqual, L_copy_16_chars);
7258
7259 bind(L_copy_16_chars_exit);
7260 if (UseAVX >= 2) {
7261 // clean upper bits of YMM registers
7262 vzeroupper();
7263 }
7264 subptr(len, 8);
7265 jccb(Assembler::greater, L_copy_8_chars_exit);
7266
7267 bind(L_copy_8_chars);
7268 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7269 ptest(tmp3Reg, tmp1Reg);
7270 jccb(Assembler::notZero, L_copy_8_chars_exit);
7271 packuswb(tmp3Reg, tmp1Reg);
7272 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7273 addptr(len, 8);
7274 jccb(Assembler::lessEqual, L_copy_8_chars);
7275
7276 bind(L_copy_8_chars_exit);
7277 subptr(len, 8);
7278 jccb(Assembler::zero, L_done);
7279 }
7280
7281 bind(L_copy_1_char);
7282 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7283 testl(tmp5, 0xff00); // check if Unicode char
7284 jccb(Assembler::notZero, L_copy_1_char_exit);
7285 movb(Address(dst, len, Address::times_1, 0), tmp5);
7286 addptr(len, 1);
7287 jccb(Assembler::less, L_copy_1_char);
7288
7289 bind(L_copy_1_char_exit);
7290 addptr(result, len); // len is negative count of not processed elements
7291 bind(L_done);
7292 }
7293
7294 #ifdef _LP64
7295 /**
7296 * Helper for multiply_to_len().
7297 */
7298 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7299 addq(dest_lo, src1);
7300 adcq(dest_hi, 0);
7301 addq(dest_lo, src2);
7302 adcq(dest_hi, 0);
7303 }
7304
7305 /**
7306 * Multiply 64 bit by 64 bit first loop.
7307 */
7308 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7309 Register y, Register y_idx, Register z,
7310 Register carry, Register product,
7311 Register idx, Register kdx) {
7312 //
7313 // jlong carry, x[], y[], z[];
7314 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7315 // huge_128 product = y[idx] * x[xstart] + carry;
7316 // z[kdx] = (jlong)product;
7317 // carry = (jlong)(product >>> 64);
7318 // }
7319 // z[xstart] = carry;
7320 //
7321
7322 Label L_first_loop, L_first_loop_exit;
7323 Label L_one_x, L_one_y, L_multiply;
7324
7325 decrementl(xstart);
7326 jcc(Assembler::negative, L_one_x);
7327
7328 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7329 rorq(x_xstart, 32); // convert big-endian to little-endian
7330
7331 bind(L_first_loop);
7332 decrementl(idx);
7333 jcc(Assembler::negative, L_first_loop_exit);
7334 decrementl(idx);
7335 jcc(Assembler::negative, L_one_y);
7336 movq(y_idx, Address(y, idx, Address::times_4, 0));
7337 rorq(y_idx, 32); // convert big-endian to little-endian
7338 bind(L_multiply);
7339 movq(product, x_xstart);
7340 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7341 addq(product, carry);
7342 adcq(rdx, 0);
7343 subl(kdx, 2);
7344 movl(Address(z, kdx, Address::times_4, 4), product);
7345 shrq(product, 32);
7346 movl(Address(z, kdx, Address::times_4, 0), product);
7347 movq(carry, rdx);
7348 jmp(L_first_loop);
7349
7350 bind(L_one_y);
7351 movl(y_idx, Address(y, 0));
7352 jmp(L_multiply);
7353
7354 bind(L_one_x);
7355 movl(x_xstart, Address(x, 0));
7356 jmp(L_first_loop);
7357
7358 bind(L_first_loop_exit);
7359 }
7360
7361 /**
7362 * Multiply 64 bit by 64 bit and add 128 bit.
7363 */
7364 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7365 Register yz_idx, Register idx,
7366 Register carry, Register product, int offset) {
7367 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7368 // z[kdx] = (jlong)product;
7369
7370 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7371 rorq(yz_idx, 32); // convert big-endian to little-endian
7372 movq(product, x_xstart);
7373 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7374 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7375 rorq(yz_idx, 32); // convert big-endian to little-endian
7376
7377 add2_with_carry(rdx, product, carry, yz_idx);
7378
7379 movl(Address(z, idx, Address::times_4, offset+4), product);
7380 shrq(product, 32);
7381 movl(Address(z, idx, Address::times_4, offset), product);
7382
7383 }
7384
7385 /**
7386 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7387 */
7388 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7389 Register yz_idx, Register idx, Register jdx,
7390 Register carry, Register product,
7391 Register carry2) {
7392 // jlong carry, x[], y[], z[];
7393 // int kdx = ystart+1;
7394 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7395 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7396 // z[kdx+idx+1] = (jlong)product;
7397 // jlong carry2 = (jlong)(product >>> 64);
7398 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7399 // z[kdx+idx] = (jlong)product;
7400 // carry = (jlong)(product >>> 64);
7401 // }
7402 // idx += 2;
7403 // if (idx > 0) {
7404 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7405 // z[kdx+idx] = (jlong)product;
7406 // carry = (jlong)(product >>> 64);
7407 // }
7408 //
7409
7410 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7411
7412 movl(jdx, idx);
7413 andl(jdx, 0xFFFFFFFC);
7414 shrl(jdx, 2);
7415
7416 bind(L_third_loop);
7417 subl(jdx, 1);
7418 jcc(Assembler::negative, L_third_loop_exit);
7419 subl(idx, 4);
7420
7421 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7422 movq(carry2, rdx);
7423
7424 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7425 movq(carry, rdx);
7426 jmp(L_third_loop);
7427
7428 bind (L_third_loop_exit);
7429
7430 andl (idx, 0x3);
7431 jcc(Assembler::zero, L_post_third_loop_done);
7432
7433 Label L_check_1;
7434 subl(idx, 2);
7435 jcc(Assembler::negative, L_check_1);
7436
7437 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7438 movq(carry, rdx);
7439
7440 bind (L_check_1);
7441 addl (idx, 0x2);
7442 andl (idx, 0x1);
7443 subl(idx, 1);
7444 jcc(Assembler::negative, L_post_third_loop_done);
7445
7446 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7447 movq(product, x_xstart);
7448 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7449 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7450
7451 add2_with_carry(rdx, product, yz_idx, carry);
7452
7453 movl(Address(z, idx, Address::times_4, 0), product);
7454 shrq(product, 32);
7455
7456 shlq(rdx, 32);
7457 orq(product, rdx);
7458 movq(carry, product);
7459
7460 bind(L_post_third_loop_done);
7461 }
7462
7463 /**
7464 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7465 *
7466 */
7467 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7468 Register carry, Register carry2,
7469 Register idx, Register jdx,
7470 Register yz_idx1, Register yz_idx2,
7471 Register tmp, Register tmp3, Register tmp4) {
7472 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7473
7474 // jlong carry, x[], y[], z[];
7475 // int kdx = ystart+1;
7476 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7477 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7478 // jlong carry2 = (jlong)(tmp3 >>> 64);
7479 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7480 // carry = (jlong)(tmp4 >>> 64);
7481 // z[kdx+idx+1] = (jlong)tmp3;
7482 // z[kdx+idx] = (jlong)tmp4;
7483 // }
7484 // idx += 2;
7485 // if (idx > 0) {
7486 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7487 // z[kdx+idx] = (jlong)yz_idx1;
7488 // carry = (jlong)(yz_idx1 >>> 64);
7489 // }
7490 //
7491
7492 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7493
7494 movl(jdx, idx);
7495 andl(jdx, 0xFFFFFFFC);
7496 shrl(jdx, 2);
7497
7498 bind(L_third_loop);
7499 subl(jdx, 1);
7500 jcc(Assembler::negative, L_third_loop_exit);
7501 subl(idx, 4);
7502
7503 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7504 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7505 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7506 rorxq(yz_idx2, yz_idx2, 32);
7507
7508 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7509 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7510
7511 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7512 rorxq(yz_idx1, yz_idx1, 32);
7513 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7514 rorxq(yz_idx2, yz_idx2, 32);
7515
7516 if (VM_Version::supports_adx()) {
7517 adcxq(tmp3, carry);
7518 adoxq(tmp3, yz_idx1);
7519
7520 adcxq(tmp4, tmp);
7521 adoxq(tmp4, yz_idx2);
7522
7523 movl(carry, 0); // does not affect flags
7524 adcxq(carry2, carry);
7525 adoxq(carry2, carry);
7526 } else {
7527 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7528 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7529 }
7530 movq(carry, carry2);
7531
7532 movl(Address(z, idx, Address::times_4, 12), tmp3);
7533 shrq(tmp3, 32);
7534 movl(Address(z, idx, Address::times_4, 8), tmp3);
7535
7536 movl(Address(z, idx, Address::times_4, 4), tmp4);
7537 shrq(tmp4, 32);
7538 movl(Address(z, idx, Address::times_4, 0), tmp4);
7539
7540 jmp(L_third_loop);
7541
7542 bind (L_third_loop_exit);
7543
7544 andl (idx, 0x3);
7545 jcc(Assembler::zero, L_post_third_loop_done);
7546
7547 Label L_check_1;
7548 subl(idx, 2);
7549 jcc(Assembler::negative, L_check_1);
7550
7551 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7552 rorxq(yz_idx1, yz_idx1, 32);
7553 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7554 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7555 rorxq(yz_idx2, yz_idx2, 32);
7556
7557 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7558
7559 movl(Address(z, idx, Address::times_4, 4), tmp3);
7560 shrq(tmp3, 32);
7561 movl(Address(z, idx, Address::times_4, 0), tmp3);
7562 movq(carry, tmp4);
7563
7564 bind (L_check_1);
7565 addl (idx, 0x2);
7566 andl (idx, 0x1);
7567 subl(idx, 1);
7568 jcc(Assembler::negative, L_post_third_loop_done);
7569 movl(tmp4, Address(y, idx, Address::times_4, 0));
7570 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7571 movl(tmp4, Address(z, idx, Address::times_4, 0));
7572
7573 add2_with_carry(carry2, tmp3, tmp4, carry);
7574
7575 movl(Address(z, idx, Address::times_4, 0), tmp3);
7576 shrq(tmp3, 32);
7577
7578 shlq(carry2, 32);
7579 orq(tmp3, carry2);
7580 movq(carry, tmp3);
7581
7582 bind(L_post_third_loop_done);
7583 }
7584
7585 /**
7586 * Code for BigInteger::multiplyToLen() instrinsic.
7587 *
7588 * rdi: x
7589 * rax: xlen
7590 * rsi: y
7591 * rcx: ylen
7592 * r8: z
7593 * r11: zlen
7594 * r12: tmp1
7595 * r13: tmp2
7596 * r14: tmp3
7597 * r15: tmp4
7598 * rbx: tmp5
7599 *
7600 */
7601 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
7602 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7603 ShortBranchVerifier sbv(this);
7604 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7605
7606 push(tmp1);
7607 push(tmp2);
7608 push(tmp3);
7609 push(tmp4);
7610 push(tmp5);
7611
7612 push(xlen);
7613 push(zlen);
7614
7615 const Register idx = tmp1;
7616 const Register kdx = tmp2;
7617 const Register xstart = tmp3;
7618
7619 const Register y_idx = tmp4;
7620 const Register carry = tmp5;
7621 const Register product = xlen;
7622 const Register x_xstart = zlen; // reuse register
7623
7624 // First Loop.
7625 //
7626 // final static long LONG_MASK = 0xffffffffL;
7627 // int xstart = xlen - 1;
7628 // int ystart = ylen - 1;
7629 // long carry = 0;
7630 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7631 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7632 // z[kdx] = (int)product;
7633 // carry = product >>> 32;
7634 // }
7635 // z[xstart] = (int)carry;
7636 //
7637
7638 movl(idx, ylen); // idx = ylen;
7639 movl(kdx, zlen); // kdx = xlen+ylen;
7640 xorq(carry, carry); // carry = 0;
7641
7642 Label L_done;
7643
7644 movl(xstart, xlen);
7645 decrementl(xstart);
7646 jcc(Assembler::negative, L_done);
7647
7648 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7649
7650 Label L_second_loop;
7651 testl(kdx, kdx);
7652 jcc(Assembler::zero, L_second_loop);
7653
7654 Label L_carry;
7655 subl(kdx, 1);
7656 jcc(Assembler::zero, L_carry);
7657
7658 movl(Address(z, kdx, Address::times_4, 0), carry);
7659 shrq(carry, 32);
7660 subl(kdx, 1);
7661
7662 bind(L_carry);
7663 movl(Address(z, kdx, Address::times_4, 0), carry);
7664
7665 // Second and third (nested) loops.
7666 //
7667 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7668 // carry = 0;
7669 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7670 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7671 // (z[k] & LONG_MASK) + carry;
7672 // z[k] = (int)product;
7673 // carry = product >>> 32;
7674 // }
7675 // z[i] = (int)carry;
7676 // }
7677 //
7678 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7679
7680 const Register jdx = tmp1;
7681
7682 bind(L_second_loop);
7683 xorl(carry, carry); // carry = 0;
7684 movl(jdx, ylen); // j = ystart+1
7685
7686 subl(xstart, 1); // i = xstart-1;
7687 jcc(Assembler::negative, L_done);
7688
7689 push (z);
7690
7691 Label L_last_x;
7692 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7693 subl(xstart, 1); // i = xstart-1;
7694 jcc(Assembler::negative, L_last_x);
7695
7696 if (UseBMI2Instructions) {
7697 movq(rdx, Address(x, xstart, Address::times_4, 0));
7698 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7699 } else {
7700 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7701 rorq(x_xstart, 32); // convert big-endian to little-endian
7702 }
7703
7704 Label L_third_loop_prologue;
7705 bind(L_third_loop_prologue);
7706
7707 push (x);
7708 push (xstart);
7709 push (ylen);
7710
7711
7712 if (UseBMI2Instructions) {
7713 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7714 } else { // !UseBMI2Instructions
7715 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7716 }
7717
7718 pop(ylen);
7719 pop(xlen);
7720 pop(x);
7721 pop(z);
7722
7723 movl(tmp3, xlen);
7724 addl(tmp3, 1);
7725 movl(Address(z, tmp3, Address::times_4, 0), carry);
7726 subl(tmp3, 1);
7727 jccb(Assembler::negative, L_done);
7728
7729 shrq(carry, 32);
7730 movl(Address(z, tmp3, Address::times_4, 0), carry);
7731 jmp(L_second_loop);
7732
7733 // Next infrequent code is moved outside loops.
7734 bind(L_last_x);
7735 if (UseBMI2Instructions) {
7736 movl(rdx, Address(x, 0));
7737 } else {
7738 movl(x_xstart, Address(x, 0));
7739 }
7740 jmp(L_third_loop_prologue);
7741
7742 bind(L_done);
7743
7744 pop(zlen);
7745 pop(xlen);
7746
7747 pop(tmp5);
7748 pop(tmp4);
7749 pop(tmp3);
7750 pop(tmp2);
7751 pop(tmp1);
7752 }
7753 #endif
7754
7755 /**
7756 * Emits code to update CRC-32 with a byte value according to constants in table
7757 *
7758 * @param [in,out]crc Register containing the crc.
7759 * @param [in]val Register containing the byte to fold into the CRC.
7760 * @param [in]table Register containing the table of crc constants.
7761 *
7762 * uint32_t crc;
7763 * val = crc_table[(val ^ crc) & 0xFF];
7764 * crc = val ^ (crc >> 8);
7765 *
7766 */
7767 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
7768 xorl(val, crc);
7769 andl(val, 0xFF);
7770 shrl(crc, 8); // unsigned shift
7771 xorl(crc, Address(table, val, Address::times_4, 0));
7772 }
7773
7774 /**
7775 * Fold 128-bit data chunk
7776 */
7777 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
7778 if (UseAVX > 0) {
7779 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
7780 vpclmulldq(xcrc, xK, xcrc); // [63:0]
7781 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
7782 pxor(xcrc, xtmp);
7783 } else {
7784 movdqa(xtmp, xcrc);
7785 pclmulhdq(xtmp, xK); // [123:64]
7786 pclmulldq(xcrc, xK); // [63:0]
7787 pxor(xcrc, xtmp);
7788 movdqu(xtmp, Address(buf, offset));
7789 pxor(xcrc, xtmp);
7790 }
7791 }
7792
7793 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
7794 if (UseAVX > 0) {
7795 vpclmulhdq(xtmp, xK, xcrc);
7796 vpclmulldq(xcrc, xK, xcrc);
7797 pxor(xcrc, xbuf);
7798 pxor(xcrc, xtmp);
7799 } else {
7800 movdqa(xtmp, xcrc);
7801 pclmulhdq(xtmp, xK);
7802 pclmulldq(xcrc, xK);
7803 pxor(xcrc, xbuf);
7804 pxor(xcrc, xtmp);
7805 }
7806 }
7807
7808 /**
7809 * 8-bit folds to compute 32-bit CRC
7810 *
7811 * uint64_t xcrc;
7812 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
7813 */
7814 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
7815 movdl(tmp, xcrc);
7816 andl(tmp, 0xFF);
7817 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
7818 psrldq(xcrc, 1); // unsigned shift one byte
7819 pxor(xcrc, xtmp);
7820 }
7821
7822 /**
7823 * uint32_t crc;
7824 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
7825 */
7826 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
7827 movl(tmp, crc);
7828 andl(tmp, 0xFF);
7829 shrl(crc, 8);
7830 xorl(crc, Address(table, tmp, Address::times_4, 0));
7831 }
7832
7833 /**
7834 * @param crc register containing existing CRC (32-bit)
7835 * @param buf register pointing to input byte buffer (byte*)
7836 * @param len register containing number of bytes
7837 * @param table register that will contain address of CRC table
7838 * @param tmp scratch register
7839 */
7840 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
7841 assert_different_registers(crc, buf, len, table, tmp, rax);
7842
7843 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7844 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7845
7846 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
7847 notl(crc); // ~crc
7848 cmpl(len, 16);
7849 jcc(Assembler::less, L_tail);
7850
7851 // Align buffer to 16 bytes
7852 movl(tmp, buf);
7853 andl(tmp, 0xF);
7854 jccb(Assembler::zero, L_aligned);
7855 subl(tmp, 16);
7856 addl(len, tmp);
7857
7858 align(4);
7859 BIND(L_align_loop);
7860 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7861 update_byte_crc32(crc, rax, table);
7862 increment(buf);
7863 incrementl(tmp);
7864 jccb(Assembler::less, L_align_loop);
7865
7866 BIND(L_aligned);
7867 movl(tmp, len); // save
7868 shrl(len, 4);
7869 jcc(Assembler::zero, L_tail_restore);
7870
7871 // Fold crc into first bytes of vector
7872 movdqa(xmm1, Address(buf, 0));
7873 movdl(rax, xmm1);
7874 xorl(crc, rax);
7875 pinsrd(xmm1, crc, 0);
7876 addptr(buf, 16);
7877 subl(len, 4); // len > 0
7878 jcc(Assembler::less, L_fold_tail);
7879
7880 movdqa(xmm2, Address(buf, 0));
7881 movdqa(xmm3, Address(buf, 16));
7882 movdqa(xmm4, Address(buf, 32));
7883 addptr(buf, 48);
7884 subl(len, 3);
7885 jcc(Assembler::lessEqual, L_fold_512b);
7886
7887 // Fold total 512 bits of polynomial on each iteration,
7888 // 128 bits per each of 4 parallel streams.
7889 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
7890
7891 align(32);
7892 BIND(L_fold_512b_loop);
7893 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
7894 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
7895 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
7896 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
7897 addptr(buf, 64);
7898 subl(len, 4);
7899 jcc(Assembler::greater, L_fold_512b_loop);
7900
7901 // Fold 512 bits to 128 bits.
7902 BIND(L_fold_512b);
7903 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7904 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
7905 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
7906 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
7907
7908 // Fold the rest of 128 bits data chunks
7909 BIND(L_fold_tail);
7910 addl(len, 3);
7911 jccb(Assembler::lessEqual, L_fold_128b);
7912 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7913
7914 BIND(L_fold_tail_loop);
7915 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
7916 addptr(buf, 16);
7917 decrementl(len);
7918 jccb(Assembler::greater, L_fold_tail_loop);
7919
7920 // Fold 128 bits in xmm1 down into 32 bits in crc register.
7921 BIND(L_fold_128b);
7922 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
7923 if (UseAVX > 0) {
7924 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
7925 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
7926 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
7927 } else {
7928 movdqa(xmm2, xmm0);
7929 pclmulqdq(xmm2, xmm1, 0x1);
7930 movdqa(xmm3, xmm0);
7931 pand(xmm3, xmm2);
7932 pclmulqdq(xmm0, xmm3, 0x1);
7933 }
7934 psrldq(xmm1, 8);
7935 psrldq(xmm2, 4);
7936 pxor(xmm0, xmm1);
7937 pxor(xmm0, xmm2);
7938
7939 // 8 8-bit folds to compute 32-bit CRC.
7940 for (int j = 0; j < 4; j++) {
7941 fold_8bit_crc32(xmm0, table, xmm1, rax);
7942 }
7943 movdl(crc, xmm0); // mov 32 bits to general register
7944 for (int j = 0; j < 4; j++) {
7945 fold_8bit_crc32(crc, table, rax);
7946 }
7947
7948 BIND(L_tail_restore);
7949 movl(len, tmp); // restore
7950 BIND(L_tail);
7951 andl(len, 0xf);
7952 jccb(Assembler::zero, L_exit);
7953
7954 // Fold the rest of bytes
7955 align(4);
7956 BIND(L_tail_loop);
7957 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7958 update_byte_crc32(crc, rax, table);
7959 increment(buf);
7960 decrementl(len);
7961 jccb(Assembler::greater, L_tail_loop);
7962
7963 BIND(L_exit);
7964 notl(crc); // ~c
7965 }
7966
7967 #undef BIND
7968 #undef BLOCK_COMMENT
7969
7970
7971 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
7972 switch (cond) {
7973 // Note some conditions are synonyms for others
7974 case Assembler::zero: return Assembler::notZero;
7975 case Assembler::notZero: return Assembler::zero;
7976 case Assembler::less: return Assembler::greaterEqual;
7977 case Assembler::lessEqual: return Assembler::greater;
7978 case Assembler::greater: return Assembler::lessEqual;
7979 case Assembler::greaterEqual: return Assembler::less;
7980 case Assembler::below: return Assembler::aboveEqual;
7981 case Assembler::belowEqual: return Assembler::above;
7982 case Assembler::above: return Assembler::belowEqual;
7983 case Assembler::aboveEqual: return Assembler::below;
7984 case Assembler::overflow: return Assembler::noOverflow;
7985 case Assembler::noOverflow: return Assembler::overflow;
7986 case Assembler::negative: return Assembler::positive;
7987 case Assembler::positive: return Assembler::negative;
7988 case Assembler::parity: return Assembler::noParity;
7989 case Assembler::noParity: return Assembler::parity;
7990 }
7991 ShouldNotReachHere(); return Assembler::overflow;
7992 }
7993
7994 SkipIfEqual::SkipIfEqual(
7995 MacroAssembler* masm, const bool* flag_addr, bool value) {
7996 _masm = masm;
7997 _masm->cmp8(ExternalAddress((address)flag_addr), value);
7998 _masm->jcc(Assembler::equal, _label);
7999 }
8000
8001 SkipIfEqual::~SkipIfEqual() {
8002 _masm->bind(_label);
8003 }