< prev index next >
src/cpu/x86/vm/vm_version_x86.hpp
Print this page
*** 207,237 ****
: 2,
bmi2 : 1,
erms : 1,
: 1,
rtm : 1,
! : 7,
adx : 1,
! : 12;
} bits;
};
union XemXcr0Eax {
uint32_t value;
struct {
uint32_t x87 : 1,
sse : 1,
ymm : 1,
! : 29;
} bits;
};
protected:
static int _cpu;
static int _model;
static int _stepping;
! static int _cpuFeatures; // features returned by the "cpuid" instruction
// 0 if this instruction is not available
static const char* _features_str;
static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
--- 207,250 ----
: 2,
bmi2 : 1,
erms : 1,
: 1,
rtm : 1,
! : 4,
! avx512f : 1,
! avx512dq : 1,
! : 1,
adx : 1,
! : 6,
! avx512pf : 1,
! avx512er : 1,
! avx512cd : 1,
! : 1,
! avx512bw : 1,
! avx512vl : 1;
} bits;
};
union XemXcr0Eax {
uint32_t value;
struct {
uint32_t x87 : 1,
sse : 1,
ymm : 1,
! : 2,
! opmask : 1,
! zmm512 : 1,
! zmm32 : 1,
! : 24;
} bits;
};
protected:
static int _cpu;
static int _model;
static int _stepping;
! static uint64_t _cpuFeatures; // features returned by the "cpuid" instruction
// 0 if this instruction is not available
static const char* _features_str;
static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
*** 261,273 ****
CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions
CPU_CLMUL = (1 << 21), // carryless multiply for CRC
CPU_BMI1 = (1 << 22),
CPU_BMI2 = (1 << 23),
CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
! CPU_ADX = (1 << 25)
} cpuFeatureFlags;
enum {
// AMD
CPU_FAMILY_AMD_11H = 0x11,
// Intel
CPU_FAMILY_INTEL_CORE = 6,
--- 274,294 ----
CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions
CPU_CLMUL = (1 << 21), // carryless multiply for CRC
CPU_BMI1 = (1 << 22),
CPU_BMI2 = (1 << 23),
CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
! CPU_ADX = (1 << 25),
! CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions
! CPU_AVX512DQ = (1 << 27),
! CPU_AVX512PF = (1 << 28),
! CPU_AVX512ER = (1 << 29),
! CPU_AVX512CD = (1 << 30),
! CPU_AVX512BW = (1 << 31)
} cpuFeatureFlags;
+ #define CPU_AVX512VL 0x100000000 // EVEX instructions with smaller vector length : enums are limited to 32bit
+
enum {
// AMD
CPU_FAMILY_AMD_11H = 0x11,
// Intel
CPU_FAMILY_INTEL_CORE = 6,
*** 280,290 ****
CPU_MODEL_SANDYBRIDGE = 0x2a,
CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
CPU_MODEL_IVYBRIDGE_EP = 0x3a,
CPU_MODEL_HASWELL_E3 = 0x3c,
CPU_MODEL_HASWELL_E7 = 0x3f,
! CPU_MODEL_BROADWELL = 0x3d
} cpuExtendedFamily;
// cpuid information block. All info derived from executing cpuid with
// various function numbers is stored here. Intel and AMD info is
// merged in this block: accessor methods disentangle it.
--- 301,312 ----
CPU_MODEL_SANDYBRIDGE = 0x2a,
CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
CPU_MODEL_IVYBRIDGE_EP = 0x3a,
CPU_MODEL_HASWELL_E3 = 0x3c,
CPU_MODEL_HASWELL_E7 = 0x3f,
! CPU_MODEL_BROADWELL = 0x3d,
! CPU_MODEL_SKYLAKE = CPU_MODEL_HASWELL_E3
} cpuExtendedFamily;
// cpuid information block. All info derived from executing cpuid with
// various function numbers is stored here. Intel and AMD info is
// merged in this block: accessor methods disentangle it.
*** 402,413 ****
static uint logical_processor_count() {
uint result = threads_per_core();
return result;
}
! static uint32_t feature_flags() {
! uint32_t result = 0;
if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
result |= CPU_CX8;
if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
result |= CPU_CMOV;
if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
--- 424,435 ----
static uint logical_processor_count() {
uint result = threads_per_core();
return result;
}
! static uint64_t feature_flags() {
! uint64_t result = 0;
if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
result |= CPU_CX8;
if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
result |= CPU_CMOV;
if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
*** 438,447 ****
--- 460,487 ----
_cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
_cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
result |= CPU_AVX;
if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
result |= CPU_AVX2;
+ if (_cpuid_info.sef_cpuid7_ebx.bits.avx512f != 0 &&
+ _cpuid_info.xem_xcr0_eax.bits.opmask != 0 &&
+ _cpuid_info.xem_xcr0_eax.bits.zmm512 != 0 &&
+ _cpuid_info.xem_xcr0_eax.bits.zmm32 != 0) {
+ result |= CPU_AVX512F;
+ if (_cpuid_info.sef_cpuid7_ebx.bits.avx512cd != 0)
+ result |= CPU_AVX512CD;
+ if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0)
+ result |= CPU_AVX512DQ;
+ if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0)
+ result |= CPU_AVX512PF;
+ if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0)
+ result |= CPU_AVX512ER;
+ if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0)
+ result |= CPU_AVX512BW;
+ if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0)
+ result |= CPU_AVX512VL;
+ }
}
if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
result |= CPU_BMI1;
if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
result |= CPU_TSC;
*** 635,644 ****
--- 675,691 ----
static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; }
static bool supports_rtm() { return (_cpuFeatures & CPU_RTM) != 0; }
static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; }
static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; }
static bool supports_adx() { return (_cpuFeatures & CPU_ADX) != 0; }
+ static bool supports_evex() { return (_cpuFeatures & CPU_AVX512F) != 0; }
+ static bool supports_avx512dq() { return (_cpuFeatures & CPU_AVX512DQ) != 0; }
+ static bool supports_avx512pf() { return (_cpuFeatures & CPU_AVX512PF) != 0; }
+ static bool supports_avx512er() { return (_cpuFeatures & CPU_AVX512ER) != 0; }
+ static bool supports_avx512cd() { return (_cpuFeatures & CPU_AVX512CD) != 0; }
+ static bool supports_avx512bw() { return (_cpuFeatures & CPU_AVX512BW) != 0; }
+ static bool supports_avx512vl() { return (_cpuFeatures & CPU_AVX512VL) != 0; }
// Intel features
static bool is_intel_family_core() { return is_intel() &&
extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
static bool is_intel_tsc_synched_at_init() {
< prev index next >