1 /*
2 * Copyright (c) 2005, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_CFGPrinter.hpp"
27 #include "c1/c1_CodeStubs.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_FrameMap.hpp"
30 #include "c1/c1_IR.hpp"
31 #include "c1/c1_LIRGenerator.hpp"
32 #include "c1/c1_LinearScan.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "code/vmreg.inline.hpp"
35 #include "utilities/bitMap.inline.hpp"
36
37 #ifndef PRODUCT
38
39 static LinearScanStatistic _stat_before_alloc;
40 static LinearScanStatistic _stat_after_asign;
41 static LinearScanStatistic _stat_final;
42
43 static LinearScanTimers _total_timer;
44
45 // helper macro for short definition of timer
46 #define TIME_LINEAR_SCAN(timer_name) TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
47
48 // helper macro for short definition of trace-output inside code
49 #define TRACE_LINEAR_SCAN(level, code) \
50 if (TraceLinearScanLevel >= level) { \
51 code; \
52 }
53
54 #else
55
56 #define TIME_LINEAR_SCAN(timer_name)
57 #define TRACE_LINEAR_SCAN(level, code)
58
59 #endif
60
61 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
62 #ifdef _LP64
63 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2, 1, 2, 1, -1};
64 #else
65 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, -1};
66 #endif
67
68
69 // Implementation of LinearScan
70
71 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
72 : _compilation(ir->compilation())
73 , _ir(ir)
74 , _gen(gen)
75 , _frame_map(frame_map)
76 , _num_virtual_regs(gen->max_virtual_register_number())
77 , _has_fpu_registers(false)
78 , _num_calls(-1)
79 , _max_spills(0)
80 , _unused_spill_slot(-1)
81 , _intervals(0) // initialized later with correct length
82 , _new_intervals_from_allocation(new IntervalList())
83 , _sorted_intervals(NULL)
84 , _needs_full_resort(false)
85 , _lir_ops(0) // initialized later with correct length
86 , _block_of_op(0) // initialized later with correct length
87 , _has_info(0)
88 , _has_call(0)
89 , _scope_value_cache(0) // initialized later with correct length
90 , _interval_in_loop(0, 0) // initialized later with correct length
91 , _cached_blocks(*ir->linear_scan_order())
92 #ifdef X86
93 , _fpu_stack_allocator(NULL)
94 #endif
95 {
96 assert(this->ir() != NULL, "check if valid");
97 assert(this->compilation() != NULL, "check if valid");
98 assert(this->gen() != NULL, "check if valid");
99 assert(this->frame_map() != NULL, "check if valid");
100 }
101
102
103 // ********** functions for converting LIR-Operands to register numbers
104 //
105 // Emulate a flat register file comprising physical integer registers,
106 // physical floating-point registers and virtual registers, in that order.
107 // Virtual registers already have appropriate numbers, since V0 is
108 // the number of physical registers.
109 // Returns -1 for hi word if opr is a single word operand.
110 //
111 // Note: the inverse operation (calculating an operand for register numbers)
112 // is done in calc_operand_for_interval()
113
114 int LinearScan::reg_num(LIR_Opr opr) {
115 assert(opr->is_register(), "should not call this otherwise");
116
117 if (opr->is_virtual_register()) {
118 assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
119 return opr->vreg_number();
120 } else if (opr->is_single_cpu()) {
121 return opr->cpu_regnr();
122 } else if (opr->is_double_cpu()) {
123 return opr->cpu_regnrLo();
124 #ifdef X86
125 } else if (opr->is_single_xmm()) {
126 return opr->fpu_regnr() + pd_first_xmm_reg;
127 } else if (opr->is_double_xmm()) {
128 return opr->fpu_regnrLo() + pd_first_xmm_reg;
129 #endif
130 } else if (opr->is_single_fpu()) {
131 return opr->fpu_regnr() + pd_first_fpu_reg;
132 } else if (opr->is_double_fpu()) {
133 return opr->fpu_regnrLo() + pd_first_fpu_reg;
134 } else {
135 ShouldNotReachHere();
136 return -1;
137 }
138 }
139
140 int LinearScan::reg_numHi(LIR_Opr opr) {
141 assert(opr->is_register(), "should not call this otherwise");
142
143 if (opr->is_virtual_register()) {
144 return -1;
145 } else if (opr->is_single_cpu()) {
146 return -1;
147 } else if (opr->is_double_cpu()) {
148 return opr->cpu_regnrHi();
149 #ifdef X86
150 } else if (opr->is_single_xmm()) {
151 return -1;
152 } else if (opr->is_double_xmm()) {
153 return -1;
154 #endif
155 } else if (opr->is_single_fpu()) {
156 return -1;
157 } else if (opr->is_double_fpu()) {
158 return opr->fpu_regnrHi() + pd_first_fpu_reg;
159 } else {
160 ShouldNotReachHere();
161 return -1;
162 }
163 }
164
165
166 // ********** functions for classification of intervals
167
168 bool LinearScan::is_precolored_interval(const Interval* i) {
169 return i->reg_num() < LinearScan::nof_regs;
170 }
171
172 bool LinearScan::is_virtual_interval(const Interval* i) {
173 return i->reg_num() >= LIR_OprDesc::vreg_base;
174 }
175
176 bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
177 return i->reg_num() < LinearScan::nof_cpu_regs;
178 }
179
180 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
181 #if defined(__SOFTFP__) || defined(E500V2)
182 return i->reg_num() >= LIR_OprDesc::vreg_base;
183 #else
184 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
185 #endif // __SOFTFP__ or E500V2
186 }
187
188 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
189 return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
190 }
191
192 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
193 #if defined(__SOFTFP__) || defined(E500V2)
194 return false;
195 #else
196 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
197 #endif // __SOFTFP__ or E500V2
198 }
199
200 bool LinearScan::is_in_fpu_register(const Interval* i) {
201 // fixed intervals not needed for FPU stack allocation
202 return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
203 }
204
205 bool LinearScan::is_oop_interval(const Interval* i) {
206 // fixed intervals never contain oops
207 return i->reg_num() >= nof_regs && i->type() == T_OBJECT;
208 }
209
210
211 // ********** General helper functions
212
213 // compute next unused stack index that can be used for spilling
214 int LinearScan::allocate_spill_slot(bool double_word) {
215 int spill_slot;
216 if (double_word) {
217 if ((_max_spills & 1) == 1) {
218 // alignment of double-word values
219 // the hole because of the alignment is filled with the next single-word value
220 assert(_unused_spill_slot == -1, "wasting a spill slot");
221 _unused_spill_slot = _max_spills;
222 _max_spills++;
223 }
224 spill_slot = _max_spills;
225 _max_spills += 2;
226
227 } else if (_unused_spill_slot != -1) {
228 // re-use hole that was the result of a previous double-word alignment
229 spill_slot = _unused_spill_slot;
230 _unused_spill_slot = -1;
231
232 } else {
233 spill_slot = _max_spills;
234 _max_spills++;
235 }
236
237 int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount();
238
239 // the class OopMapValue uses only 11 bits for storing the name of the
240 // oop location. So a stack slot bigger than 2^11 leads to an overflow
241 // that is not reported in product builds. Prevent this by checking the
242 // spill slot here (altough this value and the later used location name
243 // are slightly different)
244 if (result > 2000) {
245 bailout("too many stack slots used");
246 }
247
248 return result;
249 }
250
251 void LinearScan::assign_spill_slot(Interval* it) {
252 // assign the canonical spill slot of the parent (if a part of the interval
253 // is already spilled) or allocate a new spill slot
254 if (it->canonical_spill_slot() >= 0) {
255 it->assign_reg(it->canonical_spill_slot());
256 } else {
257 int spill = allocate_spill_slot(type2spill_size[it->type()] == 2);
258 it->set_canonical_spill_slot(spill);
259 it->assign_reg(spill);
260 }
261 }
262
263 void LinearScan::propagate_spill_slots() {
264 if (!frame_map()->finalize_frame(max_spills())) {
265 bailout("frame too large");
266 }
267 }
268
269 // create a new interval with a predefined reg_num
270 // (only used for parent intervals that are created during the building phase)
271 Interval* LinearScan::create_interval(int reg_num) {
272 assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval");
273
274 Interval* interval = new Interval(reg_num);
275 _intervals.at_put(reg_num, interval);
276
277 // assign register number for precolored intervals
278 if (reg_num < LIR_OprDesc::vreg_base) {
279 interval->assign_reg(reg_num);
280 }
281 return interval;
282 }
283
284 // assign a new reg_num to the interval and append it to the list of intervals
285 // (only used for child intervals that are created during register allocation)
286 void LinearScan::append_interval(Interval* it) {
287 it->set_reg_num(_intervals.length());
288 _intervals.append(it);
289 _new_intervals_from_allocation->append(it);
290 }
291
292 // copy the vreg-flags if an interval is split
293 void LinearScan::copy_register_flags(Interval* from, Interval* to) {
294 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) {
295 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg);
296 }
297 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) {
298 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved);
299 }
300
301 // Note: do not copy the must_start_in_memory flag because it is not necessary for child
302 // intervals (only the very beginning of the interval must be in memory)
303 }
304
305
306 // ********** spill move optimization
307 // eliminate moves from register to stack if stack slot is known to be correct
308
309 // called during building of intervals
310 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) {
311 assert(interval->is_split_parent(), "can only be called for split parents");
312
313 switch (interval->spill_state()) {
314 case noDefinitionFound:
315 assert(interval->spill_definition_pos() == -1, "must no be set before");
316 interval->set_spill_definition_pos(def_pos);
317 interval->set_spill_state(oneDefinitionFound);
318 break;
319
320 case oneDefinitionFound:
321 assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
322 if (def_pos < interval->spill_definition_pos() - 2) {
323 // second definition found, so no spill optimization possible for this interval
324 interval->set_spill_state(noOptimization);
325 } else {
326 // two consecutive definitions (because of two-operand LIR form)
327 assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
328 }
329 break;
330
331 case noOptimization:
332 // nothing to do
333 break;
334
335 default:
336 assert(false, "other states not allowed at this time");
337 }
338 }
339
340 // called during register allocation
341 void LinearScan::change_spill_state(Interval* interval, int spill_pos) {
342 switch (interval->spill_state()) {
343 case oneDefinitionFound: {
344 int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth();
345 int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth();
346
347 if (def_loop_depth < spill_loop_depth) {
348 // the loop depth of the spilling position is higher then the loop depth
349 // at the definition of the interval -> move write to memory out of loop
350 // by storing at definitin of the interval
351 interval->set_spill_state(storeAtDefinition);
352 } else {
353 // the interval is currently spilled only once, so for now there is no
354 // reason to store the interval at the definition
355 interval->set_spill_state(oneMoveInserted);
356 }
357 break;
358 }
359
360 case oneMoveInserted: {
361 // the interval is spilled more then once, so it is better to store it to
362 // memory at the definition
363 interval->set_spill_state(storeAtDefinition);
364 break;
365 }
366
367 case storeAtDefinition:
368 case startInMemory:
369 case noOptimization:
370 case noDefinitionFound:
371 // nothing to do
372 break;
373
374 default:
375 assert(false, "other states not allowed at this time");
376 }
377 }
378
379
380 bool LinearScan::must_store_at_definition(const Interval* i) {
381 return i->is_split_parent() && i->spill_state() == storeAtDefinition;
382 }
383
384 // called once before asignment of register numbers
385 void LinearScan::eliminate_spill_moves() {
386 TIME_LINEAR_SCAN(timer_eliminate_spill_moves);
387 TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves"));
388
389 // collect all intervals that must be stored after their definion.
390 // the list is sorted by Interval::spill_definition_pos
391 Interval* interval;
392 Interval* temp_list;
393 create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL);
394
395 #ifdef ASSERT
396 Interval* prev = NULL;
397 Interval* temp = interval;
398 while (temp != Interval::end()) {
399 assert(temp->spill_definition_pos() > 0, "invalid spill definition pos");
400 if (prev != NULL) {
401 assert(temp->from() >= prev->from(), "intervals not sorted");
402 assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
403 }
404
405 assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
406 assert(temp->spill_definition_pos() >= temp->from(), "invalid order");
407 assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
408
409 TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
410
411 temp = temp->next();
412 }
413 #endif
414
415 LIR_InsertionBuffer insertion_buffer;
416 int num_blocks = block_count();
417 for (int i = 0; i < num_blocks; i++) {
418 BlockBegin* block = block_at(i);
419 LIR_OpList* instructions = block->lir()->instructions_list();
420 int num_inst = instructions->length();
421 bool has_new = false;
422
423 // iterate all instructions of the block. skip the first because it is always a label
424 for (int j = 1; j < num_inst; j++) {
425 LIR_Op* op = instructions->at(j);
426 int op_id = op->id();
427
428 if (op_id == -1) {
429 // remove move from register to stack if the stack slot is guaranteed to be correct.
430 // only moves that have been inserted by LinearScan can be removed.
431 assert(op->code() == lir_move, "only moves can have a op_id of -1");
432 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
433 assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
434
435 LIR_Op1* op1 = (LIR_Op1*)op;
436 Interval* interval = interval_at(op1->result_opr()->vreg_number());
437
438 if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) {
439 // move target is a stack slot that is always correct, so eliminate instruction
440 TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
441 instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num
442 }
443
444 } else {
445 // insert move from register to stack just after the beginning of the interval
446 assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
447 assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
448
449 while (interval != Interval::end() && interval->spill_definition_pos() == op_id) {
450 if (!has_new) {
451 // prepare insertion buffer (appended when all instructions of the block are processed)
452 insertion_buffer.init(block->lir());
453 has_new = true;
454 }
455
456 LIR_Opr from_opr = operand_for_interval(interval);
457 LIR_Opr to_opr = canonical_spill_opr(interval);
458 assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
459 assert(to_opr->is_stack(), "to operand must be a stack slot");
460
461 insertion_buffer.move(j, from_opr, to_opr);
462 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
463
464 interval = interval->next();
465 }
466 }
467 } // end of instruction iteration
468
469 if (has_new) {
470 block->lir()->append(&insertion_buffer);
471 }
472 } // end of block iteration
473
474 assert(interval == Interval::end(), "missed an interval");
475 }
476
477
478 // ********** Phase 1: number all instructions in all blocks
479 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
480
481 void LinearScan::number_instructions() {
482 {
483 // dummy-timer to measure the cost of the timer itself
484 // (this time is then subtracted from all other timers to get the real value)
485 TIME_LINEAR_SCAN(timer_do_nothing);
486 }
487 TIME_LINEAR_SCAN(timer_number_instructions);
488
489 // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
490 int num_blocks = block_count();
491 int num_instructions = 0;
492 int i;
493 for (i = 0; i < num_blocks; i++) {
494 num_instructions += block_at(i)->lir()->instructions_list()->length();
495 }
496
497 // initialize with correct length
498 _lir_ops = LIR_OpArray(num_instructions);
499 _block_of_op = BlockBeginArray(num_instructions);
500
501 int op_id = 0;
502 int idx = 0;
503
504 for (i = 0; i < num_blocks; i++) {
505 BlockBegin* block = block_at(i);
506 block->set_first_lir_instruction_id(op_id);
507 LIR_OpList* instructions = block->lir()->instructions_list();
508
509 int num_inst = instructions->length();
510 for (int j = 0; j < num_inst; j++) {
511 LIR_Op* op = instructions->at(j);
512 op->set_id(op_id);
513
514 _lir_ops.at_put(idx, op);
515 _block_of_op.at_put(idx, block);
516 assert(lir_op_with_id(op_id) == op, "must match");
517
518 idx++;
519 op_id += 2; // numbering of lir_ops by two
520 }
521 block->set_last_lir_instruction_id(op_id - 2);
522 }
523 assert(idx == num_instructions, "must match");
524 assert(idx * 2 == op_id, "must match");
525
526 _has_call = BitMap(num_instructions); _has_call.clear();
527 _has_info = BitMap(num_instructions); _has_info.clear();
528 }
529
530
531 // ********** Phase 2: compute local live sets separately for each block
532 // (sets live_gen and live_kill for each block)
533
534 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
535 LIR_Opr opr = value->operand();
536 Constant* con = value->as_Constant();
537
538 // check some asumptions about debug information
539 assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
540 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands");
541 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
542
543 if ((con == NULL || con->is_pinned()) && opr->is_register()) {
544 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
545 int reg = opr->vreg_number();
546 if (!live_kill.at(reg)) {
547 live_gen.set_bit(reg);
548 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
549 }
550 }
551 }
552
553
554 void LinearScan::compute_local_live_sets() {
555 TIME_LINEAR_SCAN(timer_compute_local_live_sets);
556
557 int num_blocks = block_count();
558 int live_size = live_set_size();
559 bool local_has_fpu_registers = false;
560 int local_num_calls = 0;
561 LIR_OpVisitState visitor;
562
563 BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops());
564 local_interval_in_loop.clear();
565
566 // iterate all blocks
567 for (int i = 0; i < num_blocks; i++) {
568 BlockBegin* block = block_at(i);
569
570 BitMap live_gen(live_size); live_gen.clear();
571 BitMap live_kill(live_size); live_kill.clear();
572
573 if (block->is_set(BlockBegin::exception_entry_flag)) {
574 // Phi functions at the begin of an exception handler are
575 // implicitly defined (= killed) at the beginning of the block.
576 for_each_phi_fun(block, phi,
577 live_kill.set_bit(phi->operand()->vreg_number())
578 );
579 }
580
581 LIR_OpList* instructions = block->lir()->instructions_list();
582 int num_inst = instructions->length();
583
584 // iterate all instructions of the block. skip the first because it is always a label
585 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
586 for (int j = 1; j < num_inst; j++) {
587 LIR_Op* op = instructions->at(j);
588
589 // visit operation to collect all operands
590 visitor.visit(op);
591
592 if (visitor.has_call()) {
593 _has_call.set_bit(op->id() >> 1);
594 local_num_calls++;
595 }
596 if (visitor.info_count() > 0) {
597 _has_info.set_bit(op->id() >> 1);
598 }
599
600 // iterate input operands of instruction
601 int k, n, reg;
602 n = visitor.opr_count(LIR_OpVisitState::inputMode);
603 for (k = 0; k < n; k++) {
604 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
605 assert(opr->is_register(), "visitor should only return register operands");
606
607 if (opr->is_virtual_register()) {
608 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
609 reg = opr->vreg_number();
610 if (!live_kill.at(reg)) {
611 live_gen.set_bit(reg);
612 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for register %d at instruction %d", reg, op->id()));
613 }
614 if (block->loop_index() >= 0) {
615 local_interval_in_loop.set_bit(reg, block->loop_index());
616 }
617 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
618 }
619
620 #ifdef ASSERT
621 // fixed intervals are never live at block boundaries, so
622 // they need not be processed in live sets.
623 // this is checked by these assertions to be sure about it.
624 // the entry block may have incoming values in registers, which is ok.
625 if (!opr->is_virtual_register() && block != ir()->start()) {
626 reg = reg_num(opr);
627 if (is_processed_reg_num(reg)) {
628 assert(live_kill.at(reg), "using fixed register that is not defined in this block");
629 }
630 reg = reg_numHi(opr);
631 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
632 assert(live_kill.at(reg), "using fixed register that is not defined in this block");
633 }
634 }
635 #endif
636 }
637
638 // Add uses of live locals from interpreter's point of view for proper debug information generation
639 n = visitor.info_count();
640 for (k = 0; k < n; k++) {
641 CodeEmitInfo* info = visitor.info_at(k);
642 ValueStack* stack = info->stack();
643 for_each_state_value(stack, value,
644 set_live_gen_kill(value, op, live_gen, live_kill)
645 );
646 }
647
648 // iterate temp operands of instruction
649 n = visitor.opr_count(LIR_OpVisitState::tempMode);
650 for (k = 0; k < n; k++) {
651 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
652 assert(opr->is_register(), "visitor should only return register operands");
653
654 if (opr->is_virtual_register()) {
655 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
656 reg = opr->vreg_number();
657 live_kill.set_bit(reg);
658 if (block->loop_index() >= 0) {
659 local_interval_in_loop.set_bit(reg, block->loop_index());
660 }
661 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
662 }
663
664 #ifdef ASSERT
665 // fixed intervals are never live at block boundaries, so
666 // they need not be processed in live sets
667 // process them only in debug mode so that this can be checked
668 if (!opr->is_virtual_register()) {
669 reg = reg_num(opr);
670 if (is_processed_reg_num(reg)) {
671 live_kill.set_bit(reg_num(opr));
672 }
673 reg = reg_numHi(opr);
674 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
675 live_kill.set_bit(reg);
676 }
677 }
678 #endif
679 }
680
681 // iterate output operands of instruction
682 n = visitor.opr_count(LIR_OpVisitState::outputMode);
683 for (k = 0; k < n; k++) {
684 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
685 assert(opr->is_register(), "visitor should only return register operands");
686
687 if (opr->is_virtual_register()) {
688 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
689 reg = opr->vreg_number();
690 live_kill.set_bit(reg);
691 if (block->loop_index() >= 0) {
692 local_interval_in_loop.set_bit(reg, block->loop_index());
693 }
694 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
695 }
696
697 #ifdef ASSERT
698 // fixed intervals are never live at block boundaries, so
699 // they need not be processed in live sets
700 // process them only in debug mode so that this can be checked
701 if (!opr->is_virtual_register()) {
702 reg = reg_num(opr);
703 if (is_processed_reg_num(reg)) {
704 live_kill.set_bit(reg_num(opr));
705 }
706 reg = reg_numHi(opr);
707 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
708 live_kill.set_bit(reg);
709 }
710 }
711 #endif
712 }
713 } // end of instruction iteration
714
715 block->set_live_gen (live_gen);
716 block->set_live_kill(live_kill);
717 block->set_live_in (BitMap(live_size)); block->live_in().clear();
718 block->set_live_out (BitMap(live_size)); block->live_out().clear();
719
720 TRACE_LINEAR_SCAN(4, tty->print("live_gen B%d ", block->block_id()); print_bitmap(block->live_gen()));
721 TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
722 } // end of block iteration
723
724 // propagate local calculated information into LinearScan object
725 _has_fpu_registers = local_has_fpu_registers;
726 compilation()->set_has_fpu_code(local_has_fpu_registers);
727
728 _num_calls = local_num_calls;
729 _interval_in_loop = local_interval_in_loop;
730 }
731
732
733 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets
734 // (sets live_in and live_out for each block)
735
736 void LinearScan::compute_global_live_sets() {
737 TIME_LINEAR_SCAN(timer_compute_global_live_sets);
738
739 int num_blocks = block_count();
740 bool change_occurred;
741 bool change_occurred_in_block;
742 int iteration_count = 0;
743 BitMap live_out(live_set_size()); live_out.clear(); // scratch set for calculations
744
745 // Perform a backward dataflow analysis to compute live_out and live_in for each block.
746 // The loop is executed until a fixpoint is reached (no changes in an iteration)
747 // Exception handlers must be processed because not all live values are
748 // present in the state array, e.g. because of global value numbering
749 do {
750 change_occurred = false;
751
752 // iterate all blocks in reverse order
753 for (int i = num_blocks - 1; i >= 0; i--) {
754 BlockBegin* block = block_at(i);
755
756 change_occurred_in_block = false;
757
758 // live_out(block) is the union of live_in(sux), for successors sux of block
759 int n = block->number_of_sux();
760 int e = block->number_of_exception_handlers();
761 if (n + e > 0) {
762 // block has successors
763 if (n > 0) {
764 live_out.set_from(block->sux_at(0)->live_in());
765 for (int j = 1; j < n; j++) {
766 live_out.set_union(block->sux_at(j)->live_in());
767 }
768 } else {
769 live_out.clear();
770 }
771 for (int j = 0; j < e; j++) {
772 live_out.set_union(block->exception_handler_at(j)->live_in());
773 }
774
775 if (!block->live_out().is_same(live_out)) {
776 // A change occurred. Swap the old and new live out sets to avoid copying.
777 BitMap temp = block->live_out();
778 block->set_live_out(live_out);
779 live_out = temp;
780
781 change_occurred = true;
782 change_occurred_in_block = true;
783 }
784 }
785
786 if (iteration_count == 0 || change_occurred_in_block) {
787 // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
788 // note: live_in has to be computed only in first iteration or if live_out has changed!
789 BitMap live_in = block->live_in();
790 live_in.set_from(block->live_out());
791 live_in.set_difference(block->live_kill());
792 live_in.set_union(block->live_gen());
793 }
794
795 #ifndef PRODUCT
796 if (TraceLinearScanLevel >= 4) {
797 char c = ' ';
798 if (iteration_count == 0 || change_occurred_in_block) {
799 c = '*';
800 }
801 tty->print("(%d) live_in%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
802 tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
803 }
804 #endif
805 }
806 iteration_count++;
807
808 if (change_occurred && iteration_count > 50) {
809 BAILOUT("too many iterations in compute_global_live_sets");
810 }
811 } while (change_occurred);
812
813
814 #ifdef ASSERT
815 // check that fixed intervals are not live at block boundaries
816 // (live set must be empty at fixed intervals)
817 for (int i = 0; i < num_blocks; i++) {
818 BlockBegin* block = block_at(i);
819 for (int j = 0; j < LIR_OprDesc::vreg_base; j++) {
820 assert(block->live_in().at(j) == false, "live_in set of fixed register must be empty");
821 assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty");
822 assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty");
823 }
824 }
825 #endif
826
827 // check that the live_in set of the first block is empty
828 BitMap live_in_args(ir()->start()->live_in().size());
829 live_in_args.clear();
830 if (!ir()->start()->live_in().is_same(live_in_args)) {
831 #ifdef ASSERT
832 tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
833 tty->print_cr("affected registers:");
834 print_bitmap(ir()->start()->live_in());
835
836 // print some additional information to simplify debugging
837 for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) {
838 if (ir()->start()->live_in().at(i)) {
839 Instruction* instr = gen()->instruction_for_vreg(i);
840 tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
841
842 for (int j = 0; j < num_blocks; j++) {
843 BlockBegin* block = block_at(j);
844 if (block->live_gen().at(i)) {
845 tty->print_cr(" used in block B%d", block->block_id());
846 }
847 if (block->live_kill().at(i)) {
848 tty->print_cr(" defined in block B%d", block->block_id());
849 }
850 }
851 }
852 }
853
854 #endif
855 // when this fails, virtual registers are used before they are defined.
856 assert(false, "live_in set of first block must be empty");
857 // bailout of if this occurs in product mode.
858 bailout("live_in set of first block not empty");
859 }
860 }
861
862
863 // ********** Phase 4: build intervals
864 // (fills the list _intervals)
865
866 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) {
867 assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
868 LIR_Opr opr = value->operand();
869 Constant* con = value->as_Constant();
870
871 if ((con == NULL || con->is_pinned()) && opr->is_register()) {
872 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
873 add_use(opr, from, to, use_kind);
874 }
875 }
876
877
878 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) {
879 TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
880 assert(opr->is_register(), "should not be called otherwise");
881
882 if (opr->is_virtual_register()) {
883 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
884 add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register());
885
886 } else {
887 int reg = reg_num(opr);
888 if (is_processed_reg_num(reg)) {
889 add_def(reg, def_pos, use_kind, opr->type_register());
890 }
891 reg = reg_numHi(opr);
892 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
893 add_def(reg, def_pos, use_kind, opr->type_register());
894 }
895 }
896 }
897
898 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) {
899 TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
900 assert(opr->is_register(), "should not be called otherwise");
901
902 if (opr->is_virtual_register()) {
903 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
904 add_use(opr->vreg_number(), from, to, use_kind, opr->type_register());
905
906 } else {
907 int reg = reg_num(opr);
908 if (is_processed_reg_num(reg)) {
909 add_use(reg, from, to, use_kind, opr->type_register());
910 }
911 reg = reg_numHi(opr);
912 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
913 add_use(reg, from, to, use_kind, opr->type_register());
914 }
915 }
916 }
917
918 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) {
919 TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
920 assert(opr->is_register(), "should not be called otherwise");
921
922 if (opr->is_virtual_register()) {
923 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
924 add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register());
925
926 } else {
927 int reg = reg_num(opr);
928 if (is_processed_reg_num(reg)) {
929 add_temp(reg, temp_pos, use_kind, opr->type_register());
930 }
931 reg = reg_numHi(opr);
932 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
933 add_temp(reg, temp_pos, use_kind, opr->type_register());
934 }
935 }
936 }
937
938
939 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) {
940 Interval* interval = interval_at(reg_num);
941 if (interval != NULL) {
942 assert(interval->reg_num() == reg_num, "wrong interval");
943
944 if (type != T_ILLEGAL) {
945 interval->set_type(type);
946 }
947
948 Range* r = interval->first();
949 if (r->from() <= def_pos) {
950 // Update the starting point (when a range is first created for a use, its
951 // start is the beginning of the current block until a def is encountered.)
952 r->set_from(def_pos);
953 interval->add_use_pos(def_pos, use_kind);
954
955 } else {
956 // Dead value - make vacuous interval
957 // also add use_kind for dead intervals
958 interval->add_range(def_pos, def_pos + 1);
959 interval->add_use_pos(def_pos, use_kind);
960 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
961 }
962
963 } else {
964 // Dead value - make vacuous interval
965 // also add use_kind for dead intervals
966 interval = create_interval(reg_num);
967 if (type != T_ILLEGAL) {
968 interval->set_type(type);
969 }
970
971 interval->add_range(def_pos, def_pos + 1);
972 interval->add_use_pos(def_pos, use_kind);
973 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
974 }
975
976 change_spill_definition_pos(interval, def_pos);
977 if (use_kind == noUse && interval->spill_state() <= startInMemory) {
978 // detection of method-parameters and roundfp-results
979 // TODO: move this directly to position where use-kind is computed
980 interval->set_spill_state(startInMemory);
981 }
982 }
983
984 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
985 Interval* interval = interval_at(reg_num);
986 if (interval == NULL) {
987 interval = create_interval(reg_num);
988 }
989 assert(interval->reg_num() == reg_num, "wrong interval");
990
991 if (type != T_ILLEGAL) {
992 interval->set_type(type);
993 }
994
995 interval->add_range(from, to);
996 interval->add_use_pos(to, use_kind);
997 }
998
999 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
1000 Interval* interval = interval_at(reg_num);
1001 if (interval == NULL) {
1002 interval = create_interval(reg_num);
1003 }
1004 assert(interval->reg_num() == reg_num, "wrong interval");
1005
1006 if (type != T_ILLEGAL) {
1007 interval->set_type(type);
1008 }
1009
1010 interval->add_range(temp_pos, temp_pos + 1);
1011 interval->add_use_pos(temp_pos, use_kind);
1012 }
1013
1014
1015 // the results of this functions are used for optimizing spilling and reloading
1016 // if the functions return shouldHaveRegister and the interval is spilled,
1017 // it is not reloaded to a register.
1018 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) {
1019 if (op->code() == lir_move) {
1020 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1021 LIR_Op1* move = (LIR_Op1*)op;
1022 LIR_Opr res = move->result_opr();
1023 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1024
1025 if (result_in_memory) {
1026 // Begin of an interval with must_start_in_memory set.
1027 // This interval will always get a stack slot first, so return noUse.
1028 return noUse;
1029
1030 } else if (move->in_opr()->is_stack()) {
1031 // method argument (condition must be equal to handle_method_arguments)
1032 return noUse;
1033
1034 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1035 // Move from register to register
1036 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1037 // special handling of phi-function moves inside osr-entry blocks
1038 // input operand must have a register instead of output operand (leads to better register allocation)
1039 return shouldHaveRegister;
1040 }
1041 }
1042 }
1043
1044 if (opr->is_virtual() &&
1045 gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) {
1046 // result is a stack-slot, so prevent immediate reloading
1047 return noUse;
1048 }
1049
1050 // all other operands require a register
1051 return mustHaveRegister;
1052 }
1053
1054 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
1055 if (op->code() == lir_move) {
1056 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1057 LIR_Op1* move = (LIR_Op1*)op;
1058 LIR_Opr res = move->result_opr();
1059 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1060
1061 if (result_in_memory) {
1062 // Move to an interval with must_start_in_memory set.
1063 // To avoid moves from stack to stack (not allowed) force the input operand to a register
1064 return mustHaveRegister;
1065
1066 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1067 // Move from register to register
1068 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1069 // special handling of phi-function moves inside osr-entry blocks
1070 // input operand must have a register instead of output operand (leads to better register allocation)
1071 return mustHaveRegister;
1072 }
1073
1074 // The input operand is not forced to a register (moves from stack to register are allowed),
1075 // but it is faster if the input operand is in a register
1076 return shouldHaveRegister;
1077 }
1078 }
1079
1080
1081 #ifdef X86
1082 if (op->code() == lir_cmove) {
1083 // conditional moves can handle stack operands
1084 assert(op->result_opr()->is_register(), "result must always be in a register");
1085 return shouldHaveRegister;
1086 }
1087
1088 // optimizations for second input operand of arithmehtic operations on Intel
1089 // this operand is allowed to be on the stack in some cases
1090 BasicType opr_type = opr->type_register();
1091 if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1092 if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2) {
1093 // SSE float instruction (T_DOUBLE only supported with SSE2)
1094 switch (op->code()) {
1095 case lir_cmp:
1096 case lir_add:
1097 case lir_sub:
1098 case lir_mul:
1099 case lir_div:
1100 {
1101 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1102 LIR_Op2* op2 = (LIR_Op2*)op;
1103 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1104 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1105 return shouldHaveRegister;
1106 }
1107 }
1108 }
1109 } else {
1110 // FPU stack float instruction
1111 switch (op->code()) {
1112 case lir_add:
1113 case lir_sub:
1114 case lir_mul:
1115 case lir_div:
1116 {
1117 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1118 LIR_Op2* op2 = (LIR_Op2*)op;
1119 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1120 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1121 return shouldHaveRegister;
1122 }
1123 }
1124 }
1125 }
1126 // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1127 // Since 64bit logical operations do not current support operands on stack, we have to make sure
1128 // T_OBJECT doesn't get spilled along with T_LONG.
1129 } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1130 // integer instruction (note: long operands must always be in register)
1131 switch (op->code()) {
1132 case lir_cmp:
1133 case lir_add:
1134 case lir_sub:
1135 case lir_logic_and:
1136 case lir_logic_or:
1137 case lir_logic_xor:
1138 {
1139 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1140 LIR_Op2* op2 = (LIR_Op2*)op;
1141 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1142 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1143 return shouldHaveRegister;
1144 }
1145 }
1146 }
1147 }
1148 #endif // X86
1149
1150 // all other operands require a register
1151 return mustHaveRegister;
1152 }
1153
1154
1155 void LinearScan::handle_method_arguments(LIR_Op* op) {
1156 // special handling for method arguments (moves from stack to virtual register):
1157 // the interval gets no register assigned, but the stack slot.
1158 // it is split before the first use by the register allocator.
1159
1160 if (op->code() == lir_move) {
1161 assert(op->as_Op1() != NULL, "must be LIR_Op1");
1162 LIR_Op1* move = (LIR_Op1*)op;
1163
1164 if (move->in_opr()->is_stack()) {
1165 #ifdef ASSERT
1166 int arg_size = compilation()->method()->arg_size();
1167 LIR_Opr o = move->in_opr();
1168 if (o->is_single_stack()) {
1169 assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range");
1170 } else if (o->is_double_stack()) {
1171 assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range");
1172 } else {
1173 ShouldNotReachHere();
1174 }
1175
1176 assert(move->id() > 0, "invalid id");
1177 assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
1178 assert(move->result_opr()->is_virtual(), "result of move must be a virtual register");
1179
1180 TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
1181 #endif
1182
1183 Interval* interval = interval_at(reg_num(move->result_opr()));
1184
1185 int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
1186 interval->set_canonical_spill_slot(stack_slot);
1187 interval->assign_reg(stack_slot);
1188 }
1189 }
1190 }
1191
1192 void LinearScan::handle_doubleword_moves(LIR_Op* op) {
1193 // special handling for doubleword move from memory to register:
1194 // in this case the registers of the input address and the result
1195 // registers must not overlap -> add a temp range for the input registers
1196 if (op->code() == lir_move) {
1197 assert(op->as_Op1() != NULL, "must be LIR_Op1");
1198 LIR_Op1* move = (LIR_Op1*)op;
1199
1200 if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) {
1201 LIR_Address* address = move->in_opr()->as_address_ptr();
1202 if (address != NULL) {
1203 if (address->base()->is_valid()) {
1204 add_temp(address->base(), op->id(), noUse);
1205 }
1206 if (address->index()->is_valid()) {
1207 add_temp(address->index(), op->id(), noUse);
1208 }
1209 }
1210 }
1211 }
1212 }
1213
1214 void LinearScan::add_register_hints(LIR_Op* op) {
1215 switch (op->code()) {
1216 case lir_move: // fall through
1217 case lir_convert: {
1218 assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1");
1219 LIR_Op1* move = (LIR_Op1*)op;
1220
1221 LIR_Opr move_from = move->in_opr();
1222 LIR_Opr move_to = move->result_opr();
1223
1224 if (move_to->is_register() && move_from->is_register()) {
1225 Interval* from = interval_at(reg_num(move_from));
1226 Interval* to = interval_at(reg_num(move_to));
1227 if (from != NULL && to != NULL) {
1228 to->set_register_hint(from);
1229 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
1230 }
1231 }
1232 break;
1233 }
1234 case lir_cmove: {
1235 assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
1236 LIR_Op2* cmove = (LIR_Op2*)op;
1237
1238 LIR_Opr move_from = cmove->in_opr1();
1239 LIR_Opr move_to = cmove->result_opr();
1240
1241 if (move_to->is_register() && move_from->is_register()) {
1242 Interval* from = interval_at(reg_num(move_from));
1243 Interval* to = interval_at(reg_num(move_to));
1244 if (from != NULL && to != NULL) {
1245 to->set_register_hint(from);
1246 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1247 }
1248 }
1249 break;
1250 }
1251 }
1252 }
1253
1254
1255 void LinearScan::build_intervals() {
1256 TIME_LINEAR_SCAN(timer_build_intervals);
1257
1258 // initialize interval list with expected number of intervals
1259 // (32 is added to have some space for split children without having to resize the list)
1260 _intervals = IntervalList(num_virtual_regs() + 32);
1261 // initialize all slots that are used by build_intervals
1262 _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
1263
1264 // create a list with all caller-save registers (cpu, fpu, xmm)
1265 // when an instruction is a call, a temp range is created for all these registers
1266 int num_caller_save_registers = 0;
1267 int caller_save_registers[LinearScan::nof_regs];
1268
1269 int i;
1270 for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
1271 LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i);
1272 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1273 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1274 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1275 }
1276
1277 // temp ranges for fpu registers are only created when the method has
1278 // virtual fpu operands. Otherwise no allocation for fpu registers is
1279 // perfomed and so the temp ranges would be useless
1280 if (has_fpu_registers()) {
1281 #ifdef X86
1282 if (UseSSE < 2) {
1283 #endif
1284 for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1285 LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1286 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1287 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1288 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1289 }
1290 #ifdef X86
1291 }
1292 if (UseSSE > 0) {
1293 int num_caller_save_xmm_regs = FrameMap::nof_caller_save_xmm_regs;
1294 #if _LP64
1295 if (UseAVX < 3) {
1296 num_caller_save_xmm_regs = num_caller_save_xmm_regs / 2;
1297 }
1298 #endif
1299 for (i = 0; i < num_caller_save_xmm_regs; i ++) {
1300 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1301 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1302 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1303 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1304 }
1305 }
1306 #endif
1307 }
1308 assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1309
1310
1311 LIR_OpVisitState visitor;
1312
1313 // iterate all blocks in reverse order
1314 for (i = block_count() - 1; i >= 0; i--) {
1315 BlockBegin* block = block_at(i);
1316 LIR_OpList* instructions = block->lir()->instructions_list();
1317 int block_from = block->first_lir_instruction_id();
1318 int block_to = block->last_lir_instruction_id();
1319
1320 assert(block_from == instructions->at(0)->id(), "must be");
1321 assert(block_to == instructions->at(instructions->length() - 1)->id(), "must be");
1322
1323 // Update intervals for registers live at the end of this block;
1324 BitMap live = block->live_out();
1325 int size = (int)live.size();
1326 for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
1327 assert(live.at(number), "should not stop here otherwise");
1328 assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
1329 TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
1330
1331 add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
1332
1333 // add special use positions for loop-end blocks when the
1334 // interval is used anywhere inside this loop. It's possible
1335 // that the block was part of a non-natural loop, so it might
1336 // have an invalid loop index.
1337 if (block->is_set(BlockBegin::linear_scan_loop_end_flag) &&
1338 block->loop_index() != -1 &&
1339 is_interval_in_loop(number, block->loop_index())) {
1340 interval_at(number)->add_use_pos(block_to + 1, loopEndMarker);
1341 }
1342 }
1343
1344 // iterate all instructions of the block in reverse order.
1345 // skip the first instruction because it is always a label
1346 // definitions of intervals are processed before uses
1347 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
1348 for (int j = instructions->length() - 1; j >= 1; j--) {
1349 LIR_Op* op = instructions->at(j);
1350 int op_id = op->id();
1351
1352 // visit operation to collect all operands
1353 visitor.visit(op);
1354
1355 // add a temp range for each register if operation destroys caller-save registers
1356 if (visitor.has_call()) {
1357 for (int k = 0; k < num_caller_save_registers; k++) {
1358 add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL);
1359 }
1360 TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers"));
1361 }
1362
1363 // Add any platform dependent temps
1364 pd_add_temps(op);
1365
1366 // visit definitions (output and temp operands)
1367 int k, n;
1368 n = visitor.opr_count(LIR_OpVisitState::outputMode);
1369 for (k = 0; k < n; k++) {
1370 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
1371 assert(opr->is_register(), "visitor should only return register operands");
1372 add_def(opr, op_id, use_kind_of_output_operand(op, opr));
1373 }
1374
1375 n = visitor.opr_count(LIR_OpVisitState::tempMode);
1376 for (k = 0; k < n; k++) {
1377 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
1378 assert(opr->is_register(), "visitor should only return register operands");
1379 add_temp(opr, op_id, mustHaveRegister);
1380 }
1381
1382 // visit uses (input operands)
1383 n = visitor.opr_count(LIR_OpVisitState::inputMode);
1384 for (k = 0; k < n; k++) {
1385 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
1386 assert(opr->is_register(), "visitor should only return register operands");
1387 add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr));
1388 }
1389
1390 // Add uses of live locals from interpreter's point of view for proper
1391 // debug information generation
1392 // Treat these operands as temp values (if the life range is extended
1393 // to a call site, the value would be in a register at the call otherwise)
1394 n = visitor.info_count();
1395 for (k = 0; k < n; k++) {
1396 CodeEmitInfo* info = visitor.info_at(k);
1397 ValueStack* stack = info->stack();
1398 for_each_state_value(stack, value,
1399 add_use(value, block_from, op_id + 1, noUse);
1400 );
1401 }
1402
1403 // special steps for some instructions (especially moves)
1404 handle_method_arguments(op);
1405 handle_doubleword_moves(op);
1406 add_register_hints(op);
1407
1408 } // end of instruction iteration
1409 } // end of block iteration
1410
1411
1412 // add the range [0, 1[ to all fixed intervals
1413 // -> the register allocator need not handle unhandled fixed intervals
1414 for (int n = 0; n < LinearScan::nof_regs; n++) {
1415 Interval* interval = interval_at(n);
1416 if (interval != NULL) {
1417 interval->add_range(0, 1);
1418 }
1419 }
1420 }
1421
1422
1423 // ********** Phase 5: actual register allocation
1424
1425 int LinearScan::interval_cmp(Interval** a, Interval** b) {
1426 if (*a != NULL) {
1427 if (*b != NULL) {
1428 return (*a)->from() - (*b)->from();
1429 } else {
1430 return -1;
1431 }
1432 } else {
1433 if (*b != NULL) {
1434 return 1;
1435 } else {
1436 return 0;
1437 }
1438 }
1439 }
1440
1441 #ifndef PRODUCT
1442 bool LinearScan::is_sorted(IntervalArray* intervals) {
1443 int from = -1;
1444 int i, j;
1445 for (i = 0; i < intervals->length(); i ++) {
1446 Interval* it = intervals->at(i);
1447 if (it != NULL) {
1448 if (from > it->from()) {
1449 assert(false, "");
1450 return false;
1451 }
1452 from = it->from();
1453 }
1454 }
1455
1456 // check in both directions if sorted list and unsorted list contain same intervals
1457 for (i = 0; i < interval_count(); i++) {
1458 if (interval_at(i) != NULL) {
1459 int num_found = 0;
1460 for (j = 0; j < intervals->length(); j++) {
1461 if (interval_at(i) == intervals->at(j)) {
1462 num_found++;
1463 }
1464 }
1465 assert(num_found == 1, "lists do not contain same intervals");
1466 }
1467 }
1468 for (j = 0; j < intervals->length(); j++) {
1469 int num_found = 0;
1470 for (i = 0; i < interval_count(); i++) {
1471 if (interval_at(i) == intervals->at(j)) {
1472 num_found++;
1473 }
1474 }
1475 assert(num_found == 1, "lists do not contain same intervals");
1476 }
1477
1478 return true;
1479 }
1480 #endif
1481
1482 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) {
1483 if (*prev != NULL) {
1484 (*prev)->set_next(interval);
1485 } else {
1486 *first = interval;
1487 }
1488 *prev = interval;
1489 }
1490
1491 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
1492 assert(is_sorted(_sorted_intervals), "interval list is not sorted");
1493
1494 *list1 = *list2 = Interval::end();
1495
1496 Interval* list1_prev = NULL;
1497 Interval* list2_prev = NULL;
1498 Interval* v;
1499
1500 const int n = _sorted_intervals->length();
1501 for (int i = 0; i < n; i++) {
1502 v = _sorted_intervals->at(i);
1503 if (v == NULL) continue;
1504
1505 if (is_list1(v)) {
1506 add_to_list(list1, &list1_prev, v);
1507 } else if (is_list2 == NULL || is_list2(v)) {
1508 add_to_list(list2, &list2_prev, v);
1509 }
1510 }
1511
1512 if (list1_prev != NULL) list1_prev->set_next(Interval::end());
1513 if (list2_prev != NULL) list2_prev->set_next(Interval::end());
1514
1515 assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
1516 assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
1517 }
1518
1519
1520 void LinearScan::sort_intervals_before_allocation() {
1521 TIME_LINEAR_SCAN(timer_sort_intervals_before);
1522
1523 if (_needs_full_resort) {
1524 // There is no known reason why this should occur but just in case...
1525 assert(false, "should never occur");
1526 // Re-sort existing interval list because an Interval::from() has changed
1527 _sorted_intervals->sort(interval_cmp);
1528 _needs_full_resort = false;
1529 }
1530
1531 IntervalList* unsorted_list = &_intervals;
1532 int unsorted_len = unsorted_list->length();
1533 int sorted_len = 0;
1534 int unsorted_idx;
1535 int sorted_idx = 0;
1536 int sorted_from_max = -1;
1537
1538 // calc number of items for sorted list (sorted list must not contain NULL values)
1539 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1540 if (unsorted_list->at(unsorted_idx) != NULL) {
1541 sorted_len++;
1542 }
1543 }
1544 IntervalArray* sorted_list = new IntervalArray(sorted_len);
1545
1546 // special sorting algorithm: the original interval-list is almost sorted,
1547 // only some intervals are swapped. So this is much faster than a complete QuickSort
1548 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1549 Interval* cur_interval = unsorted_list->at(unsorted_idx);
1550
1551 if (cur_interval != NULL) {
1552 int cur_from = cur_interval->from();
1553
1554 if (sorted_from_max <= cur_from) {
1555 sorted_list->at_put(sorted_idx++, cur_interval);
1556 sorted_from_max = cur_interval->from();
1557 } else {
1558 // the asumption that the intervals are already sorted failed,
1559 // so this interval must be sorted in manually
1560 int j;
1561 for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) {
1562 sorted_list->at_put(j + 1, sorted_list->at(j));
1563 }
1564 sorted_list->at_put(j + 1, cur_interval);
1565 sorted_idx++;
1566 }
1567 }
1568 }
1569 _sorted_intervals = sorted_list;
1570 assert(is_sorted(_sorted_intervals), "intervals unsorted");
1571 }
1572
1573 void LinearScan::sort_intervals_after_allocation() {
1574 TIME_LINEAR_SCAN(timer_sort_intervals_after);
1575
1576 if (_needs_full_resort) {
1577 // Re-sort existing interval list because an Interval::from() has changed
1578 _sorted_intervals->sort(interval_cmp);
1579 _needs_full_resort = false;
1580 }
1581
1582 IntervalArray* old_list = _sorted_intervals;
1583 IntervalList* new_list = _new_intervals_from_allocation;
1584 int old_len = old_list->length();
1585 int new_len = new_list->length();
1586
1587 if (new_len == 0) {
1588 // no intervals have been added during allocation, so sorted list is already up to date
1589 assert(is_sorted(_sorted_intervals), "intervals unsorted");
1590 return;
1591 }
1592
1593 // conventional sort-algorithm for new intervals
1594 new_list->sort(interval_cmp);
1595
1596 // merge old and new list (both already sorted) into one combined list
1597 IntervalArray* combined_list = new IntervalArray(old_len + new_len);
1598 int old_idx = 0;
1599 int new_idx = 0;
1600
1601 while (old_idx + new_idx < old_len + new_len) {
1602 if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
1603 combined_list->at_put(old_idx + new_idx, old_list->at(old_idx));
1604 old_idx++;
1605 } else {
1606 combined_list->at_put(old_idx + new_idx, new_list->at(new_idx));
1607 new_idx++;
1608 }
1609 }
1610
1611 _sorted_intervals = combined_list;
1612 assert(is_sorted(_sorted_intervals), "intervals unsorted");
1613 }
1614
1615
1616 void LinearScan::allocate_registers() {
1617 TIME_LINEAR_SCAN(timer_allocate_registers);
1618
1619 Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals;
1620 Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals;
1621
1622 // allocate cpu registers
1623 create_unhandled_lists(&precolored_cpu_intervals, ¬_precolored_cpu_intervals,
1624 is_precolored_cpu_interval, is_virtual_cpu_interval);
1625
1626 // allocate fpu registers
1627 create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals,
1628 is_precolored_fpu_interval, is_virtual_fpu_interval);
1629
1630 // the fpu interval allocation cannot be moved down below with the fpu section as
1631 // the cpu_lsw.walk() changes interval positions.
1632
1633 LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals);
1634 cpu_lsw.walk();
1635 cpu_lsw.finish_allocation();
1636
1637 if (has_fpu_registers()) {
1638 LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals);
1639 fpu_lsw.walk();
1640 fpu_lsw.finish_allocation();
1641 }
1642 }
1643
1644
1645 // ********** Phase 6: resolve data flow
1646 // (insert moves at edges between blocks if intervals have been split)
1647
1648 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
1649 // instead of returning NULL
1650 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
1651 Interval* result = interval->split_child_at_op_id(op_id, mode);
1652 if (result != NULL) {
1653 return result;
1654 }
1655
1656 assert(false, "must find an interval, but do a clean bailout in product mode");
1657 result = new Interval(LIR_OprDesc::vreg_base);
1658 result->assign_reg(0);
1659 result->set_type(T_INT);
1660 BAILOUT_("LinearScan: interval is NULL", result);
1661 }
1662
1663
1664 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) {
1665 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1666 assert(interval_at(reg_num) != NULL, "no interval found");
1667
1668 return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
1669 }
1670
1671 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) {
1672 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1673 assert(interval_at(reg_num) != NULL, "no interval found");
1674
1675 return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
1676 }
1677
1678 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) {
1679 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1680 assert(interval_at(reg_num) != NULL, "no interval found");
1681
1682 return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode);
1683 }
1684
1685
1686 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1687 DEBUG_ONLY(move_resolver.check_empty());
1688
1689 const int num_regs = num_virtual_regs();
1690 const int size = live_set_size();
1691 const BitMap live_at_edge = to_block->live_in();
1692
1693 // visit all registers where the live_at_edge bit is set
1694 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
1695 assert(r < num_regs, "live information set for not exisiting interval");
1696 assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
1697
1698 Interval* from_interval = interval_at_block_end(from_block, r);
1699 Interval* to_interval = interval_at_block_begin(to_block, r);
1700
1701 if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
1702 // need to insert move instruction
1703 move_resolver.add_mapping(from_interval, to_interval);
1704 }
1705 }
1706 }
1707
1708
1709 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1710 if (from_block->number_of_sux() <= 1) {
1711 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
1712
1713 LIR_OpList* instructions = from_block->lir()->instructions_list();
1714 LIR_OpBranch* branch = instructions->last()->as_OpBranch();
1715 if (branch != NULL) {
1716 // insert moves before branch
1717 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
1718 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2);
1719 } else {
1720 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1);
1721 }
1722
1723 } else {
1724 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
1725 #ifdef ASSERT
1726 assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
1727
1728 // because the number of predecessor edges matches the number of
1729 // successor edges, blocks which are reached by switch statements
1730 // may have be more than one predecessor but it will be guaranteed
1731 // that all predecessors will be the same.
1732 for (int i = 0; i < to_block->number_of_preds(); i++) {
1733 assert(from_block == to_block->pred_at(i), "all critical edges must be broken");
1734 }
1735 #endif
1736
1737 move_resolver.set_insert_position(to_block->lir(), 0);
1738 }
1739 }
1740
1741
1742 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
1743 void LinearScan::resolve_data_flow() {
1744 TIME_LINEAR_SCAN(timer_resolve_data_flow);
1745
1746 int num_blocks = block_count();
1747 MoveResolver move_resolver(this);
1748 BitMap block_completed(num_blocks); block_completed.clear();
1749 BitMap already_resolved(num_blocks); already_resolved.clear();
1750
1751 int i;
1752 for (i = 0; i < num_blocks; i++) {
1753 BlockBegin* block = block_at(i);
1754
1755 // check if block has only one predecessor and only one successor
1756 if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
1757 LIR_OpList* instructions = block->lir()->instructions_list();
1758 assert(instructions->at(0)->code() == lir_label, "block must start with label");
1759 assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
1760 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
1761
1762 // check if block is empty (only label and branch)
1763 if (instructions->length() == 2) {
1764 BlockBegin* pred = block->pred_at(0);
1765 BlockBegin* sux = block->sux_at(0);
1766
1767 // prevent optimization of two consecutive blocks
1768 if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
1769 TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
1770 block_completed.set_bit(block->linear_scan_number());
1771
1772 // directly resolve between pred and sux (without looking at the empty block between)
1773 resolve_collect_mappings(pred, sux, move_resolver);
1774 if (move_resolver.has_mappings()) {
1775 move_resolver.set_insert_position(block->lir(), 0);
1776 move_resolver.resolve_and_append_moves();
1777 }
1778 }
1779 }
1780 }
1781 }
1782
1783
1784 for (i = 0; i < num_blocks; i++) {
1785 if (!block_completed.at(i)) {
1786 BlockBegin* from_block = block_at(i);
1787 already_resolved.set_from(block_completed);
1788
1789 int num_sux = from_block->number_of_sux();
1790 for (int s = 0; s < num_sux; s++) {
1791 BlockBegin* to_block = from_block->sux_at(s);
1792
1793 // check for duplicate edges between the same blocks (can happen with switch blocks)
1794 if (!already_resolved.at(to_block->linear_scan_number())) {
1795 TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
1796 already_resolved.set_bit(to_block->linear_scan_number());
1797
1798 // collect all intervals that have been split between from_block and to_block
1799 resolve_collect_mappings(from_block, to_block, move_resolver);
1800 if (move_resolver.has_mappings()) {
1801 resolve_find_insert_pos(from_block, to_block, move_resolver);
1802 move_resolver.resolve_and_append_moves();
1803 }
1804 }
1805 }
1806 }
1807 }
1808 }
1809
1810
1811 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
1812 if (interval_at(reg_num) == NULL) {
1813 // if a phi function is never used, no interval is created -> ignore this
1814 return;
1815 }
1816
1817 Interval* interval = interval_at_block_begin(block, reg_num);
1818 int reg = interval->assigned_reg();
1819 int regHi = interval->assigned_regHi();
1820
1821 if ((reg < nof_regs && interval->always_in_memory()) ||
1822 (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) {
1823 // the interval is split to get a short range that is located on the stack
1824 // in the following two cases:
1825 // * the interval started in memory (e.g. method parameter), but is currently in a register
1826 // this is an optimization for exception handling that reduces the number of moves that
1827 // are necessary for resolving the states when an exception uses this exception handler
1828 // * the interval would be on the fpu stack at the begin of the exception handler
1829 // this is not allowed because of the complicated fpu stack handling on Intel
1830
1831 // range that will be spilled to memory
1832 int from_op_id = block->first_lir_instruction_id();
1833 int to_op_id = from_op_id + 1; // short live range of length 1
1834 assert(interval->from() <= from_op_id && interval->to() >= to_op_id,
1835 "no split allowed between exception entry and first instruction");
1836
1837 if (interval->from() != from_op_id) {
1838 // the part before from_op_id is unchanged
1839 interval = interval->split(from_op_id);
1840 interval->assign_reg(reg, regHi);
1841 append_interval(interval);
1842 } else {
1843 _needs_full_resort = true;
1844 }
1845 assert(interval->from() == from_op_id, "must be true now");
1846
1847 Interval* spilled_part = interval;
1848 if (interval->to() != to_op_id) {
1849 // the part after to_op_id is unchanged
1850 spilled_part = interval->split_from_start(to_op_id);
1851 append_interval(spilled_part);
1852 move_resolver.add_mapping(spilled_part, interval);
1853 }
1854 assign_spill_slot(spilled_part);
1855
1856 assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking");
1857 }
1858 }
1859
1860 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) {
1861 assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
1862 DEBUG_ONLY(move_resolver.check_empty());
1863
1864 // visit all registers where the live_in bit is set
1865 int size = live_set_size();
1866 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1867 resolve_exception_entry(block, r, move_resolver);
1868 }
1869
1870 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1871 for_each_phi_fun(block, phi,
1872 resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver)
1873 );
1874
1875 if (move_resolver.has_mappings()) {
1876 // insert moves after first instruction
1877 move_resolver.set_insert_position(block->lir(), 0);
1878 move_resolver.resolve_and_append_moves();
1879 }
1880 }
1881
1882
1883 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
1884 if (interval_at(reg_num) == NULL) {
1885 // if a phi function is never used, no interval is created -> ignore this
1886 return;
1887 }
1888
1889 // the computation of to_interval is equal to resolve_collect_mappings,
1890 // but from_interval is more complicated because of phi functions
1891 BlockBegin* to_block = handler->entry_block();
1892 Interval* to_interval = interval_at_block_begin(to_block, reg_num);
1893
1894 if (phi != NULL) {
1895 // phi function of the exception entry block
1896 // no moves are created for this phi function in the LIR_Generator, so the
1897 // interval at the throwing instruction must be searched using the operands
1898 // of the phi function
1899 Value from_value = phi->operand_at(handler->phi_operand());
1900
1901 // with phi functions it can happen that the same from_value is used in
1902 // multiple mappings, so notify move-resolver that this is allowed
1903 move_resolver.set_multiple_reads_allowed();
1904
1905 Constant* con = from_value->as_Constant();
1906 if (con != NULL && !con->is_pinned()) {
1907 // unpinned constants may have no register, so add mapping from constant to interval
1908 move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval);
1909 } else {
1910 // search split child at the throwing op_id
1911 Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
1912 move_resolver.add_mapping(from_interval, to_interval);
1913 }
1914
1915 } else {
1916 // no phi function, so use reg_num also for from_interval
1917 // search split child at the throwing op_id
1918 Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id);
1919 if (from_interval != to_interval) {
1920 // optimization to reduce number of moves: when to_interval is on stack and
1921 // the stack slot is known to be always correct, then no move is necessary
1922 if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
1923 move_resolver.add_mapping(from_interval, to_interval);
1924 }
1925 }
1926 }
1927 }
1928
1929 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
1930 TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
1931
1932 DEBUG_ONLY(move_resolver.check_empty());
1933 assert(handler->lir_op_id() == -1, "already processed this xhandler");
1934 DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id));
1935 assert(handler->entry_code() == NULL, "code already present");
1936
1937 // visit all registers where the live_in bit is set
1938 BlockBegin* block = handler->entry_block();
1939 int size = live_set_size();
1940 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1941 resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
1942 }
1943
1944 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1945 for_each_phi_fun(block, phi,
1946 resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver)
1947 );
1948
1949 if (move_resolver.has_mappings()) {
1950 LIR_List* entry_code = new LIR_List(compilation());
1951 move_resolver.set_insert_position(entry_code, 0);
1952 move_resolver.resolve_and_append_moves();
1953
1954 entry_code->jump(handler->entry_block());
1955 handler->set_entry_code(entry_code);
1956 }
1957 }
1958
1959
1960 void LinearScan::resolve_exception_handlers() {
1961 MoveResolver move_resolver(this);
1962 LIR_OpVisitState visitor;
1963 int num_blocks = block_count();
1964
1965 int i;
1966 for (i = 0; i < num_blocks; i++) {
1967 BlockBegin* block = block_at(i);
1968 if (block->is_set(BlockBegin::exception_entry_flag)) {
1969 resolve_exception_entry(block, move_resolver);
1970 }
1971 }
1972
1973 for (i = 0; i < num_blocks; i++) {
1974 BlockBegin* block = block_at(i);
1975 LIR_List* ops = block->lir();
1976 int num_ops = ops->length();
1977
1978 // iterate all instructions of the block. skip the first because it is always a label
1979 assert(visitor.no_operands(ops->at(0)), "first operation must always be a label");
1980 for (int j = 1; j < num_ops; j++) {
1981 LIR_Op* op = ops->at(j);
1982 int op_id = op->id();
1983
1984 if (op_id != -1 && has_info(op_id)) {
1985 // visit operation to collect all operands
1986 visitor.visit(op);
1987 assert(visitor.info_count() > 0, "should not visit otherwise");
1988
1989 XHandlers* xhandlers = visitor.all_xhandler();
1990 int n = xhandlers->length();
1991 for (int k = 0; k < n; k++) {
1992 resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver);
1993 }
1994
1995 #ifdef ASSERT
1996 } else {
1997 visitor.visit(op);
1998 assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
1999 #endif
2000 }
2001 }
2002 }
2003 }
2004
2005
2006 // ********** Phase 7: assign register numbers back to LIR
2007 // (includes computation of debug information and oop maps)
2008
2009 VMReg LinearScan::vm_reg_for_interval(Interval* interval) {
2010 VMReg reg = interval->cached_vm_reg();
2011 if (!reg->is_valid() ) {
2012 reg = vm_reg_for_operand(operand_for_interval(interval));
2013 interval->set_cached_vm_reg(reg);
2014 }
2015 assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value");
2016 return reg;
2017 }
2018
2019 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) {
2020 assert(opr->is_oop(), "currently only implemented for oop operands");
2021 return frame_map()->regname(opr);
2022 }
2023
2024
2025 LIR_Opr LinearScan::operand_for_interval(Interval* interval) {
2026 LIR_Opr opr = interval->cached_opr();
2027 if (opr->is_illegal()) {
2028 opr = calc_operand_for_interval(interval);
2029 interval->set_cached_opr(opr);
2030 }
2031
2032 assert(opr == calc_operand_for_interval(interval), "wrong cached value");
2033 return opr;
2034 }
2035
2036 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
2037 int assigned_reg = interval->assigned_reg();
2038 BasicType type = interval->type();
2039
2040 if (assigned_reg >= nof_regs) {
2041 // stack slot
2042 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2043 return LIR_OprFact::stack(assigned_reg - nof_regs, type);
2044
2045 } else {
2046 // register
2047 switch (type) {
2048 case T_OBJECT: {
2049 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2050 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2051 return LIR_OprFact::single_cpu_oop(assigned_reg);
2052 }
2053
2054 case T_ADDRESS: {
2055 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2056 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2057 return LIR_OprFact::single_cpu_address(assigned_reg);
2058 }
2059
2060 case T_METADATA: {
2061 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2062 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2063 return LIR_OprFact::single_cpu_metadata(assigned_reg);
2064 }
2065
2066 #ifdef __SOFTFP__
2067 case T_FLOAT: // fall through
2068 #endif // __SOFTFP__
2069 case T_INT: {
2070 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2071 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2072 return LIR_OprFact::single_cpu(assigned_reg);
2073 }
2074
2075 #ifdef __SOFTFP__
2076 case T_DOUBLE: // fall through
2077 #endif // __SOFTFP__
2078 case T_LONG: {
2079 int assigned_regHi = interval->assigned_regHi();
2080 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2081 assert(num_physical_regs(T_LONG) == 1 ||
2082 (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
2083
2084 assert(assigned_reg != assigned_regHi, "invalid allocation");
2085 assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
2086 "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
2087 assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2088 if (requires_adjacent_regs(T_LONG)) {
2089 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2090 }
2091
2092 #ifdef _LP64
2093 return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2094 #else
2095 #if defined(SPARC) || defined(PPC)
2096 return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
2097 #else
2098 return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2099 #endif // SPARC
2100 #endif // LP64
2101 }
2102
2103 #ifndef __SOFTFP__
2104 case T_FLOAT: {
2105 #ifdef X86
2106 if (UseSSE >= 1) {
2107 int last_xmm_reg = pd_last_xmm_reg;
2108 #ifdef _LP64
2109 if (UseAVX < 3) {
2110 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2111 }
2112 #endif
2113 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2114 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2115 return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2116 }
2117 #endif
2118
2119 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2120 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2121 return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2122 }
2123
2124 case T_DOUBLE: {
2125 #ifdef X86
2126 if (UseSSE >= 2) {
2127 int last_xmm_reg = pd_last_xmm_reg;
2128 #ifdef _LP64
2129 if (UseAVX < 3) {
2130 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2131 }
2132 #endif
2133 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2134 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2135 return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2136 }
2137 #endif
2138
2139 #ifdef SPARC
2140 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2141 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2142 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2143 LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
2144 #elif defined(ARM32)
2145 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2146 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2147 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2148 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2149 #else
2150 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2151 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2152 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2153 #endif
2154 return result;
2155 }
2156 #endif // __SOFTFP__
2157
2158 default: {
2159 ShouldNotReachHere();
2160 return LIR_OprFact::illegalOpr;
2161 }
2162 }
2163 }
2164 }
2165
2166 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) {
2167 assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set");
2168 return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type());
2169 }
2170
2171 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) {
2172 assert(opr->is_virtual(), "should not call this otherwise");
2173
2174 Interval* interval = interval_at(opr->vreg_number());
2175 assert(interval != NULL, "interval must exist");
2176
2177 if (op_id != -1) {
2178 #ifdef ASSERT
2179 BlockBegin* block = block_of_op_with_id(op_id);
2180 if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) {
2181 // check if spill moves could have been appended at the end of this block, but
2182 // before the branch instruction. So the split child information for this branch would
2183 // be incorrect.
2184 LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch();
2185 if (branch != NULL) {
2186 if (block->live_out().at(opr->vreg_number())) {
2187 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
2188 assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
2189 }
2190 }
2191 }
2192 #endif
2193
2194 // operands are not changed when an interval is split during allocation,
2195 // so search the right interval here
2196 interval = split_child_at_op_id(interval, op_id, mode);
2197 }
2198
2199 LIR_Opr res = operand_for_interval(interval);
2200
2201 #ifdef X86
2202 // new semantic for is_last_use: not only set on definite end of interval,
2203 // but also before hole
2204 // This may still miss some cases (e.g. for dead values), but it is not necessary that the
2205 // last use information is completely correct
2206 // information is only needed for fpu stack allocation
2207 if (res->is_fpu_register()) {
2208 if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
2209 assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
2210 res = res->make_last_use();
2211 }
2212 }
2213 #endif
2214
2215 assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
2216
2217 return res;
2218 }
2219
2220
2221 #ifdef ASSERT
2222 // some methods used to check correctness of debug information
2223
2224 void assert_no_register_values(GrowableArray<ScopeValue*>* values) {
2225 if (values == NULL) {
2226 return;
2227 }
2228
2229 for (int i = 0; i < values->length(); i++) {
2230 ScopeValue* value = values->at(i);
2231
2232 if (value->is_location()) {
2233 Location location = ((LocationValue*)value)->location();
2234 assert(location.where() == Location::on_stack, "value is in register");
2235 }
2236 }
2237 }
2238
2239 void assert_no_register_values(GrowableArray<MonitorValue*>* values) {
2240 if (values == NULL) {
2241 return;
2242 }
2243
2244 for (int i = 0; i < values->length(); i++) {
2245 MonitorValue* value = values->at(i);
2246
2247 if (value->owner()->is_location()) {
2248 Location location = ((LocationValue*)value->owner())->location();
2249 assert(location.where() == Location::on_stack, "owner is in register");
2250 }
2251 assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register");
2252 }
2253 }
2254
2255 void assert_equal(Location l1, Location l2) {
2256 assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), "");
2257 }
2258
2259 void assert_equal(ScopeValue* v1, ScopeValue* v2) {
2260 if (v1->is_location()) {
2261 assert(v2->is_location(), "");
2262 assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location());
2263 } else if (v1->is_constant_int()) {
2264 assert(v2->is_constant_int(), "");
2265 assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), "");
2266 } else if (v1->is_constant_double()) {
2267 assert(v2->is_constant_double(), "");
2268 assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), "");
2269 } else if (v1->is_constant_long()) {
2270 assert(v2->is_constant_long(), "");
2271 assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), "");
2272 } else if (v1->is_constant_oop()) {
2273 assert(v2->is_constant_oop(), "");
2274 assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), "");
2275 } else {
2276 ShouldNotReachHere();
2277 }
2278 }
2279
2280 void assert_equal(MonitorValue* m1, MonitorValue* m2) {
2281 assert_equal(m1->owner(), m2->owner());
2282 assert_equal(m1->basic_lock(), m2->basic_lock());
2283 }
2284
2285 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) {
2286 assert(d1->scope() == d2->scope(), "not equal");
2287 assert(d1->bci() == d2->bci(), "not equal");
2288
2289 if (d1->locals() != NULL) {
2290 assert(d1->locals() != NULL && d2->locals() != NULL, "not equal");
2291 assert(d1->locals()->length() == d2->locals()->length(), "not equal");
2292 for (int i = 0; i < d1->locals()->length(); i++) {
2293 assert_equal(d1->locals()->at(i), d2->locals()->at(i));
2294 }
2295 } else {
2296 assert(d1->locals() == NULL && d2->locals() == NULL, "not equal");
2297 }
2298
2299 if (d1->expressions() != NULL) {
2300 assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal");
2301 assert(d1->expressions()->length() == d2->expressions()->length(), "not equal");
2302 for (int i = 0; i < d1->expressions()->length(); i++) {
2303 assert_equal(d1->expressions()->at(i), d2->expressions()->at(i));
2304 }
2305 } else {
2306 assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal");
2307 }
2308
2309 if (d1->monitors() != NULL) {
2310 assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal");
2311 assert(d1->monitors()->length() == d2->monitors()->length(), "not equal");
2312 for (int i = 0; i < d1->monitors()->length(); i++) {
2313 assert_equal(d1->monitors()->at(i), d2->monitors()->at(i));
2314 }
2315 } else {
2316 assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal");
2317 }
2318
2319 if (d1->caller() != NULL) {
2320 assert(d1->caller() != NULL && d2->caller() != NULL, "not equal");
2321 assert_equal(d1->caller(), d2->caller());
2322 } else {
2323 assert(d1->caller() == NULL && d2->caller() == NULL, "not equal");
2324 }
2325 }
2326
2327 void check_stack_depth(CodeEmitInfo* info, int stack_end) {
2328 if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
2329 Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
2330 switch (code) {
2331 case Bytecodes::_ifnull : // fall through
2332 case Bytecodes::_ifnonnull : // fall through
2333 case Bytecodes::_ifeq : // fall through
2334 case Bytecodes::_ifne : // fall through
2335 case Bytecodes::_iflt : // fall through
2336 case Bytecodes::_ifge : // fall through
2337 case Bytecodes::_ifgt : // fall through
2338 case Bytecodes::_ifle : // fall through
2339 case Bytecodes::_if_icmpeq : // fall through
2340 case Bytecodes::_if_icmpne : // fall through
2341 case Bytecodes::_if_icmplt : // fall through
2342 case Bytecodes::_if_icmpge : // fall through
2343 case Bytecodes::_if_icmpgt : // fall through
2344 case Bytecodes::_if_icmple : // fall through
2345 case Bytecodes::_if_acmpeq : // fall through
2346 case Bytecodes::_if_acmpne :
2347 assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
2348 break;
2349 }
2350 }
2351 }
2352
2353 #endif // ASSERT
2354
2355
2356 IntervalWalker* LinearScan::init_compute_oop_maps() {
2357 // setup lists of potential oops for walking
2358 Interval* oop_intervals;
2359 Interval* non_oop_intervals;
2360
2361 create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL);
2362
2363 // intervals that have no oops inside need not to be processed
2364 // to ensure a walking until the last instruction id, add a dummy interval
2365 // with a high operation id
2366 non_oop_intervals = new Interval(any_reg);
2367 non_oop_intervals->add_range(max_jint - 2, max_jint - 1);
2368
2369 return new IntervalWalker(this, oop_intervals, non_oop_intervals);
2370 }
2371
2372
2373 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
2374 TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id()));
2375
2376 // walk before the current operation -> intervals that start at
2377 // the operation (= output operands of the operation) are not
2378 // included in the oop map
2379 iw->walk_before(op->id());
2380
2381 int frame_size = frame_map()->framesize();
2382 int arg_count = frame_map()->oop_map_arg_count();
2383 OopMap* map = new OopMap(frame_size, arg_count);
2384
2385 // Iterate through active intervals
2386 for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
2387 int assigned_reg = interval->assigned_reg();
2388
2389 assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
2390 assert(interval->assigned_regHi() == any_reg, "oop must be single word");
2391 assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found");
2392
2393 // Check if this range covers the instruction. Intervals that
2394 // start or end at the current operation are not included in the
2395 // oop map, except in the case of patching moves. For patching
2396 // moves, any intervals which end at this instruction are included
2397 // in the oop map since we may safepoint while doing the patch
2398 // before we've consumed the inputs.
2399 if (op->is_patching() || op->id() < interval->current_to()) {
2400
2401 // caller-save registers must not be included into oop-maps at calls
2402 assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
2403
2404 VMReg name = vm_reg_for_interval(interval);
2405 set_oop(map, name);
2406
2407 // Spill optimization: when the stack value is guaranteed to be always correct,
2408 // then it must be added to the oop map even if the interval is currently in a register
2409 if (interval->always_in_memory() &&
2410 op->id() > interval->spill_definition_pos() &&
2411 interval->assigned_reg() != interval->canonical_spill_slot()) {
2412 assert(interval->spill_definition_pos() > 0, "position not set correctly");
2413 assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned");
2414 assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
2415
2416 set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
2417 }
2418 }
2419 }
2420
2421 // add oops from lock stack
2422 assert(info->stack() != NULL, "CodeEmitInfo must always have a stack");
2423 int locks_count = info->stack()->total_locks_size();
2424 for (int i = 0; i < locks_count; i++) {
2425 set_oop(map, frame_map()->monitor_object_regname(i));
2426 }
2427
2428 return map;
2429 }
2430
2431
2432 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
2433 assert(visitor.info_count() > 0, "no oop map needed");
2434
2435 // compute oop_map only for first CodeEmitInfo
2436 // because it is (in most cases) equal for all other infos of the same operation
2437 CodeEmitInfo* first_info = visitor.info_at(0);
2438 OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call());
2439
2440 for (int i = 0; i < visitor.info_count(); i++) {
2441 CodeEmitInfo* info = visitor.info_at(i);
2442 OopMap* oop_map = first_oop_map;
2443
2444 // compute worst case interpreter size in case of a deoptimization
2445 _compilation->update_interpreter_frame_size(info->interpreter_frame_size());
2446
2447 if (info->stack()->locks_size() != first_info->stack()->locks_size()) {
2448 // this info has a different number of locks then the precomputed oop map
2449 // (possible for lock and unlock instructions) -> compute oop map with
2450 // correct lock information
2451 oop_map = compute_oop_map(iw, op, info, visitor.has_call());
2452 }
2453
2454 if (info->_oop_map == NULL) {
2455 info->_oop_map = oop_map;
2456 } else {
2457 // a CodeEmitInfo can not be shared between different LIR-instructions
2458 // because interval splitting can occur anywhere between two instructions
2459 // and so the oop maps must be different
2460 // -> check if the already set oop_map is exactly the one calculated for this operation
2461 assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
2462 }
2463 }
2464 }
2465
2466
2467 // frequently used constants
2468 // Allocate them with new so they are never destroyed (otherwise, a
2469 // forced exit could destroy these objects while they are still in
2470 // use).
2471 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL);
2472 ConstantIntValue* LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1);
2473 ConstantIntValue* LinearScan::_int_0_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(0);
2474 ConstantIntValue* LinearScan::_int_1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1);
2475 ConstantIntValue* LinearScan::_int_2_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2);
2476 LocationValue* _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location());
2477
2478 void LinearScan::init_compute_debug_info() {
2479 // cache for frequently used scope values
2480 // (cpu registers and stack slots)
2481 _scope_value_cache = ScopeValueArray((LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2, NULL);
2482 }
2483
2484 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) {
2485 Location loc;
2486 if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) {
2487 bailout("too large frame");
2488 }
2489 ScopeValue* object_scope_value = new LocationValue(loc);
2490
2491 if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) {
2492 bailout("too large frame");
2493 }
2494 return new MonitorValue(object_scope_value, loc);
2495 }
2496
2497 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) {
2498 Location loc;
2499 if (!frame_map()->locations_for_slot(name, loc_type, &loc)) {
2500 bailout("too large frame");
2501 }
2502 return new LocationValue(loc);
2503 }
2504
2505
2506 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2507 assert(opr->is_constant(), "should not be called otherwise");
2508
2509 LIR_Const* c = opr->as_constant_ptr();
2510 BasicType t = c->type();
2511 switch (t) {
2512 case T_OBJECT: {
2513 jobject value = c->as_jobject();
2514 if (value == NULL) {
2515 scope_values->append(_oop_null_scope_value);
2516 } else {
2517 scope_values->append(new ConstantOopWriteValue(c->as_jobject()));
2518 }
2519 return 1;
2520 }
2521
2522 case T_INT: // fall through
2523 case T_FLOAT: {
2524 int value = c->as_jint_bits();
2525 switch (value) {
2526 case -1: scope_values->append(_int_m1_scope_value); break;
2527 case 0: scope_values->append(_int_0_scope_value); break;
2528 case 1: scope_values->append(_int_1_scope_value); break;
2529 case 2: scope_values->append(_int_2_scope_value); break;
2530 default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break;
2531 }
2532 return 1;
2533 }
2534
2535 case T_LONG: // fall through
2536 case T_DOUBLE: {
2537 #ifdef _LP64
2538 scope_values->append(_int_0_scope_value);
2539 scope_values->append(new ConstantLongValue(c->as_jlong_bits()));
2540 #else
2541 if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) {
2542 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2543 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2544 } else {
2545 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2546 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2547 }
2548 #endif
2549 return 2;
2550 }
2551
2552 case T_ADDRESS: {
2553 #ifdef _LP64
2554 scope_values->append(new ConstantLongValue(c->as_jint()));
2555 #else
2556 scope_values->append(new ConstantIntValue(c->as_jint()));
2557 #endif
2558 return 1;
2559 }
2560
2561 default:
2562 ShouldNotReachHere();
2563 return -1;
2564 }
2565 }
2566
2567 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2568 if (opr->is_single_stack()) {
2569 int stack_idx = opr->single_stack_ix();
2570 bool is_oop = opr->is_oop_register();
2571 int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0);
2572
2573 ScopeValue* sv = _scope_value_cache.at(cache_idx);
2574 if (sv == NULL) {
2575 Location::Type loc_type = is_oop ? Location::oop : Location::normal;
2576 sv = location_for_name(stack_idx, loc_type);
2577 _scope_value_cache.at_put(cache_idx, sv);
2578 }
2579
2580 // check if cached value is correct
2581 DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
2582
2583 scope_values->append(sv);
2584 return 1;
2585
2586 } else if (opr->is_single_cpu()) {
2587 bool is_oop = opr->is_oop_register();
2588 int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0);
2589 Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long);
2590
2591 ScopeValue* sv = _scope_value_cache.at(cache_idx);
2592 if (sv == NULL) {
2593 Location::Type loc_type = is_oop ? Location::oop : int_loc_type;
2594 VMReg rname = frame_map()->regname(opr);
2595 sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2596 _scope_value_cache.at_put(cache_idx, sv);
2597 }
2598
2599 // check if cached value is correct
2600 DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2601
2602 scope_values->append(sv);
2603 return 1;
2604
2605 #ifdef X86
2606 } else if (opr->is_single_xmm()) {
2607 VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
2608 LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2609
2610 scope_values->append(sv);
2611 return 1;
2612 #endif
2613
2614 } else if (opr->is_single_fpu()) {
2615 #ifdef X86
2616 // the exact location of fpu stack values is only known
2617 // during fpu stack allocation, so the stack allocator object
2618 // must be present
2619 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2620 assert(_fpu_stack_allocator != NULL, "must be present");
2621 opr = _fpu_stack_allocator->to_fpu_stack(opr);
2622 #endif
2623
2624 Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2625 VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2626 #ifndef __SOFTFP__
2627 #ifndef VM_LITTLE_ENDIAN
2628 if (! float_saved_as_double) {
2629 // On big endian system, we may have an issue if float registers use only
2630 // the low half of the (same) double registers.
2631 // Both the float and the double could have the same regnr but would correspond
2632 // to two different addresses once saved.
2633
2634 // get next safely (no assertion checks)
2635 VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2636 if (next->is_reg() &&
2637 (next->as_FloatRegister() == rname->as_FloatRegister())) {
2638 // the back-end does use the same numbering for the double and the float
2639 rname = next; // VMReg for the low bits, e.g. the real VMReg for the float
2640 }
2641 }
2642 #endif
2643 #endif
2644 LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2645
2646 scope_values->append(sv);
2647 return 1;
2648
2649 } else {
2650 // double-size operands
2651
2652 ScopeValue* first;
2653 ScopeValue* second;
2654
2655 if (opr->is_double_stack()) {
2656 #ifdef _LP64
2657 Location loc1;
2658 Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2659 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
2660 bailout("too large frame");
2661 }
2662 // Does this reverse on x86 vs. sparc?
2663 first = new LocationValue(loc1);
2664 second = _int_0_scope_value;
2665 #else
2666 Location loc1, loc2;
2667 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
2668 bailout("too large frame");
2669 }
2670 first = new LocationValue(loc1);
2671 second = new LocationValue(loc2);
2672 #endif // _LP64
2673
2674 } else if (opr->is_double_cpu()) {
2675 #ifdef _LP64
2676 VMReg rname_first = opr->as_register_lo()->as_VMReg();
2677 first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
2678 second = _int_0_scope_value;
2679 #else
2680 VMReg rname_first = opr->as_register_lo()->as_VMReg();
2681 VMReg rname_second = opr->as_register_hi()->as_VMReg();
2682
2683 if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) {
2684 // lo/hi and swapped relative to first and second, so swap them
2685 VMReg tmp = rname_first;
2686 rname_first = rname_second;
2687 rname_second = tmp;
2688 }
2689
2690 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2691 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2692 #endif //_LP64
2693
2694
2695 #ifdef X86
2696 } else if (opr->is_double_xmm()) {
2697 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
2698 VMReg rname_first = opr->as_xmm_double_reg()->as_VMReg();
2699 # ifdef _LP64
2700 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2701 second = _int_0_scope_value;
2702 # else
2703 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2704 // %%% This is probably a waste but we'll keep things as they were for now
2705 if (true) {
2706 VMReg rname_second = rname_first->next();
2707 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2708 }
2709 # endif
2710 #endif
2711
2712 } else if (opr->is_double_fpu()) {
2713 // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2714 // the double as float registers in the native ordering. On X86,
2715 // fpu_regnrLo is a FPU stack slot whose VMReg represents
2716 // the low-order word of the double and fpu_regnrLo + 1 is the
2717 // name for the other half. *first and *second must represent the
2718 // least and most significant words, respectively.
2719
2720 #ifdef X86
2721 // the exact location of fpu stack values is only known
2722 // during fpu stack allocation, so the stack allocator object
2723 // must be present
2724 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2725 assert(_fpu_stack_allocator != NULL, "must be present");
2726 opr = _fpu_stack_allocator->to_fpu_stack(opr);
2727
2728 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2729 #endif
2730 #ifdef SPARC
2731 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
2732 #endif
2733 #ifdef ARM32
2734 assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2735 #endif
2736 #ifdef PPC
2737 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2738 #endif
2739
2740 #ifdef VM_LITTLE_ENDIAN
2741 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2742 #else
2743 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2744 #endif
2745
2746 #ifdef _LP64
2747 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2748 second = _int_0_scope_value;
2749 #else
2750 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2751 // %%% This is probably a waste but we'll keep things as they were for now
2752 if (true) {
2753 VMReg rname_second = rname_first->next();
2754 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2755 }
2756 #endif
2757
2758 } else {
2759 ShouldNotReachHere();
2760 first = NULL;
2761 second = NULL;
2762 }
2763
2764 assert(first != NULL && second != NULL, "must be set");
2765 // The convention the interpreter uses is that the second local
2766 // holds the first raw word of the native double representation.
2767 // This is actually reasonable, since locals and stack arrays
2768 // grow downwards in all implementations.
2769 // (If, on some machine, the interpreter's Java locals or stack
2770 // were to grow upwards, the embedded doubles would be word-swapped.)
2771 scope_values->append(second);
2772 scope_values->append(first);
2773 return 2;
2774 }
2775 }
2776
2777
2778 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
2779 if (value != NULL) {
2780 LIR_Opr opr = value->operand();
2781 Constant* con = value->as_Constant();
2782
2783 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
2784 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
2785
2786 if (con != NULL && !con->is_pinned() && !opr->is_constant()) {
2787 // Unpinned constants may have a virtual operand for a part of the lifetime
2788 // or may be illegal when it was optimized away,
2789 // so always use a constant operand
2790 opr = LIR_OprFact::value_type(con->type());
2791 }
2792 assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here");
2793
2794 if (opr->is_virtual()) {
2795 LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode;
2796
2797 BlockBegin* block = block_of_op_with_id(op_id);
2798 if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) {
2799 // generating debug information for the last instruction of a block.
2800 // if this instruction is a branch, spill moves are inserted before this branch
2801 // and so the wrong operand would be returned (spill moves at block boundaries are not
2802 // considered in the live ranges of intervals)
2803 // Solution: use the first op_id of the branch target block instead.
2804 if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) {
2805 if (block->live_out().at(opr->vreg_number())) {
2806 op_id = block->sux_at(0)->first_lir_instruction_id();
2807 mode = LIR_OpVisitState::outputMode;
2808 }
2809 }
2810 }
2811
2812 // Get current location of operand
2813 // The operand must be live because debug information is considered when building the intervals
2814 // if the interval is not live, color_lir_opr will cause an assertion failure
2815 opr = color_lir_opr(opr, op_id, mode);
2816 assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
2817
2818 // Append to ScopeValue array
2819 return append_scope_value_for_operand(opr, scope_values);
2820
2821 } else {
2822 assert(value->as_Constant() != NULL, "all other instructions have only virtual operands");
2823 assert(opr->is_constant(), "operand must be constant");
2824
2825 return append_scope_value_for_constant(opr, scope_values);
2826 }
2827 } else {
2828 // append a dummy value because real value not needed
2829 scope_values->append(_illegal_value);
2830 return 1;
2831 }
2832 }
2833
2834
2835 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
2836 IRScopeDebugInfo* caller_debug_info = NULL;
2837
2838 ValueStack* caller_state = cur_state->caller_state();
2839 if (caller_state != NULL) {
2840 // process recursively to compute outermost scope first
2841 caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
2842 }
2843
2844 // initialize these to null.
2845 // If we don't need deopt info or there are no locals, expressions or monitors,
2846 // then these get recorded as no information and avoids the allocation of 0 length arrays.
2847 GrowableArray<ScopeValue*>* locals = NULL;
2848 GrowableArray<ScopeValue*>* expressions = NULL;
2849 GrowableArray<MonitorValue*>* monitors = NULL;
2850
2851 // describe local variable values
2852 int nof_locals = cur_state->locals_size();
2853 if (nof_locals > 0) {
2854 locals = new GrowableArray<ScopeValue*>(nof_locals);
2855
2856 int pos = 0;
2857 while (pos < nof_locals) {
2858 assert(pos < cur_state->locals_size(), "why not?");
2859
2860 Value local = cur_state->local_at(pos);
2861 pos += append_scope_value(op_id, local, locals);
2862
2863 assert(locals->length() == pos, "must match");
2864 }
2865 assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals");
2866 assert(locals->length() == cur_state->locals_size(), "wrong number of locals");
2867 } else if (cur_scope->method()->max_locals() > 0) {
2868 assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be");
2869 nof_locals = cur_scope->method()->max_locals();
2870 locals = new GrowableArray<ScopeValue*>(nof_locals);
2871 for(int i = 0; i < nof_locals; i++) {
2872 locals->append(_illegal_value);
2873 }
2874 }
2875
2876 // describe expression stack
2877 int nof_stack = cur_state->stack_size();
2878 if (nof_stack > 0) {
2879 expressions = new GrowableArray<ScopeValue*>(nof_stack);
2880
2881 int pos = 0;
2882 while (pos < nof_stack) {
2883 Value expression = cur_state->stack_at_inc(pos);
2884 append_scope_value(op_id, expression, expressions);
2885
2886 assert(expressions->length() == pos, "must match");
2887 }
2888 assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries");
2889 }
2890
2891 // describe monitors
2892 int nof_locks = cur_state->locks_size();
2893 if (nof_locks > 0) {
2894 int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0;
2895 monitors = new GrowableArray<MonitorValue*>(nof_locks);
2896 for (int i = 0; i < nof_locks; i++) {
2897 monitors->append(location_for_monitor_index(lock_offset + i));
2898 }
2899 }
2900
2901 return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info);
2902 }
2903
2904
2905 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) {
2906 TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id));
2907
2908 IRScope* innermost_scope = info->scope();
2909 ValueStack* innermost_state = info->stack();
2910
2911 assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?");
2912
2913 DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size()));
2914
2915 if (info->_scope_debug_info == NULL) {
2916 // compute debug information
2917 info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
2918 } else {
2919 // debug information already set. Check that it is correct from the current point of view
2920 DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
2921 }
2922 }
2923
2924
2925 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
2926 LIR_OpVisitState visitor;
2927 int num_inst = instructions->length();
2928 bool has_dead = false;
2929
2930 for (int j = 0; j < num_inst; j++) {
2931 LIR_Op* op = instructions->at(j);
2932 if (op == NULL) { // this can happen when spill-moves are removed in eliminate_spill_moves
2933 has_dead = true;
2934 continue;
2935 }
2936 int op_id = op->id();
2937
2938 // visit instruction to get list of operands
2939 visitor.visit(op);
2940
2941 // iterate all modes of the visitor and process all virtual operands
2942 for_each_visitor_mode(mode) {
2943 int n = visitor.opr_count(mode);
2944 for (int k = 0; k < n; k++) {
2945 LIR_Opr opr = visitor.opr_at(mode, k);
2946 if (opr->is_virtual_register()) {
2947 visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode));
2948 }
2949 }
2950 }
2951
2952 if (visitor.info_count() > 0) {
2953 // exception handling
2954 if (compilation()->has_exception_handlers()) {
2955 XHandlers* xhandlers = visitor.all_xhandler();
2956 int n = xhandlers->length();
2957 for (int k = 0; k < n; k++) {
2958 XHandler* handler = xhandlers->handler_at(k);
2959 if (handler->entry_code() != NULL) {
2960 assign_reg_num(handler->entry_code()->instructions_list(), NULL);
2961 }
2962 }
2963 } else {
2964 assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2965 }
2966
2967 // compute oop map
2968 assert(iw != NULL, "needed for compute_oop_map");
2969 compute_oop_map(iw, visitor, op);
2970
2971 // compute debug information
2972 if (!use_fpu_stack_allocation()) {
2973 // compute debug information if fpu stack allocation is not needed.
2974 // when fpu stack allocation is needed, the debug information can not
2975 // be computed here because the exact location of fpu operands is not known
2976 // -> debug information is created inside the fpu stack allocator
2977 int n = visitor.info_count();
2978 for (int k = 0; k < n; k++) {
2979 compute_debug_info(visitor.info_at(k), op_id);
2980 }
2981 }
2982 }
2983
2984 #ifdef ASSERT
2985 // make sure we haven't made the op invalid.
2986 op->verify();
2987 #endif
2988
2989 // remove useless moves
2990 if (op->code() == lir_move) {
2991 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
2992 LIR_Op1* move = (LIR_Op1*)op;
2993 LIR_Opr src = move->in_opr();
2994 LIR_Opr dst = move->result_opr();
2995 if (dst == src ||
2996 !dst->is_pointer() && !src->is_pointer() &&
2997 src->is_same_register(dst)) {
2998 instructions->at_put(j, NULL);
2999 has_dead = true;
3000 }
3001 }
3002 }
3003
3004 if (has_dead) {
3005 // iterate all instructions of the block and remove all null-values.
3006 int insert_point = 0;
3007 for (int j = 0; j < num_inst; j++) {
3008 LIR_Op* op = instructions->at(j);
3009 if (op != NULL) {
3010 if (insert_point != j) {
3011 instructions->at_put(insert_point, op);
3012 }
3013 insert_point++;
3014 }
3015 }
3016 instructions->truncate(insert_point);
3017 }
3018 }
3019
3020 void LinearScan::assign_reg_num() {
3021 TIME_LINEAR_SCAN(timer_assign_reg_num);
3022
3023 init_compute_debug_info();
3024 IntervalWalker* iw = init_compute_oop_maps();
3025
3026 int num_blocks = block_count();
3027 for (int i = 0; i < num_blocks; i++) {
3028 BlockBegin* block = block_at(i);
3029 assign_reg_num(block->lir()->instructions_list(), iw);
3030 }
3031 }
3032
3033
3034 void LinearScan::do_linear_scan() {
3035 NOT_PRODUCT(_total_timer.begin_method());
3036
3037 number_instructions();
3038
3039 NOT_PRODUCT(print_lir(1, "Before Register Allocation"));
3040
3041 compute_local_live_sets();
3042 compute_global_live_sets();
3043 CHECK_BAILOUT();
3044
3045 build_intervals();
3046 CHECK_BAILOUT();
3047 sort_intervals_before_allocation();
3048
3049 NOT_PRODUCT(print_intervals("Before Register Allocation"));
3050 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
3051
3052 allocate_registers();
3053 CHECK_BAILOUT();
3054
3055 resolve_data_flow();
3056 if (compilation()->has_exception_handlers()) {
3057 resolve_exception_handlers();
3058 }
3059 // fill in number of spill slots into frame_map
3060 propagate_spill_slots();
3061 CHECK_BAILOUT();
3062
3063 NOT_PRODUCT(print_intervals("After Register Allocation"));
3064 NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
3065
3066 sort_intervals_after_allocation();
3067
3068 DEBUG_ONLY(verify());
3069
3070 eliminate_spill_moves();
3071 assign_reg_num();
3072 CHECK_BAILOUT();
3073
3074 NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
3075 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
3076
3077 { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
3078
3079 if (use_fpu_stack_allocation()) {
3080 allocate_fpu_stack(); // Only has effect on Intel
3081 NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
3082 }
3083 }
3084
3085 { TIME_LINEAR_SCAN(timer_optimize_lir);
3086
3087 EdgeMoveOptimizer::optimize(ir()->code());
3088 ControlFlowOptimizer::optimize(ir()->code());
3089 // check that cfg is still correct after optimizations
3090 ir()->verify();
3091 }
3092
3093 NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
3094 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
3095 NOT_PRODUCT(_total_timer.end_method(this));
3096 }
3097
3098
3099 // ********** Printing functions
3100
3101 #ifndef PRODUCT
3102
3103 void LinearScan::print_timers(double total) {
3104 _total_timer.print(total);
3105 }
3106
3107 void LinearScan::print_statistics() {
3108 _stat_before_alloc.print("before allocation");
3109 _stat_after_asign.print("after assignment of register");
3110 _stat_final.print("after optimization");
3111 }
3112
3113 void LinearScan::print_bitmap(BitMap& b) {
3114 for (unsigned int i = 0; i < b.size(); i++) {
3115 if (b.at(i)) tty->print("%d ", i);
3116 }
3117 tty->cr();
3118 }
3119
3120 void LinearScan::print_intervals(const char* label) {
3121 if (TraceLinearScanLevel >= 1) {
3122 int i;
3123 tty->cr();
3124 tty->print_cr("%s", label);
3125
3126 for (i = 0; i < interval_count(); i++) {
3127 Interval* interval = interval_at(i);
3128 if (interval != NULL) {
3129 interval->print();
3130 }
3131 }
3132
3133 tty->cr();
3134 tty->print_cr("--- Basic Blocks ---");
3135 for (i = 0; i < block_count(); i++) {
3136 BlockBegin* block = block_at(i);
3137 tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
3138 }
3139 tty->cr();
3140 tty->cr();
3141 }
3142
3143 if (PrintCFGToFile) {
3144 CFGPrinter::print_intervals(&_intervals, label);
3145 }
3146 }
3147
3148 void LinearScan::print_lir(int level, const char* label, bool hir_valid) {
3149 if (TraceLinearScanLevel >= level) {
3150 tty->cr();
3151 tty->print_cr("%s", label);
3152 print_LIR(ir()->linear_scan_order());
3153 tty->cr();
3154 }
3155
3156 if (level == 1 && PrintCFGToFile) {
3157 CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true);
3158 }
3159 }
3160
3161 #endif //PRODUCT
3162
3163
3164 // ********** verification functions for allocation
3165 // (check that all intervals have a correct register and that no registers are overwritten)
3166 #ifdef ASSERT
3167
3168 void LinearScan::verify() {
3169 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
3170 verify_intervals();
3171
3172 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
3173 verify_no_oops_in_fixed_intervals();
3174
3175 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
3176 verify_constants();
3177
3178 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
3179 verify_registers();
3180
3181 TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
3182 }
3183
3184 void LinearScan::verify_intervals() {
3185 int len = interval_count();
3186 bool has_error = false;
3187
3188 for (int i = 0; i < len; i++) {
3189 Interval* i1 = interval_at(i);
3190 if (i1 == NULL) continue;
3191
3192 i1->check_split_children();
3193
3194 if (i1->reg_num() != i) {
3195 tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
3196 has_error = true;
3197 }
3198
3199 if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) {
3200 tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr();
3201 has_error = true;
3202 }
3203
3204 if (i1->assigned_reg() == any_reg) {
3205 tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr();
3206 has_error = true;
3207 }
3208
3209 if (i1->assigned_reg() == i1->assigned_regHi()) {
3210 tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
3211 has_error = true;
3212 }
3213
3214 if (!is_processed_reg_num(i1->assigned_reg())) {
3215 tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr();
3216 has_error = true;
3217 }
3218
3219 if (i1->first() == Range::end()) {
3220 tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr();
3221 has_error = true;
3222 }
3223
3224 for (Range* r = i1->first(); r != Range::end(); r = r->next()) {
3225 if (r->from() >= r->to()) {
3226 tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr();
3227 has_error = true;
3228 }
3229 }
3230
3231 for (int j = i + 1; j < len; j++) {
3232 Interval* i2 = interval_at(j);
3233 if (i2 == NULL) continue;
3234
3235 // special intervals that are created in MoveResolver
3236 // -> ignore them because the range information has no meaning there
3237 if (i1->from() == 1 && i1->to() == 2) continue;
3238 if (i2->from() == 1 && i2->to() == 2) continue;
3239
3240 int r1 = i1->assigned_reg();
3241 int r1Hi = i1->assigned_regHi();
3242 int r2 = i2->assigned_reg();
3243 int r2Hi = i2->assigned_regHi();
3244 if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) {
3245 tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3246 i1->print(); tty->cr();
3247 i2->print(); tty->cr();
3248 has_error = true;
3249 }
3250 }
3251 }
3252
3253 assert(has_error == false, "register allocation invalid");
3254 }
3255
3256
3257 void LinearScan::verify_no_oops_in_fixed_intervals() {
3258 Interval* fixed_intervals;
3259 Interval* other_intervals;
3260 create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
3261
3262 // to ensure a walking until the last instruction id, add a dummy interval
3263 // with a high operation id
3264 other_intervals = new Interval(any_reg);
3265 other_intervals->add_range(max_jint - 2, max_jint - 1);
3266 IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals);
3267
3268 LIR_OpVisitState visitor;
3269 for (int i = 0; i < block_count(); i++) {
3270 BlockBegin* block = block_at(i);
3271
3272 LIR_OpList* instructions = block->lir()->instructions_list();
3273
3274 for (int j = 0; j < instructions->length(); j++) {
3275 LIR_Op* op = instructions->at(j);
3276 int op_id = op->id();
3277
3278 visitor.visit(op);
3279
3280 if (visitor.info_count() > 0) {
3281 iw->walk_before(op->id());
3282 bool check_live = true;
3283 if (op->code() == lir_move) {
3284 LIR_Op1* move = (LIR_Op1*)op;
3285 check_live = (move->patch_code() == lir_patch_none);
3286 }
3287 LIR_OpBranch* branch = op->as_OpBranch();
3288 if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) {
3289 // Don't bother checking the stub in this case since the
3290 // exception stub will never return to normal control flow.
3291 check_live = false;
3292 }
3293
3294 // Make sure none of the fixed registers is live across an
3295 // oopmap since we can't handle that correctly.
3296 if (check_live) {
3297 for (Interval* interval = iw->active_first(fixedKind);
3298 interval != Interval::end();
3299 interval = interval->next()) {
3300 if (interval->current_to() > op->id() + 1) {
3301 // This interval is live out of this op so make sure
3302 // that this interval represents some value that's
3303 // referenced by this op either as an input or output.
3304 bool ok = false;
3305 for_each_visitor_mode(mode) {
3306 int n = visitor.opr_count(mode);
3307 for (int k = 0; k < n; k++) {
3308 LIR_Opr opr = visitor.opr_at(mode, k);
3309 if (opr->is_fixed_cpu()) {
3310 if (interval_at(reg_num(opr)) == interval) {
3311 ok = true;
3312 break;
3313 }
3314 int hi = reg_numHi(opr);
3315 if (hi != -1 && interval_at(hi) == interval) {
3316 ok = true;
3317 break;
3318 }
3319 }
3320 }
3321 }
3322 assert(ok, "fixed intervals should never be live across an oopmap point");
3323 }
3324 }
3325 }
3326 }
3327
3328 // oop-maps at calls do not contain registers, so check is not needed
3329 if (!visitor.has_call()) {
3330
3331 for_each_visitor_mode(mode) {
3332 int n = visitor.opr_count(mode);
3333 for (int k = 0; k < n; k++) {
3334 LIR_Opr opr = visitor.opr_at(mode, k);
3335
3336 if (opr->is_fixed_cpu() && opr->is_oop()) {
3337 // operand is a non-virtual cpu register and contains an oop
3338 TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3339
3340 Interval* interval = interval_at(reg_num(opr));
3341 assert(interval != NULL, "no interval");
3342
3343 if (mode == LIR_OpVisitState::inputMode) {
3344 if (interval->to() >= op_id + 1) {
3345 assert(interval->to() < op_id + 2 ||
3346 interval->has_hole_between(op_id, op_id + 2),
3347 "oop input operand live after instruction");
3348 }
3349 } else if (mode == LIR_OpVisitState::outputMode) {
3350 if (interval->from() <= op_id - 1) {
3351 assert(interval->has_hole_between(op_id - 1, op_id),
3352 "oop input operand live after instruction");
3353 }
3354 }
3355 }
3356 }
3357 }
3358 }
3359 }
3360 }
3361 }
3362
3363
3364 void LinearScan::verify_constants() {
3365 int num_regs = num_virtual_regs();
3366 int size = live_set_size();
3367 int num_blocks = block_count();
3368
3369 for (int i = 0; i < num_blocks; i++) {
3370 BlockBegin* block = block_at(i);
3371 BitMap live_at_edge = block->live_in();
3372
3373 // visit all registers where the live_at_edge bit is set
3374 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
3375 TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
3376
3377 Value value = gen()->instruction_for_vreg(r);
3378
3379 assert(value != NULL, "all intervals live across block boundaries must have Value");
3380 assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
3381 assert(value->operand()->vreg_number() == r, "register number must match");
3382 // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries");
3383 }
3384 }
3385 }
3386
3387
3388 class RegisterVerifier: public StackObj {
3389 private:
3390 LinearScan* _allocator;
3391 BlockList _work_list; // all blocks that must be processed
3392 IntervalsList _saved_states; // saved information of previous check
3393
3394 // simplified access to methods of LinearScan
3395 Compilation* compilation() const { return _allocator->compilation(); }
3396 Interval* interval_at(int reg_num) const { return _allocator->interval_at(reg_num); }
3397 int reg_num(LIR_Opr opr) const { return _allocator->reg_num(opr); }
3398
3399 // currently, only registers are processed
3400 int state_size() { return LinearScan::nof_regs; }
3401
3402 // accessors
3403 IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
3404 void set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
3405 void add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
3406
3407 // helper functions
3408 IntervalList* copy(IntervalList* input_state);
3409 void state_put(IntervalList* input_state, int reg, Interval* interval);
3410 bool check_state(IntervalList* input_state, int reg, Interval* interval);
3411
3412 void process_block(BlockBegin* block);
3413 void process_xhandler(XHandler* xhandler, IntervalList* input_state);
3414 void process_successor(BlockBegin* block, IntervalList* input_state);
3415 void process_operations(LIR_List* ops, IntervalList* input_state);
3416
3417 public:
3418 RegisterVerifier(LinearScan* allocator)
3419 : _allocator(allocator)
3420 , _work_list(16)
3421 , _saved_states(BlockBegin::number_of_blocks(), NULL)
3422 { }
3423
3424 void verify(BlockBegin* start);
3425 };
3426
3427
3428 // entry function from LinearScan that starts the verification
3429 void LinearScan::verify_registers() {
3430 RegisterVerifier verifier(this);
3431 verifier.verify(block_at(0));
3432 }
3433
3434
3435 void RegisterVerifier::verify(BlockBegin* start) {
3436 // setup input registers (method arguments) for first block
3437 IntervalList* input_state = new IntervalList(state_size(), NULL);
3438 CallingConvention* args = compilation()->frame_map()->incoming_arguments();
3439 for (int n = 0; n < args->length(); n++) {
3440 LIR_Opr opr = args->at(n);
3441 if (opr->is_register()) {
3442 Interval* interval = interval_at(reg_num(opr));
3443
3444 if (interval->assigned_reg() < state_size()) {
3445 input_state->at_put(interval->assigned_reg(), interval);
3446 }
3447 if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
3448 input_state->at_put(interval->assigned_regHi(), interval);
3449 }
3450 }
3451 }
3452
3453 set_state_for_block(start, input_state);
3454 add_to_work_list(start);
3455
3456 // main loop for verification
3457 do {
3458 BlockBegin* block = _work_list.at(0);
3459 _work_list.remove_at(0);
3460
3461 process_block(block);
3462 } while (!_work_list.is_empty());
3463 }
3464
3465 void RegisterVerifier::process_block(BlockBegin* block) {
3466 TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id()));
3467
3468 // must copy state because it is modified
3469 IntervalList* input_state = copy(state_for_block(block));
3470
3471 if (TraceLinearScanLevel >= 4) {
3472 tty->print_cr("Input-State of intervals:");
3473 tty->print(" ");
3474 for (int i = 0; i < state_size(); i++) {
3475 if (input_state->at(i) != NULL) {
3476 tty->print(" %4d", input_state->at(i)->reg_num());
3477 } else {
3478 tty->print(" __");
3479 }
3480 }
3481 tty->cr();
3482 tty->cr();
3483 }
3484
3485 // process all operations of the block
3486 process_operations(block->lir(), input_state);
3487
3488 // iterate all successors
3489 for (int i = 0; i < block->number_of_sux(); i++) {
3490 process_successor(block->sux_at(i), input_state);
3491 }
3492 }
3493
3494 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) {
3495 TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
3496
3497 // must copy state because it is modified
3498 input_state = copy(input_state);
3499
3500 if (xhandler->entry_code() != NULL) {
3501 process_operations(xhandler->entry_code(), input_state);
3502 }
3503 process_successor(xhandler->entry_block(), input_state);
3504 }
3505
3506 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) {
3507 IntervalList* saved_state = state_for_block(block);
3508
3509 if (saved_state != NULL) {
3510 // this block was already processed before.
3511 // check if new input_state is consistent with saved_state
3512
3513 bool saved_state_correct = true;
3514 for (int i = 0; i < state_size(); i++) {
3515 if (input_state->at(i) != saved_state->at(i)) {
3516 // current input_state and previous saved_state assume a different
3517 // interval in this register -> assume that this register is invalid
3518 if (saved_state->at(i) != NULL) {
3519 // invalidate old calculation only if it assumed that
3520 // register was valid. when the register was already invalid,
3521 // then the old calculation was correct.
3522 saved_state_correct = false;
3523 saved_state->at_put(i, NULL);
3524
3525 TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
3526 }
3527 }
3528 }
3529
3530 if (saved_state_correct) {
3531 // already processed block with correct input_state
3532 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
3533 } else {
3534 // must re-visit this block
3535 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
3536 add_to_work_list(block);
3537 }
3538
3539 } else {
3540 // block was not processed before, so set initial input_state
3541 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
3542
3543 set_state_for_block(block, copy(input_state));
3544 add_to_work_list(block);
3545 }
3546 }
3547
3548
3549 IntervalList* RegisterVerifier::copy(IntervalList* input_state) {
3550 IntervalList* copy_state = new IntervalList(input_state->length());
3551 copy_state->push_all(input_state);
3552 return copy_state;
3553 }
3554
3555 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) {
3556 if (reg != LinearScan::any_reg && reg < state_size()) {
3557 if (interval != NULL) {
3558 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = %d", reg, interval->reg_num()));
3559 } else if (input_state->at(reg) != NULL) {
3560 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = NULL", reg));
3561 }
3562
3563 input_state->at_put(reg, interval);
3564 }
3565 }
3566
3567 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) {
3568 if (reg != LinearScan::any_reg && reg < state_size()) {
3569 if (input_state->at(reg) != interval) {
3570 tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
3571 return true;
3572 }
3573 }
3574 return false;
3575 }
3576
3577 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) {
3578 // visit all instructions of the block
3579 LIR_OpVisitState visitor;
3580 bool has_error = false;
3581
3582 for (int i = 0; i < ops->length(); i++) {
3583 LIR_Op* op = ops->at(i);
3584 visitor.visit(op);
3585
3586 TRACE_LINEAR_SCAN(4, op->print_on(tty));
3587
3588 // check if input operands are correct
3589 int j;
3590 int n = visitor.opr_count(LIR_OpVisitState::inputMode);
3591 for (j = 0; j < n; j++) {
3592 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j);
3593 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3594 Interval* interval = interval_at(reg_num(opr));
3595 if (op->id() != -1) {
3596 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode);
3597 }
3598
3599 has_error |= check_state(input_state, interval->assigned_reg(), interval->split_parent());
3600 has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
3601
3602 // When an operand is marked with is_last_use, then the fpu stack allocator
3603 // removes the register from the fpu stack -> the register contains no value
3604 if (opr->is_last_use()) {
3605 state_put(input_state, interval->assigned_reg(), NULL);
3606 state_put(input_state, interval->assigned_regHi(), NULL);
3607 }
3608 }
3609 }
3610
3611 // invalidate all caller save registers at calls
3612 if (visitor.has_call()) {
3613 for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
3614 state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
3615 }
3616 for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3617 state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
3618 }
3619
3620 #ifdef X86
3621 int num_caller_save_xmm_regs = FrameMap::nof_caller_save_xmm_regs;
3622 #if _LP64
3623 if (UseAVX < 3) {
3624 num_caller_save_xmm_regs = num_caller_save_xmm_regs / 2;
3625 }
3626 #endif
3627 for (j = 0; j < num_caller_save_xmm_regs; j++) {
3628 state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
3629 }
3630 #endif
3631 }
3632
3633 // process xhandler before output and temp operands
3634 XHandlers* xhandlers = visitor.all_xhandler();
3635 n = xhandlers->length();
3636 for (int k = 0; k < n; k++) {
3637 process_xhandler(xhandlers->handler_at(k), input_state);
3638 }
3639
3640 // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
3641 n = visitor.opr_count(LIR_OpVisitState::tempMode);
3642 for (j = 0; j < n; j++) {
3643 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3644 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3645 Interval* interval = interval_at(reg_num(opr));
3646 if (op->id() != -1) {
3647 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
3648 }
3649
3650 state_put(input_state, interval->assigned_reg(), interval->split_parent());
3651 state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3652 }
3653 }
3654
3655 // set output operands
3656 n = visitor.opr_count(LIR_OpVisitState::outputMode);
3657 for (j = 0; j < n; j++) {
3658 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j);
3659 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3660 Interval* interval = interval_at(reg_num(opr));
3661 if (op->id() != -1) {
3662 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode);
3663 }
3664
3665 state_put(input_state, interval->assigned_reg(), interval->split_parent());
3666 state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3667 }
3668 }
3669 }
3670 assert(has_error == false, "Error in register allocation");
3671 }
3672
3673 #endif // ASSERT
3674
3675
3676
3677 // **** Implementation of MoveResolver ******************************
3678
3679 MoveResolver::MoveResolver(LinearScan* allocator) :
3680 _allocator(allocator),
3681 _multiple_reads_allowed(false),
3682 _mapping_from(8),
3683 _mapping_from_opr(8),
3684 _mapping_to(8),
3685 _insert_list(NULL),
3686 _insert_idx(-1),
3687 _insertion_buffer()
3688 {
3689 for (int i = 0; i < LinearScan::nof_regs; i++) {
3690 _register_blocked[i] = 0;
3691 }
3692 DEBUG_ONLY(check_empty());
3693 }
3694
3695
3696 #ifdef ASSERT
3697
3698 void MoveResolver::check_empty() {
3699 assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
3700 for (int i = 0; i < LinearScan::nof_regs; i++) {
3701 assert(register_blocked(i) == 0, "register map must be empty before and after processing");
3702 }
3703 assert(_multiple_reads_allowed == false, "must have default value");
3704 }
3705
3706 void MoveResolver::verify_before_resolve() {
3707 assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal");
3708 assert(_mapping_from.length() == _mapping_to.length(), "length must be equal");
3709 assert(_insert_list != NULL && _insert_idx != -1, "insert position not set");
3710
3711 int i, j;
3712 if (!_multiple_reads_allowed) {
3713 for (i = 0; i < _mapping_from.length(); i++) {
3714 for (j = i + 1; j < _mapping_from.length(); j++) {
3715 assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
3716 }
3717 }
3718 }
3719
3720 for (i = 0; i < _mapping_to.length(); i++) {
3721 for (j = i + 1; j < _mapping_to.length(); j++) {
3722 assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice");
3723 }
3724 }
3725
3726
3727 BitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
3728 used_regs.clear();
3729 if (!_multiple_reads_allowed) {
3730 for (i = 0; i < _mapping_from.length(); i++) {
3731 Interval* it = _mapping_from.at(i);
3732 if (it != NULL) {
3733 assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice");
3734 used_regs.set_bit(it->assigned_reg());
3735
3736 if (it->assigned_regHi() != LinearScan::any_reg) {
3737 assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
3738 used_regs.set_bit(it->assigned_regHi());
3739 }
3740 }
3741 }
3742 }
3743
3744 used_regs.clear();
3745 for (i = 0; i < _mapping_to.length(); i++) {
3746 Interval* it = _mapping_to.at(i);
3747 assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice");
3748 used_regs.set_bit(it->assigned_reg());
3749
3750 if (it->assigned_regHi() != LinearScan::any_reg) {
3751 assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
3752 used_regs.set_bit(it->assigned_regHi());
3753 }
3754 }
3755
3756 used_regs.clear();
3757 for (i = 0; i < _mapping_from.length(); i++) {
3758 Interval* it = _mapping_from.at(i);
3759 if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) {
3760 used_regs.set_bit(it->assigned_reg());
3761 }
3762 }
3763 for (i = 0; i < _mapping_to.length(); i++) {
3764 Interval* it = _mapping_to.at(i);
3765 assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
3766 }
3767 }
3768
3769 #endif // ASSERT
3770
3771
3772 // mark assigned_reg and assigned_regHi of the interval as blocked
3773 void MoveResolver::block_registers(Interval* it) {
3774 int reg = it->assigned_reg();
3775 if (reg < LinearScan::nof_regs) {
3776 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3777 set_register_blocked(reg, 1);
3778 }
3779 reg = it->assigned_regHi();
3780 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3781 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3782 set_register_blocked(reg, 1);
3783 }
3784 }
3785
3786 // mark assigned_reg and assigned_regHi of the interval as unblocked
3787 void MoveResolver::unblock_registers(Interval* it) {
3788 int reg = it->assigned_reg();
3789 if (reg < LinearScan::nof_regs) {
3790 assert(register_blocked(reg) > 0, "register already marked as unused");
3791 set_register_blocked(reg, -1);
3792 }
3793 reg = it->assigned_regHi();
3794 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3795 assert(register_blocked(reg) > 0, "register already marked as unused");
3796 set_register_blocked(reg, -1);
3797 }
3798 }
3799
3800 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
3801 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) {
3802 int from_reg = -1;
3803 int from_regHi = -1;
3804 if (from != NULL) {
3805 from_reg = from->assigned_reg();
3806 from_regHi = from->assigned_regHi();
3807 }
3808
3809 int reg = to->assigned_reg();
3810 if (reg < LinearScan::nof_regs) {
3811 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3812 return false;
3813 }
3814 }
3815 reg = to->assigned_regHi();
3816 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3817 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3818 return false;
3819 }
3820 }
3821
3822 return true;
3823 }
3824
3825
3826 void MoveResolver::create_insertion_buffer(LIR_List* list) {
3827 assert(!_insertion_buffer.initialized(), "overwriting existing buffer");
3828 _insertion_buffer.init(list);
3829 }
3830
3831 void MoveResolver::append_insertion_buffer() {
3832 if (_insertion_buffer.initialized()) {
3833 _insertion_buffer.lir_list()->append(&_insertion_buffer);
3834 }
3835 assert(!_insertion_buffer.initialized(), "must be uninitialized now");
3836
3837 _insert_list = NULL;
3838 _insert_idx = -1;
3839 }
3840
3841 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) {
3842 assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal");
3843 assert(from_interval->type() == to_interval->type(), "move between different types");
3844 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3845 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3846
3847 LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type());
3848 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3849
3850 if (!_multiple_reads_allowed) {
3851 // the last_use flag is an optimization for FPU stack allocation. When the same
3852 // input interval is used in more than one move, then it is too difficult to determine
3853 // if this move is really the last use.
3854 from_opr = from_opr->make_last_use();
3855 }
3856 _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3857
3858 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3859 }
3860
3861 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) {
3862 assert(from_opr->type() == to_interval->type(), "move between different types");
3863 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3864 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3865
3866 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3867 _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3868
3869 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3870 }
3871
3872
3873 void MoveResolver::resolve_mappings() {
3874 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
3875 DEBUG_ONLY(verify_before_resolve());
3876
3877 // Block all registers that are used as input operands of a move.
3878 // When a register is blocked, no move to this register is emitted.
3879 // This is necessary for detecting cycles in moves.
3880 int i;
3881 for (i = _mapping_from.length() - 1; i >= 0; i--) {
3882 Interval* from_interval = _mapping_from.at(i);
3883 if (from_interval != NULL) {
3884 block_registers(from_interval);
3885 }
3886 }
3887
3888 int spill_candidate = -1;
3889 while (_mapping_from.length() > 0) {
3890 bool processed_interval = false;
3891
3892 for (i = _mapping_from.length() - 1; i >= 0; i--) {
3893 Interval* from_interval = _mapping_from.at(i);
3894 Interval* to_interval = _mapping_to.at(i);
3895
3896 if (save_to_process_move(from_interval, to_interval)) {
3897 // this inverval can be processed because target is free
3898 if (from_interval != NULL) {
3899 insert_move(from_interval, to_interval);
3900 unblock_registers(from_interval);
3901 } else {
3902 insert_move(_mapping_from_opr.at(i), to_interval);
3903 }
3904 _mapping_from.remove_at(i);
3905 _mapping_from_opr.remove_at(i);
3906 _mapping_to.remove_at(i);
3907
3908 processed_interval = true;
3909 } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) {
3910 // this interval cannot be processed now because target is not free
3911 // it starts in a register, so it is a possible candidate for spilling
3912 spill_candidate = i;
3913 }
3914 }
3915
3916 if (!processed_interval) {
3917 // no move could be processed because there is a cycle in the move list
3918 // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
3919 assert(spill_candidate != -1, "no interval in register for spilling found");
3920
3921 // create a new spill interval and assign a stack slot to it
3922 Interval* from_interval = _mapping_from.at(spill_candidate);
3923 Interval* spill_interval = new Interval(-1);
3924 spill_interval->set_type(from_interval->type());
3925
3926 // add a dummy range because real position is difficult to calculate
3927 // Note: this range is a special case when the integrity of the allocation is checked
3928 spill_interval->add_range(1, 2);
3929
3930 // do not allocate a new spill slot for temporary interval, but
3931 // use spill slot assigned to from_interval. Otherwise moves from
3932 // one stack slot to another can happen (not allowed by LIR_Assembler
3933 int spill_slot = from_interval->canonical_spill_slot();
3934 if (spill_slot < 0) {
3935 spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2);
3936 from_interval->set_canonical_spill_slot(spill_slot);
3937 }
3938 spill_interval->assign_reg(spill_slot);
3939 allocator()->append_interval(spill_interval);
3940
3941 TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
3942
3943 // insert a move from register to stack and update the mapping
3944 insert_move(from_interval, spill_interval);
3945 _mapping_from.at_put(spill_candidate, spill_interval);
3946 unblock_registers(from_interval);
3947 }
3948 }
3949
3950 // reset to default value
3951 _multiple_reads_allowed = false;
3952
3953 // check that all intervals have been processed
3954 DEBUG_ONLY(check_empty());
3955 }
3956
3957
3958 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) {
3959 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
3960 assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
3961
3962 create_insertion_buffer(insert_list);
3963 _insert_list = insert_list;
3964 _insert_idx = insert_idx;
3965 }
3966
3967 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) {
3968 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
3969
3970 if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) {
3971 // insert position changed -> resolve current mappings
3972 resolve_mappings();
3973 }
3974
3975 if (insert_list != _insert_list) {
3976 // block changed -> append insertion_buffer because it is
3977 // bound to a specific block and create a new insertion_buffer
3978 append_insertion_buffer();
3979 create_insertion_buffer(insert_list);
3980 }
3981
3982 _insert_list = insert_list;
3983 _insert_idx = insert_idx;
3984 }
3985
3986 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) {
3987 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3988
3989 _mapping_from.append(from_interval);
3990 _mapping_from_opr.append(LIR_OprFact::illegalOpr);
3991 _mapping_to.append(to_interval);
3992 }
3993
3994
3995 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) {
3996 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3997 assert(from_opr->is_constant(), "only for constants");
3998
3999 _mapping_from.append(NULL);
4000 _mapping_from_opr.append(from_opr);
4001 _mapping_to.append(to_interval);
4002 }
4003
4004 void MoveResolver::resolve_and_append_moves() {
4005 if (has_mappings()) {
4006 resolve_mappings();
4007 }
4008 append_insertion_buffer();
4009 }
4010
4011
4012
4013 // **** Implementation of Range *************************************
4014
4015 Range::Range(int from, int to, Range* next) :
4016 _from(from),
4017 _to(to),
4018 _next(next)
4019 {
4020 }
4021
4022 // initialize sentinel
4023 Range* Range::_end = NULL;
4024 void Range::initialize(Arena* arena) {
4025 _end = new (arena) Range(max_jint, max_jint, NULL);
4026 }
4027
4028 int Range::intersects_at(Range* r2) const {
4029 const Range* r1 = this;
4030
4031 assert(r1 != NULL && r2 != NULL, "null ranges not allowed");
4032 assert(r1 != _end && r2 != _end, "empty ranges not allowed");
4033
4034 do {
4035 if (r1->from() < r2->from()) {
4036 if (r1->to() <= r2->from()) {
4037 r1 = r1->next(); if (r1 == _end) return -1;
4038 } else {
4039 return r2->from();
4040 }
4041 } else if (r2->from() < r1->from()) {
4042 if (r2->to() <= r1->from()) {
4043 r2 = r2->next(); if (r2 == _end) return -1;
4044 } else {
4045 return r1->from();
4046 }
4047 } else { // r1->from() == r2->from()
4048 if (r1->from() == r1->to()) {
4049 r1 = r1->next(); if (r1 == _end) return -1;
4050 } else if (r2->from() == r2->to()) {
4051 r2 = r2->next(); if (r2 == _end) return -1;
4052 } else {
4053 return r1->from();
4054 }
4055 }
4056 } while (true);
4057 }
4058
4059 #ifndef PRODUCT
4060 void Range::print(outputStream* out) const {
4061 out->print("[%d, %d[ ", _from, _to);
4062 }
4063 #endif
4064
4065
4066
4067 // **** Implementation of Interval **********************************
4068
4069 // initialize sentinel
4070 Interval* Interval::_end = NULL;
4071 void Interval::initialize(Arena* arena) {
4072 Range::initialize(arena);
4073 _end = new (arena) Interval(-1);
4074 }
4075
4076 Interval::Interval(int reg_num) :
4077 _reg_num(reg_num),
4078 _type(T_ILLEGAL),
4079 _first(Range::end()),
4080 _use_pos_and_kinds(12),
4081 _current(Range::end()),
4082 _next(_end),
4083 _state(invalidState),
4084 _assigned_reg(LinearScan::any_reg),
4085 _assigned_regHi(LinearScan::any_reg),
4086 _cached_to(-1),
4087 _cached_opr(LIR_OprFact::illegalOpr),
4088 _cached_vm_reg(VMRegImpl::Bad()),
4089 _split_children(0),
4090 _canonical_spill_slot(-1),
4091 _insert_move_when_activated(false),
4092 _register_hint(NULL),
4093 _spill_state(noDefinitionFound),
4094 _spill_definition_pos(-1)
4095 {
4096 _split_parent = this;
4097 _current_split_child = this;
4098 }
4099
4100 int Interval::calc_to() {
4101 assert(_first != Range::end(), "interval has no range");
4102
4103 Range* r = _first;
4104 while (r->next() != Range::end()) {
4105 r = r->next();
4106 }
4107 return r->to();
4108 }
4109
4110
4111 #ifdef ASSERT
4112 // consistency check of split-children
4113 void Interval::check_split_children() {
4114 if (_split_children.length() > 0) {
4115 assert(is_split_parent(), "only split parents can have children");
4116
4117 for (int i = 0; i < _split_children.length(); i++) {
4118 Interval* i1 = _split_children.at(i);
4119
4120 assert(i1->split_parent() == this, "not a split child of this interval");
4121 assert(i1->type() == type(), "must be equal for all split children");
4122 assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
4123
4124 for (int j = i + 1; j < _split_children.length(); j++) {
4125 Interval* i2 = _split_children.at(j);
4126
4127 assert(i1->reg_num() != i2->reg_num(), "same register number");
4128
4129 if (i1->from() < i2->from()) {
4130 assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping");
4131 } else {
4132 assert(i2->from() < i1->from(), "intervals start at same op_id");
4133 assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping");
4134 }
4135 }
4136 }
4137 }
4138 }
4139 #endif // ASSERT
4140
4141 Interval* Interval::register_hint(bool search_split_child) const {
4142 if (!search_split_child) {
4143 return _register_hint;
4144 }
4145
4146 if (_register_hint != NULL) {
4147 assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers");
4148
4149 if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
4150 return _register_hint;
4151
4152 } else if (_register_hint->_split_children.length() > 0) {
4153 // search the first split child that has a register assigned
4154 int len = _register_hint->_split_children.length();
4155 for (int i = 0; i < len; i++) {
4156 Interval* cur = _register_hint->_split_children.at(i);
4157
4158 if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) {
4159 return cur;
4160 }
4161 }
4162 }
4163 }
4164
4165 // no hint interval found that has a register assigned
4166 return NULL;
4167 }
4168
4169
4170 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) {
4171 assert(is_split_parent(), "can only be called for split parents");
4172 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4173
4174 Interval* result;
4175 if (_split_children.length() == 0) {
4176 result = this;
4177 } else {
4178 result = NULL;
4179 int len = _split_children.length();
4180
4181 // in outputMode, the end of the interval (op_id == cur->to()) is not valid
4182 int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1);
4183
4184 int i;
4185 for (i = 0; i < len; i++) {
4186 Interval* cur = _split_children.at(i);
4187 if (cur->from() <= op_id && op_id < cur->to() + to_offset) {
4188 if (i > 0) {
4189 // exchange current split child to start of list (faster access for next call)
4190 _split_children.at_put(i, _split_children.at(0));
4191 _split_children.at_put(0, cur);
4192 }
4193
4194 // interval found
4195 result = cur;
4196 break;
4197 }
4198 }
4199
4200 #ifdef ASSERT
4201 for (i = 0; i < len; i++) {
4202 Interval* tmp = _split_children.at(i);
4203 if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) {
4204 tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
4205 result->print();
4206 tmp->print();
4207 assert(false, "two valid result intervals found");
4208 }
4209 }
4210 #endif
4211 }
4212
4213 assert(result != NULL, "no matching interval found");
4214 assert(result->covers(op_id, mode), "op_id not covered by interval");
4215
4216 return result;
4217 }
4218
4219
4220 // returns the last split child that ends before the given op_id
4221 Interval* Interval::split_child_before_op_id(int op_id) {
4222 assert(op_id >= 0, "invalid op_id");
4223
4224 Interval* parent = split_parent();
4225 Interval* result = NULL;
4226
4227 int len = parent->_split_children.length();
4228 assert(len > 0, "no split children available");
4229
4230 for (int i = len - 1; i >= 0; i--) {
4231 Interval* cur = parent->_split_children.at(i);
4232 if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) {
4233 result = cur;
4234 }
4235 }
4236
4237 assert(result != NULL, "no split child found");
4238 return result;
4239 }
4240
4241
4242 // checks if op_id is covered by any split child
4243 bool Interval::split_child_covers(int op_id, LIR_OpVisitState::OprMode mode) {
4244 assert(is_split_parent(), "can only be called for split parents");
4245 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4246
4247 if (_split_children.length() == 0) {
4248 // simple case if interval was not split
4249 return covers(op_id, mode);
4250
4251 } else {
4252 // extended case: check all split children
4253 int len = _split_children.length();
4254 for (int i = 0; i < len; i++) {
4255 Interval* cur = _split_children.at(i);
4256 if (cur->covers(op_id, mode)) {
4257 return true;
4258 }
4259 }
4260 return false;
4261 }
4262 }
4263
4264
4265 // Note: use positions are sorted descending -> first use has highest index
4266 int Interval::first_usage(IntervalUseKind min_use_kind) const {
4267 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4268
4269 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4270 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4271 return _use_pos_and_kinds.at(i);
4272 }
4273 }
4274 return max_jint;
4275 }
4276
4277 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const {
4278 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4279
4280 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4281 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4282 return _use_pos_and_kinds.at(i);
4283 }
4284 }
4285 return max_jint;
4286 }
4287
4288 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const {
4289 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4290
4291 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4292 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) {
4293 return _use_pos_and_kinds.at(i);
4294 }
4295 }
4296 return max_jint;
4297 }
4298
4299 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const {
4300 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4301
4302 int prev = 0;
4303 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4304 if (_use_pos_and_kinds.at(i) > from) {
4305 return prev;
4306 }
4307 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4308 prev = _use_pos_and_kinds.at(i);
4309 }
4310 }
4311 return prev;
4312 }
4313
4314 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) {
4315 assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range");
4316
4317 // do not add use positions for precolored intervals because
4318 // they are never used
4319 if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) {
4320 #ifdef ASSERT
4321 assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4322 for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4323 assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position");
4324 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4325 if (i > 0) {
4326 assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending");
4327 }
4328 }
4329 #endif
4330
4331 // Note: add_use is called in descending order, so list gets sorted
4332 // automatically by just appending new use positions
4333 int len = _use_pos_and_kinds.length();
4334 if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) {
4335 _use_pos_and_kinds.append(pos);
4336 _use_pos_and_kinds.append(use_kind);
4337 } else if (_use_pos_and_kinds.at(len - 1) < use_kind) {
4338 assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly");
4339 _use_pos_and_kinds.at_put(len - 1, use_kind);
4340 }
4341 }
4342 }
4343
4344 void Interval::add_range(int from, int to) {
4345 assert(from < to, "invalid range");
4346 assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
4347 assert(from <= first()->to(), "not inserting at begin of interval");
4348
4349 if (first()->from() <= to) {
4350 // join intersecting ranges
4351 first()->set_from(MIN2(from, first()->from()));
4352 first()->set_to (MAX2(to, first()->to()));
4353 } else {
4354 // insert new range
4355 _first = new Range(from, to, first());
4356 }
4357 }
4358
4359 Interval* Interval::new_split_child() {
4360 // allocate new interval
4361 Interval* result = new Interval(-1);
4362 result->set_type(type());
4363
4364 Interval* parent = split_parent();
4365 result->_split_parent = parent;
4366 result->set_register_hint(parent);
4367
4368 // insert new interval in children-list of parent
4369 if (parent->_split_children.length() == 0) {
4370 assert(is_split_parent(), "list must be initialized at first split");
4371
4372 parent->_split_children = IntervalList(4);
4373 parent->_split_children.append(this);
4374 }
4375 parent->_split_children.append(result);
4376
4377 return result;
4378 }
4379
4380 // split this interval at the specified position and return
4381 // the remainder as a new interval.
4382 //
4383 // when an interval is split, a bi-directional link is established between the original interval
4384 // (the split parent) and the intervals that are split off this interval (the split children)
4385 // When a split child is split again, the new created interval is also a direct child
4386 // of the original parent (there is no tree of split children stored, but a flat list)
4387 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
4388 //
4389 // Note: The new interval has no valid reg_num
4390 Interval* Interval::split(int split_pos) {
4391 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4392
4393 // allocate new interval
4394 Interval* result = new_split_child();
4395
4396 // split the ranges
4397 Range* prev = NULL;
4398 Range* cur = _first;
4399 while (cur != Range::end() && cur->to() <= split_pos) {
4400 prev = cur;
4401 cur = cur->next();
4402 }
4403 assert(cur != Range::end(), "split interval after end of last range");
4404
4405 if (cur->from() < split_pos) {
4406 result->_first = new Range(split_pos, cur->to(), cur->next());
4407 cur->set_to(split_pos);
4408 cur->set_next(Range::end());
4409
4410 } else {
4411 assert(prev != NULL, "split before start of first range");
4412 result->_first = cur;
4413 prev->set_next(Range::end());
4414 }
4415 result->_current = result->_first;
4416 _cached_to = -1; // clear cached value
4417
4418 // split list of use positions
4419 int total_len = _use_pos_and_kinds.length();
4420 int start_idx = total_len - 2;
4421 while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) {
4422 start_idx -= 2;
4423 }
4424
4425 intStack new_use_pos_and_kinds(total_len - start_idx);
4426 int i;
4427 for (i = start_idx + 2; i < total_len; i++) {
4428 new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i));
4429 }
4430
4431 _use_pos_and_kinds.truncate(start_idx + 2);
4432 result->_use_pos_and_kinds = _use_pos_and_kinds;
4433 _use_pos_and_kinds = new_use_pos_and_kinds;
4434
4435 #ifdef ASSERT
4436 assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4437 assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4438 assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
4439
4440 for (i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4441 assert(_use_pos_and_kinds.at(i) < split_pos, "must be");
4442 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4443 }
4444 for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) {
4445 assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be");
4446 assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4447 }
4448 #endif
4449
4450 return result;
4451 }
4452
4453 // split this interval at the specified position and return
4454 // the head as a new interval (the original interval is the tail)
4455 //
4456 // Currently, only the first range can be split, and the new interval
4457 // must not have split positions
4458 Interval* Interval::split_from_start(int split_pos) {
4459 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4460 assert(split_pos > from() && split_pos < to(), "can only split inside interval");
4461 assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
4462 assert(first_usage(noUse) > split_pos, "can not split when use positions are present");
4463
4464 // allocate new interval
4465 Interval* result = new_split_child();
4466
4467 // the new created interval has only one range (checked by assertion above),
4468 // so the splitting of the ranges is very simple
4469 result->add_range(_first->from(), split_pos);
4470
4471 if (split_pos == _first->to()) {
4472 assert(_first->next() != Range::end(), "must not be at end");
4473 _first = _first->next();
4474 } else {
4475 _first->set_from(split_pos);
4476 }
4477
4478 return result;
4479 }
4480
4481
4482 // returns true if the op_id is inside the interval
4483 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const {
4484 Range* cur = _first;
4485
4486 while (cur != Range::end() && cur->to() < op_id) {
4487 cur = cur->next();
4488 }
4489 if (cur != Range::end()) {
4490 assert(cur->to() != cur->next()->from(), "ranges not separated");
4491
4492 if (mode == LIR_OpVisitState::outputMode) {
4493 return cur->from() <= op_id && op_id < cur->to();
4494 } else {
4495 return cur->from() <= op_id && op_id <= cur->to();
4496 }
4497 }
4498 return false;
4499 }
4500
4501 // returns true if the interval has any hole between hole_from and hole_to
4502 // (even if the hole has only the length 1)
4503 bool Interval::has_hole_between(int hole_from, int hole_to) {
4504 assert(hole_from < hole_to, "check");
4505 assert(from() <= hole_from && hole_to <= to(), "index out of interval");
4506
4507 Range* cur = _first;
4508 while (cur != Range::end()) {
4509 assert(cur->to() < cur->next()->from(), "no space between ranges");
4510
4511 // hole-range starts before this range -> hole
4512 if (hole_from < cur->from()) {
4513 return true;
4514
4515 // hole-range completely inside this range -> no hole
4516 } else if (hole_to <= cur->to()) {
4517 return false;
4518
4519 // overlapping of hole-range with this range -> hole
4520 } else if (hole_from <= cur->to()) {
4521 return true;
4522 }
4523
4524 cur = cur->next();
4525 }
4526
4527 return false;
4528 }
4529
4530
4531 #ifndef PRODUCT
4532 void Interval::print(outputStream* out) const {
4533 const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4534 const char* UseKind2Name[] = { "N", "L", "S", "M" };
4535
4536 const char* type_name;
4537 LIR_Opr opr = LIR_OprFact::illegal();
4538 if (reg_num() < LIR_OprDesc::vreg_base) {
4539 type_name = "fixed";
4540 // need a temporary operand for fixed intervals because type() cannot be called
4541 #ifdef X86
4542 int last_xmm_reg = pd_last_xmm_reg;
4543 #ifdef _LP64
4544 if (UseAVX < 3) {
4545 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
4546 }
4547 #endif
4548 #endif
4549 if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) {
4550 opr = LIR_OprFact::single_cpu(assigned_reg());
4551 } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) {
4552 opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg);
4553 #ifdef X86
4554 } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= last_xmm_reg) {
4555 opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg);
4556 #endif
4557 } else {
4558 ShouldNotReachHere();
4559 }
4560 } else {
4561 type_name = type2name(type());
4562 if (assigned_reg() != -1 &&
4563 (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4564 opr = LinearScan::calc_operand_for_interval(this);
4565 }
4566 }
4567
4568 out->print("%d %s ", reg_num(), type_name);
4569 if (opr->is_valid()) {
4570 out->print("\"");
4571 opr->print(out);
4572 out->print("\" ");
4573 }
4574 out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
4575
4576 // print ranges
4577 Range* cur = _first;
4578 while (cur != Range::end()) {
4579 cur->print(out);
4580 cur = cur->next();
4581 assert(cur != NULL, "range list not closed with range sentinel");
4582 }
4583
4584 // print use positions
4585 int prev = 0;
4586 assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4587 for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4588 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4589 assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted");
4590
4591 out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]);
4592 prev = _use_pos_and_kinds.at(i);
4593 }
4594
4595 out->print(" \"%s\"", SpillState2Name[spill_state()]);
4596 out->cr();
4597 }
4598 #endif
4599
4600
4601
4602 // **** Implementation of IntervalWalker ****************************
4603
4604 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4605 : _compilation(allocator->compilation())
4606 , _allocator(allocator)
4607 {
4608 _unhandled_first[fixedKind] = unhandled_fixed_first;
4609 _unhandled_first[anyKind] = unhandled_any_first;
4610 _active_first[fixedKind] = Interval::end();
4611 _inactive_first[fixedKind] = Interval::end();
4612 _active_first[anyKind] = Interval::end();
4613 _inactive_first[anyKind] = Interval::end();
4614 _current_position = -1;
4615 _current = NULL;
4616 next_interval();
4617 }
4618
4619
4620 // append interval at top of list
4621 void IntervalWalker::append_unsorted(Interval** list, Interval* interval) {
4622 interval->set_next(*list); *list = interval;
4623 }
4624
4625
4626 // append interval in order of current range from()
4627 void IntervalWalker::append_sorted(Interval** list, Interval* interval) {
4628 Interval* prev = NULL;
4629 Interval* cur = *list;
4630 while (cur->current_from() < interval->current_from()) {
4631 prev = cur; cur = cur->next();
4632 }
4633 if (prev == NULL) {
4634 *list = interval;
4635 } else {
4636 prev->set_next(interval);
4637 }
4638 interval->set_next(cur);
4639 }
4640
4641 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) {
4642 assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
4643
4644 Interval* prev = NULL;
4645 Interval* cur = *list;
4646 while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
4647 prev = cur; cur = cur->next();
4648 }
4649 if (prev == NULL) {
4650 *list = interval;
4651 } else {
4652 prev->set_next(interval);
4653 }
4654 interval->set_next(cur);
4655 }
4656
4657
4658 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) {
4659 while (*list != Interval::end() && *list != i) {
4660 list = (*list)->next_addr();
4661 }
4662 if (*list != Interval::end()) {
4663 assert(*list == i, "check");
4664 *list = (*list)->next();
4665 return true;
4666 } else {
4667 return false;
4668 }
4669 }
4670
4671 void IntervalWalker::remove_from_list(Interval* i) {
4672 bool deleted;
4673
4674 if (i->state() == activeState) {
4675 deleted = remove_from_list(active_first_addr(anyKind), i);
4676 } else {
4677 assert(i->state() == inactiveState, "invalid state");
4678 deleted = remove_from_list(inactive_first_addr(anyKind), i);
4679 }
4680
4681 assert(deleted, "interval has not been found in list");
4682 }
4683
4684
4685 void IntervalWalker::walk_to(IntervalState state, int from) {
4686 assert (state == activeState || state == inactiveState, "wrong state");
4687 for_each_interval_kind(kind) {
4688 Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind);
4689 Interval* next = *prev;
4690 while (next->current_from() <= from) {
4691 Interval* cur = next;
4692 next = cur->next();
4693
4694 bool range_has_changed = false;
4695 while (cur->current_to() <= from) {
4696 cur->next_range();
4697 range_has_changed = true;
4698 }
4699
4700 // also handle move from inactive list to active list
4701 range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
4702
4703 if (range_has_changed) {
4704 // remove cur from list
4705 *prev = next;
4706 if (cur->current_at_end()) {
4707 // move to handled state (not maintained as a list)
4708 cur->set_state(handledState);
4709 interval_moved(cur, kind, state, handledState);
4710 } else if (cur->current_from() <= from){
4711 // sort into active list
4712 append_sorted(active_first_addr(kind), cur);
4713 cur->set_state(activeState);
4714 if (*prev == cur) {
4715 assert(state == activeState, "check");
4716 prev = cur->next_addr();
4717 }
4718 interval_moved(cur, kind, state, activeState);
4719 } else {
4720 // sort into inactive list
4721 append_sorted(inactive_first_addr(kind), cur);
4722 cur->set_state(inactiveState);
4723 if (*prev == cur) {
4724 assert(state == inactiveState, "check");
4725 prev = cur->next_addr();
4726 }
4727 interval_moved(cur, kind, state, inactiveState);
4728 }
4729 } else {
4730 prev = cur->next_addr();
4731 continue;
4732 }
4733 }
4734 }
4735 }
4736
4737
4738 void IntervalWalker::next_interval() {
4739 IntervalKind kind;
4740 Interval* any = _unhandled_first[anyKind];
4741 Interval* fixed = _unhandled_first[fixedKind];
4742
4743 if (any != Interval::end()) {
4744 // intervals may start at same position -> prefer fixed interval
4745 kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind;
4746
4747 assert (kind == fixedKind && fixed->from() <= any->from() ||
4748 kind == anyKind && any->from() <= fixed->from(), "wrong interval!!!");
4749 assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
4750
4751 } else if (fixed != Interval::end()) {
4752 kind = fixedKind;
4753 } else {
4754 _current = NULL; return;
4755 }
4756 _current_kind = kind;
4757 _current = _unhandled_first[kind];
4758 _unhandled_first[kind] = _current->next();
4759 _current->set_next(Interval::end());
4760 _current->rewind_range();
4761 }
4762
4763
4764 void IntervalWalker::walk_to(int lir_op_id) {
4765 assert(_current_position <= lir_op_id, "can not walk backwards");
4766 while (current() != NULL) {
4767 bool is_active = current()->from() <= lir_op_id;
4768 int id = is_active ? current()->from() : lir_op_id;
4769
4770 TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
4771
4772 // set _current_position prior to call of walk_to
4773 _current_position = id;
4774
4775 // call walk_to even if _current_position == id
4776 walk_to(activeState, id);
4777 walk_to(inactiveState, id);
4778
4779 if (is_active) {
4780 current()->set_state(activeState);
4781 if (activate_current()) {
4782 append_sorted(active_first_addr(current_kind()), current());
4783 interval_moved(current(), current_kind(), unhandledState, activeState);
4784 }
4785
4786 next_interval();
4787 } else {
4788 return;
4789 }
4790 }
4791 }
4792
4793 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
4794 #ifndef PRODUCT
4795 if (TraceLinearScanLevel >= 4) {
4796 #define print_state(state) \
4797 switch(state) {\
4798 case unhandledState: tty->print("unhandled"); break;\
4799 case activeState: tty->print("active"); break;\
4800 case inactiveState: tty->print("inactive"); break;\
4801 case handledState: tty->print("handled"); break;\
4802 default: ShouldNotReachHere(); \
4803 }
4804
4805 print_state(from); tty->print(" to "); print_state(to);
4806 tty->fill_to(23);
4807 interval->print();
4808
4809 #undef print_state
4810 }
4811 #endif
4812 }
4813
4814
4815
4816 // **** Implementation of LinearScanWalker **************************
4817
4818 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4819 : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first)
4820 , _move_resolver(allocator)
4821 {
4822 for (int i = 0; i < LinearScan::nof_regs; i++) {
4823 _spill_intervals[i] = new IntervalList(2);
4824 }
4825 }
4826
4827
4828 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) {
4829 for (int i = _first_reg; i <= _last_reg; i++) {
4830 _use_pos[i] = max_jint;
4831
4832 if (!only_process_use_pos) {
4833 _block_pos[i] = max_jint;
4834 _spill_intervals[i]->clear();
4835 }
4836 }
4837 }
4838
4839 inline void LinearScanWalker::exclude_from_use(int reg) {
4840 assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
4841 if (reg >= _first_reg && reg <= _last_reg) {
4842 _use_pos[reg] = 0;
4843 }
4844 }
4845 inline void LinearScanWalker::exclude_from_use(Interval* i) {
4846 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4847
4848 exclude_from_use(i->assigned_reg());
4849 exclude_from_use(i->assigned_regHi());
4850 }
4851
4852 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
4853 assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0");
4854
4855 if (reg >= _first_reg && reg <= _last_reg) {
4856 if (_use_pos[reg] > use_pos) {
4857 _use_pos[reg] = use_pos;
4858 }
4859 if (!only_process_use_pos) {
4860 _spill_intervals[reg]->append(i);
4861 }
4862 }
4863 }
4864 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
4865 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4866 if (use_pos != -1) {
4867 set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos);
4868 set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
4869 }
4870 }
4871
4872 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) {
4873 if (reg >= _first_reg && reg <= _last_reg) {
4874 if (_block_pos[reg] > block_pos) {
4875 _block_pos[reg] = block_pos;
4876 }
4877 if (_use_pos[reg] > block_pos) {
4878 _use_pos[reg] = block_pos;
4879 }
4880 }
4881 }
4882 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) {
4883 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4884 if (block_pos != -1) {
4885 set_block_pos(i->assigned_reg(), i, block_pos);
4886 set_block_pos(i->assigned_regHi(), i, block_pos);
4887 }
4888 }
4889
4890
4891 void LinearScanWalker::free_exclude_active_fixed() {
4892 Interval* list = active_first(fixedKind);
4893 while (list != Interval::end()) {
4894 assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
4895 exclude_from_use(list);
4896 list = list->next();
4897 }
4898 }
4899
4900 void LinearScanWalker::free_exclude_active_any() {
4901 Interval* list = active_first(anyKind);
4902 while (list != Interval::end()) {
4903 exclude_from_use(list);
4904 list = list->next();
4905 }
4906 }
4907
4908 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) {
4909 Interval* list = inactive_first(fixedKind);
4910 while (list != Interval::end()) {
4911 if (cur->to() <= list->current_from()) {
4912 assert(list->current_intersects_at(cur) == -1, "must not intersect");
4913 set_use_pos(list, list->current_from(), true);
4914 } else {
4915 set_use_pos(list, list->current_intersects_at(cur), true);
4916 }
4917 list = list->next();
4918 }
4919 }
4920
4921 void LinearScanWalker::free_collect_inactive_any(Interval* cur) {
4922 Interval* list = inactive_first(anyKind);
4923 while (list != Interval::end()) {
4924 set_use_pos(list, list->current_intersects_at(cur), true);
4925 list = list->next();
4926 }
4927 }
4928
4929 void LinearScanWalker::free_collect_unhandled(IntervalKind kind, Interval* cur) {
4930 Interval* list = unhandled_first(kind);
4931 while (list != Interval::end()) {
4932 set_use_pos(list, list->intersects_at(cur), true);
4933 if (kind == fixedKind && cur->to() <= list->from()) {
4934 set_use_pos(list, list->from(), true);
4935 }
4936 list = list->next();
4937 }
4938 }
4939
4940 void LinearScanWalker::spill_exclude_active_fixed() {
4941 Interval* list = active_first(fixedKind);
4942 while (list != Interval::end()) {
4943 exclude_from_use(list);
4944 list = list->next();
4945 }
4946 }
4947
4948 void LinearScanWalker::spill_block_unhandled_fixed(Interval* cur) {
4949 Interval* list = unhandled_first(fixedKind);
4950 while (list != Interval::end()) {
4951 set_block_pos(list, list->intersects_at(cur));
4952 list = list->next();
4953 }
4954 }
4955
4956 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) {
4957 Interval* list = inactive_first(fixedKind);
4958 while (list != Interval::end()) {
4959 if (cur->to() > list->current_from()) {
4960 set_block_pos(list, list->current_intersects_at(cur));
4961 } else {
4962 assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect");
4963 }
4964
4965 list = list->next();
4966 }
4967 }
4968
4969 void LinearScanWalker::spill_collect_active_any() {
4970 Interval* list = active_first(anyKind);
4971 while (list != Interval::end()) {
4972 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
4973 list = list->next();
4974 }
4975 }
4976
4977 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) {
4978 Interval* list = inactive_first(anyKind);
4979 while (list != Interval::end()) {
4980 if (list->current_intersects(cur)) {
4981 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
4982 }
4983 list = list->next();
4984 }
4985 }
4986
4987
4988 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) {
4989 // output all moves here. When source and target are equal, the move is
4990 // optimized away later in assign_reg_nums
4991
4992 op_id = (op_id + 1) & ~1;
4993 BlockBegin* op_block = allocator()->block_of_op_with_id(op_id);
4994 assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
4995
4996 // calculate index of instruction inside instruction list of current block
4997 // the minimal index (for a block with no spill moves) can be calculated because the
4998 // numbering of instructions is known.
4999 // When the block already contains spill moves, the index must be increased until the
5000 // correct index is reached.
5001 LIR_OpList* list = op_block->lir()->instructions_list();
5002 int index = (op_id - list->at(0)->id()) / 2;
5003 assert(list->at(index)->id() <= op_id, "error in calculation");
5004
5005 while (list->at(index)->id() != op_id) {
5006 index++;
5007 assert(0 <= index && index < list->length(), "index out of bounds");
5008 }
5009 assert(1 <= index && index < list->length(), "index out of bounds");
5010 assert(list->at(index)->id() == op_id, "error in calculation");
5011
5012 // insert new instruction before instruction at position index
5013 _move_resolver.move_insert_position(op_block->lir(), index - 1);
5014 _move_resolver.add_mapping(src_it, dst_it);
5015 }
5016
5017
5018 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
5019 int from_block_nr = min_block->linear_scan_number();
5020 int to_block_nr = max_block->linear_scan_number();
5021
5022 assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range");
5023 assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range");
5024 assert(from_block_nr < to_block_nr, "must cross block boundary");
5025
5026 // Try to split at end of max_block. If this would be after
5027 // max_split_pos, then use the begin of max_block
5028 int optimal_split_pos = max_block->last_lir_instruction_id() + 2;
5029 if (optimal_split_pos > max_split_pos) {
5030 optimal_split_pos = max_block->first_lir_instruction_id();
5031 }
5032
5033 int min_loop_depth = max_block->loop_depth();
5034 for (int i = to_block_nr - 1; i >= from_block_nr; i--) {
5035 BlockBegin* cur = block_at(i);
5036
5037 if (cur->loop_depth() < min_loop_depth) {
5038 // block with lower loop-depth found -> split at the end of this block
5039 min_loop_depth = cur->loop_depth();
5040 optimal_split_pos = cur->last_lir_instruction_id() + 2;
5041 }
5042 }
5043 assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
5044
5045 return optimal_split_pos;
5046 }
5047
5048
5049 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
5050 int optimal_split_pos = -1;
5051 if (min_split_pos == max_split_pos) {
5052 // trivial case, no optimization of split position possible
5053 TRACE_LINEAR_SCAN(4, tty->print_cr(" min-pos and max-pos are equal, no optimization possible"));
5054 optimal_split_pos = min_split_pos;
5055
5056 } else {
5057 assert(min_split_pos < max_split_pos, "must be true then");
5058 assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise");
5059
5060 // reason for using min_split_pos - 1: when the minimal split pos is exactly at the
5061 // beginning of a block, then min_split_pos is also a possible split position.
5062 // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
5063 BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1);
5064
5065 // reason for using max_split_pos - 1: otherwise there would be an assertion failure
5066 // when an interval ends at the end of the last block of the method
5067 // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
5068 // block at this op_id)
5069 BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1);
5070
5071 assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order");
5072 if (min_block == max_block) {
5073 // split position cannot be moved to block boundary, so split as late as possible
5074 TRACE_LINEAR_SCAN(4, tty->print_cr(" cannot move split pos to block boundary because min_pos and max_pos are in same block"));
5075 optimal_split_pos = max_split_pos;
5076
5077 } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
5078 // Do not move split position if the interval has a hole before max_split_pos.
5079 // Intervals resulting from Phi-Functions have more than one definition (marked
5080 // as mustHaveRegister) with a hole before each definition. When the register is needed
5081 // for the second definition, an earlier reloading is unnecessary.
5082 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has hole just before max_split_pos, so splitting at max_split_pos"));
5083 optimal_split_pos = max_split_pos;
5084
5085 } else {
5086 // seach optimal block boundary between min_split_pos and max_split_pos
5087 TRACE_LINEAR_SCAN(4, tty->print_cr(" moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
5088
5089 if (do_loop_optimization) {
5090 // Loop optimization: if a loop-end marker is found between min- and max-position,
5091 // then split before this loop
5092 int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
5093 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization: loop end found at pos %d", loop_end_pos));
5094
5095 assert(loop_end_pos > min_split_pos, "invalid order");
5096 if (loop_end_pos < max_split_pos) {
5097 // loop-end marker found between min- and max-position
5098 // if it is not the end marker for the same loop as the min-position, then move
5099 // the max-position to this loop block.
5100 // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
5101 // of the interval (normally, only mustHaveRegister causes a reloading)
5102 BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos);
5103
5104 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
5105 assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
5106
5107 optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
5108 if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) {
5109 optimal_split_pos = -1;
5110 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization not necessary"));
5111 } else {
5112 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization successful"));
5113 }
5114 }
5115 }
5116
5117 if (optimal_split_pos == -1) {
5118 // not calculated by loop optimization
5119 optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos);
5120 }
5121 }
5122 }
5123 TRACE_LINEAR_SCAN(4, tty->print_cr(" optimal split position: %d", optimal_split_pos));
5124
5125 return optimal_split_pos;
5126 }
5127
5128
5129 /*
5130 split an interval at the optimal position between min_split_pos and
5131 max_split_pos in two parts:
5132 1) the left part has already a location assigned
5133 2) the right part is sorted into to the unhandled-list
5134 */
5135 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) {
5136 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting interval: "); it->print());
5137 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos));
5138
5139 assert(it->from() < min_split_pos, "cannot split at start of interval");
5140 assert(current_position() < min_split_pos, "cannot split before current position");
5141 assert(min_split_pos <= max_split_pos, "invalid order");
5142 assert(max_split_pos <= it->to(), "cannot split after end of interval");
5143
5144 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true);
5145
5146 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5147 assert(optimal_split_pos <= it->to(), "cannot split after end of interval");
5148 assert(optimal_split_pos > it->from(), "cannot split at start of interval");
5149
5150 if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
5151 // the split position would be just before the end of the interval
5152 // -> no split at all necessary
5153 TRACE_LINEAR_SCAN(4, tty->print_cr(" no split necessary because optimal split position is at end of interval"));
5154 return;
5155 }
5156
5157 // must calculate this before the actual split is performed and before split position is moved to odd op_id
5158 bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
5159
5160 if (!allocator()->is_block_begin(optimal_split_pos)) {
5161 // move position before actual instruction (odd op_id)
5162 optimal_split_pos = (optimal_split_pos - 1) | 1;
5163 }
5164
5165 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos));
5166 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5167 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5168
5169 Interval* split_part = it->split(optimal_split_pos);
5170
5171 allocator()->append_interval(split_part);
5172 allocator()->copy_register_flags(it, split_part);
5173 split_part->set_insert_move_when_activated(move_necessary);
5174 append_to_unhandled(unhandled_first_addr(anyKind), split_part);
5175
5176 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts (insert_move_when_activated: %d)", move_necessary));
5177 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print());
5178 TRACE_LINEAR_SCAN(2, tty->print (" "); split_part->print());
5179 }
5180
5181 /*
5182 split an interval at the optimal position between min_split_pos and
5183 max_split_pos in two parts:
5184 1) the left part has already a location assigned
5185 2) the right part is always on the stack and therefore ignored in further processing
5186 */
5187 void LinearScanWalker::split_for_spilling(Interval* it) {
5188 // calculate allowed range of splitting position
5189 int max_split_pos = current_position();
5190 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
5191
5192 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting and spilling interval: "); it->print());
5193 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos));
5194
5195 assert(it->state() == activeState, "why spill interval that is not active?");
5196 assert(it->from() <= min_split_pos, "cannot split before start of interval");
5197 assert(min_split_pos <= max_split_pos, "invalid order");
5198 assert(max_split_pos < it->to(), "cannot split at end end of interval");
5199 assert(current_position() < it->to(), "interval must not end before current position");
5200
5201 if (min_split_pos == it->from()) {
5202 // the whole interval is never used, so spill it entirely to memory
5203 TRACE_LINEAR_SCAN(2, tty->print_cr(" spilling entire interval because split pos is at beginning of interval"));
5204 assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
5205
5206 allocator()->assign_spill_slot(it);
5207 allocator()->change_spill_state(it, min_split_pos);
5208
5209 // Also kick parent intervals out of register to memory when they have no use
5210 // position. This avoids short interval in register surrounded by intervals in
5211 // memory -> avoid useless moves from memory to register and back
5212 Interval* parent = it;
5213 while (parent != NULL && parent->is_split_child()) {
5214 parent = parent->split_child_before_op_id(parent->from());
5215
5216 if (parent->assigned_reg() < LinearScan::nof_regs) {
5217 if (parent->first_usage(shouldHaveRegister) == max_jint) {
5218 // parent is never used, so kick it out of its assigned register
5219 TRACE_LINEAR_SCAN(4, tty->print_cr(" kicking out interval %d out of its register because it is never used", parent->reg_num()));
5220 allocator()->assign_spill_slot(parent);
5221 } else {
5222 // do not go further back because the register is actually used by the interval
5223 parent = NULL;
5224 }
5225 }
5226 }
5227
5228 } else {
5229 // search optimal split pos, split interval and spill only the right hand part
5230 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false);
5231
5232 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5233 assert(optimal_split_pos < it->to(), "cannot split at end of interval");
5234 assert(optimal_split_pos >= it->from(), "cannot split before start of interval");
5235
5236 if (!allocator()->is_block_begin(optimal_split_pos)) {
5237 // move position before actual instruction (odd op_id)
5238 optimal_split_pos = (optimal_split_pos - 1) | 1;
5239 }
5240
5241 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos));
5242 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5243 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5244
5245 Interval* spilled_part = it->split(optimal_split_pos);
5246 allocator()->append_interval(spilled_part);
5247 allocator()->assign_spill_slot(spilled_part);
5248 allocator()->change_spill_state(spilled_part, optimal_split_pos);
5249
5250 if (!allocator()->is_block_begin(optimal_split_pos)) {
5251 TRACE_LINEAR_SCAN(4, tty->print_cr(" inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
5252 insert_move(optimal_split_pos, it, spilled_part);
5253 }
5254
5255 // the current_split_child is needed later when moves are inserted for reloading
5256 assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child");
5257 spilled_part->make_current_split_child();
5258
5259 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts"));
5260 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print());
5261 TRACE_LINEAR_SCAN(2, tty->print (" "); spilled_part->print());
5262 }
5263 }
5264
5265
5266 void LinearScanWalker::split_stack_interval(Interval* it) {
5267 int min_split_pos = current_position() + 1;
5268 int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to());
5269
5270 split_before_usage(it, min_split_pos, max_split_pos);
5271 }
5272
5273 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
5274 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
5275 int max_split_pos = register_available_until;
5276
5277 split_before_usage(it, min_split_pos, max_split_pos);
5278 }
5279
5280 void LinearScanWalker::split_and_spill_interval(Interval* it) {
5281 assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
5282
5283 int current_pos = current_position();
5284 if (it->state() == inactiveState) {
5285 // the interval is currently inactive, so no spill slot is needed for now.
5286 // when the split part is activated, the interval has a new chance to get a register,
5287 // so in the best case no stack slot is necessary
5288 assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
5289 split_before_usage(it, current_pos + 1, current_pos + 1);
5290
5291 } else {
5292 // search the position where the interval must have a register and split
5293 // at the optimal position before.
5294 // The new created part is added to the unhandled list and will get a register
5295 // when it is activated
5296 int min_split_pos = current_pos + 1;
5297 int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to());
5298
5299 split_before_usage(it, min_split_pos, max_split_pos);
5300
5301 assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
5302 split_for_spilling(it);
5303 }
5304 }
5305
5306
5307 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5308 int min_full_reg = any_reg;
5309 int max_partial_reg = any_reg;
5310
5311 for (int i = _first_reg; i <= _last_reg; i++) {
5312 if (i == ignore_reg) {
5313 // this register must be ignored
5314
5315 } else if (_use_pos[i] >= interval_to) {
5316 // this register is free for the full interval
5317 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5318 min_full_reg = i;
5319 }
5320 } else if (_use_pos[i] > reg_needed_until) {
5321 // this register is at least free until reg_needed_until
5322 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5323 max_partial_reg = i;
5324 }
5325 }
5326 }
5327
5328 if (min_full_reg != any_reg) {
5329 return min_full_reg;
5330 } else if (max_partial_reg != any_reg) {
5331 *need_split = true;
5332 return max_partial_reg;
5333 } else {
5334 return any_reg;
5335 }
5336 }
5337
5338 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5339 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5340
5341 int min_full_reg = any_reg;
5342 int max_partial_reg = any_reg;
5343
5344 for (int i = _first_reg; i < _last_reg; i+=2) {
5345 if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) {
5346 // this register is free for the full interval
5347 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5348 min_full_reg = i;
5349 }
5350 } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5351 // this register is at least free until reg_needed_until
5352 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5353 max_partial_reg = i;
5354 }
5355 }
5356 }
5357
5358 if (min_full_reg != any_reg) {
5359 return min_full_reg;
5360 } else if (max_partial_reg != any_reg) {
5361 *need_split = true;
5362 return max_partial_reg;
5363 } else {
5364 return any_reg;
5365 }
5366 }
5367
5368
5369 bool LinearScanWalker::alloc_free_reg(Interval* cur) {
5370 TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print());
5371
5372 init_use_lists(true);
5373 free_exclude_active_fixed();
5374 free_exclude_active_any();
5375 free_collect_inactive_fixed(cur);
5376 free_collect_inactive_any(cur);
5377 // free_collect_unhandled(fixedKind, cur);
5378 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5379
5380 // _use_pos contains the start of the next interval that has this register assigned
5381 // (either as a fixed register or a normal allocated register in the past)
5382 // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
5383 TRACE_LINEAR_SCAN(4, tty->print_cr(" state of registers:"));
5384 TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr(" reg %d: use_pos: %d", i, _use_pos[i]));
5385
5386 int hint_reg, hint_regHi;
5387 Interval* register_hint = cur->register_hint();
5388 if (register_hint != NULL) {
5389 hint_reg = register_hint->assigned_reg();
5390 hint_regHi = register_hint->assigned_regHi();
5391
5392 if (allocator()->is_precolored_cpu_interval(register_hint)) {
5393 assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals");
5394 hint_regHi = hint_reg + 1; // connect e.g. eax-edx
5395 }
5396 TRACE_LINEAR_SCAN(4, tty->print(" hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print());
5397
5398 } else {
5399 hint_reg = any_reg;
5400 hint_regHi = any_reg;
5401 }
5402 assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal");
5403 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
5404
5405 // the register must be free at least until this position
5406 int reg_needed_until = cur->from() + 1;
5407 int interval_to = cur->to();
5408
5409 bool need_split = false;
5410 int split_pos = -1;
5411 int reg = any_reg;
5412 int regHi = any_reg;
5413
5414 if (_adjacent_regs) {
5415 reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split);
5416 regHi = reg + 1;
5417 if (reg == any_reg) {
5418 return false;
5419 }
5420 split_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5421
5422 } else {
5423 reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split);
5424 if (reg == any_reg) {
5425 return false;
5426 }
5427 split_pos = _use_pos[reg];
5428
5429 if (_num_phys_regs == 2) {
5430 regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split);
5431
5432 if (_use_pos[reg] < interval_to && regHi == any_reg) {
5433 // do not split interval if only one register can be assigned until the split pos
5434 // (when one register is found for the whole interval, split&spill is only
5435 // performed for the hi register)
5436 return false;
5437
5438 } else if (regHi != any_reg) {
5439 split_pos = MIN2(split_pos, _use_pos[regHi]);
5440
5441 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5442 if (reg > regHi) {
5443 int temp = reg;
5444 reg = regHi;
5445 regHi = temp;
5446 }
5447 }
5448 }
5449 }
5450
5451 cur->assign_reg(reg, regHi);
5452 TRACE_LINEAR_SCAN(2, tty->print_cr("selected register %d, %d", reg, regHi));
5453
5454 assert(split_pos > 0, "invalid split_pos");
5455 if (need_split) {
5456 // register not available for full interval, so split it
5457 split_when_partial_register_available(cur, split_pos);
5458 }
5459
5460 // only return true if interval is completely assigned
5461 return _num_phys_regs == 1 || regHi != any_reg;
5462 }
5463
5464
5465 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5466 int max_reg = any_reg;
5467
5468 for (int i = _first_reg; i <= _last_reg; i++) {
5469 if (i == ignore_reg) {
5470 // this register must be ignored
5471
5472 } else if (_use_pos[i] > reg_needed_until) {
5473 if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) {
5474 max_reg = i;
5475 }
5476 }
5477 }
5478
5479 if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) {
5480 *need_split = true;
5481 }
5482
5483 return max_reg;
5484 }
5485
5486 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5487 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5488
5489 int max_reg = any_reg;
5490
5491 for (int i = _first_reg; i < _last_reg; i+=2) {
5492 if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5493 if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5494 max_reg = i;
5495 }
5496 }
5497 }
5498
5499 if (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to) {
5500 *need_split = true;
5501 }
5502
5503 return max_reg;
5504 }
5505
5506 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) {
5507 assert(reg != any_reg, "no register assigned");
5508
5509 for (int i = 0; i < _spill_intervals[reg]->length(); i++) {
5510 Interval* it = _spill_intervals[reg]->at(i);
5511 remove_from_list(it);
5512 split_and_spill_interval(it);
5513 }
5514
5515 if (regHi != any_reg) {
5516 IntervalList* processed = _spill_intervals[reg];
5517 for (int i = 0; i < _spill_intervals[regHi]->length(); i++) {
5518 Interval* it = _spill_intervals[regHi]->at(i);
5519 if (processed->index_of(it) == -1) {
5520 remove_from_list(it);
5521 split_and_spill_interval(it);
5522 }
5523 }
5524 }
5525 }
5526
5527
5528 // Split an Interval and spill it to memory so that cur can be placed in a register
5529 void LinearScanWalker::alloc_locked_reg(Interval* cur) {
5530 TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
5531
5532 // collect current usage of registers
5533 init_use_lists(false);
5534 spill_exclude_active_fixed();
5535 // spill_block_unhandled_fixed(cur);
5536 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5537 spill_block_inactive_fixed(cur);
5538 spill_collect_active_any();
5539 spill_collect_inactive_any(cur);
5540
5541 #ifndef PRODUCT
5542 if (TraceLinearScanLevel >= 4) {
5543 tty->print_cr(" state of registers:");
5544 for (int i = _first_reg; i <= _last_reg; i++) {
5545 tty->print(" reg %d: use_pos: %d, block_pos: %d, intervals: ", i, _use_pos[i], _block_pos[i]);
5546 for (int j = 0; j < _spill_intervals[i]->length(); j++) {
5547 tty->print("%d ", _spill_intervals[i]->at(j)->reg_num());
5548 }
5549 tty->cr();
5550 }
5551 }
5552 #endif
5553
5554 // the register must be free at least until this position
5555 int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1);
5556 int interval_to = cur->to();
5557 assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use");
5558
5559 int split_pos = 0;
5560 int use_pos = 0;
5561 bool need_split = false;
5562 int reg, regHi;
5563
5564 if (_adjacent_regs) {
5565 reg = find_locked_double_reg(reg_needed_until, interval_to, any_reg, &need_split);
5566 regHi = reg + 1;
5567
5568 if (reg != any_reg) {
5569 use_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5570 split_pos = MIN2(_block_pos[reg], _block_pos[regHi]);
5571 }
5572 } else {
5573 reg = find_locked_reg(reg_needed_until, interval_to, any_reg, cur->assigned_reg(), &need_split);
5574 regHi = any_reg;
5575
5576 if (reg != any_reg) {
5577 use_pos = _use_pos[reg];
5578 split_pos = _block_pos[reg];
5579
5580 if (_num_phys_regs == 2) {
5581 if (cur->assigned_reg() != any_reg) {
5582 regHi = reg;
5583 reg = cur->assigned_reg();
5584 } else {
5585 regHi = find_locked_reg(reg_needed_until, interval_to, any_reg, reg, &need_split);
5586 if (regHi != any_reg) {
5587 use_pos = MIN2(use_pos, _use_pos[regHi]);
5588 split_pos = MIN2(split_pos, _block_pos[regHi]);
5589 }
5590 }
5591
5592 if (regHi != any_reg && reg > regHi) {
5593 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5594 int temp = reg;
5595 reg = regHi;
5596 regHi = temp;
5597 }
5598 }
5599 }
5600 }
5601
5602 if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
5603 // the first use of cur is later than the spilling position -> spill cur
5604 TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
5605
5606 if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) {
5607 assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
5608 // assign a reasonable register and do a bailout in product mode to avoid errors
5609 allocator()->assign_spill_slot(cur);
5610 BAILOUT("LinearScan: no register found");
5611 }
5612
5613 split_and_spill_interval(cur);
5614 } else {
5615 TRACE_LINEAR_SCAN(4, tty->print_cr("decided to use register %d, %d", reg, regHi));
5616 assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found");
5617 assert(split_pos > 0, "invalid split_pos");
5618 assert(need_split == false || split_pos > cur->from(), "splitting interval at from");
5619
5620 cur->assign_reg(reg, regHi);
5621 if (need_split) {
5622 // register not available for full interval, so split it
5623 split_when_partial_register_available(cur, split_pos);
5624 }
5625
5626 // perform splitting and spilling for all affected intervalls
5627 split_and_spill_intersecting_intervals(reg, regHi);
5628 }
5629 }
5630
5631 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
5632 #ifdef X86
5633 // fast calculation of intervals that can never get a register because the
5634 // the next instruction is a call that blocks all registers
5635 // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
5636
5637 // check if this interval is the result of a split operation
5638 // (an interval got a register until this position)
5639 int pos = cur->from();
5640 if ((pos & 1) == 1) {
5641 // the current instruction is a call that blocks all registers
5642 if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) {
5643 TRACE_LINEAR_SCAN(4, tty->print_cr(" free register cannot be available because all registers blocked by following call"));
5644
5645 // safety check that there is really no register available
5646 assert(alloc_free_reg(cur) == false, "found a register for this interval");
5647 return true;
5648 }
5649
5650 }
5651 #endif
5652 return false;
5653 }
5654
5655 void LinearScanWalker::init_vars_for_alloc(Interval* cur) {
5656 BasicType type = cur->type();
5657 _num_phys_regs = LinearScan::num_physical_regs(type);
5658 _adjacent_regs = LinearScan::requires_adjacent_regs(type);
5659
5660 if (pd_init_regs_for_alloc(cur)) {
5661 // the appropriate register range was selected.
5662 } else if (type == T_FLOAT || type == T_DOUBLE) {
5663 _first_reg = pd_first_fpu_reg;
5664 _last_reg = pd_last_fpu_reg;
5665 } else {
5666 _first_reg = pd_first_cpu_reg;
5667 _last_reg = FrameMap::last_cpu_reg();
5668 }
5669
5670 assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range");
5671 assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range");
5672 }
5673
5674
5675 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) {
5676 if (op->code() != lir_move) {
5677 return false;
5678 }
5679 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
5680
5681 LIR_Opr in = ((LIR_Op1*)op)->in_opr();
5682 LIR_Opr res = ((LIR_Op1*)op)->result_opr();
5683 return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
5684 }
5685
5686 // optimization (especially for phi functions of nested loops):
5687 // assign same spill slot to non-intersecting intervals
5688 void LinearScanWalker::combine_spilled_intervals(Interval* cur) {
5689 if (cur->is_split_child()) {
5690 // optimization is only suitable for split parents
5691 return;
5692 }
5693
5694 Interval* register_hint = cur->register_hint(false);
5695 if (register_hint == NULL) {
5696 // cur is not the target of a move, otherwise register_hint would be set
5697 return;
5698 }
5699 assert(register_hint->is_split_parent(), "register hint must be split parent");
5700
5701 if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
5702 // combining the stack slots for intervals where spill move optimization is applied
5703 // is not benefitial and would cause problems
5704 return;
5705 }
5706
5707 int begin_pos = cur->from();
5708 int end_pos = cur->to();
5709 if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) {
5710 // safety check that lir_op_with_id is allowed
5711 return;
5712 }
5713
5714 if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
5715 // cur and register_hint are not connected with two moves
5716 return;
5717 }
5718
5719 Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
5720 Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
5721 if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) {
5722 // register_hint must be split, otherwise the re-writing of use positions does not work
5723 return;
5724 }
5725
5726 assert(begin_hint->assigned_reg() != any_reg, "must have register assigned");
5727 assert(end_hint->assigned_reg() == any_reg, "must not have register assigned");
5728 assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
5729 assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
5730
5731 if (begin_hint->assigned_reg() < LinearScan::nof_regs) {
5732 // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
5733 return;
5734 }
5735 assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
5736
5737 // modify intervals such that cur gets the same stack slot as register_hint
5738 // delete use positions to prevent the intervals to get a register at beginning
5739 cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());
5740 cur->remove_first_use_pos();
5741 end_hint->remove_first_use_pos();
5742 }
5743
5744
5745 // allocate a physical register or memory location to an interval
5746 bool LinearScanWalker::activate_current() {
5747 Interval* cur = current();
5748 bool result = true;
5749
5750 TRACE_LINEAR_SCAN(2, tty->print ("+++++ activating interval "); cur->print());
5751 TRACE_LINEAR_SCAN(4, tty->print_cr(" split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
5752
5753 if (cur->assigned_reg() >= LinearScan::nof_regs) {
5754 // activating an interval that has a stack slot assigned -> split it at first use position
5755 // used for method parameters
5756 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has spill slot assigned (method parameter) -> split it before first use"));
5757
5758 split_stack_interval(cur);
5759 result = false;
5760
5761 } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
5762 // activating an interval that must start in a stack slot, but may get a register later
5763 // used for lir_roundfp: rounding is done by store to stack and reload later
5764 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval must start in stack slot -> split it before first use"));
5765 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
5766
5767 allocator()->assign_spill_slot(cur);
5768 split_stack_interval(cur);
5769 result = false;
5770
5771 } else if (cur->assigned_reg() == any_reg) {
5772 // interval has not assigned register -> normal allocation
5773 // (this is the normal case for most intervals)
5774 TRACE_LINEAR_SCAN(4, tty->print_cr(" normal allocation of register"));
5775
5776 // assign same spill slot to non-intersecting intervals
5777 combine_spilled_intervals(cur);
5778
5779 init_vars_for_alloc(cur);
5780 if (no_allocation_possible(cur) || !alloc_free_reg(cur)) {
5781 // no empty register available.
5782 // split and spill another interval so that this interval gets a register
5783 alloc_locked_reg(cur);
5784 }
5785
5786 // spilled intervals need not be move to active-list
5787 if (cur->assigned_reg() >= LinearScan::nof_regs) {
5788 result = false;
5789 }
5790 }
5791
5792 // load spilled values that become active from stack slot to register
5793 if (cur->insert_move_when_activated()) {
5794 assert(cur->is_split_child(), "must be");
5795 assert(cur->current_split_child() != NULL, "must be");
5796 assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
5797 TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
5798
5799 insert_move(cur->from(), cur->current_split_child(), cur);
5800 }
5801 cur->make_current_split_child();
5802
5803 return result; // true = interval is moved to active list
5804 }
5805
5806
5807 // Implementation of EdgeMoveOptimizer
5808
5809 EdgeMoveOptimizer::EdgeMoveOptimizer() :
5810 _edge_instructions(4),
5811 _edge_instructions_idx(4)
5812 {
5813 }
5814
5815 void EdgeMoveOptimizer::optimize(BlockList* code) {
5816 EdgeMoveOptimizer optimizer = EdgeMoveOptimizer();
5817
5818 // ignore the first block in the list (index 0 is not processed)
5819 for (int i = code->length() - 1; i >= 1; i--) {
5820 BlockBegin* block = code->at(i);
5821
5822 if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) {
5823 optimizer.optimize_moves_at_block_end(block);
5824 }
5825 if (block->number_of_sux() == 2) {
5826 optimizer.optimize_moves_at_block_begin(block);
5827 }
5828 }
5829 }
5830
5831
5832 // clear all internal data structures
5833 void EdgeMoveOptimizer::init_instructions() {
5834 _edge_instructions.clear();
5835 _edge_instructions_idx.clear();
5836 }
5837
5838 // append a lir-instruction-list and the index of the current operation in to the list
5839 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) {
5840 _edge_instructions.append(instructions);
5841 _edge_instructions_idx.append(instructions_idx);
5842 }
5843
5844 // return the current operation of the given edge (predecessor or successor)
5845 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) {
5846 LIR_OpList* instructions = _edge_instructions.at(edge);
5847 int idx = _edge_instructions_idx.at(edge);
5848
5849 if (idx < instructions->length()) {
5850 return instructions->at(idx);
5851 } else {
5852 return NULL;
5853 }
5854 }
5855
5856 // removes the current operation of the given edge (predecessor or successor)
5857 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) {
5858 LIR_OpList* instructions = _edge_instructions.at(edge);
5859 int idx = _edge_instructions_idx.at(edge);
5860 instructions->remove_at(idx);
5861
5862 if (decrement_index) {
5863 _edge_instructions_idx.at_put(edge, idx - 1);
5864 }
5865 }
5866
5867
5868 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) {
5869 if (op1 == NULL || op2 == NULL) {
5870 // at least one block is already empty -> no optimization possible
5871 return true;
5872 }
5873
5874 if (op1->code() == lir_move && op2->code() == lir_move) {
5875 assert(op1->as_Op1() != NULL, "move must be LIR_Op1");
5876 assert(op2->as_Op1() != NULL, "move must be LIR_Op1");
5877 LIR_Op1* move1 = (LIR_Op1*)op1;
5878 LIR_Op1* move2 = (LIR_Op1*)op2;
5879 if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
5880 // these moves are exactly equal and can be optimized
5881 return false;
5882 }
5883
5884 } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) {
5885 assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1");
5886 assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1");
5887 LIR_Op1* fxch1 = (LIR_Op1*)op1;
5888 LIR_Op1* fxch2 = (LIR_Op1*)op2;
5889 if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) {
5890 // equal FPU stack operations can be optimized
5891 return false;
5892 }
5893
5894 } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) {
5895 // equal FPU stack operations can be optimized
5896 return false;
5897 }
5898
5899 // no optimization possible
5900 return true;
5901 }
5902
5903 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) {
5904 TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
5905
5906 if (block->is_predecessor(block)) {
5907 // currently we can't handle this correctly.
5908 return;
5909 }
5910
5911 init_instructions();
5912 int num_preds = block->number_of_preds();
5913 assert(num_preds > 1, "do not call otherwise");
5914 assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
5915
5916 // setup a list with the lir-instructions of all predecessors
5917 int i;
5918 for (i = 0; i < num_preds; i++) {
5919 BlockBegin* pred = block->pred_at(i);
5920 LIR_OpList* pred_instructions = pred->lir()->instructions_list();
5921
5922 if (pred->number_of_sux() != 1) {
5923 // this can happen with switch-statements where multiple edges are between
5924 // the same blocks.
5925 return;
5926 }
5927
5928 assert(pred->number_of_sux() == 1, "can handle only one successor");
5929 assert(pred->sux_at(0) == block, "invalid control flow");
5930 assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
5931 assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
5932 assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
5933
5934 if (pred_instructions->last()->info() != NULL) {
5935 // can not optimize instructions when debug info is needed
5936 return;
5937 }
5938
5939 // ignore the unconditional branch at the end of the block
5940 append_instructions(pred_instructions, pred_instructions->length() - 2);
5941 }
5942
5943
5944 // process lir-instructions while all predecessors end with the same instruction
5945 while (true) {
5946 LIR_Op* op = instruction_at(0);
5947 for (i = 1; i < num_preds; i++) {
5948 if (operations_different(op, instruction_at(i))) {
5949 // these instructions are different and cannot be optimized ->
5950 // no further optimization possible
5951 return;
5952 }
5953 }
5954
5955 TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
5956
5957 // insert the instruction at the beginning of the current block
5958 block->lir()->insert_before(1, op);
5959
5960 // delete the instruction at the end of all predecessors
5961 for (i = 0; i < num_preds; i++) {
5962 remove_cur_instruction(i, true);
5963 }
5964 }
5965 }
5966
5967
5968 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) {
5969 TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
5970
5971 init_instructions();
5972 int num_sux = block->number_of_sux();
5973
5974 LIR_OpList* cur_instructions = block->lir()->instructions_list();
5975
5976 assert(num_sux == 2, "method should not be called otherwise");
5977 assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
5978 assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
5979 assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
5980
5981 if (cur_instructions->last()->info() != NULL) {
5982 // can no optimize instructions when debug info is needed
5983 return;
5984 }
5985
5986 LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2);
5987 if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
5988 // not a valid case for optimization
5989 // currently, only blocks that end with two branches (conditional branch followed
5990 // by unconditional branch) are optimized
5991 return;
5992 }
5993
5994 // now it is guaranteed that the block ends with two branch instructions.
5995 // the instructions are inserted at the end of the block before these two branches
5996 int insert_idx = cur_instructions->length() - 2;
5997
5998 int i;
5999 #ifdef ASSERT
6000 for (i = insert_idx - 1; i >= 0; i--) {
6001 LIR_Op* op = cur_instructions->at(i);
6002 if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
6003 assert(false, "block with two successors can have only two branch instructions");
6004 }
6005 }
6006 #endif
6007
6008 // setup a list with the lir-instructions of all successors
6009 for (i = 0; i < num_sux; i++) {
6010 BlockBegin* sux = block->sux_at(i);
6011 LIR_OpList* sux_instructions = sux->lir()->instructions_list();
6012
6013 assert(sux_instructions->at(0)->code() == lir_label, "block must start with label");
6014
6015 if (sux->number_of_preds() != 1) {
6016 // this can happen with switch-statements where multiple edges are between
6017 // the same blocks.
6018 return;
6019 }
6020 assert(sux->pred_at(0) == block, "invalid control flow");
6021 assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6022
6023 // ignore the label at the beginning of the block
6024 append_instructions(sux_instructions, 1);
6025 }
6026
6027 // process lir-instructions while all successors begin with the same instruction
6028 while (true) {
6029 LIR_Op* op = instruction_at(0);
6030 for (i = 1; i < num_sux; i++) {
6031 if (operations_different(op, instruction_at(i))) {
6032 // these instructions are different and cannot be optimized ->
6033 // no further optimization possible
6034 return;
6035 }
6036 }
6037
6038 TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
6039
6040 // insert instruction at end of current block
6041 block->lir()->insert_before(insert_idx, op);
6042 insert_idx++;
6043
6044 // delete the instructions at the beginning of all successors
6045 for (i = 0; i < num_sux; i++) {
6046 remove_cur_instruction(i, false);
6047 }
6048 }
6049 }
6050
6051
6052 // Implementation of ControlFlowOptimizer
6053
6054 ControlFlowOptimizer::ControlFlowOptimizer() :
6055 _original_preds(4)
6056 {
6057 }
6058
6059 void ControlFlowOptimizer::optimize(BlockList* code) {
6060 ControlFlowOptimizer optimizer = ControlFlowOptimizer();
6061
6062 // push the OSR entry block to the end so that we're not jumping over it.
6063 BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry();
6064 if (osr_entry) {
6065 int index = osr_entry->linear_scan_number();
6066 assert(code->at(index) == osr_entry, "wrong index");
6067 code->remove_at(index);
6068 code->append(osr_entry);
6069 }
6070
6071 optimizer.reorder_short_loops(code);
6072 optimizer.delete_empty_blocks(code);
6073 optimizer.delete_unnecessary_jumps(code);
6074 optimizer.delete_jumps_to_return(code);
6075 }
6076
6077 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
6078 int i = header_idx + 1;
6079 int max_end = MIN2(header_idx + ShortLoopSize, code->length());
6080 while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) {
6081 i++;
6082 }
6083
6084 if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) {
6085 int end_idx = i - 1;
6086 BlockBegin* end_block = code->at(end_idx);
6087
6088 if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) {
6089 // short loop from header_idx to end_idx found -> reorder blocks such that
6090 // the header_block is the last block instead of the first block of the loop
6091 TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d",
6092 end_idx - header_idx + 1,
6093 header_block->block_id(), end_block->block_id()));
6094
6095 for (int j = header_idx; j < end_idx; j++) {
6096 code->at_put(j, code->at(j + 1));
6097 }
6098 code->at_put(end_idx, header_block);
6099
6100 // correct the flags so that any loop alignment occurs in the right place.
6101 assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
6102 code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag);
6103 code->at(header_idx)->set(BlockBegin::backward_branch_target_flag);
6104 }
6105 }
6106 }
6107
6108 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) {
6109 for (int i = code->length() - 1; i >= 0; i--) {
6110 BlockBegin* block = code->at(i);
6111
6112 if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) {
6113 reorder_short_loop(code, block, i);
6114 }
6115 }
6116
6117 DEBUG_ONLY(verify(code));
6118 }
6119
6120 // only blocks with exactly one successor can be deleted. Such blocks
6121 // must always end with an unconditional branch to this successor
6122 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) {
6123 if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
6124 return false;
6125 }
6126
6127 LIR_OpList* instructions = block->lir()->instructions_list();
6128
6129 assert(instructions->length() >= 2, "block must have label and branch");
6130 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6131 assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch");
6132 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
6133 assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
6134
6135 // block must have exactly one successor
6136
6137 if (instructions->length() == 2 && instructions->last()->info() == NULL) {
6138 return true;
6139 }
6140 return false;
6141 }
6142
6143 // substitute branch targets in all branch-instructions of this blocks
6144 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
6145 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
6146
6147 LIR_OpList* instructions = block->lir()->instructions_list();
6148
6149 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6150 for (int i = instructions->length() - 1; i >= 1; i--) {
6151 LIR_Op* op = instructions->at(i);
6152
6153 if (op->code() == lir_branch || op->code() == lir_cond_float_branch) {
6154 assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6155 LIR_OpBranch* branch = (LIR_OpBranch*)op;
6156
6157 if (branch->block() == target_from) {
6158 branch->change_block(target_to);
6159 }
6160 if (branch->ublock() == target_from) {
6161 branch->change_ublock(target_to);
6162 }
6163 }
6164 }
6165 }
6166
6167 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) {
6168 int old_pos = 0;
6169 int new_pos = 0;
6170 int num_blocks = code->length();
6171
6172 while (old_pos < num_blocks) {
6173 BlockBegin* block = code->at(old_pos);
6174
6175 if (can_delete_block(block)) {
6176 BlockBegin* new_target = block->sux_at(0);
6177
6178 // propagate backward branch target flag for correct code alignment
6179 if (block->is_set(BlockBegin::backward_branch_target_flag)) {
6180 new_target->set(BlockBegin::backward_branch_target_flag);
6181 }
6182
6183 // collect a list with all predecessors that contains each predecessor only once
6184 // the predecessors of cur are changed during the substitution, so a copy of the
6185 // predecessor list is necessary
6186 int j;
6187 _original_preds.clear();
6188 for (j = block->number_of_preds() - 1; j >= 0; j--) {
6189 BlockBegin* pred = block->pred_at(j);
6190 if (_original_preds.index_of(pred) == -1) {
6191 _original_preds.append(pred);
6192 }
6193 }
6194
6195 for (j = _original_preds.length() - 1; j >= 0; j--) {
6196 BlockBegin* pred = _original_preds.at(j);
6197 substitute_branch_target(pred, block, new_target);
6198 pred->substitute_sux(block, new_target);
6199 }
6200 } else {
6201 // adjust position of this block in the block list if blocks before
6202 // have been deleted
6203 if (new_pos != old_pos) {
6204 code->at_put(new_pos, code->at(old_pos));
6205 }
6206 new_pos++;
6207 }
6208 old_pos++;
6209 }
6210 code->truncate(new_pos);
6211
6212 DEBUG_ONLY(verify(code));
6213 }
6214
6215 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
6216 // skip the last block because there a branch is always necessary
6217 for (int i = code->length() - 2; i >= 0; i--) {
6218 BlockBegin* block = code->at(i);
6219 LIR_OpList* instructions = block->lir()->instructions_list();
6220
6221 LIR_Op* last_op = instructions->last();
6222 if (last_op->code() == lir_branch) {
6223 assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6224 LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op;
6225
6226 assert(last_branch->block() != NULL, "last branch must always have a block as target");
6227 assert(last_branch->label() == last_branch->block()->label(), "must be equal");
6228
6229 if (last_branch->info() == NULL) {
6230 if (last_branch->block() == code->at(i + 1)) {
6231
6232 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
6233
6234 // delete last branch instruction
6235 instructions->truncate(instructions->length() - 1);
6236
6237 } else {
6238 LIR_Op* prev_op = instructions->at(instructions->length() - 2);
6239 if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) {
6240 assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6241 LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
6242
6243 if (prev_branch->stub() == NULL) {
6244
6245 LIR_Op2* prev_cmp = NULL;
6246
6247 for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
6248 prev_op = instructions->at(j);
6249 if (prev_op->code() == lir_cmp) {
6250 assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2");
6251 prev_cmp = (LIR_Op2*)prev_op;
6252 assert(prev_branch->cond() == prev_cmp->condition(), "should be the same");
6253 }
6254 }
6255 assert(prev_cmp != NULL, "should have found comp instruction for branch");
6256 if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) {
6257
6258 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
6259
6260 // eliminate a conditional branch to the immediate successor
6261 prev_branch->change_block(last_branch->block());
6262 prev_branch->negate_cond();
6263 prev_cmp->set_condition(prev_branch->cond());
6264 instructions->truncate(instructions->length() - 1);
6265 }
6266 }
6267 }
6268 }
6269 }
6270 }
6271 }
6272
6273 DEBUG_ONLY(verify(code));
6274 }
6275
6276 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) {
6277 #ifdef ASSERT
6278 BitMap return_converted(BlockBegin::number_of_blocks());
6279 return_converted.clear();
6280 #endif
6281
6282 for (int i = code->length() - 1; i >= 0; i--) {
6283 BlockBegin* block = code->at(i);
6284 LIR_OpList* cur_instructions = block->lir()->instructions_list();
6285 LIR_Op* cur_last_op = cur_instructions->last();
6286
6287 assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6288 if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) {
6289 // the block contains only a label and a return
6290 // if a predecessor ends with an unconditional jump to this block, then the jump
6291 // can be replaced with a return instruction
6292 //
6293 // Note: the original block with only a return statement cannot be deleted completely
6294 // because the predecessors might have other (conditional) jumps to this block
6295 // -> this may lead to unnecesary return instructions in the final code
6296
6297 assert(cur_last_op->info() == NULL, "return instructions do not have debug information");
6298 assert(block->number_of_sux() == 0 ||
6299 (return_converted.at(block->block_id()) && block->number_of_sux() == 1),
6300 "blocks that end with return must not have successors");
6301
6302 assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1");
6303 LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr();
6304
6305 for (int j = block->number_of_preds() - 1; j >= 0; j--) {
6306 BlockBegin* pred = block->pred_at(j);
6307 LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6308 LIR_Op* pred_last_op = pred_instructions->last();
6309
6310 if (pred_last_op->code() == lir_branch) {
6311 assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6312 LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op;
6313
6314 if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
6315 // replace the jump to a return with a direct return
6316 // Note: currently the edge between the blocks is not deleted
6317 pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr));
6318 #ifdef ASSERT
6319 return_converted.set_bit(pred->block_id());
6320 #endif
6321 }
6322 }
6323 }
6324 }
6325 }
6326 }
6327
6328
6329 #ifdef ASSERT
6330 void ControlFlowOptimizer::verify(BlockList* code) {
6331 for (int i = 0; i < code->length(); i++) {
6332 BlockBegin* block = code->at(i);
6333 LIR_OpList* instructions = block->lir()->instructions_list();
6334
6335 int j;
6336 for (j = 0; j < instructions->length(); j++) {
6337 LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch();
6338
6339 if (op_branch != NULL) {
6340 assert(op_branch->block() == NULL || code->index_of(op_branch->block()) != -1, "branch target not valid");
6341 assert(op_branch->ublock() == NULL || code->index_of(op_branch->ublock()) != -1, "branch target not valid");
6342 }
6343 }
6344
6345 for (j = 0; j < block->number_of_sux() - 1; j++) {
6346 BlockBegin* sux = block->sux_at(j);
6347 assert(code->index_of(sux) != -1, "successor not valid");
6348 }
6349
6350 for (j = 0; j < block->number_of_preds() - 1; j++) {
6351 BlockBegin* pred = block->pred_at(j);
6352 assert(code->index_of(pred) != -1, "successor not valid");
6353 }
6354 }
6355 }
6356 #endif
6357
6358
6359 #ifndef PRODUCT
6360
6361 // Implementation of LinearStatistic
6362
6363 const char* LinearScanStatistic::counter_name(int counter_idx) {
6364 switch (counter_idx) {
6365 case counter_method: return "compiled methods";
6366 case counter_fpu_method: return "methods using fpu";
6367 case counter_loop_method: return "methods with loops";
6368 case counter_exception_method:return "methods with xhandler";
6369
6370 case counter_loop: return "loops";
6371 case counter_block: return "blocks";
6372 case counter_loop_block: return "blocks inside loop";
6373 case counter_exception_block: return "exception handler entries";
6374 case counter_interval: return "intervals";
6375 case counter_fixed_interval: return "fixed intervals";
6376 case counter_range: return "ranges";
6377 case counter_fixed_range: return "fixed ranges";
6378 case counter_use_pos: return "use positions";
6379 case counter_fixed_use_pos: return "fixed use positions";
6380 case counter_spill_slots: return "spill slots";
6381
6382 // counter for classes of lir instructions
6383 case counter_instruction: return "total instructions";
6384 case counter_label: return "labels";
6385 case counter_entry: return "method entries";
6386 case counter_return: return "method returns";
6387 case counter_call: return "method calls";
6388 case counter_move: return "moves";
6389 case counter_cmp: return "compare";
6390 case counter_cond_branch: return "conditional branches";
6391 case counter_uncond_branch: return "unconditional branches";
6392 case counter_stub_branch: return "branches to stub";
6393 case counter_alu: return "artithmetic + logic";
6394 case counter_alloc: return "allocations";
6395 case counter_sync: return "synchronisation";
6396 case counter_throw: return "throw";
6397 case counter_unwind: return "unwind";
6398 case counter_typecheck: return "type+null-checks";
6399 case counter_fpu_stack: return "fpu-stack";
6400 case counter_misc_inst: return "other instructions";
6401 case counter_other_inst: return "misc. instructions";
6402
6403 // counter for different types of moves
6404 case counter_move_total: return "total moves";
6405 case counter_move_reg_reg: return "register->register";
6406 case counter_move_reg_stack: return "register->stack";
6407 case counter_move_stack_reg: return "stack->register";
6408 case counter_move_stack_stack:return "stack->stack";
6409 case counter_move_reg_mem: return "register->memory";
6410 case counter_move_mem_reg: return "memory->register";
6411 case counter_move_const_any: return "constant->any";
6412
6413 case blank_line_1: return "";
6414 case blank_line_2: return "";
6415
6416 default: ShouldNotReachHere(); return "";
6417 }
6418 }
6419
6420 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) {
6421 if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
6422 return counter_method;
6423 } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) {
6424 return counter_block;
6425 } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) {
6426 return counter_instruction;
6427 } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) {
6428 return counter_move_total;
6429 }
6430 return invalid_counter;
6431 }
6432
6433 LinearScanStatistic::LinearScanStatistic() {
6434 for (int i = 0; i < number_of_counters; i++) {
6435 _counters_sum[i] = 0;
6436 _counters_max[i] = -1;
6437 }
6438
6439 }
6440
6441 // add the method-local numbers to the total sum
6442 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) {
6443 for (int i = 0; i < number_of_counters; i++) {
6444 _counters_sum[i] += method_statistic._counters_sum[i];
6445 _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]);
6446 }
6447 }
6448
6449 void LinearScanStatistic::print(const char* title) {
6450 if (CountLinearScan || TraceLinearScanLevel > 0) {
6451 tty->cr();
6452 tty->print_cr("***** LinearScan statistic - %s *****", title);
6453
6454 for (int i = 0; i < number_of_counters; i++) {
6455 if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
6456 tty->print("%25s: %8d", counter_name(i), _counters_sum[i]);
6457
6458 if (base_counter(i) != invalid_counter) {
6459 tty->print(" (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[base_counter(i)]);
6460 } else {
6461 tty->print(" ");
6462 }
6463
6464 if (_counters_max[i] >= 0) {
6465 tty->print("%8d", _counters_max[i]);
6466 }
6467 }
6468 tty->cr();
6469 }
6470 }
6471 }
6472
6473 void LinearScanStatistic::collect(LinearScan* allocator) {
6474 inc_counter(counter_method);
6475 if (allocator->has_fpu_registers()) {
6476 inc_counter(counter_fpu_method);
6477 }
6478 if (allocator->num_loops() > 0) {
6479 inc_counter(counter_loop_method);
6480 }
6481 inc_counter(counter_loop, allocator->num_loops());
6482 inc_counter(counter_spill_slots, allocator->max_spills());
6483
6484 int i;
6485 for (i = 0; i < allocator->interval_count(); i++) {
6486 Interval* cur = allocator->interval_at(i);
6487
6488 if (cur != NULL) {
6489 inc_counter(counter_interval);
6490 inc_counter(counter_use_pos, cur->num_use_positions());
6491 if (LinearScan::is_precolored_interval(cur)) {
6492 inc_counter(counter_fixed_interval);
6493 inc_counter(counter_fixed_use_pos, cur->num_use_positions());
6494 }
6495
6496 Range* range = cur->first();
6497 while (range != Range::end()) {
6498 inc_counter(counter_range);
6499 if (LinearScan::is_precolored_interval(cur)) {
6500 inc_counter(counter_fixed_range);
6501 }
6502 range = range->next();
6503 }
6504 }
6505 }
6506
6507 bool has_xhandlers = false;
6508 // Note: only count blocks that are in code-emit order
6509 for (i = 0; i < allocator->ir()->code()->length(); i++) {
6510 BlockBegin* cur = allocator->ir()->code()->at(i);
6511
6512 inc_counter(counter_block);
6513 if (cur->loop_depth() > 0) {
6514 inc_counter(counter_loop_block);
6515 }
6516 if (cur->is_set(BlockBegin::exception_entry_flag)) {
6517 inc_counter(counter_exception_block);
6518 has_xhandlers = true;
6519 }
6520
6521 LIR_OpList* instructions = cur->lir()->instructions_list();
6522 for (int j = 0; j < instructions->length(); j++) {
6523 LIR_Op* op = instructions->at(j);
6524
6525 inc_counter(counter_instruction);
6526
6527 switch (op->code()) {
6528 case lir_label: inc_counter(counter_label); break;
6529 case lir_std_entry:
6530 case lir_osr_entry: inc_counter(counter_entry); break;
6531 case lir_return: inc_counter(counter_return); break;
6532
6533 case lir_rtcall:
6534 case lir_static_call:
6535 case lir_optvirtual_call:
6536 case lir_virtual_call: inc_counter(counter_call); break;
6537
6538 case lir_move: {
6539 inc_counter(counter_move);
6540 inc_counter(counter_move_total);
6541
6542 LIR_Opr in = op->as_Op1()->in_opr();
6543 LIR_Opr res = op->as_Op1()->result_opr();
6544 if (in->is_register()) {
6545 if (res->is_register()) {
6546 inc_counter(counter_move_reg_reg);
6547 } else if (res->is_stack()) {
6548 inc_counter(counter_move_reg_stack);
6549 } else if (res->is_address()) {
6550 inc_counter(counter_move_reg_mem);
6551 } else {
6552 ShouldNotReachHere();
6553 }
6554 } else if (in->is_stack()) {
6555 if (res->is_register()) {
6556 inc_counter(counter_move_stack_reg);
6557 } else {
6558 inc_counter(counter_move_stack_stack);
6559 }
6560 } else if (in->is_address()) {
6561 assert(res->is_register(), "must be");
6562 inc_counter(counter_move_mem_reg);
6563 } else if (in->is_constant()) {
6564 inc_counter(counter_move_const_any);
6565 } else {
6566 ShouldNotReachHere();
6567 }
6568 break;
6569 }
6570
6571 case lir_cmp: inc_counter(counter_cmp); break;
6572
6573 case lir_branch:
6574 case lir_cond_float_branch: {
6575 LIR_OpBranch* branch = op->as_OpBranch();
6576 if (branch->block() == NULL) {
6577 inc_counter(counter_stub_branch);
6578 } else if (branch->cond() == lir_cond_always) {
6579 inc_counter(counter_uncond_branch);
6580 } else {
6581 inc_counter(counter_cond_branch);
6582 }
6583 break;
6584 }
6585
6586 case lir_neg:
6587 case lir_add:
6588 case lir_sub:
6589 case lir_mul:
6590 case lir_mul_strictfp:
6591 case lir_div:
6592 case lir_div_strictfp:
6593 case lir_rem:
6594 case lir_sqrt:
6595 case lir_sin:
6596 case lir_cos:
6597 case lir_abs:
6598 case lir_log10:
6599 case lir_log:
6600 case lir_pow:
6601 case lir_exp:
6602 case lir_logic_and:
6603 case lir_logic_or:
6604 case lir_logic_xor:
6605 case lir_shl:
6606 case lir_shr:
6607 case lir_ushr: inc_counter(counter_alu); break;
6608
6609 case lir_alloc_object:
6610 case lir_alloc_array: inc_counter(counter_alloc); break;
6611
6612 case lir_monaddr:
6613 case lir_lock:
6614 case lir_unlock: inc_counter(counter_sync); break;
6615
6616 case lir_throw: inc_counter(counter_throw); break;
6617
6618 case lir_unwind: inc_counter(counter_unwind); break;
6619
6620 case lir_null_check:
6621 case lir_leal:
6622 case lir_instanceof:
6623 case lir_checkcast:
6624 case lir_store_check: inc_counter(counter_typecheck); break;
6625
6626 case lir_fpop_raw:
6627 case lir_fxch:
6628 case lir_fld: inc_counter(counter_fpu_stack); break;
6629
6630 case lir_nop:
6631 case lir_push:
6632 case lir_pop:
6633 case lir_convert:
6634 case lir_roundfp:
6635 case lir_cmove: inc_counter(counter_misc_inst); break;
6636
6637 default: inc_counter(counter_other_inst); break;
6638 }
6639 }
6640 }
6641
6642 if (has_xhandlers) {
6643 inc_counter(counter_exception_method);
6644 }
6645 }
6646
6647 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
6648 if (CountLinearScan || TraceLinearScanLevel > 0) {
6649
6650 LinearScanStatistic local_statistic = LinearScanStatistic();
6651
6652 local_statistic.collect(allocator);
6653 global_statistic.sum_up(local_statistic);
6654
6655 if (TraceLinearScanLevel > 2) {
6656 local_statistic.print("current local statistic");
6657 }
6658 }
6659 }
6660
6661
6662 // Implementation of LinearTimers
6663
6664 LinearScanTimers::LinearScanTimers() {
6665 for (int i = 0; i < number_of_timers; i++) {
6666 timer(i)->reset();
6667 }
6668 }
6669
6670 const char* LinearScanTimers::timer_name(int idx) {
6671 switch (idx) {
6672 case timer_do_nothing: return "Nothing (Time Check)";
6673 case timer_number_instructions: return "Number Instructions";
6674 case timer_compute_local_live_sets: return "Local Live Sets";
6675 case timer_compute_global_live_sets: return "Global Live Sets";
6676 case timer_build_intervals: return "Build Intervals";
6677 case timer_sort_intervals_before: return "Sort Intervals Before";
6678 case timer_allocate_registers: return "Allocate Registers";
6679 case timer_resolve_data_flow: return "Resolve Data Flow";
6680 case timer_sort_intervals_after: return "Sort Intervals After";
6681 case timer_eliminate_spill_moves: return "Spill optimization";
6682 case timer_assign_reg_num: return "Assign Reg Num";
6683 case timer_allocate_fpu_stack: return "Allocate FPU Stack";
6684 case timer_optimize_lir: return "Optimize LIR";
6685 default: ShouldNotReachHere(); return "";
6686 }
6687 }
6688
6689 void LinearScanTimers::begin_method() {
6690 if (TimeEachLinearScan) {
6691 // reset all timers to measure only current method
6692 for (int i = 0; i < number_of_timers; i++) {
6693 timer(i)->reset();
6694 }
6695 }
6696 }
6697
6698 void LinearScanTimers::end_method(LinearScan* allocator) {
6699 if (TimeEachLinearScan) {
6700
6701 double c = timer(timer_do_nothing)->seconds();
6702 double total = 0;
6703 for (int i = 1; i < number_of_timers; i++) {
6704 total += timer(i)->seconds() - c;
6705 }
6706
6707 if (total >= 0.0005) {
6708 // print all information in one line for automatic processing
6709 tty->print("@"); allocator->compilation()->method()->print_name();
6710
6711 tty->print("@ %d ", allocator->compilation()->method()->code_size());
6712 tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
6713 tty->print("@ %d ", allocator->block_count());
6714 tty->print("@ %d ", allocator->num_virtual_regs());
6715 tty->print("@ %d ", allocator->interval_count());
6716 tty->print("@ %d ", allocator->_num_calls);
6717 tty->print("@ %d ", allocator->num_loops());
6718
6719 tty->print("@ %6.6f ", total);
6720 for (int i = 1; i < number_of_timers; i++) {
6721 tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100);
6722 }
6723 tty->cr();
6724 }
6725 }
6726 }
6727
6728 void LinearScanTimers::print(double total_time) {
6729 if (TimeLinearScan) {
6730 // correction value: sum of dummy-timer that only measures the time that
6731 // is necesary to start and stop itself
6732 double c = timer(timer_do_nothing)->seconds();
6733
6734 for (int i = 0; i < number_of_timers; i++) {
6735 double t = timer(i)->seconds();
6736 tty->print_cr(" %25s: %6.3f s (%4.1f%%) corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
6737 }
6738 }
6739 }
6740
6741 #endif // #ifndef PRODUCT