1273 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1274 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1275 }
1276
1277 // temp ranges for fpu registers are only created when the method has
1278 // virtual fpu operands. Otherwise no allocation for fpu registers is
1279 // perfomed and so the temp ranges would be useless
1280 if (has_fpu_registers()) {
1281 #ifdef X86
1282 if (UseSSE < 2) {
1283 #endif
1284 for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1285 LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1286 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1287 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1288 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1289 }
1290 #ifdef X86
1291 }
1292 if (UseSSE > 0) {
1293 for (i = 0; i < FrameMap::nof_caller_save_xmm_regs; i++) {
1294 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1295 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1296 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1297 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1298 }
1299 }
1300 #endif
1301 }
1302 assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1303
1304
1305 LIR_OpVisitState visitor;
1306
1307 // iterate all blocks in reverse order
1308 for (i = block_count() - 1; i >= 0; i--) {
1309 BlockBegin* block = block_at(i);
1310 LIR_OpList* instructions = block->lir()->instructions_list();
1311 int block_from = block->first_lir_instruction_id();
1312 int block_to = block->last_lir_instruction_id();
1313
2081 assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2082 if (requires_adjacent_regs(T_LONG)) {
2083 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2084 }
2085
2086 #ifdef _LP64
2087 return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2088 #else
2089 #if defined(SPARC) || defined(PPC)
2090 return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
2091 #else
2092 return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2093 #endif // SPARC
2094 #endif // LP64
2095 }
2096
2097 #ifndef __SOFTFP__
2098 case T_FLOAT: {
2099 #ifdef X86
2100 if (UseSSE >= 1) {
2101 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
2102 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2103 return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2104 }
2105 #endif
2106
2107 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2108 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2109 return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2110 }
2111
2112 case T_DOUBLE: {
2113 #ifdef X86
2114 if (UseSSE >= 2) {
2115 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
2116 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2117 return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2118 }
2119 #endif
2120
2121 #ifdef SPARC
2122 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2123 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2124 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2125 LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
2126 #elif defined(ARM32)
2127 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2128 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2129 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2130 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2131 #else
2132 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2133 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2134 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2135 #endif
3583
3584 // When an operand is marked with is_last_use, then the fpu stack allocator
3585 // removes the register from the fpu stack -> the register contains no value
3586 if (opr->is_last_use()) {
3587 state_put(input_state, interval->assigned_reg(), NULL);
3588 state_put(input_state, interval->assigned_regHi(), NULL);
3589 }
3590 }
3591 }
3592
3593 // invalidate all caller save registers at calls
3594 if (visitor.has_call()) {
3595 for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
3596 state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
3597 }
3598 for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3599 state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
3600 }
3601
3602 #ifdef X86
3603 for (j = 0; j < FrameMap::nof_caller_save_xmm_regs; j++) {
3604 state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
3605 }
3606 #endif
3607 }
3608
3609 // process xhandler before output and temp operands
3610 XHandlers* xhandlers = visitor.all_xhandler();
3611 n = xhandlers->length();
3612 for (int k = 0; k < n; k++) {
3613 process_xhandler(xhandlers->handler_at(k), input_state);
3614 }
3615
3616 // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
3617 n = visitor.opr_count(LIR_OpVisitState::tempMode);
3618 for (j = 0; j < n; j++) {
3619 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3620 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3621 Interval* interval = interval_at(reg_num(opr));
3622 if (op->id() != -1) {
3623 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
4497 return true;
4498 }
4499
4500 cur = cur->next();
4501 }
4502
4503 return false;
4504 }
4505
4506
4507 #ifndef PRODUCT
4508 void Interval::print(outputStream* out) const {
4509 const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4510 const char* UseKind2Name[] = { "N", "L", "S", "M" };
4511
4512 const char* type_name;
4513 LIR_Opr opr = LIR_OprFact::illegal();
4514 if (reg_num() < LIR_OprDesc::vreg_base) {
4515 type_name = "fixed";
4516 // need a temporary operand for fixed intervals because type() cannot be called
4517 if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) {
4518 opr = LIR_OprFact::single_cpu(assigned_reg());
4519 } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) {
4520 opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg);
4521 #ifdef X86
4522 } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= pd_last_xmm_reg) {
4523 opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg);
4524 #endif
4525 } else {
4526 ShouldNotReachHere();
4527 }
4528 } else {
4529 type_name = type2name(type());
4530 if (assigned_reg() != -1 &&
4531 (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4532 opr = LinearScan::calc_operand_for_interval(this);
4533 }
4534 }
4535
4536 out->print("%d %s ", reg_num(), type_name);
4537 if (opr->is_valid()) {
4538 out->print("\"");
4539 opr->print(out);
4540 out->print("\" ");
4541 }
4542 out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
|
1273 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1274 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1275 }
1276
1277 // temp ranges for fpu registers are only created when the method has
1278 // virtual fpu operands. Otherwise no allocation for fpu registers is
1279 // perfomed and so the temp ranges would be useless
1280 if (has_fpu_registers()) {
1281 #ifdef X86
1282 if (UseSSE < 2) {
1283 #endif
1284 for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1285 LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1286 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1287 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1288 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1289 }
1290 #ifdef X86
1291 }
1292 if (UseSSE > 0) {
1293 int num_caller_save_xmm_regs = FrameMap::nof_caller_save_xmm_regs;
1294 #if _LP64
1295 if (UseAVX < 3) {
1296 num_caller_save_xmm_regs = num_caller_save_xmm_regs / 2;
1297 }
1298 #endif
1299 for (i = 0; i < num_caller_save_xmm_regs; i ++) {
1300 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1301 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1302 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1303 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1304 }
1305 }
1306 #endif
1307 }
1308 assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1309
1310
1311 LIR_OpVisitState visitor;
1312
1313 // iterate all blocks in reverse order
1314 for (i = block_count() - 1; i >= 0; i--) {
1315 BlockBegin* block = block_at(i);
1316 LIR_OpList* instructions = block->lir()->instructions_list();
1317 int block_from = block->first_lir_instruction_id();
1318 int block_to = block->last_lir_instruction_id();
1319
2087 assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2088 if (requires_adjacent_regs(T_LONG)) {
2089 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2090 }
2091
2092 #ifdef _LP64
2093 return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2094 #else
2095 #if defined(SPARC) || defined(PPC)
2096 return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
2097 #else
2098 return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2099 #endif // SPARC
2100 #endif // LP64
2101 }
2102
2103 #ifndef __SOFTFP__
2104 case T_FLOAT: {
2105 #ifdef X86
2106 if (UseSSE >= 1) {
2107 int last_xmm_reg = pd_last_xmm_reg;
2108 #ifdef _LP64
2109 if (UseAVX < 3) {
2110 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2111 }
2112 #endif
2113 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2114 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2115 return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2116 }
2117 #endif
2118
2119 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2120 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2121 return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2122 }
2123
2124 case T_DOUBLE: {
2125 #ifdef X86
2126 if (UseSSE >= 2) {
2127 int last_xmm_reg = pd_last_xmm_reg;
2128 #ifdef _LP64
2129 if (UseAVX < 3) {
2130 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2131 }
2132 #endif
2133 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2134 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2135 return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2136 }
2137 #endif
2138
2139 #ifdef SPARC
2140 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2141 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2142 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2143 LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
2144 #elif defined(ARM32)
2145 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2146 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2147 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2148 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2149 #else
2150 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2151 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2152 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2153 #endif
3601
3602 // When an operand is marked with is_last_use, then the fpu stack allocator
3603 // removes the register from the fpu stack -> the register contains no value
3604 if (opr->is_last_use()) {
3605 state_put(input_state, interval->assigned_reg(), NULL);
3606 state_put(input_state, interval->assigned_regHi(), NULL);
3607 }
3608 }
3609 }
3610
3611 // invalidate all caller save registers at calls
3612 if (visitor.has_call()) {
3613 for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
3614 state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
3615 }
3616 for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3617 state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
3618 }
3619
3620 #ifdef X86
3621 int num_caller_save_xmm_regs = FrameMap::nof_caller_save_xmm_regs;
3622 #if _LP64
3623 if (UseAVX < 3) {
3624 num_caller_save_xmm_regs = num_caller_save_xmm_regs / 2;
3625 }
3626 #endif
3627 for (j = 0; j < num_caller_save_xmm_regs; j++) {
3628 state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
3629 }
3630 #endif
3631 }
3632
3633 // process xhandler before output and temp operands
3634 XHandlers* xhandlers = visitor.all_xhandler();
3635 n = xhandlers->length();
3636 for (int k = 0; k < n; k++) {
3637 process_xhandler(xhandlers->handler_at(k), input_state);
3638 }
3639
3640 // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
3641 n = visitor.opr_count(LIR_OpVisitState::tempMode);
3642 for (j = 0; j < n; j++) {
3643 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3644 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3645 Interval* interval = interval_at(reg_num(opr));
3646 if (op->id() != -1) {
3647 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
4521 return true;
4522 }
4523
4524 cur = cur->next();
4525 }
4526
4527 return false;
4528 }
4529
4530
4531 #ifndef PRODUCT
4532 void Interval::print(outputStream* out) const {
4533 const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4534 const char* UseKind2Name[] = { "N", "L", "S", "M" };
4535
4536 const char* type_name;
4537 LIR_Opr opr = LIR_OprFact::illegal();
4538 if (reg_num() < LIR_OprDesc::vreg_base) {
4539 type_name = "fixed";
4540 // need a temporary operand for fixed intervals because type() cannot be called
4541 #ifdef X86
4542 int last_xmm_reg = pd_last_xmm_reg;
4543 #ifdef _LP64
4544 if (UseAVX < 3) {
4545 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
4546 }
4547 #endif
4548 #endif
4549 if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) {
4550 opr = LIR_OprFact::single_cpu(assigned_reg());
4551 } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) {
4552 opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg);
4553 #ifdef X86
4554 } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= last_xmm_reg) {
4555 opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg);
4556 #endif
4557 } else {
4558 ShouldNotReachHere();
4559 }
4560 } else {
4561 type_name = type2name(type());
4562 if (assigned_reg() != -1 &&
4563 (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4564 opr = LinearScan::calc_operand_for_interval(this);
4565 }
4566 }
4567
4568 out->print("%d %s ", reg_num(), type_name);
4569 if (opr->is_valid()) {
4570 out->print("\"");
4571 opr->print(out);
4572 out->print("\" ");
4573 }
4574 out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
|