890 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity");
891 assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity");
892 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
893 lrg.set_num_regs(RegMask::SlotsPerVecD);
894 lrg.set_reg_pressure(1);
895 break;
896 case Op_VecX:
897 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity");
898 assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity");
899 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
900 lrg.set_num_regs(RegMask::SlotsPerVecX);
901 lrg.set_reg_pressure(1);
902 break;
903 case Op_VecY:
904 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity");
905 assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity");
906 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned");
907 lrg.set_num_regs(RegMask::SlotsPerVecY);
908 lrg.set_reg_pressure(1);
909 break;
910 default:
911 ShouldNotReachHere();
912 }
913 }
914
915 // Now do the same for inputs
916 uint cnt = n->req();
917 // Setup for CISC SPILLING
918 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
919 if( UseCISCSpill && after_aggressive ) {
920 inp = n->cisc_operand();
921 if( inp != (uint)AdlcVMDeps::Not_cisc_spillable )
922 // Convert operand number to edge index number
923 inp = n->as_Mach()->operand_index(inp);
924 }
925 // Prepare register mask for each input
926 for( uint k = input_edge_start; k < cnt; k++ ) {
927 uint vreg = _lrg_map.live_range_id(n->in(k));
928 if (!vreg) {
929 continue;
1497 // Did we get a color?
1498 else if( OptoReg::is_valid(reg)) {
1499 #ifndef PRODUCT
1500 RegMask avail_rm = lrg->mask();
1501 #endif
1502
1503 // Record selected register
1504 lrg->set_reg(reg);
1505
1506 if( reg >= _max_reg ) // Compute max register limit
1507 _max_reg = OptoReg::add(reg,1);
1508 // Fold reg back into normal space
1509 reg = OptoReg::add(reg,-chunk);
1510
1511 // If the live range is not bound, then we actually had some choices
1512 // to make. In this case, the mask has more bits in it than the colors
1513 // chosen. Restrict the mask to just what was picked.
1514 int n_regs = lrg->num_regs();
1515 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1516 if (n_regs == 1 || !lrg->_fat_proj) {
1517 assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecY, "sanity");
1518 lrg->Clear(); // Clear the mask
1519 lrg->Insert(reg); // Set regmask to match selected reg
1520 // For vectors and pairs, also insert the low bit of the pair
1521 for (int i = 1; i < n_regs; i++)
1522 lrg->Insert(OptoReg::add(reg,-i));
1523 lrg->set_mask_size(n_regs);
1524 } else { // Else fatproj
1525 // mask must be equal to fatproj bits, by definition
1526 }
1527 #ifndef PRODUCT
1528 if (trace_spilling()) {
1529 ttyLocker ttyl;
1530 tty->print("L%d selected ", lidx);
1531 lrg->mask().dump();
1532 tty->print(" from ");
1533 avail_rm.dump();
1534 tty->cr();
1535 }
1536 #endif
1537 // Note that reg is the highest-numbered register in the newly-bound mask.
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890 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity");
891 assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity");
892 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
893 lrg.set_num_regs(RegMask::SlotsPerVecD);
894 lrg.set_reg_pressure(1);
895 break;
896 case Op_VecX:
897 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity");
898 assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity");
899 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
900 lrg.set_num_regs(RegMask::SlotsPerVecX);
901 lrg.set_reg_pressure(1);
902 break;
903 case Op_VecY:
904 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity");
905 assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity");
906 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned");
907 lrg.set_num_regs(RegMask::SlotsPerVecY);
908 lrg.set_reg_pressure(1);
909 break;
910 case Op_VecZ:
911 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecZ), "sanity");
912 assert(RegMask::num_registers(Op_VecZ) == RegMask::SlotsPerVecZ, "sanity");
913 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecZ), "vector should be aligned");
914 lrg.set_num_regs(RegMask::SlotsPerVecZ);
915 lrg.set_reg_pressure(1);
916 break;
917 default:
918 ShouldNotReachHere();
919 }
920 }
921
922 // Now do the same for inputs
923 uint cnt = n->req();
924 // Setup for CISC SPILLING
925 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
926 if( UseCISCSpill && after_aggressive ) {
927 inp = n->cisc_operand();
928 if( inp != (uint)AdlcVMDeps::Not_cisc_spillable )
929 // Convert operand number to edge index number
930 inp = n->as_Mach()->operand_index(inp);
931 }
932 // Prepare register mask for each input
933 for( uint k = input_edge_start; k < cnt; k++ ) {
934 uint vreg = _lrg_map.live_range_id(n->in(k));
935 if (!vreg) {
936 continue;
1504 // Did we get a color?
1505 else if( OptoReg::is_valid(reg)) {
1506 #ifndef PRODUCT
1507 RegMask avail_rm = lrg->mask();
1508 #endif
1509
1510 // Record selected register
1511 lrg->set_reg(reg);
1512
1513 if( reg >= _max_reg ) // Compute max register limit
1514 _max_reg = OptoReg::add(reg,1);
1515 // Fold reg back into normal space
1516 reg = OptoReg::add(reg,-chunk);
1517
1518 // If the live range is not bound, then we actually had some choices
1519 // to make. In this case, the mask has more bits in it than the colors
1520 // chosen. Restrict the mask to just what was picked.
1521 int n_regs = lrg->num_regs();
1522 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1523 if (n_regs == 1 || !lrg->_fat_proj) {
1524 assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecZ, "sanity");
1525 lrg->Clear(); // Clear the mask
1526 lrg->Insert(reg); // Set regmask to match selected reg
1527 // For vectors and pairs, also insert the low bit of the pair
1528 for (int i = 1; i < n_regs; i++)
1529 lrg->Insert(OptoReg::add(reg,-i));
1530 lrg->set_mask_size(n_regs);
1531 } else { // Else fatproj
1532 // mask must be equal to fatproj bits, by definition
1533 }
1534 #ifndef PRODUCT
1535 if (trace_spilling()) {
1536 ttyLocker ttyl;
1537 tty->print("L%d selected ", lidx);
1538 lrg->mask().dump();
1539 tty->print(" from ");
1540 avail_rm.dump();
1541 tty->cr();
1542 }
1543 #endif
1544 // Note that reg is the highest-numbered register in the newly-bound mask.
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