--- old/src/cpu/sparc/vm/vm_version_sparc.cpp	2015-08-25 15:39:49.000000000 -0700
+++ new/src/cpu/sparc/vm/vm_version_sparc.cpp	2015-08-25 15:39:49.000000000 -0700
@@ -359,7 +359,7 @@
   if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
     FLAG_SET_DEFAULT(UseSHA, false);
   }
-
+      
   // SPARC T4 and above should have support for CRC32C instruction
   if (has_crc32c()) {
     if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
@@ -377,6 +377,15 @@
     FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
   }
 
+  if (UseVIS > 2) {
+    if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
+      FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
+    }
+  } else if (UseAdler32Intrinsics) {
+    warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
+    FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
+  }
+
   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
     (cache_line_size > ContendedPaddingWidth))
     ContendedPaddingWidth = cache_line_size;