360     FLAG_SET_DEFAULT(UseSHA, false);
 361   }
 362 
 363   // SPARC T4 and above should have support for CRC32C instruction
 364   if (has_crc32c()) {
 365     if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
 366       if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 367         FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
 368       }
 369     } else {
 370       if (UseCRC32CIntrinsics) {
 371         warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
 372         FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
 373       }
 374     }
 375   } else if (UseCRC32CIntrinsics) {
 376     warning("CRC32C instruction is not available on this CPU");
 377     FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
 378   }
 379 









 380   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
 381     (cache_line_size > ContendedPaddingWidth))
 382     ContendedPaddingWidth = cache_line_size;
 383 
 384   // This machine does not allow unaligned memory accesses
 385   if (UseUnalignedAccesses) {
 386     if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
 387       warning("Unaligned memory access is not available on this CPU");
 388     FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
 389   }
 390 
 391 #ifndef PRODUCT
 392   if (PrintMiscellaneous && Verbose) {
 393     tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
 394     tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
 395     tty->print("Allocation");
 396     if (AllocatePrefetchStyle <= 0) {
 397       tty->print_cr(": no prefetching");
 398     } else {
 399       tty->print(" prefetching: ");

 360     FLAG_SET_DEFAULT(UseSHA, false);
 361   }
 362       
 363   // SPARC T4 and above should have support for CRC32C instruction
 364   if (has_crc32c()) {
 365     if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
 366       if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 367         FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
 368       }
 369     } else {
 370       if (UseCRC32CIntrinsics) {
 371         warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
 372         FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
 373       }
 374     }
 375   } else if (UseCRC32CIntrinsics) {
 376     warning("CRC32C instruction is not available on this CPU");
 377     FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
 378   }
 379 
 380   if (UseVIS > 2) {
 381     if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
 382       FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
 383     }
 384   } else if (UseAdler32Intrinsics) {
 385     warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
 386     FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
 387   }
 388 
 389   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
 390     (cache_line_size > ContendedPaddingWidth))
 391     ContendedPaddingWidth = cache_line_size;
 392 
 393   // This machine does not allow unaligned memory accesses
 394   if (UseUnalignedAccesses) {
 395     if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
 396       warning("Unaligned memory access is not available on this CPU");
 397     FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
 398   }
 399 
 400 #ifndef PRODUCT
 401   if (PrintMiscellaneous && Verbose) {
 402     tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
 403     tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
 404     tty->print("Allocation");
 405     if (AllocatePrefetchStyle <= 0) {
 406       tty->print_cr(": no prefetching");
 407     } else {
 408       tty->print(" prefetching: ");