1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "logging/log.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "runtime/java.hpp"
30 #include "runtime/os.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "vm_version_sparc.hpp"
33
34 unsigned int VM_Version::_L2_data_cache_line_size = 0;
35
36 void VM_Version::initialize() {
37 assert(_features != 0, "System pre-initialization is not complete.");
38 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
39
40 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
41 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
42 PrefetchFieldsAhead = prefetch_fields_ahead();
43
44 // Allocation prefetch settings
45 intx cache_line_size = prefetch_data_size();
46 if( cache_line_size > AllocatePrefetchStepSize )
47 AllocatePrefetchStepSize = cache_line_size;
48
49 AllocatePrefetchDistance = allocate_prefetch_distance();
50 AllocatePrefetchStyle = allocate_prefetch_style();
51
52 if (!has_blk_init()) {
53 if (AllocatePrefetchInstr == 1) {
54 warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
55 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
56 }
57 }
58
59 UseSSE = 0; // Only on x86 and x64
60
61 _supports_cx8 = has_v9();
62 _supports_atomic_getset4 = true; // swap instruction
63
64 if (is_niagara()) {
65 // Indirect branch is the same cost as direct
66 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
67 FLAG_SET_DEFAULT(UseInlineCaches, false);
68 }
69 // Align loops on a single instruction boundary.
70 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
71 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
72 }
73 #ifdef _LP64
74 // 32-bit oops don't make sense for the 64-bit VM on sparc
75 // since the 32-bit VM has the same registers and smaller objects.
76 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
77 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
78 #endif // _LP64
79 #ifdef COMPILER2
80 // Indirect branch is the same cost as direct
81 if (FLAG_IS_DEFAULT(UseJumpTables)) {
82 FLAG_SET_DEFAULT(UseJumpTables, true);
83 }
84 // Single-issue, so entry and loop tops are
85 // aligned on a single instruction boundary
86 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
87 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
88 }
89 if (is_niagara_plus()) {
90 if (has_blk_init() && UseTLAB &&
91 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
92 // Use BIS instruction for TLAB allocation prefetch.
93 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
94 }
95 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
96 if (AllocatePrefetchInstr == 0) {
97 // Use different prefetch distance without BIS
98 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
99 } else {
100 // Use smaller prefetch distance with BIS
101 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
102 }
103 }
104 if (is_T4()) {
105 // Double number of prefetched cache lines on T4
106 // since L2 cache line size is smaller (32 bytes).
107 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
108 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
109 }
110 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
111 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
112 }
113 }
114 }
115
116 if (AllocatePrefetchInstr == 1) {
117 // Use allocation prefetch style 3 because BIS instructions
118 // require aligned memory addresses.
119 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
120 }
121 #endif /* COMPILER2 */
122 }
123
124 // Use hardware population count instruction if available.
125 if (has_hardware_popc()) {
126 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
127 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
128 }
129 } else if (UsePopCountInstruction) {
130 warning("POPC instruction is not available on this CPU");
131 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
132 }
133
134 // T4 and newer Sparc cpus have new compare and branch instruction.
135 if (has_cbcond()) {
136 if (FLAG_IS_DEFAULT(UseCBCond)) {
137 FLAG_SET_DEFAULT(UseCBCond, true);
138 }
139 } else if (UseCBCond) {
140 warning("CBCOND instruction is not available on this CPU");
141 FLAG_SET_DEFAULT(UseCBCond, false);
142 }
143
144 assert(BlockZeroingLowLimit > 0, "invalid value");
145 if (has_block_zeroing() && cache_line_size > 0) {
146 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
147 FLAG_SET_DEFAULT(UseBlockZeroing, true);
148 }
149 } else if (UseBlockZeroing) {
150 warning("BIS zeroing instructions are not available on this CPU");
151 FLAG_SET_DEFAULT(UseBlockZeroing, false);
152 }
153
154 assert(BlockCopyLowLimit > 0, "invalid value");
155 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
156 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
157 FLAG_SET_DEFAULT(UseBlockCopy, true);
158 }
159 } else if (UseBlockCopy) {
160 warning("BIS instructions are not available or expensive on this CPU");
161 FLAG_SET_DEFAULT(UseBlockCopy, false);
162 }
163
164 #ifdef COMPILER2
165 // T4 and newer Sparc cpus have fast RDPC.
166 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
167 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
168 }
169
170 // Currently not supported anywhere.
171 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
172
173 MaxVectorSize = 8;
174
175 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
176 #endif
177
178 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
179 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
180
181 char buf[512];
182 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
183 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
184 (has_hardware_popc() ? ", popc" : ""),
185 (has_vis1() ? ", vis1" : ""),
186 (has_vis2() ? ", vis2" : ""),
187 (has_vis3() ? ", vis3" : ""),
188 (has_blk_init() ? ", blk_init" : ""),
189 (has_cbcond() ? ", cbcond" : ""),
190 (has_aes() ? ", aes" : ""),
191 (has_sha1() ? ", sha1" : ""),
192 (has_sha256() ? ", sha256" : ""),
193 (has_sha512() ? ", sha512" : ""),
194 (has_crc32c() ? ", crc32c" : ""),
195 (is_ultra3() ? ", ultra3" : ""),
196 (is_sun4v() ? ", sun4v" : ""),
197 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
198 (is_sparc64() ? ", sparc64" : ""),
199 (!has_hardware_mul32() ? ", no-mul32" : ""),
200 (!has_hardware_div32() ? ", no-div32" : ""),
201 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
202
203 // buf is started with ", " or is empty
204 _features_string = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
205
206 // UseVIS is set to the smallest of what hardware supports and what
207 // the command line requires. I.e., you cannot set UseVIS to 3 on
208 // older UltraSparc which do not support it.
209 if (UseVIS > 3) UseVIS=3;
210 if (UseVIS < 0) UseVIS=0;
211 if (!has_vis3()) // Drop to 2 if no VIS3 support
212 UseVIS = MIN2((intx)2,UseVIS);
213 if (!has_vis2()) // Drop to 1 if no VIS2 support
214 UseVIS = MIN2((intx)1,UseVIS);
215 if (!has_vis1()) // Drop to 0 if no VIS1 support
216 UseVIS = 0;
217
218 // SPARC T4 and above should have support for AES instructions
219 if (has_aes()) {
220 if (FLAG_IS_DEFAULT(UseAES)) {
221 FLAG_SET_DEFAULT(UseAES, true);
222 }
223 if (!UseAES) {
224 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
225 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
226 }
227 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
228 } else {
229 // The AES intrinsic stubs require AES instruction support (of course)
230 // but also require VIS3 mode or higher for instructions it use.
231 if (UseVIS > 2) {
232 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
233 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
234 }
235 } else {
236 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
237 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
238 }
239 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
240 }
241 }
242 } else if (UseAES || UseAESIntrinsics) {
243 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
244 warning("AES instructions are not available on this CPU");
245 FLAG_SET_DEFAULT(UseAES, false);
246 }
247 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
248 warning("AES intrinsics are not available on this CPU");
249 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
250 }
251 }
252
253 if (UseAESCTRIntrinsics) {
254 warning("AES/CTR intrinsics are not available on this CPU");
255 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
256 }
257
258 // GHASH/GCM intrinsics
259 if (has_vis3() && (UseVIS > 2)) {
260 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
261 UseGHASHIntrinsics = true;
262 }
263 } else if (UseGHASHIntrinsics) {
264 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
265 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
266 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
267 }
268
269 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
270 if (has_sha1() || has_sha256() || has_sha512()) {
271 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
272 if (FLAG_IS_DEFAULT(UseSHA)) {
273 FLAG_SET_DEFAULT(UseSHA, true);
274 }
275 } else {
276 if (UseSHA) {
277 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
278 FLAG_SET_DEFAULT(UseSHA, false);
279 }
280 }
281 } else if (UseSHA) {
282 warning("SHA instructions are not available on this CPU");
283 FLAG_SET_DEFAULT(UseSHA, false);
284 }
285
286 if (UseSHA && has_sha1()) {
287 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
288 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
289 }
290 } else if (UseSHA1Intrinsics) {
291 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
292 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
293 }
294
295 if (UseSHA && has_sha256()) {
296 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
297 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
298 }
299 } else if (UseSHA256Intrinsics) {
300 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
301 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
302 }
303
304 if (UseSHA && has_sha512()) {
305 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
306 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
307 }
308 } else if (UseSHA512Intrinsics) {
309 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
310 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
311 }
312
313 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
314 FLAG_SET_DEFAULT(UseSHA, false);
315 }
316
317 // SPARC T4 and above should have support for CRC32C instruction
318 if (has_crc32c()) {
319 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
320 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
321 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
322 }
323 } else {
324 if (UseCRC32CIntrinsics) {
325 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
326 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
327 }
328 }
329 } else if (UseCRC32CIntrinsics) {
330 warning("CRC32C instruction is not available on this CPU");
331 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
332 }
333
334 if (UseVIS > 2) {
335 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
336 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
337 }
338 } else if (UseAdler32Intrinsics) {
339 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
340 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
341 }
342
343 if (UseVIS > 2) {
344 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
345 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
346 }
347 } else if (UseCRC32Intrinsics) {
348 warning("SPARC CRC32 intrinsics require VIS3 insructions support. Intriniscs will be disabled");
349 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
350 }
351
352 if (UseVectorizedMismatchIntrinsic) {
353 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
354 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
355 }
356
357 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
358 (cache_line_size > ContendedPaddingWidth))
359 ContendedPaddingWidth = cache_line_size;
360
361 // This machine does not allow unaligned memory accesses
362 if (UseUnalignedAccesses) {
363 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
364 warning("Unaligned memory access is not available on this CPU");
365 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
366 }
367
368 if (log_is_enabled(Info, os, cpu)) {
369 ResourceMark rm;
370 outputStream* log = Log(os, cpu)::info_stream();
371 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
372 log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
373 log->print("Allocation");
374 if (AllocatePrefetchStyle <= 0) {
375 log->print(": no prefetching");
376 } else {
377 log->print(" prefetching: ");
378 if (AllocatePrefetchInstr == 0) {
379 log->print("PREFETCH");
380 } else if (AllocatePrefetchInstr == 1) {
381 log->print("BIS");
382 }
383 if (AllocatePrefetchLines > 1) {
384 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
385 } else {
386 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
387 }
388 }
389 if (PrefetchCopyIntervalInBytes > 0) {
390 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
391 }
392 if (PrefetchScanIntervalInBytes > 0) {
393 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
394 }
395 if (PrefetchFieldsAhead > 0) {
396 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
397 }
398 if (ContendedPaddingWidth > 0) {
399 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
400 }
401 }
402 }
403
404 void VM_Version::print_features() {
405 tty->print_cr("Version:%s", _features);
406 }
407
408 int VM_Version::determine_features() {
409 if (UseV8InstrsOnly) {
410 log_info(os, cpu)("Version is Forced-V8");
411 return generic_v8_m;
412 }
413
414 int features = platform_features(unknown_m); // platform_features() is os_arch specific
415
416 if (features == unknown_m) {
417 features = generic_v9_m;
418 log_info(os)("Cannot recognize SPARC version. Default to V9");
419 }
420
421 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
422 if (UseNiagaraInstrs) { // Force code generation for Niagara
423 if (is_T_family(features)) {
424 // Happy to accomodate...
425 } else {
426 log_info(os, cpu)("Version is Forced-Niagara");
427 features |= T_family_m;
428 }
429 } else {
430 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
431 log_info(os, cpu)("Version is Forced-Not-Niagara");
432 features &= ~(T_family_m | T1_model_m);
433 } else {
434 // Happy to accomodate...
435 }
436 }
437
438 return features;
439 }
440
441 static uint64_t saved_features = 0;
442
443 void VM_Version::allow_all() {
444 saved_features = _features;
445 _features = all_features_m;
446 }
447
448 void VM_Version::revert() {
449 _features = saved_features;
450 }
451
452 unsigned int VM_Version::calc_parallel_worker_threads() {
453 unsigned int result;
454 if (is_M_series()) {
455 // for now, use same gc thread calculation for M-series as for niagara-plus
456 // in future, we may want to tweak parameters for nof_parallel_worker_thread
457 result = nof_parallel_worker_threads(5, 16, 8);
458 } else if (is_niagara_plus()) {
459 result = nof_parallel_worker_threads(5, 16, 8);
460 } else {
461 result = nof_parallel_worker_threads(5, 8, 8);
462 }
463 return result;
464 }
465
466
467 int VM_Version::parse_features(const char* implementation) {
468 int features = unknown_m;
469 // Convert to UPPER case before compare.
470 char* impl = os::strdup_check_oom(implementation);
471
472 for (int i = 0; impl[i] != 0; i++)
473 impl[i] = (char)toupper((uint)impl[i]);
474
475 if (strstr(impl, "SPARC64") != NULL) {
476 features |= sparc64_family_m;
477 } else if (strstr(impl, "SPARC-M") != NULL) {
478 // M-series SPARC is based on T-series.
479 features |= (M_family_m | T_family_m);
480 } else if (strstr(impl, "SPARC-T") != NULL) {
481 features |= T_family_m;
482 if (strstr(impl, "SPARC-T1") != NULL) {
483 features |= T1_model_m;
484 }
485 } else {
486 if (strstr(impl, "SPARC") == NULL) {
487 #ifndef PRODUCT
488 // kstat on Solaris 8 virtual machines (branded zones)
489 // returns "(unsupported)" implementation. Solaris 8 is not
490 // supported anymore, but include this check to be on the
491 // safe side.
492 warning("Can't parse CPU implementation = '%s', assume generic SPARC", impl);
493 #endif
494 }
495 }
496 os::free((void*)impl);
497 return features;
498 }