src/cpu/sparc/vm/vm_version_sparc.cpp

*** 87,99 ****
        FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
      }
      if (is_niagara_plus()) {
        if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
            FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
!         // Use BIS instruction for TLAB allocation prefetch.
          FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
        }
        if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
          if (AllocatePrefetchInstr == 0) {
            // Use different prefetch distance without BIS
            FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
          } else {
--- 87,109 ----
        FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
      }
      if (is_niagara_plus()) {
        if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
            FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
!         if (!has_sparc5_instr()) {
!           // Use BIS instruction for TLAB allocation prefetch
!           // on Niagara plus processors other than those based on CoreS4
            FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
+         } else {
+           // On CoreS4 processors use prefetch instruction
+           // to avoid partial RAW issue, also use prefetch style 3
+           FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
+           if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
+             FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
            }
+         }
+       }
        if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
          if (AllocatePrefetchInstr == 0) {
            // Use different prefetch distance without BIS
            FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
          } else {