1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "logging/log.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "runtime/java.hpp"
30 #include "runtime/os.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "vm_version_sparc.hpp"
33
34 unsigned int VM_Version::_L2_data_cache_line_size = 0;
35
36 void VM_Version::initialize() {
37 assert(_features != 0, "System pre-initialization is not complete.");
38 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
39
40 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
41 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
42 PrefetchFieldsAhead = prefetch_fields_ahead();
43
44 // Allocation prefetch settings
45 intx cache_line_size = prefetch_data_size();
46 if( cache_line_size > AllocatePrefetchStepSize )
47 AllocatePrefetchStepSize = cache_line_size;
48
49 AllocatePrefetchDistance = allocate_prefetch_distance();
50 AllocatePrefetchStyle = allocate_prefetch_style();
51
52 if (!has_blk_init() || cache_line_size <= 0) {
53 if (AllocatePrefetchInstr == 1) {
54 warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
55 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
56 }
57 }
58
59 UseSSE = 0; // Only on x86 and x64
60
61 _supports_cx8 = has_v9();
62 _supports_atomic_getset4 = true; // swap instruction
63
64 if (is_niagara()) {
65 // Indirect branch is the same cost as direct
66 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
67 FLAG_SET_DEFAULT(UseInlineCaches, false);
68 }
69 // Align loops on a single instruction boundary.
70 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
71 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
72 }
73 #ifdef _LP64
74 // 32-bit oops don't make sense for the 64-bit VM on sparc
75 // since the 32-bit VM has the same registers and smaller objects.
76 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
77 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
78 #endif // _LP64
79 #ifdef COMPILER2
80 // Indirect branch is the same cost as direct
81 if (FLAG_IS_DEFAULT(UseJumpTables)) {
82 FLAG_SET_DEFAULT(UseJumpTables, true);
83 }
84 // Single-issue, so entry and loop tops are
85 // aligned on a single instruction boundary
86 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
87 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
88 }
89 if (is_niagara_plus()) {
90 if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
91 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
92 if (!has_sparc5_instr()) {
93 // Use BIS instruction for TLAB allocation prefetch
94 // on Niagara plus processors other than those based on CoreS4
95 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
96 } else {
97 // On CoreS4 processors use prefetch instruction
98 // to avoid partial RAW issue, also use prefetch style 3
99 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
100 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
101 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
102 }
103 }
104 }
105 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
106 if (AllocatePrefetchInstr == 0) {
107 // Use different prefetch distance without BIS
108 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
109 } else {
110 // Use smaller prefetch distance with BIS
111 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
112 }
113 }
114 if (is_T4()) {
115 // Double number of prefetched cache lines on T4
116 // since L2 cache line size is smaller (32 bytes).
117 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
118 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
119 }
120 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
121 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
122 }
123 }
124 }
125
126 if (AllocatePrefetchInstr == 1) {
127 // Use allocation prefetch style 3 because BIS instructions
128 // require aligned memory addresses.
129 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
130 }
131 #endif /* COMPILER2 */
132 }
133
134 // Use hardware population count instruction if available.
135 if (has_hardware_popc()) {
136 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
137 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
138 }
139 } else if (UsePopCountInstruction) {
140 warning("POPC instruction is not available on this CPU");
141 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
142 }
143
144 // T4 and newer Sparc cpus have new compare and branch instruction.
145 if (has_cbcond()) {
146 if (FLAG_IS_DEFAULT(UseCBCond)) {
147 FLAG_SET_DEFAULT(UseCBCond, true);
148 }
149 } else if (UseCBCond) {
150 warning("CBCOND instruction is not available on this CPU");
151 FLAG_SET_DEFAULT(UseCBCond, false);
152 }
153
154 assert(BlockZeroingLowLimit > 0, "invalid value");
155 if (has_block_zeroing() && cache_line_size > 0) {
156 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
157 FLAG_SET_DEFAULT(UseBlockZeroing, true);
158 }
159 } else if (UseBlockZeroing) {
160 warning("BIS zeroing instructions are not available on this CPU");
161 FLAG_SET_DEFAULT(UseBlockZeroing, false);
162 }
163
164 assert(BlockCopyLowLimit > 0, "invalid value");
165 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
166 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
167 FLAG_SET_DEFAULT(UseBlockCopy, true);
168 }
169 } else if (UseBlockCopy) {
170 warning("BIS instructions are not available or expensive on this CPU");
171 FLAG_SET_DEFAULT(UseBlockCopy, false);
172 }
173
174 #ifdef COMPILER2
175 // T4 and newer Sparc cpus have fast RDPC.
176 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
177 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
178 }
179
180 // Currently not supported anywhere.
181 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
182
183 MaxVectorSize = 8;
184
185 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
186 #endif
187
188 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
189 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
190
191 char buf[512];
192 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
193 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
194 (has_hardware_popc() ? ", popc" : ""),
195 (has_vis1() ? ", vis1" : ""),
196 (has_vis2() ? ", vis2" : ""),
197 (has_vis3() ? ", vis3" : ""),
198 (has_blk_init() ? ", blk_init" : ""),
199 (has_cbcond() ? ", cbcond" : ""),
200 (has_aes() ? ", aes" : ""),
201 (has_sha1() ? ", sha1" : ""),
202 (has_sha256() ? ", sha256" : ""),
203 (has_sha512() ? ", sha512" : ""),
204 (has_crc32c() ? ", crc32c" : ""),
205 (is_ultra3() ? ", ultra3" : ""),
206 (has_sparc5_instr() ? ", sparc5" : ""),
207 (is_sun4v() ? ", sun4v" : ""),
208 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
209 (is_sparc64() ? ", sparc64" : ""),
210 (!has_hardware_mul32() ? ", no-mul32" : ""),
211 (!has_hardware_div32() ? ", no-div32" : ""),
212 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
213
214 // buf is started with ", " or is empty
215 _features_string = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
216
217 // UseVIS is set to the smallest of what hardware supports and what
218 // the command line requires. I.e., you cannot set UseVIS to 3 on
219 // older UltraSparc which do not support it.
220 if (UseVIS > 3) UseVIS=3;
221 if (UseVIS < 0) UseVIS=0;
222 if (!has_vis3()) // Drop to 2 if no VIS3 support
223 UseVIS = MIN2((intx)2,UseVIS);
224 if (!has_vis2()) // Drop to 1 if no VIS2 support
225 UseVIS = MIN2((intx)1,UseVIS);
226 if (!has_vis1()) // Drop to 0 if no VIS1 support
227 UseVIS = 0;
228
229 // SPARC T4 and above should have support for AES instructions
230 if (has_aes()) {
231 if (FLAG_IS_DEFAULT(UseAES)) {
232 FLAG_SET_DEFAULT(UseAES, true);
233 }
234 if (!UseAES) {
235 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
236 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
237 }
238 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
239 } else {
240 // The AES intrinsic stubs require AES instruction support (of course)
241 // but also require VIS3 mode or higher for instructions it use.
242 if (UseVIS > 2) {
243 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
244 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
245 }
246 } else {
247 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
248 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
249 }
250 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
251 }
252 }
253 } else if (UseAES || UseAESIntrinsics) {
254 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
255 warning("AES instructions are not available on this CPU");
256 FLAG_SET_DEFAULT(UseAES, false);
257 }
258 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
259 warning("AES intrinsics are not available on this CPU");
260 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
261 }
262 }
263
264 if (UseAESCTRIntrinsics) {
265 warning("AES/CTR intrinsics are not available on this CPU");
266 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
267 }
268
269 // GHASH/GCM intrinsics
270 if (has_vis3() && (UseVIS > 2)) {
271 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
272 UseGHASHIntrinsics = true;
273 }
274 } else if (UseGHASHIntrinsics) {
275 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
276 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
277 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
278 }
279
280 if (UseFMA) {
281 warning("FMA instructions are not available on this CPU");
282 FLAG_SET_DEFAULT(UseFMA, false);
283 }
284
285 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
286 if (has_sha1() || has_sha256() || has_sha512()) {
287 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
288 if (FLAG_IS_DEFAULT(UseSHA)) {
289 FLAG_SET_DEFAULT(UseSHA, true);
290 }
291 } else {
292 if (UseSHA) {
293 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
294 FLAG_SET_DEFAULT(UseSHA, false);
295 }
296 }
297 } else if (UseSHA) {
298 warning("SHA instructions are not available on this CPU");
299 FLAG_SET_DEFAULT(UseSHA, false);
300 }
301
302 if (UseSHA && has_sha1()) {
303 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
304 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
305 }
306 } else if (UseSHA1Intrinsics) {
307 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
308 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
309 }
310
311 if (UseSHA && has_sha256()) {
312 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
313 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
314 }
315 } else if (UseSHA256Intrinsics) {
316 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
317 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
318 }
319
320 if (UseSHA && has_sha512()) {
321 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
322 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
323 }
324 } else if (UseSHA512Intrinsics) {
325 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
326 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
327 }
328
329 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
330 FLAG_SET_DEFAULT(UseSHA, false);
331 }
332
333 // SPARC T4 and above should have support for CRC32C instruction
334 if (has_crc32c()) {
335 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
336 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
337 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
338 }
339 } else {
340 if (UseCRC32CIntrinsics) {
341 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
342 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
343 }
344 }
345 } else if (UseCRC32CIntrinsics) {
346 warning("CRC32C instruction is not available on this CPU");
347 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
348 }
349
350 if (UseVIS > 2) {
351 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
352 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
353 }
354 } else if (UseAdler32Intrinsics) {
355 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
356 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
357 }
358
359 if (UseVIS > 2) {
360 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
361 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
362 }
363 } else if (UseCRC32Intrinsics) {
364 warning("SPARC CRC32 intrinsics require VIS3 instructions support. Intrinsics will be disabled");
365 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
366 }
367
368 if (UseVectorizedMismatchIntrinsic) {
369 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
370 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
371 }
372
373 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
374 (cache_line_size > ContendedPaddingWidth))
375 ContendedPaddingWidth = cache_line_size;
376
377 // This machine does not allow unaligned memory accesses
378 if (UseUnalignedAccesses) {
379 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
380 warning("Unaligned memory access is not available on this CPU");
381 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
382 }
383
384 if (log_is_enabled(Info, os, cpu)) {
385 ResourceMark rm;
386 outputStream* log = Log(os, cpu)::info_stream();
387 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
388 log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
389 log->print("Allocation");
390 if (AllocatePrefetchStyle <= 0) {
391 log->print(": no prefetching");
392 } else {
393 log->print(" prefetching: ");
394 if (AllocatePrefetchInstr == 0) {
395 log->print("PREFETCH");
396 } else if (AllocatePrefetchInstr == 1) {
397 log->print("BIS");
398 }
399 if (AllocatePrefetchLines > 1) {
400 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
401 } else {
402 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
403 }
404 }
405 if (PrefetchCopyIntervalInBytes > 0) {
406 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
407 }
408 if (PrefetchScanIntervalInBytes > 0) {
409 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
410 }
411 if (PrefetchFieldsAhead > 0) {
412 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
413 }
414 if (ContendedPaddingWidth > 0) {
415 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
416 }
417 }
418 }
419
420 void VM_Version::print_features() {
421 tty->print_cr("Version:%s", _features);
422 }
423
424 int VM_Version::determine_features() {
425 if (UseV8InstrsOnly) {
426 log_info(os, cpu)("Version is Forced-V8");
427 return generic_v8_m;
428 }
429
430 int features = platform_features(unknown_m); // platform_features() is os_arch specific
431
432 if (features == unknown_m) {
433 features = generic_v9_m;
434 log_info(os)("Cannot recognize SPARC version. Default to V9");
435 }
436
437 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
438 if (UseNiagaraInstrs) { // Force code generation for Niagara
439 if (is_T_family(features)) {
440 // Happy to accomodate...
441 } else {
442 log_info(os, cpu)("Version is Forced-Niagara");
443 features |= T_family_m;
444 }
445 } else {
446 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
447 log_info(os, cpu)("Version is Forced-Not-Niagara");
448 features &= ~(T_family_m | T1_model_m);
449 } else {
450 // Happy to accomodate...
451 }
452 }
453
454 return features;
455 }
456
457 static uint64_t saved_features = 0;
458
459 void VM_Version::allow_all() {
460 saved_features = _features;
461 _features = all_features_m;
462 }
463
464 void VM_Version::revert() {
465 _features = saved_features;
466 }
467
468 unsigned int VM_Version::calc_parallel_worker_threads() {
469 unsigned int result;
470 if (is_M_series() || is_S_series()) {
471 // for now, use same gc thread calculation for M-series and S-series as for
472 // niagara-plus. In future, we may want to tweak parameters for
473 // nof_parallel_worker_thread
474 result = nof_parallel_worker_threads(5, 16, 8);
475 } else if (is_niagara_plus()) {
476 result = nof_parallel_worker_threads(5, 16, 8);
477 } else {
478 result = nof_parallel_worker_threads(5, 8, 8);
479 }
480 return result;
481 }
482
483
484 int VM_Version::parse_features(const char* implementation) {
485 int features = unknown_m;
486 // Convert to UPPER case before compare.
487 char* impl = os::strdup_check_oom(implementation);
488
489 for (int i = 0; impl[i] != 0; i++)
490 impl[i] = (char)toupper((uint)impl[i]);
491
492 if (strstr(impl, "SPARC64") != NULL) {
493 features |= sparc64_family_m;
494 } else if (strstr(impl, "SPARC-M") != NULL) {
495 // M-series SPARC is based on T-series.
496 features |= (M_family_m | T_family_m);
497 } else if (strstr(impl, "SPARC-S") != NULL) {
498 // S-series SPARC is based on T-series.
499 features |= (S_family_m | T_family_m);
500 } else if (strstr(impl, "SPARC-T") != NULL) {
501 features |= T_family_m;
502 if (strstr(impl, "SPARC-T1") != NULL) {
503 features |= T1_model_m;
504 }
505 } else if (strstr(impl, "SUN4V-CPU") != NULL) {
506 // Generic or migration class LDOM
507 features |= T_family_m;
508 } else {
509 log_info(os, cpu)("Failed to parse CPU implementation = '%s'", impl);
510 }
511 os::free((void*)impl);
512 return features;
513 }