src/share/vm/opto/macro.cpp

@@ -1950,11 +1950,11 @@
       needgc_false = pf_region;
       contended_phi_rawmem = pf_phi_rawmem;
       i_o = pf_phi_abio;
    } else if( UseTLAB && AllocatePrefetchStyle == 3 ) {
       // Insert a prefetch instruction for each allocation.
-      // This code is used for SPARC with BIS.
+      // This code is used to generate 1 prefetch instruction per cache line.
 
       // Generate several prefetch instructions.
       uint lines = (length != NULL) ? AllocatePrefetchLines : AllocateInstancePrefetchLines;
       uint step_size = AllocatePrefetchStepSize;
       uint distance = AllocatePrefetchDistance;

@@ -1963,15 +1963,12 @@
       Node *cache_adr = new AddPNode(old_eden_top, old_eden_top,
                                      _igvn.MakeConX(step_size + distance));
       transform_later(cache_adr);
       cache_adr = new CastP2XNode(needgc_false, cache_adr);
       transform_later(cache_adr);
-      // For BIS instructions to be emitted, the address must be aligned at cache line size.
-      // (The VM sets AllocatePrefetchStepSize to the cache line size, unless a value is
-      // specified at the command line.) If the address is not aligned at cache line size
-      // boundary, a standard store instruction is triggered (instead of the BIS). For the
-      // latter, 8-byte alignment is necessary.
+      // Address is aligned to execute prefetch to the beginning of cache line size
+      // (it is important when BIS instruction is used on SPARC as prefetch).
       Node* mask = _igvn.MakeConX(~(intptr_t)(step_size-1));
       cache_adr = new AndXNode(cache_adr, mask);
       transform_later(cache_adr);
       cache_adr = new CastX2PNode(cache_adr);
       transform_later(cache_adr);