1 /*
   2  * Copyright (c) 2015, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  */
  23 package org.graalvm.compiler.lir.amd64;
  24 
  25 import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.DIV;
  26 import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.IDIV;
  27 import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.IMUL;
  28 import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.MUL;
  29 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.ILLEGAL;
  30 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG;
  31 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.STACK;
  32 import static jdk.vm.ci.code.ValueUtil.asRegister;
  33 import static jdk.vm.ci.code.ValueUtil.isIllegal;
  34 import static jdk.vm.ci.code.ValueUtil.isRegister;
  35 import static jdk.vm.ci.code.ValueUtil.isStackSlot;
  36 
  37 import org.graalvm.compiler.asm.amd64.AMD64Address;
  38 import org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp;
  39 import org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize;
  40 import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler;
  41 import org.graalvm.compiler.core.common.LIRKind;
  42 import org.graalvm.compiler.lir.LIRFrameState;
  43 import org.graalvm.compiler.lir.LIRInstructionClass;
  44 import org.graalvm.compiler.lir.Opcode;
  45 import org.graalvm.compiler.lir.asm.CompilationResultBuilder;
  46 
  47 import jdk.vm.ci.amd64.AMD64;
  48 import jdk.vm.ci.meta.AllocatableValue;
  49 import jdk.vm.ci.meta.Value;
  50 
  51 /**
  52  * AMD64 mul/div operation. This operation has a single operand for the second input. The first
  53  * input must be in RAX for mul and in RDX:RAX for div. The result is in RDX:RAX.
  54  */
  55 public class AMD64MulDivOp extends AMD64LIRInstruction {
  56     public static final LIRInstructionClass<AMD64MulDivOp> TYPE = LIRInstructionClass.create(AMD64MulDivOp.class);
  57 
  58     @Opcode private final AMD64MOp opcode;
  59     private final OperandSize size;
  60 
  61     @Def({REG}) protected AllocatableValue highResult;
  62     @Def({REG}) protected AllocatableValue lowResult;
  63 
  64     @Use({REG, ILLEGAL}) protected AllocatableValue highX;
  65     @Use({REG}) protected AllocatableValue lowX;
  66 
  67     @Use({REG, STACK}) protected AllocatableValue y;
  68 
  69     @State protected LIRFrameState state;
  70 
  71     public AMD64MulDivOp(AMD64MOp opcode, OperandSize size, LIRKind resultKind, AllocatableValue x, AllocatableValue y) {
  72         this(opcode, size, resultKind, Value.ILLEGAL, x, y, null);
  73     }
  74 
  75     public AMD64MulDivOp(AMD64MOp opcode, OperandSize size, LIRKind resultKind, AllocatableValue highX, AllocatableValue lowX, AllocatableValue y, LIRFrameState state) {
  76         super(TYPE);
  77         this.opcode = opcode;
  78         this.size = size;
  79 
  80         this.highResult = AMD64.rdx.asValue(resultKind);
  81         this.lowResult = AMD64.rax.asValue(resultKind);
  82 
  83         this.highX = highX;
  84         this.lowX = lowX;
  85 
  86         this.y = y;
  87 
  88         this.state = state;
  89     }
  90 
  91     public AllocatableValue getHighResult() {
  92         return highResult;
  93     }
  94 
  95     public AllocatableValue getLowResult() {
  96         return lowResult;
  97     }
  98 
  99     public AllocatableValue getQuotient() {
 100         return lowResult;
 101     }
 102 
 103     public AllocatableValue getRemainder() {
 104         return highResult;
 105     }
 106 
 107     @Override
 108     public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
 109         if (state != null) {
 110             crb.recordImplicitException(masm.position(), state);
 111         }
 112         if (isRegister(y)) {
 113             opcode.emit(masm, size, asRegister(y));
 114         } else {
 115             assert isStackSlot(y);
 116             opcode.emit(masm, size, (AMD64Address) crb.asAddress(y));
 117         }
 118     }
 119 
 120     @Override
 121     public void verify() {
 122         assert asRegister(highResult).equals(AMD64.rdx);
 123         assert asRegister(lowResult).equals(AMD64.rax);
 124 
 125         assert asRegister(lowX).equals(AMD64.rax);
 126         if (opcode == DIV || opcode == IDIV) {
 127             assert asRegister(highX).equals(AMD64.rdx);
 128         } else if (opcode == MUL || opcode == IMUL) {
 129             assert isIllegal(highX);
 130         }
 131     }
 132 }