436 int slot = 0; // counted in 32-bit VMReg slots
437 int reg = 0;
438 int fp_reg = 0;
439 for (int i = 0; i < total_args_passed; i++) {
440 switch (sig_bt[i]) {
441 case T_SHORT:
442 case T_CHAR:
443 case T_BYTE:
444 case T_BOOLEAN:
445 case T_INT:
446 if (reg < GPR_PARAMS) {
447 Register r = as_Register(reg);
448 regs[i].set1(r->as_VMReg());
449 reg++;
450 } else {
451 regs[i].set1(VMRegImpl::stack2reg(slot));
452 slot+=2;
453 }
454 break;
455 case T_LONG:
456 assert(sig_bt[i+1] == T_VOID, "missing Half" );
457 // fall through
458 case T_ARRAY:
459 case T_OBJECT:
460 case T_ADDRESS:
461 if (reg < GPR_PARAMS) {
462 Register r = as_Register(reg);
463 regs[i].set2(r->as_VMReg());
464 reg++;
465 } else {
466 regs[i].set2(VMRegImpl::stack2reg(slot));
467 slot+=2;
468 }
469 break;
470 case T_FLOAT:
471 if (fp_reg < FPR_PARAMS) {
472 FloatRegister r = as_FloatRegister(fp_reg);
473 regs[i].set1(r->as_VMReg());
474 fp_reg++;
475 } else {
476 regs[i].set1(VMRegImpl::stack2reg(slot));
477 slot+=2;
478 }
479 break;
480 case T_DOUBLE:
481 assert(sig_bt[i+1] == T_VOID, "missing Half" );
482 if (fp_reg < FPR_PARAMS) {
483 FloatRegister r = as_FloatRegister(fp_reg);
484 regs[i].set2(r->as_VMReg());
485 fp_reg++;
486 } else {
487 regs[i].set2(VMRegImpl::stack2reg(slot));
488 slot+=2;
489 }
490 break;
491 case T_VOID:
492 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
493 regs[i].set_bad();
494 break;
495 default:
496 ShouldNotReachHere();
497 }
498 }
499 return slot;
500
501 #else // AARCH64
515 case T_INT:
516 case T_ARRAY:
517 case T_OBJECT:
518 case T_ADDRESS:
519 #ifndef __ABI_HARD__
520 case T_FLOAT:
521 #endif // !__ABI_HARD__
522 if (ireg < 4) {
523 Register r = as_Register(ireg);
524 regs[i].set1(r->as_VMReg());
525 ireg++;
526 } else {
527 regs[i].set1(VMRegImpl::stack2reg(slot));
528 slot++;
529 }
530 break;
531 case T_LONG:
532 #ifndef __ABI_HARD__
533 case T_DOUBLE:
534 #endif // !__ABI_HARD__
535 assert(sig_bt[i+1] == T_VOID, "missing Half" );
536 if (ireg <= 2) {
537 #if (ALIGN_WIDE_ARGUMENTS == 1)
538 if(ireg & 1) ireg++; // Aligned location required
539 #endif
540 Register r1 = as_Register(ireg);
541 Register r2 = as_Register(ireg + 1);
542 regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());
543 ireg += 2;
544 #if (ALIGN_WIDE_ARGUMENTS == 0)
545 } else if (ireg == 3) {
546 // uses R3 + one stack slot
547 Register r = as_Register(ireg);
548 regs[i].set_pair(VMRegImpl::stack2reg(slot), r->as_VMReg());
549 ireg += 1;
550 slot += 1;
551 #endif
552 } else {
553 if (slot & 1) slot++; // Aligned location required
554 regs[i].set_pair(VMRegImpl::stack2reg(slot+1), VMRegImpl::stack2reg(slot));
555 slot += 2;
|
436 int slot = 0; // counted in 32-bit VMReg slots
437 int reg = 0;
438 int fp_reg = 0;
439 for (int i = 0; i < total_args_passed; i++) {
440 switch (sig_bt[i]) {
441 case T_SHORT:
442 case T_CHAR:
443 case T_BYTE:
444 case T_BOOLEAN:
445 case T_INT:
446 if (reg < GPR_PARAMS) {
447 Register r = as_Register(reg);
448 regs[i].set1(r->as_VMReg());
449 reg++;
450 } else {
451 regs[i].set1(VMRegImpl::stack2reg(slot));
452 slot+=2;
453 }
454 break;
455 case T_LONG:
456 assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
457 // fall through
458 case T_ARRAY:
459 case T_OBJECT:
460 case T_ADDRESS:
461 if (reg < GPR_PARAMS) {
462 Register r = as_Register(reg);
463 regs[i].set2(r->as_VMReg());
464 reg++;
465 } else {
466 regs[i].set2(VMRegImpl::stack2reg(slot));
467 slot+=2;
468 }
469 break;
470 case T_FLOAT:
471 if (fp_reg < FPR_PARAMS) {
472 FloatRegister r = as_FloatRegister(fp_reg);
473 regs[i].set1(r->as_VMReg());
474 fp_reg++;
475 } else {
476 regs[i].set1(VMRegImpl::stack2reg(slot));
477 slot+=2;
478 }
479 break;
480 case T_DOUBLE:
481 assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
482 if (fp_reg < FPR_PARAMS) {
483 FloatRegister r = as_FloatRegister(fp_reg);
484 regs[i].set2(r->as_VMReg());
485 fp_reg++;
486 } else {
487 regs[i].set2(VMRegImpl::stack2reg(slot));
488 slot+=2;
489 }
490 break;
491 case T_VOID:
492 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
493 regs[i].set_bad();
494 break;
495 default:
496 ShouldNotReachHere();
497 }
498 }
499 return slot;
500
501 #else // AARCH64
515 case T_INT:
516 case T_ARRAY:
517 case T_OBJECT:
518 case T_ADDRESS:
519 #ifndef __ABI_HARD__
520 case T_FLOAT:
521 #endif // !__ABI_HARD__
522 if (ireg < 4) {
523 Register r = as_Register(ireg);
524 regs[i].set1(r->as_VMReg());
525 ireg++;
526 } else {
527 regs[i].set1(VMRegImpl::stack2reg(slot));
528 slot++;
529 }
530 break;
531 case T_LONG:
532 #ifndef __ABI_HARD__
533 case T_DOUBLE:
534 #endif // !__ABI_HARD__
535 assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
536 if (ireg <= 2) {
537 #if (ALIGN_WIDE_ARGUMENTS == 1)
538 if(ireg & 1) ireg++; // Aligned location required
539 #endif
540 Register r1 = as_Register(ireg);
541 Register r2 = as_Register(ireg + 1);
542 regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());
543 ireg += 2;
544 #if (ALIGN_WIDE_ARGUMENTS == 0)
545 } else if (ireg == 3) {
546 // uses R3 + one stack slot
547 Register r = as_Register(ireg);
548 regs[i].set_pair(VMRegImpl::stack2reg(slot), r->as_VMReg());
549 ireg += 1;
550 slot += 1;
551 #endif
552 } else {
553 if (slot & 1) slot++; // Aligned location required
554 regs[i].set_pair(VMRegImpl::stack2reg(slot+1), VMRegImpl::stack2reg(slot));
555 slot += 2;
|