*** old/src/cpu/arm/vm/sharedRuntime_arm.cpp	Tue Dec 20 20:11:50 2016
--- new/src/cpu/arm/vm/sharedRuntime_arm.cpp	Tue Dec 20 20:11:50 2016

*** 451,461 ****
--- 451,461 ----
          regs[i].set1(VMRegImpl::stack2reg(slot));
          slot+=2;
        }
        break;
      case T_LONG:
!       assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
        // fall through
      case T_ARRAY:
      case T_OBJECT:
      case T_ADDRESS:
        if (reg < GPR_PARAMS) {

*** 476,486 ****
--- 476,486 ----
          regs[i].set1(VMRegImpl::stack2reg(slot));
          slot+=2;
        }
        break;
      case T_DOUBLE:
!       assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
        if (fp_reg < FPR_PARAMS) {
          FloatRegister r = as_FloatRegister(fp_reg);
          regs[i].set2(r->as_VMReg());
          fp_reg++;
        } else {

*** 530,540 ****
--- 530,540 ----
        break;
      case T_LONG:
  #ifndef __ABI_HARD__
      case T_DOUBLE:
  #endif // !__ABI_HARD__
!       assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
        if (ireg <= 2) {
  #if (ALIGN_WIDE_ARGUMENTS == 1)
          if(ireg & 1) ireg++;  // Aligned location required
  #endif
          Register r1 = as_Register(ireg);