1 /* 2 * Copyright (c) 2015, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 */ 23 package org.graalvm.compiler.lir.amd64; 24 25 import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.XOR; 26 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG; 27 import static jdk.vm.ci.code.ValueUtil.asRegister; 28 29 import org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64RMOp; 30 import org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize; 31 import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler; 32 import org.graalvm.compiler.lir.LIRInstructionClass; 33 import org.graalvm.compiler.lir.Opcode; 34 import org.graalvm.compiler.lir.asm.CompilationResultBuilder; 35 36 import jdk.vm.ci.meta.AllocatableValue; 37 38 public class AMD64ClearRegisterOp extends AMD64LIRInstruction { 39 public static final LIRInstructionClass<AMD64ClearRegisterOp> TYPE = LIRInstructionClass.create(AMD64ClearRegisterOp.class); 40 41 @Opcode private final AMD64RMOp op; 42 private final OperandSize size; 43 44 @Def({REG}) protected AllocatableValue result; 45 46 public AMD64ClearRegisterOp(OperandSize size, AllocatableValue result) { 47 super(TYPE); 48 this.op = XOR.getRMOpcode(size); 49 this.size = size; 50 this.result = result; 51 } 52 53 @Override 54 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) { 55 op.emit(masm, size, asRegister(result), asRegister(result)); 56 } 57 }