1 /*
2 * Copyright (c) 2015, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 */
23 package org.graalvm.compiler.lir.amd64;
24
25 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.COMPOSITE;
26 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.HINT;
27 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG;
28 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.STACK;
29 import static jdk.vm.ci.code.ValueUtil.asRegister;
30 import static jdk.vm.ci.code.ValueUtil.isRegister;
31 import static jdk.vm.ci.code.ValueUtil.isStackSlot;
32
33 import org.graalvm.compiler.asm.amd64.AMD64Address;
34 import org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp;
35 import org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MROp;
36 import org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64RMOp;
37 import org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize;
38 import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler;
39 import org.graalvm.compiler.lir.LIRFrameState;
40 import org.graalvm.compiler.lir.LIRInstructionClass;
41 import org.graalvm.compiler.lir.Opcode;
42 import org.graalvm.compiler.lir.StandardOp.ImplicitNullCheck;
43 import org.graalvm.compiler.lir.asm.CompilationResultBuilder;
44
45 import jdk.vm.ci.meta.AllocatableValue;
46 import jdk.vm.ci.meta.Value;
47
48 /**
49 * AMD64 LIR instructions that have one input and one output.
50 */
51 public class AMD64Unary {
52
53 /**
54 * Instruction with a single operand that is both input and output.
55 */
56 public static class MOp extends AMD64LIRInstruction {
57 public static final LIRInstructionClass<MOp> TYPE = LIRInstructionClass.create(MOp.class);
58
59 @Opcode private final AMD64MOp opcode;
60 private final OperandSize size;
61
62 @Def({REG, HINT}) protected AllocatableValue result;
63 @Use({REG, STACK}) protected AllocatableValue value;
64
65 public MOp(AMD64MOp opcode, OperandSize size, AllocatableValue result, AllocatableValue value) {
66 super(TYPE);
67 this.opcode = opcode;
68 this.size = size;
69
70 this.result = result;
71 this.value = value;
72 }
73
74 @Override
75 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
76 AMD64Move.move(crb, masm, result, value);
77 opcode.emit(masm, size, asRegister(result));
78 }
79 }
80
81 /**
82 * Instruction with separate input and output operands, and an operand encoding of RM.
83 */
84 public static class RMOp extends AMD64LIRInstruction {
85 public static final LIRInstructionClass<RMOp> TYPE = LIRInstructionClass.create(RMOp.class);
86
87 @Opcode private final AMD64RMOp opcode;
88 private final OperandSize size;
89
90 @Def({REG}) protected AllocatableValue result;
91 @Use({REG, STACK}) protected AllocatableValue value;
92
93 public RMOp(AMD64RMOp opcode, OperandSize size, AllocatableValue result, AllocatableValue value) {
94 super(TYPE);
95 this.opcode = opcode;
96 this.size = size;
97
98 this.result = result;
99 this.value = value;
100 }
101
102 @Override
103 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
104 if (isRegister(value)) {
105 opcode.emit(masm, size, asRegister(result), asRegister(value));
106 } else {
107 assert isStackSlot(value);
108 opcode.emit(masm, size, asRegister(result), (AMD64Address) crb.asAddress(value));
109 }
110 }
111 }
112
113 /**
114 * Instruction with separate input and output operands, and an operand encoding of MR.
115 */
116 public static class MROp extends AMD64LIRInstruction {
117 public static final LIRInstructionClass<MROp> TYPE = LIRInstructionClass.create(MROp.class);
118
119 @Opcode private final AMD64MROp opcode;
120 private final OperandSize size;
121
122 @Def({REG, STACK}) protected AllocatableValue result;
123 @Use({REG}) protected AllocatableValue value;
124
125 public MROp(AMD64MROp opcode, OperandSize size, AllocatableValue result, AllocatableValue value) {
126 super(TYPE);
127 this.opcode = opcode;
128 this.size = size;
129
130 this.result = result;
131 this.value = value;
132 }
133
134 @Override
135 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
136 if (isRegister(result)) {
137 opcode.emit(masm, size, asRegister(result), asRegister(value));
138 } else {
139 assert isStackSlot(result);
140 opcode.emit(masm, size, (AMD64Address) crb.asAddress(result), asRegister(value));
141 }
142 }
143 }
144
145 /**
146 * Instruction with a {@link AMD64AddressValue memory} operand.
147 */
148 public static class MemoryOp extends AMD64LIRInstruction implements ImplicitNullCheck {
149 public static final LIRInstructionClass<MemoryOp> TYPE = LIRInstructionClass.create(MemoryOp.class);
150
151 @Opcode private final AMD64RMOp opcode;
152 private final OperandSize size;
153
154 @Def({REG}) protected AllocatableValue result;
155 @Use({COMPOSITE}) protected AMD64AddressValue input;
156
157 @State protected LIRFrameState state;
158
159 public MemoryOp(AMD64RMOp opcode, OperandSize size, AllocatableValue result, AMD64AddressValue input, LIRFrameState state) {
160 super(TYPE);
161 this.opcode = opcode;
162 this.size = size;
163
164 this.result = result;
165 this.input = input;
166
167 this.state = state;
168 }
169
170 @Override
171 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
172 if (state != null) {
173 crb.recordImplicitException(masm.position(), state);
174 }
175 opcode.emit(masm, size, asRegister(result), input.toAddress());
176 }
177
178 @Override
179 public boolean makeNullCheckFor(Value value, LIRFrameState nullCheckState, int implicitNullCheckLimit) {
180 if (state == null && input.isValidImplicitNullCheckFor(value, implicitNullCheckLimit)) {
181 state = nullCheckState;
182 return true;
183 }
184 return false;
185 }
186 }
187 }