src/jdk.aot/share/classes/jdk.tools.jaotc/src/jdk/tools/jaotc/amd64/AMD64InstructionDecoder.java
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src/jdk.aot/share/classes/jdk.tools.jaotc/src/jdk/tools/jaotc/amd64/AMD64InstructionDecoder.java

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   1 /*
   2  * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  */
  23 
  24 package jdk.tools.jaotc.amd64;
  25 
  26 import jdk.tools.jaotc.InstructionDecoder;
  27 
  28 import jdk.vm.ci.code.TargetDescription;
  29 
  30 public final class AMD64InstructionDecoder extends InstructionDecoder {
  31 
  32     private boolean targetIs64Bit;
  33     private int currentEndOfInstruction;
  34 
  35     private static class Prefix {
  36 
  37         // segment overrides
  38         public static final int CSSegment = 0x2e;
  39         public static final int SSSegment = 0x36;
  40         public static final int DSSegment = 0x3e;
  41         public static final int ESSegment = 0x26;
  42         public static final int FSSegment = 0x64;
  43         public static final int GSSegment = 0x65;
  44         public static final int REX = 0x40;
  45         public static final int REXB = 0x41;
  46         public static final int REXX = 0x42;
  47         public static final int REXXB = 0x43;
  48         public static final int REXR = 0x44;
  49         public static final int REXRB = 0x45;
  50         public static final int REXRX = 0x46;
  51         public static final int REXRXB = 0x47;
  52         public static final int REXW = 0x48;
  53         public static final int REXWB = 0x49;
  54         public static final int REXWX = 0x4A;
  55         public static final int REXWXB = 0x4B;
  56         public static final int REXWR = 0x4C;
  57         public static final int REXWRB = 0x4D;
  58         public static final int REXWRX = 0x4E;
  59         public static final int REXWRXB = 0x4F;
  60         public static final int VEX_3BYTES = 0xC4;
  61         public static final int VEX_2BYTES = 0xC5;
  62     }
  63 
  64     public static class VexPrefix {
  65         public static final int VEX_R = 0x80;
  66         public static final int VEX_W = 0x80;
  67     }
  68 
  69     public static class VexOpcode {
  70         public static final int VEX_OPCODE_NONE = 0x0;
  71         public static final int VEX_OPCODE_0F = 0x1;
  72         public static final int VEX_OPCODE_0F_38 = 0x2;
  73         public static final int VEX_OPCODE_0F_3A = 0x3;
  74         public static final int VEX_OPCODE_MASK = 0x1F;
  75     }
  76 
  77     public AMD64InstructionDecoder(TargetDescription target) {
  78         this.targetIs64Bit = target.wordSize == 8;
  79     }
  80 
  81     @Override
  82     public int currentEndOfInstruction() {
  83         return currentEndOfInstruction;
  84     }
  85 
  86     @Override
  87     @SuppressWarnings("fallthrough")
  88     public void decodePosition(final byte[] code, int pcOffset) {
  89         assert pcOffset >= 0 && pcOffset < code.length;
  90 
  91         // Decode the given instruction, and return the Pointer of
  92         // an embedded 32-bit operand word.
  93 
  94         // If "which" is WhichOperand.disp32operand, selects the displacement portion


 429                         is64bit = ((VexPrefix.VEX_W & code[ip]) == VexPrefix.VEX_W);
 430                     } else {
 431                         vex_opcode = VexOpcode.VEX_OPCODE_0F;
 432                     }
 433                     ip++; // opcode
 434                     // To find the end of instruction (which == end_pc_operand).
 435                     switch (vex_opcode) {
 436                         case VexOpcode.VEX_OPCODE_0F:
 437                             switch (0xFF & code[ip]) {
 438                                 case 0x70: // pshufd r, r/a, #8
 439                                 case 0x71: // ps[rl|ra|ll]w r, #8
 440                                 case 0x72: // ps[rl|ra|ll]d r, #8
 441                                 case 0x73: // ps[rl|ra|ll]q r, #8
 442                                 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
 443                                 case 0xC4: // pinsrw r, r, r/a, #8
 444                                 case 0xC5: // pextrw r/a, r, #8
 445                                 case 0xC6: // shufp[s|d] r, r, r/a, #8
 446                                     tailSize = 1;  // the imm8
 447                                     break;
 448                                 default:
 449                                     ; // no imm8
 450                             }
 451                             break;
 452                         case VexOpcode.VEX_OPCODE_0F_3A:
 453                             tailSize = 1;
 454                             break;
 455                         default:
 456                             throw new InternalError("should not reach here");
 457                     }
 458                     ip++; // skip opcode
 459                     hasDisp32 = true;
 460                     break;
 461 
 462                 case 0xE8: // call rdisp32
 463                 case 0xE9: // jmp rdisp32
 464                     currentEndOfInstruction = ip + 4;
 465                     return;
 466 
 467                 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
 468                 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
 469                 case 0xD9: // fldS a; fstS a; fstpS a; fldcw a


   1 /*
   2  * Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  */
  23 
  24 package jdk.tools.jaotc.amd64;
  25 
  26 import jdk.tools.jaotc.InstructionDecoder;
  27 
  28 import jdk.vm.ci.code.TargetDescription;
  29 
  30 public final class AMD64InstructionDecoder extends InstructionDecoder {
  31 
  32     private boolean targetIs64Bit;
  33     private int currentEndOfInstruction;
  34 
  35     private static class Prefix {
  36 
  37         // segment overrides
  38         static final int CSSegment = 0x2e;
  39         static final int SSSegment = 0x36;
  40         static final int DSSegment = 0x3e;
  41         static final int ESSegment = 0x26;
  42         static final int FSSegment = 0x64;
  43         static final int GSSegment = 0x65;
  44         static final int REX = 0x40;
  45         static final int REXB = 0x41;
  46         static final int REXX = 0x42;
  47         static final int REXXB = 0x43;
  48         static final int REXR = 0x44;
  49         static final int REXRB = 0x45;
  50         static final int REXRX = 0x46;
  51         static final int REXRXB = 0x47;
  52         static final int REXW = 0x48;
  53         static final int REXWB = 0x49;
  54         static final int REXWX = 0x4A;
  55         static final int REXWXB = 0x4B;
  56         static final int REXWR = 0x4C;
  57         static final int REXWRB = 0x4D;
  58         static final int REXWRX = 0x4E;
  59         static final int REXWRXB = 0x4F;
  60         static final int VEX_3BYTES = 0xC4;
  61         static final int VEX_2BYTES = 0xC5;
  62     }
  63 
  64     private static class VexPrefix {
  65         static final int VEX_R = 0x80;
  66         static final int VEX_W = 0x80;
  67     }
  68 
  69     private static class VexOpcode {
  70         static final int VEX_OPCODE_NONE = 0x0;
  71         static final int VEX_OPCODE_0F = 0x1;
  72         static final int VEX_OPCODE_0F_38 = 0x2;
  73         static final int VEX_OPCODE_0F_3A = 0x3;
  74         static final int VEX_OPCODE_MASK = 0x1F;
  75     }
  76 
  77     public AMD64InstructionDecoder(TargetDescription target) {
  78         this.targetIs64Bit = target.wordSize == 8;
  79     }
  80 
  81     @Override
  82     public int currentEndOfInstruction() {
  83         return currentEndOfInstruction;
  84     }
  85 
  86     @Override
  87     @SuppressWarnings("fallthrough")
  88     public void decodePosition(final byte[] code, int pcOffset) {
  89         assert pcOffset >= 0 && pcOffset < code.length;
  90 
  91         // Decode the given instruction, and return the Pointer of
  92         // an embedded 32-bit operand word.
  93 
  94         // If "which" is WhichOperand.disp32operand, selects the displacement portion


 429                         is64bit = ((VexPrefix.VEX_W & code[ip]) == VexPrefix.VEX_W);
 430                     } else {
 431                         vex_opcode = VexOpcode.VEX_OPCODE_0F;
 432                     }
 433                     ip++; // opcode
 434                     // To find the end of instruction (which == end_pc_operand).
 435                     switch (vex_opcode) {
 436                         case VexOpcode.VEX_OPCODE_0F:
 437                             switch (0xFF & code[ip]) {
 438                                 case 0x70: // pshufd r, r/a, #8
 439                                 case 0x71: // ps[rl|ra|ll]w r, #8
 440                                 case 0x72: // ps[rl|ra|ll]d r, #8
 441                                 case 0x73: // ps[rl|ra|ll]q r, #8
 442                                 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
 443                                 case 0xC4: // pinsrw r, r, r/a, #8
 444                                 case 0xC5: // pextrw r/a, r, #8
 445                                 case 0xC6: // shufp[s|d] r, r, r/a, #8
 446                                     tailSize = 1;  // the imm8
 447                                     break;
 448                                 default:
 449                                     break; // no imm8
 450                             }
 451                             break;
 452                         case VexOpcode.VEX_OPCODE_0F_3A:
 453                             tailSize = 1;
 454                             break;
 455                         default:
 456                             throw new InternalError("should not reach here");
 457                     }
 458                     ip++; // skip opcode
 459                     hasDisp32 = true;
 460                     break;
 461 
 462                 case 0xE8: // call rdisp32
 463                 case 0xE9: // jmp rdisp32
 464                     currentEndOfInstruction = ip + 4;
 465                     return;
 466 
 467                 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
 468                 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
 469                 case 0xD9: // fldS a; fstS a; fstpS a; fldcw a


src/jdk.aot/share/classes/jdk.tools.jaotc/src/jdk/tools/jaotc/amd64/AMD64InstructionDecoder.java
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