1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx += 2 + ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && is_evex_instruction) {
398 switch (tuple_type) {
399 case EVEX_FV:
400 if ((evex_encoding & VEX_W) == VEX_W) {
401 mod_idx += 2 + ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
402 } else {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
404 }
405 break;
406
407 case EVEX_HV:
408 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
409 break;
410
411 case EVEX_FVM:
412 break;
413
414 case EVEX_T1S:
415 switch (input_size_in_bits) {
416 case EVEX_8bit:
417 break;
418
419 case EVEX_16bit:
420 mod_idx = 1;
421 break;
422
423 case EVEX_32bit:
424 mod_idx = 2;
425 break;
426
427 case EVEX_64bit:
428 mod_idx = 3;
429 break;
430 }
431 break;
432
433 case EVEX_T1F:
434 case EVEX_T2:
435 case EVEX_T4:
436 mod_idx = (input_size_in_bits == EVEX_64bit) ? 1 : 0;
437 break;
438
439 case EVEX_T8:
440 break;
441
442 case EVEX_HVM:
443 break;
444
445 case EVEX_QVM:
446 break;
447
448 case EVEX_OVM:
449 break;
450
451 case EVEX_M128:
452 break;
453
454 case EVEX_DUP:
455 break;
456
457 default:
458 assert(0, "no valid evex tuple_table entry");
459 break;
460 }
461
462 if (avx_vector_len >= AVX_128bit && avx_vector_len <= AVX_512bit) {
463 int disp_factor = tuple_table[tuple_type + mod_idx][avx_vector_len];
464 if ((disp % disp_factor) == 0) {
465 int new_disp = disp / disp_factor;
466 if (is8bit(new_disp)) {
467 disp = new_disp;
468 }
469 } else {
470 return false;
471 }
472 }
473 }
474 return is8bit(disp);
475 }
476
477
478 void Assembler::emit_operand(Register reg, Register base, Register index,
479 Address::ScaleFactor scale, int disp,
480 RelocationHolder const& rspec,
481 int rip_relative_correction) {
482 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
483
484 // Encode the registers as needed in the fields they are used in
485
486 int regenc = encode(reg) << 3;
487 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
488 int baseenc = base->is_valid() ? encode(base) : 0;
489
490 if (base->is_valid()) {
491 if (index->is_valid()) {
492 assert(scale != Address::no_scale, "inconsistent address");
493 // [base + index*scale + disp]
494 if (disp == 0 && rtype == relocInfo::none &&
495 base != rbp LP64_ONLY(&& base != r13)) {
496 // [base + index*scale]
497 // [00 reg 100][ss index base]
498 assert(index != rsp, "illegal addressing mode");
499 emit_int8(0x04 | regenc);
500 emit_int8(scale << 6 | indexenc | baseenc);
501 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
502 // [base + index*scale + imm8]
503 // [01 reg 100][ss index base] imm8
504 assert(index != rsp, "illegal addressing mode");
505 emit_int8(0x44 | regenc);
506 emit_int8(scale << 6 | indexenc | baseenc);
507 emit_int8(disp & 0xFF);
508 } else {
509 // [base + index*scale + disp32]
510 // [10 reg 100][ss index base] disp32
511 assert(index != rsp, "illegal addressing mode");
512 emit_int8(0x84 | regenc);
513 emit_int8(scale << 6 | indexenc | baseenc);
514 emit_data(disp, rspec, disp32_operand);
515 }
516 } else if (base == rsp LP64_ONLY(|| base == r12)) {
517 // [rsp + disp]
518 if (disp == 0 && rtype == relocInfo::none) {
519 // [rsp]
520 // [00 reg 100][00 100 100]
521 emit_int8(0x04 | regenc);
522 emit_int8(0x24);
523 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
524 // [rsp + imm8]
525 // [01 reg 100][00 100 100] disp8
526 emit_int8(0x44 | regenc);
527 emit_int8(0x24);
528 emit_int8(disp & 0xFF);
529 } else {
530 // [rsp + imm32]
531 // [10 reg 100][00 100 100] disp32
532 emit_int8(0x84 | regenc);
533 emit_int8(0x24);
534 emit_data(disp, rspec, disp32_operand);
535 }
536 } else {
537 // [base + disp]
538 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
539 if (disp == 0 && rtype == relocInfo::none &&
540 base != rbp LP64_ONLY(&& base != r13)) {
541 // [base]
542 // [00 reg base]
543 emit_int8(0x00 | regenc | baseenc);
544 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
545 // [base + disp8]
546 // [01 reg base] disp8
547 emit_int8(0x40 | regenc | baseenc);
548 emit_int8(disp & 0xFF);
549 } else {
550 // [base + disp32]
551 // [10 reg base] disp32
552 emit_int8(0x80 | regenc | baseenc);
553 emit_data(disp, rspec, disp32_operand);
554 }
555 }
556 } else {
557 if (index->is_valid()) {
558 assert(scale != Address::no_scale, "inconsistent address");
559 // [index*scale + disp]
560 // [00 reg 100][ss index 101] disp32
561 assert(index != rsp, "illegal addressing mode");
562 emit_int8(0x04 | regenc);
563 emit_int8(scale << 6 | indexenc | 0x05);
564 emit_data(disp, rspec, disp32_operand);
565 } else if (rtype != relocInfo::none ) {
566 // [disp] (64bit) RIP-RELATIVE (32bit) abs
567 // [00 000 101] disp32
568
569 emit_int8(0x05 | regenc);
570 // Note that the RIP-rel. correction applies to the generated
571 // disp field, but _not_ to the target address in the rspec.
572
573 // disp was created by converting the target address minus the pc
574 // at the start of the instruction. That needs more correction here.
575 // intptr_t disp = target - next_ip;
576 assert(inst_mark() != NULL, "must be inside InstructionMark");
577 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
578 int64_t adjusted = disp;
579 // Do rip-rel adjustment for 64bit
580 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
581 assert(is_simm32(adjusted),
582 "must be 32bit offset (RIP relative address)");
583 emit_data((int32_t) adjusted, rspec, disp32_operand);
584
585 } else {
586 // 32bit never did this, did everything as the rip-rel/disp code above
587 // [disp] ABSOLUTE
588 // [00 reg 100][00 100 101] disp32
589 emit_int8(0x04 | regenc);
590 emit_int8(0x25);
591 emit_data(disp, rspec, disp32_operand);
592 }
593 }
594 is_evex_instruction = false;
595 }
596
597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
598 Address::ScaleFactor scale, int disp,
599 RelocationHolder const& rspec) {
600 if (UseAVX > 2) {
601 int xreg_enc = reg->encoding();
602 if (xreg_enc > 15) {
603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
604 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
605 return;
606 }
607 }
608 emit_operand((Register)reg, base, index, scale, disp, rspec);
609 }
610
611 // Secret local extension to Assembler::WhichOperand:
612 #define end_pc_operand (_WhichOperand_limit)
613
614 address Assembler::locate_operand(address inst, WhichOperand which) {
615 // Decode the given instruction, and return the address of
616 // an embedded 32-bit operand word.
617
618 // If "which" is disp32_operand, selects the displacement portion
619 // of an effective address specifier.
620 // If "which" is imm64_operand, selects the trailing immediate constant.
621 // If "which" is call32_operand, selects the displacement of a call or jump.
622 // Caller is responsible for ensuring that there is such an operand,
623 // and that it is 32/64 bits wide.
624
625 // If "which" is end_pc_operand, find the end of the instruction.
626
627 address ip = inst;
628 bool is_64bit = false;
629
630 debug_only(bool has_disp32 = false);
631 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
632
633 again_after_prefix:
634 switch (0xFF & *ip++) {
635
636 // These convenience macros generate groups of "case" labels for the switch.
637 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
638 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
639 case (x)+4: case (x)+5: case (x)+6: case (x)+7
640 #define REP16(x) REP8((x)+0): \
641 case REP8((x)+8)
642
643 case CS_segment:
644 case SS_segment:
645 case DS_segment:
646 case ES_segment:
647 case FS_segment:
648 case GS_segment:
649 // Seems dubious
650 LP64_ONLY(assert(false, "shouldn't have that prefix"));
651 assert(ip == inst+1, "only one prefix allowed");
652 goto again_after_prefix;
653
654 case 0x67:
655 case REX:
656 case REX_B:
657 case REX_X:
658 case REX_XB:
659 case REX_R:
660 case REX_RB:
661 case REX_RX:
662 case REX_RXB:
663 NOT_LP64(assert(false, "64bit prefixes"));
664 goto again_after_prefix;
665
666 case REX_W:
667 case REX_WB:
668 case REX_WX:
669 case REX_WXB:
670 case REX_WR:
671 case REX_WRB:
672 case REX_WRX:
673 case REX_WRXB:
674 NOT_LP64(assert(false, "64bit prefixes"));
675 is_64bit = true;
676 goto again_after_prefix;
677
678 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
679 case 0x88: // movb a, r
680 case 0x89: // movl a, r
681 case 0x8A: // movb r, a
682 case 0x8B: // movl r, a
683 case 0x8F: // popl a
684 debug_only(has_disp32 = true);
685 break;
686
687 case 0x68: // pushq #32
688 if (which == end_pc_operand) {
689 return ip + 4;
690 }
691 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
692 return ip; // not produced by emit_operand
693
694 case 0x66: // movw ... (size prefix)
695 again_after_size_prefix2:
696 switch (0xFF & *ip++) {
697 case REX:
698 case REX_B:
699 case REX_X:
700 case REX_XB:
701 case REX_R:
702 case REX_RB:
703 case REX_RX:
704 case REX_RXB:
705 case REX_W:
706 case REX_WB:
707 case REX_WX:
708 case REX_WXB:
709 case REX_WR:
710 case REX_WRB:
711 case REX_WRX:
712 case REX_WRXB:
713 NOT_LP64(assert(false, "64bit prefix found"));
714 goto again_after_size_prefix2;
715 case 0x8B: // movw r, a
716 case 0x89: // movw a, r
717 debug_only(has_disp32 = true);
718 break;
719 case 0xC7: // movw a, #16
720 debug_only(has_disp32 = true);
721 tail_size = 2; // the imm16
722 break;
723 case 0x0F: // several SSE/SSE2 variants
724 ip--; // reparse the 0x0F
725 goto again_after_prefix;
726 default:
727 ShouldNotReachHere();
728 }
729 break;
730
731 case REP8(0xB8): // movl/q r, #32/#64(oop?)
732 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
733 // these asserts are somewhat nonsensical
734 #ifndef _LP64
735 assert(which == imm_operand || which == disp32_operand,
736 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
737 #else
738 assert((which == call32_operand || which == imm_operand) && is_64bit ||
739 which == narrow_oop_operand && !is_64bit,
740 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
741 #endif // _LP64
742 return ip;
743
744 case 0x69: // imul r, a, #32
745 case 0xC7: // movl a, #32(oop?)
746 tail_size = 4;
747 debug_only(has_disp32 = true); // has both kinds of operands!
748 break;
749
750 case 0x0F: // movx..., etc.
751 switch (0xFF & *ip++) {
752 case 0x3A: // pcmpestri
753 tail_size = 1;
754 case 0x38: // ptest, pmovzxbw
755 ip++; // skip opcode
756 debug_only(has_disp32 = true); // has both kinds of operands!
757 break;
758
759 case 0x70: // pshufd r, r/a, #8
760 debug_only(has_disp32 = true); // has both kinds of operands!
761 case 0x73: // psrldq r, #8
762 tail_size = 1;
763 break;
764
765 case 0x12: // movlps
766 case 0x28: // movaps
767 case 0x2E: // ucomiss
768 case 0x2F: // comiss
769 case 0x54: // andps
770 case 0x55: // andnps
771 case 0x56: // orps
772 case 0x57: // xorps
773 case 0x6E: // movd
774 case 0x7E: // movd
775 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
776 debug_only(has_disp32 = true);
777 break;
778
779 case 0xAD: // shrd r, a, %cl
780 case 0xAF: // imul r, a
781 case 0xBE: // movsbl r, a (movsxb)
782 case 0xBF: // movswl r, a (movsxw)
783 case 0xB6: // movzbl r, a (movzxb)
784 case 0xB7: // movzwl r, a (movzxw)
785 case REP16(0x40): // cmovl cc, r, a
786 case 0xB0: // cmpxchgb
787 case 0xB1: // cmpxchg
788 case 0xC1: // xaddl
789 case 0xC7: // cmpxchg8
790 case REP16(0x90): // setcc a
791 debug_only(has_disp32 = true);
792 // fall out of the switch to decode the address
793 break;
794
795 case 0xC4: // pinsrw r, a, #8
796 debug_only(has_disp32 = true);
797 case 0xC5: // pextrw r, r, #8
798 tail_size = 1; // the imm8
799 break;
800
801 case 0xAC: // shrd r, a, #8
802 debug_only(has_disp32 = true);
803 tail_size = 1; // the imm8
804 break;
805
806 case REP16(0x80): // jcc rdisp32
807 if (which == end_pc_operand) return ip + 4;
808 assert(which == call32_operand, "jcc has no disp32 or imm");
809 return ip;
810 default:
811 ShouldNotReachHere();
812 }
813 break;
814
815 case 0x81: // addl a, #32; addl r, #32
816 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
817 // on 32bit in the case of cmpl, the imm might be an oop
818 tail_size = 4;
819 debug_only(has_disp32 = true); // has both kinds of operands!
820 break;
821
822 case 0x83: // addl a, #8; addl r, #8
823 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
824 debug_only(has_disp32 = true); // has both kinds of operands!
825 tail_size = 1;
826 break;
827
828 case 0x9B:
829 switch (0xFF & *ip++) {
830 case 0xD9: // fnstcw a
831 debug_only(has_disp32 = true);
832 break;
833 default:
834 ShouldNotReachHere();
835 }
836 break;
837
838 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
839 case REP4(0x10): // adc...
840 case REP4(0x20): // and...
841 case REP4(0x30): // xor...
842 case REP4(0x08): // or...
843 case REP4(0x18): // sbb...
844 case REP4(0x28): // sub...
845 case 0xF7: // mull a
846 case 0x8D: // lea r, a
847 case 0x87: // xchg r, a
848 case REP4(0x38): // cmp...
849 case 0x85: // test r, a
850 debug_only(has_disp32 = true); // has both kinds of operands!
851 break;
852
853 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
854 case 0xC6: // movb a, #8
855 case 0x80: // cmpb a, #8
856 case 0x6B: // imul r, a, #8
857 debug_only(has_disp32 = true); // has both kinds of operands!
858 tail_size = 1; // the imm8
859 break;
860
861 case 0xC4: // VEX_3bytes
862 case 0xC5: // VEX_2bytes
863 assert((UseAVX > 0), "shouldn't have VEX prefix");
864 assert(ip == inst+1, "no prefixes allowed");
865 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
866 // but they have prefix 0x0F and processed when 0x0F processed above.
867 //
868 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
869 // instructions (these instructions are not supported in 64-bit mode).
870 // To distinguish them bits [7:6] are set in the VEX second byte since
871 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
872 // those VEX bits REX and vvvv bits are inverted.
873 //
874 // Fortunately C2 doesn't generate these instructions so we don't need
875 // to check for them in product version.
876
877 // Check second byte
878 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
879
880 int vex_opcode;
881 // First byte
882 if ((0xFF & *inst) == VEX_3bytes) {
883 vex_opcode = VEX_OPCODE_MASK & *ip;
884 ip++; // third byte
885 is_64bit = ((VEX_W & *ip) == VEX_W);
886 } else {
887 vex_opcode = VEX_OPCODE_0F;
888 }
889 ip++; // opcode
890 // To find the end of instruction (which == end_pc_operand).
891 switch (vex_opcode) {
892 case VEX_OPCODE_0F:
893 switch (0xFF & *ip) {
894 case 0x70: // pshufd r, r/a, #8
895 case 0x71: // ps[rl|ra|ll]w r, #8
896 case 0x72: // ps[rl|ra|ll]d r, #8
897 case 0x73: // ps[rl|ra|ll]q r, #8
898 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
899 case 0xC4: // pinsrw r, r, r/a, #8
900 case 0xC5: // pextrw r/a, r, #8
901 case 0xC6: // shufp[s|d] r, r, r/a, #8
902 tail_size = 1; // the imm8
903 break;
904 }
905 break;
906 case VEX_OPCODE_0F_3A:
907 tail_size = 1;
908 break;
909 }
910 ip++; // skip opcode
911 debug_only(has_disp32 = true); // has both kinds of operands!
912 break;
913
914 case 0x62: // EVEX_4bytes
915 assert((UseAVX > 0), "shouldn't have EVEX prefix");
916 assert(ip == inst+1, "no prefixes allowed");
917 // no EVEX collisions, all instructions that have 0x62 opcodes
918 // have EVEX versions and are subopcodes of 0x66
919 ip++; // skip P0 and exmaine W in P1
920 is_64bit = ((VEX_W & *ip) == VEX_W);
921 ip++; // move to P2
922 ip++; // skip P2, move to opcode
923 // To find the end of instruction (which == end_pc_operand).
924 switch (0xFF & *ip) {
925 case 0x61: // pcmpestri r, r/a, #8
926 case 0x70: // pshufd r, r/a, #8
927 case 0x73: // psrldq r, #8
928 tail_size = 1; // the imm8
929 break;
930 default:
931 break;
932 }
933 ip++; // skip opcode
934 debug_only(has_disp32 = true); // has both kinds of operands!
935 break;
936
937 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
938 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
939 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
940 case 0xDD: // fld_d a; fst_d a; fstp_d a
941 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
942 case 0xDF: // fild_d a; fistp_d a
943 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
944 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
945 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
946 debug_only(has_disp32 = true);
947 break;
948
949 case 0xE8: // call rdisp32
950 case 0xE9: // jmp rdisp32
951 if (which == end_pc_operand) return ip + 4;
952 assert(which == call32_operand, "call has no disp32 or imm");
953 return ip;
954
955 case 0xF0: // Lock
956 assert(os::is_MP(), "only on MP");
957 goto again_after_prefix;
958
959 case 0xF3: // For SSE
960 case 0xF2: // For SSE2
961 switch (0xFF & *ip++) {
962 case REX:
963 case REX_B:
964 case REX_X:
965 case REX_XB:
966 case REX_R:
967 case REX_RB:
968 case REX_RX:
969 case REX_RXB:
970 case REX_W:
971 case REX_WB:
972 case REX_WX:
973 case REX_WXB:
974 case REX_WR:
975 case REX_WRB:
976 case REX_WRX:
977 case REX_WRXB:
978 NOT_LP64(assert(false, "found 64bit prefix"));
979 ip++;
980 default:
981 ip++;
982 }
983 debug_only(has_disp32 = true); // has both kinds of operands!
984 break;
985
986 default:
987 ShouldNotReachHere();
988
989 #undef REP8
990 #undef REP16
991 }
992
993 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
994 #ifdef _LP64
995 assert(which != imm_operand, "instruction is not a movq reg, imm64");
996 #else
997 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
998 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
999 #endif // LP64
1000 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1001
1002 // parse the output of emit_operand
1003 int op2 = 0xFF & *ip++;
1004 int base = op2 & 0x07;
1005 int op3 = -1;
1006 const int b100 = 4;
1007 const int b101 = 5;
1008 if (base == b100 && (op2 >> 6) != 3) {
1009 op3 = 0xFF & *ip++;
1010 base = op3 & 0x07; // refetch the base
1011 }
1012 // now ip points at the disp (if any)
1013
1014 switch (op2 >> 6) {
1015 case 0:
1016 // [00 reg 100][ss index base]
1017 // [00 reg 100][00 100 esp]
1018 // [00 reg base]
1019 // [00 reg 100][ss index 101][disp32]
1020 // [00 reg 101] [disp32]
1021
1022 if (base == b101) {
1023 if (which == disp32_operand)
1024 return ip; // caller wants the disp32
1025 ip += 4; // skip the disp32
1026 }
1027 break;
1028
1029 case 1:
1030 // [01 reg 100][ss index base][disp8]
1031 // [01 reg 100][00 100 esp][disp8]
1032 // [01 reg base] [disp8]
1033 ip += 1; // skip the disp8
1034 break;
1035
1036 case 2:
1037 // [10 reg 100][ss index base][disp32]
1038 // [10 reg 100][00 100 esp][disp32]
1039 // [10 reg base] [disp32]
1040 if (which == disp32_operand)
1041 return ip; // caller wants the disp32
1042 ip += 4; // skip the disp32
1043 break;
1044
1045 case 3:
1046 // [11 reg base] (not a memory addressing mode)
1047 break;
1048 }
1049
1050 if (which == end_pc_operand) {
1051 return ip + tail_size;
1052 }
1053
1054 #ifdef _LP64
1055 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1056 #else
1057 assert(which == imm_operand, "instruction has only an imm field");
1058 #endif // LP64
1059 return ip;
1060 }
1061
1062 address Assembler::locate_next_instruction(address inst) {
1063 // Secretly share code with locate_operand:
1064 return locate_operand(inst, end_pc_operand);
1065 }
1066
1067
1068 #ifdef ASSERT
1069 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1070 address inst = inst_mark();
1071 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1072 address opnd;
1073
1074 Relocation* r = rspec.reloc();
1075 if (r->type() == relocInfo::none) {
1076 return;
1077 } else if (r->is_call() || format == call32_operand) {
1078 // assert(format == imm32_operand, "cannot specify a nonzero format");
1079 opnd = locate_operand(inst, call32_operand);
1080 } else if (r->is_data()) {
1081 assert(format == imm_operand || format == disp32_operand
1082 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1083 opnd = locate_operand(inst, (WhichOperand)format);
1084 } else {
1085 assert(format == imm_operand, "cannot specify a format");
1086 return;
1087 }
1088 assert(opnd == pc(), "must put operand where relocs can find it");
1089 }
1090 #endif // ASSERT
1091
1092 void Assembler::emit_operand32(Register reg, Address adr) {
1093 assert(reg->encoding() < 8, "no extended registers");
1094 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1095 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1096 adr._rspec);
1097 }
1098
1099 void Assembler::emit_operand(Register reg, Address adr,
1100 int rip_relative_correction) {
1101 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1102 adr._rspec,
1103 rip_relative_correction);
1104 }
1105
1106 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1107 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1108 adr._rspec);
1109 }
1110
1111 // MMX operations
1112 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1113 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1114 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1115 }
1116
1117 // work around gcc (3.2.1-7a) bug
1118 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1119 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1120 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1121 }
1122
1123
1124 void Assembler::emit_farith(int b1, int b2, int i) {
1125 assert(isByte(b1) && isByte(b2), "wrong opcode");
1126 assert(0 <= i && i < 8, "illegal stack offset");
1127 emit_int8(b1);
1128 emit_int8(b2 + i);
1129 }
1130
1131
1132 // Now the Assembler instructions (identical for 32/64 bits)
1133
1134 void Assembler::adcl(Address dst, int32_t imm32) {
1135 InstructionMark im(this);
1136 prefix(dst);
1137 emit_arith_operand(0x81, rdx, dst, imm32);
1138 }
1139
1140 void Assembler::adcl(Address dst, Register src) {
1141 InstructionMark im(this);
1142 prefix(dst, src);
1143 emit_int8(0x11);
1144 emit_operand(src, dst);
1145 }
1146
1147 void Assembler::adcl(Register dst, int32_t imm32) {
1148 prefix(dst);
1149 emit_arith(0x81, 0xD0, dst, imm32);
1150 }
1151
1152 void Assembler::adcl(Register dst, Address src) {
1153 InstructionMark im(this);
1154 prefix(src, dst);
1155 emit_int8(0x13);
1156 emit_operand(dst, src);
1157 }
1158
1159 void Assembler::adcl(Register dst, Register src) {
1160 (void) prefix_and_encode(dst->encoding(), src->encoding());
1161 emit_arith(0x13, 0xC0, dst, src);
1162 }
1163
1164 void Assembler::addl(Address dst, int32_t imm32) {
1165 InstructionMark im(this);
1166 prefix(dst);
1167 emit_arith_operand(0x81, rax, dst, imm32);
1168 }
1169
1170 void Assembler::addl(Address dst, Register src) {
1171 InstructionMark im(this);
1172 prefix(dst, src);
1173 emit_int8(0x01);
1174 emit_operand(src, dst);
1175 }
1176
1177 void Assembler::addl(Register dst, int32_t imm32) {
1178 prefix(dst);
1179 emit_arith(0x81, 0xC0, dst, imm32);
1180 }
1181
1182 void Assembler::addl(Register dst, Address src) {
1183 InstructionMark im(this);
1184 prefix(src, dst);
1185 emit_int8(0x03);
1186 emit_operand(dst, src);
1187 }
1188
1189 void Assembler::addl(Register dst, Register src) {
1190 (void) prefix_and_encode(dst->encoding(), src->encoding());
1191 emit_arith(0x03, 0xC0, dst, src);
1192 }
1193
1194 void Assembler::addr_nop_4() {
1195 assert(UseAddressNop, "no CPU support");
1196 // 4 bytes: NOP DWORD PTR [EAX+0]
1197 emit_int8(0x0F);
1198 emit_int8(0x1F);
1199 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1200 emit_int8(0); // 8-bits offset (1 byte)
1201 }
1202
1203 void Assembler::addr_nop_5() {
1204 assert(UseAddressNop, "no CPU support");
1205 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1206 emit_int8(0x0F);
1207 emit_int8(0x1F);
1208 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1209 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1210 emit_int8(0); // 8-bits offset (1 byte)
1211 }
1212
1213 void Assembler::addr_nop_7() {
1214 assert(UseAddressNop, "no CPU support");
1215 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1216 emit_int8(0x0F);
1217 emit_int8(0x1F);
1218 emit_int8((unsigned char)0x80);
1219 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1220 emit_int32(0); // 32-bits offset (4 bytes)
1221 }
1222
1223 void Assembler::addr_nop_8() {
1224 assert(UseAddressNop, "no CPU support");
1225 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1226 emit_int8(0x0F);
1227 emit_int8(0x1F);
1228 emit_int8((unsigned char)0x84);
1229 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1230 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1231 emit_int32(0); // 32-bits offset (4 bytes)
1232 }
1233
1234 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1235 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1236 if (VM_Version::supports_evex()) {
1237 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2);
1238 } else {
1239 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1240 }
1241 }
1242
1243 void Assembler::addsd(XMMRegister dst, Address src) {
1244 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1245 if (VM_Version::supports_evex()) {
1246 tuple_type = EVEX_T1S;
1247 input_size_in_bits = EVEX_64bit;
1248 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_F2);
1249 } else {
1250 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1251 }
1252 }
1253
1254 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1255 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1256 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1257 }
1258
1259 void Assembler::addss(XMMRegister dst, Address src) {
1260 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1261 if (VM_Version::supports_evex()) {
1262 tuple_type = EVEX_T1S;
1263 input_size_in_bits = EVEX_32bit;
1264 }
1265 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1266 }
1267
1268 void Assembler::aesdec(XMMRegister dst, Address src) {
1269 assert(VM_Version::supports_aes(), "");
1270 InstructionMark im(this);
1271 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1272 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1273 emit_int8((unsigned char)0xDE);
1274 emit_operand(dst, src);
1275 }
1276
1277 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1278 assert(VM_Version::supports_aes(), "");
1279 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1280 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1281 emit_int8((unsigned char)0xDE);
1282 emit_int8(0xC0 | encode);
1283 }
1284
1285 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1286 assert(VM_Version::supports_aes(), "");
1287 InstructionMark im(this);
1288 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1289 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1290 emit_int8((unsigned char)0xDF);
1291 emit_operand(dst, src);
1292 }
1293
1294 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1295 assert(VM_Version::supports_aes(), "");
1296 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1297 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1298 emit_int8((unsigned char)0xDF);
1299 emit_int8((unsigned char)(0xC0 | encode));
1300 }
1301
1302 void Assembler::aesenc(XMMRegister dst, Address src) {
1303 assert(VM_Version::supports_aes(), "");
1304 InstructionMark im(this);
1305 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1306 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1307 emit_int8((unsigned char)0xDC);
1308 emit_operand(dst, src);
1309 }
1310
1311 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1312 assert(VM_Version::supports_aes(), "");
1313 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1314 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1315 emit_int8((unsigned char)0xDC);
1316 emit_int8(0xC0 | encode);
1317 }
1318
1319 void Assembler::aesenclast(XMMRegister dst, Address src) {
1320 assert(VM_Version::supports_aes(), "");
1321 InstructionMark im(this);
1322 simd_prefix(dst, dst, src, VEX_SIMD_66, false,
1323 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1324 emit_int8((unsigned char)0xDD);
1325 emit_operand(dst, src);
1326 }
1327
1328 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1329 assert(VM_Version::supports_aes(), "");
1330 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
1331 VEX_OPCODE_0F_38, false, AVX_128bit, true);
1332 emit_int8((unsigned char)0xDD);
1333 emit_int8((unsigned char)(0xC0 | encode));
1334 }
1335
1336
1337 void Assembler::andl(Address dst, int32_t imm32) {
1338 InstructionMark im(this);
1339 prefix(dst);
1340 emit_int8((unsigned char)0x81);
1341 emit_operand(rsp, dst, 4);
1342 emit_int32(imm32);
1343 }
1344
1345 void Assembler::andl(Register dst, int32_t imm32) {
1346 prefix(dst);
1347 emit_arith(0x81, 0xE0, dst, imm32);
1348 }
1349
1350 void Assembler::andl(Register dst, Address src) {
1351 InstructionMark im(this);
1352 prefix(src, dst);
1353 emit_int8(0x23);
1354 emit_operand(dst, src);
1355 }
1356
1357 void Assembler::andl(Register dst, Register src) {
1358 (void) prefix_and_encode(dst->encoding(), src->encoding());
1359 emit_arith(0x23, 0xC0, dst, src);
1360 }
1361
1362 void Assembler::andnl(Register dst, Register src1, Register src2) {
1363 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1364 int encode = vex_prefix_0F38_and_encode_legacy(dst, src1, src2, false);
1365 emit_int8((unsigned char)0xF2);
1366 emit_int8((unsigned char)(0xC0 | encode));
1367 }
1368
1369 void Assembler::andnl(Register dst, Register src1, Address src2) {
1370 InstructionMark im(this);
1371 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1372 vex_prefix_0F38_legacy(dst, src1, src2, false);
1373 emit_int8((unsigned char)0xF2);
1374 emit_operand(dst, src2);
1375 }
1376
1377 void Assembler::bsfl(Register dst, Register src) {
1378 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1379 emit_int8(0x0F);
1380 emit_int8((unsigned char)0xBC);
1381 emit_int8((unsigned char)(0xC0 | encode));
1382 }
1383
1384 void Assembler::bsrl(Register dst, Register src) {
1385 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1386 emit_int8(0x0F);
1387 emit_int8((unsigned char)0xBD);
1388 emit_int8((unsigned char)(0xC0 | encode));
1389 }
1390
1391 void Assembler::bswapl(Register reg) { // bswap
1392 int encode = prefix_and_encode(reg->encoding());
1393 emit_int8(0x0F);
1394 emit_int8((unsigned char)(0xC8 | encode));
1395 }
1396
1397 void Assembler::blsil(Register dst, Register src) {
1398 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1399 int encode = vex_prefix_0F38_and_encode_legacy(rbx, dst, src, false);
1400 emit_int8((unsigned char)0xF3);
1401 emit_int8((unsigned char)(0xC0 | encode));
1402 }
1403
1404 void Assembler::blsil(Register dst, Address src) {
1405 InstructionMark im(this);
1406 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1407 vex_prefix_0F38_legacy(rbx, dst, src, false);
1408 emit_int8((unsigned char)0xF3);
1409 emit_operand(rbx, src);
1410 }
1411
1412 void Assembler::blsmskl(Register dst, Register src) {
1413 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1414 int encode = vex_prefix_0F38_and_encode_legacy(rdx, dst, src, false);
1415 emit_int8((unsigned char)0xF3);
1416 emit_int8((unsigned char)(0xC0 | encode));
1417 }
1418
1419 void Assembler::blsmskl(Register dst, Address src) {
1420 InstructionMark im(this);
1421 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1422 vex_prefix_0F38(rdx, dst, src, false);
1423 emit_int8((unsigned char)0xF3);
1424 emit_operand(rdx, src);
1425 }
1426
1427 void Assembler::blsrl(Register dst, Register src) {
1428 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1429 int encode = vex_prefix_0F38_and_encode_legacy(rcx, dst, src, false);
1430 emit_int8((unsigned char)0xF3);
1431 emit_int8((unsigned char)(0xC0 | encode));
1432 }
1433
1434 void Assembler::blsrl(Register dst, Address src) {
1435 InstructionMark im(this);
1436 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1437 vex_prefix_0F38_legacy(rcx, dst, src, false);
1438 emit_int8((unsigned char)0xF3);
1439 emit_operand(rcx, src);
1440 }
1441
1442 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1443 // suspect disp32 is always good
1444 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1445
1446 if (L.is_bound()) {
1447 const int long_size = 5;
1448 int offs = (int)( target(L) - pc() );
1449 assert(offs <= 0, "assembler error");
1450 InstructionMark im(this);
1451 // 1110 1000 #32-bit disp
1452 emit_int8((unsigned char)0xE8);
1453 emit_data(offs - long_size, rtype, operand);
1454 } else {
1455 InstructionMark im(this);
1456 // 1110 1000 #32-bit disp
1457 L.add_patch_at(code(), locator());
1458
1459 emit_int8((unsigned char)0xE8);
1460 emit_data(int(0), rtype, operand);
1461 }
1462 }
1463
1464 void Assembler::call(Register dst) {
1465 int encode = prefix_and_encode(dst->encoding());
1466 emit_int8((unsigned char)0xFF);
1467 emit_int8((unsigned char)(0xD0 | encode));
1468 }
1469
1470
1471 void Assembler::call(Address adr) {
1472 InstructionMark im(this);
1473 prefix(adr);
1474 emit_int8((unsigned char)0xFF);
1475 emit_operand(rdx, adr);
1476 }
1477
1478 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1479 assert(entry != NULL, "call most probably wrong");
1480 InstructionMark im(this);
1481 emit_int8((unsigned char)0xE8);
1482 intptr_t disp = entry - (pc() + sizeof(int32_t));
1483 assert(is_simm32(disp), "must be 32bit offset (call2)");
1484 // Technically, should use call32_operand, but this format is
1485 // implied by the fact that we're emitting a call instruction.
1486
1487 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1488 emit_data((int) disp, rspec, operand);
1489 }
1490
1491 void Assembler::cdql() {
1492 emit_int8((unsigned char)0x99);
1493 }
1494
1495 void Assembler::cld() {
1496 emit_int8((unsigned char)0xFC);
1497 }
1498
1499 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1500 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1501 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1502 emit_int8(0x0F);
1503 emit_int8(0x40 | cc);
1504 emit_int8((unsigned char)(0xC0 | encode));
1505 }
1506
1507
1508 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1509 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1510 prefix(src, dst);
1511 emit_int8(0x0F);
1512 emit_int8(0x40 | cc);
1513 emit_operand(dst, src);
1514 }
1515
1516 void Assembler::cmpb(Address dst, int imm8) {
1517 InstructionMark im(this);
1518 prefix(dst);
1519 emit_int8((unsigned char)0x80);
1520 emit_operand(rdi, dst, 1);
1521 emit_int8(imm8);
1522 }
1523
1524 void Assembler::cmpl(Address dst, int32_t imm32) {
1525 InstructionMark im(this);
1526 prefix(dst);
1527 emit_int8((unsigned char)0x81);
1528 emit_operand(rdi, dst, 4);
1529 emit_int32(imm32);
1530 }
1531
1532 void Assembler::cmpl(Register dst, int32_t imm32) {
1533 prefix(dst);
1534 emit_arith(0x81, 0xF8, dst, imm32);
1535 }
1536
1537 void Assembler::cmpl(Register dst, Register src) {
1538 (void) prefix_and_encode(dst->encoding(), src->encoding());
1539 emit_arith(0x3B, 0xC0, dst, src);
1540 }
1541
1542
1543 void Assembler::cmpl(Register dst, Address src) {
1544 InstructionMark im(this);
1545 prefix(src, dst);
1546 emit_int8((unsigned char)0x3B);
1547 emit_operand(dst, src);
1548 }
1549
1550 void Assembler::cmpw(Address dst, int imm16) {
1551 InstructionMark im(this);
1552 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1553 emit_int8(0x66);
1554 emit_int8((unsigned char)0x81);
1555 emit_operand(rdi, dst, 2);
1556 emit_int16(imm16);
1557 }
1558
1559 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1560 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1561 // The ZF is set if the compared values were equal, and cleared otherwise.
1562 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1563 InstructionMark im(this);
1564 prefix(adr, reg);
1565 emit_int8(0x0F);
1566 emit_int8((unsigned char)0xB1);
1567 emit_operand(reg, adr);
1568 }
1569
1570 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1571 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1572 // The ZF is set if the compared values were equal, and cleared otherwise.
1573 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1574 InstructionMark im(this);
1575 prefix(adr, reg, true);
1576 emit_int8(0x0F);
1577 emit_int8((unsigned char)0xB0);
1578 emit_operand(reg, adr);
1579 }
1580
1581 void Assembler::comisd(XMMRegister dst, Address src) {
1582 // NOTE: dbx seems to decode this as comiss even though the
1583 // 0x66 is there. Strangly ucomisd comes out correct
1584 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1585 if (VM_Version::supports_evex()) {
1586 tuple_type = EVEX_T1S;
1587 input_size_in_bits = EVEX_64bit;
1588 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, true);
1589 } else {
1590 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1591 }
1592 }
1593
1594 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1595 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1596 if (VM_Version::supports_evex()) {
1597 emit_simd_arith_nonds_q(0x2F, dst, src, VEX_SIMD_66, true);
1598 } else {
1599 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1600 }
1601 }
1602
1603 void Assembler::comiss(XMMRegister dst, Address src) {
1604 if (VM_Version::supports_evex()) {
1605 tuple_type = EVEX_T1S;
1606 input_size_in_bits = EVEX_32bit;
1607 }
1608 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1609 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true);
1610 }
1611
1612 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1613 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1614 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE, true);
1615 }
1616
1617 void Assembler::cpuid() {
1618 emit_int8(0x0F);
1619 emit_int8((unsigned char)0xA2);
1620 }
1621
1622 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1623 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1624 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1625 }
1626
1627 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1628 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1629 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1630 }
1631
1632 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1633 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1634 if (VM_Version::supports_evex()) {
1635 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1636 } else {
1637 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1638 }
1639 }
1640
1641 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1642 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1643 if (VM_Version::supports_evex()) {
1644 tuple_type = EVEX_T1F;
1645 input_size_in_bits = EVEX_64bit;
1646 emit_simd_arith_q(0x5A, dst, src, VEX_SIMD_F2);
1647 } else {
1648 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1649 }
1650 }
1651
1652 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1653 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1654 int encode = 0;
1655 if (VM_Version::supports_evex()) {
1656 encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, true);
1657 } else {
1658 encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, false);
1659 }
1660 emit_int8(0x2A);
1661 emit_int8((unsigned char)(0xC0 | encode));
1662 }
1663
1664 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1665 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1666 if (VM_Version::supports_evex()) {
1667 tuple_type = EVEX_T1S;
1668 input_size_in_bits = EVEX_32bit;
1669 emit_simd_arith_q(0x2A, dst, src, VEX_SIMD_F2, true);
1670 } else {
1671 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1672 }
1673 }
1674
1675 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1676 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1677 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, true);
1678 emit_int8(0x2A);
1679 emit_int8((unsigned char)(0xC0 | encode));
1680 }
1681
1682 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1683 if (VM_Version::supports_evex()) {
1684 tuple_type = EVEX_T1S;
1685 input_size_in_bits = EVEX_32bit;
1686 }
1687 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1688 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3, true);
1689 }
1690
1691 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1692 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1693 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3, true);
1694 emit_int8(0x2A);
1695 emit_int8((unsigned char)(0xC0 | encode));
1696 }
1697
1698 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1699 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1700 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1701 }
1702
1703 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1704 if (VM_Version::supports_evex()) {
1705 tuple_type = EVEX_T1S;
1706 input_size_in_bits = EVEX_32bit;
1707 }
1708 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1709 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1710 }
1711
1712
1713 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1714 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1715 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true);
1716 emit_int8(0x2C);
1717 emit_int8((unsigned char)(0xC0 | encode));
1718 }
1719
1720 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1721 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1722 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, true);
1723 emit_int8(0x2C);
1724 emit_int8((unsigned char)(0xC0 | encode));
1725 }
1726
1727 void Assembler::decl(Address dst) {
1728 // Don't use it directly. Use MacroAssembler::decrement() instead.
1729 InstructionMark im(this);
1730 prefix(dst);
1731 emit_int8((unsigned char)0xFF);
1732 emit_operand(rcx, dst);
1733 }
1734
1735 void Assembler::divsd(XMMRegister dst, Address src) {
1736 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1737 if (VM_Version::supports_evex()) {
1738 tuple_type = EVEX_T1S;
1739 input_size_in_bits = EVEX_64bit;
1740 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2);
1741 } else {
1742 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1743 }
1744 }
1745
1746 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1747 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1748 if (VM_Version::supports_evex()) {
1749 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_F2);
1750 } else {
1751 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1752 }
1753 }
1754
1755 void Assembler::divss(XMMRegister dst, Address src) {
1756 if (VM_Version::supports_evex()) {
1757 tuple_type = EVEX_T1S;
1758 input_size_in_bits = EVEX_32bit;
1759 }
1760 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1761 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1762 }
1763
1764 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1765 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1766 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1767 }
1768
1769 void Assembler::emms() {
1770 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1771 emit_int8(0x0F);
1772 emit_int8(0x77);
1773 }
1774
1775 void Assembler::hlt() {
1776 emit_int8((unsigned char)0xF4);
1777 }
1778
1779 void Assembler::idivl(Register src) {
1780 int encode = prefix_and_encode(src->encoding());
1781 emit_int8((unsigned char)0xF7);
1782 emit_int8((unsigned char)(0xF8 | encode));
1783 }
1784
1785 void Assembler::divl(Register src) { // Unsigned
1786 int encode = prefix_and_encode(src->encoding());
1787 emit_int8((unsigned char)0xF7);
1788 emit_int8((unsigned char)(0xF0 | encode));
1789 }
1790
1791 void Assembler::imull(Register dst, Register src) {
1792 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1793 emit_int8(0x0F);
1794 emit_int8((unsigned char)0xAF);
1795 emit_int8((unsigned char)(0xC0 | encode));
1796 }
1797
1798
1799 void Assembler::imull(Register dst, Register src, int value) {
1800 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1801 if (is8bit(value)) {
1802 emit_int8(0x6B);
1803 emit_int8((unsigned char)(0xC0 | encode));
1804 emit_int8(value & 0xFF);
1805 } else {
1806 emit_int8(0x69);
1807 emit_int8((unsigned char)(0xC0 | encode));
1808 emit_int32(value);
1809 }
1810 }
1811
1812 void Assembler::imull(Register dst, Address src) {
1813 InstructionMark im(this);
1814 prefix(src, dst);
1815 emit_int8(0x0F);
1816 emit_int8((unsigned char) 0xAF);
1817 emit_operand(dst, src);
1818 }
1819
1820
1821 void Assembler::incl(Address dst) {
1822 // Don't use it directly. Use MacroAssembler::increment() instead.
1823 InstructionMark im(this);
1824 prefix(dst);
1825 emit_int8((unsigned char)0xFF);
1826 emit_operand(rax, dst);
1827 }
1828
1829 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1830 InstructionMark im(this);
1831 assert((0 <= cc) && (cc < 16), "illegal cc");
1832 if (L.is_bound()) {
1833 address dst = target(L);
1834 assert(dst != NULL, "jcc most probably wrong");
1835
1836 const int short_size = 2;
1837 const int long_size = 6;
1838 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1839 if (maybe_short && is8bit(offs - short_size)) {
1840 // 0111 tttn #8-bit disp
1841 emit_int8(0x70 | cc);
1842 emit_int8((offs - short_size) & 0xFF);
1843 } else {
1844 // 0000 1111 1000 tttn #32-bit disp
1845 assert(is_simm32(offs - long_size),
1846 "must be 32bit offset (call4)");
1847 emit_int8(0x0F);
1848 emit_int8((unsigned char)(0x80 | cc));
1849 emit_int32(offs - long_size);
1850 }
1851 } else {
1852 // Note: could eliminate cond. jumps to this jump if condition
1853 // is the same however, seems to be rather unlikely case.
1854 // Note: use jccb() if label to be bound is very close to get
1855 // an 8-bit displacement
1856 L.add_patch_at(code(), locator());
1857 emit_int8(0x0F);
1858 emit_int8((unsigned char)(0x80 | cc));
1859 emit_int32(0);
1860 }
1861 }
1862
1863 void Assembler::jccb(Condition cc, Label& L) {
1864 if (L.is_bound()) {
1865 const int short_size = 2;
1866 address entry = target(L);
1867 #ifdef ASSERT
1868 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1869 intptr_t delta = short_branch_delta();
1870 if (delta != 0) {
1871 dist += (dist < 0 ? (-delta) :delta);
1872 }
1873 assert(is8bit(dist), "Dispacement too large for a short jmp");
1874 #endif
1875 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1876 // 0111 tttn #8-bit disp
1877 emit_int8(0x70 | cc);
1878 emit_int8((offs - short_size) & 0xFF);
1879 } else {
1880 InstructionMark im(this);
1881 L.add_patch_at(code(), locator());
1882 emit_int8(0x70 | cc);
1883 emit_int8(0);
1884 }
1885 }
1886
1887 void Assembler::jmp(Address adr) {
1888 InstructionMark im(this);
1889 prefix(adr);
1890 emit_int8((unsigned char)0xFF);
1891 emit_operand(rsp, adr);
1892 }
1893
1894 void Assembler::jmp(Label& L, bool maybe_short) {
1895 if (L.is_bound()) {
1896 address entry = target(L);
1897 assert(entry != NULL, "jmp most probably wrong");
1898 InstructionMark im(this);
1899 const int short_size = 2;
1900 const int long_size = 5;
1901 intptr_t offs = entry - pc();
1902 if (maybe_short && is8bit(offs - short_size)) {
1903 emit_int8((unsigned char)0xEB);
1904 emit_int8((offs - short_size) & 0xFF);
1905 } else {
1906 emit_int8((unsigned char)0xE9);
1907 emit_int32(offs - long_size);
1908 }
1909 } else {
1910 // By default, forward jumps are always 32-bit displacements, since
1911 // we can't yet know where the label will be bound. If you're sure that
1912 // the forward jump will not run beyond 256 bytes, use jmpb to
1913 // force an 8-bit displacement.
1914 InstructionMark im(this);
1915 L.add_patch_at(code(), locator());
1916 emit_int8((unsigned char)0xE9);
1917 emit_int32(0);
1918 }
1919 }
1920
1921 void Assembler::jmp(Register entry) {
1922 int encode = prefix_and_encode(entry->encoding());
1923 emit_int8((unsigned char)0xFF);
1924 emit_int8((unsigned char)(0xE0 | encode));
1925 }
1926
1927 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1928 InstructionMark im(this);
1929 emit_int8((unsigned char)0xE9);
1930 assert(dest != NULL, "must have a target");
1931 intptr_t disp = dest - (pc() + sizeof(int32_t));
1932 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1933 emit_data(disp, rspec.reloc(), call32_operand);
1934 }
1935
1936 void Assembler::jmpb(Label& L) {
1937 if (L.is_bound()) {
1938 const int short_size = 2;
1939 address entry = target(L);
1940 assert(entry != NULL, "jmp most probably wrong");
1941 #ifdef ASSERT
1942 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1943 intptr_t delta = short_branch_delta();
1944 if (delta != 0) {
1945 dist += (dist < 0 ? (-delta) :delta);
1946 }
1947 assert(is8bit(dist), "Dispacement too large for a short jmp");
1948 #endif
1949 intptr_t offs = entry - pc();
1950 emit_int8((unsigned char)0xEB);
1951 emit_int8((offs - short_size) & 0xFF);
1952 } else {
1953 InstructionMark im(this);
1954 L.add_patch_at(code(), locator());
1955 emit_int8((unsigned char)0xEB);
1956 emit_int8(0);
1957 }
1958 }
1959
1960 void Assembler::ldmxcsr( Address src) {
1961 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1962 InstructionMark im(this);
1963 prefix(src);
1964 emit_int8(0x0F);
1965 emit_int8((unsigned char)0xAE);
1966 emit_operand(as_Register(2), src);
1967 }
1968
1969 void Assembler::leal(Register dst, Address src) {
1970 InstructionMark im(this);
1971 #ifdef _LP64
1972 emit_int8(0x67); // addr32
1973 prefix(src, dst);
1974 #endif // LP64
1975 emit_int8((unsigned char)0x8D);
1976 emit_operand(dst, src);
1977 }
1978
1979 void Assembler::lfence() {
1980 emit_int8(0x0F);
1981 emit_int8((unsigned char)0xAE);
1982 emit_int8((unsigned char)0xE8);
1983 }
1984
1985 void Assembler::lock() {
1986 emit_int8((unsigned char)0xF0);
1987 }
1988
1989 void Assembler::lzcntl(Register dst, Register src) {
1990 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1991 emit_int8((unsigned char)0xF3);
1992 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1993 emit_int8(0x0F);
1994 emit_int8((unsigned char)0xBD);
1995 emit_int8((unsigned char)(0xC0 | encode));
1996 }
1997
1998 // Emit mfence instruction
1999 void Assembler::mfence() {
2000 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2001 emit_int8(0x0F);
2002 emit_int8((unsigned char)0xAE);
2003 emit_int8((unsigned char)0xF0);
2004 }
2005
2006 void Assembler::mov(Register dst, Register src) {
2007 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2008 }
2009
2010 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2011 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2012 if (VM_Version::supports_evex()) {
2013 emit_simd_arith_nonds_q(0x28, dst, src, VEX_SIMD_66, true);
2014 } else {
2015 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
2016 }
2017 }
2018
2019 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2020 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2021 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
2022 }
2023
2024 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2025 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2026 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, true, VEX_OPCODE_0F,
2027 false, AVX_128bit);
2028 emit_int8(0x16);
2029 emit_int8((unsigned char)(0xC0 | encode));
2030 }
2031
2032 void Assembler::movb(Register dst, Address src) {
2033 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2034 InstructionMark im(this);
2035 prefix(src, dst, true);
2036 emit_int8((unsigned char)0x8A);
2037 emit_operand(dst, src);
2038 }
2039
2040 void Assembler::kmovq(KRegister dst, KRegister src) {
2041 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2042 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE,
2043 true, VEX_OPCODE_0F, true);
2044 emit_int8((unsigned char)0x90);
2045 emit_int8((unsigned char)(0xC0 | encode));
2046 }
2047
2048 void Assembler::kmovq(KRegister dst, Address src) {
2049 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2050 int dst_enc = dst->encoding();
2051 int nds_enc = 0;
2052 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_NONE,
2053 VEX_OPCODE_0F, true, AVX_128bit, true, true);
2054 emit_int8((unsigned char)0x90);
2055 emit_operand((Register)dst, src);
2056 }
2057
2058 void Assembler::kmovq(Address dst, KRegister src) {
2059 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2060 int src_enc = src->encoding();
2061 int nds_enc = 0;
2062 vex_prefix(dst, nds_enc, src_enc, VEX_SIMD_NONE,
2063 VEX_OPCODE_0F, true, AVX_128bit, true, true);
2064 emit_int8((unsigned char)0x90);
2065 emit_operand((Register)src, dst);
2066 }
2067
2068 void Assembler::kmovql(KRegister dst, Register src) {
2069 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2070 bool supports_bw = VM_Version::supports_avx512bw();
2071 VexSimdPrefix pre = supports_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2072 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, true,
2073 VEX_OPCODE_0F, supports_bw);
2074 emit_int8((unsigned char)0x92);
2075 emit_int8((unsigned char)(0xC0 | encode));
2076 }
2077
2078 void Assembler::kmovdl(KRegister dst, Register src) {
2079 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2080 VexSimdPrefix pre = VM_Version::supports_avx512bw() ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2081 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, true, VEX_OPCODE_0F, false);
2082 emit_int8((unsigned char)0x92);
2083 emit_int8((unsigned char)(0xC0 | encode));
2084 }
2085
2086 void Assembler::movb(Address dst, int imm8) {
2087 InstructionMark im(this);
2088 prefix(dst);
2089 emit_int8((unsigned char)0xC6);
2090 emit_operand(rax, dst, 1);
2091 emit_int8(imm8);
2092 }
2093
2094
2095 void Assembler::movb(Address dst, Register src) {
2096 assert(src->has_byte_register(), "must have byte register");
2097 InstructionMark im(this);
2098 prefix(dst, src, true);
2099 emit_int8((unsigned char)0x88);
2100 emit_operand(src, dst);
2101 }
2102
2103 void Assembler::movdl(XMMRegister dst, Register src) {
2104 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2105 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, true);
2106 emit_int8(0x6E);
2107 emit_int8((unsigned char)(0xC0 | encode));
2108 }
2109
2110 void Assembler::movdl(Register dst, XMMRegister src) {
2111 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2112 // swap src/dst to get correct prefix
2113 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66, true);
2114 emit_int8(0x7E);
2115 emit_int8((unsigned char)(0xC0 | encode));
2116 }
2117
2118 void Assembler::movdl(XMMRegister dst, Address src) {
2119 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2120 if (VM_Version::supports_evex()) {
2121 tuple_type = EVEX_T1S;
2122 input_size_in_bits = EVEX_32bit;
2123 }
2124 InstructionMark im(this);
2125 simd_prefix(dst, src, VEX_SIMD_66, true, VEX_OPCODE_0F);
2126 emit_int8(0x6E);
2127 emit_operand(dst, src);
2128 }
2129
2130 void Assembler::movdl(Address dst, XMMRegister src) {
2131 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2132 if (VM_Version::supports_evex()) {
2133 tuple_type = EVEX_T1S;
2134 input_size_in_bits = EVEX_32bit;
2135 }
2136 InstructionMark im(this);
2137 simd_prefix(dst, src, VEX_SIMD_66, true);
2138 emit_int8(0x7E);
2139 emit_operand(src, dst);
2140 }
2141
2142 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2143 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2144 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
2145 }
2146
2147 void Assembler::movdqa(XMMRegister dst, Address src) {
2148 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2149 if (VM_Version::supports_evex()) {
2150 tuple_type = EVEX_FVM;
2151 }
2152 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
2153 }
2154
2155 void Assembler::movdqu(XMMRegister dst, Address src) {
2156 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2157 if (VM_Version::supports_evex()) {
2158 tuple_type = EVEX_FVM;
2159 }
2160 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
2161 }
2162
2163 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2164 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2165 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
2166 }
2167
2168 void Assembler::movdqu(Address dst, XMMRegister src) {
2169 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2170 if (VM_Version::supports_evex()) {
2171 tuple_type = EVEX_FVM;
2172 }
2173 InstructionMark im(this);
2174 simd_prefix(dst, src, VEX_SIMD_F3, false);
2175 emit_int8(0x7F);
2176 emit_operand(src, dst);
2177 }
2178
2179 // Move Unaligned 256bit Vector
2180 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2181 assert(UseAVX > 0, "");
2182 if (VM_Version::supports_evex()) {
2183 tuple_type = EVEX_FVM;
2184 }
2185 int vector_len = AVX_256bit;
2186 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector_len);
2187 emit_int8(0x6F);
2188 emit_int8((unsigned char)(0xC0 | encode));
2189 }
2190
2191 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2192 assert(UseAVX > 0, "");
2193 if (VM_Version::supports_evex()) {
2194 tuple_type = EVEX_FVM;
2195 }
2196 InstructionMark im(this);
2197 int vector_len = AVX_256bit;
2198 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2199 emit_int8(0x6F);
2200 emit_operand(dst, src);
2201 }
2202
2203 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2204 assert(UseAVX > 0, "");
2205 if (VM_Version::supports_evex()) {
2206 tuple_type = EVEX_FVM;
2207 }
2208 InstructionMark im(this);
2209 int vector_len = AVX_256bit;
2210 // swap src<->dst for encoding
2211 assert(src != xnoreg, "sanity");
2212 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2213 emit_int8(0x7F);
2214 emit_operand(src, dst);
2215 }
2216
2217 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2218 void Assembler::evmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2219 assert(UseAVX > 0, "");
2220 int src_enc = src->encoding();
2221 int dst_enc = dst->encoding();
2222 int encode = vex_prefix_and_encode(dst_enc, 0, src_enc, VEX_SIMD_F3, VEX_OPCODE_0F,
2223 true, vector_len, false, false);
2224 emit_int8(0x6F);
2225 emit_int8((unsigned char)(0xC0 | encode));
2226 }
2227
2228 void Assembler::evmovdqu(XMMRegister dst, Address src, int vector_len) {
2229 assert(UseAVX > 0, "");
2230 InstructionMark im(this);
2231 if (VM_Version::supports_evex()) {
2232 tuple_type = EVEX_FVM;
2233 vex_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2234 } else {
2235 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector_len, false);
2236 }
2237 emit_int8(0x6F);
2238 emit_operand(dst, src);
2239 }
2240
2241 void Assembler::evmovdqu(Address dst, XMMRegister src, int vector_len) {
2242 assert(UseAVX > 0, "");
2243 InstructionMark im(this);
2244 assert(src != xnoreg, "sanity");
2245 if (VM_Version::supports_evex()) {
2246 tuple_type = EVEX_FVM;
2247 // swap src<->dst for encoding
2248 vex_prefix_q(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2249 } else {
2250 // swap src<->dst for encoding
2251 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector_len, false);
2252 }
2253 emit_int8(0x7F);
2254 emit_operand(src, dst);
2255 }
2256
2257 // Uses zero extension on 64bit
2258
2259 void Assembler::movl(Register dst, int32_t imm32) {
2260 int encode = prefix_and_encode(dst->encoding());
2261 emit_int8((unsigned char)(0xB8 | encode));
2262 emit_int32(imm32);
2263 }
2264
2265 void Assembler::movl(Register dst, Register src) {
2266 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2267 emit_int8((unsigned char)0x8B);
2268 emit_int8((unsigned char)(0xC0 | encode));
2269 }
2270
2271 void Assembler::movl(Register dst, Address src) {
2272 InstructionMark im(this);
2273 prefix(src, dst);
2274 emit_int8((unsigned char)0x8B);
2275 emit_operand(dst, src);
2276 }
2277
2278 void Assembler::movl(Address dst, int32_t imm32) {
2279 InstructionMark im(this);
2280 prefix(dst);
2281 emit_int8((unsigned char)0xC7);
2282 emit_operand(rax, dst, 4);
2283 emit_int32(imm32);
2284 }
2285
2286 void Assembler::movl(Address dst, Register src) {
2287 InstructionMark im(this);
2288 prefix(dst, src);
2289 emit_int8((unsigned char)0x89);
2290 emit_operand(src, dst);
2291 }
2292
2293 // New cpus require to use movsd and movss to avoid partial register stall
2294 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2295 // The selection is done in MacroAssembler::movdbl() and movflt().
2296 void Assembler::movlpd(XMMRegister dst, Address src) {
2297 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2298 if (VM_Version::supports_evex()) {
2299 tuple_type = EVEX_T1S;
2300 input_size_in_bits = EVEX_32bit;
2301 }
2302 emit_simd_arith(0x12, dst, src, VEX_SIMD_66, true);
2303 }
2304
2305 void Assembler::movq( MMXRegister dst, Address src ) {
2306 assert( VM_Version::supports_mmx(), "" );
2307 emit_int8(0x0F);
2308 emit_int8(0x6F);
2309 emit_operand(dst, src);
2310 }
2311
2312 void Assembler::movq( Address dst, MMXRegister src ) {
2313 assert( VM_Version::supports_mmx(), "" );
2314 emit_int8(0x0F);
2315 emit_int8(0x7F);
2316 // workaround gcc (3.2.1-7a) bug
2317 // In that version of gcc with only an emit_operand(MMX, Address)
2318 // gcc will tail jump and try and reverse the parameters completely
2319 // obliterating dst in the process. By having a version available
2320 // that doesn't need to swap the args at the tail jump the bug is
2321 // avoided.
2322 emit_operand(dst, src);
2323 }
2324
2325 void Assembler::movq(XMMRegister dst, Address src) {
2326 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2327 InstructionMark im(this);
2328 if (VM_Version::supports_evex()) {
2329 tuple_type = EVEX_T1S;
2330 input_size_in_bits = EVEX_64bit;
2331 simd_prefix_q(dst, xnoreg, src, VEX_SIMD_F3, true);
2332 } else {
2333 simd_prefix(dst, src, VEX_SIMD_F3, true, VEX_OPCODE_0F);
2334 }
2335 emit_int8(0x7E);
2336 emit_operand(dst, src);
2337 }
2338
2339 void Assembler::movq(Address dst, XMMRegister src) {
2340 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2341 InstructionMark im(this);
2342 if (VM_Version::supports_evex()) {
2343 tuple_type = EVEX_T1S;
2344 input_size_in_bits = EVEX_64bit;
2345 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, true,
2346 VEX_OPCODE_0F, true, AVX_128bit);
2347 } else {
2348 simd_prefix(dst, src, VEX_SIMD_66, true);
2349 }
2350 emit_int8((unsigned char)0xD6);
2351 emit_operand(src, dst);
2352 }
2353
2354 void Assembler::movsbl(Register dst, Address src) { // movsxb
2355 InstructionMark im(this);
2356 prefix(src, dst);
2357 emit_int8(0x0F);
2358 emit_int8((unsigned char)0xBE);
2359 emit_operand(dst, src);
2360 }
2361
2362 void Assembler::movsbl(Register dst, Register src) { // movsxb
2363 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2364 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2365 emit_int8(0x0F);
2366 emit_int8((unsigned char)0xBE);
2367 emit_int8((unsigned char)(0xC0 | encode));
2368 }
2369
2370 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2371 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2372 if (VM_Version::supports_evex()) {
2373 emit_simd_arith_q(0x10, dst, src, VEX_SIMD_F2, true);
2374 } else {
2375 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
2376 }
2377 }
2378
2379 void Assembler::movsd(XMMRegister dst, Address src) {
2380 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2381 if (VM_Version::supports_evex()) {
2382 tuple_type = EVEX_T1S;
2383 input_size_in_bits = EVEX_64bit;
2384 emit_simd_arith_nonds_q(0x10, dst, src, VEX_SIMD_F2, true);
2385 } else {
2386 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
2387 }
2388 }
2389
2390 void Assembler::movsd(Address dst, XMMRegister src) {
2391 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2392 InstructionMark im(this);
2393 if (VM_Version::supports_evex()) {
2394 tuple_type = EVEX_T1S;
2395 input_size_in_bits = EVEX_64bit;
2396 simd_prefix_q(src, xnoreg, dst, VEX_SIMD_F2);
2397 } else {
2398 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, false);
2399 }
2400 emit_int8(0x11);
2401 emit_operand(src, dst);
2402 }
2403
2404 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2405 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2406 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3, true);
2407 }
2408
2409 void Assembler::movss(XMMRegister dst, Address src) {
2410 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2411 if (VM_Version::supports_evex()) {
2412 tuple_type = EVEX_T1S;
2413 input_size_in_bits = EVEX_32bit;
2414 }
2415 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3, true);
2416 }
2417
2418 void Assembler::movss(Address dst, XMMRegister src) {
2419 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2420 if (VM_Version::supports_evex()) {
2421 tuple_type = EVEX_T1S;
2422 input_size_in_bits = EVEX_32bit;
2423 }
2424 InstructionMark im(this);
2425 simd_prefix(dst, src, VEX_SIMD_F3, false);
2426 emit_int8(0x11);
2427 emit_operand(src, dst);
2428 }
2429
2430 void Assembler::movswl(Register dst, Address src) { // movsxw
2431 InstructionMark im(this);
2432 prefix(src, dst);
2433 emit_int8(0x0F);
2434 emit_int8((unsigned char)0xBF);
2435 emit_operand(dst, src);
2436 }
2437
2438 void Assembler::movswl(Register dst, Register src) { // movsxw
2439 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2440 emit_int8(0x0F);
2441 emit_int8((unsigned char)0xBF);
2442 emit_int8((unsigned char)(0xC0 | encode));
2443 }
2444
2445 void Assembler::movw(Address dst, int imm16) {
2446 InstructionMark im(this);
2447
2448 emit_int8(0x66); // switch to 16-bit mode
2449 prefix(dst);
2450 emit_int8((unsigned char)0xC7);
2451 emit_operand(rax, dst, 2);
2452 emit_int16(imm16);
2453 }
2454
2455 void Assembler::movw(Register dst, Address src) {
2456 InstructionMark im(this);
2457 emit_int8(0x66);
2458 prefix(src, dst);
2459 emit_int8((unsigned char)0x8B);
2460 emit_operand(dst, src);
2461 }
2462
2463 void Assembler::movw(Address dst, Register src) {
2464 InstructionMark im(this);
2465 emit_int8(0x66);
2466 prefix(dst, src);
2467 emit_int8((unsigned char)0x89);
2468 emit_operand(src, dst);
2469 }
2470
2471 void Assembler::movzbl(Register dst, Address src) { // movzxb
2472 InstructionMark im(this);
2473 prefix(src, dst);
2474 emit_int8(0x0F);
2475 emit_int8((unsigned char)0xB6);
2476 emit_operand(dst, src);
2477 }
2478
2479 void Assembler::movzbl(Register dst, Register src) { // movzxb
2480 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2481 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2482 emit_int8(0x0F);
2483 emit_int8((unsigned char)0xB6);
2484 emit_int8(0xC0 | encode);
2485 }
2486
2487 void Assembler::movzwl(Register dst, Address src) { // movzxw
2488 InstructionMark im(this);
2489 prefix(src, dst);
2490 emit_int8(0x0F);
2491 emit_int8((unsigned char)0xB7);
2492 emit_operand(dst, src);
2493 }
2494
2495 void Assembler::movzwl(Register dst, Register src) { // movzxw
2496 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2497 emit_int8(0x0F);
2498 emit_int8((unsigned char)0xB7);
2499 emit_int8(0xC0 | encode);
2500 }
2501
2502 void Assembler::mull(Address src) {
2503 InstructionMark im(this);
2504 prefix(src);
2505 emit_int8((unsigned char)0xF7);
2506 emit_operand(rsp, src);
2507 }
2508
2509 void Assembler::mull(Register src) {
2510 int encode = prefix_and_encode(src->encoding());
2511 emit_int8((unsigned char)0xF7);
2512 emit_int8((unsigned char)(0xE0 | encode));
2513 }
2514
2515 void Assembler::mulsd(XMMRegister dst, Address src) {
2516 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2517 if (VM_Version::supports_evex()) {
2518 tuple_type = EVEX_T1S;
2519 input_size_in_bits = EVEX_64bit;
2520 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2);
2521 } else {
2522 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2523 }
2524 }
2525
2526 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2527 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2528 if (VM_Version::supports_evex()) {
2529 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_F2);
2530 } else {
2531 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2532 }
2533 }
2534
2535 void Assembler::mulss(XMMRegister dst, Address src) {
2536 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2537 if (VM_Version::supports_evex()) {
2538 tuple_type = EVEX_T1S;
2539 input_size_in_bits = EVEX_32bit;
2540 }
2541 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2542 }
2543
2544 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2545 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2546 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2547 }
2548
2549 void Assembler::negl(Register dst) {
2550 int encode = prefix_and_encode(dst->encoding());
2551 emit_int8((unsigned char)0xF7);
2552 emit_int8((unsigned char)(0xD8 | encode));
2553 }
2554
2555 void Assembler::nop(int i) {
2556 #ifdef ASSERT
2557 assert(i > 0, " ");
2558 // The fancy nops aren't currently recognized by debuggers making it a
2559 // pain to disassemble code while debugging. If asserts are on clearly
2560 // speed is not an issue so simply use the single byte traditional nop
2561 // to do alignment.
2562
2563 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2564 return;
2565
2566 #endif // ASSERT
2567
2568 if (UseAddressNop && VM_Version::is_intel()) {
2569 //
2570 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2571 // 1: 0x90
2572 // 2: 0x66 0x90
2573 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2574 // 4: 0x0F 0x1F 0x40 0x00
2575 // 5: 0x0F 0x1F 0x44 0x00 0x00
2576 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2577 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2578 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2579 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2580 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2581 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2582
2583 // The rest coding is Intel specific - don't use consecutive address nops
2584
2585 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2586 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2587 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2588 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2589
2590 while(i >= 15) {
2591 // For Intel don't generate consecutive addess nops (mix with regular nops)
2592 i -= 15;
2593 emit_int8(0x66); // size prefix
2594 emit_int8(0x66); // size prefix
2595 emit_int8(0x66); // size prefix
2596 addr_nop_8();
2597 emit_int8(0x66); // size prefix
2598 emit_int8(0x66); // size prefix
2599 emit_int8(0x66); // size prefix
2600 emit_int8((unsigned char)0x90);
2601 // nop
2602 }
2603 switch (i) {
2604 case 14:
2605 emit_int8(0x66); // size prefix
2606 case 13:
2607 emit_int8(0x66); // size prefix
2608 case 12:
2609 addr_nop_8();
2610 emit_int8(0x66); // size prefix
2611 emit_int8(0x66); // size prefix
2612 emit_int8(0x66); // size prefix
2613 emit_int8((unsigned char)0x90);
2614 // nop
2615 break;
2616 case 11:
2617 emit_int8(0x66); // size prefix
2618 case 10:
2619 emit_int8(0x66); // size prefix
2620 case 9:
2621 emit_int8(0x66); // size prefix
2622 case 8:
2623 addr_nop_8();
2624 break;
2625 case 7:
2626 addr_nop_7();
2627 break;
2628 case 6:
2629 emit_int8(0x66); // size prefix
2630 case 5:
2631 addr_nop_5();
2632 break;
2633 case 4:
2634 addr_nop_4();
2635 break;
2636 case 3:
2637 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2638 emit_int8(0x66); // size prefix
2639 case 2:
2640 emit_int8(0x66); // size prefix
2641 case 1:
2642 emit_int8((unsigned char)0x90);
2643 // nop
2644 break;
2645 default:
2646 assert(i == 0, " ");
2647 }
2648 return;
2649 }
2650 if (UseAddressNop && VM_Version::is_amd()) {
2651 //
2652 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2653 // 1: 0x90
2654 // 2: 0x66 0x90
2655 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2656 // 4: 0x0F 0x1F 0x40 0x00
2657 // 5: 0x0F 0x1F 0x44 0x00 0x00
2658 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2659 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2660 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2661 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2662 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2663 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2664
2665 // The rest coding is AMD specific - use consecutive address nops
2666
2667 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2668 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2669 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2670 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2671 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2672 // Size prefixes (0x66) are added for larger sizes
2673
2674 while(i >= 22) {
2675 i -= 11;
2676 emit_int8(0x66); // size prefix
2677 emit_int8(0x66); // size prefix
2678 emit_int8(0x66); // size prefix
2679 addr_nop_8();
2680 }
2681 // Generate first nop for size between 21-12
2682 switch (i) {
2683 case 21:
2684 i -= 1;
2685 emit_int8(0x66); // size prefix
2686 case 20:
2687 case 19:
2688 i -= 1;
2689 emit_int8(0x66); // size prefix
2690 case 18:
2691 case 17:
2692 i -= 1;
2693 emit_int8(0x66); // size prefix
2694 case 16:
2695 case 15:
2696 i -= 8;
2697 addr_nop_8();
2698 break;
2699 case 14:
2700 case 13:
2701 i -= 7;
2702 addr_nop_7();
2703 break;
2704 case 12:
2705 i -= 6;
2706 emit_int8(0x66); // size prefix
2707 addr_nop_5();
2708 break;
2709 default:
2710 assert(i < 12, " ");
2711 }
2712
2713 // Generate second nop for size between 11-1
2714 switch (i) {
2715 case 11:
2716 emit_int8(0x66); // size prefix
2717 case 10:
2718 emit_int8(0x66); // size prefix
2719 case 9:
2720 emit_int8(0x66); // size prefix
2721 case 8:
2722 addr_nop_8();
2723 break;
2724 case 7:
2725 addr_nop_7();
2726 break;
2727 case 6:
2728 emit_int8(0x66); // size prefix
2729 case 5:
2730 addr_nop_5();
2731 break;
2732 case 4:
2733 addr_nop_4();
2734 break;
2735 case 3:
2736 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2737 emit_int8(0x66); // size prefix
2738 case 2:
2739 emit_int8(0x66); // size prefix
2740 case 1:
2741 emit_int8((unsigned char)0x90);
2742 // nop
2743 break;
2744 default:
2745 assert(i == 0, " ");
2746 }
2747 return;
2748 }
2749
2750 // Using nops with size prefixes "0x66 0x90".
2751 // From AMD Optimization Guide:
2752 // 1: 0x90
2753 // 2: 0x66 0x90
2754 // 3: 0x66 0x66 0x90
2755 // 4: 0x66 0x66 0x66 0x90
2756 // 5: 0x66 0x66 0x90 0x66 0x90
2757 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2758 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2759 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2760 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2761 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2762 //
2763 while(i > 12) {
2764 i -= 4;
2765 emit_int8(0x66); // size prefix
2766 emit_int8(0x66);
2767 emit_int8(0x66);
2768 emit_int8((unsigned char)0x90);
2769 // nop
2770 }
2771 // 1 - 12 nops
2772 if(i > 8) {
2773 if(i > 9) {
2774 i -= 1;
2775 emit_int8(0x66);
2776 }
2777 i -= 3;
2778 emit_int8(0x66);
2779 emit_int8(0x66);
2780 emit_int8((unsigned char)0x90);
2781 }
2782 // 1 - 8 nops
2783 if(i > 4) {
2784 if(i > 6) {
2785 i -= 1;
2786 emit_int8(0x66);
2787 }
2788 i -= 3;
2789 emit_int8(0x66);
2790 emit_int8(0x66);
2791 emit_int8((unsigned char)0x90);
2792 }
2793 switch (i) {
2794 case 4:
2795 emit_int8(0x66);
2796 case 3:
2797 emit_int8(0x66);
2798 case 2:
2799 emit_int8(0x66);
2800 case 1:
2801 emit_int8((unsigned char)0x90);
2802 break;
2803 default:
2804 assert(i == 0, " ");
2805 }
2806 }
2807
2808 void Assembler::notl(Register dst) {
2809 int encode = prefix_and_encode(dst->encoding());
2810 emit_int8((unsigned char)0xF7);
2811 emit_int8((unsigned char)(0xD0 | encode));
2812 }
2813
2814 void Assembler::orl(Address dst, int32_t imm32) {
2815 InstructionMark im(this);
2816 prefix(dst);
2817 emit_arith_operand(0x81, rcx, dst, imm32);
2818 }
2819
2820 void Assembler::orl(Register dst, int32_t imm32) {
2821 prefix(dst);
2822 emit_arith(0x81, 0xC8, dst, imm32);
2823 }
2824
2825 void Assembler::orl(Register dst, Address src) {
2826 InstructionMark im(this);
2827 prefix(src, dst);
2828 emit_int8(0x0B);
2829 emit_operand(dst, src);
2830 }
2831
2832 void Assembler::orl(Register dst, Register src) {
2833 (void) prefix_and_encode(dst->encoding(), src->encoding());
2834 emit_arith(0x0B, 0xC0, dst, src);
2835 }
2836
2837 void Assembler::orl(Address dst, Register src) {
2838 InstructionMark im(this);
2839 prefix(dst, src);
2840 emit_int8(0x09);
2841 emit_operand(src, dst);
2842 }
2843
2844 void Assembler::packuswb(XMMRegister dst, Address src) {
2845 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2846 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2847 if (VM_Version::supports_evex()) {
2848 tuple_type = EVEX_FV;
2849 input_size_in_bits = EVEX_32bit;
2850 }
2851 emit_simd_arith(0x67, dst, src, VEX_SIMD_66,
2852 false, (VM_Version::supports_avx512dq() == false));
2853 }
2854
2855 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2856 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2857 emit_simd_arith(0x67, dst, src, VEX_SIMD_66,
2858 false, (VM_Version::supports_avx512dq() == false));
2859 }
2860
2861 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2862 assert(UseAVX > 0, "some form of AVX must be enabled");
2863 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector_len,
2864 false, (VM_Version::supports_avx512dq() == false));
2865 }
2866
2867 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
2868 assert(VM_Version::supports_avx2(), "");
2869 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false,
2870 VEX_OPCODE_0F_3A, true, vector_len);
2871 emit_int8(0x00);
2872 emit_int8(0xC0 | encode);
2873 emit_int8(imm8);
2874 }
2875
2876 void Assembler::pause() {
2877 emit_int8((unsigned char)0xF3);
2878 emit_int8((unsigned char)0x90);
2879 }
2880
2881 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2882 assert(VM_Version::supports_sse4_2(), "");
2883 InstructionMark im(this);
2884 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, false, VEX_OPCODE_0F_3A,
2885 false, AVX_128bit, true);
2886 emit_int8(0x61);
2887 emit_operand(dst, src);
2888 emit_int8(imm8);
2889 }
2890
2891 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2892 assert(VM_Version::supports_sse4_2(), "");
2893 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false,
2894 VEX_OPCODE_0F_3A, false, AVX_128bit, true);
2895 emit_int8(0x61);
2896 emit_int8((unsigned char)(0xC0 | encode));
2897 emit_int8(imm8);
2898 }
2899
2900 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
2901 assert(VM_Version::supports_sse4_1(), "");
2902 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2903 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2904 emit_int8(0x16);
2905 emit_int8((unsigned char)(0xC0 | encode));
2906 emit_int8(imm8);
2907 }
2908
2909 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
2910 assert(VM_Version::supports_sse4_1(), "");
2911 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2912 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2913 emit_int8(0x16);
2914 emit_int8((unsigned char)(0xC0 | encode));
2915 emit_int8(imm8);
2916 }
2917
2918 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
2919 assert(VM_Version::supports_sse4_1(), "");
2920 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2921 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2922 emit_int8(0x22);
2923 emit_int8((unsigned char)(0xC0 | encode));
2924 emit_int8(imm8);
2925 }
2926
2927 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
2928 assert(VM_Version::supports_sse4_1(), "");
2929 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, true, VEX_OPCODE_0F_3A,
2930 false, AVX_128bit, (VM_Version::supports_avx512dq() == false));
2931 emit_int8(0x22);
2932 emit_int8((unsigned char)(0xC0 | encode));
2933 emit_int8(imm8);
2934 }
2935
2936 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2937 assert(VM_Version::supports_sse4_1(), "");
2938 if (VM_Version::supports_evex()) {
2939 tuple_type = EVEX_HVM;
2940 }
2941 InstructionMark im(this);
2942 simd_prefix(dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38);
2943 emit_int8(0x30);
2944 emit_operand(dst, src);
2945 }
2946
2947 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2948 assert(VM_Version::supports_sse4_1(), "");
2949 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38);
2950 emit_int8(0x30);
2951 emit_int8((unsigned char)(0xC0 | encode));
2952 }
2953
2954 // generic
2955 void Assembler::pop(Register dst) {
2956 int encode = prefix_and_encode(dst->encoding());
2957 emit_int8(0x58 | encode);
2958 }
2959
2960 void Assembler::popcntl(Register dst, Address src) {
2961 assert(VM_Version::supports_popcnt(), "must support");
2962 InstructionMark im(this);
2963 emit_int8((unsigned char)0xF3);
2964 prefix(src, dst);
2965 emit_int8(0x0F);
2966 emit_int8((unsigned char)0xB8);
2967 emit_operand(dst, src);
2968 }
2969
2970 void Assembler::popcntl(Register dst, Register src) {
2971 assert(VM_Version::supports_popcnt(), "must support");
2972 emit_int8((unsigned char)0xF3);
2973 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2974 emit_int8(0x0F);
2975 emit_int8((unsigned char)0xB8);
2976 emit_int8((unsigned char)(0xC0 | encode));
2977 }
2978
2979 void Assembler::popf() {
2980 emit_int8((unsigned char)0x9D);
2981 }
2982
2983 #ifndef _LP64 // no 32bit push/pop on amd64
2984 void Assembler::popl(Address dst) {
2985 // NOTE: this will adjust stack by 8byte on 64bits
2986 InstructionMark im(this);
2987 prefix(dst);
2988 emit_int8((unsigned char)0x8F);
2989 emit_operand(rax, dst);
2990 }
2991 #endif
2992
2993 void Assembler::prefetch_prefix(Address src) {
2994 prefix(src);
2995 emit_int8(0x0F);
2996 }
2997
2998 void Assembler::prefetchnta(Address src) {
2999 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3000 InstructionMark im(this);
3001 prefetch_prefix(src);
3002 emit_int8(0x18);
3003 emit_operand(rax, src); // 0, src
3004 }
3005
3006 void Assembler::prefetchr(Address src) {
3007 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3008 InstructionMark im(this);
3009 prefetch_prefix(src);
3010 emit_int8(0x0D);
3011 emit_operand(rax, src); // 0, src
3012 }
3013
3014 void Assembler::prefetcht0(Address src) {
3015 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3016 InstructionMark im(this);
3017 prefetch_prefix(src);
3018 emit_int8(0x18);
3019 emit_operand(rcx, src); // 1, src
3020 }
3021
3022 void Assembler::prefetcht1(Address src) {
3023 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3024 InstructionMark im(this);
3025 prefetch_prefix(src);
3026 emit_int8(0x18);
3027 emit_operand(rdx, src); // 2, src
3028 }
3029
3030 void Assembler::prefetcht2(Address src) {
3031 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3032 InstructionMark im(this);
3033 prefetch_prefix(src);
3034 emit_int8(0x18);
3035 emit_operand(rbx, src); // 3, src
3036 }
3037
3038 void Assembler::prefetchw(Address src) {
3039 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3040 InstructionMark im(this);
3041 prefetch_prefix(src);
3042 emit_int8(0x0D);
3043 emit_operand(rcx, src); // 1, src
3044 }
3045
3046 void Assembler::prefix(Prefix p) {
3047 emit_int8(p);
3048 }
3049
3050 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3051 assert(VM_Version::supports_ssse3(), "");
3052 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38,
3053 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3054 emit_int8(0x00);
3055 emit_int8((unsigned char)(0xC0 | encode));
3056 }
3057
3058 void Assembler::pshufb(XMMRegister dst, Address src) {
3059 assert(VM_Version::supports_ssse3(), "");
3060 if (VM_Version::supports_evex()) {
3061 tuple_type = EVEX_FVM;
3062 }
3063 InstructionMark im(this);
3064 simd_prefix(dst, dst, src, VEX_SIMD_66, false, VEX_OPCODE_0F_38,
3065 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3066 emit_int8(0x00);
3067 emit_operand(dst, src);
3068 }
3069
3070 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3071 assert(isByte(mode), "invalid value");
3072 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3073 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
3074 emit_int8(mode & 0xFF);
3075
3076 }
3077
3078 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3079 assert(isByte(mode), "invalid value");
3080 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3081 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3082 if (VM_Version::supports_evex()) {
3083 tuple_type = EVEX_FV;
3084 input_size_in_bits = EVEX_32bit;
3085 }
3086 InstructionMark im(this);
3087 simd_prefix(dst, src, VEX_SIMD_66, false);
3088 emit_int8(0x70);
3089 emit_operand(dst, src);
3090 emit_int8(mode & 0xFF);
3091 }
3092
3093 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3094 assert(isByte(mode), "invalid value");
3095 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3096 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2, false,
3097 (VM_Version::supports_avx512bw() == false));
3098 emit_int8(mode & 0xFF);
3099 }
3100
3101 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3102 assert(isByte(mode), "invalid value");
3103 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3104 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3105 if (VM_Version::supports_evex()) {
3106 tuple_type = EVEX_FVM;
3107 }
3108 InstructionMark im(this);
3109 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, false, VEX_OPCODE_0F,
3110 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3111 emit_int8(0x70);
3112 emit_operand(dst, src);
3113 emit_int8(mode & 0xFF);
3114 }
3115
3116 void Assembler::psrldq(XMMRegister dst, int shift) {
3117 // Shift 128 bit value in xmm register by number of bytes.
3118 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3119 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3120 emit_int8(0x73);
3121 emit_int8((unsigned char)(0xC0 | encode));
3122 emit_int8(shift);
3123 }
3124
3125 void Assembler::pslldq(XMMRegister dst, int shift) {
3126 // Shift left 128 bit value in xmm register by number of bytes.
3127 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3128 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
3129 emit_int8(0x73);
3130 emit_int8((unsigned char)(0xC0 | encode));
3131 emit_int8(shift);
3132 }
3133
3134 void Assembler::ptest(XMMRegister dst, Address src) {
3135 assert(VM_Version::supports_sse4_1(), "");
3136 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3137 InstructionMark im(this);
3138 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, false,
3139 VEX_OPCODE_0F_38, false, AVX_128bit, true);
3140 emit_int8(0x17);
3141 emit_operand(dst, src);
3142 }
3143
3144 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3145 assert(VM_Version::supports_sse4_1(), "");
3146 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, false,
3147 VEX_OPCODE_0F_38, false, AVX_128bit, true);
3148 emit_int8(0x17);
3149 emit_int8((unsigned char)(0xC0 | encode));
3150 }
3151
3152 void Assembler::vptest(XMMRegister dst, Address src) {
3153 assert(VM_Version::supports_avx(), "");
3154 InstructionMark im(this);
3155 int vector_len = AVX_256bit;
3156 assert(dst != xnoreg, "sanity");
3157 int dst_enc = dst->encoding();
3158 // swap src<->dst for encoding
3159 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len, true, false);
3160 emit_int8(0x17);
3161 emit_operand(dst, src);
3162 }
3163
3164 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3165 assert(VM_Version::supports_avx(), "");
3166 int vector_len = AVX_256bit;
3167 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
3168 vector_len, VEX_OPCODE_0F_38, true, false);
3169 emit_int8(0x17);
3170 emit_int8((unsigned char)(0xC0 | encode));
3171 }
3172
3173 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3174 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3175 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3176 if (VM_Version::supports_evex()) {
3177 tuple_type = EVEX_FVM;
3178 }
3179 emit_simd_arith(0x60, dst, src, VEX_SIMD_66, false, (VM_Version::supports_avx512vlbw() == false));
3180 }
3181
3182 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3183 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3184 emit_simd_arith(0x60, dst, src, VEX_SIMD_66, false, (VM_Version::supports_avx512vlbw() == false));
3185 }
3186
3187 void Assembler::punpckldq(XMMRegister dst, Address src) {
3188 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3189 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3190 if (VM_Version::supports_evex()) {
3191 tuple_type = EVEX_FV;
3192 input_size_in_bits = EVEX_32bit;
3193 }
3194 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
3195 }
3196
3197 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3198 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3199 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
3200 }
3201
3202 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3203 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3204 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
3205 }
3206
3207 void Assembler::push(int32_t imm32) {
3208 // in 64bits we push 64bits onto the stack but only
3209 // take a 32bit immediate
3210 emit_int8(0x68);
3211 emit_int32(imm32);
3212 }
3213
3214 void Assembler::push(Register src) {
3215 int encode = prefix_and_encode(src->encoding());
3216
3217 emit_int8(0x50 | encode);
3218 }
3219
3220 void Assembler::pushf() {
3221 emit_int8((unsigned char)0x9C);
3222 }
3223
3224 #ifndef _LP64 // no 32bit push/pop on amd64
3225 void Assembler::pushl(Address src) {
3226 // Note this will push 64bit on 64bit
3227 InstructionMark im(this);
3228 prefix(src);
3229 emit_int8((unsigned char)0xFF);
3230 emit_operand(rsi, src);
3231 }
3232 #endif
3233
3234 void Assembler::rcll(Register dst, int imm8) {
3235 assert(isShiftCount(imm8), "illegal shift count");
3236 int encode = prefix_and_encode(dst->encoding());
3237 if (imm8 == 1) {
3238 emit_int8((unsigned char)0xD1);
3239 emit_int8((unsigned char)(0xD0 | encode));
3240 } else {
3241 emit_int8((unsigned char)0xC1);
3242 emit_int8((unsigned char)0xD0 | encode);
3243 emit_int8(imm8);
3244 }
3245 }
3246
3247 void Assembler::rdtsc() {
3248 emit_int8((unsigned char)0x0F);
3249 emit_int8((unsigned char)0x31);
3250 }
3251
3252 // copies data from [esi] to [edi] using rcx pointer sized words
3253 // generic
3254 void Assembler::rep_mov() {
3255 emit_int8((unsigned char)0xF3);
3256 // MOVSQ
3257 LP64_ONLY(prefix(REX_W));
3258 emit_int8((unsigned char)0xA5);
3259 }
3260
3261 // sets rcx bytes with rax, value at [edi]
3262 void Assembler::rep_stosb() {
3263 emit_int8((unsigned char)0xF3); // REP
3264 LP64_ONLY(prefix(REX_W));
3265 emit_int8((unsigned char)0xAA); // STOSB
3266 }
3267
3268 // sets rcx pointer sized words with rax, value at [edi]
3269 // generic
3270 void Assembler::rep_stos() {
3271 emit_int8((unsigned char)0xF3); // REP
3272 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3273 emit_int8((unsigned char)0xAB);
3274 }
3275
3276 // scans rcx pointer sized words at [edi] for occurance of rax,
3277 // generic
3278 void Assembler::repne_scan() { // repne_scan
3279 emit_int8((unsigned char)0xF2);
3280 // SCASQ
3281 LP64_ONLY(prefix(REX_W));
3282 emit_int8((unsigned char)0xAF);
3283 }
3284
3285 #ifdef _LP64
3286 // scans rcx 4 byte words at [edi] for occurance of rax,
3287 // generic
3288 void Assembler::repne_scanl() { // repne_scan
3289 emit_int8((unsigned char)0xF2);
3290 // SCASL
3291 emit_int8((unsigned char)0xAF);
3292 }
3293 #endif
3294
3295 void Assembler::ret(int imm16) {
3296 if (imm16 == 0) {
3297 emit_int8((unsigned char)0xC3);
3298 } else {
3299 emit_int8((unsigned char)0xC2);
3300 emit_int16(imm16);
3301 }
3302 }
3303
3304 void Assembler::sahf() {
3305 #ifdef _LP64
3306 // Not supported in 64bit mode
3307 ShouldNotReachHere();
3308 #endif
3309 emit_int8((unsigned char)0x9E);
3310 }
3311
3312 void Assembler::sarl(Register dst, int imm8) {
3313 int encode = prefix_and_encode(dst->encoding());
3314 assert(isShiftCount(imm8), "illegal shift count");
3315 if (imm8 == 1) {
3316 emit_int8((unsigned char)0xD1);
3317 emit_int8((unsigned char)(0xF8 | encode));
3318 } else {
3319 emit_int8((unsigned char)0xC1);
3320 emit_int8((unsigned char)(0xF8 | encode));
3321 emit_int8(imm8);
3322 }
3323 }
3324
3325 void Assembler::sarl(Register dst) {
3326 int encode = prefix_and_encode(dst->encoding());
3327 emit_int8((unsigned char)0xD3);
3328 emit_int8((unsigned char)(0xF8 | encode));
3329 }
3330
3331 void Assembler::sbbl(Address dst, int32_t imm32) {
3332 InstructionMark im(this);
3333 prefix(dst);
3334 emit_arith_operand(0x81, rbx, dst, imm32);
3335 }
3336
3337 void Assembler::sbbl(Register dst, int32_t imm32) {
3338 prefix(dst);
3339 emit_arith(0x81, 0xD8, dst, imm32);
3340 }
3341
3342
3343 void Assembler::sbbl(Register dst, Address src) {
3344 InstructionMark im(this);
3345 prefix(src, dst);
3346 emit_int8(0x1B);
3347 emit_operand(dst, src);
3348 }
3349
3350 void Assembler::sbbl(Register dst, Register src) {
3351 (void) prefix_and_encode(dst->encoding(), src->encoding());
3352 emit_arith(0x1B, 0xC0, dst, src);
3353 }
3354
3355 void Assembler::setb(Condition cc, Register dst) {
3356 assert(0 <= cc && cc < 16, "illegal cc");
3357 int encode = prefix_and_encode(dst->encoding(), true);
3358 emit_int8(0x0F);
3359 emit_int8((unsigned char)0x90 | cc);
3360 emit_int8((unsigned char)(0xC0 | encode));
3361 }
3362
3363 void Assembler::shll(Register dst, int imm8) {
3364 assert(isShiftCount(imm8), "illegal shift count");
3365 int encode = prefix_and_encode(dst->encoding());
3366 if (imm8 == 1 ) {
3367 emit_int8((unsigned char)0xD1);
3368 emit_int8((unsigned char)(0xE0 | encode));
3369 } else {
3370 emit_int8((unsigned char)0xC1);
3371 emit_int8((unsigned char)(0xE0 | encode));
3372 emit_int8(imm8);
3373 }
3374 }
3375
3376 void Assembler::shll(Register dst) {
3377 int encode = prefix_and_encode(dst->encoding());
3378 emit_int8((unsigned char)0xD3);
3379 emit_int8((unsigned char)(0xE0 | encode));
3380 }
3381
3382 void Assembler::shrl(Register dst, int imm8) {
3383 assert(isShiftCount(imm8), "illegal shift count");
3384 int encode = prefix_and_encode(dst->encoding());
3385 emit_int8((unsigned char)0xC1);
3386 emit_int8((unsigned char)(0xE8 | encode));
3387 emit_int8(imm8);
3388 }
3389
3390 void Assembler::shrl(Register dst) {
3391 int encode = prefix_and_encode(dst->encoding());
3392 emit_int8((unsigned char)0xD3);
3393 emit_int8((unsigned char)(0xE8 | encode));
3394 }
3395
3396 // copies a single word from [esi] to [edi]
3397 void Assembler::smovl() {
3398 emit_int8((unsigned char)0xA5);
3399 }
3400
3401 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
3402 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3403 if (VM_Version::supports_evex()) {
3404 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2);
3405 } else {
3406 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
3407 }
3408 }
3409
3410 void Assembler::sqrtsd(XMMRegister dst, Address src) {
3411 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3412 if (VM_Version::supports_evex()) {
3413 tuple_type = EVEX_T1S;
3414 input_size_in_bits = EVEX_64bit;
3415 emit_simd_arith_q(0x51, dst, src, VEX_SIMD_F2);
3416 } else {
3417 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
3418 }
3419 }
3420
3421 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
3422 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3423 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
3424 }
3425
3426 void Assembler::std() {
3427 emit_int8((unsigned char)0xFD);
3428 }
3429
3430 void Assembler::sqrtss(XMMRegister dst, Address src) {
3431 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3432 if (VM_Version::supports_evex()) {
3433 tuple_type = EVEX_T1S;
3434 input_size_in_bits = EVEX_32bit;
3435 }
3436 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
3437 }
3438
3439 void Assembler::stmxcsr( Address dst) {
3440 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3441 InstructionMark im(this);
3442 prefix(dst);
3443 emit_int8(0x0F);
3444 emit_int8((unsigned char)0xAE);
3445 emit_operand(as_Register(3), dst);
3446 }
3447
3448 void Assembler::subl(Address dst, int32_t imm32) {
3449 InstructionMark im(this);
3450 prefix(dst);
3451 emit_arith_operand(0x81, rbp, dst, imm32);
3452 }
3453
3454 void Assembler::subl(Address dst, Register src) {
3455 InstructionMark im(this);
3456 prefix(dst, src);
3457 emit_int8(0x29);
3458 emit_operand(src, dst);
3459 }
3460
3461 void Assembler::subl(Register dst, int32_t imm32) {
3462 prefix(dst);
3463 emit_arith(0x81, 0xE8, dst, imm32);
3464 }
3465
3466 // Force generation of a 4 byte immediate value even if it fits into 8bit
3467 void Assembler::subl_imm32(Register dst, int32_t imm32) {
3468 prefix(dst);
3469 emit_arith_imm32(0x81, 0xE8, dst, imm32);
3470 }
3471
3472 void Assembler::subl(Register dst, Address src) {
3473 InstructionMark im(this);
3474 prefix(src, dst);
3475 emit_int8(0x2B);
3476 emit_operand(dst, src);
3477 }
3478
3479 void Assembler::subl(Register dst, Register src) {
3480 (void) prefix_and_encode(dst->encoding(), src->encoding());
3481 emit_arith(0x2B, 0xC0, dst, src);
3482 }
3483
3484 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
3485 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3486 if (VM_Version::supports_evex()) {
3487 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2);
3488 } else {
3489 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
3490 }
3491 }
3492
3493 void Assembler::subsd(XMMRegister dst, Address src) {
3494 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3495 if (VM_Version::supports_evex()) {
3496 tuple_type = EVEX_T1S;
3497 input_size_in_bits = EVEX_64bit;
3498 }
3499 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_F2);
3500 }
3501
3502 void Assembler::subss(XMMRegister dst, XMMRegister src) {
3503 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3504 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3505 }
3506
3507 void Assembler::subss(XMMRegister dst, Address src) {
3508 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3509 if (VM_Version::supports_evex()) {
3510 tuple_type = EVEX_T1S;
3511 input_size_in_bits = EVEX_32bit;
3512 }
3513 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
3514 }
3515
3516 void Assembler::testb(Register dst, int imm8) {
3517 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3518 (void) prefix_and_encode(dst->encoding(), true);
3519 emit_arith_b(0xF6, 0xC0, dst, imm8);
3520 }
3521
3522 void Assembler::testl(Register dst, int32_t imm32) {
3523 // not using emit_arith because test
3524 // doesn't support sign-extension of
3525 // 8bit operands
3526 int encode = dst->encoding();
3527 if (encode == 0) {
3528 emit_int8((unsigned char)0xA9);
3529 } else {
3530 encode = prefix_and_encode(encode);
3531 emit_int8((unsigned char)0xF7);
3532 emit_int8((unsigned char)(0xC0 | encode));
3533 }
3534 emit_int32(imm32);
3535 }
3536
3537 void Assembler::testl(Register dst, Register src) {
3538 (void) prefix_and_encode(dst->encoding(), src->encoding());
3539 emit_arith(0x85, 0xC0, dst, src);
3540 }
3541
3542 void Assembler::testl(Register dst, Address src) {
3543 InstructionMark im(this);
3544 prefix(src, dst);
3545 emit_int8((unsigned char)0x85);
3546 emit_operand(dst, src);
3547 }
3548
3549 void Assembler::tzcntl(Register dst, Register src) {
3550 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3551 emit_int8((unsigned char)0xF3);
3552 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3553 emit_int8(0x0F);
3554 emit_int8((unsigned char)0xBC);
3555 emit_int8((unsigned char)0xC0 | encode);
3556 }
3557
3558 void Assembler::tzcntq(Register dst, Register src) {
3559 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3560 emit_int8((unsigned char)0xF3);
3561 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3562 emit_int8(0x0F);
3563 emit_int8((unsigned char)0xBC);
3564 emit_int8((unsigned char)(0xC0 | encode));
3565 }
3566
3567 void Assembler::ucomisd(XMMRegister dst, Address src) {
3568 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3569 if (VM_Version::supports_evex()) {
3570 tuple_type = EVEX_T1S;
3571 input_size_in_bits = EVEX_64bit;
3572 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, true);
3573 } else {
3574 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
3575 }
3576 }
3577
3578 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
3579 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3580 if (VM_Version::supports_evex()) {
3581 emit_simd_arith_nonds_q(0x2E, dst, src, VEX_SIMD_66, true);
3582 } else {
3583 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
3584 }
3585 }
3586
3587 void Assembler::ucomiss(XMMRegister dst, Address src) {
3588 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3589 if (VM_Version::supports_evex()) {
3590 tuple_type = EVEX_T1S;
3591 input_size_in_bits = EVEX_32bit;
3592 }
3593 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, true);
3594 }
3595
3596 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
3597 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3598 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE, true);
3599 }
3600
3601 void Assembler::xabort(int8_t imm8) {
3602 emit_int8((unsigned char)0xC6);
3603 emit_int8((unsigned char)0xF8);
3604 emit_int8((unsigned char)(imm8 & 0xFF));
3605 }
3606
3607 void Assembler::xaddl(Address dst, Register src) {
3608 InstructionMark im(this);
3609 prefix(dst, src);
3610 emit_int8(0x0F);
3611 emit_int8((unsigned char)0xC1);
3612 emit_operand(src, dst);
3613 }
3614
3615 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
3616 InstructionMark im(this);
3617 relocate(rtype);
3618 if (abort.is_bound()) {
3619 address entry = target(abort);
3620 assert(entry != NULL, "abort entry NULL");
3621 intptr_t offset = entry - pc();
3622 emit_int8((unsigned char)0xC7);
3623 emit_int8((unsigned char)0xF8);
3624 emit_int32(offset - 6); // 2 opcode + 4 address
3625 } else {
3626 abort.add_patch_at(code(), locator());
3627 emit_int8((unsigned char)0xC7);
3628 emit_int8((unsigned char)0xF8);
3629 emit_int32(0);
3630 }
3631 }
3632
3633 void Assembler::xchgl(Register dst, Address src) { // xchg
3634 InstructionMark im(this);
3635 prefix(src, dst);
3636 emit_int8((unsigned char)0x87);
3637 emit_operand(dst, src);
3638 }
3639
3640 void Assembler::xchgl(Register dst, Register src) {
3641 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3642 emit_int8((unsigned char)0x87);
3643 emit_int8((unsigned char)(0xC0 | encode));
3644 }
3645
3646 void Assembler::xend() {
3647 emit_int8((unsigned char)0x0F);
3648 emit_int8((unsigned char)0x01);
3649 emit_int8((unsigned char)0xD5);
3650 }
3651
3652 void Assembler::xgetbv() {
3653 emit_int8(0x0F);
3654 emit_int8(0x01);
3655 emit_int8((unsigned char)0xD0);
3656 }
3657
3658 void Assembler::xorl(Register dst, int32_t imm32) {
3659 prefix(dst);
3660 emit_arith(0x81, 0xF0, dst, imm32);
3661 }
3662
3663 void Assembler::xorl(Register dst, Address src) {
3664 InstructionMark im(this);
3665 prefix(src, dst);
3666 emit_int8(0x33);
3667 emit_operand(dst, src);
3668 }
3669
3670 void Assembler::xorl(Register dst, Register src) {
3671 (void) prefix_and_encode(dst->encoding(), src->encoding());
3672 emit_arith(0x33, 0xC0, dst, src);
3673 }
3674
3675
3676 // AVX 3-operands scalar float-point arithmetic instructions
3677
3678 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3679 assert(VM_Version::supports_avx(), "");
3680 if (VM_Version::supports_evex()) {
3681 tuple_type = EVEX_T1S;
3682 input_size_in_bits = EVEX_64bit;
3683 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3684 } else {
3685 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3686 }
3687 }
3688
3689 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3690 assert(VM_Version::supports_avx(), "");
3691 if (VM_Version::supports_evex()) {
3692 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3693 } else {
3694 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3695 }
3696 }
3697
3698 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3699 assert(VM_Version::supports_avx(), "");
3700 if (VM_Version::supports_evex()) {
3701 tuple_type = EVEX_T1S;
3702 input_size_in_bits = EVEX_32bit;
3703 }
3704 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3705 }
3706
3707 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3708 assert(VM_Version::supports_avx(), "");
3709 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3710 }
3711
3712 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3713 assert(VM_Version::supports_avx(), "");
3714 if (VM_Version::supports_evex()) {
3715 tuple_type = EVEX_T1S;
3716 input_size_in_bits = EVEX_64bit;
3717 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3718 } else {
3719 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3720 }
3721 }
3722
3723 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3724 assert(VM_Version::supports_avx(), "");
3725 if (VM_Version::supports_evex()) {
3726 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3727 } else {
3728 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3729 }
3730 }
3731
3732 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3733 assert(VM_Version::supports_avx(), "");
3734 if (VM_Version::supports_evex()) {
3735 tuple_type = EVEX_T1S;
3736 input_size_in_bits = EVEX_32bit;
3737 }
3738 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3739 }
3740
3741 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3742 assert(VM_Version::supports_avx(), "");
3743 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3744 }
3745
3746 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3747 assert(VM_Version::supports_avx(), "");
3748 if (VM_Version::supports_evex()) {
3749 tuple_type = EVEX_T1S;
3750 input_size_in_bits = EVEX_64bit;
3751 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3752 } else {
3753 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3754 }
3755 }
3756
3757 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3758 assert(VM_Version::supports_avx(), "");
3759 if (VM_Version::supports_evex()) {
3760 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3761 } else {
3762 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3763 }
3764 }
3765
3766 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3767 assert(VM_Version::supports_avx(), "");
3768 if (VM_Version::supports_evex()) {
3769 tuple_type = EVEX_T1S;
3770 input_size_in_bits = EVEX_32bit;
3771 }
3772 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3773 }
3774
3775 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3776 assert(VM_Version::supports_avx(), "");
3777 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3778 }
3779
3780 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3781 assert(VM_Version::supports_avx(), "");
3782 if (VM_Version::supports_evex()) {
3783 tuple_type = EVEX_T1S;
3784 input_size_in_bits = EVEX_64bit;
3785 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3786 } else {
3787 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3788 }
3789 }
3790
3791 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3792 assert(VM_Version::supports_avx(), "");
3793 if (VM_Version::supports_evex()) {
3794 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3795 } else {
3796 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, AVX_128bit);
3797 }
3798 }
3799
3800 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3801 assert(VM_Version::supports_avx(), "");
3802 if (VM_Version::supports_evex()) {
3803 tuple_type = EVEX_T1S;
3804 input_size_in_bits = EVEX_32bit;
3805 }
3806 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3807 }
3808
3809 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3810 assert(VM_Version::supports_avx(), "");
3811 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, AVX_128bit);
3812 }
3813
3814 //====================VECTOR ARITHMETIC=====================================
3815
3816 // Float-point vector arithmetic
3817
3818 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
3819 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3820 if (VM_Version::supports_evex()) {
3821 emit_simd_arith_q(0x58, dst, src, VEX_SIMD_66);
3822 } else {
3823 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
3824 }
3825 }
3826
3827 void Assembler::addps(XMMRegister dst, XMMRegister src) {
3828 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3829 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
3830 }
3831
3832 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3833 assert(VM_Version::supports_avx(), "");
3834 if (VM_Version::supports_evex()) {
3835 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3836 } else {
3837 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3838 }
3839 }
3840
3841 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3842 assert(VM_Version::supports_avx(), "");
3843 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len);
3844 }
3845
3846 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3847 assert(VM_Version::supports_avx(), "");
3848 if (VM_Version::supports_evex()) {
3849 tuple_type = EVEX_FV;
3850 input_size_in_bits = EVEX_64bit;
3851 emit_vex_arith_q(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3852 } else {
3853 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector_len);
3854 }
3855 }
3856
3857 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3858 assert(VM_Version::supports_avx(), "");
3859 if (VM_Version::supports_evex()) {
3860 tuple_type = EVEX_FV;
3861 input_size_in_bits = EVEX_32bit;
3862 }
3863 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector_len);
3864 }
3865
3866 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
3867 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3868 if (VM_Version::supports_evex()) {
3869 emit_simd_arith_q(0x5C, dst, src, VEX_SIMD_66);
3870 } else {
3871 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
3872 }
3873 }
3874
3875 void Assembler::subps(XMMRegister dst, XMMRegister src) {
3876 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3877 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
3878 }
3879
3880 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3881 assert(VM_Version::supports_avx(), "");
3882 if (VM_Version::supports_evex()) {
3883 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3884 } else {
3885 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3886 }
3887 }
3888
3889 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3890 assert(VM_Version::supports_avx(), "");
3891 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len);
3892 }
3893
3894 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3895 assert(VM_Version::supports_avx(), "");
3896 if (VM_Version::supports_evex()) {
3897 tuple_type = EVEX_FV;
3898 input_size_in_bits = EVEX_64bit;
3899 emit_vex_arith_q(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3900 } else {
3901 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector_len);
3902 }
3903 }
3904
3905 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3906 assert(VM_Version::supports_avx(), "");
3907 if (VM_Version::supports_evex()) {
3908 tuple_type = EVEX_FV;
3909 input_size_in_bits = EVEX_32bit;
3910 }
3911 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector_len);
3912 }
3913
3914 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
3915 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3916 if (VM_Version::supports_evex()) {
3917 emit_simd_arith_q(0x59, dst, src, VEX_SIMD_66);
3918 } else {
3919 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
3920 }
3921 }
3922
3923 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
3924 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3925 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
3926 }
3927
3928 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3929 assert(VM_Version::supports_avx(), "");
3930 if (VM_Version::supports_evex()) {
3931 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3932 } else {
3933 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3934 }
3935 }
3936
3937 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3938 assert(VM_Version::supports_avx(), "");
3939 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len);
3940 }
3941
3942 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3943 assert(VM_Version::supports_avx(), "");
3944 if (VM_Version::supports_evex()) {
3945 tuple_type = EVEX_FV;
3946 input_size_in_bits = EVEX_64bit;
3947 emit_vex_arith_q(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3948 } else {
3949 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector_len);
3950 }
3951 }
3952
3953 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3954 assert(VM_Version::supports_avx(), "");
3955 if (VM_Version::supports_evex()) {
3956 tuple_type = EVEX_FV;
3957 input_size_in_bits = EVEX_32bit;
3958 }
3959 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector_len);
3960 }
3961
3962 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
3963 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3964 if (VM_Version::supports_evex()) {
3965 emit_simd_arith_q(0x5E, dst, src, VEX_SIMD_66);
3966 } else {
3967 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
3968 }
3969 }
3970
3971 void Assembler::divps(XMMRegister dst, XMMRegister src) {
3972 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3973 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
3974 }
3975
3976 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3977 assert(VM_Version::supports_avx(), "");
3978 if (VM_Version::supports_evex()) {
3979 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3980 } else {
3981 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3982 }
3983 }
3984
3985 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3986 assert(VM_Version::supports_avx(), "");
3987 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len);
3988 }
3989
3990 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3991 assert(VM_Version::supports_avx(), "");
3992 if (VM_Version::supports_evex()) {
3993 tuple_type = EVEX_FV;
3994 input_size_in_bits = EVEX_64bit;
3995 emit_vex_arith_q(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3996 } else {
3997 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector_len);
3998 }
3999 }
4000
4001 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4002 assert(VM_Version::supports_avx(), "");
4003 if (VM_Version::supports_evex()) {
4004 tuple_type = EVEX_FV;
4005 input_size_in_bits = EVEX_32bit;
4006 }
4007 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector_len);
4008 }
4009
4010 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
4011 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4012 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4013 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66);
4014 } else {
4015 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, false, true);
4016 }
4017 }
4018
4019 void Assembler::andps(XMMRegister dst, XMMRegister src) {
4020 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4021 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE, false,
4022 (VM_Version::supports_avx512dq() == false));
4023 }
4024
4025 void Assembler::andps(XMMRegister dst, Address src) {
4026 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4027 if (VM_Version::supports_evex()) {
4028 tuple_type = EVEX_FV;
4029 input_size_in_bits = EVEX_32bit;
4030 }
4031 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE,
4032 false, (VM_Version::supports_avx512dq() == false));
4033 }
4034
4035 void Assembler::andpd(XMMRegister dst, Address src) {
4036 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4037 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4038 tuple_type = EVEX_FV;
4039 input_size_in_bits = EVEX_64bit;
4040 emit_simd_arith_q(0x54, dst, src, VEX_SIMD_66);
4041 } else {
4042 emit_simd_arith(0x54, dst, src, VEX_SIMD_66, false, true);
4043 }
4044 }
4045
4046 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4047 assert(VM_Version::supports_avx(), "");
4048 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4049 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len);
4050 } else {
4051 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, true);
4052 }
4053 }
4054
4055 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4056 assert(VM_Version::supports_avx(), "");
4057 bool legacy_mode = (VM_Version::supports_avx512dq() == false);
4058 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len, legacy_mode);
4059 }
4060
4061 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4062 assert(VM_Version::supports_avx(), "");
4063 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4064 tuple_type = EVEX_FV;
4065 input_size_in_bits = EVEX_64bit;
4066 emit_vex_arith_q(0x54, dst, nds, src, VEX_SIMD_66, vector_len);
4067 } else {
4068 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector_len, true);
4069 }
4070 }
4071
4072 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4073 assert(VM_Version::supports_avx(), "");
4074 if (VM_Version::supports_evex()) {
4075 tuple_type = EVEX_FV;
4076 input_size_in_bits = EVEX_32bit;
4077 }
4078 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector_len,
4079 (VM_Version::supports_avx512dq() == false));
4080 }
4081
4082 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4083 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4084 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4085 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
4086 } else {
4087 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, false, true);
4088 }
4089 }
4090
4091 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4092 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4093 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE,
4094 false, (VM_Version::supports_avx512dq() == false));
4095 }
4096
4097 void Assembler::xorpd(XMMRegister dst, Address src) {
4098 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4099 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4100 tuple_type = EVEX_FV;
4101 input_size_in_bits = EVEX_64bit;
4102 emit_simd_arith_q(0x57, dst, src, VEX_SIMD_66);
4103 } else {
4104 emit_simd_arith(0x57, dst, src, VEX_SIMD_66, false, true);
4105 }
4106 }
4107
4108 void Assembler::xorps(XMMRegister dst, Address src) {
4109 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4110 if (VM_Version::supports_evex()) {
4111 tuple_type = EVEX_FV;
4112 input_size_in_bits = EVEX_32bit;
4113 }
4114 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE, false,
4115 (VM_Version::supports_avx512dq() == false));
4116 }
4117
4118 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4119 assert(VM_Version::supports_avx(), "");
4120 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4121 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len);
4122 } else {
4123 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, true);
4124 }
4125 }
4126
4127 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4128 assert(VM_Version::supports_avx(), "");
4129 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len,
4130 (VM_Version::supports_avx512dq() == false));
4131 }
4132
4133 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4134 assert(VM_Version::supports_avx(), "");
4135 if (VM_Version::supports_evex() && VM_Version::supports_avx512dq()) {
4136 tuple_type = EVEX_FV;
4137 input_size_in_bits = EVEX_64bit;
4138 emit_vex_arith_q(0x57, dst, nds, src, VEX_SIMD_66, vector_len);
4139 } else {
4140 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector_len, true);
4141 }
4142 }
4143
4144 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4145 assert(VM_Version::supports_avx(), "");
4146 if (VM_Version::supports_evex()) {
4147 tuple_type = EVEX_FV;
4148 input_size_in_bits = EVEX_32bit;
4149 }
4150 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector_len,
4151 (VM_Version::supports_avx512dq() == false));
4152 }
4153
4154 // Integer vector arithmetic
4155 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4156 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4157 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4158 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len,
4159 VEX_OPCODE_0F_38, true, false);
4160 emit_int8(0x01);
4161 emit_int8((unsigned char)(0xC0 | encode));
4162 }
4163
4164 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4165 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4166 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4167 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len,
4168 VEX_OPCODE_0F_38, true, false);
4169 emit_int8(0x02);
4170 emit_int8((unsigned char)(0xC0 | encode));
4171 }
4172
4173 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
4174 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4175 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
4176 }
4177
4178 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
4179 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4180 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
4181 }
4182
4183 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
4184 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4185 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
4186 }
4187
4188 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
4189 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4190 if (VM_Version::supports_evex()) {
4191 emit_simd_arith_q(0xD4, dst, src, VEX_SIMD_66);
4192 } else {
4193 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
4194 }
4195 }
4196
4197 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
4198 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4199 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
4200 VEX_OPCODE_0F_38, false, AVX_128bit, true);
4201 emit_int8(0x01);
4202 emit_int8((unsigned char)(0xC0 | encode));
4203 }
4204
4205 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
4206 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4207 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
4208 VEX_OPCODE_0F_38, false, AVX_128bit, true);
4209 emit_int8(0x02);
4210 emit_int8((unsigned char)(0xC0 | encode));
4211 }
4212
4213 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4214 assert(UseAVX > 0, "requires some form of AVX");
4215 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len,
4216 (VM_Version::supports_avx512bw() == false));
4217 }
4218
4219 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4220 assert(UseAVX > 0, "requires some form of AVX");
4221 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len,
4222 (VM_Version::supports_avx512bw() == false));
4223 }
4224
4225 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4226 assert(UseAVX > 0, "requires some form of AVX");
4227 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len);
4228 }
4229
4230 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4231 assert(UseAVX > 0, "requires some form of AVX");
4232 if (VM_Version::supports_evex()) {
4233 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4234 } else {
4235 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4236 }
4237 }
4238
4239 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4240 assert(UseAVX > 0, "requires some form of AVX");
4241 if (VM_Version::supports_evex()) {
4242 tuple_type = EVEX_FVM;
4243 }
4244 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector_len);
4245 }
4246
4247 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4248 assert(UseAVX > 0, "requires some form of AVX");
4249 if (VM_Version::supports_evex()) {
4250 tuple_type = EVEX_FVM;
4251 }
4252 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector_len);
4253 }
4254
4255 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4256 assert(UseAVX > 0, "requires some form of AVX");
4257 if (VM_Version::supports_evex()) {
4258 tuple_type = EVEX_FV;
4259 input_size_in_bits = EVEX_32bit;
4260 }
4261 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector_len);
4262 }
4263
4264 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4265 assert(UseAVX > 0, "requires some form of AVX");
4266 if (VM_Version::supports_evex()) {
4267 tuple_type = EVEX_FV;
4268 input_size_in_bits = EVEX_64bit;
4269 emit_vex_arith_q(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4270 } else {
4271 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector_len);
4272 }
4273 }
4274
4275 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
4276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4277 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
4278 }
4279
4280 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
4281 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4282 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
4283 }
4284
4285 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
4286 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4287 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
4288 }
4289
4290 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
4291 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4292 if (VM_Version::supports_evex()) {
4293 emit_simd_arith_q(0xFB, dst, src, VEX_SIMD_66);
4294 } else {
4295 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
4296 }
4297 }
4298
4299 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4300 assert(UseAVX > 0, "requires some form of AVX");
4301 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len,
4302 (VM_Version::supports_avx512bw() == false));
4303 }
4304
4305 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4306 assert(UseAVX > 0, "requires some form of AVX");
4307 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len,
4308 (VM_Version::supports_avx512bw() == false));
4309 }
4310
4311 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4312 assert(UseAVX > 0, "requires some form of AVX");
4313 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len);
4314 }
4315
4316 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4317 assert(UseAVX > 0, "requires some form of AVX");
4318 if (VM_Version::supports_evex()) {
4319 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4320 } else {
4321 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4322 }
4323 }
4324
4325 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4326 assert(UseAVX > 0, "requires some form of AVX");
4327 if (VM_Version::supports_evex()) {
4328 tuple_type = EVEX_FVM;
4329 }
4330 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector_len,
4331 (VM_Version::supports_avx512bw() == false));
4332 }
4333
4334 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4335 assert(UseAVX > 0, "requires some form of AVX");
4336 if (VM_Version::supports_evex()) {
4337 tuple_type = EVEX_FVM;
4338 }
4339 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector_len,
4340 (VM_Version::supports_avx512bw() == false));
4341 }
4342
4343 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4344 assert(UseAVX > 0, "requires some form of AVX");
4345 if (VM_Version::supports_evex()) {
4346 tuple_type = EVEX_FV;
4347 input_size_in_bits = EVEX_32bit;
4348 }
4349 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector_len);
4350 }
4351
4352 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4353 assert(UseAVX > 0, "requires some form of AVX");
4354 if (VM_Version::supports_evex()) {
4355 tuple_type = EVEX_FV;
4356 input_size_in_bits = EVEX_64bit;
4357 emit_vex_arith_q(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4358 } else {
4359 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector_len);
4360 }
4361 }
4362
4363 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
4364 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4365 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66,
4366 (VM_Version::supports_avx512bw() == false));
4367 }
4368
4369 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
4370 assert(VM_Version::supports_sse4_1(), "");
4371 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66,
4372 false, VEX_OPCODE_0F_38);
4373 emit_int8(0x40);
4374 emit_int8((unsigned char)(0xC0 | encode));
4375 }
4376
4377 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4378 assert(UseAVX > 0, "requires some form of AVX");
4379 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len,
4380 (VM_Version::supports_avx512bw() == false));
4381 }
4382
4383 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4384 assert(UseAVX > 0, "requires some form of AVX");
4385 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66,
4386 vector_len, VEX_OPCODE_0F_38);
4387 emit_int8(0x40);
4388 emit_int8((unsigned char)(0xC0 | encode));
4389 }
4390
4391 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4392 assert(UseAVX > 2, "requires some form of AVX");
4393 int src_enc = src->encoding();
4394 int dst_enc = dst->encoding();
4395 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4396 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66,
4397 VEX_OPCODE_0F_38, true, vector_len, false, false);
4398 emit_int8(0x40);
4399 emit_int8((unsigned char)(0xC0 | encode));
4400 }
4401
4402 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4403 assert(UseAVX > 0, "requires some form of AVX");
4404 if (VM_Version::supports_evex()) {
4405 tuple_type = EVEX_FVM;
4406 }
4407 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector_len);
4408 }
4409
4410 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4411 assert(UseAVX > 0, "requires some form of AVX");
4412 if (VM_Version::supports_evex()) {
4413 tuple_type = EVEX_FV;
4414 input_size_in_bits = EVEX_32bit;
4415 }
4416 InstructionMark im(this);
4417 int dst_enc = dst->encoding();
4418 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4419 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66,
4420 VEX_OPCODE_0F_38, false, vector_len);
4421 emit_int8(0x40);
4422 emit_operand(dst, src);
4423 }
4424
4425 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4426 assert(UseAVX > 0, "requires some form of AVX");
4427 if (VM_Version::supports_evex()) {
4428 tuple_type = EVEX_FV;
4429 input_size_in_bits = EVEX_64bit;
4430 }
4431 InstructionMark im(this);
4432 int dst_enc = dst->encoding();
4433 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4434 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, true, vector_len);
4435 emit_int8(0x40);
4436 emit_operand(dst, src);
4437 }
4438
4439 // Shift packed integers left by specified number of bits.
4440 void Assembler::psllw(XMMRegister dst, int shift) {
4441 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4442 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4443 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4444 false, AVX_128bit, (VM_Version::supports_avx512bw() == false));
4445 emit_int8(0x71);
4446 emit_int8((unsigned char)(0xC0 | encode));
4447 emit_int8(shift & 0xFF);
4448 }
4449
4450 void Assembler::pslld(XMMRegister dst, int shift) {
4451 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4452 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4453 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false);
4454 emit_int8(0x72);
4455 emit_int8((unsigned char)(0xC0 | encode));
4456 emit_int8(shift & 0xFF);
4457 }
4458
4459 void Assembler::psllq(XMMRegister dst, int shift) {
4460 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4461 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4462 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, true);
4463 emit_int8(0x73);
4464 emit_int8((unsigned char)(0xC0 | encode));
4465 emit_int8(shift & 0xFF);
4466 }
4467
4468 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
4469 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4470 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66, false,
4471 (VM_Version::supports_avx512bw() == false));
4472 }
4473
4474 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
4475 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4476 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
4477 }
4478
4479 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
4480 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4481 if (VM_Version::supports_evex()) {
4482 emit_simd_arith_q(0xF3, dst, shift, VEX_SIMD_66);
4483 } else {
4484 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
4485 }
4486 }
4487
4488 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4489 assert(UseAVX > 0, "requires some form of AVX");
4490 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4491 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector_len,
4492 (VM_Version::supports_avx512bw() == false));
4493 emit_int8(shift & 0xFF);
4494 }
4495
4496 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4497 assert(UseAVX > 0, "requires some form of AVX");
4498 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4499 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector_len);
4500 emit_int8(shift & 0xFF);
4501 }
4502
4503 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4504 assert(UseAVX > 0, "requires some form of AVX");
4505 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4506 if (VM_Version::supports_evex()) {
4507 emit_vex_arith_q(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len);
4508 } else {
4509 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector_len);
4510 }
4511 emit_int8(shift & 0xFF);
4512 }
4513
4514 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4515 assert(UseAVX > 0, "requires some form of AVX");
4516 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector_len,
4517 (VM_Version::supports_avx512bw() == false));
4518 }
4519
4520 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4521 assert(UseAVX > 0, "requires some form of AVX");
4522 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector_len);
4523 }
4524
4525 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4526 assert(UseAVX > 0, "requires some form of AVX");
4527 if (VM_Version::supports_evex()) {
4528 emit_vex_arith_q(0xF3, dst, src, shift, VEX_SIMD_66, vector_len);
4529 } else {
4530 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector_len);
4531 }
4532 }
4533
4534 // Shift packed integers logically right by specified number of bits.
4535 void Assembler::psrlw(XMMRegister dst, int shift) {
4536 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4537 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
4538 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4539 (VM_Version::supports_avx512bw() == false));
4540 emit_int8(0x71);
4541 emit_int8((unsigned char)(0xC0 | encode));
4542 emit_int8(shift & 0xFF);
4543 }
4544
4545 void Assembler::psrld(XMMRegister dst, int shift) {
4546 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4547 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
4548 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false);
4549 emit_int8(0x72);
4550 emit_int8((unsigned char)(0xC0 | encode));
4551 emit_int8(shift & 0xFF);
4552 }
4553
4554 void Assembler::psrlq(XMMRegister dst, int shift) {
4555 // Do not confuse it with psrldq SSE2 instruction which
4556 // shifts 128 bit value in xmm register by number of bytes.
4557 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4558 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4559 int encode = 0;
4560 if (VM_Version::supports_evex() && VM_Version::supports_avx512bw()) {
4561 encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, true, VEX_OPCODE_0F, false);
4562 } else {
4563 encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F, true);
4564 }
4565 emit_int8(0x73);
4566 emit_int8((unsigned char)(0xC0 | encode));
4567 emit_int8(shift & 0xFF);
4568 }
4569
4570 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
4571 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4572 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66, false,
4573 (VM_Version::supports_avx512bw() == false));
4574 }
4575
4576 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
4577 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4578 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
4579 }
4580
4581 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
4582 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4583 if (VM_Version::supports_evex()) {
4584 emit_simd_arith_q(0xD3, dst, shift, VEX_SIMD_66);
4585 } else {
4586 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
4587 }
4588 }
4589
4590 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4591 assert(UseAVX > 0, "requires some form of AVX");
4592 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4593 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector_len,
4594 (VM_Version::supports_avx512bw() == false));
4595 emit_int8(shift & 0xFF);
4596 }
4597
4598 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4599 assert(UseAVX > 0, "requires some form of AVX");
4600 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4601 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector_len);
4602 emit_int8(shift & 0xFF);
4603 }
4604
4605 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4606 assert(UseAVX > 0, "requires some form of AVX");
4607 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4608 if (VM_Version::supports_evex()) {
4609 emit_vex_arith_q(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len);
4610 } else {
4611 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector_len);
4612 }
4613 emit_int8(shift & 0xFF);
4614 }
4615
4616 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4617 assert(UseAVX > 0, "requires some form of AVX");
4618 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector_len,
4619 (VM_Version::supports_avx512bw() == false));
4620 }
4621
4622 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4623 assert(UseAVX > 0, "requires some form of AVX");
4624 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector_len);
4625 }
4626
4627 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4628 assert(UseAVX > 0, "requires some form of AVX");
4629 if (VM_Version::supports_evex()) {
4630 emit_vex_arith_q(0xD3, dst, src, shift, VEX_SIMD_66, vector_len);
4631 } else {
4632 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector_len);
4633 }
4634 }
4635
4636 // Shift packed integers arithmetically right by specified number of bits.
4637 void Assembler::psraw(XMMRegister dst, int shift) {
4638 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4639 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4640 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, false, VEX_OPCODE_0F,
4641 (VM_Version::supports_avx512bw() == false));
4642 emit_int8(0x71);
4643 emit_int8((unsigned char)(0xC0 | encode));
4644 emit_int8(shift & 0xFF);
4645 }
4646
4647 void Assembler::psrad(XMMRegister dst, int shift) {
4648 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4649 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
4650 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, false);
4651 emit_int8(0x72);
4652 emit_int8((unsigned char)(0xC0 | encode));
4653 emit_int8(shift & 0xFF);
4654 }
4655
4656 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
4657 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4658 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66,
4659 (VM_Version::supports_avx512bw() == false));
4660 }
4661
4662 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
4663 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4664 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
4665 }
4666
4667 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4668 assert(UseAVX > 0, "requires some form of AVX");
4669 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4670 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector_len,
4671 (VM_Version::supports_avx512bw() == false));
4672 emit_int8(shift & 0xFF);
4673 }
4674
4675 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4676 assert(UseAVX > 0, "requires some form of AVX");
4677 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
4678 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector_len);
4679 emit_int8(shift & 0xFF);
4680 }
4681
4682 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4683 assert(UseAVX > 0, "requires some form of AVX");
4684 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector_len,
4685 (VM_Version::supports_avx512bw() == false));
4686 }
4687
4688 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4689 assert(UseAVX > 0, "requires some form of AVX");
4690 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector_len);
4691 }
4692
4693
4694 // AND packed integers
4695 void Assembler::pand(XMMRegister dst, XMMRegister src) {
4696 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4697 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
4698 }
4699
4700 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4701 assert(UseAVX > 0, "requires some form of AVX");
4702 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
4703 }
4704
4705 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4706 assert(UseAVX > 0, "requires some form of AVX");
4707 if (VM_Version::supports_evex()) {
4708 tuple_type = EVEX_FV;
4709 input_size_in_bits = EVEX_32bit;
4710 }
4711 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector_len);
4712 }
4713
4714 void Assembler::por(XMMRegister dst, XMMRegister src) {
4715 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4716 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
4717 }
4718
4719 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4720 assert(UseAVX > 0, "requires some form of AVX");
4721 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len);
4722 }
4723
4724 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4725 assert(UseAVX > 0, "requires some form of AVX");
4726 if (VM_Version::supports_evex()) {
4727 tuple_type = EVEX_FV;
4728 input_size_in_bits = EVEX_32bit;
4729 }
4730 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector_len);
4731 }
4732
4733 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
4734 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4735 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
4736 }
4737
4738 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4739 assert(UseAVX > 0, "requires some form of AVX");
4740 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len);
4741 }
4742
4743 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4744 assert(UseAVX > 0, "requires some form of AVX");
4745 if (VM_Version::supports_evex()) {
4746 tuple_type = EVEX_FV;
4747 input_size_in_bits = EVEX_32bit;
4748 }
4749 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector_len);
4750 }
4751
4752
4753 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4754 assert(VM_Version::supports_avx(), "");
4755 int vector_len = AVX_256bit;
4756 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4757 emit_int8(0x18);
4758 emit_int8((unsigned char)(0xC0 | encode));
4759 // 0x00 - insert into lower 128 bits
4760 // 0x01 - insert into upper 128 bits
4761 emit_int8(0x01);
4762 }
4763
4764 void Assembler::vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4765 assert(VM_Version::supports_evex(), "");
4766 int vector_len = AVX_512bit;
4767 int src_enc = src->encoding();
4768 int dst_enc = dst->encoding();
4769 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4770 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66,
4771 VEX_OPCODE_0F_3A, true, vector_len, false, false);
4772 emit_int8(0x1A);
4773 emit_int8((unsigned char)(0xC0 | encode));
4774 // 0x00 - insert into lower 256 bits
4775 // 0x01 - insert into upper 256 bits
4776 emit_int8(0x01);
4777 }
4778
4779 void Assembler::vinsertf64x4h(XMMRegister dst, Address src) {
4780 assert(VM_Version::supports_avx(), "");
4781 if (VM_Version::supports_evex()) {
4782 tuple_type = EVEX_T4;
4783 input_size_in_bits = EVEX_64bit;
4784 }
4785 InstructionMark im(this);
4786 int vector_len = AVX_512bit;
4787 assert(dst != xnoreg, "sanity");
4788 int dst_enc = dst->encoding();
4789 // swap src<->dst for encoding
4790 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector_len);
4791 emit_int8(0x1A);
4792 emit_operand(dst, src);
4793 // 0x01 - insert into upper 128 bits
4794 emit_int8(0x01);
4795 }
4796
4797 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
4798 assert(VM_Version::supports_avx(), "");
4799 if (VM_Version::supports_evex()) {
4800 tuple_type = EVEX_T4;
4801 input_size_in_bits = EVEX_32bit;
4802 }
4803 InstructionMark im(this);
4804 int vector_len = AVX_256bit;
4805 assert(dst != xnoreg, "sanity");
4806 int dst_enc = dst->encoding();
4807 // swap src<->dst for encoding
4808 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4809 emit_int8(0x18);
4810 emit_operand(dst, src);
4811 // 0x01 - insert into upper 128 bits
4812 emit_int8(0x01);
4813 }
4814
4815 void Assembler::vextractf128h(XMMRegister dst, XMMRegister src) {
4816 assert(VM_Version::supports_avx(), "");
4817 int vector_len = AVX_256bit;
4818 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4819 emit_int8(0x19);
4820 emit_int8((unsigned char)(0xC0 | encode));
4821 // 0x00 - insert into lower 128 bits
4822 // 0x01 - insert into upper 128 bits
4823 emit_int8(0x01);
4824 }
4825
4826 void Assembler::vextractf128h(Address dst, XMMRegister src) {
4827 assert(VM_Version::supports_avx(), "");
4828 if (VM_Version::supports_evex()) {
4829 tuple_type = EVEX_T4;
4830 input_size_in_bits = EVEX_32bit;
4831 }
4832 InstructionMark im(this);
4833 int vector_len = AVX_256bit;
4834 assert(src != xnoreg, "sanity");
4835 int src_enc = src->encoding();
4836 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4837 emit_int8(0x19);
4838 emit_operand(src, dst);
4839 // 0x01 - extract from upper 128 bits
4840 emit_int8(0x01);
4841 }
4842
4843 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4844 assert(VM_Version::supports_avx2(), "");
4845 int vector_len = AVX_256bit;
4846 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4847 emit_int8(0x38);
4848 emit_int8((unsigned char)(0xC0 | encode));
4849 // 0x00 - insert into lower 128 bits
4850 // 0x01 - insert into upper 128 bits
4851 emit_int8(0x01);
4852 }
4853
4854 void Assembler::vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4855 assert(VM_Version::supports_evex(), "");
4856 int vector_len = AVX_512bit;
4857 int src_enc = src->encoding();
4858 int dst_enc = dst->encoding();
4859 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4860 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4861 VM_Version::supports_avx512dq(), vector_len, false, false);
4862 emit_int8(0x38);
4863 emit_int8((unsigned char)(0xC0 | encode));
4864 // 0x00 - insert into lower 256 bits
4865 // 0x01 - insert into upper 256 bits
4866 emit_int8(0x01);
4867 }
4868
4869 void Assembler::vinserti128h(XMMRegister dst, Address src) {
4870 assert(VM_Version::supports_avx2(), "");
4871 if (VM_Version::supports_evex()) {
4872 tuple_type = EVEX_T4;
4873 input_size_in_bits = EVEX_32bit;
4874 }
4875 InstructionMark im(this);
4876 int vector_len = AVX_256bit;
4877 assert(dst != xnoreg, "sanity");
4878 int dst_enc = dst->encoding();
4879 // swap src<->dst for encoding
4880 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4881 emit_int8(0x38);
4882 emit_operand(dst, src);
4883 // 0x01 - insert into upper 128 bits
4884 emit_int8(0x01);
4885 }
4886
4887 void Assembler::vextracti128h(XMMRegister dst, XMMRegister src) {
4888 assert(VM_Version::supports_avx(), "");
4889 int vector_len = AVX_256bit;
4890 int encode = vex_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A);
4891 emit_int8(0x39);
4892 emit_int8((unsigned char)(0xC0 | encode));
4893 // 0x00 - insert into lower 128 bits
4894 // 0x01 - insert into upper 128 bits
4895 emit_int8(0x01);
4896 }
4897
4898 void Assembler::vextracti128h(Address dst, XMMRegister src) {
4899 assert(VM_Version::supports_avx2(), "");
4900 if (VM_Version::supports_evex()) {
4901 tuple_type = EVEX_T4;
4902 input_size_in_bits = EVEX_32bit;
4903 }
4904 InstructionMark im(this);
4905 int vector_len = AVX_256bit;
4906 assert(src != xnoreg, "sanity");
4907 int src_enc = src->encoding();
4908 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector_len);
4909 emit_int8(0x39);
4910 emit_operand(src, dst);
4911 // 0x01 - extract from upper 128 bits
4912 emit_int8(0x01);
4913 }
4914
4915 void Assembler::vextracti64x4h(XMMRegister dst, XMMRegister src) {
4916 assert(VM_Version::supports_evex(), "");
4917 int vector_len = AVX_512bit;
4918 int src_enc = src->encoding();
4919 int dst_enc = dst->encoding();
4920 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4921 true, vector_len, false, false);
4922 emit_int8(0x3B);
4923 emit_int8((unsigned char)(0xC0 | encode));
4924 // 0x01 - extract from upper 256 bits
4925 emit_int8(0x01);
4926 }
4927
4928 void Assembler::vextracti64x2h(XMMRegister dst, XMMRegister src, int value) {
4929 assert(VM_Version::supports_evex(), "");
4930 int vector_len = AVX_512bit;
4931 int src_enc = src->encoding();
4932 int dst_enc = dst->encoding();
4933 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4934 VM_Version::supports_avx512dq(), vector_len, false, false);
4935 emit_int8(0x39);
4936 emit_int8((unsigned char)(0xC0 | encode));
4937 // 0x01 - extract from bits 255:128
4938 // 0x02 - extract from bits 383:256
4939 // 0x03 - extract from bits 511:384
4940 emit_int8(value & 0x3);
4941 }
4942
4943 void Assembler::vextractf64x4h(XMMRegister dst, XMMRegister src) {
4944 assert(VM_Version::supports_evex(), "");
4945 int vector_len = AVX_512bit;
4946 int src_enc = src->encoding();
4947 int dst_enc = dst->encoding();
4948 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4949 VM_Version::supports_avx512dq(), vector_len, false, false);
4950 emit_int8(0x1B);
4951 emit_int8((unsigned char)(0xC0 | encode));
4952 // 0x01 - extract from upper 256 bits
4953 emit_int8(0x01);
4954 }
4955
4956 void Assembler::vextractf64x4h(Address dst, XMMRegister src) {
4957 assert(VM_Version::supports_avx2(), "");
4958 tuple_type = EVEX_T4;
4959 input_size_in_bits = EVEX_64bit;
4960 InstructionMark im(this);
4961 int vector_len = AVX_512bit;
4962 assert(src != xnoreg, "sanity");
4963 int src_enc = src->encoding();
4964 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4965 VM_Version::supports_avx512dq(), vector_len);
4966 emit_int8(0x1B);
4967 emit_operand(src, dst);
4968 // 0x01 - extract from upper 128 bits
4969 emit_int8(0x01);
4970 }
4971
4972 void Assembler::vextractf32x4h(XMMRegister dst, XMMRegister src, int value) {
4973 assert(VM_Version::supports_evex(), "");
4974 int vector_len = AVX_512bit;
4975 int src_enc = src->encoding();
4976 int dst_enc = dst->encoding();
4977 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66,
4978 VEX_OPCODE_0F_3A, false, vector_len, false, false);
4979 emit_int8(0x19);
4980 emit_int8((unsigned char)(0xC0 | encode));
4981 // 0x01 - extract from bits 255:128
4982 // 0x02 - extract from bits 383:256
4983 // 0x03 - extract from bits 511:384
4984 emit_int8(value & 0x3);
4985 }
4986
4987 void Assembler::vextractf64x2h(XMMRegister dst, XMMRegister src, int value) {
4988 assert(VM_Version::supports_evex(), "");
4989 int vector_len = AVX_512bit;
4990 int src_enc = src->encoding();
4991 int dst_enc = dst->encoding();
4992 int encode = vex_prefix_and_encode(src_enc, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A,
4993 VM_Version::supports_avx512dq(), vector_len, false, false);
4994 emit_int8(0x19);
4995 emit_int8((unsigned char)(0xC0 | encode));
4996 // 0x01 - extract from bits 255:128
4997 // 0x02 - extract from bits 383:256
4998 // 0x03 - extract from bits 511:384
4999 emit_int8(value & 0x3);
5000 }
5001
5002 // duplicate 4-bytes integer data from src into 8 locations in dest
5003 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
5004 assert(VM_Version::supports_avx2(), "");
5005 int vector_len = AVX_256bit;
5006 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
5007 vector_len, VEX_OPCODE_0F_38, false);
5008 emit_int8(0x58);
5009 emit_int8((unsigned char)(0xC0 | encode));
5010 }
5011
5012 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5013 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
5014 assert(VM_Version::supports_evex(), "");
5015 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
5016 vector_len, VEX_OPCODE_0F_38, false);
5017 emit_int8(0x78);
5018 emit_int8((unsigned char)(0xC0 | encode));
5019 }
5020
5021 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
5022 assert(VM_Version::supports_evex(), "");
5023 tuple_type = EVEX_T1S;
5024 input_size_in_bits = EVEX_8bit;
5025 InstructionMark im(this);
5026 assert(dst != xnoreg, "sanity");
5027 int dst_enc = dst->encoding();
5028 // swap src<->dst for encoding
5029 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
5030 emit_int8(0x78);
5031 emit_operand(dst, src);
5032 }
5033
5034 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5035 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
5036 assert(VM_Version::supports_evex(), "");
5037 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
5038 vector_len, VEX_OPCODE_0F_38, false);
5039 emit_int8(0x79);
5040 emit_int8((unsigned char)(0xC0 | encode));
5041 }
5042
5043 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
5044 assert(VM_Version::supports_evex(), "");
5045 tuple_type = EVEX_T1S;
5046 input_size_in_bits = EVEX_16bit;
5047 InstructionMark im(this);
5048 assert(dst != xnoreg, "sanity");
5049 int dst_enc = dst->encoding();
5050 // swap src<->dst for encoding
5051 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
5052 emit_int8(0x79);
5053 emit_operand(dst, src);
5054 }
5055
5056 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5057 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
5058 assert(VM_Version::supports_evex(), "");
5059 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66,
5060 vector_len, VEX_OPCODE_0F_38, false);
5061 emit_int8(0x58);
5062 emit_int8((unsigned char)(0xC0 | encode));
5063 }
5064
5065 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
5066 assert(VM_Version::supports_evex(), "");
5067 tuple_type = EVEX_T1S;
5068 input_size_in_bits = EVEX_32bit;
5069 InstructionMark im(this);
5070 assert(dst != xnoreg, "sanity");
5071 int dst_enc = dst->encoding();
5072 // swap src<->dst for encoding
5073 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
5074 emit_int8(0x58);
5075 emit_operand(dst, src);
5076 }
5077
5078 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5079 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
5080 assert(VM_Version::supports_evex(), "");
5081 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5082 VEX_OPCODE_0F_38, true, vector_len, false, false);
5083 emit_int8(0x59);
5084 emit_int8((unsigned char)(0xC0 | encode));
5085 }
5086
5087 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
5088 assert(VM_Version::supports_evex(), "");
5089 tuple_type = EVEX_T1S;
5090 input_size_in_bits = EVEX_64bit;
5091 InstructionMark im(this);
5092 assert(dst != xnoreg, "sanity");
5093 int dst_enc = dst->encoding();
5094 // swap src<->dst for encoding
5095 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, true, vector_len);
5096 emit_int8(0x59);
5097 emit_operand(dst, src);
5098 }
5099
5100 // duplicate single precision fp from src into 4|8|16 locations in dest : requires AVX512VL
5101 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
5102 assert(VM_Version::supports_evex(), "");
5103 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5104 VEX_OPCODE_0F_38, false, vector_len, false, false);
5105 emit_int8(0x18);
5106 emit_int8((unsigned char)(0xC0 | encode));
5107 }
5108
5109 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
5110 assert(VM_Version::supports_evex(), "");
5111 tuple_type = EVEX_T1S;
5112 input_size_in_bits = EVEX_32bit;
5113 InstructionMark im(this);
5114 assert(dst != xnoreg, "sanity");
5115 int dst_enc = dst->encoding();
5116 // swap src<->dst for encoding
5117 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector_len);
5118 emit_int8(0x18);
5119 emit_operand(dst, src);
5120 }
5121
5122 // duplicate double precision fp from src into 2|4|8 locations in dest : requires AVX512VL
5123 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
5124 assert(VM_Version::supports_evex(), "");
5125 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5126 VEX_OPCODE_0F_38, true, vector_len, false, false);
5127 emit_int8(0x19);
5128 emit_int8((unsigned char)(0xC0 | encode));
5129 }
5130
5131 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
5132 assert(VM_Version::supports_evex(), "");
5133 tuple_type = EVEX_T1S;
5134 input_size_in_bits = EVEX_64bit;
5135 InstructionMark im(this);
5136 assert(dst != xnoreg, "sanity");
5137 int dst_enc = dst->encoding();
5138 // swap src<->dst for encoding
5139 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, true, vector_len);
5140 emit_int8(0x19);
5141 emit_operand(dst, src);
5142 }
5143
5144 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5145 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
5146 assert(VM_Version::supports_evex(), "");
5147 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5148 VEX_OPCODE_0F_38, false, vector_len, false, false);
5149 emit_int8(0x7A);
5150 emit_int8((unsigned char)(0xC0 | encode));
5151 }
5152
5153 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5154 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
5155 assert(VM_Version::supports_evex(), "");
5156 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5157 VEX_OPCODE_0F_38, false, vector_len, false, false);
5158 emit_int8(0x7B);
5159 emit_int8((unsigned char)(0xC0 | encode));
5160 }
5161
5162 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5163 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
5164 assert(VM_Version::supports_evex(), "");
5165 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5166 VEX_OPCODE_0F_38, false, vector_len, false, false);
5167 emit_int8(0x7C);
5168 emit_int8((unsigned char)(0xC0 | encode));
5169 }
5170
5171 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5172 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
5173 assert(VM_Version::supports_evex(), "");
5174 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66,
5175 VEX_OPCODE_0F_38, true, vector_len, false, false);
5176 emit_int8(0x7C);
5177 emit_int8((unsigned char)(0xC0 | encode));
5178 }
5179
5180 // Carry-Less Multiplication Quadword
5181 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
5182 assert(VM_Version::supports_clmul(), "");
5183 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, false,
5184 VEX_OPCODE_0F_3A, false, AVX_128bit, true);
5185 emit_int8(0x44);
5186 emit_int8((unsigned char)(0xC0 | encode));
5187 emit_int8((unsigned char)mask);
5188 }
5189
5190 // Carry-Less Multiplication Quadword
5191 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
5192 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
5193 int vector_len = AVX_128bit;
5194 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66,
5195 vector_len, VEX_OPCODE_0F_3A, true);
5196 emit_int8(0x44);
5197 emit_int8((unsigned char)(0xC0 | encode));
5198 emit_int8((unsigned char)mask);
5199 }
5200
5201 void Assembler::vzeroupper() {
5202 assert(VM_Version::supports_avx(), "");
5203 if (UseAVX < 3)
5204 {
5205 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
5206 emit_int8(0x77);
5207 }
5208 }
5209
5210
5211 #ifndef _LP64
5212 // 32bit only pieces of the assembler
5213
5214 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5215 // NO PREFIX AS NEVER 64BIT
5216 InstructionMark im(this);
5217 emit_int8((unsigned char)0x81);
5218 emit_int8((unsigned char)(0xF8 | src1->encoding()));
5219 emit_data(imm32, rspec, 0);
5220 }
5221
5222 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5223 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
5224 InstructionMark im(this);
5225 emit_int8((unsigned char)0x81);
5226 emit_operand(rdi, src1);
5227 emit_data(imm32, rspec, 0);
5228 }
5229
5230 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
5231 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
5232 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
5233 void Assembler::cmpxchg8(Address adr) {
5234 InstructionMark im(this);
5235 emit_int8(0x0F);
5236 emit_int8((unsigned char)0xC7);
5237 emit_operand(rcx, adr);
5238 }
5239
5240 void Assembler::decl(Register dst) {
5241 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5242 emit_int8(0x48 | dst->encoding());
5243 }
5244
5245 #endif // _LP64
5246
5247 // 64bit typically doesn't use the x87 but needs to for the trig funcs
5248
5249 void Assembler::fabs() {
5250 emit_int8((unsigned char)0xD9);
5251 emit_int8((unsigned char)0xE1);
5252 }
5253
5254 void Assembler::fadd(int i) {
5255 emit_farith(0xD8, 0xC0, i);
5256 }
5257
5258 void Assembler::fadd_d(Address src) {
5259 InstructionMark im(this);
5260 emit_int8((unsigned char)0xDC);
5261 emit_operand32(rax, src);
5262 }
5263
5264 void Assembler::fadd_s(Address src) {
5265 InstructionMark im(this);
5266 emit_int8((unsigned char)0xD8);
5267 emit_operand32(rax, src);
5268 }
5269
5270 void Assembler::fadda(int i) {
5271 emit_farith(0xDC, 0xC0, i);
5272 }
5273
5274 void Assembler::faddp(int i) {
5275 emit_farith(0xDE, 0xC0, i);
5276 }
5277
5278 void Assembler::fchs() {
5279 emit_int8((unsigned char)0xD9);
5280 emit_int8((unsigned char)0xE0);
5281 }
5282
5283 void Assembler::fcom(int i) {
5284 emit_farith(0xD8, 0xD0, i);
5285 }
5286
5287 void Assembler::fcomp(int i) {
5288 emit_farith(0xD8, 0xD8, i);
5289 }
5290
5291 void Assembler::fcomp_d(Address src) {
5292 InstructionMark im(this);
5293 emit_int8((unsigned char)0xDC);
5294 emit_operand32(rbx, src);
5295 }
5296
5297 void Assembler::fcomp_s(Address src) {
5298 InstructionMark im(this);
5299 emit_int8((unsigned char)0xD8);
5300 emit_operand32(rbx, src);
5301 }
5302
5303 void Assembler::fcompp() {
5304 emit_int8((unsigned char)0xDE);
5305 emit_int8((unsigned char)0xD9);
5306 }
5307
5308 void Assembler::fcos() {
5309 emit_int8((unsigned char)0xD9);
5310 emit_int8((unsigned char)0xFF);
5311 }
5312
5313 void Assembler::fdecstp() {
5314 emit_int8((unsigned char)0xD9);
5315 emit_int8((unsigned char)0xF6);
5316 }
5317
5318 void Assembler::fdiv(int i) {
5319 emit_farith(0xD8, 0xF0, i);
5320 }
5321
5322 void Assembler::fdiv_d(Address src) {
5323 InstructionMark im(this);
5324 emit_int8((unsigned char)0xDC);
5325 emit_operand32(rsi, src);
5326 }
5327
5328 void Assembler::fdiv_s(Address src) {
5329 InstructionMark im(this);
5330 emit_int8((unsigned char)0xD8);
5331 emit_operand32(rsi, src);
5332 }
5333
5334 void Assembler::fdiva(int i) {
5335 emit_farith(0xDC, 0xF8, i);
5336 }
5337
5338 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
5339 // is erroneous for some of the floating-point instructions below.
5340
5341 void Assembler::fdivp(int i) {
5342 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
5343 }
5344
5345 void Assembler::fdivr(int i) {
5346 emit_farith(0xD8, 0xF8, i);
5347 }
5348
5349 void Assembler::fdivr_d(Address src) {
5350 InstructionMark im(this);
5351 emit_int8((unsigned char)0xDC);
5352 emit_operand32(rdi, src);
5353 }
5354
5355 void Assembler::fdivr_s(Address src) {
5356 InstructionMark im(this);
5357 emit_int8((unsigned char)0xD8);
5358 emit_operand32(rdi, src);
5359 }
5360
5361 void Assembler::fdivra(int i) {
5362 emit_farith(0xDC, 0xF0, i);
5363 }
5364
5365 void Assembler::fdivrp(int i) {
5366 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
5367 }
5368
5369 void Assembler::ffree(int i) {
5370 emit_farith(0xDD, 0xC0, i);
5371 }
5372
5373 void Assembler::fild_d(Address adr) {
5374 InstructionMark im(this);
5375 emit_int8((unsigned char)0xDF);
5376 emit_operand32(rbp, adr);
5377 }
5378
5379 void Assembler::fild_s(Address adr) {
5380 InstructionMark im(this);
5381 emit_int8((unsigned char)0xDB);
5382 emit_operand32(rax, adr);
5383 }
5384
5385 void Assembler::fincstp() {
5386 emit_int8((unsigned char)0xD9);
5387 emit_int8((unsigned char)0xF7);
5388 }
5389
5390 void Assembler::finit() {
5391 emit_int8((unsigned char)0x9B);
5392 emit_int8((unsigned char)0xDB);
5393 emit_int8((unsigned char)0xE3);
5394 }
5395
5396 void Assembler::fist_s(Address adr) {
5397 InstructionMark im(this);
5398 emit_int8((unsigned char)0xDB);
5399 emit_operand32(rdx, adr);
5400 }
5401
5402 void Assembler::fistp_d(Address adr) {
5403 InstructionMark im(this);
5404 emit_int8((unsigned char)0xDF);
5405 emit_operand32(rdi, adr);
5406 }
5407
5408 void Assembler::fistp_s(Address adr) {
5409 InstructionMark im(this);
5410 emit_int8((unsigned char)0xDB);
5411 emit_operand32(rbx, adr);
5412 }
5413
5414 void Assembler::fld1() {
5415 emit_int8((unsigned char)0xD9);
5416 emit_int8((unsigned char)0xE8);
5417 }
5418
5419 void Assembler::fld_d(Address adr) {
5420 InstructionMark im(this);
5421 emit_int8((unsigned char)0xDD);
5422 emit_operand32(rax, adr);
5423 }
5424
5425 void Assembler::fld_s(Address adr) {
5426 InstructionMark im(this);
5427 emit_int8((unsigned char)0xD9);
5428 emit_operand32(rax, adr);
5429 }
5430
5431
5432 void Assembler::fld_s(int index) {
5433 emit_farith(0xD9, 0xC0, index);
5434 }
5435
5436 void Assembler::fld_x(Address adr) {
5437 InstructionMark im(this);
5438 emit_int8((unsigned char)0xDB);
5439 emit_operand32(rbp, adr);
5440 }
5441
5442 void Assembler::fldcw(Address src) {
5443 InstructionMark im(this);
5444 emit_int8((unsigned char)0xD9);
5445 emit_operand32(rbp, src);
5446 }
5447
5448 void Assembler::fldenv(Address src) {
5449 InstructionMark im(this);
5450 emit_int8((unsigned char)0xD9);
5451 emit_operand32(rsp, src);
5452 }
5453
5454 void Assembler::fldlg2() {
5455 emit_int8((unsigned char)0xD9);
5456 emit_int8((unsigned char)0xEC);
5457 }
5458
5459 void Assembler::fldln2() {
5460 emit_int8((unsigned char)0xD9);
5461 emit_int8((unsigned char)0xED);
5462 }
5463
5464 void Assembler::fldz() {
5465 emit_int8((unsigned char)0xD9);
5466 emit_int8((unsigned char)0xEE);
5467 }
5468
5469 void Assembler::flog() {
5470 fldln2();
5471 fxch();
5472 fyl2x();
5473 }
5474
5475 void Assembler::flog10() {
5476 fldlg2();
5477 fxch();
5478 fyl2x();
5479 }
5480
5481 void Assembler::fmul(int i) {
5482 emit_farith(0xD8, 0xC8, i);
5483 }
5484
5485 void Assembler::fmul_d(Address src) {
5486 InstructionMark im(this);
5487 emit_int8((unsigned char)0xDC);
5488 emit_operand32(rcx, src);
5489 }
5490
5491 void Assembler::fmul_s(Address src) {
5492 InstructionMark im(this);
5493 emit_int8((unsigned char)0xD8);
5494 emit_operand32(rcx, src);
5495 }
5496
5497 void Assembler::fmula(int i) {
5498 emit_farith(0xDC, 0xC8, i);
5499 }
5500
5501 void Assembler::fmulp(int i) {
5502 emit_farith(0xDE, 0xC8, i);
5503 }
5504
5505 void Assembler::fnsave(Address dst) {
5506 InstructionMark im(this);
5507 emit_int8((unsigned char)0xDD);
5508 emit_operand32(rsi, dst);
5509 }
5510
5511 void Assembler::fnstcw(Address src) {
5512 InstructionMark im(this);
5513 emit_int8((unsigned char)0x9B);
5514 emit_int8((unsigned char)0xD9);
5515 emit_operand32(rdi, src);
5516 }
5517
5518 void Assembler::fnstsw_ax() {
5519 emit_int8((unsigned char)0xDF);
5520 emit_int8((unsigned char)0xE0);
5521 }
5522
5523 void Assembler::fprem() {
5524 emit_int8((unsigned char)0xD9);
5525 emit_int8((unsigned char)0xF8);
5526 }
5527
5528 void Assembler::fprem1() {
5529 emit_int8((unsigned char)0xD9);
5530 emit_int8((unsigned char)0xF5);
5531 }
5532
5533 void Assembler::frstor(Address src) {
5534 InstructionMark im(this);
5535 emit_int8((unsigned char)0xDD);
5536 emit_operand32(rsp, src);
5537 }
5538
5539 void Assembler::fsin() {
5540 emit_int8((unsigned char)0xD9);
5541 emit_int8((unsigned char)0xFE);
5542 }
5543
5544 void Assembler::fsqrt() {
5545 emit_int8((unsigned char)0xD9);
5546 emit_int8((unsigned char)0xFA);
5547 }
5548
5549 void Assembler::fst_d(Address adr) {
5550 InstructionMark im(this);
5551 emit_int8((unsigned char)0xDD);
5552 emit_operand32(rdx, adr);
5553 }
5554
5555 void Assembler::fst_s(Address adr) {
5556 InstructionMark im(this);
5557 emit_int8((unsigned char)0xD9);
5558 emit_operand32(rdx, adr);
5559 }
5560
5561 void Assembler::fstp_d(Address adr) {
5562 InstructionMark im(this);
5563 emit_int8((unsigned char)0xDD);
5564 emit_operand32(rbx, adr);
5565 }
5566
5567 void Assembler::fstp_d(int index) {
5568 emit_farith(0xDD, 0xD8, index);
5569 }
5570
5571 void Assembler::fstp_s(Address adr) {
5572 InstructionMark im(this);
5573 emit_int8((unsigned char)0xD9);
5574 emit_operand32(rbx, adr);
5575 }
5576
5577 void Assembler::fstp_x(Address adr) {
5578 InstructionMark im(this);
5579 emit_int8((unsigned char)0xDB);
5580 emit_operand32(rdi, adr);
5581 }
5582
5583 void Assembler::fsub(int i) {
5584 emit_farith(0xD8, 0xE0, i);
5585 }
5586
5587 void Assembler::fsub_d(Address src) {
5588 InstructionMark im(this);
5589 emit_int8((unsigned char)0xDC);
5590 emit_operand32(rsp, src);
5591 }
5592
5593 void Assembler::fsub_s(Address src) {
5594 InstructionMark im(this);
5595 emit_int8((unsigned char)0xD8);
5596 emit_operand32(rsp, src);
5597 }
5598
5599 void Assembler::fsuba(int i) {
5600 emit_farith(0xDC, 0xE8, i);
5601 }
5602
5603 void Assembler::fsubp(int i) {
5604 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
5605 }
5606
5607 void Assembler::fsubr(int i) {
5608 emit_farith(0xD8, 0xE8, i);
5609 }
5610
5611 void Assembler::fsubr_d(Address src) {
5612 InstructionMark im(this);
5613 emit_int8((unsigned char)0xDC);
5614 emit_operand32(rbp, src);
5615 }
5616
5617 void Assembler::fsubr_s(Address src) {
5618 InstructionMark im(this);
5619 emit_int8((unsigned char)0xD8);
5620 emit_operand32(rbp, src);
5621 }
5622
5623 void Assembler::fsubra(int i) {
5624 emit_farith(0xDC, 0xE0, i);
5625 }
5626
5627 void Assembler::fsubrp(int i) {
5628 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
5629 }
5630
5631 void Assembler::ftan() {
5632 emit_int8((unsigned char)0xD9);
5633 emit_int8((unsigned char)0xF2);
5634 emit_int8((unsigned char)0xDD);
5635 emit_int8((unsigned char)0xD8);
5636 }
5637
5638 void Assembler::ftst() {
5639 emit_int8((unsigned char)0xD9);
5640 emit_int8((unsigned char)0xE4);
5641 }
5642
5643 void Assembler::fucomi(int i) {
5644 // make sure the instruction is supported (introduced for P6, together with cmov)
5645 guarantee(VM_Version::supports_cmov(), "illegal instruction");
5646 emit_farith(0xDB, 0xE8, i);
5647 }
5648
5649 void Assembler::fucomip(int i) {
5650 // make sure the instruction is supported (introduced for P6, together with cmov)
5651 guarantee(VM_Version::supports_cmov(), "illegal instruction");
5652 emit_farith(0xDF, 0xE8, i);
5653 }
5654
5655 void Assembler::fwait() {
5656 emit_int8((unsigned char)0x9B);
5657 }
5658
5659 void Assembler::fxch(int i) {
5660 emit_farith(0xD9, 0xC8, i);
5661 }
5662
5663 void Assembler::fyl2x() {
5664 emit_int8((unsigned char)0xD9);
5665 emit_int8((unsigned char)0xF1);
5666 }
5667
5668 void Assembler::frndint() {
5669 emit_int8((unsigned char)0xD9);
5670 emit_int8((unsigned char)0xFC);
5671 }
5672
5673 void Assembler::f2xm1() {
5674 emit_int8((unsigned char)0xD9);
5675 emit_int8((unsigned char)0xF0);
5676 }
5677
5678 void Assembler::fldl2e() {
5679 emit_int8((unsigned char)0xD9);
5680 emit_int8((unsigned char)0xEA);
5681 }
5682
5683 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
5684 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
5685 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
5686 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
5687
5688 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
5689 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
5690 if (pre > 0) {
5691 emit_int8(simd_pre[pre]);
5692 }
5693 if (rex_w) {
5694 prefixq(adr, xreg);
5695 } else {
5696 prefix(adr, xreg);
5697 }
5698 if (opc > 0) {
5699 emit_int8(0x0F);
5700 int opc2 = simd_opc[opc];
5701 if (opc2 > 0) {
5702 emit_int8(opc2);
5703 }
5704 }
5705 }
5706
5707 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
5708 if (pre > 0) {
5709 emit_int8(simd_pre[pre]);
5710 }
5711 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
5712 prefix_and_encode(dst_enc, src_enc);
5713 if (opc > 0) {
5714 emit_int8(0x0F);
5715 int opc2 = simd_opc[opc];
5716 if (opc2 > 0) {
5717 emit_int8(opc2);
5718 }
5719 }
5720 return encode;
5721 }
5722
5723
5724 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, int vector_len) {
5725 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
5726 prefix(VEX_3bytes);
5727
5728 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
5729 byte1 = (~byte1) & 0xE0;
5730 byte1 |= opc;
5731 emit_int8(byte1);
5732
5733 int byte2 = ((~nds_enc) & 0xf) << 3;
5734 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
5735 emit_int8(byte2);
5736 } else {
5737 prefix(VEX_2bytes);
5738
5739 int byte1 = vex_r ? VEX_R : 0;
5740 byte1 = (~byte1) & 0x80;
5741 byte1 |= ((~nds_enc) & 0xf) << 3;
5742 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
5743 emit_int8(byte1);
5744 }
5745 }
5746
5747 // This is a 4 byte encoding
5748 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, bool evex_r, bool evex_v,
5749 int nds_enc, VexSimdPrefix pre, VexOpcode opc,
5750 bool is_extended_context, bool is_merge_context,
5751 int vector_len, bool no_mask_reg ){
5752 // EVEX 0x62 prefix
5753 prefix(EVEX_4bytes);
5754 evex_encoding = (vex_w ? VEX_W : 0) | (evex_r ? EVEX_Rb : 0);
5755
5756 // P0: byte 2, initialized to RXBR`00mm
5757 // instead of not'd
5758 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
5759 byte2 = (~byte2) & 0xF0;
5760 // confine opc opcode extensions in mm bits to lower two bits
5761 // of form {0F, 0F_38, 0F_3A}
5762 byte2 |= opc;
5763 emit_int8(byte2);
5764
5765 // P1: byte 3 as Wvvvv1pp
5766 int byte3 = ((~nds_enc) & 0xf) << 3;
5767 // p[10] is always 1
5768 byte3 |= EVEX_F;
5769 byte3 |= (vex_w & 1) << 7;
5770 // confine pre opcode extensions in pp bits to lower two bits
5771 // of form {66, F3, F2}
5772 byte3 |= pre;
5773 emit_int8(byte3);
5774
5775 // P2: byte 4 as zL'Lbv'aaa
5776 int byte4 = (no_mask_reg) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
5777 // EVEX.v` for extending EVEX.vvvv or VIDX
5778 byte4 |= (evex_v ? 0: EVEX_V);
5779 // third EXEC.b for broadcast actions
5780 byte4 |= (is_extended_context ? EVEX_Rb : 0);
5781 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
5782 byte4 |= ((vector_len) & 0x3) << 5;
5783 // last is EVEX.z for zero/merge actions
5784 byte4 |= (is_merge_context ? EVEX_Z : 0);
5785 emit_int8(byte4);
5786 }
5787
5788 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre,
5789 VexOpcode opc, bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg) {
5790 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
5791 bool vex_b = adr.base_needs_rex();
5792 bool vex_x = adr.index_needs_rex();
5793 avx_vector_len = vector_len;
5794
5795 // if vector length is turned off, revert to AVX for vectors smaller than AVX_512bit
5796 if (VM_Version::supports_avx512vl() == false) {
5797 switch (vector_len) {
5798 case AVX_128bit:
5799 case AVX_256bit:
5800 legacy_mode = true;
5801 break;
5802 }
5803 }
5804
5805 if ((UseAVX > 2) && (legacy_mode == false))
5806 {
5807 bool evex_r = (xreg_enc >= 16);
5808 bool evex_v = (nds_enc >= 16);
5809 is_evex_instruction = true;
5810 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg);
5811 } else {
5812 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len);
5813 }
5814 }
5815
5816 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
5817 bool vex_w, int vector_len, bool legacy_mode, bool no_mask_reg ) {
5818 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
5819 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
5820 bool vex_x = false;
5821 avx_vector_len = vector_len;
5822
5823 // if vector length is turned off, revert to AVX for vectors smaller than AVX_512bit
5824 if (VM_Version::supports_avx512vl() == false) {
5825 switch (vector_len) {
5826 case AVX_128bit:
5827 case AVX_256bit:
5828 legacy_mode = true;
5829 break;
5830 }
5831 }
5832
5833 if ((UseAVX > 2) && (legacy_mode == false))
5834 {
5835 bool evex_r = (dst_enc >= 16);
5836 bool evex_v = (nds_enc >= 16);
5837 // can use vex_x as bank extender on rm encoding
5838 vex_x = (src_enc >= 16);
5839 evex_prefix(vex_r, vex_b, vex_x, vex_w, evex_r, evex_v, nds_enc, pre, opc, false, false, vector_len, no_mask_reg);
5840 } else {
5841 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector_len);
5842 }
5843
5844 // return modrm byte components for operands
5845 return (((dst_enc & 7) << 3) | (src_enc & 7));
5846 }
5847
5848
5849 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
5850 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) {
5851 if (UseAVX > 0) {
5852 int xreg_enc = xreg->encoding();
5853 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5854 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg);
5855 } else {
5856 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
5857 rex_prefix(adr, xreg, pre, opc, rex_w);
5858 }
5859 }
5860
5861 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
5862 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len, bool legacy_mode) {
5863 int dst_enc = dst->encoding();
5864 int src_enc = src->encoding();
5865 if (UseAVX > 0) {
5866 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5867 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, legacy_mode, no_mask_reg);
5868 } else {
5869 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
5870 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
5871 }
5872 }
5873
5874 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src, VexSimdPrefix pre,
5875 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) {
5876 int dst_enc = dst->encoding();
5877 int src_enc = src->encoding();
5878 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5879 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg);
5880 }
5881
5882 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src, VexSimdPrefix pre,
5883 bool no_mask_reg, VexOpcode opc, bool rex_w, int vector_len) {
5884 int dst_enc = dst->encoding();
5885 int src_enc = src->encoding();
5886 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5887 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector_len, true, no_mask_reg);
5888 }
5889
5890 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5891 InstructionMark im(this);
5892 simd_prefix(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
5893 emit_int8(opcode);
5894 emit_operand(dst, src);
5895 }
5896
5897 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool no_mask_reg) {
5898 InstructionMark im(this);
5899 simd_prefix_q(dst, dst, src, pre, no_mask_reg);
5900 emit_int8(opcode);
5901 emit_operand(dst, src);
5902 }
5903
5904 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5905 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, false, AVX_128bit, legacy_mode);
5906 emit_int8(opcode);
5907 emit_int8((unsigned char)(0xC0 | encode));
5908 }
5909
5910 void Assembler::emit_simd_arith_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
5911 int encode = simd_prefix_and_encode(dst, dst, src, pre, no_mask_reg, VEX_OPCODE_0F, true, AVX_128bit);
5912 emit_int8(opcode);
5913 emit_int8((unsigned char)(0xC0 | encode));
5914 }
5915
5916 // Versions with no second source register (non-destructive source).
5917 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) {
5918 InstructionMark im(this);
5919 simd_prefix(dst, xnoreg, src, pre, opNoRegMask);
5920 emit_int8(opcode);
5921 emit_operand(dst, src);
5922 }
5923
5924 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre, bool opNoRegMask) {
5925 InstructionMark im(this);
5926 simd_prefix_q(dst, xnoreg, src, pre, opNoRegMask);
5927 emit_int8(opcode);
5928 emit_operand(dst, src);
5929 }
5930
5931 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg, bool legacy_mode) {
5932 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, legacy_mode, AVX_128bit);
5933 emit_int8(opcode);
5934 emit_int8((unsigned char)(0xC0 | encode));
5935 }
5936
5937 void Assembler::emit_simd_arith_nonds_q(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre, bool no_mask_reg) {
5938 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre, no_mask_reg, VEX_OPCODE_0F, true, AVX_128bit);
5939 emit_int8(opcode);
5940 emit_int8((unsigned char)(0xC0 | encode));
5941 }
5942
5943 // 3-operands AVX instructions
5944 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, Address src,
5945 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
5946 InstructionMark im(this);
5947 vex_prefix(dst, nds, src, pre, vector_len, no_mask_reg, legacy_mode);
5948 emit_int8(opcode);
5949 emit_operand(dst, src);
5950 }
5951
5952 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds,
5953 Address src, VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
5954 InstructionMark im(this);
5955 vex_prefix_q(dst, nds, src, pre, vector_len, no_mask_reg);
5956 emit_int8(opcode);
5957 emit_operand(dst, src);
5958 }
5959
5960 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
5961 VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
5962 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector_len, VEX_OPCODE_0F, false, no_mask_reg);
5963 emit_int8(opcode);
5964 emit_int8((unsigned char)(0xC0 | encode));
5965 }
5966
5967 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
5968 VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
5969 int src_enc = src->encoding();
5970 int dst_enc = dst->encoding();
5971 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5972 int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
5973 emit_int8(opcode);
5974 emit_int8((unsigned char)(0xC0 | encode));
5975 }
5976
5977 #ifndef _LP64
5978
5979 void Assembler::incl(Register dst) {
5980 // Don't use it directly. Use MacroAssembler::incrementl() instead.
5981 emit_int8(0x40 | dst->encoding());
5982 }
5983
5984 void Assembler::lea(Register dst, Address src) {
5985 leal(dst, src);
5986 }
5987
5988 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
5989 InstructionMark im(this);
5990 emit_int8((unsigned char)0xC7);
5991 emit_operand(rax, dst);
5992 emit_data((int)imm32, rspec, 0);
5993 }
5994
5995 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
5996 InstructionMark im(this);
5997 int encode = prefix_and_encode(dst->encoding());
5998 emit_int8((unsigned char)(0xB8 | encode));
5999 emit_data((int)imm32, rspec, 0);
6000 }
6001
6002 void Assembler::popa() { // 32bit
6003 emit_int8(0x61);
6004 }
6005
6006 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
6007 InstructionMark im(this);
6008 emit_int8(0x68);
6009 emit_data(imm32, rspec, 0);
6010 }
6011
6012 void Assembler::pusha() { // 32bit
6013 emit_int8(0x60);
6014 }
6015
6016 void Assembler::set_byte_if_not_zero(Register dst) {
6017 emit_int8(0x0F);
6018 emit_int8((unsigned char)0x95);
6019 emit_int8((unsigned char)(0xE0 | dst->encoding()));
6020 }
6021
6022 void Assembler::shldl(Register dst, Register src) {
6023 emit_int8(0x0F);
6024 emit_int8((unsigned char)0xA5);
6025 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6026 }
6027
6028 void Assembler::shrdl(Register dst, Register src) {
6029 emit_int8(0x0F);
6030 emit_int8((unsigned char)0xAD);
6031 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6032 }
6033
6034 #else // LP64
6035
6036 void Assembler::set_byte_if_not_zero(Register dst) {
6037 int enc = prefix_and_encode(dst->encoding(), true);
6038 emit_int8(0x0F);
6039 emit_int8((unsigned char)0x95);
6040 emit_int8((unsigned char)(0xE0 | enc));
6041 }
6042
6043 // 64bit only pieces of the assembler
6044 // This should only be used by 64bit instructions that can use rip-relative
6045 // it cannot be used by instructions that want an immediate value.
6046
6047 bool Assembler::reachable(AddressLiteral adr) {
6048 int64_t disp;
6049 // None will force a 64bit literal to the code stream. Likely a placeholder
6050 // for something that will be patched later and we need to certain it will
6051 // always be reachable.
6052 if (adr.reloc() == relocInfo::none) {
6053 return false;
6054 }
6055 if (adr.reloc() == relocInfo::internal_word_type) {
6056 // This should be rip relative and easily reachable.
6057 return true;
6058 }
6059 if (adr.reloc() == relocInfo::virtual_call_type ||
6060 adr.reloc() == relocInfo::opt_virtual_call_type ||
6061 adr.reloc() == relocInfo::static_call_type ||
6062 adr.reloc() == relocInfo::static_stub_type ) {
6063 // This should be rip relative within the code cache and easily
6064 // reachable until we get huge code caches. (At which point
6065 // ic code is going to have issues).
6066 return true;
6067 }
6068 if (adr.reloc() != relocInfo::external_word_type &&
6069 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
6070 adr.reloc() != relocInfo::poll_type && // relocs to identify them
6071 adr.reloc() != relocInfo::runtime_call_type ) {
6072 return false;
6073 }
6074
6075 // Stress the correction code
6076 if (ForceUnreachable) {
6077 // Must be runtimecall reloc, see if it is in the codecache
6078 // Flipping stuff in the codecache to be unreachable causes issues
6079 // with things like inline caches where the additional instructions
6080 // are not handled.
6081 if (CodeCache::find_blob(adr._target) == NULL) {
6082 return false;
6083 }
6084 }
6085 // For external_word_type/runtime_call_type if it is reachable from where we
6086 // are now (possibly a temp buffer) and where we might end up
6087 // anywhere in the codeCache then we are always reachable.
6088 // This would have to change if we ever save/restore shared code
6089 // to be more pessimistic.
6090 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
6091 if (!is_simm32(disp)) return false;
6092 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
6093 if (!is_simm32(disp)) return false;
6094
6095 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
6096
6097 // Because rip relative is a disp + address_of_next_instruction and we
6098 // don't know the value of address_of_next_instruction we apply a fudge factor
6099 // to make sure we will be ok no matter the size of the instruction we get placed into.
6100 // We don't have to fudge the checks above here because they are already worst case.
6101
6102 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
6103 // + 4 because better safe than sorry.
6104 const int fudge = 12 + 4;
6105 if (disp < 0) {
6106 disp -= fudge;
6107 } else {
6108 disp += fudge;
6109 }
6110 return is_simm32(disp);
6111 }
6112
6113 // Check if the polling page is not reachable from the code cache using rip-relative
6114 // addressing.
6115 bool Assembler::is_polling_page_far() {
6116 intptr_t addr = (intptr_t)os::get_polling_page();
6117 return ForceUnreachable ||
6118 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
6119 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
6120 }
6121
6122 void Assembler::emit_data64(jlong data,
6123 relocInfo::relocType rtype,
6124 int format) {
6125 if (rtype == relocInfo::none) {
6126 emit_int64(data);
6127 } else {
6128 emit_data64(data, Relocation::spec_simple(rtype), format);
6129 }
6130 }
6131
6132 void Assembler::emit_data64(jlong data,
6133 RelocationHolder const& rspec,
6134 int format) {
6135 assert(imm_operand == 0, "default format must be immediate in this file");
6136 assert(imm_operand == format, "must be immediate");
6137 assert(inst_mark() != NULL, "must be inside InstructionMark");
6138 // Do not use AbstractAssembler::relocate, which is not intended for
6139 // embedded words. Instead, relocate to the enclosing instruction.
6140 code_section()->relocate(inst_mark(), rspec, format);
6141 #ifdef ASSERT
6142 check_relocation(rspec, format);
6143 #endif
6144 emit_int64(data);
6145 }
6146
6147 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
6148 if (reg_enc >= 8) {
6149 prefix(REX_B);
6150 reg_enc -= 8;
6151 } else if (byteinst && reg_enc >= 4) {
6152 prefix(REX);
6153 }
6154 return reg_enc;
6155 }
6156
6157 int Assembler::prefixq_and_encode(int reg_enc) {
6158 if (reg_enc < 8) {
6159 prefix(REX_W);
6160 } else {
6161 prefix(REX_WB);
6162 reg_enc -= 8;
6163 }
6164 return reg_enc;
6165 }
6166
6167 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
6168 if (dst_enc < 8) {
6169 if (src_enc >= 8) {
6170 prefix(REX_B);
6171 src_enc -= 8;
6172 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
6173 prefix(REX);
6174 }
6175 } else {
6176 if (src_enc < 8) {
6177 prefix(REX_R);
6178 } else {
6179 prefix(REX_RB);
6180 src_enc -= 8;
6181 }
6182 dst_enc -= 8;
6183 }
6184 return dst_enc << 3 | src_enc;
6185 }
6186
6187 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
6188 if (dst_enc < 8) {
6189 if (src_enc < 8) {
6190 prefix(REX_W);
6191 } else {
6192 prefix(REX_WB);
6193 src_enc -= 8;
6194 }
6195 } else {
6196 if (src_enc < 8) {
6197 prefix(REX_WR);
6198 } else {
6199 prefix(REX_WRB);
6200 src_enc -= 8;
6201 }
6202 dst_enc -= 8;
6203 }
6204 return dst_enc << 3 | src_enc;
6205 }
6206
6207 void Assembler::prefix(Register reg) {
6208 if (reg->encoding() >= 8) {
6209 prefix(REX_B);
6210 }
6211 }
6212
6213 void Assembler::prefix(Address adr) {
6214 if (adr.base_needs_rex()) {
6215 if (adr.index_needs_rex()) {
6216 prefix(REX_XB);
6217 } else {
6218 prefix(REX_B);
6219 }
6220 } else {
6221 if (adr.index_needs_rex()) {
6222 prefix(REX_X);
6223 }
6224 }
6225 }
6226
6227 void Assembler::prefixq(Address adr) {
6228 if (adr.base_needs_rex()) {
6229 if (adr.index_needs_rex()) {
6230 prefix(REX_WXB);
6231 } else {
6232 prefix(REX_WB);
6233 }
6234 } else {
6235 if (adr.index_needs_rex()) {
6236 prefix(REX_WX);
6237 } else {
6238 prefix(REX_W);
6239 }
6240 }
6241 }
6242
6243
6244 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
6245 if (reg->encoding() < 8) {
6246 if (adr.base_needs_rex()) {
6247 if (adr.index_needs_rex()) {
6248 prefix(REX_XB);
6249 } else {
6250 prefix(REX_B);
6251 }
6252 } else {
6253 if (adr.index_needs_rex()) {
6254 prefix(REX_X);
6255 } else if (byteinst && reg->encoding() >= 4 ) {
6256 prefix(REX);
6257 }
6258 }
6259 } else {
6260 if (adr.base_needs_rex()) {
6261 if (adr.index_needs_rex()) {
6262 prefix(REX_RXB);
6263 } else {
6264 prefix(REX_RB);
6265 }
6266 } else {
6267 if (adr.index_needs_rex()) {
6268 prefix(REX_RX);
6269 } else {
6270 prefix(REX_R);
6271 }
6272 }
6273 }
6274 }
6275
6276 void Assembler::prefixq(Address adr, Register src) {
6277 if (src->encoding() < 8) {
6278 if (adr.base_needs_rex()) {
6279 if (adr.index_needs_rex()) {
6280 prefix(REX_WXB);
6281 } else {
6282 prefix(REX_WB);
6283 }
6284 } else {
6285 if (adr.index_needs_rex()) {
6286 prefix(REX_WX);
6287 } else {
6288 prefix(REX_W);
6289 }
6290 }
6291 } else {
6292 if (adr.base_needs_rex()) {
6293 if (adr.index_needs_rex()) {
6294 prefix(REX_WRXB);
6295 } else {
6296 prefix(REX_WRB);
6297 }
6298 } else {
6299 if (adr.index_needs_rex()) {
6300 prefix(REX_WRX);
6301 } else {
6302 prefix(REX_WR);
6303 }
6304 }
6305 }
6306 }
6307
6308 void Assembler::prefix(Address adr, XMMRegister reg) {
6309 if (reg->encoding() < 8) {
6310 if (adr.base_needs_rex()) {
6311 if (adr.index_needs_rex()) {
6312 prefix(REX_XB);
6313 } else {
6314 prefix(REX_B);
6315 }
6316 } else {
6317 if (adr.index_needs_rex()) {
6318 prefix(REX_X);
6319 }
6320 }
6321 } else {
6322 if (adr.base_needs_rex()) {
6323 if (adr.index_needs_rex()) {
6324 prefix(REX_RXB);
6325 } else {
6326 prefix(REX_RB);
6327 }
6328 } else {
6329 if (adr.index_needs_rex()) {
6330 prefix(REX_RX);
6331 } else {
6332 prefix(REX_R);
6333 }
6334 }
6335 }
6336 }
6337
6338 void Assembler::prefixq(Address adr, XMMRegister src) {
6339 if (src->encoding() < 8) {
6340 if (adr.base_needs_rex()) {
6341 if (adr.index_needs_rex()) {
6342 prefix(REX_WXB);
6343 } else {
6344 prefix(REX_WB);
6345 }
6346 } else {
6347 if (adr.index_needs_rex()) {
6348 prefix(REX_WX);
6349 } else {
6350 prefix(REX_W);
6351 }
6352 }
6353 } else {
6354 if (adr.base_needs_rex()) {
6355 if (adr.index_needs_rex()) {
6356 prefix(REX_WRXB);
6357 } else {
6358 prefix(REX_WRB);
6359 }
6360 } else {
6361 if (adr.index_needs_rex()) {
6362 prefix(REX_WRX);
6363 } else {
6364 prefix(REX_WR);
6365 }
6366 }
6367 }
6368 }
6369
6370 void Assembler::adcq(Register dst, int32_t imm32) {
6371 (void) prefixq_and_encode(dst->encoding());
6372 emit_arith(0x81, 0xD0, dst, imm32);
6373 }
6374
6375 void Assembler::adcq(Register dst, Address src) {
6376 InstructionMark im(this);
6377 prefixq(src, dst);
6378 emit_int8(0x13);
6379 emit_operand(dst, src);
6380 }
6381
6382 void Assembler::adcq(Register dst, Register src) {
6383 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6384 emit_arith(0x13, 0xC0, dst, src);
6385 }
6386
6387 void Assembler::addq(Address dst, int32_t imm32) {
6388 InstructionMark im(this);
6389 prefixq(dst);
6390 emit_arith_operand(0x81, rax, dst,imm32);
6391 }
6392
6393 void Assembler::addq(Address dst, Register src) {
6394 InstructionMark im(this);
6395 prefixq(dst, src);
6396 emit_int8(0x01);
6397 emit_operand(src, dst);
6398 }
6399
6400 void Assembler::addq(Register dst, int32_t imm32) {
6401 (void) prefixq_and_encode(dst->encoding());
6402 emit_arith(0x81, 0xC0, dst, imm32);
6403 }
6404
6405 void Assembler::addq(Register dst, Address src) {
6406 InstructionMark im(this);
6407 prefixq(src, dst);
6408 emit_int8(0x03);
6409 emit_operand(dst, src);
6410 }
6411
6412 void Assembler::addq(Register dst, Register src) {
6413 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6414 emit_arith(0x03, 0xC0, dst, src);
6415 }
6416
6417 void Assembler::adcxq(Register dst, Register src) {
6418 //assert(VM_Version::supports_adx(), "adx instructions not supported");
6419 emit_int8((unsigned char)0x66);
6420 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6421 emit_int8(0x0F);
6422 emit_int8(0x38);
6423 emit_int8((unsigned char)0xF6);
6424 emit_int8((unsigned char)(0xC0 | encode));
6425 }
6426
6427 void Assembler::adoxq(Register dst, Register src) {
6428 //assert(VM_Version::supports_adx(), "adx instructions not supported");
6429 emit_int8((unsigned char)0xF3);
6430 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6431 emit_int8(0x0F);
6432 emit_int8(0x38);
6433 emit_int8((unsigned char)0xF6);
6434 emit_int8((unsigned char)(0xC0 | encode));
6435 }
6436
6437 void Assembler::andq(Address dst, int32_t imm32) {
6438 InstructionMark im(this);
6439 prefixq(dst);
6440 emit_int8((unsigned char)0x81);
6441 emit_operand(rsp, dst, 4);
6442 emit_int32(imm32);
6443 }
6444
6445 void Assembler::andq(Register dst, int32_t imm32) {
6446 (void) prefixq_and_encode(dst->encoding());
6447 emit_arith(0x81, 0xE0, dst, imm32);
6448 }
6449
6450 void Assembler::andq(Register dst, Address src) {
6451 InstructionMark im(this);
6452 prefixq(src, dst);
6453 emit_int8(0x23);
6454 emit_operand(dst, src);
6455 }
6456
6457 void Assembler::andq(Register dst, Register src) {
6458 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6459 emit_arith(0x23, 0xC0, dst, src);
6460 }
6461
6462 void Assembler::andnq(Register dst, Register src1, Register src2) {
6463 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6464 int encode = vex_prefix_0F38_and_encode_q_legacy(dst, src1, src2);
6465 emit_int8((unsigned char)0xF2);
6466 emit_int8((unsigned char)(0xC0 | encode));
6467 }
6468
6469 void Assembler::andnq(Register dst, Register src1, Address src2) {
6470 InstructionMark im(this);
6471 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6472 vex_prefix_0F38_q_legacy(dst, src1, src2);
6473 emit_int8((unsigned char)0xF2);
6474 emit_operand(dst, src2);
6475 }
6476
6477 void Assembler::bsfq(Register dst, Register src) {
6478 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6479 emit_int8(0x0F);
6480 emit_int8((unsigned char)0xBC);
6481 emit_int8((unsigned char)(0xC0 | encode));
6482 }
6483
6484 void Assembler::bsrq(Register dst, Register src) {
6485 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6486 emit_int8(0x0F);
6487 emit_int8((unsigned char)0xBD);
6488 emit_int8((unsigned char)(0xC0 | encode));
6489 }
6490
6491 void Assembler::bswapq(Register reg) {
6492 int encode = prefixq_and_encode(reg->encoding());
6493 emit_int8(0x0F);
6494 emit_int8((unsigned char)(0xC8 | encode));
6495 }
6496
6497 void Assembler::blsiq(Register dst, Register src) {
6498 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6499 int encode = vex_prefix_0F38_and_encode_q_legacy(rbx, dst, src);
6500 emit_int8((unsigned char)0xF3);
6501 emit_int8((unsigned char)(0xC0 | encode));
6502 }
6503
6504 void Assembler::blsiq(Register dst, Address src) {
6505 InstructionMark im(this);
6506 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6507 vex_prefix_0F38_q_legacy(rbx, dst, src);
6508 emit_int8((unsigned char)0xF3);
6509 emit_operand(rbx, src);
6510 }
6511
6512 void Assembler::blsmskq(Register dst, Register src) {
6513 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6514 int encode = vex_prefix_0F38_and_encode_q_legacy(rdx, dst, src);
6515 emit_int8((unsigned char)0xF3);
6516 emit_int8((unsigned char)(0xC0 | encode));
6517 }
6518
6519 void Assembler::blsmskq(Register dst, Address src) {
6520 InstructionMark im(this);
6521 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6522 vex_prefix_0F38_q_legacy(rdx, dst, src);
6523 emit_int8((unsigned char)0xF3);
6524 emit_operand(rdx, src);
6525 }
6526
6527 void Assembler::blsrq(Register dst, Register src) {
6528 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6529 int encode = vex_prefix_0F38_and_encode_q_legacy(rcx, dst, src);
6530 emit_int8((unsigned char)0xF3);
6531 emit_int8((unsigned char)(0xC0 | encode));
6532 }
6533
6534 void Assembler::blsrq(Register dst, Address src) {
6535 InstructionMark im(this);
6536 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6537 vex_prefix_0F38_q_legacy(rcx, dst, src);
6538 emit_int8((unsigned char)0xF3);
6539 emit_operand(rcx, src);
6540 }
6541
6542 void Assembler::cdqq() {
6543 prefix(REX_W);
6544 emit_int8((unsigned char)0x99);
6545 }
6546
6547 void Assembler::clflush(Address adr) {
6548 prefix(adr);
6549 emit_int8(0x0F);
6550 emit_int8((unsigned char)0xAE);
6551 emit_operand(rdi, adr);
6552 }
6553
6554 void Assembler::cmovq(Condition cc, Register dst, Register src) {
6555 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6556 emit_int8(0x0F);
6557 emit_int8(0x40 | cc);
6558 emit_int8((unsigned char)(0xC0 | encode));
6559 }
6560
6561 void Assembler::cmovq(Condition cc, Register dst, Address src) {
6562 InstructionMark im(this);
6563 prefixq(src, dst);
6564 emit_int8(0x0F);
6565 emit_int8(0x40 | cc);
6566 emit_operand(dst, src);
6567 }
6568
6569 void Assembler::cmpq(Address dst, int32_t imm32) {
6570 InstructionMark im(this);
6571 prefixq(dst);
6572 emit_int8((unsigned char)0x81);
6573 emit_operand(rdi, dst, 4);
6574 emit_int32(imm32);
6575 }
6576
6577 void Assembler::cmpq(Register dst, int32_t imm32) {
6578 (void) prefixq_and_encode(dst->encoding());
6579 emit_arith(0x81, 0xF8, dst, imm32);
6580 }
6581
6582 void Assembler::cmpq(Address dst, Register src) {
6583 InstructionMark im(this);
6584 prefixq(dst, src);
6585 emit_int8(0x3B);
6586 emit_operand(src, dst);
6587 }
6588
6589 void Assembler::cmpq(Register dst, Register src) {
6590 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6591 emit_arith(0x3B, 0xC0, dst, src);
6592 }
6593
6594 void Assembler::cmpq(Register dst, Address src) {
6595 InstructionMark im(this);
6596 prefixq(src, dst);
6597 emit_int8(0x3B);
6598 emit_operand(dst, src);
6599 }
6600
6601 void Assembler::cmpxchgq(Register reg, Address adr) {
6602 InstructionMark im(this);
6603 prefixq(adr, reg);
6604 emit_int8(0x0F);
6605 emit_int8((unsigned char)0xB1);
6606 emit_operand(reg, adr);
6607 }
6608
6609 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
6610 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6611 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, true);
6612 emit_int8(0x2A);
6613 emit_int8((unsigned char)(0xC0 | encode));
6614 }
6615
6616 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
6617 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6618 if (VM_Version::supports_evex()) {
6619 tuple_type = EVEX_T1S;
6620 input_size_in_bits = EVEX_32bit;
6621 }
6622 InstructionMark im(this);
6623 simd_prefix_q(dst, dst, src, VEX_SIMD_F2, true);
6624 emit_int8(0x2A);
6625 emit_operand(dst, src);
6626 }
6627
6628 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
6629 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6630 if (VM_Version::supports_evex()) {
6631 tuple_type = EVEX_T1S;
6632 input_size_in_bits = EVEX_32bit;
6633 }
6634 InstructionMark im(this);
6635 simd_prefix_q(dst, dst, src, VEX_SIMD_F3, true);
6636 emit_int8(0x2A);
6637 emit_operand(dst, src);
6638 }
6639
6640 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
6641 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6642 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true);
6643 emit_int8(0x2C);
6644 emit_int8((unsigned char)(0xC0 | encode));
6645 }
6646
6647 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
6648 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6649 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, true);
6650 emit_int8(0x2C);
6651 emit_int8((unsigned char)(0xC0 | encode));
6652 }
6653
6654 void Assembler::decl(Register dst) {
6655 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6656 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
6657 int encode = prefix_and_encode(dst->encoding());
6658 emit_int8((unsigned char)0xFF);
6659 emit_int8((unsigned char)(0xC8 | encode));
6660 }
6661
6662 void Assembler::decq(Register dst) {
6663 // Don't use it directly. Use MacroAssembler::decrementq() instead.
6664 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6665 int encode = prefixq_and_encode(dst->encoding());
6666 emit_int8((unsigned char)0xFF);
6667 emit_int8(0xC8 | encode);
6668 }
6669
6670 void Assembler::decq(Address dst) {
6671 // Don't use it directly. Use MacroAssembler::decrementq() instead.
6672 InstructionMark im(this);
6673 prefixq(dst);
6674 emit_int8((unsigned char)0xFF);
6675 emit_operand(rcx, dst);
6676 }
6677
6678 void Assembler::fxrstor(Address src) {
6679 prefixq(src);
6680 emit_int8(0x0F);
6681 emit_int8((unsigned char)0xAE);
6682 emit_operand(as_Register(1), src);
6683 }
6684
6685 void Assembler::fxsave(Address dst) {
6686 prefixq(dst);
6687 emit_int8(0x0F);
6688 emit_int8((unsigned char)0xAE);
6689 emit_operand(as_Register(0), dst);
6690 }
6691
6692 void Assembler::idivq(Register src) {
6693 int encode = prefixq_and_encode(src->encoding());
6694 emit_int8((unsigned char)0xF7);
6695 emit_int8((unsigned char)(0xF8 | encode));
6696 }
6697
6698 void Assembler::imulq(Register dst, Register src) {
6699 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6700 emit_int8(0x0F);
6701 emit_int8((unsigned char)0xAF);
6702 emit_int8((unsigned char)(0xC0 | encode));
6703 }
6704
6705 void Assembler::imulq(Register dst, Register src, int value) {
6706 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6707 if (is8bit(value)) {
6708 emit_int8(0x6B);
6709 emit_int8((unsigned char)(0xC0 | encode));
6710 emit_int8(value & 0xFF);
6711 } else {
6712 emit_int8(0x69);
6713 emit_int8((unsigned char)(0xC0 | encode));
6714 emit_int32(value);
6715 }
6716 }
6717
6718 void Assembler::imulq(Register dst, Address src) {
6719 InstructionMark im(this);
6720 prefixq(src, dst);
6721 emit_int8(0x0F);
6722 emit_int8((unsigned char) 0xAF);
6723 emit_operand(dst, src);
6724 }
6725
6726 void Assembler::incl(Register dst) {
6727 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6728 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6729 int encode = prefix_and_encode(dst->encoding());
6730 emit_int8((unsigned char)0xFF);
6731 emit_int8((unsigned char)(0xC0 | encode));
6732 }
6733
6734 void Assembler::incq(Register dst) {
6735 // Don't use it directly. Use MacroAssembler::incrementq() instead.
6736 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
6737 int encode = prefixq_and_encode(dst->encoding());
6738 emit_int8((unsigned char)0xFF);
6739 emit_int8((unsigned char)(0xC0 | encode));
6740 }
6741
6742 void Assembler::incq(Address dst) {
6743 // Don't use it directly. Use MacroAssembler::incrementq() instead.
6744 InstructionMark im(this);
6745 prefixq(dst);
6746 emit_int8((unsigned char)0xFF);
6747 emit_operand(rax, dst);
6748 }
6749
6750 void Assembler::lea(Register dst, Address src) {
6751 leaq(dst, src);
6752 }
6753
6754 void Assembler::leaq(Register dst, Address src) {
6755 InstructionMark im(this);
6756 prefixq(src, dst);
6757 emit_int8((unsigned char)0x8D);
6758 emit_operand(dst, src);
6759 }
6760
6761 void Assembler::mov64(Register dst, int64_t imm64) {
6762 InstructionMark im(this);
6763 int encode = prefixq_and_encode(dst->encoding());
6764 emit_int8((unsigned char)(0xB8 | encode));
6765 emit_int64(imm64);
6766 }
6767
6768 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
6769 InstructionMark im(this);
6770 int encode = prefixq_and_encode(dst->encoding());
6771 emit_int8(0xB8 | encode);
6772 emit_data64(imm64, rspec);
6773 }
6774
6775 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6776 InstructionMark im(this);
6777 int encode = prefix_and_encode(dst->encoding());
6778 emit_int8((unsigned char)(0xB8 | encode));
6779 emit_data((int)imm32, rspec, narrow_oop_operand);
6780 }
6781
6782 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6783 InstructionMark im(this);
6784 prefix(dst);
6785 emit_int8((unsigned char)0xC7);
6786 emit_operand(rax, dst, 4);
6787 emit_data((int)imm32, rspec, narrow_oop_operand);
6788 }
6789
6790 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6791 InstructionMark im(this);
6792 int encode = prefix_and_encode(src1->encoding());
6793 emit_int8((unsigned char)0x81);
6794 emit_int8((unsigned char)(0xF8 | encode));
6795 emit_data((int)imm32, rspec, narrow_oop_operand);
6796 }
6797
6798 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6799 InstructionMark im(this);
6800 prefix(src1);
6801 emit_int8((unsigned char)0x81);
6802 emit_operand(rax, src1, 4);
6803 emit_data((int)imm32, rspec, narrow_oop_operand);
6804 }
6805
6806 void Assembler::lzcntq(Register dst, Register src) {
6807 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
6808 emit_int8((unsigned char)0xF3);
6809 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6810 emit_int8(0x0F);
6811 emit_int8((unsigned char)0xBD);
6812 emit_int8((unsigned char)(0xC0 | encode));
6813 }
6814
6815 void Assembler::movdq(XMMRegister dst, Register src) {
6816 // table D-1 says MMX/SSE2
6817 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6818 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66, true);
6819 emit_int8(0x6E);
6820 emit_int8((unsigned char)(0xC0 | encode));
6821 }
6822
6823 void Assembler::movdq(Register dst, XMMRegister src) {
6824 // table D-1 says MMX/SSE2
6825 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6826 // swap src/dst to get correct prefix
6827 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66, true);
6828 emit_int8(0x7E);
6829 emit_int8((unsigned char)(0xC0 | encode));
6830 }
6831
6832 void Assembler::movq(Register dst, Register src) {
6833 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6834 emit_int8((unsigned char)0x8B);
6835 emit_int8((unsigned char)(0xC0 | encode));
6836 }
6837
6838 void Assembler::movq(Register dst, Address src) {
6839 InstructionMark im(this);
6840 prefixq(src, dst);
6841 emit_int8((unsigned char)0x8B);
6842 emit_operand(dst, src);
6843 }
6844
6845 void Assembler::movq(Address dst, Register src) {
6846 InstructionMark im(this);
6847 prefixq(dst, src);
6848 emit_int8((unsigned char)0x89);
6849 emit_operand(src, dst);
6850 }
6851
6852 void Assembler::movsbq(Register dst, Address src) {
6853 InstructionMark im(this);
6854 prefixq(src, dst);
6855 emit_int8(0x0F);
6856 emit_int8((unsigned char)0xBE);
6857 emit_operand(dst, src);
6858 }
6859
6860 void Assembler::movsbq(Register dst, Register src) {
6861 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6862 emit_int8(0x0F);
6863 emit_int8((unsigned char)0xBE);
6864 emit_int8((unsigned char)(0xC0 | encode));
6865 }
6866
6867 void Assembler::movslq(Register dst, int32_t imm32) {
6868 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
6869 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
6870 // as a result we shouldn't use until tested at runtime...
6871 ShouldNotReachHere();
6872 InstructionMark im(this);
6873 int encode = prefixq_and_encode(dst->encoding());
6874 emit_int8((unsigned char)(0xC7 | encode));
6875 emit_int32(imm32);
6876 }
6877
6878 void Assembler::movslq(Address dst, int32_t imm32) {
6879 assert(is_simm32(imm32), "lost bits");
6880 InstructionMark im(this);
6881 prefixq(dst);
6882 emit_int8((unsigned char)0xC7);
6883 emit_operand(rax, dst, 4);
6884 emit_int32(imm32);
6885 }
6886
6887 void Assembler::movslq(Register dst, Address src) {
6888 InstructionMark im(this);
6889 prefixq(src, dst);
6890 emit_int8(0x63);
6891 emit_operand(dst, src);
6892 }
6893
6894 void Assembler::movslq(Register dst, Register src) {
6895 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6896 emit_int8(0x63);
6897 emit_int8((unsigned char)(0xC0 | encode));
6898 }
6899
6900 void Assembler::movswq(Register dst, Address src) {
6901 InstructionMark im(this);
6902 prefixq(src, dst);
6903 emit_int8(0x0F);
6904 emit_int8((unsigned char)0xBF);
6905 emit_operand(dst, src);
6906 }
6907
6908 void Assembler::movswq(Register dst, Register src) {
6909 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6910 emit_int8((unsigned char)0x0F);
6911 emit_int8((unsigned char)0xBF);
6912 emit_int8((unsigned char)(0xC0 | encode));
6913 }
6914
6915 void Assembler::movzbq(Register dst, Address src) {
6916 InstructionMark im(this);
6917 prefixq(src, dst);
6918 emit_int8((unsigned char)0x0F);
6919 emit_int8((unsigned char)0xB6);
6920 emit_operand(dst, src);
6921 }
6922
6923 void Assembler::movzbq(Register dst, Register src) {
6924 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6925 emit_int8(0x0F);
6926 emit_int8((unsigned char)0xB6);
6927 emit_int8(0xC0 | encode);
6928 }
6929
6930 void Assembler::movzwq(Register dst, Address src) {
6931 InstructionMark im(this);
6932 prefixq(src, dst);
6933 emit_int8((unsigned char)0x0F);
6934 emit_int8((unsigned char)0xB7);
6935 emit_operand(dst, src);
6936 }
6937
6938 void Assembler::movzwq(Register dst, Register src) {
6939 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6940 emit_int8((unsigned char)0x0F);
6941 emit_int8((unsigned char)0xB7);
6942 emit_int8((unsigned char)(0xC0 | encode));
6943 }
6944
6945 void Assembler::mulq(Address src) {
6946 InstructionMark im(this);
6947 prefixq(src);
6948 emit_int8((unsigned char)0xF7);
6949 emit_operand(rsp, src);
6950 }
6951
6952 void Assembler::mulq(Register src) {
6953 int encode = prefixq_and_encode(src->encoding());
6954 emit_int8((unsigned char)0xF7);
6955 emit_int8((unsigned char)(0xE0 | encode));
6956 }
6957
6958 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
6959 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
6960 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(),
6961 VEX_SIMD_F2, VEX_OPCODE_0F_38, true, AVX_128bit, true, false);
6962 emit_int8((unsigned char)0xF6);
6963 emit_int8((unsigned char)(0xC0 | encode));
6964 }
6965
6966 void Assembler::negq(Register dst) {
6967 int encode = prefixq_and_encode(dst->encoding());
6968 emit_int8((unsigned char)0xF7);
6969 emit_int8((unsigned char)(0xD8 | encode));
6970 }
6971
6972 void Assembler::notq(Register dst) {
6973 int encode = prefixq_and_encode(dst->encoding());
6974 emit_int8((unsigned char)0xF7);
6975 emit_int8((unsigned char)(0xD0 | encode));
6976 }
6977
6978 void Assembler::orq(Address dst, int32_t imm32) {
6979 InstructionMark im(this);
6980 prefixq(dst);
6981 emit_int8((unsigned char)0x81);
6982 emit_operand(rcx, dst, 4);
6983 emit_int32(imm32);
6984 }
6985
6986 void Assembler::orq(Register dst, int32_t imm32) {
6987 (void) prefixq_and_encode(dst->encoding());
6988 emit_arith(0x81, 0xC8, dst, imm32);
6989 }
6990
6991 void Assembler::orq(Register dst, Address src) {
6992 InstructionMark im(this);
6993 prefixq(src, dst);
6994 emit_int8(0x0B);
6995 emit_operand(dst, src);
6996 }
6997
6998 void Assembler::orq(Register dst, Register src) {
6999 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7000 emit_arith(0x0B, 0xC0, dst, src);
7001 }
7002
7003 void Assembler::popa() { // 64bit
7004 movq(r15, Address(rsp, 0));
7005 movq(r14, Address(rsp, wordSize));
7006 movq(r13, Address(rsp, 2 * wordSize));
7007 movq(r12, Address(rsp, 3 * wordSize));
7008 movq(r11, Address(rsp, 4 * wordSize));
7009 movq(r10, Address(rsp, 5 * wordSize));
7010 movq(r9, Address(rsp, 6 * wordSize));
7011 movq(r8, Address(rsp, 7 * wordSize));
7012 movq(rdi, Address(rsp, 8 * wordSize));
7013 movq(rsi, Address(rsp, 9 * wordSize));
7014 movq(rbp, Address(rsp, 10 * wordSize));
7015 // skip rsp
7016 movq(rbx, Address(rsp, 12 * wordSize));
7017 movq(rdx, Address(rsp, 13 * wordSize));
7018 movq(rcx, Address(rsp, 14 * wordSize));
7019 movq(rax, Address(rsp, 15 * wordSize));
7020
7021 addq(rsp, 16 * wordSize);
7022 }
7023
7024 void Assembler::popcntq(Register dst, Address src) {
7025 assert(VM_Version::supports_popcnt(), "must support");
7026 InstructionMark im(this);
7027 emit_int8((unsigned char)0xF3);
7028 prefixq(src, dst);
7029 emit_int8((unsigned char)0x0F);
7030 emit_int8((unsigned char)0xB8);
7031 emit_operand(dst, src);
7032 }
7033
7034 void Assembler::popcntq(Register dst, Register src) {
7035 assert(VM_Version::supports_popcnt(), "must support");
7036 emit_int8((unsigned char)0xF3);
7037 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7038 emit_int8((unsigned char)0x0F);
7039 emit_int8((unsigned char)0xB8);
7040 emit_int8((unsigned char)(0xC0 | encode));
7041 }
7042
7043 void Assembler::popq(Address dst) {
7044 InstructionMark im(this);
7045 prefixq(dst);
7046 emit_int8((unsigned char)0x8F);
7047 emit_operand(rax, dst);
7048 }
7049
7050 void Assembler::pusha() { // 64bit
7051 // we have to store original rsp. ABI says that 128 bytes
7052 // below rsp are local scratch.
7053 movq(Address(rsp, -5 * wordSize), rsp);
7054
7055 subq(rsp, 16 * wordSize);
7056
7057 movq(Address(rsp, 15 * wordSize), rax);
7058 movq(Address(rsp, 14 * wordSize), rcx);
7059 movq(Address(rsp, 13 * wordSize), rdx);
7060 movq(Address(rsp, 12 * wordSize), rbx);
7061 // skip rsp
7062 movq(Address(rsp, 10 * wordSize), rbp);
7063 movq(Address(rsp, 9 * wordSize), rsi);
7064 movq(Address(rsp, 8 * wordSize), rdi);
7065 movq(Address(rsp, 7 * wordSize), r8);
7066 movq(Address(rsp, 6 * wordSize), r9);
7067 movq(Address(rsp, 5 * wordSize), r10);
7068 movq(Address(rsp, 4 * wordSize), r11);
7069 movq(Address(rsp, 3 * wordSize), r12);
7070 movq(Address(rsp, 2 * wordSize), r13);
7071 movq(Address(rsp, wordSize), r14);
7072 movq(Address(rsp, 0), r15);
7073 }
7074
7075 void Assembler::pushq(Address src) {
7076 InstructionMark im(this);
7077 prefixq(src);
7078 emit_int8((unsigned char)0xFF);
7079 emit_operand(rsi, src);
7080 }
7081
7082 void Assembler::rclq(Register dst, int imm8) {
7083 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7084 int encode = prefixq_and_encode(dst->encoding());
7085 if (imm8 == 1) {
7086 emit_int8((unsigned char)0xD1);
7087 emit_int8((unsigned char)(0xD0 | encode));
7088 } else {
7089 emit_int8((unsigned char)0xC1);
7090 emit_int8((unsigned char)(0xD0 | encode));
7091 emit_int8(imm8);
7092 }
7093 }
7094
7095 void Assembler::rcrq(Register dst, int imm8) {
7096 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7097 int encode = prefixq_and_encode(dst->encoding());
7098 if (imm8 == 1) {
7099 emit_int8((unsigned char)0xD1);
7100 emit_int8((unsigned char)(0xD8 | encode));
7101 } else {
7102 emit_int8((unsigned char)0xC1);
7103 emit_int8((unsigned char)(0xD8 | encode));
7104 emit_int8(imm8);
7105 }
7106 }
7107
7108 void Assembler::rorq(Register dst, int imm8) {
7109 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7110 int encode = prefixq_and_encode(dst->encoding());
7111 if (imm8 == 1) {
7112 emit_int8((unsigned char)0xD1);
7113 emit_int8((unsigned char)(0xC8 | encode));
7114 } else {
7115 emit_int8((unsigned char)0xC1);
7116 emit_int8((unsigned char)(0xc8 | encode));
7117 emit_int8(imm8);
7118 }
7119 }
7120
7121 void Assembler::rorxq(Register dst, Register src, int imm8) {
7122 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7123 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2,
7124 VEX_OPCODE_0F_3A, true, AVX_128bit, true, false);
7125 emit_int8((unsigned char)0xF0);
7126 emit_int8((unsigned char)(0xC0 | encode));
7127 emit_int8(imm8);
7128 }
7129
7130 void Assembler::sarq(Register dst, int imm8) {
7131 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7132 int encode = prefixq_and_encode(dst->encoding());
7133 if (imm8 == 1) {
7134 emit_int8((unsigned char)0xD1);
7135 emit_int8((unsigned char)(0xF8 | encode));
7136 } else {
7137 emit_int8((unsigned char)0xC1);
7138 emit_int8((unsigned char)(0xF8 | encode));
7139 emit_int8(imm8);
7140 }
7141 }
7142
7143 void Assembler::sarq(Register dst) {
7144 int encode = prefixq_and_encode(dst->encoding());
7145 emit_int8((unsigned char)0xD3);
7146 emit_int8((unsigned char)(0xF8 | encode));
7147 }
7148
7149 void Assembler::sbbq(Address dst, int32_t imm32) {
7150 InstructionMark im(this);
7151 prefixq(dst);
7152 emit_arith_operand(0x81, rbx, dst, imm32);
7153 }
7154
7155 void Assembler::sbbq(Register dst, int32_t imm32) {
7156 (void) prefixq_and_encode(dst->encoding());
7157 emit_arith(0x81, 0xD8, dst, imm32);
7158 }
7159
7160 void Assembler::sbbq(Register dst, Address src) {
7161 InstructionMark im(this);
7162 prefixq(src, dst);
7163 emit_int8(0x1B);
7164 emit_operand(dst, src);
7165 }
7166
7167 void Assembler::sbbq(Register dst, Register src) {
7168 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7169 emit_arith(0x1B, 0xC0, dst, src);
7170 }
7171
7172 void Assembler::shlq(Register dst, int imm8) {
7173 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7174 int encode = prefixq_and_encode(dst->encoding());
7175 if (imm8 == 1) {
7176 emit_int8((unsigned char)0xD1);
7177 emit_int8((unsigned char)(0xE0 | encode));
7178 } else {
7179 emit_int8((unsigned char)0xC1);
7180 emit_int8((unsigned char)(0xE0 | encode));
7181 emit_int8(imm8);
7182 }
7183 }
7184
7185 void Assembler::shlq(Register dst) {
7186 int encode = prefixq_and_encode(dst->encoding());
7187 emit_int8((unsigned char)0xD3);
7188 emit_int8((unsigned char)(0xE0 | encode));
7189 }
7190
7191 void Assembler::shrq(Register dst, int imm8) {
7192 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7193 int encode = prefixq_and_encode(dst->encoding());
7194 emit_int8((unsigned char)0xC1);
7195 emit_int8((unsigned char)(0xE8 | encode));
7196 emit_int8(imm8);
7197 }
7198
7199 void Assembler::shrq(Register dst) {
7200 int encode = prefixq_and_encode(dst->encoding());
7201 emit_int8((unsigned char)0xD3);
7202 emit_int8(0xE8 | encode);
7203 }
7204
7205 void Assembler::subq(Address dst, int32_t imm32) {
7206 InstructionMark im(this);
7207 prefixq(dst);
7208 emit_arith_operand(0x81, rbp, dst, imm32);
7209 }
7210
7211 void Assembler::subq(Address dst, Register src) {
7212 InstructionMark im(this);
7213 prefixq(dst, src);
7214 emit_int8(0x29);
7215 emit_operand(src, dst);
7216 }
7217
7218 void Assembler::subq(Register dst, int32_t imm32) {
7219 (void) prefixq_and_encode(dst->encoding());
7220 emit_arith(0x81, 0xE8, dst, imm32);
7221 }
7222
7223 // Force generation of a 4 byte immediate value even if it fits into 8bit
7224 void Assembler::subq_imm32(Register dst, int32_t imm32) {
7225 (void) prefixq_and_encode(dst->encoding());
7226 emit_arith_imm32(0x81, 0xE8, dst, imm32);
7227 }
7228
7229 void Assembler::subq(Register dst, Address src) {
7230 InstructionMark im(this);
7231 prefixq(src, dst);
7232 emit_int8(0x2B);
7233 emit_operand(dst, src);
7234 }
7235
7236 void Assembler::subq(Register dst, Register src) {
7237 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7238 emit_arith(0x2B, 0xC0, dst, src);
7239 }
7240
7241 void Assembler::testq(Register dst, int32_t imm32) {
7242 // not using emit_arith because test
7243 // doesn't support sign-extension of
7244 // 8bit operands
7245 int encode = dst->encoding();
7246 if (encode == 0) {
7247 prefix(REX_W);
7248 emit_int8((unsigned char)0xA9);
7249 } else {
7250 encode = prefixq_and_encode(encode);
7251 emit_int8((unsigned char)0xF7);
7252 emit_int8((unsigned char)(0xC0 | encode));
7253 }
7254 emit_int32(imm32);
7255 }
7256
7257 void Assembler::testq(Register dst, Register src) {
7258 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7259 emit_arith(0x85, 0xC0, dst, src);
7260 }
7261
7262 void Assembler::xaddq(Address dst, Register src) {
7263 InstructionMark im(this);
7264 prefixq(dst, src);
7265 emit_int8(0x0F);
7266 emit_int8((unsigned char)0xC1);
7267 emit_operand(src, dst);
7268 }
7269
7270 void Assembler::xchgq(Register dst, Address src) {
7271 InstructionMark im(this);
7272 prefixq(src, dst);
7273 emit_int8((unsigned char)0x87);
7274 emit_operand(dst, src);
7275 }
7276
7277 void Assembler::xchgq(Register dst, Register src) {
7278 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7279 emit_int8((unsigned char)0x87);
7280 emit_int8((unsigned char)(0xc0 | encode));
7281 }
7282
7283 void Assembler::xorq(Register dst, Register src) {
7284 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7285 emit_arith(0x33, 0xC0, dst, src);
7286 }
7287
7288 void Assembler::xorq(Register dst, Address src) {
7289 InstructionMark im(this);
7290 prefixq(src, dst);
7291 emit_int8(0x33);
7292 emit_operand(dst, src);
7293 }
7294
7295 #endif // !LP64