1 //
2 // Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer registers (including RSP and RBP)
173 reg_class any_reg_with_rbp(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all pointer registers (including RSP, but excluding RBP)
191 reg_class any_reg_no_rbp(RAX, RAX_H,
192 RDX, RDX_H,
193 RDI, RDI_H,
194 RSI, RSI_H,
195 RCX, RCX_H,
196 RBX, RBX_H,
197 RSP, RSP_H,
198 R8, R8_H,
199 R9, R9_H,
200 R10, R10_H,
201 R11, R11_H,
202 R12, R12_H,
203 R13, R13_H,
204 R14, R14_H,
205 R15, R15_H);
206
207 // Dynamic register class that selects at runtime between register classes
208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
211
212 // Class for all pointer registers (excluding RSP)
213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
214 RDX, RDX_H,
215 RBP, RBP_H,
216 RDI, RDI_H,
217 RSI, RSI_H,
218 RCX, RCX_H,
219 RBX, RBX_H,
220 R8, R8_H,
221 R9, R9_H,
222 R10, R10_H,
223 R11, R11_H,
224 R13, R13_H,
225 R14, R14_H);
226
227 // Class for all pointer registers (excluding RSP and RBP)
228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
229 RDX, RDX_H,
230 RDI, RDI_H,
231 RSI, RSI_H,
232 RCX, RCX_H,
233 RBX, RBX_H,
234 R8, R8_H,
235 R9, R9_H,
236 R10, R10_H,
237 R11, R11_H,
238 R13, R13_H,
239 R14, R14_H);
240
241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
243
244 // Class for all pointer registers (excluding RAX and RSP)
245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
246 RBP, RBP_H,
247 RDI, RDI_H,
248 RSI, RSI_H,
249 RCX, RCX_H,
250 RBX, RBX_H,
251 R8, R8_H,
252 R9, R9_H,
253 R10, R10_H,
254 R11, R11_H,
255 R13, R13_H,
256 R14, R14_H);
257
258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
260 RDI, RDI_H,
261 RSI, RSI_H,
262 RCX, RCX_H,
263 RBX, RBX_H,
264 R8, R8_H,
265 R9, R9_H,
266 R10, R10_H,
267 R11, R11_H,
268 R13, R13_H,
269 R14, R14_H);
270
271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
273
274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
276 RBP, RBP_H,
277 RDI, RDI_H,
278 RSI, RSI_H,
279 RCX, RCX_H,
280 R8, R8_H,
281 R9, R9_H,
282 R10, R10_H,
283 R11, R11_H,
284 R13, R13_H,
285 R14, R14_H);
286
287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 R8, R8_H,
293 R9, R9_H,
294 R10, R10_H,
295 R11, R11_H,
296 R13, R13_H,
297 R14, R14_H);
298
299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
301
302 // Singleton class for RAX pointer register
303 reg_class ptr_rax_reg(RAX, RAX_H);
304
305 // Singleton class for RBX pointer register
306 reg_class ptr_rbx_reg(RBX, RBX_H);
307
308 // Singleton class for RSI pointer register
309 reg_class ptr_rsi_reg(RSI, RSI_H);
310
311 // Singleton class for RDI pointer register
312 reg_class ptr_rdi_reg(RDI, RDI_H);
313
314 // Singleton class for stack pointer
315 reg_class ptr_rsp_reg(RSP, RSP_H);
316
317 // Singleton class for TLS pointer
318 reg_class ptr_r15_reg(R15, R15_H);
319
320 // Class for all long registers (excluding RSP)
321 reg_class long_reg_with_rbp(RAX, RAX_H,
322 RDX, RDX_H,
323 RBP, RBP_H,
324 RDI, RDI_H,
325 RSI, RSI_H,
326 RCX, RCX_H,
327 RBX, RBX_H,
328 R8, R8_H,
329 R9, R9_H,
330 R10, R10_H,
331 R11, R11_H,
332 R13, R13_H,
333 R14, R14_H);
334
335 // Class for all long registers (excluding RSP and RBP)
336 reg_class long_reg_no_rbp(RAX, RAX_H,
337 RDX, RDX_H,
338 RDI, RDI_H,
339 RSI, RSI_H,
340 RCX, RCX_H,
341 RBX, RBX_H,
342 R8, R8_H,
343 R9, R9_H,
344 R10, R10_H,
345 R11, R11_H,
346 R13, R13_H,
347 R14, R14_H);
348
349 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
350 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
351
352 // Class for all long registers (excluding RAX, RDX and RSP)
353 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
354 RDI, RDI_H,
355 RSI, RSI_H,
356 RCX, RCX_H,
357 RBX, RBX_H,
358 R8, R8_H,
359 R9, R9_H,
360 R10, R10_H,
361 R11, R11_H,
362 R13, R13_H,
363 R14, R14_H);
364
365 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
366 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
367 RSI, RSI_H,
368 RCX, RCX_H,
369 RBX, RBX_H,
370 R8, R8_H,
371 R9, R9_H,
372 R10, R10_H,
373 R11, R11_H,
374 R13, R13_H,
375 R14, R14_H);
376
377 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
378 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
379
380 // Class for all long registers (excluding RCX and RSP)
381 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
382 RDI, RDI_H,
383 RSI, RSI_H,
384 RAX, RAX_H,
385 RDX, RDX_H,
386 RBX, RBX_H,
387 R8, R8_H,
388 R9, R9_H,
389 R10, R10_H,
390 R11, R11_H,
391 R13, R13_H,
392 R14, R14_H);
393
394 // Class for all long registers (excluding RCX, RSP, and RBP)
395 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
396 RSI, RSI_H,
397 RAX, RAX_H,
398 RDX, RDX_H,
399 RBX, RBX_H,
400 R8, R8_H,
401 R9, R9_H,
402 R10, R10_H,
403 R11, R11_H,
404 R13, R13_H,
405 R14, R14_H);
406
407 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
408 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
409
410 // Singleton class for RAX long register
411 reg_class long_rax_reg(RAX, RAX_H);
412
413 // Singleton class for RCX long register
414 reg_class long_rcx_reg(RCX, RCX_H);
415
416 // Singleton class for RDX long register
417 reg_class long_rdx_reg(RDX, RDX_H);
418
419 // Class for all int registers (excluding RSP)
420 reg_class int_reg_with_rbp(RAX,
421 RDX,
422 RBP,
423 RDI,
424 RSI,
425 RCX,
426 RBX,
427 R8,
428 R9,
429 R10,
430 R11,
431 R13,
432 R14);
433
434 // Class for all int registers (excluding RSP and RBP)
435 reg_class int_reg_no_rbp(RAX,
436 RDX,
437 RDI,
438 RSI,
439 RCX,
440 RBX,
441 R8,
442 R9,
443 R10,
444 R11,
445 R13,
446 R14);
447
448 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
449 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
450
451 // Class for all int registers (excluding RCX and RSP)
452 reg_class int_no_rcx_reg_with_rbp(RAX,
453 RDX,
454 RBP,
455 RDI,
456 RSI,
457 RBX,
458 R8,
459 R9,
460 R10,
461 R11,
462 R13,
463 R14);
464
465 // Class for all int registers (excluding RCX, RSP, and RBP)
466 reg_class int_no_rcx_reg_no_rbp(RAX,
467 RDX,
468 RDI,
469 RSI,
470 RBX,
471 R8,
472 R9,
473 R10,
474 R11,
475 R13,
476 R14);
477
478 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
479 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
480
481 // Class for all int registers (excluding RAX, RDX, and RSP)
482 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
483 RDI,
484 RSI,
485 RCX,
486 RBX,
487 R8,
488 R9,
489 R10,
490 R11,
491 R13,
492 R14);
493
494 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
495 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
496 RSI,
497 RCX,
498 RBX,
499 R8,
500 R9,
501 R10,
502 R11,
503 R13,
504 R14);
505
506 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
507 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
508
509 // Singleton class for RAX int register
510 reg_class int_rax_reg(RAX);
511
512 // Singleton class for RBX int register
513 reg_class int_rbx_reg(RBX);
514
515 // Singleton class for RCX int register
516 reg_class int_rcx_reg(RCX);
517
518 // Singleton class for RCX int register
519 reg_class int_rdx_reg(RDX);
520
521 // Singleton class for RCX int register
522 reg_class int_rdi_reg(RDI);
523
524 // Singleton class for instruction pointer
525 // reg_class ip_reg(RIP);
526
527 %}
528
529 //----------SOURCE BLOCK-------------------------------------------------------
530 // This is a block of C++ code which provides values, functions, and
531 // definitions necessary in the rest of the architecture description
532 source %{
533 #define RELOC_IMM64 Assembler::imm_operand
534 #define RELOC_DISP32 Assembler::disp32_operand
535
536 #define __ _masm.
537
538 static int clear_avx_size() {
539 if(UseAVX > 2) {
540 return 0; // vzeroupper is ignored
541 } else {
542 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
543 }
544 }
545
546 // !!!!! Special hack to get all types of calls to specify the byte offset
547 // from the start of the call to the point where the return address
548 // will point.
549 int MachCallStaticJavaNode::ret_addr_offset()
550 {
551 int offset = 5; // 5 bytes from start of call to where return address points
552 offset += clear_avx_size();
553 return offset;
554 }
555
556 int MachCallDynamicJavaNode::ret_addr_offset()
557 {
558 int offset = 15; // 15 bytes from start of call to where return address points
559 offset += clear_avx_size();
560 return offset;
561 }
562
563 int MachCallRuntimeNode::ret_addr_offset() {
564 int offset = 13; // movq r10,#addr; callq (r10)
565 offset += clear_avx_size();
566 return offset;
567 }
568
569 // Indicate if the safepoint node needs the polling page as an input,
570 // it does if the polling page is more than disp32 away.
571 bool SafePointNode::needs_polling_address_input()
572 {
573 return Assembler::is_polling_page_far();
574 }
575
576 //
577 // Compute padding required for nodes which need alignment
578 //
579
580 // The address of the call instruction needs to be 4-byte aligned to
581 // ensure that it does not span a cache line so that it can be patched.
582 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
583 {
584 current_offset += clear_avx_size(); // skip vzeroupper
585 current_offset += 1; // skip call opcode byte
586 return round_to(current_offset, alignment_required()) - current_offset;
587 }
588
589 // The address of the call instruction needs to be 4-byte aligned to
590 // ensure that it does not span a cache line so that it can be patched.
591 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
592 {
593 current_offset += clear_avx_size(); // skip vzeroupper
594 current_offset += 11; // skip movq instruction + call opcode byte
595 return round_to(current_offset, alignment_required()) - current_offset;
596 }
597
598 // EMIT_RM()
599 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
600 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
601 cbuf.insts()->emit_int8(c);
602 }
603
604 // EMIT_CC()
605 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
606 unsigned char c = (unsigned char) (f1 | f2);
607 cbuf.insts()->emit_int8(c);
608 }
609
610 // EMIT_OPCODE()
611 void emit_opcode(CodeBuffer &cbuf, int code) {
612 cbuf.insts()->emit_int8((unsigned char) code);
613 }
614
615 // EMIT_OPCODE() w/ relocation information
616 void emit_opcode(CodeBuffer &cbuf,
617 int code, relocInfo::relocType reloc, int offset, int format)
618 {
619 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
620 emit_opcode(cbuf, code);
621 }
622
623 // EMIT_D8()
624 void emit_d8(CodeBuffer &cbuf, int d8) {
625 cbuf.insts()->emit_int8((unsigned char) d8);
626 }
627
628 // EMIT_D16()
629 void emit_d16(CodeBuffer &cbuf, int d16) {
630 cbuf.insts()->emit_int16(d16);
631 }
632
633 // EMIT_D32()
634 void emit_d32(CodeBuffer &cbuf, int d32) {
635 cbuf.insts()->emit_int32(d32);
636 }
637
638 // EMIT_D64()
639 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
640 cbuf.insts()->emit_int64(d64);
641 }
642
643 // emit 32 bit value and construct relocation entry from relocInfo::relocType
644 void emit_d32_reloc(CodeBuffer& cbuf,
645 int d32,
646 relocInfo::relocType reloc,
647 int format)
648 {
649 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
650 cbuf.relocate(cbuf.insts_mark(), reloc, format);
651 cbuf.insts()->emit_int32(d32);
652 }
653
654 // emit 32 bit value and construct relocation entry from RelocationHolder
655 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
656 #ifdef ASSERT
657 if (rspec.reloc()->type() == relocInfo::oop_type &&
658 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
659 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
660 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
661 }
662 #endif
663 cbuf.relocate(cbuf.insts_mark(), rspec, format);
664 cbuf.insts()->emit_int32(d32);
665 }
666
667 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
668 address next_ip = cbuf.insts_end() + 4;
669 emit_d32_reloc(cbuf, (int) (addr - next_ip),
670 external_word_Relocation::spec(addr),
671 RELOC_DISP32);
672 }
673
674
675 // emit 64 bit value and construct relocation entry from relocInfo::relocType
676 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
677 cbuf.relocate(cbuf.insts_mark(), reloc, format);
678 cbuf.insts()->emit_int64(d64);
679 }
680
681 // emit 64 bit value and construct relocation entry from RelocationHolder
682 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
683 #ifdef ASSERT
684 if (rspec.reloc()->type() == relocInfo::oop_type &&
685 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
686 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
687 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
688 "cannot embed scavengable oops in code");
689 }
690 #endif
691 cbuf.relocate(cbuf.insts_mark(), rspec, format);
692 cbuf.insts()->emit_int64(d64);
693 }
694
695 // Access stack slot for load or store
696 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
697 {
698 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
699 if (-0x80 <= disp && disp < 0x80) {
700 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
701 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
702 emit_d8(cbuf, disp); // Displacement // R/M byte
703 } else {
704 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
705 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
706 emit_d32(cbuf, disp); // Displacement // R/M byte
707 }
708 }
709
710 // rRegI ereg, memory mem) %{ // emit_reg_mem
711 void encode_RegMem(CodeBuffer &cbuf,
712 int reg,
713 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
714 {
715 assert(disp_reloc == relocInfo::none, "cannot have disp");
716 int regenc = reg & 7;
717 int baseenc = base & 7;
718 int indexenc = index & 7;
719
720 // There is no index & no scale, use form without SIB byte
721 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
722 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
723 if (disp == 0 && base != RBP_enc && base != R13_enc) {
724 emit_rm(cbuf, 0x0, regenc, baseenc); // *
725 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
726 // If 8-bit displacement, mode 0x1
727 emit_rm(cbuf, 0x1, regenc, baseenc); // *
728 emit_d8(cbuf, disp);
729 } else {
730 // If 32-bit displacement
731 if (base == -1) { // Special flag for absolute address
732 emit_rm(cbuf, 0x0, regenc, 0x5); // *
733 if (disp_reloc != relocInfo::none) {
734 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
735 } else {
736 emit_d32(cbuf, disp);
737 }
738 } else {
739 // Normal base + offset
740 emit_rm(cbuf, 0x2, regenc, baseenc); // *
741 if (disp_reloc != relocInfo::none) {
742 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
743 } else {
744 emit_d32(cbuf, disp);
745 }
746 }
747 }
748 } else {
749 // Else, encode with the SIB byte
750 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
751 if (disp == 0 && base != RBP_enc && base != R13_enc) {
752 // If no displacement
753 emit_rm(cbuf, 0x0, regenc, 0x4); // *
754 emit_rm(cbuf, scale, indexenc, baseenc);
755 } else {
756 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
757 // If 8-bit displacement, mode 0x1
758 emit_rm(cbuf, 0x1, regenc, 0x4); // *
759 emit_rm(cbuf, scale, indexenc, baseenc);
760 emit_d8(cbuf, disp);
761 } else {
762 // If 32-bit displacement
763 if (base == 0x04 ) {
764 emit_rm(cbuf, 0x2, regenc, 0x4);
765 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
766 } else {
767 emit_rm(cbuf, 0x2, regenc, 0x4);
768 emit_rm(cbuf, scale, indexenc, baseenc); // *
769 }
770 if (disp_reloc != relocInfo::none) {
771 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
772 } else {
773 emit_d32(cbuf, disp);
774 }
775 }
776 }
777 }
778 }
779
780 // This could be in MacroAssembler but it's fairly C2 specific
781 void emit_cmpfp_fixup(MacroAssembler& _masm) {
782 Label exit;
783 __ jccb(Assembler::noParity, exit);
784 __ pushf();
785 //
786 // comiss/ucomiss instructions set ZF,PF,CF flags and
787 // zero OF,AF,SF for NaN values.
788 // Fixup flags by zeroing ZF,PF so that compare of NaN
789 // values returns 'less than' result (CF is set).
790 // Leave the rest of flags unchanged.
791 //
792 // 7 6 5 4 3 2 1 0
793 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
794 // 0 0 1 0 1 0 1 1 (0x2B)
795 //
796 __ andq(Address(rsp, 0), 0xffffff2b);
797 __ popf();
798 __ bind(exit);
799 }
800
801 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
802 Label done;
803 __ movl(dst, -1);
804 __ jcc(Assembler::parity, done);
805 __ jcc(Assembler::below, done);
806 __ setb(Assembler::notEqual, dst);
807 __ movzbl(dst, dst);
808 __ bind(done);
809 }
810
811
812 //=============================================================================
813 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
814
815 int Compile::ConstantTable::calculate_table_base_offset() const {
816 return 0; // absolute addressing, no offset
817 }
818
819 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
820 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
821 ShouldNotReachHere();
822 }
823
824 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
825 // Empty encoding
826 }
827
828 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
829 return 0;
830 }
831
832 #ifndef PRODUCT
833 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
834 st->print("# MachConstantBaseNode (empty encoding)");
835 }
836 #endif
837
838
839 //=============================================================================
840 #ifndef PRODUCT
841 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
842 Compile* C = ra_->C;
843
844 int framesize = C->frame_size_in_bytes();
845 int bangsize = C->bang_size_in_bytes();
846 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
847 // Remove wordSize for return addr which is already pushed.
848 framesize -= wordSize;
849
850 if (C->need_stack_bang(bangsize)) {
851 framesize -= wordSize;
852 st->print("# stack bang (%d bytes)", bangsize);
853 st->print("\n\t");
854 st->print("pushq rbp\t# Save rbp");
855 if (PreserveFramePointer) {
856 st->print("\n\t");
857 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
858 }
859 if (framesize) {
860 st->print("\n\t");
861 st->print("subq rsp, #%d\t# Create frame",framesize);
862 }
863 } else {
864 st->print("subq rsp, #%d\t# Create frame",framesize);
865 st->print("\n\t");
866 framesize -= wordSize;
867 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
868 if (PreserveFramePointer) {
869 st->print("\n\t");
870 st->print("movq rbp, [rsp + #%d]\t# Save the caller's SP into rbp", (framesize + wordSize));
871 }
872 }
873
874 if (VerifyStackAtCalls) {
875 st->print("\n\t");
876 framesize -= wordSize;
877 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
878 #ifdef ASSERT
879 st->print("\n\t");
880 st->print("# stack alignment check");
881 #endif
882 }
883 st->cr();
884 }
885 #endif
886
887 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
888 Compile* C = ra_->C;
889 MacroAssembler _masm(&cbuf);
890
891 int framesize = C->frame_size_in_bytes();
892 int bangsize = C->bang_size_in_bytes();
893
894 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
895
896 C->set_frame_complete(cbuf.insts_size());
897
898 if (C->has_mach_constant_base_node()) {
899 // NOTE: We set the table base offset here because users might be
900 // emitted before MachConstantBaseNode.
901 Compile::ConstantTable& constant_table = C->constant_table();
902 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
903 }
904 }
905
906 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
907 {
908 return MachNode::size(ra_); // too many variables; just compute it
909 // the hard way
910 }
911
912 int MachPrologNode::reloc() const
913 {
914 return 0; // a large enough number
915 }
916
917 //=============================================================================
918 #ifndef PRODUCT
919 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
920 {
921 Compile* C = ra_->C;
922 if (C->max_vector_size() > 16) {
923 st->print("vzeroupper");
924 st->cr(); st->print("\t");
925 }
926
927 int framesize = C->frame_size_in_bytes();
928 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
929 // Remove word for return adr already pushed
930 // and RBP
931 framesize -= 2*wordSize;
932
933 if (framesize) {
934 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
935 st->print("\t");
936 }
937
938 st->print_cr("popq rbp");
939 if (do_polling() && C->is_method_compilation()) {
940 st->print("\t");
941 if (Assembler::is_polling_page_far()) {
942 st->print_cr("movq rscratch1, #polling_page_address\n\t"
943 "testl rax, [rscratch1]\t"
944 "# Safepoint: poll for GC");
945 } else {
946 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
947 "# Safepoint: poll for GC");
948 }
949 }
950 }
951 #endif
952
953 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
954 {
955 Compile* C = ra_->C;
956 if (C->max_vector_size() > 16) {
957 // Clear upper bits of YMM registers when current compiled code uses
958 // wide vectors to avoid AVX <-> SSE transition penalty during call.
959 MacroAssembler _masm(&cbuf);
960 __ vzeroupper();
961 }
962
963 int framesize = C->frame_size_in_bytes();
964 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
965 // Remove word for return adr already pushed
966 // and RBP
967 framesize -= 2*wordSize;
968
969 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
970
971 if (framesize) {
972 emit_opcode(cbuf, Assembler::REX_W);
973 if (framesize < 0x80) {
974 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
975 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
976 emit_d8(cbuf, framesize);
977 } else {
978 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
979 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
980 emit_d32(cbuf, framesize);
981 }
982 }
983
984 // popq rbp
985 emit_opcode(cbuf, 0x58 | RBP_enc);
986
987 if (do_polling() && C->is_method_compilation()) {
988 MacroAssembler _masm(&cbuf);
989 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
990 if (Assembler::is_polling_page_far()) {
991 __ lea(rscratch1, polling_page);
992 __ relocate(relocInfo::poll_return_type);
993 __ testl(rax, Address(rscratch1, 0));
994 } else {
995 __ testl(rax, polling_page);
996 }
997 }
998 }
999
1000 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1001 {
1002 return MachNode::size(ra_); // too many variables; just compute it
1003 // the hard way
1004 }
1005
1006 int MachEpilogNode::reloc() const
1007 {
1008 return 2; // a large enough number
1009 }
1010
1011 const Pipeline* MachEpilogNode::pipeline() const
1012 {
1013 return MachNode::pipeline_class();
1014 }
1015
1016 int MachEpilogNode::safepoint_offset() const
1017 {
1018 return 0;
1019 }
1020
1021 //=============================================================================
1022
1023 enum RC {
1024 rc_bad,
1025 rc_int,
1026 rc_float,
1027 rc_stack
1028 };
1029
1030 static enum RC rc_class(OptoReg::Name reg)
1031 {
1032 if( !OptoReg::is_valid(reg) ) return rc_bad;
1033
1034 if (OptoReg::is_stack(reg)) return rc_stack;
1035
1036 VMReg r = OptoReg::as_VMReg(reg);
1037
1038 if (r->is_Register()) return rc_int;
1039
1040 assert(r->is_XMMRegister(), "must be");
1041 return rc_float;
1042 }
1043
1044 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1045 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1046 int src_hi, int dst_hi, uint ireg, outputStream* st);
1047
1048 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1049 int stack_offset, int reg, uint ireg, outputStream* st);
1050
1051 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1052 int dst_offset, uint ireg, outputStream* st) {
1053 if (cbuf) {
1054 MacroAssembler _masm(cbuf);
1055 switch (ireg) {
1056 case Op_VecS:
1057 __ movq(Address(rsp, -8), rax);
1058 __ movl(rax, Address(rsp, src_offset));
1059 __ movl(Address(rsp, dst_offset), rax);
1060 __ movq(rax, Address(rsp, -8));
1061 break;
1062 case Op_VecD:
1063 __ pushq(Address(rsp, src_offset));
1064 __ popq (Address(rsp, dst_offset));
1065 break;
1066 case Op_VecX:
1067 __ pushq(Address(rsp, src_offset));
1068 __ popq (Address(rsp, dst_offset));
1069 __ pushq(Address(rsp, src_offset+8));
1070 __ popq (Address(rsp, dst_offset+8));
1071 break;
1072 case Op_VecY:
1073 __ vmovdqu(Address(rsp, -32), xmm0);
1074 __ vmovdqu(xmm0, Address(rsp, src_offset));
1075 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1076 __ vmovdqu(xmm0, Address(rsp, -32));
1077 case Op_VecZ:
1078 __ evmovdqu(Address(rsp, -64), xmm0, 2);
1079 __ evmovdqu(xmm0, Address(rsp, src_offset), 2);
1080 __ evmovdqu(Address(rsp, dst_offset), xmm0, 2);
1081 __ evmovdqu(xmm0, Address(rsp, -64), 2);
1082 break;
1083 default:
1084 ShouldNotReachHere();
1085 }
1086 #ifndef PRODUCT
1087 } else {
1088 switch (ireg) {
1089 case Op_VecS:
1090 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1091 "movl rax, [rsp + #%d]\n\t"
1092 "movl [rsp + #%d], rax\n\t"
1093 "movq rax, [rsp - #8]",
1094 src_offset, dst_offset);
1095 break;
1096 case Op_VecD:
1097 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1098 "popq [rsp + #%d]",
1099 src_offset, dst_offset);
1100 break;
1101 case Op_VecX:
1102 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1103 "popq [rsp + #%d]\n\t"
1104 "pushq [rsp + #%d]\n\t"
1105 "popq [rsp + #%d]",
1106 src_offset, dst_offset, src_offset+8, dst_offset+8);
1107 break;
1108 case Op_VecY:
1109 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1110 "vmovdqu xmm0, [rsp + #%d]\n\t"
1111 "vmovdqu [rsp + #%d], xmm0\n\t"
1112 "vmovdqu xmm0, [rsp - #32]",
1113 src_offset, dst_offset);
1114 break;
1115 case Op_VecZ:
1116 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1117 "vmovdqu xmm0, [rsp + #%d]\n\t"
1118 "vmovdqu [rsp + #%d], xmm0\n\t"
1119 "vmovdqu xmm0, [rsp - #64]",
1120 src_offset, dst_offset);
1121 break;
1122 default:
1123 ShouldNotReachHere();
1124 }
1125 #endif
1126 }
1127 }
1128
1129 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1130 PhaseRegAlloc* ra_,
1131 bool do_size,
1132 outputStream* st) const {
1133 assert(cbuf != NULL || st != NULL, "sanity");
1134 // Get registers to move
1135 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1136 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1137 OptoReg::Name dst_second = ra_->get_reg_second(this);
1138 OptoReg::Name dst_first = ra_->get_reg_first(this);
1139
1140 enum RC src_second_rc = rc_class(src_second);
1141 enum RC src_first_rc = rc_class(src_first);
1142 enum RC dst_second_rc = rc_class(dst_second);
1143 enum RC dst_first_rc = rc_class(dst_first);
1144
1145 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1146 "must move at least 1 register" );
1147
1148 if (src_first == dst_first && src_second == dst_second) {
1149 // Self copy, no move
1150 return 0;
1151 }
1152 if (bottom_type()->isa_vect() != NULL) {
1153 uint ireg = ideal_reg();
1154 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1155 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1156 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1157 // mem -> mem
1158 int src_offset = ra_->reg2offset(src_first);
1159 int dst_offset = ra_->reg2offset(dst_first);
1160 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1161 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1162 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1163 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1164 int stack_offset = ra_->reg2offset(dst_first);
1165 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1166 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1167 int stack_offset = ra_->reg2offset(src_first);
1168 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1169 } else {
1170 ShouldNotReachHere();
1171 }
1172 return 0;
1173 }
1174 if (src_first_rc == rc_stack) {
1175 // mem ->
1176 if (dst_first_rc == rc_stack) {
1177 // mem -> mem
1178 assert(src_second != dst_first, "overlap");
1179 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1180 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1181 // 64-bit
1182 int src_offset = ra_->reg2offset(src_first);
1183 int dst_offset = ra_->reg2offset(dst_first);
1184 if (cbuf) {
1185 MacroAssembler _masm(cbuf);
1186 __ pushq(Address(rsp, src_offset));
1187 __ popq (Address(rsp, dst_offset));
1188 #ifndef PRODUCT
1189 } else {
1190 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1191 "popq [rsp + #%d]",
1192 src_offset, dst_offset);
1193 #endif
1194 }
1195 } else {
1196 // 32-bit
1197 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1198 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1199 // No pushl/popl, so:
1200 int src_offset = ra_->reg2offset(src_first);
1201 int dst_offset = ra_->reg2offset(dst_first);
1202 if (cbuf) {
1203 MacroAssembler _masm(cbuf);
1204 __ movq(Address(rsp, -8), rax);
1205 __ movl(rax, Address(rsp, src_offset));
1206 __ movl(Address(rsp, dst_offset), rax);
1207 __ movq(rax, Address(rsp, -8));
1208 #ifndef PRODUCT
1209 } else {
1210 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1211 "movl rax, [rsp + #%d]\n\t"
1212 "movl [rsp + #%d], rax\n\t"
1213 "movq rax, [rsp - #8]",
1214 src_offset, dst_offset);
1215 #endif
1216 }
1217 }
1218 return 0;
1219 } else if (dst_first_rc == rc_int) {
1220 // mem -> gpr
1221 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1222 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1223 // 64-bit
1224 int offset = ra_->reg2offset(src_first);
1225 if (cbuf) {
1226 MacroAssembler _masm(cbuf);
1227 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1228 #ifndef PRODUCT
1229 } else {
1230 st->print("movq %s, [rsp + #%d]\t# spill",
1231 Matcher::regName[dst_first],
1232 offset);
1233 #endif
1234 }
1235 } else {
1236 // 32-bit
1237 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1238 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1239 int offset = ra_->reg2offset(src_first);
1240 if (cbuf) {
1241 MacroAssembler _masm(cbuf);
1242 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1243 #ifndef PRODUCT
1244 } else {
1245 st->print("movl %s, [rsp + #%d]\t# spill",
1246 Matcher::regName[dst_first],
1247 offset);
1248 #endif
1249 }
1250 }
1251 return 0;
1252 } else if (dst_first_rc == rc_float) {
1253 // mem-> xmm
1254 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1255 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1256 // 64-bit
1257 int offset = ra_->reg2offset(src_first);
1258 if (cbuf) {
1259 MacroAssembler _masm(cbuf);
1260 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1261 #ifndef PRODUCT
1262 } else {
1263 st->print("%s %s, [rsp + #%d]\t# spill",
1264 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1265 Matcher::regName[dst_first],
1266 offset);
1267 #endif
1268 }
1269 } else {
1270 // 32-bit
1271 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1272 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1273 int offset = ra_->reg2offset(src_first);
1274 if (cbuf) {
1275 MacroAssembler _masm(cbuf);
1276 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1277 #ifndef PRODUCT
1278 } else {
1279 st->print("movss %s, [rsp + #%d]\t# spill",
1280 Matcher::regName[dst_first],
1281 offset);
1282 #endif
1283 }
1284 }
1285 return 0;
1286 }
1287 } else if (src_first_rc == rc_int) {
1288 // gpr ->
1289 if (dst_first_rc == rc_stack) {
1290 // gpr -> mem
1291 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1292 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1293 // 64-bit
1294 int offset = ra_->reg2offset(dst_first);
1295 if (cbuf) {
1296 MacroAssembler _masm(cbuf);
1297 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1298 #ifndef PRODUCT
1299 } else {
1300 st->print("movq [rsp + #%d], %s\t# spill",
1301 offset,
1302 Matcher::regName[src_first]);
1303 #endif
1304 }
1305 } else {
1306 // 32-bit
1307 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1308 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1309 int offset = ra_->reg2offset(dst_first);
1310 if (cbuf) {
1311 MacroAssembler _masm(cbuf);
1312 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1313 #ifndef PRODUCT
1314 } else {
1315 st->print("movl [rsp + #%d], %s\t# spill",
1316 offset,
1317 Matcher::regName[src_first]);
1318 #endif
1319 }
1320 }
1321 return 0;
1322 } else if (dst_first_rc == rc_int) {
1323 // gpr -> gpr
1324 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1325 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1326 // 64-bit
1327 if (cbuf) {
1328 MacroAssembler _masm(cbuf);
1329 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1330 as_Register(Matcher::_regEncode[src_first]));
1331 #ifndef PRODUCT
1332 } else {
1333 st->print("movq %s, %s\t# spill",
1334 Matcher::regName[dst_first],
1335 Matcher::regName[src_first]);
1336 #endif
1337 }
1338 return 0;
1339 } else {
1340 // 32-bit
1341 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1342 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1343 if (cbuf) {
1344 MacroAssembler _masm(cbuf);
1345 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1346 as_Register(Matcher::_regEncode[src_first]));
1347 #ifndef PRODUCT
1348 } else {
1349 st->print("movl %s, %s\t# spill",
1350 Matcher::regName[dst_first],
1351 Matcher::regName[src_first]);
1352 #endif
1353 }
1354 return 0;
1355 }
1356 } else if (dst_first_rc == rc_float) {
1357 // gpr -> xmm
1358 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1359 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1360 // 64-bit
1361 if (cbuf) {
1362 MacroAssembler _masm(cbuf);
1363 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1364 #ifndef PRODUCT
1365 } else {
1366 st->print("movdq %s, %s\t# spill",
1367 Matcher::regName[dst_first],
1368 Matcher::regName[src_first]);
1369 #endif
1370 }
1371 } else {
1372 // 32-bit
1373 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1374 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1375 if (cbuf) {
1376 MacroAssembler _masm(cbuf);
1377 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1378 #ifndef PRODUCT
1379 } else {
1380 st->print("movdl %s, %s\t# spill",
1381 Matcher::regName[dst_first],
1382 Matcher::regName[src_first]);
1383 #endif
1384 }
1385 }
1386 return 0;
1387 }
1388 } else if (src_first_rc == rc_float) {
1389 // xmm ->
1390 if (dst_first_rc == rc_stack) {
1391 // xmm -> mem
1392 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1393 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1394 // 64-bit
1395 int offset = ra_->reg2offset(dst_first);
1396 if (cbuf) {
1397 MacroAssembler _masm(cbuf);
1398 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1399 #ifndef PRODUCT
1400 } else {
1401 st->print("movsd [rsp + #%d], %s\t# spill",
1402 offset,
1403 Matcher::regName[src_first]);
1404 #endif
1405 }
1406 } else {
1407 // 32-bit
1408 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1409 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1410 int offset = ra_->reg2offset(dst_first);
1411 if (cbuf) {
1412 MacroAssembler _masm(cbuf);
1413 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1414 #ifndef PRODUCT
1415 } else {
1416 st->print("movss [rsp + #%d], %s\t# spill",
1417 offset,
1418 Matcher::regName[src_first]);
1419 #endif
1420 }
1421 }
1422 return 0;
1423 } else if (dst_first_rc == rc_int) {
1424 // xmm -> gpr
1425 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1426 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1427 // 64-bit
1428 if (cbuf) {
1429 MacroAssembler _masm(cbuf);
1430 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1431 #ifndef PRODUCT
1432 } else {
1433 st->print("movdq %s, %s\t# spill",
1434 Matcher::regName[dst_first],
1435 Matcher::regName[src_first]);
1436 #endif
1437 }
1438 } else {
1439 // 32-bit
1440 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1441 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1442 if (cbuf) {
1443 MacroAssembler _masm(cbuf);
1444 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1445 #ifndef PRODUCT
1446 } else {
1447 st->print("movdl %s, %s\t# spill",
1448 Matcher::regName[dst_first],
1449 Matcher::regName[src_first]);
1450 #endif
1451 }
1452 }
1453 return 0;
1454 } else if (dst_first_rc == rc_float) {
1455 // xmm -> xmm
1456 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1457 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1458 // 64-bit
1459 if (cbuf) {
1460 MacroAssembler _masm(cbuf);
1461 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1462 #ifndef PRODUCT
1463 } else {
1464 st->print("%s %s, %s\t# spill",
1465 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1466 Matcher::regName[dst_first],
1467 Matcher::regName[src_first]);
1468 #endif
1469 }
1470 } else {
1471 // 32-bit
1472 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1473 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1474 if (cbuf) {
1475 MacroAssembler _masm(cbuf);
1476 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1477 #ifndef PRODUCT
1478 } else {
1479 st->print("%s %s, %s\t# spill",
1480 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1481 Matcher::regName[dst_first],
1482 Matcher::regName[src_first]);
1483 #endif
1484 }
1485 }
1486 return 0;
1487 }
1488 }
1489
1490 assert(0," foo ");
1491 Unimplemented();
1492 return 0;
1493 }
1494
1495 #ifndef PRODUCT
1496 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1497 implementation(NULL, ra_, false, st);
1498 }
1499 #endif
1500
1501 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1502 implementation(&cbuf, ra_, false, NULL);
1503 }
1504
1505 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1506 return MachNode::size(ra_);
1507 }
1508
1509 //=============================================================================
1510 #ifndef PRODUCT
1511 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1512 {
1513 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1514 int reg = ra_->get_reg_first(this);
1515 st->print("leaq %s, [rsp + #%d]\t# box lock",
1516 Matcher::regName[reg], offset);
1517 }
1518 #endif
1519
1520 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1521 {
1522 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1523 int reg = ra_->get_encode(this);
1524 if (offset >= 0x80) {
1525 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1526 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1527 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1528 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1529 emit_d32(cbuf, offset);
1530 } else {
1531 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1532 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1533 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1534 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1535 emit_d8(cbuf, offset);
1536 }
1537 }
1538
1539 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1540 {
1541 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1542 return (offset < 0x80) ? 5 : 8; // REX
1543 }
1544
1545 //=============================================================================
1546 #ifndef PRODUCT
1547 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1548 {
1549 if (UseCompressedClassPointers) {
1550 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1551 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1552 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1553 } else {
1554 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1555 "# Inline cache check");
1556 }
1557 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1558 st->print_cr("\tnop\t# nops to align entry point");
1559 }
1560 #endif
1561
1562 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1563 {
1564 MacroAssembler masm(&cbuf);
1565 uint insts_size = cbuf.insts_size();
1566 if (UseCompressedClassPointers) {
1567 masm.load_klass(rscratch1, j_rarg0);
1568 masm.cmpptr(rax, rscratch1);
1569 } else {
1570 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1571 }
1572
1573 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1574
1575 /* WARNING these NOPs are critical so that verified entry point is properly
1576 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1577 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1578 if (OptoBreakpoint) {
1579 // Leave space for int3
1580 nops_cnt -= 1;
1581 }
1582 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1583 if (nops_cnt > 0)
1584 masm.nop(nops_cnt);
1585 }
1586
1587 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1588 {
1589 return MachNode::size(ra_); // too many variables; just compute it
1590 // the hard way
1591 }
1592
1593
1594 //=============================================================================
1595
1596 int Matcher::regnum_to_fpu_offset(int regnum)
1597 {
1598 return regnum - 32; // The FP registers are in the second chunk
1599 }
1600
1601 // This is UltraSparc specific, true just means we have fast l2f conversion
1602 const bool Matcher::convL2FSupported(void) {
1603 return true;
1604 }
1605
1606 // Is this branch offset short enough that a short branch can be used?
1607 //
1608 // NOTE: If the platform does not provide any short branch variants, then
1609 // this method should return false for offset 0.
1610 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1611 // The passed offset is relative to address of the branch.
1612 // On 86 a branch displacement is calculated relative to address
1613 // of a next instruction.
1614 offset -= br_size;
1615
1616 // the short version of jmpConUCF2 contains multiple branches,
1617 // making the reach slightly less
1618 if (rule == jmpConUCF2_rule)
1619 return (-126 <= offset && offset <= 125);
1620 return (-128 <= offset && offset <= 127);
1621 }
1622
1623 const bool Matcher::isSimpleConstant64(jlong value) {
1624 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1625 //return value == (int) value; // Cf. storeImmL and immL32.
1626
1627 // Probably always true, even if a temp register is required.
1628 return true;
1629 }
1630
1631 // The ecx parameter to rep stosq for the ClearArray node is in words.
1632 const bool Matcher::init_array_count_is_in_bytes = false;
1633
1634 // Threshold size for cleararray.
1635 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1636
1637 // No additional cost for CMOVL.
1638 const int Matcher::long_cmove_cost() { return 0; }
1639
1640 // No CMOVF/CMOVD with SSE2
1641 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1642
1643 // Does the CPU require late expand (see block.cpp for description of late expand)?
1644 const bool Matcher::require_postalloc_expand = false;
1645
1646 // Should the Matcher clone shifts on addressing modes, expecting them
1647 // to be subsumed into complex addressing expressions or compute them
1648 // into registers? True for Intel but false for most RISCs
1649 const bool Matcher::clone_shift_expressions = true;
1650
1651 // Do we need to mask the count passed to shift instructions or does
1652 // the cpu only look at the lower 5/6 bits anyway?
1653 const bool Matcher::need_masked_shift_count = false;
1654
1655 bool Matcher::narrow_oop_use_complex_address() {
1656 assert(UseCompressedOops, "only for compressed oops code");
1657 return (LogMinObjAlignmentInBytes <= 3);
1658 }
1659
1660 bool Matcher::narrow_klass_use_complex_address() {
1661 assert(UseCompressedClassPointers, "only for compressed klass code");
1662 return (LogKlassAlignmentInBytes <= 3);
1663 }
1664
1665 // Is it better to copy float constants, or load them directly from
1666 // memory? Intel can load a float constant from a direct address,
1667 // requiring no extra registers. Most RISCs will have to materialize
1668 // an address into a register first, so they would do better to copy
1669 // the constant from stack.
1670 const bool Matcher::rematerialize_float_constants = true; // XXX
1671
1672 // If CPU can load and store mis-aligned doubles directly then no
1673 // fixup is needed. Else we split the double into 2 integer pieces
1674 // and move it piece-by-piece. Only happens when passing doubles into
1675 // C code as the Java calling convention forces doubles to be aligned.
1676 const bool Matcher::misaligned_doubles_ok = true;
1677
1678 // No-op on amd64
1679 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1680
1681 // Advertise here if the CPU requires explicit rounding operations to
1682 // implement the UseStrictFP mode.
1683 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1684
1685 // Are floats conerted to double when stored to stack during deoptimization?
1686 // On x64 it is stored without convertion so we can use normal access.
1687 bool Matcher::float_in_double() { return false; }
1688
1689 // Do ints take an entire long register or just half?
1690 const bool Matcher::int_in_long = true;
1691
1692 // Return whether or not this register is ever used as an argument.
1693 // This function is used on startup to build the trampoline stubs in
1694 // generateOptoStub. Registers not mentioned will be killed by the VM
1695 // call in the trampoline, and arguments in those registers not be
1696 // available to the callee.
1697 bool Matcher::can_be_java_arg(int reg)
1698 {
1699 return
1700 reg == RDI_num || reg == RDI_H_num ||
1701 reg == RSI_num || reg == RSI_H_num ||
1702 reg == RDX_num || reg == RDX_H_num ||
1703 reg == RCX_num || reg == RCX_H_num ||
1704 reg == R8_num || reg == R8_H_num ||
1705 reg == R9_num || reg == R9_H_num ||
1706 reg == R12_num || reg == R12_H_num ||
1707 reg == XMM0_num || reg == XMM0b_num ||
1708 reg == XMM1_num || reg == XMM1b_num ||
1709 reg == XMM2_num || reg == XMM2b_num ||
1710 reg == XMM3_num || reg == XMM3b_num ||
1711 reg == XMM4_num || reg == XMM4b_num ||
1712 reg == XMM5_num || reg == XMM5b_num ||
1713 reg == XMM6_num || reg == XMM6b_num ||
1714 reg == XMM7_num || reg == XMM7b_num;
1715 }
1716
1717 bool Matcher::is_spillable_arg(int reg)
1718 {
1719 return can_be_java_arg(reg);
1720 }
1721
1722 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1723 // In 64 bit mode a code which use multiply when
1724 // devisor is constant is faster than hardware
1725 // DIV instruction (it uses MulHiL).
1726 return false;
1727 }
1728
1729 // Register for DIVI projection of divmodI
1730 RegMask Matcher::divI_proj_mask() {
1731 return INT_RAX_REG_mask();
1732 }
1733
1734 // Register for MODI projection of divmodI
1735 RegMask Matcher::modI_proj_mask() {
1736 return INT_RDX_REG_mask();
1737 }
1738
1739 // Register for DIVL projection of divmodL
1740 RegMask Matcher::divL_proj_mask() {
1741 return LONG_RAX_REG_mask();
1742 }
1743
1744 // Register for MODL projection of divmodL
1745 RegMask Matcher::modL_proj_mask() {
1746 return LONG_RDX_REG_mask();
1747 }
1748
1749 // Register for saving SP into on method handle invokes. Not used on x86_64.
1750 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1751 return NO_REG_mask();
1752 }
1753
1754 %}
1755
1756 //----------ENCODING BLOCK-----------------------------------------------------
1757 // This block specifies the encoding classes used by the compiler to
1758 // output byte streams. Encoding classes are parameterized macros
1759 // used by Machine Instruction Nodes in order to generate the bit
1760 // encoding of the instruction. Operands specify their base encoding
1761 // interface with the interface keyword. There are currently
1762 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1763 // COND_INTER. REG_INTER causes an operand to generate a function
1764 // which returns its register number when queried. CONST_INTER causes
1765 // an operand to generate a function which returns the value of the
1766 // constant when queried. MEMORY_INTER causes an operand to generate
1767 // four functions which return the Base Register, the Index Register,
1768 // the Scale Value, and the Offset Value of the operand when queried.
1769 // COND_INTER causes an operand to generate six functions which return
1770 // the encoding code (ie - encoding bits for the instruction)
1771 // associated with each basic boolean condition for a conditional
1772 // instruction.
1773 //
1774 // Instructions specify two basic values for encoding. Again, a
1775 // function is available to check if the constant displacement is an
1776 // oop. They use the ins_encode keyword to specify their encoding
1777 // classes (which must be a sequence of enc_class names, and their
1778 // parameters, specified in the encoding block), and they use the
1779 // opcode keyword to specify, in order, their primary, secondary, and
1780 // tertiary opcode. Only the opcode sections which a particular
1781 // instruction needs for encoding need to be specified.
1782 encode %{
1783 // Build emit functions for each basic byte or larger field in the
1784 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1785 // from C++ code in the enc_class source block. Emit functions will
1786 // live in the main source block for now. In future, we can
1787 // generalize this by adding a syntax that specifies the sizes of
1788 // fields in an order, so that the adlc can build the emit functions
1789 // automagically
1790
1791 // Emit primary opcode
1792 enc_class OpcP
1793 %{
1794 emit_opcode(cbuf, $primary);
1795 %}
1796
1797 // Emit secondary opcode
1798 enc_class OpcS
1799 %{
1800 emit_opcode(cbuf, $secondary);
1801 %}
1802
1803 // Emit tertiary opcode
1804 enc_class OpcT
1805 %{
1806 emit_opcode(cbuf, $tertiary);
1807 %}
1808
1809 // Emit opcode directly
1810 enc_class Opcode(immI d8)
1811 %{
1812 emit_opcode(cbuf, $d8$$constant);
1813 %}
1814
1815 // Emit size prefix
1816 enc_class SizePrefix
1817 %{
1818 emit_opcode(cbuf, 0x66);
1819 %}
1820
1821 enc_class reg(rRegI reg)
1822 %{
1823 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1824 %}
1825
1826 enc_class reg_reg(rRegI dst, rRegI src)
1827 %{
1828 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1829 %}
1830
1831 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1832 %{
1833 emit_opcode(cbuf, $opcode$$constant);
1834 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1835 %}
1836
1837 enc_class cdql_enc(no_rax_rdx_RegI div)
1838 %{
1839 // Full implementation of Java idiv and irem; checks for
1840 // special case as described in JVM spec., p.243 & p.271.
1841 //
1842 // normal case special case
1843 //
1844 // input : rax: dividend min_int
1845 // reg: divisor -1
1846 //
1847 // output: rax: quotient (= rax idiv reg) min_int
1848 // rdx: remainder (= rax irem reg) 0
1849 //
1850 // Code sequnce:
1851 //
1852 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1853 // 5: 75 07/08 jne e <normal>
1854 // 7: 33 d2 xor %edx,%edx
1855 // [div >= 8 -> offset + 1]
1856 // [REX_B]
1857 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1858 // c: 74 03/04 je 11 <done>
1859 // 000000000000000e <normal>:
1860 // e: 99 cltd
1861 // [div >= 8 -> offset + 1]
1862 // [REX_B]
1863 // f: f7 f9 idiv $div
1864 // 0000000000000011 <done>:
1865
1866 // cmp $0x80000000,%eax
1867 emit_opcode(cbuf, 0x3d);
1868 emit_d8(cbuf, 0x00);
1869 emit_d8(cbuf, 0x00);
1870 emit_d8(cbuf, 0x00);
1871 emit_d8(cbuf, 0x80);
1872
1873 // jne e <normal>
1874 emit_opcode(cbuf, 0x75);
1875 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1876
1877 // xor %edx,%edx
1878 emit_opcode(cbuf, 0x33);
1879 emit_d8(cbuf, 0xD2);
1880
1881 // cmp $0xffffffffffffffff,%ecx
1882 if ($div$$reg >= 8) {
1883 emit_opcode(cbuf, Assembler::REX_B);
1884 }
1885 emit_opcode(cbuf, 0x83);
1886 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1887 emit_d8(cbuf, 0xFF);
1888
1889 // je 11 <done>
1890 emit_opcode(cbuf, 0x74);
1891 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1892
1893 // <normal>
1894 // cltd
1895 emit_opcode(cbuf, 0x99);
1896
1897 // idivl (note: must be emitted by the user of this rule)
1898 // <done>
1899 %}
1900
1901 enc_class cdqq_enc(no_rax_rdx_RegL div)
1902 %{
1903 // Full implementation of Java ldiv and lrem; checks for
1904 // special case as described in JVM spec., p.243 & p.271.
1905 //
1906 // normal case special case
1907 //
1908 // input : rax: dividend min_long
1909 // reg: divisor -1
1910 //
1911 // output: rax: quotient (= rax idiv reg) min_long
1912 // rdx: remainder (= rax irem reg) 0
1913 //
1914 // Code sequnce:
1915 //
1916 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1917 // 7: 00 00 80
1918 // a: 48 39 d0 cmp %rdx,%rax
1919 // d: 75 08 jne 17 <normal>
1920 // f: 33 d2 xor %edx,%edx
1921 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1922 // 15: 74 05 je 1c <done>
1923 // 0000000000000017 <normal>:
1924 // 17: 48 99 cqto
1925 // 19: 48 f7 f9 idiv $div
1926 // 000000000000001c <done>:
1927
1928 // mov $0x8000000000000000,%rdx
1929 emit_opcode(cbuf, Assembler::REX_W);
1930 emit_opcode(cbuf, 0xBA);
1931 emit_d8(cbuf, 0x00);
1932 emit_d8(cbuf, 0x00);
1933 emit_d8(cbuf, 0x00);
1934 emit_d8(cbuf, 0x00);
1935 emit_d8(cbuf, 0x00);
1936 emit_d8(cbuf, 0x00);
1937 emit_d8(cbuf, 0x00);
1938 emit_d8(cbuf, 0x80);
1939
1940 // cmp %rdx,%rax
1941 emit_opcode(cbuf, Assembler::REX_W);
1942 emit_opcode(cbuf, 0x39);
1943 emit_d8(cbuf, 0xD0);
1944
1945 // jne 17 <normal>
1946 emit_opcode(cbuf, 0x75);
1947 emit_d8(cbuf, 0x08);
1948
1949 // xor %edx,%edx
1950 emit_opcode(cbuf, 0x33);
1951 emit_d8(cbuf, 0xD2);
1952
1953 // cmp $0xffffffffffffffff,$div
1954 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1955 emit_opcode(cbuf, 0x83);
1956 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1957 emit_d8(cbuf, 0xFF);
1958
1959 // je 1e <done>
1960 emit_opcode(cbuf, 0x74);
1961 emit_d8(cbuf, 0x05);
1962
1963 // <normal>
1964 // cqto
1965 emit_opcode(cbuf, Assembler::REX_W);
1966 emit_opcode(cbuf, 0x99);
1967
1968 // idivq (note: must be emitted by the user of this rule)
1969 // <done>
1970 %}
1971
1972 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1973 enc_class OpcSE(immI imm)
1974 %{
1975 // Emit primary opcode and set sign-extend bit
1976 // Check for 8-bit immediate, and set sign extend bit in opcode
1977 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1978 emit_opcode(cbuf, $primary | 0x02);
1979 } else {
1980 // 32-bit immediate
1981 emit_opcode(cbuf, $primary);
1982 }
1983 %}
1984
1985 enc_class OpcSErm(rRegI dst, immI imm)
1986 %{
1987 // OpcSEr/m
1988 int dstenc = $dst$$reg;
1989 if (dstenc >= 8) {
1990 emit_opcode(cbuf, Assembler::REX_B);
1991 dstenc -= 8;
1992 }
1993 // Emit primary opcode and set sign-extend bit
1994 // Check for 8-bit immediate, and set sign extend bit in opcode
1995 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1996 emit_opcode(cbuf, $primary | 0x02);
1997 } else {
1998 // 32-bit immediate
1999 emit_opcode(cbuf, $primary);
2000 }
2001 // Emit r/m byte with secondary opcode, after primary opcode.
2002 emit_rm(cbuf, 0x3, $secondary, dstenc);
2003 %}
2004
2005 enc_class OpcSErm_wide(rRegL dst, immI imm)
2006 %{
2007 // OpcSEr/m
2008 int dstenc = $dst$$reg;
2009 if (dstenc < 8) {
2010 emit_opcode(cbuf, Assembler::REX_W);
2011 } else {
2012 emit_opcode(cbuf, Assembler::REX_WB);
2013 dstenc -= 8;
2014 }
2015 // Emit primary opcode and set sign-extend bit
2016 // Check for 8-bit immediate, and set sign extend bit in opcode
2017 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2018 emit_opcode(cbuf, $primary | 0x02);
2019 } else {
2020 // 32-bit immediate
2021 emit_opcode(cbuf, $primary);
2022 }
2023 // Emit r/m byte with secondary opcode, after primary opcode.
2024 emit_rm(cbuf, 0x3, $secondary, dstenc);
2025 %}
2026
2027 enc_class Con8or32(immI imm)
2028 %{
2029 // Check for 8-bit immediate, and set sign extend bit in opcode
2030 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2031 $$$emit8$imm$$constant;
2032 } else {
2033 // 32-bit immediate
2034 $$$emit32$imm$$constant;
2035 }
2036 %}
2037
2038 enc_class opc2_reg(rRegI dst)
2039 %{
2040 // BSWAP
2041 emit_cc(cbuf, $secondary, $dst$$reg);
2042 %}
2043
2044 enc_class opc3_reg(rRegI dst)
2045 %{
2046 // BSWAP
2047 emit_cc(cbuf, $tertiary, $dst$$reg);
2048 %}
2049
2050 enc_class reg_opc(rRegI div)
2051 %{
2052 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2053 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2054 %}
2055
2056 enc_class enc_cmov(cmpOp cop)
2057 %{
2058 // CMOV
2059 $$$emit8$primary;
2060 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2061 %}
2062
2063 enc_class enc_PartialSubtypeCheck()
2064 %{
2065 Register Rrdi = as_Register(RDI_enc); // result register
2066 Register Rrax = as_Register(RAX_enc); // super class
2067 Register Rrcx = as_Register(RCX_enc); // killed
2068 Register Rrsi = as_Register(RSI_enc); // sub class
2069 Label miss;
2070 const bool set_cond_codes = true;
2071
2072 MacroAssembler _masm(&cbuf);
2073 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2074 NULL, &miss,
2075 /*set_cond_codes:*/ true);
2076 if ($primary) {
2077 __ xorptr(Rrdi, Rrdi);
2078 }
2079 __ bind(miss);
2080 %}
2081
2082 enc_class clear_avx %{
2083 debug_only(int off0 = cbuf.insts_size());
2084 if (ra_->C->max_vector_size() > 16) {
2085 // Clear upper bits of YMM registers when current compiled code uses
2086 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2087 MacroAssembler _masm(&cbuf);
2088 __ vzeroupper();
2089 }
2090 debug_only(int off1 = cbuf.insts_size());
2091 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2092 %}
2093
2094 enc_class Java_To_Runtime(method meth) %{
2095 // No relocation needed
2096 MacroAssembler _masm(&cbuf);
2097 __ mov64(r10, (int64_t) $meth$$method);
2098 __ call(r10);
2099 %}
2100
2101 enc_class Java_To_Interpreter(method meth)
2102 %{
2103 // CALL Java_To_Interpreter
2104 // This is the instruction starting address for relocation info.
2105 cbuf.set_insts_mark();
2106 $$$emit8$primary;
2107 // CALL directly to the runtime
2108 emit_d32_reloc(cbuf,
2109 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2110 runtime_call_Relocation::spec(),
2111 RELOC_DISP32);
2112 %}
2113
2114 enc_class Java_Static_Call(method meth)
2115 %{
2116 // JAVA STATIC CALL
2117 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2118 // determine who we intended to call.
2119 cbuf.set_insts_mark();
2120 $$$emit8$primary;
2121
2122 if (!_method) {
2123 emit_d32_reloc(cbuf,
2124 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2125 runtime_call_Relocation::spec(),
2126 RELOC_DISP32);
2127 } else if (_optimized_virtual) {
2128 emit_d32_reloc(cbuf,
2129 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2130 opt_virtual_call_Relocation::spec(),
2131 RELOC_DISP32);
2132 } else {
2133 emit_d32_reloc(cbuf,
2134 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2135 static_call_Relocation::spec(),
2136 RELOC_DISP32);
2137 }
2138 if (_method) {
2139 // Emit stubs for static call.
2140 address mark = cbuf.insts_mark();
2141 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2142 if (stub == NULL) {
2143 ciEnv::current()->record_failure("CodeCache is full");
2144 return;
2145 }
2146 }
2147 %}
2148
2149 enc_class Java_Dynamic_Call(method meth) %{
2150 MacroAssembler _masm(&cbuf);
2151 __ ic_call((address)$meth$$method);
2152 %}
2153
2154 enc_class Java_Compiled_Call(method meth)
2155 %{
2156 // JAVA COMPILED CALL
2157 int disp = in_bytes(Method:: from_compiled_offset());
2158
2159 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2160 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2161
2162 // callq *disp(%rax)
2163 cbuf.set_insts_mark();
2164 $$$emit8$primary;
2165 if (disp < 0x80) {
2166 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2167 emit_d8(cbuf, disp); // Displacement
2168 } else {
2169 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2170 emit_d32(cbuf, disp); // Displacement
2171 }
2172 %}
2173
2174 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2175 %{
2176 // SAL, SAR, SHR
2177 int dstenc = $dst$$reg;
2178 if (dstenc >= 8) {
2179 emit_opcode(cbuf, Assembler::REX_B);
2180 dstenc -= 8;
2181 }
2182 $$$emit8$primary;
2183 emit_rm(cbuf, 0x3, $secondary, dstenc);
2184 $$$emit8$shift$$constant;
2185 %}
2186
2187 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2188 %{
2189 // SAL, SAR, SHR
2190 int dstenc = $dst$$reg;
2191 if (dstenc < 8) {
2192 emit_opcode(cbuf, Assembler::REX_W);
2193 } else {
2194 emit_opcode(cbuf, Assembler::REX_WB);
2195 dstenc -= 8;
2196 }
2197 $$$emit8$primary;
2198 emit_rm(cbuf, 0x3, $secondary, dstenc);
2199 $$$emit8$shift$$constant;
2200 %}
2201
2202 enc_class load_immI(rRegI dst, immI src)
2203 %{
2204 int dstenc = $dst$$reg;
2205 if (dstenc >= 8) {
2206 emit_opcode(cbuf, Assembler::REX_B);
2207 dstenc -= 8;
2208 }
2209 emit_opcode(cbuf, 0xB8 | dstenc);
2210 $$$emit32$src$$constant;
2211 %}
2212
2213 enc_class load_immL(rRegL dst, immL src)
2214 %{
2215 int dstenc = $dst$$reg;
2216 if (dstenc < 8) {
2217 emit_opcode(cbuf, Assembler::REX_W);
2218 } else {
2219 emit_opcode(cbuf, Assembler::REX_WB);
2220 dstenc -= 8;
2221 }
2222 emit_opcode(cbuf, 0xB8 | dstenc);
2223 emit_d64(cbuf, $src$$constant);
2224 %}
2225
2226 enc_class load_immUL32(rRegL dst, immUL32 src)
2227 %{
2228 // same as load_immI, but this time we care about zeroes in the high word
2229 int dstenc = $dst$$reg;
2230 if (dstenc >= 8) {
2231 emit_opcode(cbuf, Assembler::REX_B);
2232 dstenc -= 8;
2233 }
2234 emit_opcode(cbuf, 0xB8 | dstenc);
2235 $$$emit32$src$$constant;
2236 %}
2237
2238 enc_class load_immL32(rRegL dst, immL32 src)
2239 %{
2240 int dstenc = $dst$$reg;
2241 if (dstenc < 8) {
2242 emit_opcode(cbuf, Assembler::REX_W);
2243 } else {
2244 emit_opcode(cbuf, Assembler::REX_WB);
2245 dstenc -= 8;
2246 }
2247 emit_opcode(cbuf, 0xC7);
2248 emit_rm(cbuf, 0x03, 0x00, dstenc);
2249 $$$emit32$src$$constant;
2250 %}
2251
2252 enc_class load_immP31(rRegP dst, immP32 src)
2253 %{
2254 // same as load_immI, but this time we care about zeroes in the high word
2255 int dstenc = $dst$$reg;
2256 if (dstenc >= 8) {
2257 emit_opcode(cbuf, Assembler::REX_B);
2258 dstenc -= 8;
2259 }
2260 emit_opcode(cbuf, 0xB8 | dstenc);
2261 $$$emit32$src$$constant;
2262 %}
2263
2264 enc_class load_immP(rRegP dst, immP src)
2265 %{
2266 int dstenc = $dst$$reg;
2267 if (dstenc < 8) {
2268 emit_opcode(cbuf, Assembler::REX_W);
2269 } else {
2270 emit_opcode(cbuf, Assembler::REX_WB);
2271 dstenc -= 8;
2272 }
2273 emit_opcode(cbuf, 0xB8 | dstenc);
2274 // This next line should be generated from ADLC
2275 if ($src->constant_reloc() != relocInfo::none) {
2276 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2277 } else {
2278 emit_d64(cbuf, $src$$constant);
2279 }
2280 %}
2281
2282 enc_class Con32(immI src)
2283 %{
2284 // Output immediate
2285 $$$emit32$src$$constant;
2286 %}
2287
2288 enc_class Con32F_as_bits(immF src)
2289 %{
2290 // Output Float immediate bits
2291 jfloat jf = $src$$constant;
2292 jint jf_as_bits = jint_cast(jf);
2293 emit_d32(cbuf, jf_as_bits);
2294 %}
2295
2296 enc_class Con16(immI src)
2297 %{
2298 // Output immediate
2299 $$$emit16$src$$constant;
2300 %}
2301
2302 // How is this different from Con32??? XXX
2303 enc_class Con_d32(immI src)
2304 %{
2305 emit_d32(cbuf,$src$$constant);
2306 %}
2307
2308 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2309 // Output immediate memory reference
2310 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2311 emit_d32(cbuf, 0x00);
2312 %}
2313
2314 enc_class lock_prefix()
2315 %{
2316 if (os::is_MP()) {
2317 emit_opcode(cbuf, 0xF0); // lock
2318 }
2319 %}
2320
2321 enc_class REX_mem(memory mem)
2322 %{
2323 if ($mem$$base >= 8) {
2324 if ($mem$$index < 8) {
2325 emit_opcode(cbuf, Assembler::REX_B);
2326 } else {
2327 emit_opcode(cbuf, Assembler::REX_XB);
2328 }
2329 } else {
2330 if ($mem$$index >= 8) {
2331 emit_opcode(cbuf, Assembler::REX_X);
2332 }
2333 }
2334 %}
2335
2336 enc_class REX_mem_wide(memory mem)
2337 %{
2338 if ($mem$$base >= 8) {
2339 if ($mem$$index < 8) {
2340 emit_opcode(cbuf, Assembler::REX_WB);
2341 } else {
2342 emit_opcode(cbuf, Assembler::REX_WXB);
2343 }
2344 } else {
2345 if ($mem$$index < 8) {
2346 emit_opcode(cbuf, Assembler::REX_W);
2347 } else {
2348 emit_opcode(cbuf, Assembler::REX_WX);
2349 }
2350 }
2351 %}
2352
2353 // for byte regs
2354 enc_class REX_breg(rRegI reg)
2355 %{
2356 if ($reg$$reg >= 4) {
2357 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2358 }
2359 %}
2360
2361 // for byte regs
2362 enc_class REX_reg_breg(rRegI dst, rRegI src)
2363 %{
2364 if ($dst$$reg < 8) {
2365 if ($src$$reg >= 4) {
2366 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2367 }
2368 } else {
2369 if ($src$$reg < 8) {
2370 emit_opcode(cbuf, Assembler::REX_R);
2371 } else {
2372 emit_opcode(cbuf, Assembler::REX_RB);
2373 }
2374 }
2375 %}
2376
2377 // for byte regs
2378 enc_class REX_breg_mem(rRegI reg, memory mem)
2379 %{
2380 if ($reg$$reg < 8) {
2381 if ($mem$$base < 8) {
2382 if ($mem$$index >= 8) {
2383 emit_opcode(cbuf, Assembler::REX_X);
2384 } else if ($reg$$reg >= 4) {
2385 emit_opcode(cbuf, Assembler::REX);
2386 }
2387 } else {
2388 if ($mem$$index < 8) {
2389 emit_opcode(cbuf, Assembler::REX_B);
2390 } else {
2391 emit_opcode(cbuf, Assembler::REX_XB);
2392 }
2393 }
2394 } else {
2395 if ($mem$$base < 8) {
2396 if ($mem$$index < 8) {
2397 emit_opcode(cbuf, Assembler::REX_R);
2398 } else {
2399 emit_opcode(cbuf, Assembler::REX_RX);
2400 }
2401 } else {
2402 if ($mem$$index < 8) {
2403 emit_opcode(cbuf, Assembler::REX_RB);
2404 } else {
2405 emit_opcode(cbuf, Assembler::REX_RXB);
2406 }
2407 }
2408 }
2409 %}
2410
2411 enc_class REX_reg(rRegI reg)
2412 %{
2413 if ($reg$$reg >= 8) {
2414 emit_opcode(cbuf, Assembler::REX_B);
2415 }
2416 %}
2417
2418 enc_class REX_reg_wide(rRegI reg)
2419 %{
2420 if ($reg$$reg < 8) {
2421 emit_opcode(cbuf, Assembler::REX_W);
2422 } else {
2423 emit_opcode(cbuf, Assembler::REX_WB);
2424 }
2425 %}
2426
2427 enc_class REX_reg_reg(rRegI dst, rRegI src)
2428 %{
2429 if ($dst$$reg < 8) {
2430 if ($src$$reg >= 8) {
2431 emit_opcode(cbuf, Assembler::REX_B);
2432 }
2433 } else {
2434 if ($src$$reg < 8) {
2435 emit_opcode(cbuf, Assembler::REX_R);
2436 } else {
2437 emit_opcode(cbuf, Assembler::REX_RB);
2438 }
2439 }
2440 %}
2441
2442 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2443 %{
2444 if ($dst$$reg < 8) {
2445 if ($src$$reg < 8) {
2446 emit_opcode(cbuf, Assembler::REX_W);
2447 } else {
2448 emit_opcode(cbuf, Assembler::REX_WB);
2449 }
2450 } else {
2451 if ($src$$reg < 8) {
2452 emit_opcode(cbuf, Assembler::REX_WR);
2453 } else {
2454 emit_opcode(cbuf, Assembler::REX_WRB);
2455 }
2456 }
2457 %}
2458
2459 enc_class REX_reg_mem(rRegI reg, memory mem)
2460 %{
2461 if ($reg$$reg < 8) {
2462 if ($mem$$base < 8) {
2463 if ($mem$$index >= 8) {
2464 emit_opcode(cbuf, Assembler::REX_X);
2465 }
2466 } else {
2467 if ($mem$$index < 8) {
2468 emit_opcode(cbuf, Assembler::REX_B);
2469 } else {
2470 emit_opcode(cbuf, Assembler::REX_XB);
2471 }
2472 }
2473 } else {
2474 if ($mem$$base < 8) {
2475 if ($mem$$index < 8) {
2476 emit_opcode(cbuf, Assembler::REX_R);
2477 } else {
2478 emit_opcode(cbuf, Assembler::REX_RX);
2479 }
2480 } else {
2481 if ($mem$$index < 8) {
2482 emit_opcode(cbuf, Assembler::REX_RB);
2483 } else {
2484 emit_opcode(cbuf, Assembler::REX_RXB);
2485 }
2486 }
2487 }
2488 %}
2489
2490 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2491 %{
2492 if ($reg$$reg < 8) {
2493 if ($mem$$base < 8) {
2494 if ($mem$$index < 8) {
2495 emit_opcode(cbuf, Assembler::REX_W);
2496 } else {
2497 emit_opcode(cbuf, Assembler::REX_WX);
2498 }
2499 } else {
2500 if ($mem$$index < 8) {
2501 emit_opcode(cbuf, Assembler::REX_WB);
2502 } else {
2503 emit_opcode(cbuf, Assembler::REX_WXB);
2504 }
2505 }
2506 } else {
2507 if ($mem$$base < 8) {
2508 if ($mem$$index < 8) {
2509 emit_opcode(cbuf, Assembler::REX_WR);
2510 } else {
2511 emit_opcode(cbuf, Assembler::REX_WRX);
2512 }
2513 } else {
2514 if ($mem$$index < 8) {
2515 emit_opcode(cbuf, Assembler::REX_WRB);
2516 } else {
2517 emit_opcode(cbuf, Assembler::REX_WRXB);
2518 }
2519 }
2520 }
2521 %}
2522
2523 enc_class reg_mem(rRegI ereg, memory mem)
2524 %{
2525 // High registers handle in encode_RegMem
2526 int reg = $ereg$$reg;
2527 int base = $mem$$base;
2528 int index = $mem$$index;
2529 int scale = $mem$$scale;
2530 int disp = $mem$$disp;
2531 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2532
2533 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2534 %}
2535
2536 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2537 %{
2538 int rm_byte_opcode = $rm_opcode$$constant;
2539
2540 // High registers handle in encode_RegMem
2541 int base = $mem$$base;
2542 int index = $mem$$index;
2543 int scale = $mem$$scale;
2544 int displace = $mem$$disp;
2545
2546 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2547 // working with static
2548 // globals
2549 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2550 disp_reloc);
2551 %}
2552
2553 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2554 %{
2555 int reg_encoding = $dst$$reg;
2556 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2557 int index = 0x04; // 0x04 indicates no index
2558 int scale = 0x00; // 0x00 indicates no scale
2559 int displace = $src1$$constant; // 0x00 indicates no displacement
2560 relocInfo::relocType disp_reloc = relocInfo::none;
2561 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2562 disp_reloc);
2563 %}
2564
2565 enc_class neg_reg(rRegI dst)
2566 %{
2567 int dstenc = $dst$$reg;
2568 if (dstenc >= 8) {
2569 emit_opcode(cbuf, Assembler::REX_B);
2570 dstenc -= 8;
2571 }
2572 // NEG $dst
2573 emit_opcode(cbuf, 0xF7);
2574 emit_rm(cbuf, 0x3, 0x03, dstenc);
2575 %}
2576
2577 enc_class neg_reg_wide(rRegI dst)
2578 %{
2579 int dstenc = $dst$$reg;
2580 if (dstenc < 8) {
2581 emit_opcode(cbuf, Assembler::REX_W);
2582 } else {
2583 emit_opcode(cbuf, Assembler::REX_WB);
2584 dstenc -= 8;
2585 }
2586 // NEG $dst
2587 emit_opcode(cbuf, 0xF7);
2588 emit_rm(cbuf, 0x3, 0x03, dstenc);
2589 %}
2590
2591 enc_class setLT_reg(rRegI dst)
2592 %{
2593 int dstenc = $dst$$reg;
2594 if (dstenc >= 8) {
2595 emit_opcode(cbuf, Assembler::REX_B);
2596 dstenc -= 8;
2597 } else if (dstenc >= 4) {
2598 emit_opcode(cbuf, Assembler::REX);
2599 }
2600 // SETLT $dst
2601 emit_opcode(cbuf, 0x0F);
2602 emit_opcode(cbuf, 0x9C);
2603 emit_rm(cbuf, 0x3, 0x0, dstenc);
2604 %}
2605
2606 enc_class setNZ_reg(rRegI dst)
2607 %{
2608 int dstenc = $dst$$reg;
2609 if (dstenc >= 8) {
2610 emit_opcode(cbuf, Assembler::REX_B);
2611 dstenc -= 8;
2612 } else if (dstenc >= 4) {
2613 emit_opcode(cbuf, Assembler::REX);
2614 }
2615 // SETNZ $dst
2616 emit_opcode(cbuf, 0x0F);
2617 emit_opcode(cbuf, 0x95);
2618 emit_rm(cbuf, 0x3, 0x0, dstenc);
2619 %}
2620
2621
2622 // Compare the lonogs and set -1, 0, or 1 into dst
2623 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2624 %{
2625 int src1enc = $src1$$reg;
2626 int src2enc = $src2$$reg;
2627 int dstenc = $dst$$reg;
2628
2629 // cmpq $src1, $src2
2630 if (src1enc < 8) {
2631 if (src2enc < 8) {
2632 emit_opcode(cbuf, Assembler::REX_W);
2633 } else {
2634 emit_opcode(cbuf, Assembler::REX_WB);
2635 }
2636 } else {
2637 if (src2enc < 8) {
2638 emit_opcode(cbuf, Assembler::REX_WR);
2639 } else {
2640 emit_opcode(cbuf, Assembler::REX_WRB);
2641 }
2642 }
2643 emit_opcode(cbuf, 0x3B);
2644 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2645
2646 // movl $dst, -1
2647 if (dstenc >= 8) {
2648 emit_opcode(cbuf, Assembler::REX_B);
2649 }
2650 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2651 emit_d32(cbuf, -1);
2652
2653 // jl,s done
2654 emit_opcode(cbuf, 0x7C);
2655 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2656
2657 // setne $dst
2658 if (dstenc >= 4) {
2659 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2660 }
2661 emit_opcode(cbuf, 0x0F);
2662 emit_opcode(cbuf, 0x95);
2663 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2664
2665 // movzbl $dst, $dst
2666 if (dstenc >= 4) {
2667 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2668 }
2669 emit_opcode(cbuf, 0x0F);
2670 emit_opcode(cbuf, 0xB6);
2671 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2672 %}
2673
2674 enc_class Push_ResultXD(regD dst) %{
2675 MacroAssembler _masm(&cbuf);
2676 __ fstp_d(Address(rsp, 0));
2677 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2678 __ addptr(rsp, 8);
2679 %}
2680
2681 enc_class Push_SrcXD(regD src) %{
2682 MacroAssembler _masm(&cbuf);
2683 __ subptr(rsp, 8);
2684 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2685 __ fld_d(Address(rsp, 0));
2686 %}
2687
2688
2689 enc_class enc_rethrow()
2690 %{
2691 cbuf.set_insts_mark();
2692 emit_opcode(cbuf, 0xE9); // jmp entry
2693 emit_d32_reloc(cbuf,
2694 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2695 runtime_call_Relocation::spec(),
2696 RELOC_DISP32);
2697 %}
2698
2699 %}
2700
2701
2702
2703 //----------FRAME--------------------------------------------------------------
2704 // Definition of frame structure and management information.
2705 //
2706 // S T A C K L A Y O U T Allocators stack-slot number
2707 // | (to get allocators register number
2708 // G Owned by | | v add OptoReg::stack0())
2709 // r CALLER | |
2710 // o | +--------+ pad to even-align allocators stack-slot
2711 // w V | pad0 | numbers; owned by CALLER
2712 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2713 // h ^ | in | 5
2714 // | | args | 4 Holes in incoming args owned by SELF
2715 // | | | | 3
2716 // | | +--------+
2717 // V | | old out| Empty on Intel, window on Sparc
2718 // | old |preserve| Must be even aligned.
2719 // | SP-+--------+----> Matcher::_old_SP, even aligned
2720 // | | in | 3 area for Intel ret address
2721 // Owned by |preserve| Empty on Sparc.
2722 // SELF +--------+
2723 // | | pad2 | 2 pad to align old SP
2724 // | +--------+ 1
2725 // | | locks | 0
2726 // | +--------+----> OptoReg::stack0(), even aligned
2727 // | | pad1 | 11 pad to align new SP
2728 // | +--------+
2729 // | | | 10
2730 // | | spills | 9 spills
2731 // V | | 8 (pad0 slot for callee)
2732 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2733 // ^ | out | 7
2734 // | | args | 6 Holes in outgoing args owned by CALLEE
2735 // Owned by +--------+
2736 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2737 // | new |preserve| Must be even-aligned.
2738 // | SP-+--------+----> Matcher::_new_SP, even aligned
2739 // | | |
2740 //
2741 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2742 // known from SELF's arguments and the Java calling convention.
2743 // Region 6-7 is determined per call site.
2744 // Note 2: If the calling convention leaves holes in the incoming argument
2745 // area, those holes are owned by SELF. Holes in the outgoing area
2746 // are owned by the CALLEE. Holes should not be nessecary in the
2747 // incoming area, as the Java calling convention is completely under
2748 // the control of the AD file. Doubles can be sorted and packed to
2749 // avoid holes. Holes in the outgoing arguments may be nessecary for
2750 // varargs C calling conventions.
2751 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2752 // even aligned with pad0 as needed.
2753 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2754 // region 6-11 is even aligned; it may be padded out more so that
2755 // the region from SP to FP meets the minimum stack alignment.
2756 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2757 // alignment. Region 11, pad1, may be dynamically extended so that
2758 // SP meets the minimum alignment.
2759
2760 frame
2761 %{
2762 // What direction does stack grow in (assumed to be same for C & Java)
2763 stack_direction(TOWARDS_LOW);
2764
2765 // These three registers define part of the calling convention
2766 // between compiled code and the interpreter.
2767 inline_cache_reg(RAX); // Inline Cache Register
2768 interpreter_method_oop_reg(RBX); // Method Oop Register when
2769 // calling interpreter
2770
2771 // Optional: name the operand used by cisc-spilling to access
2772 // [stack_pointer + offset]
2773 cisc_spilling_operand_name(indOffset32);
2774
2775 // Number of stack slots consumed by locking an object
2776 sync_stack_slots(2);
2777
2778 // Compiled code's Frame Pointer
2779 frame_pointer(RSP);
2780
2781 // Interpreter stores its frame pointer in a register which is
2782 // stored to the stack by I2CAdaptors.
2783 // I2CAdaptors convert from interpreted java to compiled java.
2784 interpreter_frame_pointer(RBP);
2785
2786 // Stack alignment requirement
2787 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2788
2789 // Number of stack slots between incoming argument block and the start of
2790 // a new frame. The PROLOG must add this many slots to the stack. The
2791 // EPILOG must remove this many slots. amd64 needs two slots for
2792 // return address.
2793 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2794
2795 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2796 // for calls to C. Supports the var-args backing area for register parms.
2797 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2798
2799 // The after-PROLOG location of the return address. Location of
2800 // return address specifies a type (REG or STACK) and a number
2801 // representing the register number (i.e. - use a register name) or
2802 // stack slot.
2803 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2804 // Otherwise, it is above the locks and verification slot and alignment word
2805 return_addr(STACK - 2 +
2806 round_to((Compile::current()->in_preserve_stack_slots() +
2807 Compile::current()->fixed_slots()),
2808 stack_alignment_in_slots()));
2809
2810 // Body of function which returns an integer array locating
2811 // arguments either in registers or in stack slots. Passed an array
2812 // of ideal registers called "sig" and a "length" count. Stack-slot
2813 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2814 // arguments for a CALLEE. Incoming stack arguments are
2815 // automatically biased by the preserve_stack_slots field above.
2816
2817 calling_convention
2818 %{
2819 // No difference between ingoing/outgoing just pass false
2820 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2821 %}
2822
2823 c_calling_convention
2824 %{
2825 // This is obviously always outgoing
2826 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2827 %}
2828
2829 // Location of compiled Java return values. Same as C for now.
2830 return_value
2831 %{
2832 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2833 "only return normal values");
2834
2835 static const int lo[Op_RegL + 1] = {
2836 0,
2837 0,
2838 RAX_num, // Op_RegN
2839 RAX_num, // Op_RegI
2840 RAX_num, // Op_RegP
2841 XMM0_num, // Op_RegF
2842 XMM0_num, // Op_RegD
2843 RAX_num // Op_RegL
2844 };
2845 static const int hi[Op_RegL + 1] = {
2846 0,
2847 0,
2848 OptoReg::Bad, // Op_RegN
2849 OptoReg::Bad, // Op_RegI
2850 RAX_H_num, // Op_RegP
2851 OptoReg::Bad, // Op_RegF
2852 XMM0b_num, // Op_RegD
2853 RAX_H_num // Op_RegL
2854 };
2855 // Excluded flags and vector registers.
2856 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2857 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2858 %}
2859 %}
2860
2861 //----------ATTRIBUTES---------------------------------------------------------
2862 //----------Operand Attributes-------------------------------------------------
2863 op_attrib op_cost(0); // Required cost attribute
2864
2865 //----------Instruction Attributes---------------------------------------------
2866 ins_attrib ins_cost(100); // Required cost attribute
2867 ins_attrib ins_size(8); // Required size attribute (in bits)
2868 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2869 // a non-matching short branch variant
2870 // of some long branch?
2871 ins_attrib ins_alignment(1); // Required alignment attribute (must
2872 // be a power of 2) specifies the
2873 // alignment that some part of the
2874 // instruction (not necessarily the
2875 // start) requires. If > 1, a
2876 // compute_padding() function must be
2877 // provided for the instruction
2878
2879 //----------OPERANDS-----------------------------------------------------------
2880 // Operand definitions must precede instruction definitions for correct parsing
2881 // in the ADLC because operands constitute user defined types which are used in
2882 // instruction definitions.
2883
2884 //----------Simple Operands----------------------------------------------------
2885 // Immediate Operands
2886 // Integer Immediate
2887 operand immI()
2888 %{
2889 match(ConI);
2890
2891 op_cost(10);
2892 format %{ %}
2893 interface(CONST_INTER);
2894 %}
2895
2896 // Constant for test vs zero
2897 operand immI0()
2898 %{
2899 predicate(n->get_int() == 0);
2900 match(ConI);
2901
2902 op_cost(0);
2903 format %{ %}
2904 interface(CONST_INTER);
2905 %}
2906
2907 // Constant for increment
2908 operand immI1()
2909 %{
2910 predicate(n->get_int() == 1);
2911 match(ConI);
2912
2913 op_cost(0);
2914 format %{ %}
2915 interface(CONST_INTER);
2916 %}
2917
2918 // Constant for decrement
2919 operand immI_M1()
2920 %{
2921 predicate(n->get_int() == -1);
2922 match(ConI);
2923
2924 op_cost(0);
2925 format %{ %}
2926 interface(CONST_INTER);
2927 %}
2928
2929 // Valid scale values for addressing modes
2930 operand immI2()
2931 %{
2932 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2933 match(ConI);
2934
2935 format %{ %}
2936 interface(CONST_INTER);
2937 %}
2938
2939 operand immI8()
2940 %{
2941 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2942 match(ConI);
2943
2944 op_cost(5);
2945 format %{ %}
2946 interface(CONST_INTER);
2947 %}
2948
2949 operand immI16()
2950 %{
2951 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2952 match(ConI);
2953
2954 op_cost(10);
2955 format %{ %}
2956 interface(CONST_INTER);
2957 %}
2958
2959 // Int Immediate non-negative
2960 operand immU31()
2961 %{
2962 predicate(n->get_int() >= 0);
2963 match(ConI);
2964
2965 op_cost(0);
2966 format %{ %}
2967 interface(CONST_INTER);
2968 %}
2969
2970 // Constant for long shifts
2971 operand immI_32()
2972 %{
2973 predicate( n->get_int() == 32 );
2974 match(ConI);
2975
2976 op_cost(0);
2977 format %{ %}
2978 interface(CONST_INTER);
2979 %}
2980
2981 // Constant for long shifts
2982 operand immI_64()
2983 %{
2984 predicate( n->get_int() == 64 );
2985 match(ConI);
2986
2987 op_cost(0);
2988 format %{ %}
2989 interface(CONST_INTER);
2990 %}
2991
2992 // Pointer Immediate
2993 operand immP()
2994 %{
2995 match(ConP);
2996
2997 op_cost(10);
2998 format %{ %}
2999 interface(CONST_INTER);
3000 %}
3001
3002 // NULL Pointer Immediate
3003 operand immP0()
3004 %{
3005 predicate(n->get_ptr() == 0);
3006 match(ConP);
3007
3008 op_cost(5);
3009 format %{ %}
3010 interface(CONST_INTER);
3011 %}
3012
3013 // Pointer Immediate
3014 operand immN() %{
3015 match(ConN);
3016
3017 op_cost(10);
3018 format %{ %}
3019 interface(CONST_INTER);
3020 %}
3021
3022 operand immNKlass() %{
3023 match(ConNKlass);
3024
3025 op_cost(10);
3026 format %{ %}
3027 interface(CONST_INTER);
3028 %}
3029
3030 // NULL Pointer Immediate
3031 operand immN0() %{
3032 predicate(n->get_narrowcon() == 0);
3033 match(ConN);
3034
3035 op_cost(5);
3036 format %{ %}
3037 interface(CONST_INTER);
3038 %}
3039
3040 operand immP31()
3041 %{
3042 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3043 && (n->get_ptr() >> 31) == 0);
3044 match(ConP);
3045
3046 op_cost(5);
3047 format %{ %}
3048 interface(CONST_INTER);
3049 %}
3050
3051
3052 // Long Immediate
3053 operand immL()
3054 %{
3055 match(ConL);
3056
3057 op_cost(20);
3058 format %{ %}
3059 interface(CONST_INTER);
3060 %}
3061
3062 // Long Immediate 8-bit
3063 operand immL8()
3064 %{
3065 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3066 match(ConL);
3067
3068 op_cost(5);
3069 format %{ %}
3070 interface(CONST_INTER);
3071 %}
3072
3073 // Long Immediate 32-bit unsigned
3074 operand immUL32()
3075 %{
3076 predicate(n->get_long() == (unsigned int) (n->get_long()));
3077 match(ConL);
3078
3079 op_cost(10);
3080 format %{ %}
3081 interface(CONST_INTER);
3082 %}
3083
3084 // Long Immediate 32-bit signed
3085 operand immL32()
3086 %{
3087 predicate(n->get_long() == (int) (n->get_long()));
3088 match(ConL);
3089
3090 op_cost(15);
3091 format %{ %}
3092 interface(CONST_INTER);
3093 %}
3094
3095 // Long Immediate zero
3096 operand immL0()
3097 %{
3098 predicate(n->get_long() == 0L);
3099 match(ConL);
3100
3101 op_cost(10);
3102 format %{ %}
3103 interface(CONST_INTER);
3104 %}
3105
3106 // Constant for increment
3107 operand immL1()
3108 %{
3109 predicate(n->get_long() == 1);
3110 match(ConL);
3111
3112 format %{ %}
3113 interface(CONST_INTER);
3114 %}
3115
3116 // Constant for decrement
3117 operand immL_M1()
3118 %{
3119 predicate(n->get_long() == -1);
3120 match(ConL);
3121
3122 format %{ %}
3123 interface(CONST_INTER);
3124 %}
3125
3126 // Long Immediate: the value 10
3127 operand immL10()
3128 %{
3129 predicate(n->get_long() == 10);
3130 match(ConL);
3131
3132 format %{ %}
3133 interface(CONST_INTER);
3134 %}
3135
3136 // Long immediate from 0 to 127.
3137 // Used for a shorter form of long mul by 10.
3138 operand immL_127()
3139 %{
3140 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3141 match(ConL);
3142
3143 op_cost(10);
3144 format %{ %}
3145 interface(CONST_INTER);
3146 %}
3147
3148 // Long Immediate: low 32-bit mask
3149 operand immL_32bits()
3150 %{
3151 predicate(n->get_long() == 0xFFFFFFFFL);
3152 match(ConL);
3153 op_cost(20);
3154
3155 format %{ %}
3156 interface(CONST_INTER);
3157 %}
3158
3159 // Float Immediate zero
3160 operand immF0()
3161 %{
3162 predicate(jint_cast(n->getf()) == 0);
3163 match(ConF);
3164
3165 op_cost(5);
3166 format %{ %}
3167 interface(CONST_INTER);
3168 %}
3169
3170 // Float Immediate
3171 operand immF()
3172 %{
3173 match(ConF);
3174
3175 op_cost(15);
3176 format %{ %}
3177 interface(CONST_INTER);
3178 %}
3179
3180 // Double Immediate zero
3181 operand immD0()
3182 %{
3183 predicate(jlong_cast(n->getd()) == 0);
3184 match(ConD);
3185
3186 op_cost(5);
3187 format %{ %}
3188 interface(CONST_INTER);
3189 %}
3190
3191 // Double Immediate
3192 operand immD()
3193 %{
3194 match(ConD);
3195
3196 op_cost(15);
3197 format %{ %}
3198 interface(CONST_INTER);
3199 %}
3200
3201 // Immediates for special shifts (sign extend)
3202
3203 // Constants for increment
3204 operand immI_16()
3205 %{
3206 predicate(n->get_int() == 16);
3207 match(ConI);
3208
3209 format %{ %}
3210 interface(CONST_INTER);
3211 %}
3212
3213 operand immI_24()
3214 %{
3215 predicate(n->get_int() == 24);
3216 match(ConI);
3217
3218 format %{ %}
3219 interface(CONST_INTER);
3220 %}
3221
3222 // Constant for byte-wide masking
3223 operand immI_255()
3224 %{
3225 predicate(n->get_int() == 255);
3226 match(ConI);
3227
3228 format %{ %}
3229 interface(CONST_INTER);
3230 %}
3231
3232 // Constant for short-wide masking
3233 operand immI_65535()
3234 %{
3235 predicate(n->get_int() == 65535);
3236 match(ConI);
3237
3238 format %{ %}
3239 interface(CONST_INTER);
3240 %}
3241
3242 // Constant for byte-wide masking
3243 operand immL_255()
3244 %{
3245 predicate(n->get_long() == 255);
3246 match(ConL);
3247
3248 format %{ %}
3249 interface(CONST_INTER);
3250 %}
3251
3252 // Constant for short-wide masking
3253 operand immL_65535()
3254 %{
3255 predicate(n->get_long() == 65535);
3256 match(ConL);
3257
3258 format %{ %}
3259 interface(CONST_INTER);
3260 %}
3261
3262 // Register Operands
3263 // Integer Register
3264 operand rRegI()
3265 %{
3266 constraint(ALLOC_IN_RC(int_reg));
3267 match(RegI);
3268
3269 match(rax_RegI);
3270 match(rbx_RegI);
3271 match(rcx_RegI);
3272 match(rdx_RegI);
3273 match(rdi_RegI);
3274
3275 format %{ %}
3276 interface(REG_INTER);
3277 %}
3278
3279 // Special Registers
3280 operand rax_RegI()
3281 %{
3282 constraint(ALLOC_IN_RC(int_rax_reg));
3283 match(RegI);
3284 match(rRegI);
3285
3286 format %{ "RAX" %}
3287 interface(REG_INTER);
3288 %}
3289
3290 // Special Registers
3291 operand rbx_RegI()
3292 %{
3293 constraint(ALLOC_IN_RC(int_rbx_reg));
3294 match(RegI);
3295 match(rRegI);
3296
3297 format %{ "RBX" %}
3298 interface(REG_INTER);
3299 %}
3300
3301 operand rcx_RegI()
3302 %{
3303 constraint(ALLOC_IN_RC(int_rcx_reg));
3304 match(RegI);
3305 match(rRegI);
3306
3307 format %{ "RCX" %}
3308 interface(REG_INTER);
3309 %}
3310
3311 operand rdx_RegI()
3312 %{
3313 constraint(ALLOC_IN_RC(int_rdx_reg));
3314 match(RegI);
3315 match(rRegI);
3316
3317 format %{ "RDX" %}
3318 interface(REG_INTER);
3319 %}
3320
3321 operand rdi_RegI()
3322 %{
3323 constraint(ALLOC_IN_RC(int_rdi_reg));
3324 match(RegI);
3325 match(rRegI);
3326
3327 format %{ "RDI" %}
3328 interface(REG_INTER);
3329 %}
3330
3331 operand no_rcx_RegI()
3332 %{
3333 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3334 match(RegI);
3335 match(rax_RegI);
3336 match(rbx_RegI);
3337 match(rdx_RegI);
3338 match(rdi_RegI);
3339
3340 format %{ %}
3341 interface(REG_INTER);
3342 %}
3343
3344 operand no_rax_rdx_RegI()
3345 %{
3346 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3347 match(RegI);
3348 match(rbx_RegI);
3349 match(rcx_RegI);
3350 match(rdi_RegI);
3351
3352 format %{ %}
3353 interface(REG_INTER);
3354 %}
3355
3356 // Pointer Register
3357 operand any_RegP()
3358 %{
3359 constraint(ALLOC_IN_RC(any_reg));
3360 match(RegP);
3361 match(rax_RegP);
3362 match(rbx_RegP);
3363 match(rdi_RegP);
3364 match(rsi_RegP);
3365 match(rbp_RegP);
3366 match(r15_RegP);
3367 match(rRegP);
3368
3369 format %{ %}
3370 interface(REG_INTER);
3371 %}
3372
3373 operand rRegP()
3374 %{
3375 constraint(ALLOC_IN_RC(ptr_reg));
3376 match(RegP);
3377 match(rax_RegP);
3378 match(rbx_RegP);
3379 match(rdi_RegP);
3380 match(rsi_RegP);
3381 match(rbp_RegP); // See Q&A below about
3382 match(r15_RegP); // r15_RegP and rbp_RegP.
3383
3384 format %{ %}
3385 interface(REG_INTER);
3386 %}
3387
3388 operand rRegN() %{
3389 constraint(ALLOC_IN_RC(int_reg));
3390 match(RegN);
3391
3392 format %{ %}
3393 interface(REG_INTER);
3394 %}
3395
3396 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3397 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3398 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3399 // The output of an instruction is controlled by the allocator, which respects
3400 // register class masks, not match rules. Unless an instruction mentions
3401 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3402 // by the allocator as an input.
3403 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3404 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3405 // result, RBP is not included in the output of the instruction either.
3406
3407 operand no_rax_RegP()
3408 %{
3409 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3410 match(RegP);
3411 match(rbx_RegP);
3412 match(rsi_RegP);
3413 match(rdi_RegP);
3414
3415 format %{ %}
3416 interface(REG_INTER);
3417 %}
3418
3419 // This operand is not allowed to use RBP even if
3420 // RBP is not used to hold the frame pointer.
3421 operand no_rbp_RegP()
3422 %{
3423 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3424 match(RegP);
3425 match(rbx_RegP);
3426 match(rsi_RegP);
3427 match(rdi_RegP);
3428
3429 format %{ %}
3430 interface(REG_INTER);
3431 %}
3432
3433 operand no_rax_rbx_RegP()
3434 %{
3435 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3436 match(RegP);
3437 match(rsi_RegP);
3438 match(rdi_RegP);
3439
3440 format %{ %}
3441 interface(REG_INTER);
3442 %}
3443
3444 // Special Registers
3445 // Return a pointer value
3446 operand rax_RegP()
3447 %{
3448 constraint(ALLOC_IN_RC(ptr_rax_reg));
3449 match(RegP);
3450 match(rRegP);
3451
3452 format %{ %}
3453 interface(REG_INTER);
3454 %}
3455
3456 // Special Registers
3457 // Return a compressed pointer value
3458 operand rax_RegN()
3459 %{
3460 constraint(ALLOC_IN_RC(int_rax_reg));
3461 match(RegN);
3462 match(rRegN);
3463
3464 format %{ %}
3465 interface(REG_INTER);
3466 %}
3467
3468 // Used in AtomicAdd
3469 operand rbx_RegP()
3470 %{
3471 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3472 match(RegP);
3473 match(rRegP);
3474
3475 format %{ %}
3476 interface(REG_INTER);
3477 %}
3478
3479 operand rsi_RegP()
3480 %{
3481 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3482 match(RegP);
3483 match(rRegP);
3484
3485 format %{ %}
3486 interface(REG_INTER);
3487 %}
3488
3489 // Used in rep stosq
3490 operand rdi_RegP()
3491 %{
3492 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3493 match(RegP);
3494 match(rRegP);
3495
3496 format %{ %}
3497 interface(REG_INTER);
3498 %}
3499
3500 operand r15_RegP()
3501 %{
3502 constraint(ALLOC_IN_RC(ptr_r15_reg));
3503 match(RegP);
3504 match(rRegP);
3505
3506 format %{ %}
3507 interface(REG_INTER);
3508 %}
3509
3510 operand rRegL()
3511 %{
3512 constraint(ALLOC_IN_RC(long_reg));
3513 match(RegL);
3514 match(rax_RegL);
3515 match(rdx_RegL);
3516
3517 format %{ %}
3518 interface(REG_INTER);
3519 %}
3520
3521 // Special Registers
3522 operand no_rax_rdx_RegL()
3523 %{
3524 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3525 match(RegL);
3526 match(rRegL);
3527
3528 format %{ %}
3529 interface(REG_INTER);
3530 %}
3531
3532 operand no_rax_RegL()
3533 %{
3534 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3535 match(RegL);
3536 match(rRegL);
3537 match(rdx_RegL);
3538
3539 format %{ %}
3540 interface(REG_INTER);
3541 %}
3542
3543 operand no_rcx_RegL()
3544 %{
3545 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3546 match(RegL);
3547 match(rRegL);
3548
3549 format %{ %}
3550 interface(REG_INTER);
3551 %}
3552
3553 operand rax_RegL()
3554 %{
3555 constraint(ALLOC_IN_RC(long_rax_reg));
3556 match(RegL);
3557 match(rRegL);
3558
3559 format %{ "RAX" %}
3560 interface(REG_INTER);
3561 %}
3562
3563 operand rcx_RegL()
3564 %{
3565 constraint(ALLOC_IN_RC(long_rcx_reg));
3566 match(RegL);
3567 match(rRegL);
3568
3569 format %{ %}
3570 interface(REG_INTER);
3571 %}
3572
3573 operand rdx_RegL()
3574 %{
3575 constraint(ALLOC_IN_RC(long_rdx_reg));
3576 match(RegL);
3577 match(rRegL);
3578
3579 format %{ %}
3580 interface(REG_INTER);
3581 %}
3582
3583 // Flags register, used as output of compare instructions
3584 operand rFlagsReg()
3585 %{
3586 constraint(ALLOC_IN_RC(int_flags));
3587 match(RegFlags);
3588
3589 format %{ "RFLAGS" %}
3590 interface(REG_INTER);
3591 %}
3592
3593 // Flags register, used as output of FLOATING POINT compare instructions
3594 operand rFlagsRegU()
3595 %{
3596 constraint(ALLOC_IN_RC(int_flags));
3597 match(RegFlags);
3598
3599 format %{ "RFLAGS_U" %}
3600 interface(REG_INTER);
3601 %}
3602
3603 operand rFlagsRegUCF() %{
3604 constraint(ALLOC_IN_RC(int_flags));
3605 match(RegFlags);
3606 predicate(false);
3607
3608 format %{ "RFLAGS_U_CF" %}
3609 interface(REG_INTER);
3610 %}
3611
3612 // Float register operands
3613 operand regF() %{
3614 constraint(ALLOC_IN_RC(float_reg));
3615 match(RegF);
3616
3617 format %{ %}
3618 interface(REG_INTER);
3619 %}
3620
3621 // Double register operands
3622 operand regD() %{
3623 constraint(ALLOC_IN_RC(double_reg));
3624 match(RegD);
3625
3626 format %{ %}
3627 interface(REG_INTER);
3628 %}
3629
3630 // Vectors
3631 operand vecS() %{
3632 constraint(ALLOC_IN_RC(vectors_reg));
3633 match(VecS);
3634
3635 format %{ %}
3636 interface(REG_INTER);
3637 %}
3638
3639 operand vecD() %{
3640 constraint(ALLOC_IN_RC(vectord_reg));
3641 match(VecD);
3642
3643 format %{ %}
3644 interface(REG_INTER);
3645 %}
3646
3647 operand vecX() %{
3648 constraint(ALLOC_IN_RC(vectorx_reg));
3649 match(VecX);
3650
3651 format %{ %}
3652 interface(REG_INTER);
3653 %}
3654
3655 operand vecY() %{
3656 constraint(ALLOC_IN_RC(vectory_reg));
3657 match(VecY);
3658
3659 format %{ %}
3660 interface(REG_INTER);
3661 %}
3662
3663 //----------Memory Operands----------------------------------------------------
3664 // Direct Memory Operand
3665 // operand direct(immP addr)
3666 // %{
3667 // match(addr);
3668
3669 // format %{ "[$addr]" %}
3670 // interface(MEMORY_INTER) %{
3671 // base(0xFFFFFFFF);
3672 // index(0x4);
3673 // scale(0x0);
3674 // disp($addr);
3675 // %}
3676 // %}
3677
3678 // Indirect Memory Operand
3679 operand indirect(any_RegP reg)
3680 %{
3681 constraint(ALLOC_IN_RC(ptr_reg));
3682 match(reg);
3683
3684 format %{ "[$reg]" %}
3685 interface(MEMORY_INTER) %{
3686 base($reg);
3687 index(0x4);
3688 scale(0x0);
3689 disp(0x0);
3690 %}
3691 %}
3692
3693 // Indirect Memory Plus Short Offset Operand
3694 operand indOffset8(any_RegP reg, immL8 off)
3695 %{
3696 constraint(ALLOC_IN_RC(ptr_reg));
3697 match(AddP reg off);
3698
3699 format %{ "[$reg + $off (8-bit)]" %}
3700 interface(MEMORY_INTER) %{
3701 base($reg);
3702 index(0x4);
3703 scale(0x0);
3704 disp($off);
3705 %}
3706 %}
3707
3708 // Indirect Memory Plus Long Offset Operand
3709 operand indOffset32(any_RegP reg, immL32 off)
3710 %{
3711 constraint(ALLOC_IN_RC(ptr_reg));
3712 match(AddP reg off);
3713
3714 format %{ "[$reg + $off (32-bit)]" %}
3715 interface(MEMORY_INTER) %{
3716 base($reg);
3717 index(0x4);
3718 scale(0x0);
3719 disp($off);
3720 %}
3721 %}
3722
3723 // Indirect Memory Plus Index Register Plus Offset Operand
3724 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3725 %{
3726 constraint(ALLOC_IN_RC(ptr_reg));
3727 match(AddP (AddP reg lreg) off);
3728
3729 op_cost(10);
3730 format %{"[$reg + $off + $lreg]" %}
3731 interface(MEMORY_INTER) %{
3732 base($reg);
3733 index($lreg);
3734 scale(0x0);
3735 disp($off);
3736 %}
3737 %}
3738
3739 // Indirect Memory Plus Index Register Plus Offset Operand
3740 operand indIndex(any_RegP reg, rRegL lreg)
3741 %{
3742 constraint(ALLOC_IN_RC(ptr_reg));
3743 match(AddP reg lreg);
3744
3745 op_cost(10);
3746 format %{"[$reg + $lreg]" %}
3747 interface(MEMORY_INTER) %{
3748 base($reg);
3749 index($lreg);
3750 scale(0x0);
3751 disp(0x0);
3752 %}
3753 %}
3754
3755 // Indirect Memory Times Scale Plus Index Register
3756 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3757 %{
3758 constraint(ALLOC_IN_RC(ptr_reg));
3759 match(AddP reg (LShiftL lreg scale));
3760
3761 op_cost(10);
3762 format %{"[$reg + $lreg << $scale]" %}
3763 interface(MEMORY_INTER) %{
3764 base($reg);
3765 index($lreg);
3766 scale($scale);
3767 disp(0x0);
3768 %}
3769 %}
3770
3771 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3772 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3773 %{
3774 constraint(ALLOC_IN_RC(ptr_reg));
3775 match(AddP (AddP reg (LShiftL lreg scale)) off);
3776
3777 op_cost(10);
3778 format %{"[$reg + $off + $lreg << $scale]" %}
3779 interface(MEMORY_INTER) %{
3780 base($reg);
3781 index($lreg);
3782 scale($scale);
3783 disp($off);
3784 %}
3785 %}
3786
3787 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3788 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3789 %{
3790 constraint(ALLOC_IN_RC(ptr_reg));
3791 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3792 match(AddP (AddP reg (ConvI2L idx)) off);
3793
3794 op_cost(10);
3795 format %{"[$reg + $off + $idx]" %}
3796 interface(MEMORY_INTER) %{
3797 base($reg);
3798 index($idx);
3799 scale(0x0);
3800 disp($off);
3801 %}
3802 %}
3803
3804 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3805 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3806 %{
3807 constraint(ALLOC_IN_RC(ptr_reg));
3808 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3809 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3810
3811 op_cost(10);
3812 format %{"[$reg + $off + $idx << $scale]" %}
3813 interface(MEMORY_INTER) %{
3814 base($reg);
3815 index($idx);
3816 scale($scale);
3817 disp($off);
3818 %}
3819 %}
3820
3821 // Indirect Narrow Oop Plus Offset Operand
3822 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3823 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3824 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3825 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3826 constraint(ALLOC_IN_RC(ptr_reg));
3827 match(AddP (DecodeN reg) off);
3828
3829 op_cost(10);
3830 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3831 interface(MEMORY_INTER) %{
3832 base(0xc); // R12
3833 index($reg);
3834 scale(0x3);
3835 disp($off);
3836 %}
3837 %}
3838
3839 // Indirect Memory Operand
3840 operand indirectNarrow(rRegN reg)
3841 %{
3842 predicate(Universe::narrow_oop_shift() == 0);
3843 constraint(ALLOC_IN_RC(ptr_reg));
3844 match(DecodeN reg);
3845
3846 format %{ "[$reg]" %}
3847 interface(MEMORY_INTER) %{
3848 base($reg);
3849 index(0x4);
3850 scale(0x0);
3851 disp(0x0);
3852 %}
3853 %}
3854
3855 // Indirect Memory Plus Short Offset Operand
3856 operand indOffset8Narrow(rRegN reg, immL8 off)
3857 %{
3858 predicate(Universe::narrow_oop_shift() == 0);
3859 constraint(ALLOC_IN_RC(ptr_reg));
3860 match(AddP (DecodeN reg) off);
3861
3862 format %{ "[$reg + $off (8-bit)]" %}
3863 interface(MEMORY_INTER) %{
3864 base($reg);
3865 index(0x4);
3866 scale(0x0);
3867 disp($off);
3868 %}
3869 %}
3870
3871 // Indirect Memory Plus Long Offset Operand
3872 operand indOffset32Narrow(rRegN reg, immL32 off)
3873 %{
3874 predicate(Universe::narrow_oop_shift() == 0);
3875 constraint(ALLOC_IN_RC(ptr_reg));
3876 match(AddP (DecodeN reg) off);
3877
3878 format %{ "[$reg + $off (32-bit)]" %}
3879 interface(MEMORY_INTER) %{
3880 base($reg);
3881 index(0x4);
3882 scale(0x0);
3883 disp($off);
3884 %}
3885 %}
3886
3887 // Indirect Memory Plus Index Register Plus Offset Operand
3888 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3889 %{
3890 predicate(Universe::narrow_oop_shift() == 0);
3891 constraint(ALLOC_IN_RC(ptr_reg));
3892 match(AddP (AddP (DecodeN reg) lreg) off);
3893
3894 op_cost(10);
3895 format %{"[$reg + $off + $lreg]" %}
3896 interface(MEMORY_INTER) %{
3897 base($reg);
3898 index($lreg);
3899 scale(0x0);
3900 disp($off);
3901 %}
3902 %}
3903
3904 // Indirect Memory Plus Index Register Plus Offset Operand
3905 operand indIndexNarrow(rRegN reg, rRegL lreg)
3906 %{
3907 predicate(Universe::narrow_oop_shift() == 0);
3908 constraint(ALLOC_IN_RC(ptr_reg));
3909 match(AddP (DecodeN reg) lreg);
3910
3911 op_cost(10);
3912 format %{"[$reg + $lreg]" %}
3913 interface(MEMORY_INTER) %{
3914 base($reg);
3915 index($lreg);
3916 scale(0x0);
3917 disp(0x0);
3918 %}
3919 %}
3920
3921 // Indirect Memory Times Scale Plus Index Register
3922 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3923 %{
3924 predicate(Universe::narrow_oop_shift() == 0);
3925 constraint(ALLOC_IN_RC(ptr_reg));
3926 match(AddP (DecodeN reg) (LShiftL lreg scale));
3927
3928 op_cost(10);
3929 format %{"[$reg + $lreg << $scale]" %}
3930 interface(MEMORY_INTER) %{
3931 base($reg);
3932 index($lreg);
3933 scale($scale);
3934 disp(0x0);
3935 %}
3936 %}
3937
3938 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3939 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3940 %{
3941 predicate(Universe::narrow_oop_shift() == 0);
3942 constraint(ALLOC_IN_RC(ptr_reg));
3943 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3944
3945 op_cost(10);
3946 format %{"[$reg + $off + $lreg << $scale]" %}
3947 interface(MEMORY_INTER) %{
3948 base($reg);
3949 index($lreg);
3950 scale($scale);
3951 disp($off);
3952 %}
3953 %}
3954
3955 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
3956 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
3957 %{
3958 constraint(ALLOC_IN_RC(ptr_reg));
3959 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3960 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
3961
3962 op_cost(10);
3963 format %{"[$reg + $off + $idx]" %}
3964 interface(MEMORY_INTER) %{
3965 base($reg);
3966 index($idx);
3967 scale(0x0);
3968 disp($off);
3969 %}
3970 %}
3971
3972 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3973 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3974 %{
3975 constraint(ALLOC_IN_RC(ptr_reg));
3976 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3977 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
3978
3979 op_cost(10);
3980 format %{"[$reg + $off + $idx << $scale]" %}
3981 interface(MEMORY_INTER) %{
3982 base($reg);
3983 index($idx);
3984 scale($scale);
3985 disp($off);
3986 %}
3987 %}
3988
3989 //----------Special Memory Operands--------------------------------------------
3990 // Stack Slot Operand - This operand is used for loading and storing temporary
3991 // values on the stack where a match requires a value to
3992 // flow through memory.
3993 operand stackSlotP(sRegP reg)
3994 %{
3995 constraint(ALLOC_IN_RC(stack_slots));
3996 // No match rule because this operand is only generated in matching
3997
3998 format %{ "[$reg]" %}
3999 interface(MEMORY_INTER) %{
4000 base(0x4); // RSP
4001 index(0x4); // No Index
4002 scale(0x0); // No Scale
4003 disp($reg); // Stack Offset
4004 %}
4005 %}
4006
4007 operand stackSlotI(sRegI reg)
4008 %{
4009 constraint(ALLOC_IN_RC(stack_slots));
4010 // No match rule because this operand is only generated in matching
4011
4012 format %{ "[$reg]" %}
4013 interface(MEMORY_INTER) %{
4014 base(0x4); // RSP
4015 index(0x4); // No Index
4016 scale(0x0); // No Scale
4017 disp($reg); // Stack Offset
4018 %}
4019 %}
4020
4021 operand stackSlotF(sRegF reg)
4022 %{
4023 constraint(ALLOC_IN_RC(stack_slots));
4024 // No match rule because this operand is only generated in matching
4025
4026 format %{ "[$reg]" %}
4027 interface(MEMORY_INTER) %{
4028 base(0x4); // RSP
4029 index(0x4); // No Index
4030 scale(0x0); // No Scale
4031 disp($reg); // Stack Offset
4032 %}
4033 %}
4034
4035 operand stackSlotD(sRegD reg)
4036 %{
4037 constraint(ALLOC_IN_RC(stack_slots));
4038 // No match rule because this operand is only generated in matching
4039
4040 format %{ "[$reg]" %}
4041 interface(MEMORY_INTER) %{
4042 base(0x4); // RSP
4043 index(0x4); // No Index
4044 scale(0x0); // No Scale
4045 disp($reg); // Stack Offset
4046 %}
4047 %}
4048 operand stackSlotL(sRegL reg)
4049 %{
4050 constraint(ALLOC_IN_RC(stack_slots));
4051 // No match rule because this operand is only generated in matching
4052
4053 format %{ "[$reg]" %}
4054 interface(MEMORY_INTER) %{
4055 base(0x4); // RSP
4056 index(0x4); // No Index
4057 scale(0x0); // No Scale
4058 disp($reg); // Stack Offset
4059 %}
4060 %}
4061
4062 //----------Conditional Branch Operands----------------------------------------
4063 // Comparison Op - This is the operation of the comparison, and is limited to
4064 // the following set of codes:
4065 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4066 //
4067 // Other attributes of the comparison, such as unsignedness, are specified
4068 // by the comparison instruction that sets a condition code flags register.
4069 // That result is represented by a flags operand whose subtype is appropriate
4070 // to the unsignedness (etc.) of the comparison.
4071 //
4072 // Later, the instruction which matches both the Comparison Op (a Bool) and
4073 // the flags (produced by the Cmp) specifies the coding of the comparison op
4074 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4075
4076 // Comparision Code
4077 operand cmpOp()
4078 %{
4079 match(Bool);
4080
4081 format %{ "" %}
4082 interface(COND_INTER) %{
4083 equal(0x4, "e");
4084 not_equal(0x5, "ne");
4085 less(0xC, "l");
4086 greater_equal(0xD, "ge");
4087 less_equal(0xE, "le");
4088 greater(0xF, "g");
4089 overflow(0x0, "o");
4090 no_overflow(0x1, "no");
4091 %}
4092 %}
4093
4094 // Comparison Code, unsigned compare. Used by FP also, with
4095 // C2 (unordered) turned into GT or LT already. The other bits
4096 // C0 and C3 are turned into Carry & Zero flags.
4097 operand cmpOpU()
4098 %{
4099 match(Bool);
4100
4101 format %{ "" %}
4102 interface(COND_INTER) %{
4103 equal(0x4, "e");
4104 not_equal(0x5, "ne");
4105 less(0x2, "b");
4106 greater_equal(0x3, "nb");
4107 less_equal(0x6, "be");
4108 greater(0x7, "nbe");
4109 overflow(0x0, "o");
4110 no_overflow(0x1, "no");
4111 %}
4112 %}
4113
4114
4115 // Floating comparisons that don't require any fixup for the unordered case
4116 operand cmpOpUCF() %{
4117 match(Bool);
4118 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4119 n->as_Bool()->_test._test == BoolTest::ge ||
4120 n->as_Bool()->_test._test == BoolTest::le ||
4121 n->as_Bool()->_test._test == BoolTest::gt);
4122 format %{ "" %}
4123 interface(COND_INTER) %{
4124 equal(0x4, "e");
4125 not_equal(0x5, "ne");
4126 less(0x2, "b");
4127 greater_equal(0x3, "nb");
4128 less_equal(0x6, "be");
4129 greater(0x7, "nbe");
4130 overflow(0x0, "o");
4131 no_overflow(0x1, "no");
4132 %}
4133 %}
4134
4135
4136 // Floating comparisons that can be fixed up with extra conditional jumps
4137 operand cmpOpUCF2() %{
4138 match(Bool);
4139 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4140 n->as_Bool()->_test._test == BoolTest::eq);
4141 format %{ "" %}
4142 interface(COND_INTER) %{
4143 equal(0x4, "e");
4144 not_equal(0x5, "ne");
4145 less(0x2, "b");
4146 greater_equal(0x3, "nb");
4147 less_equal(0x6, "be");
4148 greater(0x7, "nbe");
4149 overflow(0x0, "o");
4150 no_overflow(0x1, "no");
4151 %}
4152 %}
4153
4154
4155 //----------OPERAND CLASSES----------------------------------------------------
4156 // Operand Classes are groups of operands that are used as to simplify
4157 // instruction definitions by not requiring the AD writer to specify separate
4158 // instructions for every form of operand when the instruction accepts
4159 // multiple operand types with the same basic encoding and format. The classic
4160 // case of this is memory operands.
4161
4162 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4163 indIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4164 indCompressedOopOffset,
4165 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4166 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4167 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4168
4169 //----------PIPELINE-----------------------------------------------------------
4170 // Rules which define the behavior of the target architectures pipeline.
4171 pipeline %{
4172
4173 //----------ATTRIBUTES---------------------------------------------------------
4174 attributes %{
4175 variable_size_instructions; // Fixed size instructions
4176 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4177 instruction_unit_size = 1; // An instruction is 1 bytes long
4178 instruction_fetch_unit_size = 16; // The processor fetches one line
4179 instruction_fetch_units = 1; // of 16 bytes
4180
4181 // List of nop instructions
4182 nops( MachNop );
4183 %}
4184
4185 //----------RESOURCES----------------------------------------------------------
4186 // Resources are the functional units available to the machine
4187
4188 // Generic P2/P3 pipeline
4189 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4190 // 3 instructions decoded per cycle.
4191 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4192 // 3 ALU op, only ALU0 handles mul instructions.
4193 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4194 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4195 BR, FPU,
4196 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4197
4198 //----------PIPELINE DESCRIPTION-----------------------------------------------
4199 // Pipeline Description specifies the stages in the machine's pipeline
4200
4201 // Generic P2/P3 pipeline
4202 pipe_desc(S0, S1, S2, S3, S4, S5);
4203
4204 //----------PIPELINE CLASSES---------------------------------------------------
4205 // Pipeline Classes describe the stages in which input and output are
4206 // referenced by the hardware pipeline.
4207
4208 // Naming convention: ialu or fpu
4209 // Then: _reg
4210 // Then: _reg if there is a 2nd register
4211 // Then: _long if it's a pair of instructions implementing a long
4212 // Then: _fat if it requires the big decoder
4213 // Or: _mem if it requires the big decoder and a memory unit.
4214
4215 // Integer ALU reg operation
4216 pipe_class ialu_reg(rRegI dst)
4217 %{
4218 single_instruction;
4219 dst : S4(write);
4220 dst : S3(read);
4221 DECODE : S0; // any decoder
4222 ALU : S3; // any alu
4223 %}
4224
4225 // Long ALU reg operation
4226 pipe_class ialu_reg_long(rRegL dst)
4227 %{
4228 instruction_count(2);
4229 dst : S4(write);
4230 dst : S3(read);
4231 DECODE : S0(2); // any 2 decoders
4232 ALU : S3(2); // both alus
4233 %}
4234
4235 // Integer ALU reg operation using big decoder
4236 pipe_class ialu_reg_fat(rRegI dst)
4237 %{
4238 single_instruction;
4239 dst : S4(write);
4240 dst : S3(read);
4241 D0 : S0; // big decoder only
4242 ALU : S3; // any alu
4243 %}
4244
4245 // Long ALU reg operation using big decoder
4246 pipe_class ialu_reg_long_fat(rRegL dst)
4247 %{
4248 instruction_count(2);
4249 dst : S4(write);
4250 dst : S3(read);
4251 D0 : S0(2); // big decoder only; twice
4252 ALU : S3(2); // any 2 alus
4253 %}
4254
4255 // Integer ALU reg-reg operation
4256 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4257 %{
4258 single_instruction;
4259 dst : S4(write);
4260 src : S3(read);
4261 DECODE : S0; // any decoder
4262 ALU : S3; // any alu
4263 %}
4264
4265 // Long ALU reg-reg operation
4266 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4267 %{
4268 instruction_count(2);
4269 dst : S4(write);
4270 src : S3(read);
4271 DECODE : S0(2); // any 2 decoders
4272 ALU : S3(2); // both alus
4273 %}
4274
4275 // Integer ALU reg-reg operation
4276 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4277 %{
4278 single_instruction;
4279 dst : S4(write);
4280 src : S3(read);
4281 D0 : S0; // big decoder only
4282 ALU : S3; // any alu
4283 %}
4284
4285 // Long ALU reg-reg operation
4286 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4287 %{
4288 instruction_count(2);
4289 dst : S4(write);
4290 src : S3(read);
4291 D0 : S0(2); // big decoder only; twice
4292 ALU : S3(2); // both alus
4293 %}
4294
4295 // Integer ALU reg-mem operation
4296 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4297 %{
4298 single_instruction;
4299 dst : S5(write);
4300 mem : S3(read);
4301 D0 : S0; // big decoder only
4302 ALU : S4; // any alu
4303 MEM : S3; // any mem
4304 %}
4305
4306 // Integer mem operation (prefetch)
4307 pipe_class ialu_mem(memory mem)
4308 %{
4309 single_instruction;
4310 mem : S3(read);
4311 D0 : S0; // big decoder only
4312 MEM : S3; // any mem
4313 %}
4314
4315 // Integer Store to Memory
4316 pipe_class ialu_mem_reg(memory mem, rRegI src)
4317 %{
4318 single_instruction;
4319 mem : S3(read);
4320 src : S5(read);
4321 D0 : S0; // big decoder only
4322 ALU : S4; // any alu
4323 MEM : S3;
4324 %}
4325
4326 // // Long Store to Memory
4327 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4328 // %{
4329 // instruction_count(2);
4330 // mem : S3(read);
4331 // src : S5(read);
4332 // D0 : S0(2); // big decoder only; twice
4333 // ALU : S4(2); // any 2 alus
4334 // MEM : S3(2); // Both mems
4335 // %}
4336
4337 // Integer Store to Memory
4338 pipe_class ialu_mem_imm(memory mem)
4339 %{
4340 single_instruction;
4341 mem : S3(read);
4342 D0 : S0; // big decoder only
4343 ALU : S4; // any alu
4344 MEM : S3;
4345 %}
4346
4347 // Integer ALU0 reg-reg operation
4348 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4349 %{
4350 single_instruction;
4351 dst : S4(write);
4352 src : S3(read);
4353 D0 : S0; // Big decoder only
4354 ALU0 : S3; // only alu0
4355 %}
4356
4357 // Integer ALU0 reg-mem operation
4358 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4359 %{
4360 single_instruction;
4361 dst : S5(write);
4362 mem : S3(read);
4363 D0 : S0; // big decoder only
4364 ALU0 : S4; // ALU0 only
4365 MEM : S3; // any mem
4366 %}
4367
4368 // Integer ALU reg-reg operation
4369 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4370 %{
4371 single_instruction;
4372 cr : S4(write);
4373 src1 : S3(read);
4374 src2 : S3(read);
4375 DECODE : S0; // any decoder
4376 ALU : S3; // any alu
4377 %}
4378
4379 // Integer ALU reg-imm operation
4380 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4381 %{
4382 single_instruction;
4383 cr : S4(write);
4384 src1 : S3(read);
4385 DECODE : S0; // any decoder
4386 ALU : S3; // any alu
4387 %}
4388
4389 // Integer ALU reg-mem operation
4390 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4391 %{
4392 single_instruction;
4393 cr : S4(write);
4394 src1 : S3(read);
4395 src2 : S3(read);
4396 D0 : S0; // big decoder only
4397 ALU : S4; // any alu
4398 MEM : S3;
4399 %}
4400
4401 // Conditional move reg-reg
4402 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4403 %{
4404 instruction_count(4);
4405 y : S4(read);
4406 q : S3(read);
4407 p : S3(read);
4408 DECODE : S0(4); // any decoder
4409 %}
4410
4411 // Conditional move reg-reg
4412 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4413 %{
4414 single_instruction;
4415 dst : S4(write);
4416 src : S3(read);
4417 cr : S3(read);
4418 DECODE : S0; // any decoder
4419 %}
4420
4421 // Conditional move reg-mem
4422 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4423 %{
4424 single_instruction;
4425 dst : S4(write);
4426 src : S3(read);
4427 cr : S3(read);
4428 DECODE : S0; // any decoder
4429 MEM : S3;
4430 %}
4431
4432 // Conditional move reg-reg long
4433 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4434 %{
4435 single_instruction;
4436 dst : S4(write);
4437 src : S3(read);
4438 cr : S3(read);
4439 DECODE : S0(2); // any 2 decoders
4440 %}
4441
4442 // XXX
4443 // // Conditional move double reg-reg
4444 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4445 // %{
4446 // single_instruction;
4447 // dst : S4(write);
4448 // src : S3(read);
4449 // cr : S3(read);
4450 // DECODE : S0; // any decoder
4451 // %}
4452
4453 // Float reg-reg operation
4454 pipe_class fpu_reg(regD dst)
4455 %{
4456 instruction_count(2);
4457 dst : S3(read);
4458 DECODE : S0(2); // any 2 decoders
4459 FPU : S3;
4460 %}
4461
4462 // Float reg-reg operation
4463 pipe_class fpu_reg_reg(regD dst, regD src)
4464 %{
4465 instruction_count(2);
4466 dst : S4(write);
4467 src : S3(read);
4468 DECODE : S0(2); // any 2 decoders
4469 FPU : S3;
4470 %}
4471
4472 // Float reg-reg operation
4473 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4474 %{
4475 instruction_count(3);
4476 dst : S4(write);
4477 src1 : S3(read);
4478 src2 : S3(read);
4479 DECODE : S0(3); // any 3 decoders
4480 FPU : S3(2);
4481 %}
4482
4483 // Float reg-reg operation
4484 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4485 %{
4486 instruction_count(4);
4487 dst : S4(write);
4488 src1 : S3(read);
4489 src2 : S3(read);
4490 src3 : S3(read);
4491 DECODE : S0(4); // any 3 decoders
4492 FPU : S3(2);
4493 %}
4494
4495 // Float reg-reg operation
4496 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4497 %{
4498 instruction_count(4);
4499 dst : S4(write);
4500 src1 : S3(read);
4501 src2 : S3(read);
4502 src3 : S3(read);
4503 DECODE : S1(3); // any 3 decoders
4504 D0 : S0; // Big decoder only
4505 FPU : S3(2);
4506 MEM : S3;
4507 %}
4508
4509 // Float reg-mem operation
4510 pipe_class fpu_reg_mem(regD dst, memory mem)
4511 %{
4512 instruction_count(2);
4513 dst : S5(write);
4514 mem : S3(read);
4515 D0 : S0; // big decoder only
4516 DECODE : S1; // any decoder for FPU POP
4517 FPU : S4;
4518 MEM : S3; // any mem
4519 %}
4520
4521 // Float reg-mem operation
4522 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4523 %{
4524 instruction_count(3);
4525 dst : S5(write);
4526 src1 : S3(read);
4527 mem : S3(read);
4528 D0 : S0; // big decoder only
4529 DECODE : S1(2); // any decoder for FPU POP
4530 FPU : S4;
4531 MEM : S3; // any mem
4532 %}
4533
4534 // Float mem-reg operation
4535 pipe_class fpu_mem_reg(memory mem, regD src)
4536 %{
4537 instruction_count(2);
4538 src : S5(read);
4539 mem : S3(read);
4540 DECODE : S0; // any decoder for FPU PUSH
4541 D0 : S1; // big decoder only
4542 FPU : S4;
4543 MEM : S3; // any mem
4544 %}
4545
4546 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4547 %{
4548 instruction_count(3);
4549 src1 : S3(read);
4550 src2 : S3(read);
4551 mem : S3(read);
4552 DECODE : S0(2); // any decoder for FPU PUSH
4553 D0 : S1; // big decoder only
4554 FPU : S4;
4555 MEM : S3; // any mem
4556 %}
4557
4558 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4559 %{
4560 instruction_count(3);
4561 src1 : S3(read);
4562 src2 : S3(read);
4563 mem : S4(read);
4564 DECODE : S0; // any decoder for FPU PUSH
4565 D0 : S0(2); // big decoder only
4566 FPU : S4;
4567 MEM : S3(2); // any mem
4568 %}
4569
4570 pipe_class fpu_mem_mem(memory dst, memory src1)
4571 %{
4572 instruction_count(2);
4573 src1 : S3(read);
4574 dst : S4(read);
4575 D0 : S0(2); // big decoder only
4576 MEM : S3(2); // any mem
4577 %}
4578
4579 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4580 %{
4581 instruction_count(3);
4582 src1 : S3(read);
4583 src2 : S3(read);
4584 dst : S4(read);
4585 D0 : S0(3); // big decoder only
4586 FPU : S4;
4587 MEM : S3(3); // any mem
4588 %}
4589
4590 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4591 %{
4592 instruction_count(3);
4593 src1 : S4(read);
4594 mem : S4(read);
4595 DECODE : S0; // any decoder for FPU PUSH
4596 D0 : S0(2); // big decoder only
4597 FPU : S4;
4598 MEM : S3(2); // any mem
4599 %}
4600
4601 // Float load constant
4602 pipe_class fpu_reg_con(regD dst)
4603 %{
4604 instruction_count(2);
4605 dst : S5(write);
4606 D0 : S0; // big decoder only for the load
4607 DECODE : S1; // any decoder for FPU POP
4608 FPU : S4;
4609 MEM : S3; // any mem
4610 %}
4611
4612 // Float load constant
4613 pipe_class fpu_reg_reg_con(regD dst, regD src)
4614 %{
4615 instruction_count(3);
4616 dst : S5(write);
4617 src : S3(read);
4618 D0 : S0; // big decoder only for the load
4619 DECODE : S1(2); // any decoder for FPU POP
4620 FPU : S4;
4621 MEM : S3; // any mem
4622 %}
4623
4624 // UnConditional branch
4625 pipe_class pipe_jmp(label labl)
4626 %{
4627 single_instruction;
4628 BR : S3;
4629 %}
4630
4631 // Conditional branch
4632 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4633 %{
4634 single_instruction;
4635 cr : S1(read);
4636 BR : S3;
4637 %}
4638
4639 // Allocation idiom
4640 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4641 %{
4642 instruction_count(1); force_serialization;
4643 fixed_latency(6);
4644 heap_ptr : S3(read);
4645 DECODE : S0(3);
4646 D0 : S2;
4647 MEM : S3;
4648 ALU : S3(2);
4649 dst : S5(write);
4650 BR : S5;
4651 %}
4652
4653 // Generic big/slow expanded idiom
4654 pipe_class pipe_slow()
4655 %{
4656 instruction_count(10); multiple_bundles; force_serialization;
4657 fixed_latency(100);
4658 D0 : S0(2);
4659 MEM : S3(2);
4660 %}
4661
4662 // The real do-nothing guy
4663 pipe_class empty()
4664 %{
4665 instruction_count(0);
4666 %}
4667
4668 // Define the class for the Nop node
4669 define
4670 %{
4671 MachNop = empty;
4672 %}
4673
4674 %}
4675
4676 //----------INSTRUCTIONS-------------------------------------------------------
4677 //
4678 // match -- States which machine-independent subtree may be replaced
4679 // by this instruction.
4680 // ins_cost -- The estimated cost of this instruction is used by instruction
4681 // selection to identify a minimum cost tree of machine
4682 // instructions that matches a tree of machine-independent
4683 // instructions.
4684 // format -- A string providing the disassembly for this instruction.
4685 // The value of an instruction's operand may be inserted
4686 // by referring to it with a '$' prefix.
4687 // opcode -- Three instruction opcodes may be provided. These are referred
4688 // to within an encode class as $primary, $secondary, and $tertiary
4689 // rrspectively. The primary opcode is commonly used to
4690 // indicate the type of machine instruction, while secondary
4691 // and tertiary are often used for prefix options or addressing
4692 // modes.
4693 // ins_encode -- A list of encode classes with parameters. The encode class
4694 // name must have been defined in an 'enc_class' specification
4695 // in the encode section of the architecture description.
4696
4697
4698 //----------Load/Store/Move Instructions---------------------------------------
4699 //----------Load Instructions--------------------------------------------------
4700
4701 // Load Byte (8 bit signed)
4702 instruct loadB(rRegI dst, memory mem)
4703 %{
4704 match(Set dst (LoadB mem));
4705
4706 ins_cost(125);
4707 format %{ "movsbl $dst, $mem\t# byte" %}
4708
4709 ins_encode %{
4710 __ movsbl($dst$$Register, $mem$$Address);
4711 %}
4712
4713 ins_pipe(ialu_reg_mem);
4714 %}
4715
4716 // Load Byte (8 bit signed) into Long Register
4717 instruct loadB2L(rRegL dst, memory mem)
4718 %{
4719 match(Set dst (ConvI2L (LoadB mem)));
4720
4721 ins_cost(125);
4722 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4723
4724 ins_encode %{
4725 __ movsbq($dst$$Register, $mem$$Address);
4726 %}
4727
4728 ins_pipe(ialu_reg_mem);
4729 %}
4730
4731 // Load Unsigned Byte (8 bit UNsigned)
4732 instruct loadUB(rRegI dst, memory mem)
4733 %{
4734 match(Set dst (LoadUB mem));
4735
4736 ins_cost(125);
4737 format %{ "movzbl $dst, $mem\t# ubyte" %}
4738
4739 ins_encode %{
4740 __ movzbl($dst$$Register, $mem$$Address);
4741 %}
4742
4743 ins_pipe(ialu_reg_mem);
4744 %}
4745
4746 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4747 instruct loadUB2L(rRegL dst, memory mem)
4748 %{
4749 match(Set dst (ConvI2L (LoadUB mem)));
4750
4751 ins_cost(125);
4752 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4753
4754 ins_encode %{
4755 __ movzbq($dst$$Register, $mem$$Address);
4756 %}
4757
4758 ins_pipe(ialu_reg_mem);
4759 %}
4760
4761 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4762 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4763 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4764 effect(KILL cr);
4765
4766 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4767 "andl $dst, right_n_bits($mask, 8)" %}
4768 ins_encode %{
4769 Register Rdst = $dst$$Register;
4770 __ movzbq(Rdst, $mem$$Address);
4771 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4772 %}
4773 ins_pipe(ialu_reg_mem);
4774 %}
4775
4776 // Load Short (16 bit signed)
4777 instruct loadS(rRegI dst, memory mem)
4778 %{
4779 match(Set dst (LoadS mem));
4780
4781 ins_cost(125);
4782 format %{ "movswl $dst, $mem\t# short" %}
4783
4784 ins_encode %{
4785 __ movswl($dst$$Register, $mem$$Address);
4786 %}
4787
4788 ins_pipe(ialu_reg_mem);
4789 %}
4790
4791 // Load Short (16 bit signed) to Byte (8 bit signed)
4792 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4793 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4794
4795 ins_cost(125);
4796 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4797 ins_encode %{
4798 __ movsbl($dst$$Register, $mem$$Address);
4799 %}
4800 ins_pipe(ialu_reg_mem);
4801 %}
4802
4803 // Load Short (16 bit signed) into Long Register
4804 instruct loadS2L(rRegL dst, memory mem)
4805 %{
4806 match(Set dst (ConvI2L (LoadS mem)));
4807
4808 ins_cost(125);
4809 format %{ "movswq $dst, $mem\t# short -> long" %}
4810
4811 ins_encode %{
4812 __ movswq($dst$$Register, $mem$$Address);
4813 %}
4814
4815 ins_pipe(ialu_reg_mem);
4816 %}
4817
4818 // Load Unsigned Short/Char (16 bit UNsigned)
4819 instruct loadUS(rRegI dst, memory mem)
4820 %{
4821 match(Set dst (LoadUS mem));
4822
4823 ins_cost(125);
4824 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4825
4826 ins_encode %{
4827 __ movzwl($dst$$Register, $mem$$Address);
4828 %}
4829
4830 ins_pipe(ialu_reg_mem);
4831 %}
4832
4833 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4834 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4835 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4836
4837 ins_cost(125);
4838 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4839 ins_encode %{
4840 __ movsbl($dst$$Register, $mem$$Address);
4841 %}
4842 ins_pipe(ialu_reg_mem);
4843 %}
4844
4845 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4846 instruct loadUS2L(rRegL dst, memory mem)
4847 %{
4848 match(Set dst (ConvI2L (LoadUS mem)));
4849
4850 ins_cost(125);
4851 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4852
4853 ins_encode %{
4854 __ movzwq($dst$$Register, $mem$$Address);
4855 %}
4856
4857 ins_pipe(ialu_reg_mem);
4858 %}
4859
4860 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4861 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4862 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4863
4864 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4865 ins_encode %{
4866 __ movzbq($dst$$Register, $mem$$Address);
4867 %}
4868 ins_pipe(ialu_reg_mem);
4869 %}
4870
4871 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4872 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4873 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4874 effect(KILL cr);
4875
4876 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4877 "andl $dst, right_n_bits($mask, 16)" %}
4878 ins_encode %{
4879 Register Rdst = $dst$$Register;
4880 __ movzwq(Rdst, $mem$$Address);
4881 __ andl(Rdst, $mask$$constant & right_n_bits(16));
4882 %}
4883 ins_pipe(ialu_reg_mem);
4884 %}
4885
4886 // Load Integer
4887 instruct loadI(rRegI dst, memory mem)
4888 %{
4889 match(Set dst (LoadI mem));
4890
4891 ins_cost(125);
4892 format %{ "movl $dst, $mem\t# int" %}
4893
4894 ins_encode %{
4895 __ movl($dst$$Register, $mem$$Address);
4896 %}
4897
4898 ins_pipe(ialu_reg_mem);
4899 %}
4900
4901 // Load Integer (32 bit signed) to Byte (8 bit signed)
4902 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4903 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4904
4905 ins_cost(125);
4906 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4907 ins_encode %{
4908 __ movsbl($dst$$Register, $mem$$Address);
4909 %}
4910 ins_pipe(ialu_reg_mem);
4911 %}
4912
4913 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4914 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4915 match(Set dst (AndI (LoadI mem) mask));
4916
4917 ins_cost(125);
4918 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4919 ins_encode %{
4920 __ movzbl($dst$$Register, $mem$$Address);
4921 %}
4922 ins_pipe(ialu_reg_mem);
4923 %}
4924
4925 // Load Integer (32 bit signed) to Short (16 bit signed)
4926 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4927 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4928
4929 ins_cost(125);
4930 format %{ "movswl $dst, $mem\t# int -> short" %}
4931 ins_encode %{
4932 __ movswl($dst$$Register, $mem$$Address);
4933 %}
4934 ins_pipe(ialu_reg_mem);
4935 %}
4936
4937 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4938 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4939 match(Set dst (AndI (LoadI mem) mask));
4940
4941 ins_cost(125);
4942 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4943 ins_encode %{
4944 __ movzwl($dst$$Register, $mem$$Address);
4945 %}
4946 ins_pipe(ialu_reg_mem);
4947 %}
4948
4949 // Load Integer into Long Register
4950 instruct loadI2L(rRegL dst, memory mem)
4951 %{
4952 match(Set dst (ConvI2L (LoadI mem)));
4953
4954 ins_cost(125);
4955 format %{ "movslq $dst, $mem\t# int -> long" %}
4956
4957 ins_encode %{
4958 __ movslq($dst$$Register, $mem$$Address);
4959 %}
4960
4961 ins_pipe(ialu_reg_mem);
4962 %}
4963
4964 // Load Integer with mask 0xFF into Long Register
4965 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4966 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4967
4968 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
4969 ins_encode %{
4970 __ movzbq($dst$$Register, $mem$$Address);
4971 %}
4972 ins_pipe(ialu_reg_mem);
4973 %}
4974
4975 // Load Integer with mask 0xFFFF into Long Register
4976 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
4977 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4978
4979 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
4980 ins_encode %{
4981 __ movzwq($dst$$Register, $mem$$Address);
4982 %}
4983 ins_pipe(ialu_reg_mem);
4984 %}
4985
4986 // Load Integer with a 31-bit mask into Long Register
4987 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
4988 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4989 effect(KILL cr);
4990
4991 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
4992 "andl $dst, $mask" %}
4993 ins_encode %{
4994 Register Rdst = $dst$$Register;
4995 __ movl(Rdst, $mem$$Address);
4996 __ andl(Rdst, $mask$$constant);
4997 %}
4998 ins_pipe(ialu_reg_mem);
4999 %}
5000
5001 // Load Unsigned Integer into Long Register
5002 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5003 %{
5004 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5005
5006 ins_cost(125);
5007 format %{ "movl $dst, $mem\t# uint -> long" %}
5008
5009 ins_encode %{
5010 __ movl($dst$$Register, $mem$$Address);
5011 %}
5012
5013 ins_pipe(ialu_reg_mem);
5014 %}
5015
5016 // Load Long
5017 instruct loadL(rRegL dst, memory mem)
5018 %{
5019 match(Set dst (LoadL mem));
5020
5021 ins_cost(125);
5022 format %{ "movq $dst, $mem\t# long" %}
5023
5024 ins_encode %{
5025 __ movq($dst$$Register, $mem$$Address);
5026 %}
5027
5028 ins_pipe(ialu_reg_mem); // XXX
5029 %}
5030
5031 // Load Range
5032 instruct loadRange(rRegI dst, memory mem)
5033 %{
5034 match(Set dst (LoadRange mem));
5035
5036 ins_cost(125); // XXX
5037 format %{ "movl $dst, $mem\t# range" %}
5038 opcode(0x8B);
5039 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5040 ins_pipe(ialu_reg_mem);
5041 %}
5042
5043 // Load Pointer
5044 instruct loadP(rRegP dst, memory mem)
5045 %{
5046 match(Set dst (LoadP mem));
5047
5048 ins_cost(125); // XXX
5049 format %{ "movq $dst, $mem\t# ptr" %}
5050 opcode(0x8B);
5051 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5052 ins_pipe(ialu_reg_mem); // XXX
5053 %}
5054
5055 // Load Compressed Pointer
5056 instruct loadN(rRegN dst, memory mem)
5057 %{
5058 match(Set dst (LoadN mem));
5059
5060 ins_cost(125); // XXX
5061 format %{ "movl $dst, $mem\t# compressed ptr" %}
5062 ins_encode %{
5063 __ movl($dst$$Register, $mem$$Address);
5064 %}
5065 ins_pipe(ialu_reg_mem); // XXX
5066 %}
5067
5068
5069 // Load Klass Pointer
5070 instruct loadKlass(rRegP dst, memory mem)
5071 %{
5072 match(Set dst (LoadKlass mem));
5073
5074 ins_cost(125); // XXX
5075 format %{ "movq $dst, $mem\t# class" %}
5076 opcode(0x8B);
5077 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5078 ins_pipe(ialu_reg_mem); // XXX
5079 %}
5080
5081 // Load narrow Klass Pointer
5082 instruct loadNKlass(rRegN dst, memory mem)
5083 %{
5084 match(Set dst (LoadNKlass mem));
5085
5086 ins_cost(125); // XXX
5087 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5088 ins_encode %{
5089 __ movl($dst$$Register, $mem$$Address);
5090 %}
5091 ins_pipe(ialu_reg_mem); // XXX
5092 %}
5093
5094 // Load Float
5095 instruct loadF(regF dst, memory mem)
5096 %{
5097 match(Set dst (LoadF mem));
5098
5099 ins_cost(145); // XXX
5100 format %{ "movss $dst, $mem\t# float" %}
5101 ins_encode %{
5102 __ movflt($dst$$XMMRegister, $mem$$Address);
5103 %}
5104 ins_pipe(pipe_slow); // XXX
5105 %}
5106
5107 // Load Double
5108 instruct loadD_partial(regD dst, memory mem)
5109 %{
5110 predicate(!UseXmmLoadAndClearUpper);
5111 match(Set dst (LoadD mem));
5112
5113 ins_cost(145); // XXX
5114 format %{ "movlpd $dst, $mem\t# double" %}
5115 ins_encode %{
5116 __ movdbl($dst$$XMMRegister, $mem$$Address);
5117 %}
5118 ins_pipe(pipe_slow); // XXX
5119 %}
5120
5121 instruct loadD(regD dst, memory mem)
5122 %{
5123 predicate(UseXmmLoadAndClearUpper);
5124 match(Set dst (LoadD mem));
5125
5126 ins_cost(145); // XXX
5127 format %{ "movsd $dst, $mem\t# double" %}
5128 ins_encode %{
5129 __ movdbl($dst$$XMMRegister, $mem$$Address);
5130 %}
5131 ins_pipe(pipe_slow); // XXX
5132 %}
5133
5134 // Load Effective Address
5135 instruct leaP8(rRegP dst, indOffset8 mem)
5136 %{
5137 match(Set dst mem);
5138
5139 ins_cost(110); // XXX
5140 format %{ "leaq $dst, $mem\t# ptr 8" %}
5141 opcode(0x8D);
5142 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5143 ins_pipe(ialu_reg_reg_fat);
5144 %}
5145
5146 instruct leaP32(rRegP dst, indOffset32 mem)
5147 %{
5148 match(Set dst mem);
5149
5150 ins_cost(110);
5151 format %{ "leaq $dst, $mem\t# ptr 32" %}
5152 opcode(0x8D);
5153 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5154 ins_pipe(ialu_reg_reg_fat);
5155 %}
5156
5157 // instruct leaPIdx(rRegP dst, indIndex mem)
5158 // %{
5159 // match(Set dst mem);
5160
5161 // ins_cost(110);
5162 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5163 // opcode(0x8D);
5164 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5165 // ins_pipe(ialu_reg_reg_fat);
5166 // %}
5167
5168 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5169 %{
5170 match(Set dst mem);
5171
5172 ins_cost(110);
5173 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5174 opcode(0x8D);
5175 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5176 ins_pipe(ialu_reg_reg_fat);
5177 %}
5178
5179 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5180 %{
5181 match(Set dst mem);
5182
5183 ins_cost(110);
5184 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5185 opcode(0x8D);
5186 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5187 ins_pipe(ialu_reg_reg_fat);
5188 %}
5189
5190 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5191 %{
5192 match(Set dst mem);
5193
5194 ins_cost(110);
5195 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5196 opcode(0x8D);
5197 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5198 ins_pipe(ialu_reg_reg_fat);
5199 %}
5200
5201 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5202 %{
5203 match(Set dst mem);
5204
5205 ins_cost(110);
5206 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5207 opcode(0x8D);
5208 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5209 ins_pipe(ialu_reg_reg_fat);
5210 %}
5211
5212 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5213 %{
5214 match(Set dst mem);
5215
5216 ins_cost(110);
5217 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5218 opcode(0x8D);
5219 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5220 ins_pipe(ialu_reg_reg_fat);
5221 %}
5222
5223 // Load Effective Address which uses Narrow (32-bits) oop
5224 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5225 %{
5226 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5227 match(Set dst mem);
5228
5229 ins_cost(110);
5230 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5231 opcode(0x8D);
5232 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5233 ins_pipe(ialu_reg_reg_fat);
5234 %}
5235
5236 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5237 %{
5238 predicate(Universe::narrow_oop_shift() == 0);
5239 match(Set dst mem);
5240
5241 ins_cost(110); // XXX
5242 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5243 opcode(0x8D);
5244 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5245 ins_pipe(ialu_reg_reg_fat);
5246 %}
5247
5248 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5249 %{
5250 predicate(Universe::narrow_oop_shift() == 0);
5251 match(Set dst mem);
5252
5253 ins_cost(110);
5254 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5255 opcode(0x8D);
5256 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5257 ins_pipe(ialu_reg_reg_fat);
5258 %}
5259
5260 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5261 %{
5262 predicate(Universe::narrow_oop_shift() == 0);
5263 match(Set dst mem);
5264
5265 ins_cost(110);
5266 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5267 opcode(0x8D);
5268 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5269 ins_pipe(ialu_reg_reg_fat);
5270 %}
5271
5272 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5273 %{
5274 predicate(Universe::narrow_oop_shift() == 0);
5275 match(Set dst mem);
5276
5277 ins_cost(110);
5278 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5279 opcode(0x8D);
5280 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5281 ins_pipe(ialu_reg_reg_fat);
5282 %}
5283
5284 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5285 %{
5286 predicate(Universe::narrow_oop_shift() == 0);
5287 match(Set dst mem);
5288
5289 ins_cost(110);
5290 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5291 opcode(0x8D);
5292 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5293 ins_pipe(ialu_reg_reg_fat);
5294 %}
5295
5296 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5297 %{
5298 predicate(Universe::narrow_oop_shift() == 0);
5299 match(Set dst mem);
5300
5301 ins_cost(110);
5302 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5303 opcode(0x8D);
5304 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5305 ins_pipe(ialu_reg_reg_fat);
5306 %}
5307
5308 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5309 %{
5310 predicate(Universe::narrow_oop_shift() == 0);
5311 match(Set dst mem);
5312
5313 ins_cost(110);
5314 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5315 opcode(0x8D);
5316 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5317 ins_pipe(ialu_reg_reg_fat);
5318 %}
5319
5320 instruct loadConI(rRegI dst, immI src)
5321 %{
5322 match(Set dst src);
5323
5324 format %{ "movl $dst, $src\t# int" %}
5325 ins_encode(load_immI(dst, src));
5326 ins_pipe(ialu_reg_fat); // XXX
5327 %}
5328
5329 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5330 %{
5331 match(Set dst src);
5332 effect(KILL cr);
5333
5334 ins_cost(50);
5335 format %{ "xorl $dst, $dst\t# int" %}
5336 opcode(0x33); /* + rd */
5337 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5338 ins_pipe(ialu_reg);
5339 %}
5340
5341 instruct loadConL(rRegL dst, immL src)
5342 %{
5343 match(Set dst src);
5344
5345 ins_cost(150);
5346 format %{ "movq $dst, $src\t# long" %}
5347 ins_encode(load_immL(dst, src));
5348 ins_pipe(ialu_reg);
5349 %}
5350
5351 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5352 %{
5353 match(Set dst src);
5354 effect(KILL cr);
5355
5356 ins_cost(50);
5357 format %{ "xorl $dst, $dst\t# long" %}
5358 opcode(0x33); /* + rd */
5359 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5360 ins_pipe(ialu_reg); // XXX
5361 %}
5362
5363 instruct loadConUL32(rRegL dst, immUL32 src)
5364 %{
5365 match(Set dst src);
5366
5367 ins_cost(60);
5368 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5369 ins_encode(load_immUL32(dst, src));
5370 ins_pipe(ialu_reg);
5371 %}
5372
5373 instruct loadConL32(rRegL dst, immL32 src)
5374 %{
5375 match(Set dst src);
5376
5377 ins_cost(70);
5378 format %{ "movq $dst, $src\t# long (32-bit)" %}
5379 ins_encode(load_immL32(dst, src));
5380 ins_pipe(ialu_reg);
5381 %}
5382
5383 instruct loadConP(rRegP dst, immP con) %{
5384 match(Set dst con);
5385
5386 format %{ "movq $dst, $con\t# ptr" %}
5387 ins_encode(load_immP(dst, con));
5388 ins_pipe(ialu_reg_fat); // XXX
5389 %}
5390
5391 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5392 %{
5393 match(Set dst src);
5394 effect(KILL cr);
5395
5396 ins_cost(50);
5397 format %{ "xorl $dst, $dst\t# ptr" %}
5398 opcode(0x33); /* + rd */
5399 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5400 ins_pipe(ialu_reg);
5401 %}
5402
5403 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5404 %{
5405 match(Set dst src);
5406 effect(KILL cr);
5407
5408 ins_cost(60);
5409 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5410 ins_encode(load_immP31(dst, src));
5411 ins_pipe(ialu_reg);
5412 %}
5413
5414 instruct loadConF(regF dst, immF con) %{
5415 match(Set dst con);
5416 ins_cost(125);
5417 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5418 ins_encode %{
5419 __ movflt($dst$$XMMRegister, $constantaddress($con));
5420 %}
5421 ins_pipe(pipe_slow);
5422 %}
5423
5424 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5425 match(Set dst src);
5426 effect(KILL cr);
5427 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5428 ins_encode %{
5429 __ xorq($dst$$Register, $dst$$Register);
5430 %}
5431 ins_pipe(ialu_reg);
5432 %}
5433
5434 instruct loadConN(rRegN dst, immN src) %{
5435 match(Set dst src);
5436
5437 ins_cost(125);
5438 format %{ "movl $dst, $src\t# compressed ptr" %}
5439 ins_encode %{
5440 address con = (address)$src$$constant;
5441 if (con == NULL) {
5442 ShouldNotReachHere();
5443 } else {
5444 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5445 }
5446 %}
5447 ins_pipe(ialu_reg_fat); // XXX
5448 %}
5449
5450 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5451 match(Set dst src);
5452
5453 ins_cost(125);
5454 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5455 ins_encode %{
5456 address con = (address)$src$$constant;
5457 if (con == NULL) {
5458 ShouldNotReachHere();
5459 } else {
5460 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5461 }
5462 %}
5463 ins_pipe(ialu_reg_fat); // XXX
5464 %}
5465
5466 instruct loadConF0(regF dst, immF0 src)
5467 %{
5468 match(Set dst src);
5469 ins_cost(100);
5470
5471 format %{ "xorps $dst, $dst\t# float 0.0" %}
5472 ins_encode %{
5473 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5474 %}
5475 ins_pipe(pipe_slow);
5476 %}
5477
5478 // Use the same format since predicate() can not be used here.
5479 instruct loadConD(regD dst, immD con) %{
5480 match(Set dst con);
5481 ins_cost(125);
5482 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5483 ins_encode %{
5484 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5485 %}
5486 ins_pipe(pipe_slow);
5487 %}
5488
5489 instruct loadConD0(regD dst, immD0 src)
5490 %{
5491 match(Set dst src);
5492 ins_cost(100);
5493
5494 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5495 ins_encode %{
5496 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5497 %}
5498 ins_pipe(pipe_slow);
5499 %}
5500
5501 instruct loadSSI(rRegI dst, stackSlotI src)
5502 %{
5503 match(Set dst src);
5504
5505 ins_cost(125);
5506 format %{ "movl $dst, $src\t# int stk" %}
5507 opcode(0x8B);
5508 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5509 ins_pipe(ialu_reg_mem);
5510 %}
5511
5512 instruct loadSSL(rRegL dst, stackSlotL src)
5513 %{
5514 match(Set dst src);
5515
5516 ins_cost(125);
5517 format %{ "movq $dst, $src\t# long stk" %}
5518 opcode(0x8B);
5519 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5520 ins_pipe(ialu_reg_mem);
5521 %}
5522
5523 instruct loadSSP(rRegP dst, stackSlotP src)
5524 %{
5525 match(Set dst src);
5526
5527 ins_cost(125);
5528 format %{ "movq $dst, $src\t# ptr stk" %}
5529 opcode(0x8B);
5530 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5531 ins_pipe(ialu_reg_mem);
5532 %}
5533
5534 instruct loadSSF(regF dst, stackSlotF src)
5535 %{
5536 match(Set dst src);
5537
5538 ins_cost(125);
5539 format %{ "movss $dst, $src\t# float stk" %}
5540 ins_encode %{
5541 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5542 %}
5543 ins_pipe(pipe_slow); // XXX
5544 %}
5545
5546 // Use the same format since predicate() can not be used here.
5547 instruct loadSSD(regD dst, stackSlotD src)
5548 %{
5549 match(Set dst src);
5550
5551 ins_cost(125);
5552 format %{ "movsd $dst, $src\t# double stk" %}
5553 ins_encode %{
5554 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5555 %}
5556 ins_pipe(pipe_slow); // XXX
5557 %}
5558
5559 // Prefetch instructions for allocation.
5560 // Must be safe to execute with invalid address (cannot fault).
5561
5562 instruct prefetchAlloc( memory mem ) %{
5563 predicate(AllocatePrefetchInstr==3);
5564 match(PrefetchAllocation mem);
5565 ins_cost(125);
5566
5567 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5568 ins_encode %{
5569 __ prefetchw($mem$$Address);
5570 %}
5571 ins_pipe(ialu_mem);
5572 %}
5573
5574 instruct prefetchAllocNTA( memory mem ) %{
5575 predicate(AllocatePrefetchInstr==0);
5576 match(PrefetchAllocation mem);
5577 ins_cost(125);
5578
5579 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5580 ins_encode %{
5581 __ prefetchnta($mem$$Address);
5582 %}
5583 ins_pipe(ialu_mem);
5584 %}
5585
5586 instruct prefetchAllocT0( memory mem ) %{
5587 predicate(AllocatePrefetchInstr==1);
5588 match(PrefetchAllocation mem);
5589 ins_cost(125);
5590
5591 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5592 ins_encode %{
5593 __ prefetcht0($mem$$Address);
5594 %}
5595 ins_pipe(ialu_mem);
5596 %}
5597
5598 instruct prefetchAllocT2( memory mem ) %{
5599 predicate(AllocatePrefetchInstr==2);
5600 match(PrefetchAllocation mem);
5601 ins_cost(125);
5602
5603 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5604 ins_encode %{
5605 __ prefetcht2($mem$$Address);
5606 %}
5607 ins_pipe(ialu_mem);
5608 %}
5609
5610 //----------Store Instructions-------------------------------------------------
5611
5612 // Store Byte
5613 instruct storeB(memory mem, rRegI src)
5614 %{
5615 match(Set mem (StoreB mem src));
5616
5617 ins_cost(125); // XXX
5618 format %{ "movb $mem, $src\t# byte" %}
5619 opcode(0x88);
5620 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5621 ins_pipe(ialu_mem_reg);
5622 %}
5623
5624 // Store Char/Short
5625 instruct storeC(memory mem, rRegI src)
5626 %{
5627 match(Set mem (StoreC mem src));
5628
5629 ins_cost(125); // XXX
5630 format %{ "movw $mem, $src\t# char/short" %}
5631 opcode(0x89);
5632 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5633 ins_pipe(ialu_mem_reg);
5634 %}
5635
5636 // Store Integer
5637 instruct storeI(memory mem, rRegI src)
5638 %{
5639 match(Set mem (StoreI mem src));
5640
5641 ins_cost(125); // XXX
5642 format %{ "movl $mem, $src\t# int" %}
5643 opcode(0x89);
5644 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5645 ins_pipe(ialu_mem_reg);
5646 %}
5647
5648 // Store Long
5649 instruct storeL(memory mem, rRegL src)
5650 %{
5651 match(Set mem (StoreL mem src));
5652
5653 ins_cost(125); // XXX
5654 format %{ "movq $mem, $src\t# long" %}
5655 opcode(0x89);
5656 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5657 ins_pipe(ialu_mem_reg); // XXX
5658 %}
5659
5660 // Store Pointer
5661 instruct storeP(memory mem, any_RegP src)
5662 %{
5663 match(Set mem (StoreP mem src));
5664
5665 ins_cost(125); // XXX
5666 format %{ "movq $mem, $src\t# ptr" %}
5667 opcode(0x89);
5668 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5669 ins_pipe(ialu_mem_reg);
5670 %}
5671
5672 instruct storeImmP0(memory mem, immP0 zero)
5673 %{
5674 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5675 match(Set mem (StoreP mem zero));
5676
5677 ins_cost(125); // XXX
5678 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5679 ins_encode %{
5680 __ movq($mem$$Address, r12);
5681 %}
5682 ins_pipe(ialu_mem_reg);
5683 %}
5684
5685 // Store NULL Pointer, mark word, or other simple pointer constant.
5686 instruct storeImmP(memory mem, immP31 src)
5687 %{
5688 match(Set mem (StoreP mem src));
5689
5690 ins_cost(150); // XXX
5691 format %{ "movq $mem, $src\t# ptr" %}
5692 opcode(0xC7); /* C7 /0 */
5693 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5694 ins_pipe(ialu_mem_imm);
5695 %}
5696
5697 // Store Compressed Pointer
5698 instruct storeN(memory mem, rRegN src)
5699 %{
5700 match(Set mem (StoreN mem src));
5701
5702 ins_cost(125); // XXX
5703 format %{ "movl $mem, $src\t# compressed ptr" %}
5704 ins_encode %{
5705 __ movl($mem$$Address, $src$$Register);
5706 %}
5707 ins_pipe(ialu_mem_reg);
5708 %}
5709
5710 instruct storeNKlass(memory mem, rRegN src)
5711 %{
5712 match(Set mem (StoreNKlass mem src));
5713
5714 ins_cost(125); // XXX
5715 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5716 ins_encode %{
5717 __ movl($mem$$Address, $src$$Register);
5718 %}
5719 ins_pipe(ialu_mem_reg);
5720 %}
5721
5722 instruct storeImmN0(memory mem, immN0 zero)
5723 %{
5724 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
5725 match(Set mem (StoreN mem zero));
5726
5727 ins_cost(125); // XXX
5728 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5729 ins_encode %{
5730 __ movl($mem$$Address, r12);
5731 %}
5732 ins_pipe(ialu_mem_reg);
5733 %}
5734
5735 instruct storeImmN(memory mem, immN src)
5736 %{
5737 match(Set mem (StoreN mem src));
5738
5739 ins_cost(150); // XXX
5740 format %{ "movl $mem, $src\t# compressed ptr" %}
5741 ins_encode %{
5742 address con = (address)$src$$constant;
5743 if (con == NULL) {
5744 __ movl($mem$$Address, (int32_t)0);
5745 } else {
5746 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5747 }
5748 %}
5749 ins_pipe(ialu_mem_imm);
5750 %}
5751
5752 instruct storeImmNKlass(memory mem, immNKlass src)
5753 %{
5754 match(Set mem (StoreNKlass mem src));
5755
5756 ins_cost(150); // XXX
5757 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5758 ins_encode %{
5759 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5760 %}
5761 ins_pipe(ialu_mem_imm);
5762 %}
5763
5764 // Store Integer Immediate
5765 instruct storeImmI0(memory mem, immI0 zero)
5766 %{
5767 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5768 match(Set mem (StoreI mem zero));
5769
5770 ins_cost(125); // XXX
5771 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5772 ins_encode %{
5773 __ movl($mem$$Address, r12);
5774 %}
5775 ins_pipe(ialu_mem_reg);
5776 %}
5777
5778 instruct storeImmI(memory mem, immI src)
5779 %{
5780 match(Set mem (StoreI mem src));
5781
5782 ins_cost(150);
5783 format %{ "movl $mem, $src\t# int" %}
5784 opcode(0xC7); /* C7 /0 */
5785 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5786 ins_pipe(ialu_mem_imm);
5787 %}
5788
5789 // Store Long Immediate
5790 instruct storeImmL0(memory mem, immL0 zero)
5791 %{
5792 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5793 match(Set mem (StoreL mem zero));
5794
5795 ins_cost(125); // XXX
5796 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5797 ins_encode %{
5798 __ movq($mem$$Address, r12);
5799 %}
5800 ins_pipe(ialu_mem_reg);
5801 %}
5802
5803 instruct storeImmL(memory mem, immL32 src)
5804 %{
5805 match(Set mem (StoreL mem src));
5806
5807 ins_cost(150);
5808 format %{ "movq $mem, $src\t# long" %}
5809 opcode(0xC7); /* C7 /0 */
5810 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5811 ins_pipe(ialu_mem_imm);
5812 %}
5813
5814 // Store Short/Char Immediate
5815 instruct storeImmC0(memory mem, immI0 zero)
5816 %{
5817 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5818 match(Set mem (StoreC mem zero));
5819
5820 ins_cost(125); // XXX
5821 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5822 ins_encode %{
5823 __ movw($mem$$Address, r12);
5824 %}
5825 ins_pipe(ialu_mem_reg);
5826 %}
5827
5828 instruct storeImmI16(memory mem, immI16 src)
5829 %{
5830 predicate(UseStoreImmI16);
5831 match(Set mem (StoreC mem src));
5832
5833 ins_cost(150);
5834 format %{ "movw $mem, $src\t# short/char" %}
5835 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
5836 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
5837 ins_pipe(ialu_mem_imm);
5838 %}
5839
5840 // Store Byte Immediate
5841 instruct storeImmB0(memory mem, immI0 zero)
5842 %{
5843 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5844 match(Set mem (StoreB mem zero));
5845
5846 ins_cost(125); // XXX
5847 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5848 ins_encode %{
5849 __ movb($mem$$Address, r12);
5850 %}
5851 ins_pipe(ialu_mem_reg);
5852 %}
5853
5854 instruct storeImmB(memory mem, immI8 src)
5855 %{
5856 match(Set mem (StoreB mem src));
5857
5858 ins_cost(150); // XXX
5859 format %{ "movb $mem, $src\t# byte" %}
5860 opcode(0xC6); /* C6 /0 */
5861 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5862 ins_pipe(ialu_mem_imm);
5863 %}
5864
5865 // Store CMS card-mark Immediate
5866 instruct storeImmCM0_reg(memory mem, immI0 zero)
5867 %{
5868 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5869 match(Set mem (StoreCM mem zero));
5870
5871 ins_cost(125); // XXX
5872 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5873 ins_encode %{
5874 __ movb($mem$$Address, r12);
5875 %}
5876 ins_pipe(ialu_mem_reg);
5877 %}
5878
5879 instruct storeImmCM0(memory mem, immI0 src)
5880 %{
5881 match(Set mem (StoreCM mem src));
5882
5883 ins_cost(150); // XXX
5884 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5885 opcode(0xC6); /* C6 /0 */
5886 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5887 ins_pipe(ialu_mem_imm);
5888 %}
5889
5890 // Store Float
5891 instruct storeF(memory mem, regF src)
5892 %{
5893 match(Set mem (StoreF mem src));
5894
5895 ins_cost(95); // XXX
5896 format %{ "movss $mem, $src\t# float" %}
5897 ins_encode %{
5898 __ movflt($mem$$Address, $src$$XMMRegister);
5899 %}
5900 ins_pipe(pipe_slow); // XXX
5901 %}
5902
5903 // Store immediate Float value (it is faster than store from XMM register)
5904 instruct storeF0(memory mem, immF0 zero)
5905 %{
5906 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5907 match(Set mem (StoreF mem zero));
5908
5909 ins_cost(25); // XXX
5910 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5911 ins_encode %{
5912 __ movl($mem$$Address, r12);
5913 %}
5914 ins_pipe(ialu_mem_reg);
5915 %}
5916
5917 instruct storeF_imm(memory mem, immF src)
5918 %{
5919 match(Set mem (StoreF mem src));
5920
5921 ins_cost(50);
5922 format %{ "movl $mem, $src\t# float" %}
5923 opcode(0xC7); /* C7 /0 */
5924 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5925 ins_pipe(ialu_mem_imm);
5926 %}
5927
5928 // Store Double
5929 instruct storeD(memory mem, regD src)
5930 %{
5931 match(Set mem (StoreD mem src));
5932
5933 ins_cost(95); // XXX
5934 format %{ "movsd $mem, $src\t# double" %}
5935 ins_encode %{
5936 __ movdbl($mem$$Address, $src$$XMMRegister);
5937 %}
5938 ins_pipe(pipe_slow); // XXX
5939 %}
5940
5941 // Store immediate double 0.0 (it is faster than store from XMM register)
5942 instruct storeD0_imm(memory mem, immD0 src)
5943 %{
5944 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
5945 match(Set mem (StoreD mem src));
5946
5947 ins_cost(50);
5948 format %{ "movq $mem, $src\t# double 0." %}
5949 opcode(0xC7); /* C7 /0 */
5950 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5951 ins_pipe(ialu_mem_imm);
5952 %}
5953
5954 instruct storeD0(memory mem, immD0 zero)
5955 %{
5956 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5957 match(Set mem (StoreD mem zero));
5958
5959 ins_cost(25); // XXX
5960 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
5961 ins_encode %{
5962 __ movq($mem$$Address, r12);
5963 %}
5964 ins_pipe(ialu_mem_reg);
5965 %}
5966
5967 instruct storeSSI(stackSlotI dst, rRegI src)
5968 %{
5969 match(Set dst src);
5970
5971 ins_cost(100);
5972 format %{ "movl $dst, $src\t# int stk" %}
5973 opcode(0x89);
5974 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
5975 ins_pipe( ialu_mem_reg );
5976 %}
5977
5978 instruct storeSSL(stackSlotL dst, rRegL src)
5979 %{
5980 match(Set dst src);
5981
5982 ins_cost(100);
5983 format %{ "movq $dst, $src\t# long stk" %}
5984 opcode(0x89);
5985 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
5986 ins_pipe(ialu_mem_reg);
5987 %}
5988
5989 instruct storeSSP(stackSlotP dst, rRegP src)
5990 %{
5991 match(Set dst src);
5992
5993 ins_cost(100);
5994 format %{ "movq $dst, $src\t# ptr stk" %}
5995 opcode(0x89);
5996 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
5997 ins_pipe(ialu_mem_reg);
5998 %}
5999
6000 instruct storeSSF(stackSlotF dst, regF src)
6001 %{
6002 match(Set dst src);
6003
6004 ins_cost(95); // XXX
6005 format %{ "movss $dst, $src\t# float stk" %}
6006 ins_encode %{
6007 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6008 %}
6009 ins_pipe(pipe_slow); // XXX
6010 %}
6011
6012 instruct storeSSD(stackSlotD dst, regD src)
6013 %{
6014 match(Set dst src);
6015
6016 ins_cost(95); // XXX
6017 format %{ "movsd $dst, $src\t# double stk" %}
6018 ins_encode %{
6019 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6020 %}
6021 ins_pipe(pipe_slow); // XXX
6022 %}
6023
6024 //----------BSWAP Instructions-------------------------------------------------
6025 instruct bytes_reverse_int(rRegI dst) %{
6026 match(Set dst (ReverseBytesI dst));
6027
6028 format %{ "bswapl $dst" %}
6029 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6030 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6031 ins_pipe( ialu_reg );
6032 %}
6033
6034 instruct bytes_reverse_long(rRegL dst) %{
6035 match(Set dst (ReverseBytesL dst));
6036
6037 format %{ "bswapq $dst" %}
6038 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6039 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6040 ins_pipe( ialu_reg);
6041 %}
6042
6043 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6044 match(Set dst (ReverseBytesUS dst));
6045 effect(KILL cr);
6046
6047 format %{ "bswapl $dst\n\t"
6048 "shrl $dst,16\n\t" %}
6049 ins_encode %{
6050 __ bswapl($dst$$Register);
6051 __ shrl($dst$$Register, 16);
6052 %}
6053 ins_pipe( ialu_reg );
6054 %}
6055
6056 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6057 match(Set dst (ReverseBytesS dst));
6058 effect(KILL cr);
6059
6060 format %{ "bswapl $dst\n\t"
6061 "sar $dst,16\n\t" %}
6062 ins_encode %{
6063 __ bswapl($dst$$Register);
6064 __ sarl($dst$$Register, 16);
6065 %}
6066 ins_pipe( ialu_reg );
6067 %}
6068
6069 //---------- Zeros Count Instructions ------------------------------------------
6070
6071 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6072 predicate(UseCountLeadingZerosInstruction);
6073 match(Set dst (CountLeadingZerosI src));
6074 effect(KILL cr);
6075
6076 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6077 ins_encode %{
6078 __ lzcntl($dst$$Register, $src$$Register);
6079 %}
6080 ins_pipe(ialu_reg);
6081 %}
6082
6083 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6084 predicate(!UseCountLeadingZerosInstruction);
6085 match(Set dst (CountLeadingZerosI src));
6086 effect(KILL cr);
6087
6088 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6089 "jnz skip\n\t"
6090 "movl $dst, -1\n"
6091 "skip:\n\t"
6092 "negl $dst\n\t"
6093 "addl $dst, 31" %}
6094 ins_encode %{
6095 Register Rdst = $dst$$Register;
6096 Register Rsrc = $src$$Register;
6097 Label skip;
6098 __ bsrl(Rdst, Rsrc);
6099 __ jccb(Assembler::notZero, skip);
6100 __ movl(Rdst, -1);
6101 __ bind(skip);
6102 __ negl(Rdst);
6103 __ addl(Rdst, BitsPerInt - 1);
6104 %}
6105 ins_pipe(ialu_reg);
6106 %}
6107
6108 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6109 predicate(UseCountLeadingZerosInstruction);
6110 match(Set dst (CountLeadingZerosL src));
6111 effect(KILL cr);
6112
6113 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6114 ins_encode %{
6115 __ lzcntq($dst$$Register, $src$$Register);
6116 %}
6117 ins_pipe(ialu_reg);
6118 %}
6119
6120 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6121 predicate(!UseCountLeadingZerosInstruction);
6122 match(Set dst (CountLeadingZerosL src));
6123 effect(KILL cr);
6124
6125 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6126 "jnz skip\n\t"
6127 "movl $dst, -1\n"
6128 "skip:\n\t"
6129 "negl $dst\n\t"
6130 "addl $dst, 63" %}
6131 ins_encode %{
6132 Register Rdst = $dst$$Register;
6133 Register Rsrc = $src$$Register;
6134 Label skip;
6135 __ bsrq(Rdst, Rsrc);
6136 __ jccb(Assembler::notZero, skip);
6137 __ movl(Rdst, -1);
6138 __ bind(skip);
6139 __ negl(Rdst);
6140 __ addl(Rdst, BitsPerLong - 1);
6141 %}
6142 ins_pipe(ialu_reg);
6143 %}
6144
6145 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6146 predicate(UseCountTrailingZerosInstruction);
6147 match(Set dst (CountTrailingZerosI src));
6148 effect(KILL cr);
6149
6150 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6151 ins_encode %{
6152 __ tzcntl($dst$$Register, $src$$Register);
6153 %}
6154 ins_pipe(ialu_reg);
6155 %}
6156
6157 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6158 predicate(!UseCountTrailingZerosInstruction);
6159 match(Set dst (CountTrailingZerosI src));
6160 effect(KILL cr);
6161
6162 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6163 "jnz done\n\t"
6164 "movl $dst, 32\n"
6165 "done:" %}
6166 ins_encode %{
6167 Register Rdst = $dst$$Register;
6168 Label done;
6169 __ bsfl(Rdst, $src$$Register);
6170 __ jccb(Assembler::notZero, done);
6171 __ movl(Rdst, BitsPerInt);
6172 __ bind(done);
6173 %}
6174 ins_pipe(ialu_reg);
6175 %}
6176
6177 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6178 predicate(UseCountTrailingZerosInstruction);
6179 match(Set dst (CountTrailingZerosL src));
6180 effect(KILL cr);
6181
6182 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6183 ins_encode %{
6184 __ tzcntq($dst$$Register, $src$$Register);
6185 %}
6186 ins_pipe(ialu_reg);
6187 %}
6188
6189 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6190 predicate(!UseCountTrailingZerosInstruction);
6191 match(Set dst (CountTrailingZerosL src));
6192 effect(KILL cr);
6193
6194 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6195 "jnz done\n\t"
6196 "movl $dst, 64\n"
6197 "done:" %}
6198 ins_encode %{
6199 Register Rdst = $dst$$Register;
6200 Label done;
6201 __ bsfq(Rdst, $src$$Register);
6202 __ jccb(Assembler::notZero, done);
6203 __ movl(Rdst, BitsPerLong);
6204 __ bind(done);
6205 %}
6206 ins_pipe(ialu_reg);
6207 %}
6208
6209
6210 //---------- Population Count Instructions -------------------------------------
6211
6212 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6213 predicate(UsePopCountInstruction);
6214 match(Set dst (PopCountI src));
6215 effect(KILL cr);
6216
6217 format %{ "popcnt $dst, $src" %}
6218 ins_encode %{
6219 __ popcntl($dst$$Register, $src$$Register);
6220 %}
6221 ins_pipe(ialu_reg);
6222 %}
6223
6224 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6225 predicate(UsePopCountInstruction);
6226 match(Set dst (PopCountI (LoadI mem)));
6227 effect(KILL cr);
6228
6229 format %{ "popcnt $dst, $mem" %}
6230 ins_encode %{
6231 __ popcntl($dst$$Register, $mem$$Address);
6232 %}
6233 ins_pipe(ialu_reg);
6234 %}
6235
6236 // Note: Long.bitCount(long) returns an int.
6237 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6238 predicate(UsePopCountInstruction);
6239 match(Set dst (PopCountL src));
6240 effect(KILL cr);
6241
6242 format %{ "popcnt $dst, $src" %}
6243 ins_encode %{
6244 __ popcntq($dst$$Register, $src$$Register);
6245 %}
6246 ins_pipe(ialu_reg);
6247 %}
6248
6249 // Note: Long.bitCount(long) returns an int.
6250 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6251 predicate(UsePopCountInstruction);
6252 match(Set dst (PopCountL (LoadL mem)));
6253 effect(KILL cr);
6254
6255 format %{ "popcnt $dst, $mem" %}
6256 ins_encode %{
6257 __ popcntq($dst$$Register, $mem$$Address);
6258 %}
6259 ins_pipe(ialu_reg);
6260 %}
6261
6262
6263 //----------MemBar Instructions-----------------------------------------------
6264 // Memory barrier flavors
6265
6266 instruct membar_acquire()
6267 %{
6268 match(MemBarAcquire);
6269 match(LoadFence);
6270 ins_cost(0);
6271
6272 size(0);
6273 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6274 ins_encode();
6275 ins_pipe(empty);
6276 %}
6277
6278 instruct membar_acquire_lock()
6279 %{
6280 match(MemBarAcquireLock);
6281 ins_cost(0);
6282
6283 size(0);
6284 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6285 ins_encode();
6286 ins_pipe(empty);
6287 %}
6288
6289 instruct membar_release()
6290 %{
6291 match(MemBarRelease);
6292 match(StoreFence);
6293 ins_cost(0);
6294
6295 size(0);
6296 format %{ "MEMBAR-release ! (empty encoding)" %}
6297 ins_encode();
6298 ins_pipe(empty);
6299 %}
6300
6301 instruct membar_release_lock()
6302 %{
6303 match(MemBarReleaseLock);
6304 ins_cost(0);
6305
6306 size(0);
6307 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6308 ins_encode();
6309 ins_pipe(empty);
6310 %}
6311
6312 instruct membar_volatile(rFlagsReg cr) %{
6313 match(MemBarVolatile);
6314 effect(KILL cr);
6315 ins_cost(400);
6316
6317 format %{
6318 $$template
6319 if (os::is_MP()) {
6320 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6321 } else {
6322 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6323 }
6324 %}
6325 ins_encode %{
6326 __ membar(Assembler::StoreLoad);
6327 %}
6328 ins_pipe(pipe_slow);
6329 %}
6330
6331 instruct unnecessary_membar_volatile()
6332 %{
6333 match(MemBarVolatile);
6334 predicate(Matcher::post_store_load_barrier(n));
6335 ins_cost(0);
6336
6337 size(0);
6338 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6339 ins_encode();
6340 ins_pipe(empty);
6341 %}
6342
6343 instruct membar_storestore() %{
6344 match(MemBarStoreStore);
6345 ins_cost(0);
6346
6347 size(0);
6348 format %{ "MEMBAR-storestore (empty encoding)" %}
6349 ins_encode( );
6350 ins_pipe(empty);
6351 %}
6352
6353 //----------Move Instructions--------------------------------------------------
6354
6355 instruct castX2P(rRegP dst, rRegL src)
6356 %{
6357 match(Set dst (CastX2P src));
6358
6359 format %{ "movq $dst, $src\t# long->ptr" %}
6360 ins_encode %{
6361 if ($dst$$reg != $src$$reg) {
6362 __ movptr($dst$$Register, $src$$Register);
6363 }
6364 %}
6365 ins_pipe(ialu_reg_reg); // XXX
6366 %}
6367
6368 instruct castP2X(rRegL dst, rRegP src)
6369 %{
6370 match(Set dst (CastP2X src));
6371
6372 format %{ "movq $dst, $src\t# ptr -> long" %}
6373 ins_encode %{
6374 if ($dst$$reg != $src$$reg) {
6375 __ movptr($dst$$Register, $src$$Register);
6376 }
6377 %}
6378 ins_pipe(ialu_reg_reg); // XXX
6379 %}
6380
6381 // Convert oop into int for vectors alignment masking
6382 instruct convP2I(rRegI dst, rRegP src)
6383 %{
6384 match(Set dst (ConvL2I (CastP2X src)));
6385
6386 format %{ "movl $dst, $src\t# ptr -> int" %}
6387 ins_encode %{
6388 __ movl($dst$$Register, $src$$Register);
6389 %}
6390 ins_pipe(ialu_reg_reg); // XXX
6391 %}
6392
6393 // Convert compressed oop into int for vectors alignment masking
6394 // in case of 32bit oops (heap < 4Gb).
6395 instruct convN2I(rRegI dst, rRegN src)
6396 %{
6397 predicate(Universe::narrow_oop_shift() == 0);
6398 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6399
6400 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6401 ins_encode %{
6402 __ movl($dst$$Register, $src$$Register);
6403 %}
6404 ins_pipe(ialu_reg_reg); // XXX
6405 %}
6406
6407 // Convert oop pointer into compressed form
6408 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6409 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6410 match(Set dst (EncodeP src));
6411 effect(KILL cr);
6412 format %{ "encode_heap_oop $dst,$src" %}
6413 ins_encode %{
6414 Register s = $src$$Register;
6415 Register d = $dst$$Register;
6416 if (s != d) {
6417 __ movq(d, s);
6418 }
6419 __ encode_heap_oop(d);
6420 %}
6421 ins_pipe(ialu_reg_long);
6422 %}
6423
6424 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6425 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6426 match(Set dst (EncodeP src));
6427 effect(KILL cr);
6428 format %{ "encode_heap_oop_not_null $dst,$src" %}
6429 ins_encode %{
6430 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6431 %}
6432 ins_pipe(ialu_reg_long);
6433 %}
6434
6435 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6436 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6437 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6438 match(Set dst (DecodeN src));
6439 effect(KILL cr);
6440 format %{ "decode_heap_oop $dst,$src" %}
6441 ins_encode %{
6442 Register s = $src$$Register;
6443 Register d = $dst$$Register;
6444 if (s != d) {
6445 __ movq(d, s);
6446 }
6447 __ decode_heap_oop(d);
6448 %}
6449 ins_pipe(ialu_reg_long);
6450 %}
6451
6452 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6453 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6454 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6455 match(Set dst (DecodeN src));
6456 effect(KILL cr);
6457 format %{ "decode_heap_oop_not_null $dst,$src" %}
6458 ins_encode %{
6459 Register s = $src$$Register;
6460 Register d = $dst$$Register;
6461 if (s != d) {
6462 __ decode_heap_oop_not_null(d, s);
6463 } else {
6464 __ decode_heap_oop_not_null(d);
6465 }
6466 %}
6467 ins_pipe(ialu_reg_long);
6468 %}
6469
6470 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6471 match(Set dst (EncodePKlass src));
6472 effect(KILL cr);
6473 format %{ "encode_klass_not_null $dst,$src" %}
6474 ins_encode %{
6475 __ encode_klass_not_null($dst$$Register, $src$$Register);
6476 %}
6477 ins_pipe(ialu_reg_long);
6478 %}
6479
6480 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6481 match(Set dst (DecodeNKlass src));
6482 effect(KILL cr);
6483 format %{ "decode_klass_not_null $dst,$src" %}
6484 ins_encode %{
6485 Register s = $src$$Register;
6486 Register d = $dst$$Register;
6487 if (s != d) {
6488 __ decode_klass_not_null(d, s);
6489 } else {
6490 __ decode_klass_not_null(d);
6491 }
6492 %}
6493 ins_pipe(ialu_reg_long);
6494 %}
6495
6496
6497 //----------Conditional Move---------------------------------------------------
6498 // Jump
6499 // dummy instruction for generating temp registers
6500 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6501 match(Jump (LShiftL switch_val shift));
6502 ins_cost(350);
6503 predicate(false);
6504 effect(TEMP dest);
6505
6506 format %{ "leaq $dest, [$constantaddress]\n\t"
6507 "jmp [$dest + $switch_val << $shift]\n\t" %}
6508 ins_encode %{
6509 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6510 // to do that and the compiler is using that register as one it can allocate.
6511 // So we build it all by hand.
6512 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6513 // ArrayAddress dispatch(table, index);
6514 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6515 __ lea($dest$$Register, $constantaddress);
6516 __ jmp(dispatch);
6517 %}
6518 ins_pipe(pipe_jmp);
6519 %}
6520
6521 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6522 match(Jump (AddL (LShiftL switch_val shift) offset));
6523 ins_cost(350);
6524 effect(TEMP dest);
6525
6526 format %{ "leaq $dest, [$constantaddress]\n\t"
6527 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6528 ins_encode %{
6529 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6530 // to do that and the compiler is using that register as one it can allocate.
6531 // So we build it all by hand.
6532 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6533 // ArrayAddress dispatch(table, index);
6534 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6535 __ lea($dest$$Register, $constantaddress);
6536 __ jmp(dispatch);
6537 %}
6538 ins_pipe(pipe_jmp);
6539 %}
6540
6541 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6542 match(Jump switch_val);
6543 ins_cost(350);
6544 effect(TEMP dest);
6545
6546 format %{ "leaq $dest, [$constantaddress]\n\t"
6547 "jmp [$dest + $switch_val]\n\t" %}
6548 ins_encode %{
6549 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6550 // to do that and the compiler is using that register as one it can allocate.
6551 // So we build it all by hand.
6552 // Address index(noreg, switch_reg, Address::times_1);
6553 // ArrayAddress dispatch(table, index);
6554 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6555 __ lea($dest$$Register, $constantaddress);
6556 __ jmp(dispatch);
6557 %}
6558 ins_pipe(pipe_jmp);
6559 %}
6560
6561 // Conditional move
6562 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6563 %{
6564 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6565
6566 ins_cost(200); // XXX
6567 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6568 opcode(0x0F, 0x40);
6569 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6570 ins_pipe(pipe_cmov_reg);
6571 %}
6572
6573 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6574 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6575
6576 ins_cost(200); // XXX
6577 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6578 opcode(0x0F, 0x40);
6579 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6580 ins_pipe(pipe_cmov_reg);
6581 %}
6582
6583 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6584 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6585 ins_cost(200);
6586 expand %{
6587 cmovI_regU(cop, cr, dst, src);
6588 %}
6589 %}
6590
6591 // Conditional move
6592 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6593 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6594
6595 ins_cost(250); // XXX
6596 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6597 opcode(0x0F, 0x40);
6598 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6599 ins_pipe(pipe_cmov_mem);
6600 %}
6601
6602 // Conditional move
6603 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6604 %{
6605 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6606
6607 ins_cost(250); // XXX
6608 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6609 opcode(0x0F, 0x40);
6610 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6611 ins_pipe(pipe_cmov_mem);
6612 %}
6613
6614 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6615 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6616 ins_cost(250);
6617 expand %{
6618 cmovI_memU(cop, cr, dst, src);
6619 %}
6620 %}
6621
6622 // Conditional move
6623 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6624 %{
6625 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6626
6627 ins_cost(200); // XXX
6628 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6629 opcode(0x0F, 0x40);
6630 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6631 ins_pipe(pipe_cmov_reg);
6632 %}
6633
6634 // Conditional move
6635 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6636 %{
6637 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6638
6639 ins_cost(200); // XXX
6640 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6641 opcode(0x0F, 0x40);
6642 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6643 ins_pipe(pipe_cmov_reg);
6644 %}
6645
6646 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6647 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6648 ins_cost(200);
6649 expand %{
6650 cmovN_regU(cop, cr, dst, src);
6651 %}
6652 %}
6653
6654 // Conditional move
6655 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6656 %{
6657 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6658
6659 ins_cost(200); // XXX
6660 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6661 opcode(0x0F, 0x40);
6662 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6663 ins_pipe(pipe_cmov_reg); // XXX
6664 %}
6665
6666 // Conditional move
6667 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6668 %{
6669 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6670
6671 ins_cost(200); // XXX
6672 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6673 opcode(0x0F, 0x40);
6674 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6675 ins_pipe(pipe_cmov_reg); // XXX
6676 %}
6677
6678 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6679 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6680 ins_cost(200);
6681 expand %{
6682 cmovP_regU(cop, cr, dst, src);
6683 %}
6684 %}
6685
6686 // DISABLED: Requires the ADLC to emit a bottom_type call that
6687 // correctly meets the two pointer arguments; one is an incoming
6688 // register but the other is a memory operand. ALSO appears to
6689 // be buggy with implicit null checks.
6690 //
6691 //// Conditional move
6692 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6693 //%{
6694 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6695 // ins_cost(250);
6696 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6697 // opcode(0x0F,0x40);
6698 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6699 // ins_pipe( pipe_cmov_mem );
6700 //%}
6701 //
6702 //// Conditional move
6703 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6704 //%{
6705 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6706 // ins_cost(250);
6707 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6708 // opcode(0x0F,0x40);
6709 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6710 // ins_pipe( pipe_cmov_mem );
6711 //%}
6712
6713 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6714 %{
6715 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6716
6717 ins_cost(200); // XXX
6718 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6719 opcode(0x0F, 0x40);
6720 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6721 ins_pipe(pipe_cmov_reg); // XXX
6722 %}
6723
6724 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6725 %{
6726 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6727
6728 ins_cost(200); // XXX
6729 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6730 opcode(0x0F, 0x40);
6731 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6732 ins_pipe(pipe_cmov_mem); // XXX
6733 %}
6734
6735 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6736 %{
6737 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6738
6739 ins_cost(200); // XXX
6740 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6741 opcode(0x0F, 0x40);
6742 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6743 ins_pipe(pipe_cmov_reg); // XXX
6744 %}
6745
6746 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6747 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6748 ins_cost(200);
6749 expand %{
6750 cmovL_regU(cop, cr, dst, src);
6751 %}
6752 %}
6753
6754 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6755 %{
6756 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6757
6758 ins_cost(200); // XXX
6759 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6760 opcode(0x0F, 0x40);
6761 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6762 ins_pipe(pipe_cmov_mem); // XXX
6763 %}
6764
6765 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6766 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6767 ins_cost(200);
6768 expand %{
6769 cmovL_memU(cop, cr, dst, src);
6770 %}
6771 %}
6772
6773 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6774 %{
6775 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6776
6777 ins_cost(200); // XXX
6778 format %{ "jn$cop skip\t# signed cmove float\n\t"
6779 "movss $dst, $src\n"
6780 "skip:" %}
6781 ins_encode %{
6782 Label Lskip;
6783 // Invert sense of branch from sense of CMOV
6784 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6785 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6786 __ bind(Lskip);
6787 %}
6788 ins_pipe(pipe_slow);
6789 %}
6790
6791 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
6792 // %{
6793 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
6794
6795 // ins_cost(200); // XXX
6796 // format %{ "jn$cop skip\t# signed cmove float\n\t"
6797 // "movss $dst, $src\n"
6798 // "skip:" %}
6799 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
6800 // ins_pipe(pipe_slow);
6801 // %}
6802
6803 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6804 %{
6805 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6806
6807 ins_cost(200); // XXX
6808 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6809 "movss $dst, $src\n"
6810 "skip:" %}
6811 ins_encode %{
6812 Label Lskip;
6813 // Invert sense of branch from sense of CMOV
6814 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6815 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6816 __ bind(Lskip);
6817 %}
6818 ins_pipe(pipe_slow);
6819 %}
6820
6821 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6822 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6823 ins_cost(200);
6824 expand %{
6825 cmovF_regU(cop, cr, dst, src);
6826 %}
6827 %}
6828
6829 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6830 %{
6831 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6832
6833 ins_cost(200); // XXX
6834 format %{ "jn$cop skip\t# signed cmove double\n\t"
6835 "movsd $dst, $src\n"
6836 "skip:" %}
6837 ins_encode %{
6838 Label Lskip;
6839 // Invert sense of branch from sense of CMOV
6840 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6841 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6842 __ bind(Lskip);
6843 %}
6844 ins_pipe(pipe_slow);
6845 %}
6846
6847 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6848 %{
6849 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6850
6851 ins_cost(200); // XXX
6852 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6853 "movsd $dst, $src\n"
6854 "skip:" %}
6855 ins_encode %{
6856 Label Lskip;
6857 // Invert sense of branch from sense of CMOV
6858 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6859 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6860 __ bind(Lskip);
6861 %}
6862 ins_pipe(pipe_slow);
6863 %}
6864
6865 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6866 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6867 ins_cost(200);
6868 expand %{
6869 cmovD_regU(cop, cr, dst, src);
6870 %}
6871 %}
6872
6873 //----------Arithmetic Instructions--------------------------------------------
6874 //----------Addition Instructions----------------------------------------------
6875
6876 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6877 %{
6878 match(Set dst (AddI dst src));
6879 effect(KILL cr);
6880
6881 format %{ "addl $dst, $src\t# int" %}
6882 opcode(0x03);
6883 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6884 ins_pipe(ialu_reg_reg);
6885 %}
6886
6887 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6888 %{
6889 match(Set dst (AddI dst src));
6890 effect(KILL cr);
6891
6892 format %{ "addl $dst, $src\t# int" %}
6893 opcode(0x81, 0x00); /* /0 id */
6894 ins_encode(OpcSErm(dst, src), Con8or32(src));
6895 ins_pipe( ialu_reg );
6896 %}
6897
6898 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6899 %{
6900 match(Set dst (AddI dst (LoadI src)));
6901 effect(KILL cr);
6902
6903 ins_cost(125); // XXX
6904 format %{ "addl $dst, $src\t# int" %}
6905 opcode(0x03);
6906 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6907 ins_pipe(ialu_reg_mem);
6908 %}
6909
6910 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6911 %{
6912 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6913 effect(KILL cr);
6914
6915 ins_cost(150); // XXX
6916 format %{ "addl $dst, $src\t# int" %}
6917 opcode(0x01); /* Opcode 01 /r */
6918 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6919 ins_pipe(ialu_mem_reg);
6920 %}
6921
6922 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
6923 %{
6924 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6925 effect(KILL cr);
6926
6927 ins_cost(125); // XXX
6928 format %{ "addl $dst, $src\t# int" %}
6929 opcode(0x81); /* Opcode 81 /0 id */
6930 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
6931 ins_pipe(ialu_mem_imm);
6932 %}
6933
6934 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
6935 %{
6936 predicate(UseIncDec);
6937 match(Set dst (AddI dst src));
6938 effect(KILL cr);
6939
6940 format %{ "incl $dst\t# int" %}
6941 opcode(0xFF, 0x00); // FF /0
6942 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6943 ins_pipe(ialu_reg);
6944 %}
6945
6946 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
6947 %{
6948 predicate(UseIncDec);
6949 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6950 effect(KILL cr);
6951
6952 ins_cost(125); // XXX
6953 format %{ "incl $dst\t# int" %}
6954 opcode(0xFF); /* Opcode FF /0 */
6955 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
6956 ins_pipe(ialu_mem_imm);
6957 %}
6958
6959 // XXX why does that use AddI
6960 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
6961 %{
6962 predicate(UseIncDec);
6963 match(Set dst (AddI dst src));
6964 effect(KILL cr);
6965
6966 format %{ "decl $dst\t# int" %}
6967 opcode(0xFF, 0x01); // FF /1
6968 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6969 ins_pipe(ialu_reg);
6970 %}
6971
6972 // XXX why does that use AddI
6973 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
6974 %{
6975 predicate(UseIncDec);
6976 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6977 effect(KILL cr);
6978
6979 ins_cost(125); // XXX
6980 format %{ "decl $dst\t# int" %}
6981 opcode(0xFF); /* Opcode FF /1 */
6982 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
6983 ins_pipe(ialu_mem_imm);
6984 %}
6985
6986 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
6987 %{
6988 match(Set dst (AddI src0 src1));
6989
6990 ins_cost(110);
6991 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
6992 opcode(0x8D); /* 0x8D /r */
6993 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
6994 ins_pipe(ialu_reg_reg);
6995 %}
6996
6997 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
6998 %{
6999 match(Set dst (AddL dst src));
7000 effect(KILL cr);
7001
7002 format %{ "addq $dst, $src\t# long" %}
7003 opcode(0x03);
7004 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7005 ins_pipe(ialu_reg_reg);
7006 %}
7007
7008 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7009 %{
7010 match(Set dst (AddL dst src));
7011 effect(KILL cr);
7012
7013 format %{ "addq $dst, $src\t# long" %}
7014 opcode(0x81, 0x00); /* /0 id */
7015 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7016 ins_pipe( ialu_reg );
7017 %}
7018
7019 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7020 %{
7021 match(Set dst (AddL dst (LoadL src)));
7022 effect(KILL cr);
7023
7024 ins_cost(125); // XXX
7025 format %{ "addq $dst, $src\t# long" %}
7026 opcode(0x03);
7027 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7028 ins_pipe(ialu_reg_mem);
7029 %}
7030
7031 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7032 %{
7033 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7034 effect(KILL cr);
7035
7036 ins_cost(150); // XXX
7037 format %{ "addq $dst, $src\t# long" %}
7038 opcode(0x01); /* Opcode 01 /r */
7039 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7040 ins_pipe(ialu_mem_reg);
7041 %}
7042
7043 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7044 %{
7045 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7046 effect(KILL cr);
7047
7048 ins_cost(125); // XXX
7049 format %{ "addq $dst, $src\t# long" %}
7050 opcode(0x81); /* Opcode 81 /0 id */
7051 ins_encode(REX_mem_wide(dst),
7052 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7053 ins_pipe(ialu_mem_imm);
7054 %}
7055
7056 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7057 %{
7058 predicate(UseIncDec);
7059 match(Set dst (AddL dst src));
7060 effect(KILL cr);
7061
7062 format %{ "incq $dst\t# long" %}
7063 opcode(0xFF, 0x00); // FF /0
7064 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7065 ins_pipe(ialu_reg);
7066 %}
7067
7068 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7069 %{
7070 predicate(UseIncDec);
7071 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7072 effect(KILL cr);
7073
7074 ins_cost(125); // XXX
7075 format %{ "incq $dst\t# long" %}
7076 opcode(0xFF); /* Opcode FF /0 */
7077 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7078 ins_pipe(ialu_mem_imm);
7079 %}
7080
7081 // XXX why does that use AddL
7082 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7083 %{
7084 predicate(UseIncDec);
7085 match(Set dst (AddL dst src));
7086 effect(KILL cr);
7087
7088 format %{ "decq $dst\t# long" %}
7089 opcode(0xFF, 0x01); // FF /1
7090 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7091 ins_pipe(ialu_reg);
7092 %}
7093
7094 // XXX why does that use AddL
7095 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7096 %{
7097 predicate(UseIncDec);
7098 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7099 effect(KILL cr);
7100
7101 ins_cost(125); // XXX
7102 format %{ "decq $dst\t# long" %}
7103 opcode(0xFF); /* Opcode FF /1 */
7104 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7105 ins_pipe(ialu_mem_imm);
7106 %}
7107
7108 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7109 %{
7110 match(Set dst (AddL src0 src1));
7111
7112 ins_cost(110);
7113 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7114 opcode(0x8D); /* 0x8D /r */
7115 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7116 ins_pipe(ialu_reg_reg);
7117 %}
7118
7119 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7120 %{
7121 match(Set dst (AddP dst src));
7122 effect(KILL cr);
7123
7124 format %{ "addq $dst, $src\t# ptr" %}
7125 opcode(0x03);
7126 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7127 ins_pipe(ialu_reg_reg);
7128 %}
7129
7130 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7131 %{
7132 match(Set dst (AddP dst src));
7133 effect(KILL cr);
7134
7135 format %{ "addq $dst, $src\t# ptr" %}
7136 opcode(0x81, 0x00); /* /0 id */
7137 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7138 ins_pipe( ialu_reg );
7139 %}
7140
7141 // XXX addP mem ops ????
7142
7143 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7144 %{
7145 match(Set dst (AddP src0 src1));
7146
7147 ins_cost(110);
7148 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7149 opcode(0x8D); /* 0x8D /r */
7150 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7151 ins_pipe(ialu_reg_reg);
7152 %}
7153
7154 instruct checkCastPP(rRegP dst)
7155 %{
7156 match(Set dst (CheckCastPP dst));
7157
7158 size(0);
7159 format %{ "# checkcastPP of $dst" %}
7160 ins_encode(/* empty encoding */);
7161 ins_pipe(empty);
7162 %}
7163
7164 instruct castPP(rRegP dst)
7165 %{
7166 match(Set dst (CastPP dst));
7167
7168 size(0);
7169 format %{ "# castPP of $dst" %}
7170 ins_encode(/* empty encoding */);
7171 ins_pipe(empty);
7172 %}
7173
7174 instruct castII(rRegI dst)
7175 %{
7176 match(Set dst (CastII dst));
7177
7178 size(0);
7179 format %{ "# castII of $dst" %}
7180 ins_encode(/* empty encoding */);
7181 ins_cost(0);
7182 ins_pipe(empty);
7183 %}
7184
7185 // LoadP-locked same as a regular LoadP when used with compare-swap
7186 instruct loadPLocked(rRegP dst, memory mem)
7187 %{
7188 match(Set dst (LoadPLocked mem));
7189
7190 ins_cost(125); // XXX
7191 format %{ "movq $dst, $mem\t# ptr locked" %}
7192 opcode(0x8B);
7193 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7194 ins_pipe(ialu_reg_mem); // XXX
7195 %}
7196
7197 // Conditional-store of the updated heap-top.
7198 // Used during allocation of the shared heap.
7199 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7200
7201 instruct storePConditional(memory heap_top_ptr,
7202 rax_RegP oldval, rRegP newval,
7203 rFlagsReg cr)
7204 %{
7205 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7206
7207 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7208 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7209 opcode(0x0F, 0xB1);
7210 ins_encode(lock_prefix,
7211 REX_reg_mem_wide(newval, heap_top_ptr),
7212 OpcP, OpcS,
7213 reg_mem(newval, heap_top_ptr));
7214 ins_pipe(pipe_cmpxchg);
7215 %}
7216
7217 // Conditional-store of an int value.
7218 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7219 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7220 %{
7221 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7222 effect(KILL oldval);
7223
7224 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7225 opcode(0x0F, 0xB1);
7226 ins_encode(lock_prefix,
7227 REX_reg_mem(newval, mem),
7228 OpcP, OpcS,
7229 reg_mem(newval, mem));
7230 ins_pipe(pipe_cmpxchg);
7231 %}
7232
7233 // Conditional-store of a long value.
7234 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7235 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7236 %{
7237 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7238 effect(KILL oldval);
7239
7240 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7241 opcode(0x0F, 0xB1);
7242 ins_encode(lock_prefix,
7243 REX_reg_mem_wide(newval, mem),
7244 OpcP, OpcS,
7245 reg_mem(newval, mem));
7246 ins_pipe(pipe_cmpxchg);
7247 %}
7248
7249
7250 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7251 instruct compareAndSwapP(rRegI res,
7252 memory mem_ptr,
7253 rax_RegP oldval, rRegP newval,
7254 rFlagsReg cr)
7255 %{
7256 predicate(VM_Version::supports_cx8());
7257 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7258 effect(KILL cr, KILL oldval);
7259
7260 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7261 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7262 "sete $res\n\t"
7263 "movzbl $res, $res" %}
7264 opcode(0x0F, 0xB1);
7265 ins_encode(lock_prefix,
7266 REX_reg_mem_wide(newval, mem_ptr),
7267 OpcP, OpcS,
7268 reg_mem(newval, mem_ptr),
7269 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7270 REX_reg_breg(res, res), // movzbl
7271 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7272 ins_pipe( pipe_cmpxchg );
7273 %}
7274
7275 instruct compareAndSwapL(rRegI res,
7276 memory mem_ptr,
7277 rax_RegL oldval, rRegL newval,
7278 rFlagsReg cr)
7279 %{
7280 predicate(VM_Version::supports_cx8());
7281 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7282 effect(KILL cr, KILL oldval);
7283
7284 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7285 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7286 "sete $res\n\t"
7287 "movzbl $res, $res" %}
7288 opcode(0x0F, 0xB1);
7289 ins_encode(lock_prefix,
7290 REX_reg_mem_wide(newval, mem_ptr),
7291 OpcP, OpcS,
7292 reg_mem(newval, mem_ptr),
7293 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7294 REX_reg_breg(res, res), // movzbl
7295 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7296 ins_pipe( pipe_cmpxchg );
7297 %}
7298
7299 instruct compareAndSwapI(rRegI res,
7300 memory mem_ptr,
7301 rax_RegI oldval, rRegI newval,
7302 rFlagsReg cr)
7303 %{
7304 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7305 effect(KILL cr, KILL oldval);
7306
7307 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7308 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7309 "sete $res\n\t"
7310 "movzbl $res, $res" %}
7311 opcode(0x0F, 0xB1);
7312 ins_encode(lock_prefix,
7313 REX_reg_mem(newval, mem_ptr),
7314 OpcP, OpcS,
7315 reg_mem(newval, mem_ptr),
7316 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7317 REX_reg_breg(res, res), // movzbl
7318 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7319 ins_pipe( pipe_cmpxchg );
7320 %}
7321
7322
7323 instruct compareAndSwapN(rRegI res,
7324 memory mem_ptr,
7325 rax_RegN oldval, rRegN newval,
7326 rFlagsReg cr) %{
7327 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7328 effect(KILL cr, KILL oldval);
7329
7330 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7331 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7332 "sete $res\n\t"
7333 "movzbl $res, $res" %}
7334 opcode(0x0F, 0xB1);
7335 ins_encode(lock_prefix,
7336 REX_reg_mem(newval, mem_ptr),
7337 OpcP, OpcS,
7338 reg_mem(newval, mem_ptr),
7339 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7340 REX_reg_breg(res, res), // movzbl
7341 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7342 ins_pipe( pipe_cmpxchg );
7343 %}
7344
7345 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7346 predicate(n->as_LoadStore()->result_not_used());
7347 match(Set dummy (GetAndAddI mem add));
7348 effect(KILL cr);
7349 format %{ "ADDL [$mem],$add" %}
7350 ins_encode %{
7351 if (os::is_MP()) { __ lock(); }
7352 __ addl($mem$$Address, $add$$constant);
7353 %}
7354 ins_pipe( pipe_cmpxchg );
7355 %}
7356
7357 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7358 match(Set newval (GetAndAddI mem newval));
7359 effect(KILL cr);
7360 format %{ "XADDL [$mem],$newval" %}
7361 ins_encode %{
7362 if (os::is_MP()) { __ lock(); }
7363 __ xaddl($mem$$Address, $newval$$Register);
7364 %}
7365 ins_pipe( pipe_cmpxchg );
7366 %}
7367
7368 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7369 predicate(n->as_LoadStore()->result_not_used());
7370 match(Set dummy (GetAndAddL mem add));
7371 effect(KILL cr);
7372 format %{ "ADDQ [$mem],$add" %}
7373 ins_encode %{
7374 if (os::is_MP()) { __ lock(); }
7375 __ addq($mem$$Address, $add$$constant);
7376 %}
7377 ins_pipe( pipe_cmpxchg );
7378 %}
7379
7380 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7381 match(Set newval (GetAndAddL mem newval));
7382 effect(KILL cr);
7383 format %{ "XADDQ [$mem],$newval" %}
7384 ins_encode %{
7385 if (os::is_MP()) { __ lock(); }
7386 __ xaddq($mem$$Address, $newval$$Register);
7387 %}
7388 ins_pipe( pipe_cmpxchg );
7389 %}
7390
7391 instruct xchgI( memory mem, rRegI newval) %{
7392 match(Set newval (GetAndSetI mem newval));
7393 format %{ "XCHGL $newval,[$mem]" %}
7394 ins_encode %{
7395 __ xchgl($newval$$Register, $mem$$Address);
7396 %}
7397 ins_pipe( pipe_cmpxchg );
7398 %}
7399
7400 instruct xchgL( memory mem, rRegL newval) %{
7401 match(Set newval (GetAndSetL mem newval));
7402 format %{ "XCHGL $newval,[$mem]" %}
7403 ins_encode %{
7404 __ xchgq($newval$$Register, $mem$$Address);
7405 %}
7406 ins_pipe( pipe_cmpxchg );
7407 %}
7408
7409 instruct xchgP( memory mem, rRegP newval) %{
7410 match(Set newval (GetAndSetP mem newval));
7411 format %{ "XCHGQ $newval,[$mem]" %}
7412 ins_encode %{
7413 __ xchgq($newval$$Register, $mem$$Address);
7414 %}
7415 ins_pipe( pipe_cmpxchg );
7416 %}
7417
7418 instruct xchgN( memory mem, rRegN newval) %{
7419 match(Set newval (GetAndSetN mem newval));
7420 format %{ "XCHGL $newval,$mem]" %}
7421 ins_encode %{
7422 __ xchgl($newval$$Register, $mem$$Address);
7423 %}
7424 ins_pipe( pipe_cmpxchg );
7425 %}
7426
7427 //----------Subtraction Instructions-------------------------------------------
7428
7429 // Integer Subtraction Instructions
7430 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7431 %{
7432 match(Set dst (SubI dst src));
7433 effect(KILL cr);
7434
7435 format %{ "subl $dst, $src\t# int" %}
7436 opcode(0x2B);
7437 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7438 ins_pipe(ialu_reg_reg);
7439 %}
7440
7441 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7442 %{
7443 match(Set dst (SubI dst src));
7444 effect(KILL cr);
7445
7446 format %{ "subl $dst, $src\t# int" %}
7447 opcode(0x81, 0x05); /* Opcode 81 /5 */
7448 ins_encode(OpcSErm(dst, src), Con8or32(src));
7449 ins_pipe(ialu_reg);
7450 %}
7451
7452 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7453 %{
7454 match(Set dst (SubI dst (LoadI src)));
7455 effect(KILL cr);
7456
7457 ins_cost(125);
7458 format %{ "subl $dst, $src\t# int" %}
7459 opcode(0x2B);
7460 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7461 ins_pipe(ialu_reg_mem);
7462 %}
7463
7464 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7465 %{
7466 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7467 effect(KILL cr);
7468
7469 ins_cost(150);
7470 format %{ "subl $dst, $src\t# int" %}
7471 opcode(0x29); /* Opcode 29 /r */
7472 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7473 ins_pipe(ialu_mem_reg);
7474 %}
7475
7476 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7477 %{
7478 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7479 effect(KILL cr);
7480
7481 ins_cost(125); // XXX
7482 format %{ "subl $dst, $src\t# int" %}
7483 opcode(0x81); /* Opcode 81 /5 id */
7484 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7485 ins_pipe(ialu_mem_imm);
7486 %}
7487
7488 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7489 %{
7490 match(Set dst (SubL dst src));
7491 effect(KILL cr);
7492
7493 format %{ "subq $dst, $src\t# long" %}
7494 opcode(0x2B);
7495 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7496 ins_pipe(ialu_reg_reg);
7497 %}
7498
7499 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7500 %{
7501 match(Set dst (SubL dst src));
7502 effect(KILL cr);
7503
7504 format %{ "subq $dst, $src\t# long" %}
7505 opcode(0x81, 0x05); /* Opcode 81 /5 */
7506 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7507 ins_pipe(ialu_reg);
7508 %}
7509
7510 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7511 %{
7512 match(Set dst (SubL dst (LoadL src)));
7513 effect(KILL cr);
7514
7515 ins_cost(125);
7516 format %{ "subq $dst, $src\t# long" %}
7517 opcode(0x2B);
7518 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7519 ins_pipe(ialu_reg_mem);
7520 %}
7521
7522 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7523 %{
7524 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7525 effect(KILL cr);
7526
7527 ins_cost(150);
7528 format %{ "subq $dst, $src\t# long" %}
7529 opcode(0x29); /* Opcode 29 /r */
7530 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7531 ins_pipe(ialu_mem_reg);
7532 %}
7533
7534 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7535 %{
7536 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7537 effect(KILL cr);
7538
7539 ins_cost(125); // XXX
7540 format %{ "subq $dst, $src\t# long" %}
7541 opcode(0x81); /* Opcode 81 /5 id */
7542 ins_encode(REX_mem_wide(dst),
7543 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7544 ins_pipe(ialu_mem_imm);
7545 %}
7546
7547 // Subtract from a pointer
7548 // XXX hmpf???
7549 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7550 %{
7551 match(Set dst (AddP dst (SubI zero src)));
7552 effect(KILL cr);
7553
7554 format %{ "subq $dst, $src\t# ptr - int" %}
7555 opcode(0x2B);
7556 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7557 ins_pipe(ialu_reg_reg);
7558 %}
7559
7560 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7561 %{
7562 match(Set dst (SubI zero dst));
7563 effect(KILL cr);
7564
7565 format %{ "negl $dst\t# int" %}
7566 opcode(0xF7, 0x03); // Opcode F7 /3
7567 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7568 ins_pipe(ialu_reg);
7569 %}
7570
7571 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7572 %{
7573 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7574 effect(KILL cr);
7575
7576 format %{ "negl $dst\t# int" %}
7577 opcode(0xF7, 0x03); // Opcode F7 /3
7578 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7579 ins_pipe(ialu_reg);
7580 %}
7581
7582 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7583 %{
7584 match(Set dst (SubL zero dst));
7585 effect(KILL cr);
7586
7587 format %{ "negq $dst\t# long" %}
7588 opcode(0xF7, 0x03); // Opcode F7 /3
7589 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7590 ins_pipe(ialu_reg);
7591 %}
7592
7593 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7594 %{
7595 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7596 effect(KILL cr);
7597
7598 format %{ "negq $dst\t# long" %}
7599 opcode(0xF7, 0x03); // Opcode F7 /3
7600 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7601 ins_pipe(ialu_reg);
7602 %}
7603
7604 //----------Multiplication/Division Instructions-------------------------------
7605 // Integer Multiplication Instructions
7606 // Multiply Register
7607
7608 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7609 %{
7610 match(Set dst (MulI dst src));
7611 effect(KILL cr);
7612
7613 ins_cost(300);
7614 format %{ "imull $dst, $src\t# int" %}
7615 opcode(0x0F, 0xAF);
7616 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7617 ins_pipe(ialu_reg_reg_alu0);
7618 %}
7619
7620 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7621 %{
7622 match(Set dst (MulI src imm));
7623 effect(KILL cr);
7624
7625 ins_cost(300);
7626 format %{ "imull $dst, $src, $imm\t# int" %}
7627 opcode(0x69); /* 69 /r id */
7628 ins_encode(REX_reg_reg(dst, src),
7629 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7630 ins_pipe(ialu_reg_reg_alu0);
7631 %}
7632
7633 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7634 %{
7635 match(Set dst (MulI dst (LoadI src)));
7636 effect(KILL cr);
7637
7638 ins_cost(350);
7639 format %{ "imull $dst, $src\t# int" %}
7640 opcode(0x0F, 0xAF);
7641 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7642 ins_pipe(ialu_reg_mem_alu0);
7643 %}
7644
7645 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7646 %{
7647 match(Set dst (MulI (LoadI src) imm));
7648 effect(KILL cr);
7649
7650 ins_cost(300);
7651 format %{ "imull $dst, $src, $imm\t# int" %}
7652 opcode(0x69); /* 69 /r id */
7653 ins_encode(REX_reg_mem(dst, src),
7654 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7655 ins_pipe(ialu_reg_mem_alu0);
7656 %}
7657
7658 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7659 %{
7660 match(Set dst (MulL dst src));
7661 effect(KILL cr);
7662
7663 ins_cost(300);
7664 format %{ "imulq $dst, $src\t# long" %}
7665 opcode(0x0F, 0xAF);
7666 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7667 ins_pipe(ialu_reg_reg_alu0);
7668 %}
7669
7670 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7671 %{
7672 match(Set dst (MulL src imm));
7673 effect(KILL cr);
7674
7675 ins_cost(300);
7676 format %{ "imulq $dst, $src, $imm\t# long" %}
7677 opcode(0x69); /* 69 /r id */
7678 ins_encode(REX_reg_reg_wide(dst, src),
7679 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7680 ins_pipe(ialu_reg_reg_alu0);
7681 %}
7682
7683 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7684 %{
7685 match(Set dst (MulL dst (LoadL src)));
7686 effect(KILL cr);
7687
7688 ins_cost(350);
7689 format %{ "imulq $dst, $src\t# long" %}
7690 opcode(0x0F, 0xAF);
7691 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
7692 ins_pipe(ialu_reg_mem_alu0);
7693 %}
7694
7695 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7696 %{
7697 match(Set dst (MulL (LoadL src) imm));
7698 effect(KILL cr);
7699
7700 ins_cost(300);
7701 format %{ "imulq $dst, $src, $imm\t# long" %}
7702 opcode(0x69); /* 69 /r id */
7703 ins_encode(REX_reg_mem_wide(dst, src),
7704 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7705 ins_pipe(ialu_reg_mem_alu0);
7706 %}
7707
7708 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7709 %{
7710 match(Set dst (MulHiL src rax));
7711 effect(USE_KILL rax, KILL cr);
7712
7713 ins_cost(300);
7714 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7715 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7716 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7717 ins_pipe(ialu_reg_reg_alu0);
7718 %}
7719
7720 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7721 rFlagsReg cr)
7722 %{
7723 match(Set rax (DivI rax div));
7724 effect(KILL rdx, KILL cr);
7725
7726 ins_cost(30*100+10*100); // XXX
7727 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7728 "jne,s normal\n\t"
7729 "xorl rdx, rdx\n\t"
7730 "cmpl $div, -1\n\t"
7731 "je,s done\n"
7732 "normal: cdql\n\t"
7733 "idivl $div\n"
7734 "done:" %}
7735 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7736 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7737 ins_pipe(ialu_reg_reg_alu0);
7738 %}
7739
7740 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7741 rFlagsReg cr)
7742 %{
7743 match(Set rax (DivL rax div));
7744 effect(KILL rdx, KILL cr);
7745
7746 ins_cost(30*100+10*100); // XXX
7747 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7748 "cmpq rax, rdx\n\t"
7749 "jne,s normal\n\t"
7750 "xorl rdx, rdx\n\t"
7751 "cmpq $div, -1\n\t"
7752 "je,s done\n"
7753 "normal: cdqq\n\t"
7754 "idivq $div\n"
7755 "done:" %}
7756 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7757 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7758 ins_pipe(ialu_reg_reg_alu0);
7759 %}
7760
7761 // Integer DIVMOD with Register, both quotient and mod results
7762 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7763 rFlagsReg cr)
7764 %{
7765 match(DivModI rax div);
7766 effect(KILL cr);
7767
7768 ins_cost(30*100+10*100); // XXX
7769 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7770 "jne,s normal\n\t"
7771 "xorl rdx, rdx\n\t"
7772 "cmpl $div, -1\n\t"
7773 "je,s done\n"
7774 "normal: cdql\n\t"
7775 "idivl $div\n"
7776 "done:" %}
7777 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7778 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7779 ins_pipe(pipe_slow);
7780 %}
7781
7782 // Long DIVMOD with Register, both quotient and mod results
7783 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7784 rFlagsReg cr)
7785 %{
7786 match(DivModL rax div);
7787 effect(KILL cr);
7788
7789 ins_cost(30*100+10*100); // XXX
7790 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7791 "cmpq rax, rdx\n\t"
7792 "jne,s normal\n\t"
7793 "xorl rdx, rdx\n\t"
7794 "cmpq $div, -1\n\t"
7795 "je,s done\n"
7796 "normal: cdqq\n\t"
7797 "idivq $div\n"
7798 "done:" %}
7799 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7800 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7801 ins_pipe(pipe_slow);
7802 %}
7803
7804 //----------- DivL-By-Constant-Expansions--------------------------------------
7805 // DivI cases are handled by the compiler
7806
7807 // Magic constant, reciprocal of 10
7808 instruct loadConL_0x6666666666666667(rRegL dst)
7809 %{
7810 effect(DEF dst);
7811
7812 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
7813 ins_encode(load_immL(dst, 0x6666666666666667));
7814 ins_pipe(ialu_reg);
7815 %}
7816
7817 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7818 %{
7819 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
7820
7821 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
7822 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7823 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7824 ins_pipe(ialu_reg_reg_alu0);
7825 %}
7826
7827 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
7828 %{
7829 effect(USE_DEF dst, KILL cr);
7830
7831 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
7832 opcode(0xC1, 0x7); /* C1 /7 ib */
7833 ins_encode(reg_opc_imm_wide(dst, 0x3F));
7834 ins_pipe(ialu_reg);
7835 %}
7836
7837 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
7838 %{
7839 effect(USE_DEF dst, KILL cr);
7840
7841 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
7842 opcode(0xC1, 0x7); /* C1 /7 ib */
7843 ins_encode(reg_opc_imm_wide(dst, 0x2));
7844 ins_pipe(ialu_reg);
7845 %}
7846
7847 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
7848 %{
7849 match(Set dst (DivL src div));
7850
7851 ins_cost((5+8)*100);
7852 expand %{
7853 rax_RegL rax; // Killed temp
7854 rFlagsReg cr; // Killed
7855 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
7856 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
7857 sarL_rReg_63(src, cr); // sarq src, 63
7858 sarL_rReg_2(dst, cr); // sarq rdx, 2
7859 subL_rReg(dst, src, cr); // subl rdx, src
7860 %}
7861 %}
7862
7863 //-----------------------------------------------------------------------------
7864
7865 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
7866 rFlagsReg cr)
7867 %{
7868 match(Set rdx (ModI rax div));
7869 effect(KILL rax, KILL cr);
7870
7871 ins_cost(300); // XXX
7872 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
7873 "jne,s normal\n\t"
7874 "xorl rdx, rdx\n\t"
7875 "cmpl $div, -1\n\t"
7876 "je,s done\n"
7877 "normal: cdql\n\t"
7878 "idivl $div\n"
7879 "done:" %}
7880 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7881 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7882 ins_pipe(ialu_reg_reg_alu0);
7883 %}
7884
7885 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
7886 rFlagsReg cr)
7887 %{
7888 match(Set rdx (ModL rax div));
7889 effect(KILL rax, KILL cr);
7890
7891 ins_cost(300); // XXX
7892 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
7893 "cmpq rax, rdx\n\t"
7894 "jne,s normal\n\t"
7895 "xorl rdx, rdx\n\t"
7896 "cmpq $div, -1\n\t"
7897 "je,s done\n"
7898 "normal: cdqq\n\t"
7899 "idivq $div\n"
7900 "done:" %}
7901 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7902 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7903 ins_pipe(ialu_reg_reg_alu0);
7904 %}
7905
7906 // Integer Shift Instructions
7907 // Shift Left by one
7908 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7909 %{
7910 match(Set dst (LShiftI dst shift));
7911 effect(KILL cr);
7912
7913 format %{ "sall $dst, $shift" %}
7914 opcode(0xD1, 0x4); /* D1 /4 */
7915 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7916 ins_pipe(ialu_reg);
7917 %}
7918
7919 // Shift Left by one
7920 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7921 %{
7922 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7923 effect(KILL cr);
7924
7925 format %{ "sall $dst, $shift\t" %}
7926 opcode(0xD1, 0x4); /* D1 /4 */
7927 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7928 ins_pipe(ialu_mem_imm);
7929 %}
7930
7931 // Shift Left by 8-bit immediate
7932 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7933 %{
7934 match(Set dst (LShiftI dst shift));
7935 effect(KILL cr);
7936
7937 format %{ "sall $dst, $shift" %}
7938 opcode(0xC1, 0x4); /* C1 /4 ib */
7939 ins_encode(reg_opc_imm(dst, shift));
7940 ins_pipe(ialu_reg);
7941 %}
7942
7943 // Shift Left by 8-bit immediate
7944 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7945 %{
7946 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7947 effect(KILL cr);
7948
7949 format %{ "sall $dst, $shift" %}
7950 opcode(0xC1, 0x4); /* C1 /4 ib */
7951 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
7952 ins_pipe(ialu_mem_imm);
7953 %}
7954
7955 // Shift Left by variable
7956 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
7957 %{
7958 match(Set dst (LShiftI dst shift));
7959 effect(KILL cr);
7960
7961 format %{ "sall $dst, $shift" %}
7962 opcode(0xD3, 0x4); /* D3 /4 */
7963 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7964 ins_pipe(ialu_reg_reg);
7965 %}
7966
7967 // Shift Left by variable
7968 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
7969 %{
7970 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7971 effect(KILL cr);
7972
7973 format %{ "sall $dst, $shift" %}
7974 opcode(0xD3, 0x4); /* D3 /4 */
7975 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7976 ins_pipe(ialu_mem_reg);
7977 %}
7978
7979 // Arithmetic shift right by one
7980 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7981 %{
7982 match(Set dst (RShiftI dst shift));
7983 effect(KILL cr);
7984
7985 format %{ "sarl $dst, $shift" %}
7986 opcode(0xD1, 0x7); /* D1 /7 */
7987 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7988 ins_pipe(ialu_reg);
7989 %}
7990
7991 // Arithmetic shift right by one
7992 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7993 %{
7994 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7995 effect(KILL cr);
7996
7997 format %{ "sarl $dst, $shift" %}
7998 opcode(0xD1, 0x7); /* D1 /7 */
7999 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8000 ins_pipe(ialu_mem_imm);
8001 %}
8002
8003 // Arithmetic Shift Right by 8-bit immediate
8004 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8005 %{
8006 match(Set dst (RShiftI dst shift));
8007 effect(KILL cr);
8008
8009 format %{ "sarl $dst, $shift" %}
8010 opcode(0xC1, 0x7); /* C1 /7 ib */
8011 ins_encode(reg_opc_imm(dst, shift));
8012 ins_pipe(ialu_mem_imm);
8013 %}
8014
8015 // Arithmetic Shift Right by 8-bit immediate
8016 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8017 %{
8018 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8019 effect(KILL cr);
8020
8021 format %{ "sarl $dst, $shift" %}
8022 opcode(0xC1, 0x7); /* C1 /7 ib */
8023 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8024 ins_pipe(ialu_mem_imm);
8025 %}
8026
8027 // Arithmetic Shift Right by variable
8028 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8029 %{
8030 match(Set dst (RShiftI dst shift));
8031 effect(KILL cr);
8032
8033 format %{ "sarl $dst, $shift" %}
8034 opcode(0xD3, 0x7); /* D3 /7 */
8035 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8036 ins_pipe(ialu_reg_reg);
8037 %}
8038
8039 // Arithmetic Shift Right by variable
8040 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8041 %{
8042 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8043 effect(KILL cr);
8044
8045 format %{ "sarl $dst, $shift" %}
8046 opcode(0xD3, 0x7); /* D3 /7 */
8047 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8048 ins_pipe(ialu_mem_reg);
8049 %}
8050
8051 // Logical shift right by one
8052 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8053 %{
8054 match(Set dst (URShiftI dst shift));
8055 effect(KILL cr);
8056
8057 format %{ "shrl $dst, $shift" %}
8058 opcode(0xD1, 0x5); /* D1 /5 */
8059 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8060 ins_pipe(ialu_reg);
8061 %}
8062
8063 // Logical shift right by one
8064 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8065 %{
8066 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8067 effect(KILL cr);
8068
8069 format %{ "shrl $dst, $shift" %}
8070 opcode(0xD1, 0x5); /* D1 /5 */
8071 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8072 ins_pipe(ialu_mem_imm);
8073 %}
8074
8075 // Logical Shift Right by 8-bit immediate
8076 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8077 %{
8078 match(Set dst (URShiftI dst shift));
8079 effect(KILL cr);
8080
8081 format %{ "shrl $dst, $shift" %}
8082 opcode(0xC1, 0x5); /* C1 /5 ib */
8083 ins_encode(reg_opc_imm(dst, shift));
8084 ins_pipe(ialu_reg);
8085 %}
8086
8087 // Logical Shift Right by 8-bit immediate
8088 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8089 %{
8090 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8091 effect(KILL cr);
8092
8093 format %{ "shrl $dst, $shift" %}
8094 opcode(0xC1, 0x5); /* C1 /5 ib */
8095 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8096 ins_pipe(ialu_mem_imm);
8097 %}
8098
8099 // Logical Shift Right by variable
8100 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8101 %{
8102 match(Set dst (URShiftI dst shift));
8103 effect(KILL cr);
8104
8105 format %{ "shrl $dst, $shift" %}
8106 opcode(0xD3, 0x5); /* D3 /5 */
8107 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8108 ins_pipe(ialu_reg_reg);
8109 %}
8110
8111 // Logical Shift Right by variable
8112 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8113 %{
8114 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8115 effect(KILL cr);
8116
8117 format %{ "shrl $dst, $shift" %}
8118 opcode(0xD3, 0x5); /* D3 /5 */
8119 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8120 ins_pipe(ialu_mem_reg);
8121 %}
8122
8123 // Long Shift Instructions
8124 // Shift Left by one
8125 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8126 %{
8127 match(Set dst (LShiftL dst shift));
8128 effect(KILL cr);
8129
8130 format %{ "salq $dst, $shift" %}
8131 opcode(0xD1, 0x4); /* D1 /4 */
8132 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8133 ins_pipe(ialu_reg);
8134 %}
8135
8136 // Shift Left by one
8137 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8138 %{
8139 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8140 effect(KILL cr);
8141
8142 format %{ "salq $dst, $shift" %}
8143 opcode(0xD1, 0x4); /* D1 /4 */
8144 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8145 ins_pipe(ialu_mem_imm);
8146 %}
8147
8148 // Shift Left by 8-bit immediate
8149 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8150 %{
8151 match(Set dst (LShiftL dst shift));
8152 effect(KILL cr);
8153
8154 format %{ "salq $dst, $shift" %}
8155 opcode(0xC1, 0x4); /* C1 /4 ib */
8156 ins_encode(reg_opc_imm_wide(dst, shift));
8157 ins_pipe(ialu_reg);
8158 %}
8159
8160 // Shift Left by 8-bit immediate
8161 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8162 %{
8163 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8164 effect(KILL cr);
8165
8166 format %{ "salq $dst, $shift" %}
8167 opcode(0xC1, 0x4); /* C1 /4 ib */
8168 ins_encode(REX_mem_wide(dst), OpcP,
8169 RM_opc_mem(secondary, dst), Con8or32(shift));
8170 ins_pipe(ialu_mem_imm);
8171 %}
8172
8173 // Shift Left by variable
8174 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8175 %{
8176 match(Set dst (LShiftL dst shift));
8177 effect(KILL cr);
8178
8179 format %{ "salq $dst, $shift" %}
8180 opcode(0xD3, 0x4); /* D3 /4 */
8181 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8182 ins_pipe(ialu_reg_reg);
8183 %}
8184
8185 // Shift Left by variable
8186 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8187 %{
8188 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8189 effect(KILL cr);
8190
8191 format %{ "salq $dst, $shift" %}
8192 opcode(0xD3, 0x4); /* D3 /4 */
8193 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8194 ins_pipe(ialu_mem_reg);
8195 %}
8196
8197 // Arithmetic shift right by one
8198 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8199 %{
8200 match(Set dst (RShiftL dst shift));
8201 effect(KILL cr);
8202
8203 format %{ "sarq $dst, $shift" %}
8204 opcode(0xD1, 0x7); /* D1 /7 */
8205 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8206 ins_pipe(ialu_reg);
8207 %}
8208
8209 // Arithmetic shift right by one
8210 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8211 %{
8212 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8213 effect(KILL cr);
8214
8215 format %{ "sarq $dst, $shift" %}
8216 opcode(0xD1, 0x7); /* D1 /7 */
8217 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8218 ins_pipe(ialu_mem_imm);
8219 %}
8220
8221 // Arithmetic Shift Right by 8-bit immediate
8222 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8223 %{
8224 match(Set dst (RShiftL dst shift));
8225 effect(KILL cr);
8226
8227 format %{ "sarq $dst, $shift" %}
8228 opcode(0xC1, 0x7); /* C1 /7 ib */
8229 ins_encode(reg_opc_imm_wide(dst, shift));
8230 ins_pipe(ialu_mem_imm);
8231 %}
8232
8233 // Arithmetic Shift Right by 8-bit immediate
8234 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8235 %{
8236 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8237 effect(KILL cr);
8238
8239 format %{ "sarq $dst, $shift" %}
8240 opcode(0xC1, 0x7); /* C1 /7 ib */
8241 ins_encode(REX_mem_wide(dst), OpcP,
8242 RM_opc_mem(secondary, dst), Con8or32(shift));
8243 ins_pipe(ialu_mem_imm);
8244 %}
8245
8246 // Arithmetic Shift Right by variable
8247 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8248 %{
8249 match(Set dst (RShiftL dst shift));
8250 effect(KILL cr);
8251
8252 format %{ "sarq $dst, $shift" %}
8253 opcode(0xD3, 0x7); /* D3 /7 */
8254 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8255 ins_pipe(ialu_reg_reg);
8256 %}
8257
8258 // Arithmetic Shift Right by variable
8259 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8260 %{
8261 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8262 effect(KILL cr);
8263
8264 format %{ "sarq $dst, $shift" %}
8265 opcode(0xD3, 0x7); /* D3 /7 */
8266 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8267 ins_pipe(ialu_mem_reg);
8268 %}
8269
8270 // Logical shift right by one
8271 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8272 %{
8273 match(Set dst (URShiftL dst shift));
8274 effect(KILL cr);
8275
8276 format %{ "shrq $dst, $shift" %}
8277 opcode(0xD1, 0x5); /* D1 /5 */
8278 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8279 ins_pipe(ialu_reg);
8280 %}
8281
8282 // Logical shift right by one
8283 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8284 %{
8285 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8286 effect(KILL cr);
8287
8288 format %{ "shrq $dst, $shift" %}
8289 opcode(0xD1, 0x5); /* D1 /5 */
8290 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8291 ins_pipe(ialu_mem_imm);
8292 %}
8293
8294 // Logical Shift Right by 8-bit immediate
8295 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8296 %{
8297 match(Set dst (URShiftL dst shift));
8298 effect(KILL cr);
8299
8300 format %{ "shrq $dst, $shift" %}
8301 opcode(0xC1, 0x5); /* C1 /5 ib */
8302 ins_encode(reg_opc_imm_wide(dst, shift));
8303 ins_pipe(ialu_reg);
8304 %}
8305
8306
8307 // Logical Shift Right by 8-bit immediate
8308 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8309 %{
8310 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8311 effect(KILL cr);
8312
8313 format %{ "shrq $dst, $shift" %}
8314 opcode(0xC1, 0x5); /* C1 /5 ib */
8315 ins_encode(REX_mem_wide(dst), OpcP,
8316 RM_opc_mem(secondary, dst), Con8or32(shift));
8317 ins_pipe(ialu_mem_imm);
8318 %}
8319
8320 // Logical Shift Right by variable
8321 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8322 %{
8323 match(Set dst (URShiftL dst shift));
8324 effect(KILL cr);
8325
8326 format %{ "shrq $dst, $shift" %}
8327 opcode(0xD3, 0x5); /* D3 /5 */
8328 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8329 ins_pipe(ialu_reg_reg);
8330 %}
8331
8332 // Logical Shift Right by variable
8333 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8334 %{
8335 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8336 effect(KILL cr);
8337
8338 format %{ "shrq $dst, $shift" %}
8339 opcode(0xD3, 0x5); /* D3 /5 */
8340 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8341 ins_pipe(ialu_mem_reg);
8342 %}
8343
8344 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8345 // This idiom is used by the compiler for the i2b bytecode.
8346 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8347 %{
8348 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8349
8350 format %{ "movsbl $dst, $src\t# i2b" %}
8351 opcode(0x0F, 0xBE);
8352 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8353 ins_pipe(ialu_reg_reg);
8354 %}
8355
8356 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8357 // This idiom is used by the compiler the i2s bytecode.
8358 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8359 %{
8360 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8361
8362 format %{ "movswl $dst, $src\t# i2s" %}
8363 opcode(0x0F, 0xBF);
8364 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8365 ins_pipe(ialu_reg_reg);
8366 %}
8367
8368 // ROL/ROR instructions
8369
8370 // ROL expand
8371 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8372 effect(KILL cr, USE_DEF dst);
8373
8374 format %{ "roll $dst" %}
8375 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8376 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8377 ins_pipe(ialu_reg);
8378 %}
8379
8380 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8381 effect(USE_DEF dst, USE shift, KILL cr);
8382
8383 format %{ "roll $dst, $shift" %}
8384 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8385 ins_encode( reg_opc_imm(dst, shift) );
8386 ins_pipe(ialu_reg);
8387 %}
8388
8389 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8390 %{
8391 effect(USE_DEF dst, USE shift, KILL cr);
8392
8393 format %{ "roll $dst, $shift" %}
8394 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8395 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8396 ins_pipe(ialu_reg_reg);
8397 %}
8398 // end of ROL expand
8399
8400 // Rotate Left by one
8401 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8402 %{
8403 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8404
8405 expand %{
8406 rolI_rReg_imm1(dst, cr);
8407 %}
8408 %}
8409
8410 // Rotate Left by 8-bit immediate
8411 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8412 %{
8413 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8414 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8415
8416 expand %{
8417 rolI_rReg_imm8(dst, lshift, cr);
8418 %}
8419 %}
8420
8421 // Rotate Left by variable
8422 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8423 %{
8424 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8425
8426 expand %{
8427 rolI_rReg_CL(dst, shift, cr);
8428 %}
8429 %}
8430
8431 // Rotate Left by variable
8432 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8433 %{
8434 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8435
8436 expand %{
8437 rolI_rReg_CL(dst, shift, cr);
8438 %}
8439 %}
8440
8441 // ROR expand
8442 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8443 %{
8444 effect(USE_DEF dst, KILL cr);
8445
8446 format %{ "rorl $dst" %}
8447 opcode(0xD1, 0x1); /* D1 /1 */
8448 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8449 ins_pipe(ialu_reg);
8450 %}
8451
8452 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8453 %{
8454 effect(USE_DEF dst, USE shift, KILL cr);
8455
8456 format %{ "rorl $dst, $shift" %}
8457 opcode(0xC1, 0x1); /* C1 /1 ib */
8458 ins_encode(reg_opc_imm(dst, shift));
8459 ins_pipe(ialu_reg);
8460 %}
8461
8462 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8463 %{
8464 effect(USE_DEF dst, USE shift, KILL cr);
8465
8466 format %{ "rorl $dst, $shift" %}
8467 opcode(0xD3, 0x1); /* D3 /1 */
8468 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8469 ins_pipe(ialu_reg_reg);
8470 %}
8471 // end of ROR expand
8472
8473 // Rotate Right by one
8474 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8475 %{
8476 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8477
8478 expand %{
8479 rorI_rReg_imm1(dst, cr);
8480 %}
8481 %}
8482
8483 // Rotate Right by 8-bit immediate
8484 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8485 %{
8486 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8487 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8488
8489 expand %{
8490 rorI_rReg_imm8(dst, rshift, cr);
8491 %}
8492 %}
8493
8494 // Rotate Right by variable
8495 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8496 %{
8497 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8498
8499 expand %{
8500 rorI_rReg_CL(dst, shift, cr);
8501 %}
8502 %}
8503
8504 // Rotate Right by variable
8505 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8506 %{
8507 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8508
8509 expand %{
8510 rorI_rReg_CL(dst, shift, cr);
8511 %}
8512 %}
8513
8514 // for long rotate
8515 // ROL expand
8516 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8517 effect(USE_DEF dst, KILL cr);
8518
8519 format %{ "rolq $dst" %}
8520 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8521 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8522 ins_pipe(ialu_reg);
8523 %}
8524
8525 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8526 effect(USE_DEF dst, USE shift, KILL cr);
8527
8528 format %{ "rolq $dst, $shift" %}
8529 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8530 ins_encode( reg_opc_imm_wide(dst, shift) );
8531 ins_pipe(ialu_reg);
8532 %}
8533
8534 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8535 %{
8536 effect(USE_DEF dst, USE shift, KILL cr);
8537
8538 format %{ "rolq $dst, $shift" %}
8539 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8540 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8541 ins_pipe(ialu_reg_reg);
8542 %}
8543 // end of ROL expand
8544
8545 // Rotate Left by one
8546 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8547 %{
8548 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8549
8550 expand %{
8551 rolL_rReg_imm1(dst, cr);
8552 %}
8553 %}
8554
8555 // Rotate Left by 8-bit immediate
8556 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8557 %{
8558 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8559 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8560
8561 expand %{
8562 rolL_rReg_imm8(dst, lshift, cr);
8563 %}
8564 %}
8565
8566 // Rotate Left by variable
8567 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8568 %{
8569 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8570
8571 expand %{
8572 rolL_rReg_CL(dst, shift, cr);
8573 %}
8574 %}
8575
8576 // Rotate Left by variable
8577 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8578 %{
8579 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8580
8581 expand %{
8582 rolL_rReg_CL(dst, shift, cr);
8583 %}
8584 %}
8585
8586 // ROR expand
8587 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8588 %{
8589 effect(USE_DEF dst, KILL cr);
8590
8591 format %{ "rorq $dst" %}
8592 opcode(0xD1, 0x1); /* D1 /1 */
8593 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8594 ins_pipe(ialu_reg);
8595 %}
8596
8597 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8598 %{
8599 effect(USE_DEF dst, USE shift, KILL cr);
8600
8601 format %{ "rorq $dst, $shift" %}
8602 opcode(0xC1, 0x1); /* C1 /1 ib */
8603 ins_encode(reg_opc_imm_wide(dst, shift));
8604 ins_pipe(ialu_reg);
8605 %}
8606
8607 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8608 %{
8609 effect(USE_DEF dst, USE shift, KILL cr);
8610
8611 format %{ "rorq $dst, $shift" %}
8612 opcode(0xD3, 0x1); /* D3 /1 */
8613 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8614 ins_pipe(ialu_reg_reg);
8615 %}
8616 // end of ROR expand
8617
8618 // Rotate Right by one
8619 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8620 %{
8621 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8622
8623 expand %{
8624 rorL_rReg_imm1(dst, cr);
8625 %}
8626 %}
8627
8628 // Rotate Right by 8-bit immediate
8629 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8630 %{
8631 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8632 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8633
8634 expand %{
8635 rorL_rReg_imm8(dst, rshift, cr);
8636 %}
8637 %}
8638
8639 // Rotate Right by variable
8640 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8641 %{
8642 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8643
8644 expand %{
8645 rorL_rReg_CL(dst, shift, cr);
8646 %}
8647 %}
8648
8649 // Rotate Right by variable
8650 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8651 %{
8652 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8653
8654 expand %{
8655 rorL_rReg_CL(dst, shift, cr);
8656 %}
8657 %}
8658
8659 // Logical Instructions
8660
8661 // Integer Logical Instructions
8662
8663 // And Instructions
8664 // And Register with Register
8665 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8666 %{
8667 match(Set dst (AndI dst src));
8668 effect(KILL cr);
8669
8670 format %{ "andl $dst, $src\t# int" %}
8671 opcode(0x23);
8672 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8673 ins_pipe(ialu_reg_reg);
8674 %}
8675
8676 // And Register with Immediate 255
8677 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
8678 %{
8679 match(Set dst (AndI dst src));
8680
8681 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
8682 opcode(0x0F, 0xB6);
8683 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8684 ins_pipe(ialu_reg);
8685 %}
8686
8687 // And Register with Immediate 255 and promote to long
8688 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8689 %{
8690 match(Set dst (ConvI2L (AndI src mask)));
8691
8692 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8693 opcode(0x0F, 0xB6);
8694 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8695 ins_pipe(ialu_reg);
8696 %}
8697
8698 // And Register with Immediate 65535
8699 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
8700 %{
8701 match(Set dst (AndI dst src));
8702
8703 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
8704 opcode(0x0F, 0xB7);
8705 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8706 ins_pipe(ialu_reg);
8707 %}
8708
8709 // And Register with Immediate 65535 and promote to long
8710 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
8711 %{
8712 match(Set dst (ConvI2L (AndI src mask)));
8713
8714 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
8715 opcode(0x0F, 0xB7);
8716 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8717 ins_pipe(ialu_reg);
8718 %}
8719
8720 // And Register with Immediate
8721 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8722 %{
8723 match(Set dst (AndI dst src));
8724 effect(KILL cr);
8725
8726 format %{ "andl $dst, $src\t# int" %}
8727 opcode(0x81, 0x04); /* Opcode 81 /4 */
8728 ins_encode(OpcSErm(dst, src), Con8or32(src));
8729 ins_pipe(ialu_reg);
8730 %}
8731
8732 // And Register with Memory
8733 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8734 %{
8735 match(Set dst (AndI dst (LoadI src)));
8736 effect(KILL cr);
8737
8738 ins_cost(125);
8739 format %{ "andl $dst, $src\t# int" %}
8740 opcode(0x23);
8741 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8742 ins_pipe(ialu_reg_mem);
8743 %}
8744
8745 // And Memory with Register
8746 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8747 %{
8748 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8749 effect(KILL cr);
8750
8751 ins_cost(150);
8752 format %{ "andl $dst, $src\t# int" %}
8753 opcode(0x21); /* Opcode 21 /r */
8754 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8755 ins_pipe(ialu_mem_reg);
8756 %}
8757
8758 // And Memory with Immediate
8759 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
8760 %{
8761 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8762 effect(KILL cr);
8763
8764 ins_cost(125);
8765 format %{ "andl $dst, $src\t# int" %}
8766 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8767 ins_encode(REX_mem(dst), OpcSE(src),
8768 RM_opc_mem(secondary, dst), Con8or32(src));
8769 ins_pipe(ialu_mem_imm);
8770 %}
8771
8772 // BMI1 instructions
8773 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
8774 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
8775 predicate(UseBMI1Instructions);
8776 effect(KILL cr);
8777
8778 ins_cost(125);
8779 format %{ "andnl $dst, $src1, $src2" %}
8780
8781 ins_encode %{
8782 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
8783 %}
8784 ins_pipe(ialu_reg_mem);
8785 %}
8786
8787 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
8788 match(Set dst (AndI (XorI src1 minus_1) src2));
8789 predicate(UseBMI1Instructions);
8790 effect(KILL cr);
8791
8792 format %{ "andnl $dst, $src1, $src2" %}
8793
8794 ins_encode %{
8795 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
8796 %}
8797 ins_pipe(ialu_reg);
8798 %}
8799
8800 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
8801 match(Set dst (AndI (SubI imm_zero src) src));
8802 predicate(UseBMI1Instructions);
8803 effect(KILL cr);
8804
8805 format %{ "blsil $dst, $src" %}
8806
8807 ins_encode %{
8808 __ blsil($dst$$Register, $src$$Register);
8809 %}
8810 ins_pipe(ialu_reg);
8811 %}
8812
8813 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
8814 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
8815 predicate(UseBMI1Instructions);
8816 effect(KILL cr);
8817
8818 ins_cost(125);
8819 format %{ "blsil $dst, $src" %}
8820
8821 ins_encode %{
8822 __ blsil($dst$$Register, $src$$Address);
8823 %}
8824 ins_pipe(ialu_reg_mem);
8825 %}
8826
8827 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
8828 %{
8829 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
8830 predicate(UseBMI1Instructions);
8831 effect(KILL cr);
8832
8833 ins_cost(125);
8834 format %{ "blsmskl $dst, $src" %}
8835
8836 ins_encode %{
8837 __ blsmskl($dst$$Register, $src$$Address);
8838 %}
8839 ins_pipe(ialu_reg_mem);
8840 %}
8841
8842 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
8843 %{
8844 match(Set dst (XorI (AddI src minus_1) src));
8845 predicate(UseBMI1Instructions);
8846 effect(KILL cr);
8847
8848 format %{ "blsmskl $dst, $src" %}
8849
8850 ins_encode %{
8851 __ blsmskl($dst$$Register, $src$$Register);
8852 %}
8853
8854 ins_pipe(ialu_reg);
8855 %}
8856
8857 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
8858 %{
8859 match(Set dst (AndI (AddI src minus_1) src) );
8860 predicate(UseBMI1Instructions);
8861 effect(KILL cr);
8862
8863 format %{ "blsrl $dst, $src" %}
8864
8865 ins_encode %{
8866 __ blsrl($dst$$Register, $src$$Register);
8867 %}
8868
8869 ins_pipe(ialu_reg_mem);
8870 %}
8871
8872 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
8873 %{
8874 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
8875 predicate(UseBMI1Instructions);
8876 effect(KILL cr);
8877
8878 ins_cost(125);
8879 format %{ "blsrl $dst, $src" %}
8880
8881 ins_encode %{
8882 __ blsrl($dst$$Register, $src$$Address);
8883 %}
8884
8885 ins_pipe(ialu_reg);
8886 %}
8887
8888 // Or Instructions
8889 // Or Register with Register
8890 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8891 %{
8892 match(Set dst (OrI dst src));
8893 effect(KILL cr);
8894
8895 format %{ "orl $dst, $src\t# int" %}
8896 opcode(0x0B);
8897 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8898 ins_pipe(ialu_reg_reg);
8899 %}
8900
8901 // Or Register with Immediate
8902 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8903 %{
8904 match(Set dst (OrI dst src));
8905 effect(KILL cr);
8906
8907 format %{ "orl $dst, $src\t# int" %}
8908 opcode(0x81, 0x01); /* Opcode 81 /1 id */
8909 ins_encode(OpcSErm(dst, src), Con8or32(src));
8910 ins_pipe(ialu_reg);
8911 %}
8912
8913 // Or Register with Memory
8914 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8915 %{
8916 match(Set dst (OrI dst (LoadI src)));
8917 effect(KILL cr);
8918
8919 ins_cost(125);
8920 format %{ "orl $dst, $src\t# int" %}
8921 opcode(0x0B);
8922 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8923 ins_pipe(ialu_reg_mem);
8924 %}
8925
8926 // Or Memory with Register
8927 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8928 %{
8929 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8930 effect(KILL cr);
8931
8932 ins_cost(150);
8933 format %{ "orl $dst, $src\t# int" %}
8934 opcode(0x09); /* Opcode 09 /r */
8935 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8936 ins_pipe(ialu_mem_reg);
8937 %}
8938
8939 // Or Memory with Immediate
8940 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
8941 %{
8942 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8943 effect(KILL cr);
8944
8945 ins_cost(125);
8946 format %{ "orl $dst, $src\t# int" %}
8947 opcode(0x81, 0x1); /* Opcode 81 /1 id */
8948 ins_encode(REX_mem(dst), OpcSE(src),
8949 RM_opc_mem(secondary, dst), Con8or32(src));
8950 ins_pipe(ialu_mem_imm);
8951 %}
8952
8953 // Xor Instructions
8954 // Xor Register with Register
8955 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8956 %{
8957 match(Set dst (XorI dst src));
8958 effect(KILL cr);
8959
8960 format %{ "xorl $dst, $src\t# int" %}
8961 opcode(0x33);
8962 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8963 ins_pipe(ialu_reg_reg);
8964 %}
8965
8966 // Xor Register with Immediate -1
8967 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
8968 match(Set dst (XorI dst imm));
8969
8970 format %{ "not $dst" %}
8971 ins_encode %{
8972 __ notl($dst$$Register);
8973 %}
8974 ins_pipe(ialu_reg);
8975 %}
8976
8977 // Xor Register with Immediate
8978 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8979 %{
8980 match(Set dst (XorI dst src));
8981 effect(KILL cr);
8982
8983 format %{ "xorl $dst, $src\t# int" %}
8984 opcode(0x81, 0x06); /* Opcode 81 /6 id */
8985 ins_encode(OpcSErm(dst, src), Con8or32(src));
8986 ins_pipe(ialu_reg);
8987 %}
8988
8989 // Xor Register with Memory
8990 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8991 %{
8992 match(Set dst (XorI dst (LoadI src)));
8993 effect(KILL cr);
8994
8995 ins_cost(125);
8996 format %{ "xorl $dst, $src\t# int" %}
8997 opcode(0x33);
8998 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8999 ins_pipe(ialu_reg_mem);
9000 %}
9001
9002 // Xor Memory with Register
9003 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9004 %{
9005 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9006 effect(KILL cr);
9007
9008 ins_cost(150);
9009 format %{ "xorl $dst, $src\t# int" %}
9010 opcode(0x31); /* Opcode 31 /r */
9011 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9012 ins_pipe(ialu_mem_reg);
9013 %}
9014
9015 // Xor Memory with Immediate
9016 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9017 %{
9018 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9019 effect(KILL cr);
9020
9021 ins_cost(125);
9022 format %{ "xorl $dst, $src\t# int" %}
9023 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9024 ins_encode(REX_mem(dst), OpcSE(src),
9025 RM_opc_mem(secondary, dst), Con8or32(src));
9026 ins_pipe(ialu_mem_imm);
9027 %}
9028
9029
9030 // Long Logical Instructions
9031
9032 // And Instructions
9033 // And Register with Register
9034 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9035 %{
9036 match(Set dst (AndL dst src));
9037 effect(KILL cr);
9038
9039 format %{ "andq $dst, $src\t# long" %}
9040 opcode(0x23);
9041 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9042 ins_pipe(ialu_reg_reg);
9043 %}
9044
9045 // And Register with Immediate 255
9046 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9047 %{
9048 match(Set dst (AndL dst src));
9049
9050 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9051 opcode(0x0F, 0xB6);
9052 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9053 ins_pipe(ialu_reg);
9054 %}
9055
9056 // And Register with Immediate 65535
9057 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9058 %{
9059 match(Set dst (AndL dst src));
9060
9061 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9062 opcode(0x0F, 0xB7);
9063 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9064 ins_pipe(ialu_reg);
9065 %}
9066
9067 // And Register with Immediate
9068 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9069 %{
9070 match(Set dst (AndL dst src));
9071 effect(KILL cr);
9072
9073 format %{ "andq $dst, $src\t# long" %}
9074 opcode(0x81, 0x04); /* Opcode 81 /4 */
9075 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9076 ins_pipe(ialu_reg);
9077 %}
9078
9079 // And Register with Memory
9080 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9081 %{
9082 match(Set dst (AndL dst (LoadL src)));
9083 effect(KILL cr);
9084
9085 ins_cost(125);
9086 format %{ "andq $dst, $src\t# long" %}
9087 opcode(0x23);
9088 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9089 ins_pipe(ialu_reg_mem);
9090 %}
9091
9092 // And Memory with Register
9093 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9094 %{
9095 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9096 effect(KILL cr);
9097
9098 ins_cost(150);
9099 format %{ "andq $dst, $src\t# long" %}
9100 opcode(0x21); /* Opcode 21 /r */
9101 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9102 ins_pipe(ialu_mem_reg);
9103 %}
9104
9105 // And Memory with Immediate
9106 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9107 %{
9108 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9109 effect(KILL cr);
9110
9111 ins_cost(125);
9112 format %{ "andq $dst, $src\t# long" %}
9113 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9114 ins_encode(REX_mem_wide(dst), OpcSE(src),
9115 RM_opc_mem(secondary, dst), Con8or32(src));
9116 ins_pipe(ialu_mem_imm);
9117 %}
9118
9119 // BMI1 instructions
9120 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9121 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9122 predicate(UseBMI1Instructions);
9123 effect(KILL cr);
9124
9125 ins_cost(125);
9126 format %{ "andnq $dst, $src1, $src2" %}
9127
9128 ins_encode %{
9129 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9130 %}
9131 ins_pipe(ialu_reg_mem);
9132 %}
9133
9134 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9135 match(Set dst (AndL (XorL src1 minus_1) src2));
9136 predicate(UseBMI1Instructions);
9137 effect(KILL cr);
9138
9139 format %{ "andnq $dst, $src1, $src2" %}
9140
9141 ins_encode %{
9142 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9143 %}
9144 ins_pipe(ialu_reg_mem);
9145 %}
9146
9147 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9148 match(Set dst (AndL (SubL imm_zero src) src));
9149 predicate(UseBMI1Instructions);
9150 effect(KILL cr);
9151
9152 format %{ "blsiq $dst, $src" %}
9153
9154 ins_encode %{
9155 __ blsiq($dst$$Register, $src$$Register);
9156 %}
9157 ins_pipe(ialu_reg);
9158 %}
9159
9160 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9161 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9162 predicate(UseBMI1Instructions);
9163 effect(KILL cr);
9164
9165 ins_cost(125);
9166 format %{ "blsiq $dst, $src" %}
9167
9168 ins_encode %{
9169 __ blsiq($dst$$Register, $src$$Address);
9170 %}
9171 ins_pipe(ialu_reg_mem);
9172 %}
9173
9174 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9175 %{
9176 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9177 predicate(UseBMI1Instructions);
9178 effect(KILL cr);
9179
9180 ins_cost(125);
9181 format %{ "blsmskq $dst, $src" %}
9182
9183 ins_encode %{
9184 __ blsmskq($dst$$Register, $src$$Address);
9185 %}
9186 ins_pipe(ialu_reg_mem);
9187 %}
9188
9189 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9190 %{
9191 match(Set dst (XorL (AddL src minus_1) src));
9192 predicate(UseBMI1Instructions);
9193 effect(KILL cr);
9194
9195 format %{ "blsmskq $dst, $src" %}
9196
9197 ins_encode %{
9198 __ blsmskq($dst$$Register, $src$$Register);
9199 %}
9200
9201 ins_pipe(ialu_reg);
9202 %}
9203
9204 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9205 %{
9206 match(Set dst (AndL (AddL src minus_1) src) );
9207 predicate(UseBMI1Instructions);
9208 effect(KILL cr);
9209
9210 format %{ "blsrq $dst, $src" %}
9211
9212 ins_encode %{
9213 __ blsrq($dst$$Register, $src$$Register);
9214 %}
9215
9216 ins_pipe(ialu_reg);
9217 %}
9218
9219 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9220 %{
9221 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9222 predicate(UseBMI1Instructions);
9223 effect(KILL cr);
9224
9225 ins_cost(125);
9226 format %{ "blsrq $dst, $src" %}
9227
9228 ins_encode %{
9229 __ blsrq($dst$$Register, $src$$Address);
9230 %}
9231
9232 ins_pipe(ialu_reg);
9233 %}
9234
9235 // Or Instructions
9236 // Or Register with Register
9237 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9238 %{
9239 match(Set dst (OrL dst src));
9240 effect(KILL cr);
9241
9242 format %{ "orq $dst, $src\t# long" %}
9243 opcode(0x0B);
9244 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9245 ins_pipe(ialu_reg_reg);
9246 %}
9247
9248 // Use any_RegP to match R15 (TLS register) without spilling.
9249 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9250 match(Set dst (OrL dst (CastP2X src)));
9251 effect(KILL cr);
9252
9253 format %{ "orq $dst, $src\t# long" %}
9254 opcode(0x0B);
9255 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9256 ins_pipe(ialu_reg_reg);
9257 %}
9258
9259
9260 // Or Register with Immediate
9261 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9262 %{
9263 match(Set dst (OrL dst src));
9264 effect(KILL cr);
9265
9266 format %{ "orq $dst, $src\t# long" %}
9267 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9268 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9269 ins_pipe(ialu_reg);
9270 %}
9271
9272 // Or Register with Memory
9273 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9274 %{
9275 match(Set dst (OrL dst (LoadL src)));
9276 effect(KILL cr);
9277
9278 ins_cost(125);
9279 format %{ "orq $dst, $src\t# long" %}
9280 opcode(0x0B);
9281 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9282 ins_pipe(ialu_reg_mem);
9283 %}
9284
9285 // Or Memory with Register
9286 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9287 %{
9288 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9289 effect(KILL cr);
9290
9291 ins_cost(150);
9292 format %{ "orq $dst, $src\t# long" %}
9293 opcode(0x09); /* Opcode 09 /r */
9294 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9295 ins_pipe(ialu_mem_reg);
9296 %}
9297
9298 // Or Memory with Immediate
9299 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9300 %{
9301 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9302 effect(KILL cr);
9303
9304 ins_cost(125);
9305 format %{ "orq $dst, $src\t# long" %}
9306 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9307 ins_encode(REX_mem_wide(dst), OpcSE(src),
9308 RM_opc_mem(secondary, dst), Con8or32(src));
9309 ins_pipe(ialu_mem_imm);
9310 %}
9311
9312 // Xor Instructions
9313 // Xor Register with Register
9314 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9315 %{
9316 match(Set dst (XorL dst src));
9317 effect(KILL cr);
9318
9319 format %{ "xorq $dst, $src\t# long" %}
9320 opcode(0x33);
9321 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9322 ins_pipe(ialu_reg_reg);
9323 %}
9324
9325 // Xor Register with Immediate -1
9326 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9327 match(Set dst (XorL dst imm));
9328
9329 format %{ "notq $dst" %}
9330 ins_encode %{
9331 __ notq($dst$$Register);
9332 %}
9333 ins_pipe(ialu_reg);
9334 %}
9335
9336 // Xor Register with Immediate
9337 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9338 %{
9339 match(Set dst (XorL dst src));
9340 effect(KILL cr);
9341
9342 format %{ "xorq $dst, $src\t# long" %}
9343 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9344 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9345 ins_pipe(ialu_reg);
9346 %}
9347
9348 // Xor Register with Memory
9349 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9350 %{
9351 match(Set dst (XorL dst (LoadL src)));
9352 effect(KILL cr);
9353
9354 ins_cost(125);
9355 format %{ "xorq $dst, $src\t# long" %}
9356 opcode(0x33);
9357 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9358 ins_pipe(ialu_reg_mem);
9359 %}
9360
9361 // Xor Memory with Register
9362 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9363 %{
9364 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9365 effect(KILL cr);
9366
9367 ins_cost(150);
9368 format %{ "xorq $dst, $src\t# long" %}
9369 opcode(0x31); /* Opcode 31 /r */
9370 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9371 ins_pipe(ialu_mem_reg);
9372 %}
9373
9374 // Xor Memory with Immediate
9375 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9376 %{
9377 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9378 effect(KILL cr);
9379
9380 ins_cost(125);
9381 format %{ "xorq $dst, $src\t# long" %}
9382 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9383 ins_encode(REX_mem_wide(dst), OpcSE(src),
9384 RM_opc_mem(secondary, dst), Con8or32(src));
9385 ins_pipe(ialu_mem_imm);
9386 %}
9387
9388 // Convert Int to Boolean
9389 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9390 %{
9391 match(Set dst (Conv2B src));
9392 effect(KILL cr);
9393
9394 format %{ "testl $src, $src\t# ci2b\n\t"
9395 "setnz $dst\n\t"
9396 "movzbl $dst, $dst" %}
9397 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9398 setNZ_reg(dst),
9399 REX_reg_breg(dst, dst), // movzbl
9400 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9401 ins_pipe(pipe_slow); // XXX
9402 %}
9403
9404 // Convert Pointer to Boolean
9405 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9406 %{
9407 match(Set dst (Conv2B src));
9408 effect(KILL cr);
9409
9410 format %{ "testq $src, $src\t# cp2b\n\t"
9411 "setnz $dst\n\t"
9412 "movzbl $dst, $dst" %}
9413 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9414 setNZ_reg(dst),
9415 REX_reg_breg(dst, dst), // movzbl
9416 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9417 ins_pipe(pipe_slow); // XXX
9418 %}
9419
9420 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9421 %{
9422 match(Set dst (CmpLTMask p q));
9423 effect(KILL cr);
9424
9425 ins_cost(400);
9426 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9427 "setlt $dst\n\t"
9428 "movzbl $dst, $dst\n\t"
9429 "negl $dst" %}
9430 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9431 setLT_reg(dst),
9432 REX_reg_breg(dst, dst), // movzbl
9433 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9434 neg_reg(dst));
9435 ins_pipe(pipe_slow);
9436 %}
9437
9438 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9439 %{
9440 match(Set dst (CmpLTMask dst zero));
9441 effect(KILL cr);
9442
9443 ins_cost(100);
9444 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9445 ins_encode %{
9446 __ sarl($dst$$Register, 31);
9447 %}
9448 ins_pipe(ialu_reg);
9449 %}
9450
9451 /* Better to save a register than avoid a branch */
9452 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9453 %{
9454 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9455 effect(KILL cr);
9456 ins_cost(300);
9457 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
9458 "jge done\n\t"
9459 "addl $p,$y\n"
9460 "done: " %}
9461 ins_encode %{
9462 Register Rp = $p$$Register;
9463 Register Rq = $q$$Register;
9464 Register Ry = $y$$Register;
9465 Label done;
9466 __ subl(Rp, Rq);
9467 __ jccb(Assembler::greaterEqual, done);
9468 __ addl(Rp, Ry);
9469 __ bind(done);
9470 %}
9471 ins_pipe(pipe_cmplt);
9472 %}
9473
9474 /* Better to save a register than avoid a branch */
9475 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9476 %{
9477 match(Set y (AndI (CmpLTMask p q) y));
9478 effect(KILL cr);
9479
9480 ins_cost(300);
9481
9482 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
9483 "jlt done\n\t"
9484 "xorl $y, $y\n"
9485 "done: " %}
9486 ins_encode %{
9487 Register Rp = $p$$Register;
9488 Register Rq = $q$$Register;
9489 Register Ry = $y$$Register;
9490 Label done;
9491 __ cmpl(Rp, Rq);
9492 __ jccb(Assembler::less, done);
9493 __ xorl(Ry, Ry);
9494 __ bind(done);
9495 %}
9496 ins_pipe(pipe_cmplt);
9497 %}
9498
9499
9500 //---------- FP Instructions------------------------------------------------
9501
9502 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9503 %{
9504 match(Set cr (CmpF src1 src2));
9505
9506 ins_cost(145);
9507 format %{ "ucomiss $src1, $src2\n\t"
9508 "jnp,s exit\n\t"
9509 "pushfq\t# saw NaN, set CF\n\t"
9510 "andq [rsp], #0xffffff2b\n\t"
9511 "popfq\n"
9512 "exit:" %}
9513 ins_encode %{
9514 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9515 emit_cmpfp_fixup(_masm);
9516 %}
9517 ins_pipe(pipe_slow);
9518 %}
9519
9520 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9521 match(Set cr (CmpF src1 src2));
9522
9523 ins_cost(100);
9524 format %{ "ucomiss $src1, $src2" %}
9525 ins_encode %{
9526 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9527 %}
9528 ins_pipe(pipe_slow);
9529 %}
9530
9531 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9532 %{
9533 match(Set cr (CmpF src1 (LoadF src2)));
9534
9535 ins_cost(145);
9536 format %{ "ucomiss $src1, $src2\n\t"
9537 "jnp,s exit\n\t"
9538 "pushfq\t# saw NaN, set CF\n\t"
9539 "andq [rsp], #0xffffff2b\n\t"
9540 "popfq\n"
9541 "exit:" %}
9542 ins_encode %{
9543 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9544 emit_cmpfp_fixup(_masm);
9545 %}
9546 ins_pipe(pipe_slow);
9547 %}
9548
9549 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9550 match(Set cr (CmpF src1 (LoadF src2)));
9551
9552 ins_cost(100);
9553 format %{ "ucomiss $src1, $src2" %}
9554 ins_encode %{
9555 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9556 %}
9557 ins_pipe(pipe_slow);
9558 %}
9559
9560 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9561 match(Set cr (CmpF src con));
9562
9563 ins_cost(145);
9564 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9565 "jnp,s exit\n\t"
9566 "pushfq\t# saw NaN, set CF\n\t"
9567 "andq [rsp], #0xffffff2b\n\t"
9568 "popfq\n"
9569 "exit:" %}
9570 ins_encode %{
9571 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9572 emit_cmpfp_fixup(_masm);
9573 %}
9574 ins_pipe(pipe_slow);
9575 %}
9576
9577 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9578 match(Set cr (CmpF src con));
9579 ins_cost(100);
9580 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9581 ins_encode %{
9582 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9583 %}
9584 ins_pipe(pipe_slow);
9585 %}
9586
9587 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9588 %{
9589 match(Set cr (CmpD src1 src2));
9590
9591 ins_cost(145);
9592 format %{ "ucomisd $src1, $src2\n\t"
9593 "jnp,s exit\n\t"
9594 "pushfq\t# saw NaN, set CF\n\t"
9595 "andq [rsp], #0xffffff2b\n\t"
9596 "popfq\n"
9597 "exit:" %}
9598 ins_encode %{
9599 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9600 emit_cmpfp_fixup(_masm);
9601 %}
9602 ins_pipe(pipe_slow);
9603 %}
9604
9605 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9606 match(Set cr (CmpD src1 src2));
9607
9608 ins_cost(100);
9609 format %{ "ucomisd $src1, $src2 test" %}
9610 ins_encode %{
9611 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9612 %}
9613 ins_pipe(pipe_slow);
9614 %}
9615
9616 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9617 %{
9618 match(Set cr (CmpD src1 (LoadD src2)));
9619
9620 ins_cost(145);
9621 format %{ "ucomisd $src1, $src2\n\t"
9622 "jnp,s exit\n\t"
9623 "pushfq\t# saw NaN, set CF\n\t"
9624 "andq [rsp], #0xffffff2b\n\t"
9625 "popfq\n"
9626 "exit:" %}
9627 ins_encode %{
9628 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9629 emit_cmpfp_fixup(_masm);
9630 %}
9631 ins_pipe(pipe_slow);
9632 %}
9633
9634 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9635 match(Set cr (CmpD src1 (LoadD src2)));
9636
9637 ins_cost(100);
9638 format %{ "ucomisd $src1, $src2" %}
9639 ins_encode %{
9640 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9641 %}
9642 ins_pipe(pipe_slow);
9643 %}
9644
9645 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9646 match(Set cr (CmpD src con));
9647
9648 ins_cost(145);
9649 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9650 "jnp,s exit\n\t"
9651 "pushfq\t# saw NaN, set CF\n\t"
9652 "andq [rsp], #0xffffff2b\n\t"
9653 "popfq\n"
9654 "exit:" %}
9655 ins_encode %{
9656 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9657 emit_cmpfp_fixup(_masm);
9658 %}
9659 ins_pipe(pipe_slow);
9660 %}
9661
9662 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9663 match(Set cr (CmpD src con));
9664 ins_cost(100);
9665 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9666 ins_encode %{
9667 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9668 %}
9669 ins_pipe(pipe_slow);
9670 %}
9671
9672 // Compare into -1,0,1
9673 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9674 %{
9675 match(Set dst (CmpF3 src1 src2));
9676 effect(KILL cr);
9677
9678 ins_cost(275);
9679 format %{ "ucomiss $src1, $src2\n\t"
9680 "movl $dst, #-1\n\t"
9681 "jp,s done\n\t"
9682 "jb,s done\n\t"
9683 "setne $dst\n\t"
9684 "movzbl $dst, $dst\n"
9685 "done:" %}
9686 ins_encode %{
9687 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9688 emit_cmpfp3(_masm, $dst$$Register);
9689 %}
9690 ins_pipe(pipe_slow);
9691 %}
9692
9693 // Compare into -1,0,1
9694 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9695 %{
9696 match(Set dst (CmpF3 src1 (LoadF src2)));
9697 effect(KILL cr);
9698
9699 ins_cost(275);
9700 format %{ "ucomiss $src1, $src2\n\t"
9701 "movl $dst, #-1\n\t"
9702 "jp,s done\n\t"
9703 "jb,s done\n\t"
9704 "setne $dst\n\t"
9705 "movzbl $dst, $dst\n"
9706 "done:" %}
9707 ins_encode %{
9708 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9709 emit_cmpfp3(_masm, $dst$$Register);
9710 %}
9711 ins_pipe(pipe_slow);
9712 %}
9713
9714 // Compare into -1,0,1
9715 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9716 match(Set dst (CmpF3 src con));
9717 effect(KILL cr);
9718
9719 ins_cost(275);
9720 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9721 "movl $dst, #-1\n\t"
9722 "jp,s done\n\t"
9723 "jb,s done\n\t"
9724 "setne $dst\n\t"
9725 "movzbl $dst, $dst\n"
9726 "done:" %}
9727 ins_encode %{
9728 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9729 emit_cmpfp3(_masm, $dst$$Register);
9730 %}
9731 ins_pipe(pipe_slow);
9732 %}
9733
9734 // Compare into -1,0,1
9735 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9736 %{
9737 match(Set dst (CmpD3 src1 src2));
9738 effect(KILL cr);
9739
9740 ins_cost(275);
9741 format %{ "ucomisd $src1, $src2\n\t"
9742 "movl $dst, #-1\n\t"
9743 "jp,s done\n\t"
9744 "jb,s done\n\t"
9745 "setne $dst\n\t"
9746 "movzbl $dst, $dst\n"
9747 "done:" %}
9748 ins_encode %{
9749 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9750 emit_cmpfp3(_masm, $dst$$Register);
9751 %}
9752 ins_pipe(pipe_slow);
9753 %}
9754
9755 // Compare into -1,0,1
9756 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
9757 %{
9758 match(Set dst (CmpD3 src1 (LoadD src2)));
9759 effect(KILL cr);
9760
9761 ins_cost(275);
9762 format %{ "ucomisd $src1, $src2\n\t"
9763 "movl $dst, #-1\n\t"
9764 "jp,s done\n\t"
9765 "jb,s done\n\t"
9766 "setne $dst\n\t"
9767 "movzbl $dst, $dst\n"
9768 "done:" %}
9769 ins_encode %{
9770 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9771 emit_cmpfp3(_masm, $dst$$Register);
9772 %}
9773 ins_pipe(pipe_slow);
9774 %}
9775
9776 // Compare into -1,0,1
9777 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
9778 match(Set dst (CmpD3 src con));
9779 effect(KILL cr);
9780
9781 ins_cost(275);
9782 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9783 "movl $dst, #-1\n\t"
9784 "jp,s done\n\t"
9785 "jb,s done\n\t"
9786 "setne $dst\n\t"
9787 "movzbl $dst, $dst\n"
9788 "done:" %}
9789 ins_encode %{
9790 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9791 emit_cmpfp3(_masm, $dst$$Register);
9792 %}
9793 ins_pipe(pipe_slow);
9794 %}
9795
9796 // -----------Trig and Trancendental Instructions------------------------------
9797 instruct cosD_reg(regD dst) %{
9798 match(Set dst (CosD dst));
9799
9800 format %{ "dcos $dst\n\t" %}
9801 opcode(0xD9, 0xFF);
9802 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9803 ins_pipe( pipe_slow );
9804 %}
9805
9806 instruct sinD_reg(regD dst) %{
9807 match(Set dst (SinD dst));
9808
9809 format %{ "dsin $dst\n\t" %}
9810 opcode(0xD9, 0xFE);
9811 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9812 ins_pipe( pipe_slow );
9813 %}
9814
9815 instruct tanD_reg(regD dst) %{
9816 match(Set dst (TanD dst));
9817
9818 format %{ "dtan $dst\n\t" %}
9819 ins_encode( Push_SrcXD(dst),
9820 Opcode(0xD9), Opcode(0xF2), //fptan
9821 Opcode(0xDD), Opcode(0xD8), //fstp st
9822 Push_ResultXD(dst) );
9823 ins_pipe( pipe_slow );
9824 %}
9825
9826 instruct log10D_reg(regD dst) %{
9827 // The source and result Double operands in XMM registers
9828 match(Set dst (Log10D dst));
9829 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9830 // fyl2x ; compute log_10(2) * log_2(x)
9831 format %{ "fldlg2\t\t\t#Log10\n\t"
9832 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
9833 %}
9834 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
9835 Push_SrcXD(dst),
9836 Opcode(0xD9), Opcode(0xF1), // fyl2x
9837 Push_ResultXD(dst));
9838
9839 ins_pipe( pipe_slow );
9840 %}
9841
9842 instruct logD_reg(regD dst) %{
9843 // The source and result Double operands in XMM registers
9844 match(Set dst (LogD dst));
9845 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9846 // fyl2x ; compute log_e(2) * log_2(x)
9847 format %{ "fldln2\t\t\t#Log_e\n\t"
9848 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
9849 %}
9850 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9851 Push_SrcXD(dst),
9852 Opcode(0xD9), Opcode(0xF1), // fyl2x
9853 Push_ResultXD(dst));
9854 ins_pipe( pipe_slow );
9855 %}
9856
9857 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9858 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9859 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9860 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9861 ins_encode %{
9862 __ subptr(rsp, 8);
9863 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9864 __ fld_d(Address(rsp, 0));
9865 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9866 __ fld_d(Address(rsp, 0));
9867 __ fast_pow();
9868 __ fstp_d(Address(rsp, 0));
9869 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9870 __ addptr(rsp, 8);
9871 %}
9872 ins_pipe( pipe_slow );
9873 %}
9874
9875 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9876 match(Set dst (ExpD src));
9877 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9878 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9879 ins_encode %{
9880 __ subptr(rsp, 8);
9881 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9882 __ fld_d(Address(rsp, 0));
9883 __ fast_exp();
9884 __ fstp_d(Address(rsp, 0));
9885 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9886 __ addptr(rsp, 8);
9887 %}
9888 ins_pipe( pipe_slow );
9889 %}
9890
9891 //----------Arithmetic Conversion Instructions---------------------------------
9892
9893 instruct roundFloat_nop(regF dst)
9894 %{
9895 match(Set dst (RoundFloat dst));
9896
9897 ins_cost(0);
9898 ins_encode();
9899 ins_pipe(empty);
9900 %}
9901
9902 instruct roundDouble_nop(regD dst)
9903 %{
9904 match(Set dst (RoundDouble dst));
9905
9906 ins_cost(0);
9907 ins_encode();
9908 ins_pipe(empty);
9909 %}
9910
9911 instruct convF2D_reg_reg(regD dst, regF src)
9912 %{
9913 match(Set dst (ConvF2D src));
9914
9915 format %{ "cvtss2sd $dst, $src" %}
9916 ins_encode %{
9917 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
9918 %}
9919 ins_pipe(pipe_slow); // XXX
9920 %}
9921
9922 instruct convF2D_reg_mem(regD dst, memory src)
9923 %{
9924 match(Set dst (ConvF2D (LoadF src)));
9925
9926 format %{ "cvtss2sd $dst, $src" %}
9927 ins_encode %{
9928 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
9929 %}
9930 ins_pipe(pipe_slow); // XXX
9931 %}
9932
9933 instruct convD2F_reg_reg(regF dst, regD src)
9934 %{
9935 match(Set dst (ConvD2F src));
9936
9937 format %{ "cvtsd2ss $dst, $src" %}
9938 ins_encode %{
9939 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
9940 %}
9941 ins_pipe(pipe_slow); // XXX
9942 %}
9943
9944 instruct convD2F_reg_mem(regF dst, memory src)
9945 %{
9946 match(Set dst (ConvD2F (LoadD src)));
9947
9948 format %{ "cvtsd2ss $dst, $src" %}
9949 ins_encode %{
9950 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
9951 %}
9952 ins_pipe(pipe_slow); // XXX
9953 %}
9954
9955 // XXX do mem variants
9956 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
9957 %{
9958 match(Set dst (ConvF2I src));
9959 effect(KILL cr);
9960
9961 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
9962 "cmpl $dst, #0x80000000\n\t"
9963 "jne,s done\n\t"
9964 "subq rsp, #8\n\t"
9965 "movss [rsp], $src\n\t"
9966 "call f2i_fixup\n\t"
9967 "popq $dst\n"
9968 "done: "%}
9969 ins_encode %{
9970 Label done;
9971 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
9972 __ cmpl($dst$$Register, 0x80000000);
9973 __ jccb(Assembler::notEqual, done);
9974 __ subptr(rsp, 8);
9975 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9976 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9977 __ pop($dst$$Register);
9978 __ bind(done);
9979 %}
9980 ins_pipe(pipe_slow);
9981 %}
9982
9983 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
9984 %{
9985 match(Set dst (ConvF2L src));
9986 effect(KILL cr);
9987
9988 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
9989 "cmpq $dst, [0x8000000000000000]\n\t"
9990 "jne,s done\n\t"
9991 "subq rsp, #8\n\t"
9992 "movss [rsp], $src\n\t"
9993 "call f2l_fixup\n\t"
9994 "popq $dst\n"
9995 "done: "%}
9996 ins_encode %{
9997 Label done;
9998 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
9999 __ cmp64($dst$$Register,
10000 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10001 __ jccb(Assembler::notEqual, done);
10002 __ subptr(rsp, 8);
10003 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10004 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10005 __ pop($dst$$Register);
10006 __ bind(done);
10007 %}
10008 ins_pipe(pipe_slow);
10009 %}
10010
10011 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10012 %{
10013 match(Set dst (ConvD2I src));
10014 effect(KILL cr);
10015
10016 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10017 "cmpl $dst, #0x80000000\n\t"
10018 "jne,s done\n\t"
10019 "subq rsp, #8\n\t"
10020 "movsd [rsp], $src\n\t"
10021 "call d2i_fixup\n\t"
10022 "popq $dst\n"
10023 "done: "%}
10024 ins_encode %{
10025 Label done;
10026 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10027 __ cmpl($dst$$Register, 0x80000000);
10028 __ jccb(Assembler::notEqual, done);
10029 __ subptr(rsp, 8);
10030 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10031 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10032 __ pop($dst$$Register);
10033 __ bind(done);
10034 %}
10035 ins_pipe(pipe_slow);
10036 %}
10037
10038 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10039 %{
10040 match(Set dst (ConvD2L src));
10041 effect(KILL cr);
10042
10043 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10044 "cmpq $dst, [0x8000000000000000]\n\t"
10045 "jne,s done\n\t"
10046 "subq rsp, #8\n\t"
10047 "movsd [rsp], $src\n\t"
10048 "call d2l_fixup\n\t"
10049 "popq $dst\n"
10050 "done: "%}
10051 ins_encode %{
10052 Label done;
10053 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10054 __ cmp64($dst$$Register,
10055 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10056 __ jccb(Assembler::notEqual, done);
10057 __ subptr(rsp, 8);
10058 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10059 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10060 __ pop($dst$$Register);
10061 __ bind(done);
10062 %}
10063 ins_pipe(pipe_slow);
10064 %}
10065
10066 instruct convI2F_reg_reg(regF dst, rRegI src)
10067 %{
10068 predicate(!UseXmmI2F);
10069 match(Set dst (ConvI2F src));
10070
10071 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10072 ins_encode %{
10073 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10074 %}
10075 ins_pipe(pipe_slow); // XXX
10076 %}
10077
10078 instruct convI2F_reg_mem(regF dst, memory src)
10079 %{
10080 match(Set dst (ConvI2F (LoadI src)));
10081
10082 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10083 ins_encode %{
10084 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10085 %}
10086 ins_pipe(pipe_slow); // XXX
10087 %}
10088
10089 instruct convI2D_reg_reg(regD dst, rRegI src)
10090 %{
10091 predicate(!UseXmmI2D);
10092 match(Set dst (ConvI2D src));
10093
10094 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10095 ins_encode %{
10096 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10097 %}
10098 ins_pipe(pipe_slow); // XXX
10099 %}
10100
10101 instruct convI2D_reg_mem(regD dst, memory src)
10102 %{
10103 match(Set dst (ConvI2D (LoadI src)));
10104
10105 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10106 ins_encode %{
10107 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10108 %}
10109 ins_pipe(pipe_slow); // XXX
10110 %}
10111
10112 instruct convXI2F_reg(regF dst, rRegI src)
10113 %{
10114 predicate(UseXmmI2F);
10115 match(Set dst (ConvI2F src));
10116
10117 format %{ "movdl $dst, $src\n\t"
10118 "cvtdq2psl $dst, $dst\t# i2f" %}
10119 ins_encode %{
10120 __ movdl($dst$$XMMRegister, $src$$Register);
10121 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10122 %}
10123 ins_pipe(pipe_slow); // XXX
10124 %}
10125
10126 instruct convXI2D_reg(regD dst, rRegI src)
10127 %{
10128 predicate(UseXmmI2D);
10129 match(Set dst (ConvI2D src));
10130
10131 format %{ "movdl $dst, $src\n\t"
10132 "cvtdq2pdl $dst, $dst\t# i2d" %}
10133 ins_encode %{
10134 __ movdl($dst$$XMMRegister, $src$$Register);
10135 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10136 %}
10137 ins_pipe(pipe_slow); // XXX
10138 %}
10139
10140 instruct convL2F_reg_reg(regF dst, rRegL src)
10141 %{
10142 match(Set dst (ConvL2F src));
10143
10144 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10145 ins_encode %{
10146 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10147 %}
10148 ins_pipe(pipe_slow); // XXX
10149 %}
10150
10151 instruct convL2F_reg_mem(regF dst, memory src)
10152 %{
10153 match(Set dst (ConvL2F (LoadL src)));
10154
10155 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10156 ins_encode %{
10157 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10158 %}
10159 ins_pipe(pipe_slow); // XXX
10160 %}
10161
10162 instruct convL2D_reg_reg(regD dst, rRegL src)
10163 %{
10164 match(Set dst (ConvL2D src));
10165
10166 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10167 ins_encode %{
10168 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10169 %}
10170 ins_pipe(pipe_slow); // XXX
10171 %}
10172
10173 instruct convL2D_reg_mem(regD dst, memory src)
10174 %{
10175 match(Set dst (ConvL2D (LoadL src)));
10176
10177 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10178 ins_encode %{
10179 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10180 %}
10181 ins_pipe(pipe_slow); // XXX
10182 %}
10183
10184 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10185 %{
10186 match(Set dst (ConvI2L src));
10187
10188 ins_cost(125);
10189 format %{ "movslq $dst, $src\t# i2l" %}
10190 ins_encode %{
10191 __ movslq($dst$$Register, $src$$Register);
10192 %}
10193 ins_pipe(ialu_reg_reg);
10194 %}
10195
10196 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10197 // %{
10198 // match(Set dst (ConvI2L src));
10199 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10200 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10201 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10202 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10203 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10204 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10205
10206 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10207 // ins_encode(enc_copy(dst, src));
10208 // // opcode(0x63); // needs REX.W
10209 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10210 // ins_pipe(ialu_reg_reg);
10211 // %}
10212
10213 // Zero-extend convert int to long
10214 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10215 %{
10216 match(Set dst (AndL (ConvI2L src) mask));
10217
10218 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10219 ins_encode %{
10220 if ($dst$$reg != $src$$reg) {
10221 __ movl($dst$$Register, $src$$Register);
10222 }
10223 %}
10224 ins_pipe(ialu_reg_reg);
10225 %}
10226
10227 // Zero-extend convert int to long
10228 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10229 %{
10230 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10231
10232 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10233 ins_encode %{
10234 __ movl($dst$$Register, $src$$Address);
10235 %}
10236 ins_pipe(ialu_reg_mem);
10237 %}
10238
10239 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10240 %{
10241 match(Set dst (AndL src mask));
10242
10243 format %{ "movl $dst, $src\t# zero-extend long" %}
10244 ins_encode %{
10245 __ movl($dst$$Register, $src$$Register);
10246 %}
10247 ins_pipe(ialu_reg_reg);
10248 %}
10249
10250 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10251 %{
10252 match(Set dst (ConvL2I src));
10253
10254 format %{ "movl $dst, $src\t# l2i" %}
10255 ins_encode %{
10256 __ movl($dst$$Register, $src$$Register);
10257 %}
10258 ins_pipe(ialu_reg_reg);
10259 %}
10260
10261
10262 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10263 match(Set dst (MoveF2I src));
10264 effect(DEF dst, USE src);
10265
10266 ins_cost(125);
10267 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10268 ins_encode %{
10269 __ movl($dst$$Register, Address(rsp, $src$$disp));
10270 %}
10271 ins_pipe(ialu_reg_mem);
10272 %}
10273
10274 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10275 match(Set dst (MoveI2F src));
10276 effect(DEF dst, USE src);
10277
10278 ins_cost(125);
10279 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10280 ins_encode %{
10281 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10282 %}
10283 ins_pipe(pipe_slow);
10284 %}
10285
10286 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10287 match(Set dst (MoveD2L src));
10288 effect(DEF dst, USE src);
10289
10290 ins_cost(125);
10291 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10292 ins_encode %{
10293 __ movq($dst$$Register, Address(rsp, $src$$disp));
10294 %}
10295 ins_pipe(ialu_reg_mem);
10296 %}
10297
10298 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10299 predicate(!UseXmmLoadAndClearUpper);
10300 match(Set dst (MoveL2D src));
10301 effect(DEF dst, USE src);
10302
10303 ins_cost(125);
10304 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10305 ins_encode %{
10306 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10307 %}
10308 ins_pipe(pipe_slow);
10309 %}
10310
10311 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10312 predicate(UseXmmLoadAndClearUpper);
10313 match(Set dst (MoveL2D src));
10314 effect(DEF dst, USE src);
10315
10316 ins_cost(125);
10317 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10318 ins_encode %{
10319 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10320 %}
10321 ins_pipe(pipe_slow);
10322 %}
10323
10324
10325 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10326 match(Set dst (MoveF2I src));
10327 effect(DEF dst, USE src);
10328
10329 ins_cost(95); // XXX
10330 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10331 ins_encode %{
10332 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10333 %}
10334 ins_pipe(pipe_slow);
10335 %}
10336
10337 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10338 match(Set dst (MoveI2F src));
10339 effect(DEF dst, USE src);
10340
10341 ins_cost(100);
10342 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10343 ins_encode %{
10344 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10345 %}
10346 ins_pipe( ialu_mem_reg );
10347 %}
10348
10349 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10350 match(Set dst (MoveD2L src));
10351 effect(DEF dst, USE src);
10352
10353 ins_cost(95); // XXX
10354 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10355 ins_encode %{
10356 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10357 %}
10358 ins_pipe(pipe_slow);
10359 %}
10360
10361 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10362 match(Set dst (MoveL2D src));
10363 effect(DEF dst, USE src);
10364
10365 ins_cost(100);
10366 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10367 ins_encode %{
10368 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10369 %}
10370 ins_pipe(ialu_mem_reg);
10371 %}
10372
10373 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10374 match(Set dst (MoveF2I src));
10375 effect(DEF dst, USE src);
10376 ins_cost(85);
10377 format %{ "movd $dst,$src\t# MoveF2I" %}
10378 ins_encode %{
10379 __ movdl($dst$$Register, $src$$XMMRegister);
10380 %}
10381 ins_pipe( pipe_slow );
10382 %}
10383
10384 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10385 match(Set dst (MoveD2L src));
10386 effect(DEF dst, USE src);
10387 ins_cost(85);
10388 format %{ "movd $dst,$src\t# MoveD2L" %}
10389 ins_encode %{
10390 __ movdq($dst$$Register, $src$$XMMRegister);
10391 %}
10392 ins_pipe( pipe_slow );
10393 %}
10394
10395 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10396 match(Set dst (MoveI2F src));
10397 effect(DEF dst, USE src);
10398 ins_cost(100);
10399 format %{ "movd $dst,$src\t# MoveI2F" %}
10400 ins_encode %{
10401 __ movdl($dst$$XMMRegister, $src$$Register);
10402 %}
10403 ins_pipe( pipe_slow );
10404 %}
10405
10406 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10407 match(Set dst (MoveL2D src));
10408 effect(DEF dst, USE src);
10409 ins_cost(100);
10410 format %{ "movd $dst,$src\t# MoveL2D" %}
10411 ins_encode %{
10412 __ movdq($dst$$XMMRegister, $src$$Register);
10413 %}
10414 ins_pipe( pipe_slow );
10415 %}
10416
10417
10418 // =======================================================================
10419 // fast clearing of an array
10420 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10421 rFlagsReg cr)
10422 %{
10423 predicate(!UseFastStosb);
10424 match(Set dummy (ClearArray cnt base));
10425 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10426
10427 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10428 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
10429 ins_encode %{
10430 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10431 %}
10432 ins_pipe(pipe_slow);
10433 %}
10434
10435 instruct rep_fast_stosb(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10436 rFlagsReg cr)
10437 %{
10438 predicate(UseFastStosb);
10439 match(Set dummy (ClearArray cnt base));
10440 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10441 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10442 "shlq rcx,3\t# Convert doublewords to bytes\n\t"
10443 "rep stosb\t# Store rax to *rdi++ while rcx--" %}
10444 ins_encode %{
10445 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10446 %}
10447 ins_pipe( pipe_slow );
10448 %}
10449
10450 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10451 rax_RegI result, regD tmp1, rFlagsReg cr)
10452 %{
10453 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10454 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10455
10456 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10457 ins_encode %{
10458 __ string_compare($str1$$Register, $str2$$Register,
10459 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10460 $tmp1$$XMMRegister);
10461 %}
10462 ins_pipe( pipe_slow );
10463 %}
10464
10465 // fast search of substring with known size.
10466 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10467 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10468 %{
10469 predicate(UseSSE42Intrinsics);
10470 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10471 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10472
10473 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10474 ins_encode %{
10475 int icnt2 = (int)$int_cnt2$$constant;
10476 if (icnt2 >= 8) {
10477 // IndexOf for constant substrings with size >= 8 elements
10478 // which don't need to be loaded through stack.
10479 __ string_indexofC8($str1$$Register, $str2$$Register,
10480 $cnt1$$Register, $cnt2$$Register,
10481 icnt2, $result$$Register,
10482 $vec$$XMMRegister, $tmp$$Register);
10483 } else {
10484 // Small strings are loaded through stack if they cross page boundary.
10485 __ string_indexof($str1$$Register, $str2$$Register,
10486 $cnt1$$Register, $cnt2$$Register,
10487 icnt2, $result$$Register,
10488 $vec$$XMMRegister, $tmp$$Register);
10489 }
10490 %}
10491 ins_pipe( pipe_slow );
10492 %}
10493
10494 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10495 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10496 %{
10497 predicate(UseSSE42Intrinsics);
10498 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10499 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10500
10501 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10502 ins_encode %{
10503 __ string_indexof($str1$$Register, $str2$$Register,
10504 $cnt1$$Register, $cnt2$$Register,
10505 (-1), $result$$Register,
10506 $vec$$XMMRegister, $tmp$$Register);
10507 %}
10508 ins_pipe( pipe_slow );
10509 %}
10510
10511 // fast string equals
10512 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10513 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10514 %{
10515 match(Set result (StrEquals (Binary str1 str2) cnt));
10516 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10517
10518 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10519 ins_encode %{
10520 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
10521 $cnt$$Register, $result$$Register, $tmp3$$Register,
10522 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10523 %}
10524 ins_pipe( pipe_slow );
10525 %}
10526
10527 // fast array equals
10528 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10529 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10530 %{
10531 match(Set result (AryEq ary1 ary2));
10532 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10533 //ins_cost(300);
10534
10535 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10536 ins_encode %{
10537 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
10538 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10539 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10540 %}
10541 ins_pipe( pipe_slow );
10542 %}
10543
10544 // encode char[] to byte[] in ISO_8859_1
10545 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10546 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10547 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10548 match(Set result (EncodeISOArray src (Binary dst len)));
10549 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10550
10551 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10552 ins_encode %{
10553 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10554 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10555 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10556 %}
10557 ins_pipe( pipe_slow );
10558 %}
10559
10560 //----------Overflow Math Instructions-----------------------------------------
10561
10562 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10563 %{
10564 match(Set cr (OverflowAddI op1 op2));
10565 effect(DEF cr, USE_KILL op1, USE op2);
10566
10567 format %{ "addl $op1, $op2\t# overflow check int" %}
10568
10569 ins_encode %{
10570 __ addl($op1$$Register, $op2$$Register);
10571 %}
10572 ins_pipe(ialu_reg_reg);
10573 %}
10574
10575 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10576 %{
10577 match(Set cr (OverflowAddI op1 op2));
10578 effect(DEF cr, USE_KILL op1, USE op2);
10579
10580 format %{ "addl $op1, $op2\t# overflow check int" %}
10581
10582 ins_encode %{
10583 __ addl($op1$$Register, $op2$$constant);
10584 %}
10585 ins_pipe(ialu_reg_reg);
10586 %}
10587
10588 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10589 %{
10590 match(Set cr (OverflowAddL op1 op2));
10591 effect(DEF cr, USE_KILL op1, USE op2);
10592
10593 format %{ "addq $op1, $op2\t# overflow check long" %}
10594 ins_encode %{
10595 __ addq($op1$$Register, $op2$$Register);
10596 %}
10597 ins_pipe(ialu_reg_reg);
10598 %}
10599
10600 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
10601 %{
10602 match(Set cr (OverflowAddL op1 op2));
10603 effect(DEF cr, USE_KILL op1, USE op2);
10604
10605 format %{ "addq $op1, $op2\t# overflow check long" %}
10606 ins_encode %{
10607 __ addq($op1$$Register, $op2$$constant);
10608 %}
10609 ins_pipe(ialu_reg_reg);
10610 %}
10611
10612 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10613 %{
10614 match(Set cr (OverflowSubI op1 op2));
10615
10616 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10617 ins_encode %{
10618 __ cmpl($op1$$Register, $op2$$Register);
10619 %}
10620 ins_pipe(ialu_reg_reg);
10621 %}
10622
10623 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10624 %{
10625 match(Set cr (OverflowSubI op1 op2));
10626
10627 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10628 ins_encode %{
10629 __ cmpl($op1$$Register, $op2$$constant);
10630 %}
10631 ins_pipe(ialu_reg_reg);
10632 %}
10633
10634 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10635 %{
10636 match(Set cr (OverflowSubL op1 op2));
10637
10638 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10639 ins_encode %{
10640 __ cmpq($op1$$Register, $op2$$Register);
10641 %}
10642 ins_pipe(ialu_reg_reg);
10643 %}
10644
10645 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10646 %{
10647 match(Set cr (OverflowSubL op1 op2));
10648
10649 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10650 ins_encode %{
10651 __ cmpq($op1$$Register, $op2$$constant);
10652 %}
10653 ins_pipe(ialu_reg_reg);
10654 %}
10655
10656 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
10657 %{
10658 match(Set cr (OverflowSubI zero op2));
10659 effect(DEF cr, USE_KILL op2);
10660
10661 format %{ "negl $op2\t# overflow check int" %}
10662 ins_encode %{
10663 __ negl($op2$$Register);
10664 %}
10665 ins_pipe(ialu_reg_reg);
10666 %}
10667
10668 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
10669 %{
10670 match(Set cr (OverflowSubL zero op2));
10671 effect(DEF cr, USE_KILL op2);
10672
10673 format %{ "negq $op2\t# overflow check long" %}
10674 ins_encode %{
10675 __ negq($op2$$Register);
10676 %}
10677 ins_pipe(ialu_reg_reg);
10678 %}
10679
10680 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10681 %{
10682 match(Set cr (OverflowMulI op1 op2));
10683 effect(DEF cr, USE_KILL op1, USE op2);
10684
10685 format %{ "imull $op1, $op2\t# overflow check int" %}
10686 ins_encode %{
10687 __ imull($op1$$Register, $op2$$Register);
10688 %}
10689 ins_pipe(ialu_reg_reg_alu0);
10690 %}
10691
10692 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
10693 %{
10694 match(Set cr (OverflowMulI op1 op2));
10695 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10696
10697 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
10698 ins_encode %{
10699 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
10700 %}
10701 ins_pipe(ialu_reg_reg_alu0);
10702 %}
10703
10704 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10705 %{
10706 match(Set cr (OverflowMulL op1 op2));
10707 effect(DEF cr, USE_KILL op1, USE op2);
10708
10709 format %{ "imulq $op1, $op2\t# overflow check long" %}
10710 ins_encode %{
10711 __ imulq($op1$$Register, $op2$$Register);
10712 %}
10713 ins_pipe(ialu_reg_reg_alu0);
10714 %}
10715
10716 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
10717 %{
10718 match(Set cr (OverflowMulL op1 op2));
10719 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10720
10721 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
10722 ins_encode %{
10723 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
10724 %}
10725 ins_pipe(ialu_reg_reg_alu0);
10726 %}
10727
10728
10729 //----------Control Flow Instructions------------------------------------------
10730 // Signed compare Instructions
10731
10732 // XXX more variants!!
10733 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10734 %{
10735 match(Set cr (CmpI op1 op2));
10736 effect(DEF cr, USE op1, USE op2);
10737
10738 format %{ "cmpl $op1, $op2" %}
10739 opcode(0x3B); /* Opcode 3B /r */
10740 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10741 ins_pipe(ialu_cr_reg_reg);
10742 %}
10743
10744 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10745 %{
10746 match(Set cr (CmpI op1 op2));
10747
10748 format %{ "cmpl $op1, $op2" %}
10749 opcode(0x81, 0x07); /* Opcode 81 /7 */
10750 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10751 ins_pipe(ialu_cr_reg_imm);
10752 %}
10753
10754 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
10755 %{
10756 match(Set cr (CmpI op1 (LoadI op2)));
10757
10758 ins_cost(500); // XXX
10759 format %{ "cmpl $op1, $op2" %}
10760 opcode(0x3B); /* Opcode 3B /r */
10761 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10762 ins_pipe(ialu_cr_reg_mem);
10763 %}
10764
10765 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
10766 %{
10767 match(Set cr (CmpI src zero));
10768
10769 format %{ "testl $src, $src" %}
10770 opcode(0x85);
10771 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10772 ins_pipe(ialu_cr_reg_imm);
10773 %}
10774
10775 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
10776 %{
10777 match(Set cr (CmpI (AndI src con) zero));
10778
10779 format %{ "testl $src, $con" %}
10780 opcode(0xF7, 0x00);
10781 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
10782 ins_pipe(ialu_cr_reg_imm);
10783 %}
10784
10785 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
10786 %{
10787 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
10788
10789 format %{ "testl $src, $mem" %}
10790 opcode(0x85);
10791 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
10792 ins_pipe(ialu_cr_reg_mem);
10793 %}
10794
10795 // Unsigned compare Instructions; really, same as signed except they
10796 // produce an rFlagsRegU instead of rFlagsReg.
10797 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
10798 %{
10799 match(Set cr (CmpU op1 op2));
10800
10801 format %{ "cmpl $op1, $op2\t# unsigned" %}
10802 opcode(0x3B); /* Opcode 3B /r */
10803 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10804 ins_pipe(ialu_cr_reg_reg);
10805 %}
10806
10807 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
10808 %{
10809 match(Set cr (CmpU op1 op2));
10810
10811 format %{ "cmpl $op1, $op2\t# unsigned" %}
10812 opcode(0x81,0x07); /* Opcode 81 /7 */
10813 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10814 ins_pipe(ialu_cr_reg_imm);
10815 %}
10816
10817 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
10818 %{
10819 match(Set cr (CmpU op1 (LoadI op2)));
10820
10821 ins_cost(500); // XXX
10822 format %{ "cmpl $op1, $op2\t# unsigned" %}
10823 opcode(0x3B); /* Opcode 3B /r */
10824 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10825 ins_pipe(ialu_cr_reg_mem);
10826 %}
10827
10828 // // // Cisc-spilled version of cmpU_rReg
10829 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
10830 // //%{
10831 // // match(Set cr (CmpU (LoadI op1) op2));
10832 // //
10833 // // format %{ "CMPu $op1,$op2" %}
10834 // // ins_cost(500);
10835 // // opcode(0x39); /* Opcode 39 /r */
10836 // // ins_encode( OpcP, reg_mem( op1, op2) );
10837 // //%}
10838
10839 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
10840 %{
10841 match(Set cr (CmpU src zero));
10842
10843 format %{ "testl $src, $src\t# unsigned" %}
10844 opcode(0x85);
10845 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10846 ins_pipe(ialu_cr_reg_imm);
10847 %}
10848
10849 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
10850 %{
10851 match(Set cr (CmpP op1 op2));
10852
10853 format %{ "cmpq $op1, $op2\t# ptr" %}
10854 opcode(0x3B); /* Opcode 3B /r */
10855 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10856 ins_pipe(ialu_cr_reg_reg);
10857 %}
10858
10859 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
10860 %{
10861 match(Set cr (CmpP op1 (LoadP op2)));
10862
10863 ins_cost(500); // XXX
10864 format %{ "cmpq $op1, $op2\t# ptr" %}
10865 opcode(0x3B); /* Opcode 3B /r */
10866 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10867 ins_pipe(ialu_cr_reg_mem);
10868 %}
10869
10870 // // // Cisc-spilled version of cmpP_rReg
10871 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
10872 // //%{
10873 // // match(Set cr (CmpP (LoadP op1) op2));
10874 // //
10875 // // format %{ "CMPu $op1,$op2" %}
10876 // // ins_cost(500);
10877 // // opcode(0x39); /* Opcode 39 /r */
10878 // // ins_encode( OpcP, reg_mem( op1, op2) );
10879 // //%}
10880
10881 // XXX this is generalized by compP_rReg_mem???
10882 // Compare raw pointer (used in out-of-heap check).
10883 // Only works because non-oop pointers must be raw pointers
10884 // and raw pointers have no anti-dependencies.
10885 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
10886 %{
10887 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
10888 match(Set cr (CmpP op1 (LoadP op2)));
10889
10890 format %{ "cmpq $op1, $op2\t# raw ptr" %}
10891 opcode(0x3B); /* Opcode 3B /r */
10892 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10893 ins_pipe(ialu_cr_reg_mem);
10894 %}
10895
10896 // This will generate a signed flags result. This should be OK since
10897 // any compare to a zero should be eq/neq.
10898 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
10899 %{
10900 match(Set cr (CmpP src zero));
10901
10902 format %{ "testq $src, $src\t# ptr" %}
10903 opcode(0x85);
10904 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10905 ins_pipe(ialu_cr_reg_imm);
10906 %}
10907
10908 // This will generate a signed flags result. This should be OK since
10909 // any compare to a zero should be eq/neq.
10910 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
10911 %{
10912 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
10913 match(Set cr (CmpP (LoadP op) zero));
10914
10915 ins_cost(500); // XXX
10916 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
10917 opcode(0xF7); /* Opcode F7 /0 */
10918 ins_encode(REX_mem_wide(op),
10919 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
10920 ins_pipe(ialu_cr_reg_imm);
10921 %}
10922
10923 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
10924 %{
10925 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
10926 match(Set cr (CmpP (LoadP mem) zero));
10927
10928 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
10929 ins_encode %{
10930 __ cmpq(r12, $mem$$Address);
10931 %}
10932 ins_pipe(ialu_cr_reg_mem);
10933 %}
10934
10935 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
10936 %{
10937 match(Set cr (CmpN op1 op2));
10938
10939 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10940 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
10941 ins_pipe(ialu_cr_reg_reg);
10942 %}
10943
10944 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
10945 %{
10946 match(Set cr (CmpN src (LoadN mem)));
10947
10948 format %{ "cmpl $src, $mem\t# compressed ptr" %}
10949 ins_encode %{
10950 __ cmpl($src$$Register, $mem$$Address);
10951 %}
10952 ins_pipe(ialu_cr_reg_mem);
10953 %}
10954
10955 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
10956 match(Set cr (CmpN op1 op2));
10957
10958 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10959 ins_encode %{
10960 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
10961 %}
10962 ins_pipe(ialu_cr_reg_imm);
10963 %}
10964
10965 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
10966 %{
10967 match(Set cr (CmpN src (LoadN mem)));
10968
10969 format %{ "cmpl $mem, $src\t# compressed ptr" %}
10970 ins_encode %{
10971 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
10972 %}
10973 ins_pipe(ialu_cr_reg_mem);
10974 %}
10975
10976 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
10977 match(Set cr (CmpN op1 op2));
10978
10979 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
10980 ins_encode %{
10981 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
10982 %}
10983 ins_pipe(ialu_cr_reg_imm);
10984 %}
10985
10986 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
10987 %{
10988 match(Set cr (CmpN src (LoadNKlass mem)));
10989
10990 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
10991 ins_encode %{
10992 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
10993 %}
10994 ins_pipe(ialu_cr_reg_mem);
10995 %}
10996
10997 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
10998 match(Set cr (CmpN src zero));
10999
11000 format %{ "testl $src, $src\t# compressed ptr" %}
11001 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11002 ins_pipe(ialu_cr_reg_imm);
11003 %}
11004
11005 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11006 %{
11007 predicate(Universe::narrow_oop_base() != NULL);
11008 match(Set cr (CmpN (LoadN mem) zero));
11009
11010 ins_cost(500); // XXX
11011 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11012 ins_encode %{
11013 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11014 %}
11015 ins_pipe(ialu_cr_reg_mem);
11016 %}
11017
11018 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11019 %{
11020 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
11021 match(Set cr (CmpN (LoadN mem) zero));
11022
11023 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11024 ins_encode %{
11025 __ cmpl(r12, $mem$$Address);
11026 %}
11027 ins_pipe(ialu_cr_reg_mem);
11028 %}
11029
11030 // Yanked all unsigned pointer compare operations.
11031 // Pointer compares are done with CmpP which is already unsigned.
11032
11033 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11034 %{
11035 match(Set cr (CmpL op1 op2));
11036
11037 format %{ "cmpq $op1, $op2" %}
11038 opcode(0x3B); /* Opcode 3B /r */
11039 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11040 ins_pipe(ialu_cr_reg_reg);
11041 %}
11042
11043 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11044 %{
11045 match(Set cr (CmpL op1 op2));
11046
11047 format %{ "cmpq $op1, $op2" %}
11048 opcode(0x81, 0x07); /* Opcode 81 /7 */
11049 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11050 ins_pipe(ialu_cr_reg_imm);
11051 %}
11052
11053 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11054 %{
11055 match(Set cr (CmpL op1 (LoadL op2)));
11056
11057 format %{ "cmpq $op1, $op2" %}
11058 opcode(0x3B); /* Opcode 3B /r */
11059 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11060 ins_pipe(ialu_cr_reg_mem);
11061 %}
11062
11063 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11064 %{
11065 match(Set cr (CmpL src zero));
11066
11067 format %{ "testq $src, $src" %}
11068 opcode(0x85);
11069 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11070 ins_pipe(ialu_cr_reg_imm);
11071 %}
11072
11073 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11074 %{
11075 match(Set cr (CmpL (AndL src con) zero));
11076
11077 format %{ "testq $src, $con\t# long" %}
11078 opcode(0xF7, 0x00);
11079 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11080 ins_pipe(ialu_cr_reg_imm);
11081 %}
11082
11083 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11084 %{
11085 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11086
11087 format %{ "testq $src, $mem" %}
11088 opcode(0x85);
11089 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11090 ins_pipe(ialu_cr_reg_mem);
11091 %}
11092
11093 // Manifest a CmpL result in an integer register. Very painful.
11094 // This is the test to avoid.
11095 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11096 %{
11097 match(Set dst (CmpL3 src1 src2));
11098 effect(KILL flags);
11099
11100 ins_cost(275); // XXX
11101 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11102 "movl $dst, -1\n\t"
11103 "jl,s done\n\t"
11104 "setne $dst\n\t"
11105 "movzbl $dst, $dst\n\t"
11106 "done:" %}
11107 ins_encode(cmpl3_flag(src1, src2, dst));
11108 ins_pipe(pipe_slow);
11109 %}
11110
11111 //----------Max and Min--------------------------------------------------------
11112 // Min Instructions
11113
11114 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11115 %{
11116 effect(USE_DEF dst, USE src, USE cr);
11117
11118 format %{ "cmovlgt $dst, $src\t# min" %}
11119 opcode(0x0F, 0x4F);
11120 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11121 ins_pipe(pipe_cmov_reg);
11122 %}
11123
11124
11125 instruct minI_rReg(rRegI dst, rRegI src)
11126 %{
11127 match(Set dst (MinI dst src));
11128
11129 ins_cost(200);
11130 expand %{
11131 rFlagsReg cr;
11132 compI_rReg(cr, dst, src);
11133 cmovI_reg_g(dst, src, cr);
11134 %}
11135 %}
11136
11137 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11138 %{
11139 effect(USE_DEF dst, USE src, USE cr);
11140
11141 format %{ "cmovllt $dst, $src\t# max" %}
11142 opcode(0x0F, 0x4C);
11143 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11144 ins_pipe(pipe_cmov_reg);
11145 %}
11146
11147
11148 instruct maxI_rReg(rRegI dst, rRegI src)
11149 %{
11150 match(Set dst (MaxI dst src));
11151
11152 ins_cost(200);
11153 expand %{
11154 rFlagsReg cr;
11155 compI_rReg(cr, dst, src);
11156 cmovI_reg_l(dst, src, cr);
11157 %}
11158 %}
11159
11160 // ============================================================================
11161 // Branch Instructions
11162
11163 // Jump Direct - Label defines a relative address from JMP+1
11164 instruct jmpDir(label labl)
11165 %{
11166 match(Goto);
11167 effect(USE labl);
11168
11169 ins_cost(300);
11170 format %{ "jmp $labl" %}
11171 size(5);
11172 ins_encode %{
11173 Label* L = $labl$$label;
11174 __ jmp(*L, false); // Always long jump
11175 %}
11176 ins_pipe(pipe_jmp);
11177 %}
11178
11179 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11180 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11181 %{
11182 match(If cop cr);
11183 effect(USE labl);
11184
11185 ins_cost(300);
11186 format %{ "j$cop $labl" %}
11187 size(6);
11188 ins_encode %{
11189 Label* L = $labl$$label;
11190 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11191 %}
11192 ins_pipe(pipe_jcc);
11193 %}
11194
11195 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11196 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11197 %{
11198 match(CountedLoopEnd cop cr);
11199 effect(USE labl);
11200
11201 ins_cost(300);
11202 format %{ "j$cop $labl\t# loop end" %}
11203 size(6);
11204 ins_encode %{
11205 Label* L = $labl$$label;
11206 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11207 %}
11208 ins_pipe(pipe_jcc);
11209 %}
11210
11211 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11212 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11213 match(CountedLoopEnd cop cmp);
11214 effect(USE labl);
11215
11216 ins_cost(300);
11217 format %{ "j$cop,u $labl\t# loop end" %}
11218 size(6);
11219 ins_encode %{
11220 Label* L = $labl$$label;
11221 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11222 %}
11223 ins_pipe(pipe_jcc);
11224 %}
11225
11226 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11227 match(CountedLoopEnd cop cmp);
11228 effect(USE labl);
11229
11230 ins_cost(200);
11231 format %{ "j$cop,u $labl\t# loop end" %}
11232 size(6);
11233 ins_encode %{
11234 Label* L = $labl$$label;
11235 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11236 %}
11237 ins_pipe(pipe_jcc);
11238 %}
11239
11240 // Jump Direct Conditional - using unsigned comparison
11241 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11242 match(If cop cmp);
11243 effect(USE labl);
11244
11245 ins_cost(300);
11246 format %{ "j$cop,u $labl" %}
11247 size(6);
11248 ins_encode %{
11249 Label* L = $labl$$label;
11250 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11251 %}
11252 ins_pipe(pipe_jcc);
11253 %}
11254
11255 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11256 match(If cop cmp);
11257 effect(USE labl);
11258
11259 ins_cost(200);
11260 format %{ "j$cop,u $labl" %}
11261 size(6);
11262 ins_encode %{
11263 Label* L = $labl$$label;
11264 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11265 %}
11266 ins_pipe(pipe_jcc);
11267 %}
11268
11269 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11270 match(If cop cmp);
11271 effect(USE labl);
11272
11273 ins_cost(200);
11274 format %{ $$template
11275 if ($cop$$cmpcode == Assembler::notEqual) {
11276 $$emit$$"jp,u $labl\n\t"
11277 $$emit$$"j$cop,u $labl"
11278 } else {
11279 $$emit$$"jp,u done\n\t"
11280 $$emit$$"j$cop,u $labl\n\t"
11281 $$emit$$"done:"
11282 }
11283 %}
11284 ins_encode %{
11285 Label* l = $labl$$label;
11286 if ($cop$$cmpcode == Assembler::notEqual) {
11287 __ jcc(Assembler::parity, *l, false);
11288 __ jcc(Assembler::notEqual, *l, false);
11289 } else if ($cop$$cmpcode == Assembler::equal) {
11290 Label done;
11291 __ jccb(Assembler::parity, done);
11292 __ jcc(Assembler::equal, *l, false);
11293 __ bind(done);
11294 } else {
11295 ShouldNotReachHere();
11296 }
11297 %}
11298 ins_pipe(pipe_jcc);
11299 %}
11300
11301 // ============================================================================
11302 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11303 // superklass array for an instance of the superklass. Set a hidden
11304 // internal cache on a hit (cache is checked with exposed code in
11305 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11306 // encoding ALSO sets flags.
11307
11308 instruct partialSubtypeCheck(rdi_RegP result,
11309 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11310 rFlagsReg cr)
11311 %{
11312 match(Set result (PartialSubtypeCheck sub super));
11313 effect(KILL rcx, KILL cr);
11314
11315 ins_cost(1100); // slightly larger than the next version
11316 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11317 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11318 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11319 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
11320 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
11321 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11322 "xorq $result, $result\t\t Hit: rdi zero\n\t"
11323 "miss:\t" %}
11324
11325 opcode(0x1); // Force a XOR of RDI
11326 ins_encode(enc_PartialSubtypeCheck());
11327 ins_pipe(pipe_slow);
11328 %}
11329
11330 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
11331 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11332 immP0 zero,
11333 rdi_RegP result)
11334 %{
11335 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11336 effect(KILL rcx, KILL result);
11337
11338 ins_cost(1000);
11339 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11340 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11341 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11342 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
11343 "jne,s miss\t\t# Missed: flags nz\n\t"
11344 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11345 "miss:\t" %}
11346
11347 opcode(0x0); // No need to XOR RDI
11348 ins_encode(enc_PartialSubtypeCheck());
11349 ins_pipe(pipe_slow);
11350 %}
11351
11352 // ============================================================================
11353 // Branch Instructions -- short offset versions
11354 //
11355 // These instructions are used to replace jumps of a long offset (the default
11356 // match) with jumps of a shorter offset. These instructions are all tagged
11357 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11358 // match rules in general matching. Instead, the ADLC generates a conversion
11359 // method in the MachNode which can be used to do in-place replacement of the
11360 // long variant with the shorter variant. The compiler will determine if a
11361 // branch can be taken by the is_short_branch_offset() predicate in the machine
11362 // specific code section of the file.
11363
11364 // Jump Direct - Label defines a relative address from JMP+1
11365 instruct jmpDir_short(label labl) %{
11366 match(Goto);
11367 effect(USE labl);
11368
11369 ins_cost(300);
11370 format %{ "jmp,s $labl" %}
11371 size(2);
11372 ins_encode %{
11373 Label* L = $labl$$label;
11374 __ jmpb(*L);
11375 %}
11376 ins_pipe(pipe_jmp);
11377 ins_short_branch(1);
11378 %}
11379
11380 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11381 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
11382 match(If cop cr);
11383 effect(USE labl);
11384
11385 ins_cost(300);
11386 format %{ "j$cop,s $labl" %}
11387 size(2);
11388 ins_encode %{
11389 Label* L = $labl$$label;
11390 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11391 %}
11392 ins_pipe(pipe_jcc);
11393 ins_short_branch(1);
11394 %}
11395
11396 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11397 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
11398 match(CountedLoopEnd cop cr);
11399 effect(USE labl);
11400
11401 ins_cost(300);
11402 format %{ "j$cop,s $labl\t# loop end" %}
11403 size(2);
11404 ins_encode %{
11405 Label* L = $labl$$label;
11406 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11407 %}
11408 ins_pipe(pipe_jcc);
11409 ins_short_branch(1);
11410 %}
11411
11412 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11413 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11414 match(CountedLoopEnd cop cmp);
11415 effect(USE labl);
11416
11417 ins_cost(300);
11418 format %{ "j$cop,us $labl\t# loop end" %}
11419 size(2);
11420 ins_encode %{
11421 Label* L = $labl$$label;
11422 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11423 %}
11424 ins_pipe(pipe_jcc);
11425 ins_short_branch(1);
11426 %}
11427
11428 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11429 match(CountedLoopEnd cop cmp);
11430 effect(USE labl);
11431
11432 ins_cost(300);
11433 format %{ "j$cop,us $labl\t# loop end" %}
11434 size(2);
11435 ins_encode %{
11436 Label* L = $labl$$label;
11437 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11438 %}
11439 ins_pipe(pipe_jcc);
11440 ins_short_branch(1);
11441 %}
11442
11443 // Jump Direct Conditional - using unsigned comparison
11444 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11445 match(If cop cmp);
11446 effect(USE labl);
11447
11448 ins_cost(300);
11449 format %{ "j$cop,us $labl" %}
11450 size(2);
11451 ins_encode %{
11452 Label* L = $labl$$label;
11453 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11454 %}
11455 ins_pipe(pipe_jcc);
11456 ins_short_branch(1);
11457 %}
11458
11459 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11460 match(If cop cmp);
11461 effect(USE labl);
11462
11463 ins_cost(300);
11464 format %{ "j$cop,us $labl" %}
11465 size(2);
11466 ins_encode %{
11467 Label* L = $labl$$label;
11468 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11469 %}
11470 ins_pipe(pipe_jcc);
11471 ins_short_branch(1);
11472 %}
11473
11474 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11475 match(If cop cmp);
11476 effect(USE labl);
11477
11478 ins_cost(300);
11479 format %{ $$template
11480 if ($cop$$cmpcode == Assembler::notEqual) {
11481 $$emit$$"jp,u,s $labl\n\t"
11482 $$emit$$"j$cop,u,s $labl"
11483 } else {
11484 $$emit$$"jp,u,s done\n\t"
11485 $$emit$$"j$cop,u,s $labl\n\t"
11486 $$emit$$"done:"
11487 }
11488 %}
11489 size(4);
11490 ins_encode %{
11491 Label* l = $labl$$label;
11492 if ($cop$$cmpcode == Assembler::notEqual) {
11493 __ jccb(Assembler::parity, *l);
11494 __ jccb(Assembler::notEqual, *l);
11495 } else if ($cop$$cmpcode == Assembler::equal) {
11496 Label done;
11497 __ jccb(Assembler::parity, done);
11498 __ jccb(Assembler::equal, *l);
11499 __ bind(done);
11500 } else {
11501 ShouldNotReachHere();
11502 }
11503 %}
11504 ins_pipe(pipe_jcc);
11505 ins_short_branch(1);
11506 %}
11507
11508 // ============================================================================
11509 // inlined locking and unlocking
11510
11511 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
11512 predicate(Compile::current()->use_rtm());
11513 match(Set cr (FastLock object box));
11514 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
11515 ins_cost(300);
11516 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
11517 ins_encode %{
11518 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
11519 $scr$$Register, $cx1$$Register, $cx2$$Register,
11520 _counters, _rtm_counters, _stack_rtm_counters,
11521 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
11522 true, ra_->C->profile_rtm());
11523 %}
11524 ins_pipe(pipe_slow);
11525 %}
11526
11527 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
11528 predicate(!Compile::current()->use_rtm());
11529 match(Set cr (FastLock object box));
11530 effect(TEMP tmp, TEMP scr, USE_KILL box);
11531 ins_cost(300);
11532 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
11533 ins_encode %{
11534 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
11535 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
11536 %}
11537 ins_pipe(pipe_slow);
11538 %}
11539
11540 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
11541 match(Set cr (FastUnlock object box));
11542 effect(TEMP tmp, USE_KILL box);
11543 ins_cost(300);
11544 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
11545 ins_encode %{
11546 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
11547 %}
11548 ins_pipe(pipe_slow);
11549 %}
11550
11551
11552 // ============================================================================
11553 // Safepoint Instructions
11554 instruct safePoint_poll(rFlagsReg cr)
11555 %{
11556 predicate(!Assembler::is_polling_page_far());
11557 match(SafePoint);
11558 effect(KILL cr);
11559
11560 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
11561 "# Safepoint: poll for GC" %}
11562 ins_cost(125);
11563 ins_encode %{
11564 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
11565 __ testl(rax, addr);
11566 %}
11567 ins_pipe(ialu_reg_mem);
11568 %}
11569
11570 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
11571 %{
11572 predicate(Assembler::is_polling_page_far());
11573 match(SafePoint poll);
11574 effect(KILL cr, USE poll);
11575
11576 format %{ "testl rax, [$poll]\t"
11577 "# Safepoint: poll for GC" %}
11578 ins_cost(125);
11579 ins_encode %{
11580 __ relocate(relocInfo::poll_type);
11581 __ testl(rax, Address($poll$$Register, 0));
11582 %}
11583 ins_pipe(ialu_reg_mem);
11584 %}
11585
11586 // ============================================================================
11587 // Procedure Call/Return Instructions
11588 // Call Java Static Instruction
11589 // Note: If this code changes, the corresponding ret_addr_offset() and
11590 // compute_padding() functions will have to be adjusted.
11591 instruct CallStaticJavaDirect(method meth) %{
11592 match(CallStaticJava);
11593 effect(USE meth);
11594
11595 ins_cost(300);
11596 format %{ "call,static " %}
11597 opcode(0xE8); /* E8 cd */
11598 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
11599 ins_pipe(pipe_slow);
11600 ins_alignment(4);
11601 %}
11602
11603 // Call Java Dynamic Instruction
11604 // Note: If this code changes, the corresponding ret_addr_offset() and
11605 // compute_padding() functions will have to be adjusted.
11606 instruct CallDynamicJavaDirect(method meth)
11607 %{
11608 match(CallDynamicJava);
11609 effect(USE meth);
11610
11611 ins_cost(300);
11612 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11613 "call,dynamic " %}
11614 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
11615 ins_pipe(pipe_slow);
11616 ins_alignment(4);
11617 %}
11618
11619 // Call Runtime Instruction
11620 instruct CallRuntimeDirect(method meth)
11621 %{
11622 match(CallRuntime);
11623 effect(USE meth);
11624
11625 ins_cost(300);
11626 format %{ "call,runtime " %}
11627 ins_encode(clear_avx, Java_To_Runtime(meth));
11628 ins_pipe(pipe_slow);
11629 %}
11630
11631 // Call runtime without safepoint
11632 instruct CallLeafDirect(method meth)
11633 %{
11634 match(CallLeaf);
11635 effect(USE meth);
11636
11637 ins_cost(300);
11638 format %{ "call_leaf,runtime " %}
11639 ins_encode(clear_avx, Java_To_Runtime(meth));
11640 ins_pipe(pipe_slow);
11641 %}
11642
11643 // Call runtime without safepoint
11644 instruct CallLeafNoFPDirect(method meth)
11645 %{
11646 match(CallLeafNoFP);
11647 effect(USE meth);
11648
11649 ins_cost(300);
11650 format %{ "call_leaf_nofp,runtime " %}
11651 ins_encode(Java_To_Runtime(meth));
11652 ins_pipe(pipe_slow);
11653 %}
11654
11655 // Return Instruction
11656 // Remove the return address & jump to it.
11657 // Notice: We always emit a nop after a ret to make sure there is room
11658 // for safepoint patching
11659 instruct Ret()
11660 %{
11661 match(Return);
11662
11663 format %{ "ret" %}
11664 opcode(0xC3);
11665 ins_encode(OpcP);
11666 ins_pipe(pipe_jmp);
11667 %}
11668
11669 // Tail Call; Jump from runtime stub to Java code.
11670 // Also known as an 'interprocedural jump'.
11671 // Target of jump will eventually return to caller.
11672 // TailJump below removes the return address.
11673 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
11674 %{
11675 match(TailCall jump_target method_oop);
11676
11677 ins_cost(300);
11678 format %{ "jmp $jump_target\t# rbx holds method oop" %}
11679 opcode(0xFF, 0x4); /* Opcode FF /4 */
11680 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
11681 ins_pipe(pipe_jmp);
11682 %}
11683
11684 // Tail Jump; remove the return address; jump to target.
11685 // TailCall above leaves the return address around.
11686 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
11687 %{
11688 match(TailJump jump_target ex_oop);
11689
11690 ins_cost(300);
11691 format %{ "popq rdx\t# pop return address\n\t"
11692 "jmp $jump_target" %}
11693 opcode(0xFF, 0x4); /* Opcode FF /4 */
11694 ins_encode(Opcode(0x5a), // popq rdx
11695 REX_reg(jump_target), OpcP, reg_opc(jump_target));
11696 ins_pipe(pipe_jmp);
11697 %}
11698
11699 // Create exception oop: created by stack-crawling runtime code.
11700 // Created exception is now available to this handler, and is setup
11701 // just prior to jumping to this handler. No code emitted.
11702 instruct CreateException(rax_RegP ex_oop)
11703 %{
11704 match(Set ex_oop (CreateEx));
11705
11706 size(0);
11707 // use the following format syntax
11708 format %{ "# exception oop is in rax; no code emitted" %}
11709 ins_encode();
11710 ins_pipe(empty);
11711 %}
11712
11713 // Rethrow exception:
11714 // The exception oop will come in the first argument position.
11715 // Then JUMP (not call) to the rethrow stub code.
11716 instruct RethrowException()
11717 %{
11718 match(Rethrow);
11719
11720 // use the following format syntax
11721 format %{ "jmp rethrow_stub" %}
11722 ins_encode(enc_rethrow);
11723 ins_pipe(pipe_jmp);
11724 %}
11725
11726
11727 // ============================================================================
11728 // This name is KNOWN by the ADLC and cannot be changed.
11729 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11730 // for this guy.
11731 instruct tlsLoadP(r15_RegP dst) %{
11732 match(Set dst (ThreadLocal));
11733 effect(DEF dst);
11734
11735 size(0);
11736 format %{ "# TLS is in R15" %}
11737 ins_encode( /*empty encoding*/ );
11738 ins_pipe(ialu_reg_reg);
11739 %}
11740
11741
11742 //----------PEEPHOLE RULES-----------------------------------------------------
11743 // These must follow all instruction definitions as they use the names
11744 // defined in the instructions definitions.
11745 //
11746 // peepmatch ( root_instr_name [preceding_instruction]* );
11747 //
11748 // peepconstraint %{
11749 // (instruction_number.operand_name relational_op instruction_number.operand_name
11750 // [, ...] );
11751 // // instruction numbers are zero-based using left to right order in peepmatch
11752 //
11753 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11754 // // provide an instruction_number.operand_name for each operand that appears
11755 // // in the replacement instruction's match rule
11756 //
11757 // ---------VM FLAGS---------------------------------------------------------
11758 //
11759 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11760 //
11761 // Each peephole rule is given an identifying number starting with zero and
11762 // increasing by one in the order seen by the parser. An individual peephole
11763 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11764 // on the command-line.
11765 //
11766 // ---------CURRENT LIMITATIONS----------------------------------------------
11767 //
11768 // Only match adjacent instructions in same basic block
11769 // Only equality constraints
11770 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11771 // Only one replacement instruction
11772 //
11773 // ---------EXAMPLE----------------------------------------------------------
11774 //
11775 // // pertinent parts of existing instructions in architecture description
11776 // instruct movI(rRegI dst, rRegI src)
11777 // %{
11778 // match(Set dst (CopyI src));
11779 // %}
11780 //
11781 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
11782 // %{
11783 // match(Set dst (AddI dst src));
11784 // effect(KILL cr);
11785 // %}
11786 //
11787 // // Change (inc mov) to lea
11788 // peephole %{
11789 // // increment preceeded by register-register move
11790 // peepmatch ( incI_rReg movI );
11791 // // require that the destination register of the increment
11792 // // match the destination register of the move
11793 // peepconstraint ( 0.dst == 1.dst );
11794 // // construct a replacement instruction that sets
11795 // // the destination to ( move's source register + one )
11796 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
11797 // %}
11798 //
11799
11800 // Implementation no longer uses movX instructions since
11801 // machine-independent system no longer uses CopyX nodes.
11802 //
11803 // peephole
11804 // %{
11805 // peepmatch (incI_rReg movI);
11806 // peepconstraint (0.dst == 1.dst);
11807 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11808 // %}
11809
11810 // peephole
11811 // %{
11812 // peepmatch (decI_rReg movI);
11813 // peepconstraint (0.dst == 1.dst);
11814 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11815 // %}
11816
11817 // peephole
11818 // %{
11819 // peepmatch (addI_rReg_imm movI);
11820 // peepconstraint (0.dst == 1.dst);
11821 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11822 // %}
11823
11824 // peephole
11825 // %{
11826 // peepmatch (incL_rReg movL);
11827 // peepconstraint (0.dst == 1.dst);
11828 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11829 // %}
11830
11831 // peephole
11832 // %{
11833 // peepmatch (decL_rReg movL);
11834 // peepconstraint (0.dst == 1.dst);
11835 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11836 // %}
11837
11838 // peephole
11839 // %{
11840 // peepmatch (addL_rReg_imm movL);
11841 // peepconstraint (0.dst == 1.dst);
11842 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11843 // %}
11844
11845 // peephole
11846 // %{
11847 // peepmatch (addP_rReg_imm movP);
11848 // peepconstraint (0.dst == 1.dst);
11849 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
11850 // %}
11851
11852 // // Change load of spilled value to only a spill
11853 // instruct storeI(memory mem, rRegI src)
11854 // %{
11855 // match(Set mem (StoreI mem src));
11856 // %}
11857 //
11858 // instruct loadI(rRegI dst, memory mem)
11859 // %{
11860 // match(Set dst (LoadI mem));
11861 // %}
11862 //
11863
11864 peephole
11865 %{
11866 peepmatch (loadI storeI);
11867 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11868 peepreplace (storeI(1.mem 1.mem 1.src));
11869 %}
11870
11871 peephole
11872 %{
11873 peepmatch (loadL storeL);
11874 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11875 peepreplace (storeL(1.mem 1.mem 1.src));
11876 %}
11877
11878 //----------SMARTSPILL RULES---------------------------------------------------
11879 // These must follow all instruction definitions as they use the names
11880 // defined in the instructions definitions.